diff options
1033 files changed, 29755 insertions, 15086 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index d6f3fa423c6..b9d6aa98a0b 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -287,9 +287,6 @@ stages: sandbox64_clang: TEST_PY_BD: "sandbox64" OVERRIDE: "-O clang-16" - sandbox_nolto: - TEST_PY_BD: "sandbox" - BUILD_ENV: "NO_LTO=1" sandbox_spl: TEST_PY_BD: "sandbox_spl" TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index fee165198ae..fbf99f0322a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -258,12 +258,6 @@ sandbox with clang test.py: OVERRIDE: "-O clang-16" <<: *buildman_and_testpy_dfn -sandbox without LTO test.py: - variables: - TEST_PY_BD: "sandbox" - BUILD_ENV: "NO_LTO=1" - <<: *buildman_and_testpy_dfn - sandbox64 test.py: variables: TEST_PY_BD: "sandbox64" @@ -275,12 +269,6 @@ sandbox64 with clang test.py: OVERRIDE: "-O clang-16" <<: *buildman_and_testpy_dfn -sandbox64 without LTO test.py: - variables: - TEST_PY_BD: "sandbox64" - BUILD_ENV: "NO_LTO=1" - <<: *buildman_and_testpy_dfn - sandbox_spl test.py: variables: TEST_PY_BD: "sandbox_spl" diff --git a/MAINTAINERS b/MAINTAINERS index 9f74c0aacaa..25f2bb80deb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -117,7 +117,7 @@ F: drivers/mmc/snps_dw_mmc.c APPLE M1 SOC SUPPORT M: Mark Kettenis <kettenis@openbsd.org> S: Maintained -F: arch/arm/include/asm/arch-m1/ +F: arch/arm/include/asm/arch-apple/ F: arch/arm/mach-apple/ F: configs/apple_m1_defconfig F: drivers/iommu/apple_dart.c @@ -979,7 +979,7 @@ EFI APP M: Simon Glass <sjg@chromium.org> M: Heinrich Schuchardt <xypron.glpk@gmx.de> S: Maintained -W: https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html +W: https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html F: board/efi/efi-x86_app F: configs/efi-x86_app* F: doc/develop/uefi/u-boot_on_efi.rst @@ -1528,7 +1528,6 @@ F: cmd/stackprot_test.c F: test/py/tests/test_stackprotector.py TARGET_BCMNS3 -M: Bharat Gooty <bharat.gooty@broadcom.com> M: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> S: Maintained F: board/broadcom/bcmns3/ @@ -1551,6 +1550,11 @@ M: Liviu Dudau <liviu.dudau@foss.arm.com> S: Maintained F: drivers/video/tda19988.c +TI LP5562 LED DRIVER +M: Rasmus Villemoes <rasmus.villemoes@prevas.dk> +S: Supported +F: drivers/led/led_lp5562.c + TI SYSTEM SECURITY M: Andrew F. Davis <afd@ti.com> S: Supported @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* @@ -750,6 +750,7 @@ endif ifeq ($(CONFIG_STACKPROTECTOR),y) KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong) +KBUILD_CFLAGS += $(call cc-option,-mstack-protector-guard=global) CFLAGS_EFI += $(call cc-option,-fno-stack-protector) else KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) @@ -851,7 +852,7 @@ HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makef libs-$(CONFIG_API) += api/ libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ libs-y += boot/ -libs-y += cmd/ +libs-$(CONFIG_CMDLINE) += cmd/ libs-y += common/ libs-$(CONFIG_OF_EMBED) += dts/ libs-y += env/ @@ -1153,7 +1154,6 @@ endif @# is enable to tell 'deprecated' that one of these symbols exists $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x)) $(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL)) - $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI)) @# Check that this build does not override OF_HAS_PRIOR_STAGE by @# disabling OF_BOARD. $(call cmd,ofcheck,$(KCONFIG_CONFIG)) @@ -1349,6 +1349,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ $(foreach f,$(BINMAN_INDIRS),-I $(f)) \ -a atf-bl31-path=${BL31} \ -a tee-os-path=${TEE} \ + -a ti-dm-path=${TI_DM} \ -a opensbi-path=${OPENSBI} \ -a default-dt=$(default_dt) \ -a scp-path=$(SCP) \ @@ -1191,11 +1191,10 @@ The following options need to be configured: Support for a lightweight UBI (fastmap) scanner and loader - CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, - CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, - CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, - CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE, - CFG_SYS_NAND_ECCBYTES + CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_SIZE, + CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, + CONFIG_SYS_NAND_BAD_BLOCK_POS, CFG_SYS_NAND_ECCPOS, + CFG_SYS_NAND_ECCSIZE, CFG_SYS_NAND_ECCBYTES Defines the size and behavior of the NAND that SPL uses to read U-Boot @@ -1545,16 +1544,26 @@ Low Level (hardware related) configuration options: globally (CONFIG_CMD_MEMORY). - CONFIG_SPL_BUILD - Set when the currently-running compilation is for an artifact - that will end up in the SPL (as opposed to the TPL or U-Boot - proper). Code that needs stage-specific behavior should check - this. + Set when the currently running compilation is for an artifact + that will end up in one of the 'xPL' builds, i.e. SPL, TPL or + VPL. Code that needs phase-specific behaviour can check this, + or (where possible) use spl_phase() instead. + + Note that CONFIG_SPL_BUILD *is* always defined when either + of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be + counter-intuitive and should perhaps be changed. - CONFIG_TPL_BUILD - Set when the currently-running compilation is for an artifact - that will end up in the TPL (as opposed to the SPL or U-Boot - proper). Code that needs stage-specific behavior should check - this. + Set when the currently running compilation is for an artifact + that will end up in the TPL build (as opposed to SPL, VPL or + U-Boot proper). Code that needs phase-specific behaviour can + check this, or (where possible) use spl_phase() instead. + +- CONFIG_VPL_BUILD + Set when the currently running compilation is for an artifact + that will end up in the VPL build (as opposed to the SPL, TPL + or U-Boot proper). Code that needs phase-specific behaviour can + check this, or (where possible) use spl_phase() instead. - CONFIG_ARCH_MAP_SYSMEM Generally U-Boot (and in particular the md command) uses @@ -2650,5 +2659,5 @@ Contributing The U-Boot projects depends on contributions from the user community. If you want to participate, please, have a look at the 'General' -section of https://u-boot.readthedocs.io/en/latest/develop/index.html +section of https://docs.u-boot.org/en/latest/develop/index.html where we describe coding standards and the patch submission process. diff --git a/api/api_storage.c b/api/api_storage.c index 997e8727a96..78becbe39fb 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -67,13 +67,6 @@ void dev_stor_init(void) specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA; specs[ENUM_SATA].name = "sata"; #endif -#if defined(CONFIG_SCSI) - specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE; - specs[ENUM_SCSI].enum_started = 0; - specs[ENUM_SCSI].enum_ended = 0; - specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI; - specs[ENUM_SCSI].name = "scsi"; -#endif #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV; specs[ENUM_USB].enum_started = 0; diff --git a/arch/Kconfig b/arch/Kconfig index 4f5b75129f3..2e0528d819c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -134,7 +134,7 @@ config SANDBOX select ARCH_SUPPORTS_LTO select BOARD_LATE_INIT select BZIP2 - select CMD_POWEROFF + select CMD_POWEROFF if CMDLINE select DM select DM_EVENT select DM_FUZZING_ENGINE @@ -152,10 +152,10 @@ config SANDBOX select PCI_ENDPOINT select SPI select SUPPORT_OF_CONTROL - select SYSRESET_CMD_POWEROFF + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF select SYS_CACHE_SHIFT_4 select IRQ - select SUPPORT_EXTENSION_SCAN + select SUPPORT_EXTENSION_SCAN if CMDLINE select SUPPORT_ACPI imply BITREVERSE select BLOBLIST @@ -210,6 +210,9 @@ config SANDBOX imply BINMAN imply CMD_MBR imply CMD_MMC + imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE + imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE + imply CMD_SYSBOOT if BOOTSTD_FULL config SH bool "SuperH architecture" @@ -248,7 +251,7 @@ config X86 imply DM_KEYBOARD imply DM_MMC imply DM_RTC - imply DM_SCSI + imply SCSI imply DM_SERIAL imply DM_SPI imply DM_SPI_FLASH diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c984..1fd7aacc380 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -568,6 +568,7 @@ config ARCH_AT91 select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL + imply SYS_THUMB_BUILD config ARCH_DAVINCI bool "TI DaVinci" @@ -1133,7 +1134,6 @@ config ARCH_SUNXI select DM_SPI_FLASH if SPI select DM_KEYBOARD select DM_MMC if MMC - select DM_SCSI if SCSI select DM_SERIAL select OF_BOARD_SETUP select OF_CONTROL @@ -1838,7 +1838,7 @@ config TARGET_SL28 select PCI select DM_RNG select DM_RTC - select DM_SCSI + select SCSI select DM_SERIAL select DM_SPI select GPIO_EXTRA_HEADER @@ -1945,7 +1945,7 @@ config ARCH_STM32MP select REGMAP select SYSCON select SYSRESET - select SYS_THUMB_BUILD + select SYS_THUMB_BUILD if !ARM64 imply SPL_SYSRESET imply CMD_DM imply CMD_POWEROFF @@ -2053,7 +2053,6 @@ config TARGET_POMELO select PCI select DM_PCI select SCSI - select DM_SCSI select DM_SERIAL imply CMD_PCI help diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 6d6166cb839..4f3cb63c56d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -71,6 +71,7 @@ void reset_cpu(void) * actually 0x20, this the associated <destination address>. Loading the PC * register with an address performs a jump to that address. */ +noinline __attribute__((target("arm"))) void mx28_fixup_vt(uint32_t start_addr) { /* ldr pc, [pc, #0x18] */ @@ -85,6 +86,9 @@ void mx28_fixup_vt(uint32_t start_addr) /* cppcheck-suppress nullPointer */ vt[i + 8] = start_addr + (4 * i); } + + /* Make sure ARM core points to low vectors */ + set_cr(get_cr() & ~CR_V); } #ifdef CONFIG_ARCH_MISC_INIT diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 5e7bdb78be1..249f8de8fbe 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/sections.h> +#include <asm/system.h> #include <linux/compiler.h> #include "mxs_init.h" @@ -93,7 +94,9 @@ static uint8_t mxs_get_bootmode_index(void) return i; } -static void mxs_spl_fixup_vectors(void) +static noinline +__attribute__((target("arm"))) +void mxs_spl_fixup_vectors(void) { /* * Copy our vector table to 0x0, since due to HAB, we cannot @@ -104,6 +107,9 @@ static void mxs_spl_fixup_vectors(void) /* cppcheck-suppress nullPointer */ memcpy(0x0, _start, 0x60); + + /* Make sure ARM core points to low vectors */ + set_cr(get_cr() & ~CR_V); } static void mxs_spl_console_init(void) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index fc4f63d8348..7724c9332c3 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -14,9 +14,6 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { -#ifndef CONFIG_CMDLINE - /DISCARD/ : { *(__u_boot_list_2_cmd_*) } -#endif #if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) /* * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1be08c5fdc2..e9e58c5478d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -835,6 +835,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ sun50i-h616-orangepi-zero2.dtb \ + sun50i-h618-orangepi-zero3.dtb \ sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ @@ -1074,6 +1075,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-phg.dtb \ + imx8mm-phyboard-polis-rdk.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ imx8mm-venice-gw72xx-0x.dtb \ @@ -1084,7 +1086,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-venice-gw7904.dtb \ imx8mm-venice-gw7905-0x.dtb \ imx8mm-verdin-wifi-dev.dtb \ - phycore-imx8mm.dtb \ imx8mn-bsh-smm-s2.dtb \ imx8mn-bsh-smm-s2pro.dtb \ imx8mn-ddr4-evk.dtb \ @@ -1104,6 +1105,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ + imx8mp-debix-model-a.dtb \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ @@ -1381,6 +1383,9 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcor-drc-compact.dtb \ stm32mp15xx-dhcor-testbench.dtb +dtb-$(CONFIG_STM32MP25X) += \ + stm32mp257f-ev1.dtb + dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ k3-am654-r5-base-board.dtb \ @@ -1397,7 +1402,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ k3-j7200-common-proc-board.dtb \ k3-j7200-r5-common-proc-board.dtb \ k3-j721e-sk.dtb \ - k3-j721e-r5-sk.dtb + k3-j721e-r5-sk.dtb \ + k3-j721e-beagleboneai64.dtb \ + k3-j721e-r5-beagleboneai64.dtb + dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\ k3-am68-sk-r5-base-board.dtb\ k3-j721s2-common-proc-board.dtb\ @@ -1509,6 +1517,8 @@ targets += $(dtb-y) # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 +DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format + PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) @: diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index f2d6b183ed9..c54a59e89c5 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -93,6 +93,12 @@ &gpio4 { bootph-some-ram; + + usbh_en { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; }; &gpio5 { diff --git a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi index 843b4583e53..3b5f14ecb04 100644 --- a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi +++ b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi @@ -1,11 +1,18 @@ #include "imx7s-u-boot.dtsi" /{ - aliases { - mmc0 = &usdhc3; - usb0 = &usbotg1; - display0 = &lcdif; - }; + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + usb0 = &usbotg1; + display0 = &lcdif; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &usbotg1 { @@ -45,6 +52,10 @@ }; }; +&wdog1 { + bootph-pre-ram; +}; + &iomuxc { pinctrl_backlight: backlight { fsl,pins = < diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi index 71bfd80aab8..eace17e052e 100644 --- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi +++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi @@ -18,57 +18,6 @@ dr_mode = "peripheral"; }; -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; -}; - -&pinctrl_usdhc1 { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; -}; - -&iomuxc { - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; -}; - &wdog1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 78f4224a9bf..75f1cd14bea 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -24,14 +24,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -39,12 +39,12 @@ }; }; - spi4 { + spi-4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; - gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; @@ -60,6 +60,17 @@ }; }; + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <200000>; + off-on-delay-us = <20000>; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -205,13 +216,8 @@ pinctrl-0 = <&pinctrl_tsc2046_pendown>; interrupt-parent = <&gpio2>; interrupts = <29 0>; - pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <0>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <0>; - ti,pressure-max = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <400>; + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; + touchscreen-max-pressure = <255>; wakeup-source; }; }; @@ -269,7 +275,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -478,10 +484,13 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; wakeup-source; keep-power-in-suspend; status = "okay"; @@ -736,6 +745,15 @@ >; }; + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 @@ -744,9 +762,28 @@ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; diff --git a/arch/arm/dts/imx7s-warp-u-boot.dtsi b/arch/arm/dts/imx7s-warp-u-boot.dtsi index 49b992dccca..4f44598c9a2 100644 --- a/arch/arm/dts/imx7s-warp-u-boot.dtsi +++ b/arch/arm/dts/imx7s-warp-u-boot.dtsi @@ -1,12 +1,12 @@ / { - aliases { - mmc0 = &usdhc3; - usb0 = &usbotg1; - }; + aliases { + mmc0 = &usdhc3; + usb0 = &usbotg1; + }; - chosen { - stdout-path = &uart1; - }; + chosen { + stdout-path = &uart1; + }; }; &aips3 { diff --git a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi index 516e52e1f5d..516e52e1f5d 100644 --- a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts new file mode 100644 index 00000000000..03e7679217b --- /dev/null +++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mm-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; + compatible = "phytec,imx8mm-phyboard-polis-rdk", + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart3; + }; + + bt_osc_32k: bt-lp-clock { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "bt_osc_32k"; + #clock-cells = <0>; + }; + + can_osc_40m: can-clock { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "can_osc_40m"; + #clock-cells = <0>; + }; + + fan { + compatible = "gpio-fan"; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 13000 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan>; + #cooling-cells = <2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + }; + + led-1 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_CPU; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <60>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CAN_EN"; + startup-delay-us = <20>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; + regulator-name = "usb_otg1_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; + + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3"; + }; +}; + +/* SPI - CAN MCP251XFD */ +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp251xfd"; + clocks = <&can_osc_40m>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + spi-max-frequency = <20000000>; + xceiver-supply = <®_can_en>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", + "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "BT_REG_ON", "WL_REG_ON", + "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", + "X_SD2_CD_B", "", "", "", + "", "", "", "SD2_RESET_B"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "FAN", "miniPCIe_nPERST", "", "", + "COEX1", "COEX2"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "ECSPI1_SS0"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + +/* PCIe */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <250000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + +&rv3028 { + trickle-resistor-ohms = <3000>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* UART - RS232/RS485 */ +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +/* UART - Sterling-LWB Bluetooth */ +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&bt_osc_32k>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + vddio-supply = <®_vcc_3v3>; + }; +}; + +/* UART - console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + over-current-active-low; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +/* SDIO - Sterling-LWB Wifi */ +&usdhc1 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_nvcc_sd2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 + >; + }; + + pinctrl_can_en: can-engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 + >; + }; + + pinctrl_can_int: can-intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 + >; + }; + + pinctrl_fan: fan0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_leds: leds1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 + >; + }; + + pinctrl_uart2_bt: uart2btgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 + MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 + MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-phycore-som.dtsi b/arch/arm/dts/imx8mm-phycore-som.dtsi new file mode 100644 index 00000000000..92616bc4f71 --- /dev/null +++ b/arch/arm/dts/imx8mm-phycore-som.dtsi @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +#include "imx8mm.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "PHYTEC phyCORE-i.MX8MM"; + compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_vdd_3v3_s: regulator-vdd-3v3-s { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_S"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +/* Ethernet */ +&fec1 { + fsl,magic-packet; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; + }; +}; + +/* SPI Flash */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + som_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "", "", "nENABLE_FLATLINK"; +}; + +/* I2C1 */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default","gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@8 { + compatible = "nxp,pf8121a"; + reg = <0x08>; + + regulators { + reg_nvcc_sd1: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "NVCC_SD1 (LDO1)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_nvcc_sd2: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO2)"; + vselect-en; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vcc_enet: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VCC_ENET_2V5 (LDO3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdda_1v8: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VDDA_1V8 (LDO4)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1500000>; + regulator-suspend-max-microvolt = <1500000>; + }; + }; + + reg_soc_vdda_phy: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <400000>; + regulator-suspend-max-microvolt = <400000>; + }; + }; + + reg_vdd_gpu_dram: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "VDD_GPU_DRAM (BUCK2)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1000000>; + regulator-suspend-min-microvolt = <1000000>; + }; + }; + + reg_vdd_gpu: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_VPU (BUCK3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_mipi: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <900000>; + regulator-name = "VDD_MIPI_0P9 (BUCK4)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_arm: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_ARM (BUCK5)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_1v8: buck6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8 (BUCK6)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1800000>; + regulator-suspend-min-microvolt = <1800000>; + }; + }; + + reg_nvcc_dram: buck7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; + }; + + reg_vsnvs: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; + }; + }; + }; + + sn65dsi83: bridge@2d { + compatible = "ti,sn65dsi83"; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sn65dsi83>; + reg = <0x2d>; + status = "disabled"; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x51>; + vcc-supply = <®_vdd_3v3_s>; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x52>; + }; +}; + +/* EMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + keep-power-in-suspend; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_sn65dsi83: sn65dsi83grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi index 92e44d4ba96..31f9d47bced 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi @@ -39,6 +39,13 @@ gpios = <9 GPIO_ACTIVE_HIGH>; line-name = "dio1"; }; + + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; }; &gpio4 { diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi index 244ef8d6cc6..7b2130dbdb2 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi @@ -104,8 +104,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -364,6 +371,7 @@ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index afb90f59c83..738024baaa5 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -276,6 +277,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; }; usbphynop2: usbphynop2 { @@ -285,6 +287,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg2>; }; soc: soc@0 { @@ -396,6 +399,7 @@ "pll8k", "pll11k", "clkext3"; dmas = <&sdma2 24 25 0x80000000>; dma-names = "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -493,6 +497,8 @@ compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -547,8 +553,8 @@ reg = <0x30330000 0x10000>; }; - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; + gpr: syscon@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -560,22 +566,40 @@ #address-cells = <1>; #size-cells = <1>; - imx8mm_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -674,13 +698,11 @@ pgc_otg1: power-domain@2 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG1>; - power-domains = <&pgc_hsiomix>; }; pgc_otg2: power-domain@3 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG2>; - power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@4 { @@ -1098,6 +1120,61 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + csi: csi@32e20000 { compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; reg = <0x32e20000 0x1000>; @@ -1145,10 +1222,9 @@ compatible = "fsl,imx8mm-mipi-csi2"; reg = <0x32e30000 0x1000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, - <&clk IMX8MM_CLK_CSI1_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, - <&clk IMX8MM_SYS_PLL2_1000M>; + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>; + clock-frequency = <333000000>; clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, <&clk IMX8MM_CLK_CSI1_ROOT>, @@ -1177,7 +1253,7 @@ }; usbotg1: usb@32e40000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; @@ -1186,18 +1262,19 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e40200 0x200>; }; usbotg2: usb@32e50000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e50000 0x200>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; @@ -1206,12 +1283,13 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; - power-domains = <&pgc_otg2>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc2: usbmisc@32e50200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e50200 0x200>; }; @@ -1238,16 +1316,15 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; }; - gpmi: nand-controller@33002000{ + gpmi: nand-controller@33002000 { compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -1268,8 +1345,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; @@ -1282,12 +1359,40 @@ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie0_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x400000>, + <0x18000000 0x8000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "apps", "turnoff"; phys = <&pcie_phy>; phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; status = "disabled"; }; diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi index e0caf3179ea..2bbc4a49418 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi @@ -39,11 +39,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pinctrl_i2c1 { - bootph-pre-ram; + bootph-all; }; &pinctrl_pmic { @@ -83,5 +83,5 @@ }; &eeprom_som { - bootph-pre-ram; + bootph-all; }; diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index cb2836bfbd9..1bb1d0c1bae 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -295,6 +296,7 @@ sai2: sai@30020000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -309,6 +311,7 @@ sai3: sai@30030000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -323,6 +326,7 @@ sai5: sai@30050000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -339,6 +343,7 @@ sai6: sai@30060000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -366,6 +371,7 @@ "pll8k", "pll11k", "clkext3"; dmas = <&sdma2 24 25 0x80000000>; dma-names = "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -396,6 +402,7 @@ sai7: sai@300b0000 { compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -497,6 +504,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -551,7 +560,7 @@ reg = <0x30330000 0x10000>; }; - gpr: iomuxc-gpr@30340000 { + gpr: syscon@30340000 { compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -563,23 +572,40 @@ #address-cells = <1>; #size-cells = <1>; - imx8mn_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -662,7 +688,6 @@ pgc_otg1: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8MN_POWER_DOMAIN_OTG1>; - power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@2 { @@ -1038,6 +1063,72 @@ #size-cells = <1>; ranges; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + + isi: isi@32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x32e20000 0x8000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&disp_blk_ctrl>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in: endpoint { + remote-endpoint = <&mipi_csi_out>; + }; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1063,11 +1154,60 @@ "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", "dsi-ref", "csi-aclk", "csi-pclk"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_VIDEO_PLL1_OUT>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <266000000>, + <24000000>, + <594000000>, + <500000000>, + <200000000>; #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_out: endpoint { + remote-endpoint = <&isi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; @@ -1076,12 +1216,13 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e40200 0x200>; }; @@ -1094,7 +1235,6 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; @@ -1103,7 +1243,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -1175,5 +1315,6 @@ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; }; }; diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi new file mode 100644 index 00000000000..33bd89a8434 --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2021 NXP + * Copyright 2023 Gilles Talis <gilles.talis@gmail.com> + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&crypto { + bootph-pre-ram; +}; + +ðphy0 { + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + reset-delay-us = <15000>; + reset-post-delay-us = <100000>; +}; + +&fec { + phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&pinctrl_i2c1 { + bootph-pre-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; +}; + +&pinctrl_uart2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&pmic { + bootph-pre-ram; + + regulators { + bootph-pre-ram; + }; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&uart2 { + bootph-pre-ram; +}; + +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&usdhc3 { + bootph-pre-ram; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts new file mode 100644 index 00000000000..58dae612b4b --- /dev/null +++ b/arch/arm/dts/imx8mp-debix-model-a.dts @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2022 Ideas on Board Oy + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/usb/pd.h> + +#include "imx8mp.dtsi" + +/ { + model = "Polyhex Debix Model A i.MX8MPlus board"; + compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-connection-type = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { /* RTL8211E */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <200000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* SD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f + MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; + diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 9ed62f1bb02..51c84383673 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -13,6 +13,22 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; @@ -66,7 +82,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &i2c2 { @@ -121,17 +137,3 @@ &wdog1 { bootph-pre-ram; }; - -ðphy0 { - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-delay-us = <15000>; - reset-post-delay-us = <100000>; -}; - -&fec { - phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - phy-reset-duration = <15>; - phy-reset-post-delay = <100>; -}; - - diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi index 70433c07329..4d0e9a1e67c 100644 --- a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi @@ -10,6 +10,15 @@ reset-post-delay-us = <300000>; }; +&gpio1 { + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; +}; + &gpio4 { dio_1 { gpio-hog; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi index 1c05398c862..88c3c006fa2 100644 --- a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi @@ -95,8 +95,14 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -327,6 +333,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index 428c60462e3..c9a610ba483 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -202,6 +202,60 @@ clock-output-names = "clk_ext4"; }; + funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -304,6 +358,153 @@ nvmem-cells = <&imx8mp_uid>; nvmem-cell-names = "soc_unique_id"; + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28440000 0x1000>; + cpu = <&A53_0>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28540000 0x1000>; + cpu = <&A53_1>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28640000 0x1000>; + cpu = <&A53_2>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28740000 0x1000>; + cpu = <&A53_3>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x28c03000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + + hugo_funnel_in_port1: endpoint { + /* M7 input */ + }; + }; + + port@2 { + reg = <2>; + + hugo_funnel_in_port2: endpoint { + /* DSP input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c04000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c06000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -497,7 +698,7 @@ snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; + regmap = <&snvs>; offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -534,26 +735,16 @@ <&clk IMX8MP_CLK_A53_CORE>, <&clk IMX8MP_CLK_NOC>, <&clk IMX8MP_CLK_NOC_IO>, - <&clk IMX8MP_CLK_GIC>, - <&clk IMX8MP_CLK_AUDIO_AHB>, - <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, - <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; + <&clk IMX8MP_CLK_GIC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_ARM_PLL_OUT>, <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL2_500M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; + <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <0>, <0>, <1000000000>, <800000000>, - <500000000>, - <400000000>, - <800000000>, - <393216000>, - <361267200>; + <500000000>; }; src: reset-controller@30390000 { @@ -595,6 +786,19 @@ reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; }; + pgc_audio: power-domain@5 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI>; + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, + <600000000>; + }; + pgc_gpu2d: power-domain@6 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_GPU2D>; @@ -653,7 +857,7 @@ pgc_vpumix: power-domain@19 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; - clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + clocks = <&clk IMX8MP_CLK_VPU_ROOT>; }; pgc_vpu_g1: power-domain@20 { @@ -1147,6 +1351,198 @@ }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c10000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c20000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c30000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c50000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c60000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c80000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + easrc: easrc@30c90000 { + compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; + reg = <0x30c90000 0x10000>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + firmware-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-format = <2>; + status = "disabled"; + }; + + micfil: audio-controller@30ca0000 { + compatible = "fsl,imx8mp-micfil"; + reg = <0x30ca0000 0x10000>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e00000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e10000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + audio_blk_ctrl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctrl"; + reg = <0x30e20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_SAI1>, + <&clk IMX8MP_CLK_SAI2>, + <&clk IMX8MP_CLK_SAI3>, + <&clk IMX8MP_CLK_SAI5>, + <&clk IMX8MP_CLK_SAI6>, + <&clk IMX8MP_CLK_SAI7>; + clock-names = "ahb", + "sai1", "sai2", "sai3", + "sai5", "sai6", "sai7"; + power-domains = <&pgc_audio>; + }; + }; + noc: interconnect@32700000 { compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; reg = <0x32700000 0x100000>; @@ -1174,6 +1570,118 @@ #size-cells = <1>; ranges; + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi"; + reg = <0x32e00000 0x4000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + isi_in_0: endpoint { + remote-endpoint = <&mipi_csi_0_out>; + }; + }; + + port@1 { + reg = <1>; + + isi_in_1: endpoint { + remote-endpoint = <&mipi_csi_1_out>; + }; + }; + }; + }; + + dewarp: dwe@32e30000 { + compatible = "nxp,imx8mp-dw100"; + reg = <0x32e30000 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "ahb"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e40000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_0_out: endpoint { + remote-endpoint = <&isi_in_0>; + }; + }; + }; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e50000 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <266000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_1_out: endpoint { + remote-endpoint = <&isi_in_1>; + }; + }; + }; + }; + mipi_dsi: dsi@32e60000 { compatible = "fsl,imx8mp-mipi-dsim"; reg = <0x32e60000 0x400>; @@ -1382,8 +1890,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ - <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index a9dffa5a71e..4ecb53ed8be 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -131,10 +131,6 @@ phy-reset-post-delay = <100>; }; -&eqos { - compatible = "fsl,imx-eqos"; -}; - ðphy1 { reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; reset-assert-us = <15000>; diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index 284b90c94da..e5c64c86d1d 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -81,7 +81,8 @@ }; dmss: bus@48000000 { - compatible = "simple-mfd"; + bootph-all; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; dma-ranges; @@ -90,6 +91,7 @@ ti,sci-dev-id = <25>; secure_proxy_main: mailbox@4d000000 { + bootph-all; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; @@ -165,6 +167,7 @@ }; dmsc: system-controller@44043000 { + bootph-all; compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; @@ -174,16 +177,19 @@ reg = <0x00 0x44043000 0x00 0xfe0>; k3_pds: power-controller { + bootph-all; compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { + bootph-all; compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { + bootph-all; compatible = "ti,sci-reset"; #reset-cells = <2>; }; @@ -202,6 +208,7 @@ }; secure_proxy_sa3: mailbox@43600000 { + bootph-pre-ram; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; @@ -217,6 +224,7 @@ }; main_pmx0: pinctrl@f4000 { + bootph-all; compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; #pinctrl-cells = <1>; @@ -225,12 +233,14 @@ }; main_esm: esm@420000 { + bootph-pre-ram; compatible = "ti,j721e-esm"; reg = <0x00 0x420000 0x00 0x1000>; ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; }; main_timer0: timer@2400000 { + bootph-all; compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi index 80a3e1db26a..0e0b234581c 100644 --- a/arch/arm/dts/k3-am62-mcu.dtsi +++ b/arch/arm/dts/k3-am62-mcu.dtsi @@ -7,6 +7,7 @@ &cbass_mcu { mcu_pmx0: pinctrl@4084000 { + bootph-all; compatible = "pinctrl-single"; reg = <0x00 0x04084000 0x00 0x88>; #pinctrl-cells = <1>; @@ -15,6 +16,7 @@ }; mcu_esm: esm@4100000 { + bootph-pre-ram; compatible = "ti,j721e-esm"; reg = <0x00 0x4100000 0x00 0x1000>; ti,esm-pins = <0>, <1>, <2>, <85>; diff --git a/arch/arm/dts/k3-am62-verdin-wifi.dtsi b/arch/arm/dts/k3-am62-verdin-wifi.dtsi index 90ddc71bcd3..a6808b10c7b 100644 --- a/arch/arm/dts/k3-am62-verdin-wifi.dtsi +++ b/arch/arm/dts/k3-am62-verdin-wifi.dtsi @@ -35,5 +35,11 @@ &main_uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; }; diff --git a/arch/arm/dts/k3-am62-verdin.dtsi b/arch/arm/dts/k3-am62-verdin.dtsi index 40992e7e4c3..5db52f23725 100644 --- a/arch/arm/dts/k3-am62-verdin.dtsi +++ b/arch/arm/dts/k3-am62-verdin.dtsi @@ -1061,6 +1061,7 @@ vddc-supply = <®_1v2_dsi>; vddmipi-supply = <®_1v2_dsi>; vddio-supply = <®_1v8_dsi>; + status = "disabled"; dsi_bridge_ports: ports { #address-cells = <1>; diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi index eae05288718..fef76f52a52 100644 --- a/arch/arm/dts/k3-am62-wakeup.dtsi +++ b/arch/arm/dts/k3-am62-wakeup.dtsi @@ -7,6 +7,7 @@ &cbass_wakeup { wkup_conf: syscon@43000000 { + bootph-all; compatible = "syscon", "simple-mfd"; reg = <0x00 0x43000000 0x00 0x20000>; #address-cells = <1>; @@ -14,6 +15,7 @@ ranges = <0x0 0x00 0x43000000 0x20000>; chipid: chipid@14 { + bootph-all; compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi index 11f14eef2d4..f1e15206e1c 100644 --- a/arch/arm/dts/k3-am62.dtsi +++ b/arch/arm/dts/k3-am62.dtsi @@ -47,6 +47,7 @@ }; cbass_main: bus@f0000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -86,6 +87,7 @@ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; cbass_mcu: bus@4000000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -93,6 +95,7 @@ }; cbass_wakeup: bus@b00000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index d6c6baa5518..a723caa5805 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -6,151 +6,49 @@ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation */ -#include "k3-am625-sk-binman.dtsi" +#include "k3-binman.dtsi" / { chosen { tick-timer = &main_timer0; }; - memory@80000000 { - bootph-all; - }; - /* Keep the LEDs on by default to indicate life */ leds { - bootph-all; led-0 { default-state = "on"; - bootph-all; }; led-1 { default-state = "on"; - bootph-all; }; led-2 { default-state = "on"; - bootph-all; }; led-3 { default-state = "on"; - bootph-all; }; led-4 { default-state = "on"; - bootph-all; }; }; }; -&cbass_main { - bootph-all; -}; - &main_timer0 { clock-frequency = <25000000>; - bootph-all; -}; - -&dmss { - bootph-all; -}; - -&secure_proxy_main { - bootph-all; -}; - -&dmsc { - bootph-all; -}; - -&k3_pds { - bootph-all; -}; - -&k3_clks { - bootph-all; -}; - -&k3_reset { - bootph-all; }; &dmsc { - bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; bootph-all; }; }; -&wkup_conf { - bootph-all; -}; - -&chipid { - bootph-all; -}; - -&main_pmx0 { - bootph-all; -}; - -&main_uart0 { - bootph-all; -}; - -&console_pins_default { - bootph-all; -}; - -&cbass_mcu { - bootph-all; -}; - -&cbass_wakeup { - bootph-all; -}; - -&mcu_pmx0 { - bootph-all; -}; - -&main_i2c0 { - bootph-all; -}; - -&local_i2c_pins_default { - bootph-all; -}; - -&gpio0_pins_default { - bootph-all; -}; - -&main_gpio0 { - bootph-all; -}; - -&main_gpio1 { - bootph-all; -}; - -&sdhci0 { - /* EMMC */ - bootph-all; -}; - -&emmc_pins_default { - bootph-all; -}; - &sd_pins_default { - bootph-all; /* Force to use SDCD card detect pin */ pinctrl-single,pins = < AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -163,33 +61,155 @@ >; }; -&tps65219 { - bootph-all; -}; - -&sdhci1 { - bootph-all; -}; - -#ifdef CONFIG_TARGET_AM625_A53_EVM +#ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb" +#define UBOOT_NODTB "u-boot-nodtb.bin" #define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb" -&spl_am625_sk_dtb { - filename = SPL_AM625_BEAGLEPLAY_DTB; -}; - -&am625_sk_dtb { - filename = AM625_BEAGLEPLAY_DTB; -}; +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; -&spl_am625_sk_dtb_unsigned { - filename = SPL_AM625_BEAGLEPLAY_DTB; -}; + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = <CONFIG_K3_ATF_LOAD_ADDR>; + entry = <CONFIG_K3_ATF_LOAD_ADDR>; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SPL_TEXT_BASE>; + entry = <CONFIG_SPL_TEXT_BASE>; + blob { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + + fdt-0 { + description = "k3-am625-beagleplay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + spl_am625_bp_dtb_unsigned: blob { + filename = SPL_AM625_BEAGLEPLAY_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am625-beagleplay"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; -&am625_sk_dtb_unsigned { - filename = AM625_BEAGLEPLAY_DTB; + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM625 board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am625-beagleplay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + am625_bp_dtb_unsigned: blob { + filename = AM625_BEAGLEPLAY_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am625-beagleplay"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; }; - #endif diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts index 7cfdf562b53..9a6bd0a3c94 100644 --- a/arch/arm/dts/k3-am625-beagleplay.dts +++ b/arch/arm/dts/k3-am625-beagleplay.dts @@ -46,6 +46,7 @@ }; memory@80000000 { + bootph-pre-ram; device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; @@ -58,7 +59,7 @@ ramoops: ramoops@9ca00000 { compatible = "ramoops"; - reg = <0x00 0x9c700000 0x00 0x00100000>; + reg = <0x00 0x9ca00000 0x00 0x00100000>; record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x00>; @@ -83,6 +84,7 @@ }; vsys_5v0: regulator-1 { + bootph-all; compatible = "regulator-fixed"; regulator-name = "vsys_5v0"; regulator-min-microvolt = <5000000>; @@ -93,6 +95,7 @@ vdd_3v3: regulator-2 { /* output of TLV62595DMQR-U12 */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; regulator-min-microvolt = <3300000>; @@ -118,6 +121,7 @@ vdd_3v3_sd: regulator-4 { /* output of TPS22918DBVR-U21 */ + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&vdd_3v3_sd_pins_default>; @@ -132,6 +136,7 @@ }; vdd_sd_dv: regulator-5 { + bootph-all; compatible = "regulator-gpio"; regulator-name = "sd_hs200_switch"; pinctrl-names = "default"; @@ -146,9 +151,11 @@ }; leds { + bootph-all; compatible = "gpio-leds"; led-0 { + bootph-all; gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; function = LED_FUNCTION_HEARTBEAT; @@ -156,6 +163,7 @@ }; led-1 { + bootph-all; gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; function = LED_FUNCTION_DISK_ACTIVITY; @@ -163,16 +171,19 @@ }; led-2 { + bootph-all; gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; function = LED_FUNCTION_CPU; }; led-3 { + bootph-all; gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; function = LED_FUNCTION_LAN; }; led-4 { + bootph-all; gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>; function = LED_FUNCTION_WLAN; }; @@ -245,6 +256,7 @@ &main_pmx0 { gpio0_pins_default: gpio0-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ @@ -264,6 +276,7 @@ }; vdd_sd_dv_pins_default: vdd-sd-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; @@ -283,6 +296,7 @@ }; local_i2c_pins_default: local-i2c-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ @@ -321,6 +335,7 @@ }; emmc_pins_default: emmc-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ @@ -336,12 +351,14 @@ }; vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ >; }; sd_pins_default: sd-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -418,6 +435,7 @@ }; mikrobus_gpio_pins_default: mikrobus-gpio-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ @@ -426,6 +444,7 @@ }; console_pins_default: console-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ @@ -597,6 +616,7 @@ }; &main_gpio0 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&gpio0_pins_default>; gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */ @@ -616,6 +636,7 @@ }; &main_gpio1 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&mikrobus_gpio_pins_default>; gpio-line-names = "", "", "", "", "", /* 0-4 */ @@ -633,6 +654,7 @@ }; &main_i2c0 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&local_i2c_pins_default>; clock-frequency = <400000>; @@ -651,6 +673,7 @@ }; tps65219: pmic@30 { + bootph-all; compatible = "ti,tps65219"; reg = <0x30>; buck1-supply = <&vsys_5v0>; @@ -801,6 +824,7 @@ }; &sdhci0 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; ti,driver-strength-ohm = <50>; @@ -810,6 +834,7 @@ &sdhci1 { /* SD/MMC */ + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&sd_pins_default>; @@ -850,6 +875,7 @@ }; &main_uart0 { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&console_pins_default>; status = "okay"; @@ -870,6 +896,12 @@ pinctrl-names = "default"; pinctrl-0 = <&wifi_debug_uart_pins_default>; status = "okay"; + + mcu { + compatible = "ti,cc1352p7"; + reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_LOW>; + vdds-supply = <&vdd_3v3>; + }; }; &dss { diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index 9c9d0570592..9db58f093c8 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -54,12 +54,7 @@ ti,secure-host; }; -&mcu_esm { - bootph-pre-ram; -}; - &secure_proxy_sa3 { - bootph-pre-ram; /* We require this for boot handshake */ status = "okay"; }; @@ -73,10 +68,6 @@ }; }; -&main_esm { - bootph-pre-ram; -}; - &main_pktdma { ti,sci = <&dm_tifs>; }; @@ -84,3 +75,42 @@ &main_bcdma { ti,sci = <&dm_tifs>; }; + +&binman { + tiboot3-am62x-gp-evm.bin { + filename = "tiboot3-am62x-gp-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, + <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; + combined; + dm-data; + content-sbl = <&u_boot_spl_unsigned>; + load = <0x43c00000>; + content-sysfw = <&ti_fs_gp>; + load-sysfw = <0x40000>; + content-sysfw-data = <&combined_tifs_cfg_gp>; + load-sysfw-data = <0x67000>; + content-dm-data = <&combined_dm_cfg_gp>; + load-dm-data = <0x43c3a800>; + sw-rev = <1>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + ti_fs_gp: ti-fs-gp.bin { + filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + combined_dm_cfg_gp: combined-dm-cfg-gp.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + + }; +}; diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index bf219226b97..6b9f40e5558 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -55,20 +55,11 @@ ti,secure-host; }; -&mcu_esm { - bootph-pre-ram; -}; - &secure_proxy_sa3 { - bootph-pre-ram; /* We require this for boot handshake */ status = "okay"; }; -&main_esm { - bootph-pre-ram; -}; - &cbass_main { sysctrler: sysctrler { compatible = "ti,am654-system-controller"; @@ -78,22 +69,14 @@ }; }; -&wkup_uart0_pins_default { - bootph-pre-ram; -}; - -&main_uart1_pins_default { - bootph-pre-ram; -}; - /* WKUP UART0 is used for DM firmware logs */ &wkup_uart0 { - bootph-pre-ram; + status = "okay"; }; /* Main UART1 is used for TIFS firmware logs */ &main_uart1 { - bootph-pre-ram; + status = "okay"; }; &ospi0 { diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 41277bf4bfd..5b058bd03a0 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -141,10 +141,7 @@ #ifdef CONFIG_TARGET_AM625_A53_EVM -#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb" - -#define UBOOT_NODTB "u-boot-nodtb.bin" #define AM625_SK_DTB "u-boot.dtb" &binman { @@ -155,81 +152,20 @@ }; }; ti-spl { - filename = "tispl.bin"; - pad-byte = <0xff>; + insert-template = <&ti_spl_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - ti-secure { - content = <&atf>; - keyfile = "custMpk.pem"; - }; - atf: atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - ti-secure { - content = <&tee>; - keyfile = "custMpk.pem"; - }; - tee: tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; ti-secure { content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - ti-secure { - content = <&u_boot_spl_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_spl_nodtb: blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-am625-sk"; type = "flat_dt"; @@ -263,29 +199,12 @@ &binman { u-boot { - filename = "u-boot.img"; - pad-byte = <0xff>; + insert-template = <&u_boot_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM625 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - ti-secure { - content = <&u_boot_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_nodtb: u-boot-nodtb { - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM625 Board"; }; fdt-0 { @@ -323,67 +242,17 @@ &binman { ti-spl_unsigned { - filename = "tispl.bin_unsigned"; - pad-byte = <0xff>; + insert-template = <&ti_spl_unsigned_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - atf-bl31 { - filename = "bl31.bin"; - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - tee-os { - filename = "tee-raw.bin"; - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - blob { - filename = "spl/u-boot-spl-nodtb.bin"; - }; - }; - fdt-0 { description = "k3-am625-sk"; type = "flat_dt"; @@ -411,26 +280,12 @@ &binman { u-boot_unsigned { - filename = "u-boot.img_unsigned"; - pad-byte = <0xff>; + insert-template = <&u_boot_unsigned_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM625 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - blob { - filename = UBOOT_NODTB; - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM625 Board"; }; fdt-0 { diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index 7ae5e01f7c7..fa778b0ff4c 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -8,122 +8,12 @@ / { chosen { - stdout-path = "serial2:115200n8"; tick-timer = &main_timer0; }; - - aliases { - mmc1 = &sdhci1; - }; - - memory@80000000 { - bootph-all; - }; -}; - -&main_conf { - bootph-all; -}; - -&cbass_main { - bootph-all; }; &main_timer0 { clock-frequency = <25000000>; - bootph-all; -}; - -&dmss { - bootph-all; -}; - -&secure_proxy_main { - bootph-all; -}; - -&dmsc { - bootph-all; -}; - -&k3_pds { - bootph-all; -}; - -&k3_clks { - bootph-all; -}; - -&k3_reset { - bootph-all; -}; - -&wkup_conf { - bootph-all; -}; - -&chipid { - bootph-all; -}; - -&main_pmx0 { - bootph-all; -}; - -&main_uart0 { - bootph-all; -}; - -&main_uart0_pins_default { - bootph-all; -}; - -&cbass_mcu { - bootph-all; -}; - -&cbass_wakeup { - bootph-all; -}; - -&mcu_pmx0 { - bootph-all; -}; - -&sdhci1 { - bootph-all; -}; - -&main_mmc1_pins_default { - bootph-all; -}; - -&fss { - bootph-all; -}; - -&ospi0_pins_default { - bootph-all; -}; - -&ospi0 { - bootph-all; - - flash@0 { - bootph-all; - - partitions { - bootph-all; - - partition@3fc0000 { - bootph-all; - }; - }; - }; -}; - -&inta_main_dmss { - bootph-all; }; &main_bcdma { @@ -153,41 +43,6 @@ bootph-all; }; -&cpsw3g_mdio { - bootph-all; -}; - -&cpsw3g_phy0 { - bootph-all; -}; - -&cpsw3g_phy1 { - bootph-all; -}; - -&main_rgmii1_pins_default { - bootph-all; -}; - -&main_rgmii2_pins_default { - bootph-all; -}; - -&phy_gmii_sel { - bootph-all; -}; - -&cpsw3g { - bootph-all; - ethernet-ports { - bootph-all; - }; -}; - -&cpsw_port1 { - bootph-all; -}; - &cpsw_port2 { status = "disabled"; }; diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts index 7c98c1b855d..b18092497c9 100644 --- a/arch/arm/dts/k3-am625-sk.dts +++ b/arch/arm/dts/k3-am625-sk.dts @@ -31,6 +31,7 @@ vmain_pd: regulator-0 { /* TPS65988 PD CONTROLLER OUTPUT */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vmain_pd"; regulator-min-microvolt = <5000000>; @@ -41,6 +42,7 @@ vcc_5v0: regulator-1 { /* Output of LM34936 */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vcc_5v0"; regulator-min-microvolt = <5000000>; @@ -52,6 +54,7 @@ vcc_3v3_sys: regulator-2 { /* output of LM61460-Q1 */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vcc_3v3_sys"; regulator-min-microvolt = <3300000>; @@ -63,6 +66,7 @@ vdd_mmc1: regulator-3 { /* TPS22918DBVR */ + bootph-all; compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; regulator-min-microvolt = <3300000>; @@ -75,6 +79,7 @@ vdd_sd_dv: regulator-4 { /* Output of TLV71033 */ + bootph-all; compatible = "regulator-gpio"; regulator-name = "tlv71033"; pinctrl-names = "default"; @@ -102,6 +107,7 @@ &main_pmx0 { main_rgmii2_pins_default: main-rgmii2-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ @@ -119,6 +125,7 @@ }; ospi0_pins_default: ospi0-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ @@ -135,20 +142,32 @@ }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ >; }; main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; }; }; +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + &main_i2c1 { + bootph-all; exp1: gpio@22 { + bootph-all; compatible = "ti,tca6424"; reg = <0x22>; gpio-controller; @@ -207,12 +226,18 @@ }; }; +&fss { + bootph-all; +}; + &ospi0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; flash@0 { + bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -225,6 +250,7 @@ cdns,read-delay = <4>; partitions { + bootph-all; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -260,6 +286,7 @@ }; partition@3fc0000 { + bootph-pre-ram; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 0cae9c57773..305d199678b 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -69,16 +69,7 @@ ti,secure-host; }; -&main_esm { - bootph-pre-ram; -}; - -&mcu_esm { - bootph-pre-ram; -}; - &secure_proxy_sa3 { - bootph-pre-ram; /* We require this for boot handshake */ status = "okay"; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 089b2a5f5cd..4e3704809a6 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -5,80 +5,6 @@ #include "k3-binman.dtsi" -&custmpk_pem { - filename = "../../ti/keys/custMpk.pem"; -}; - -&dkey_pem { - filename = "../../ti/keys/ti-degenerate-key.pem"; -}; - -#ifndef CONFIG_ARM64 - -&bcfg_yaml { - schema = "../../ti/common/schema.yaml"; -}; - -&pcfg_yaml { - schema = "../../ti/common/schema.yaml"; -}; - -&rcfg_yaml { - schema = "../../ti/common/schema.yaml"; -}; - -&scfg_yaml { - schema = "../../ti/common/schema.yaml"; -}; - -/* combined-tifs-cfg */ - -&bcfg_yaml_tifs { - schema = "../../ti/common/schema.yaml"; -}; - -&pcfg_yaml_tifs { - schema = "../../ti/common/schema.yaml"; -}; - -&rcfg_yaml_tifs { - schema = "../../ti/common/schema.yaml"; -}; - -&scfg_yaml_tifs { - schema = "../../ti/common/schema.yaml"; -}; - -/* combined-dm-cfg */ - -&pcfg_yaml_dm { - schema = "../../ti/common/schema.yaml"; -}; - -&rcfg_yaml_dm { - schema = "../../ti/common/schema.yaml"; -}; - -/* combined-sysfw-cfg */ - -&bcfg_yaml_sysfw { - schema = "../../ti/common/schema.yaml"; -}; - -&pcfg_yaml_sysfw { - schema = "../../ti/common/schema.yaml"; -}; - -&rcfg_yaml_sysfw { - schema = "../../ti/common/schema.yaml"; -}; - -&scfg_yaml_sysfw { - schema = "../../ti/common/schema.yaml"; -}; - -#endif /* CONFIG_ARM64 */ - #ifdef CONFIG_TARGET_VERDIN_AM62_R5 &binman { @@ -214,10 +140,7 @@ #ifdef CONFIG_TARGET_VERDIN_AM62_A53 -#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb" - -#define UBOOT_NODTB "u-boot-nodtb.bin" #define VERDIN_AM62_DTB "u-boot.dtb" &binman { @@ -228,80 +151,21 @@ }; }; ti-spl { - filename = "tispl.bin"; - pad-byte = <0xff>; + insert-template = <&ti_spl_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; images { - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - ti-secure { - content = <&atf>; - keyfile = "custMpk.pem"; - }; - atf: atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - ti-secure { - content = <&tee>; - keyfile = "custMpk.pem"; - }; - tee: tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; ti-secure { content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - ti-secure { - content = <&u_boot_spl_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_spl_nodtb: blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-am625-verdin-wifi-dev"; type = "flat_dt"; @@ -333,29 +197,12 @@ &binman { u-boot { - filename = "u-boot.img"; - pad-byte = <0xff>; + insert-template = <&u_boot_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM625 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - ti-secure { - content = <&u_boot_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_nodtb: u-boot-nodtb { - }; - hash { - algo = "crc32"; - }; + description = "U-Boot fot AM625 Verdin Board"; }; fdt-0 { @@ -392,66 +239,16 @@ &binman { ti-spl_unsigned { - filename = "tispl.bin_unsigned"; - pad-byte = <0xff>; + insert-template = <&ti_spl_unsigned_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - atf-bl31 { - filename = "bl31.bin"; - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - tee-os { - filename = "tee-raw.bin"; - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - blob { - filename = "spl/u-boot-spl-nodtb.bin"; - }; - }; - fdt-0 { description = "k3-am625-verdin-wifi-dev"; type = "flat_dt"; @@ -479,26 +276,12 @@ &binman { u-boot_unsigned { - filename = "u-boot.img_unsigned"; - pad-byte = <0xff>; + insert-template = <&u_boot_unsigned_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM625 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - blob { - filename = UBOOT_NODTB; - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM625 Verdin Board"; }; fdt-0 { diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi index 75cb60b57d7..02f34c90c6d 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi @@ -21,25 +21,8 @@ }; }; -&cbass_main { - bootph-all; - - timer@2400000 { - clock-frequency = <25000000>; - bootph-all; - }; -}; - -&cbass_mcu { - bootph-all; -}; - -&cbass_wakeup { - bootph-all; -}; - -&chipid { - bootph-all; +&main_timer0 { + clock-frequency = <25000000>; }; &main_bcdma { @@ -53,6 +36,7 @@ <0x00 0x484c2000 0x00 0x2000>; reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt" , "cfg", "tchan", "rchan"; + bootph-all; }; &main_pktdma { @@ -98,34 +82,16 @@ }; &dmsc { - bootph-all; - k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; bootph-all; }; }; -&dmss { - bootph-all; -}; - &fss { bootph-all; }; -&k3_clks { - bootph-all; -}; - -&k3_pds { - bootph-all; -}; - -&k3_reset { - bootph-all; -}; - &main_gpio0 { bootph-all; }; @@ -156,10 +122,6 @@ }; }; -&main_pmx0 { - bootph-all; -}; - /* Verdin UART_3, used as the Linux console */ &main_uart0 { bootph-all; @@ -170,10 +132,6 @@ bootph-all; }; -&mcu_pmx0 { - bootph-all; -}; - &pinctrl_ctrl_sleep_moci { bootph-all; }; @@ -210,18 +168,10 @@ status = "disabled"; }; -&secure_proxy_main { - bootph-all; -}; - &verdin_ctrl_sleep_moci { bootph-all; }; -&wkup_conf { - bootph-all; -}; - /* Verdin UART_2 */ &wkup_uart0 { bootph-all; diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi index bc4b50bcd17..4ae7fdc5221 100644 --- a/arch/arm/dts/k3-am62a-main.dtsi +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -48,6 +48,18 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock-controller@4130 { + compatible = "ti,am62-epwm-tbclk"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; }; dmss: bus@48000000 { @@ -69,6 +81,67 @@ interrupt-names = "rx_012"; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <28>; + ti,interrupt-ranges = <6 70 34>; + ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible = "ti,am64-dmss-bcdma"; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <26>; + ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am64-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <30>; + ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; }; dmsc: system-controller@44043000 { @@ -77,8 +150,8 @@ reg-names = "debug_messages"; ti,host-id = <12>; mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 12>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; k3_pds: power-controller { compatible = "ti,sci-pm-domain"; @@ -96,6 +169,21 @@ }; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; @@ -104,6 +192,102 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -222,6 +406,39 @@ status = "disabled"; }; + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 141 0>; + status = "disabled"; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 142 0>; + status = "disabled"; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 143 0>; + status = "disabled"; + }; + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; reg = <0x00 0x00a00000 0x00 0x800>; @@ -295,4 +512,368 @@ no-1-8-v; status = "disabled"; }; + + usbss0: dwc3-usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31000000 0x00 0x50000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x8000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 3>; + assigned-clock-parents = <&k3_clks 13 11>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&wkup_conf 0x200>; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 13 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29000000 0x00 0x200>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster1: mailbox@29010000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29010000 0x00 0x200>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster2: mailbox@29020000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29020000 0x00 0x200>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster3: mailbox@29030000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29030000 0x00 0x200>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti4: watchdog@e040000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e040000 0x00 0x100>; + clocks = <&k3_clks 205 0>; + power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 205 0>; + assigned-clock-parents = <&k3_clks 205 2>; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23000000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23010000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23020000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + status = "disabled"; + }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi index 6d1e501b94a..a6d16a94088 100644 --- a/arch/arm/dts/k3-am62a-mcu.dtsi +++ b/arch/arm/dts/k3-am62a-mcu.dtsi @@ -15,6 +15,51 @@ status = "disabled"; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; @@ -36,4 +81,90 @@ clock-names = "fck"; status = "disabled"; }; + + mcu_spi0: spi@4b00000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x04b00000 0x00 0x400>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 147 0>; + status = "disabled"; + }; + + mcu_spi1: spi@4b10000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x04b10000 0x00 0x400>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + status = "disabled"; + }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x04201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index de09430d936..ec3bf7ce913 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -144,10 +144,7 @@ #ifdef CONFIG_TARGET_AM62A7_A53_EVM -#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb" - -#define UBOOT_NODTB "u-boot-nodtb.bin" #define AM62A7_SK_DTB "u-boot.dtb" &binman { @@ -158,81 +155,20 @@ }; }; ti-spl { - filename = "tispl.bin"; - pad-byte = <0xff>; + insert-template = <&ti_spl_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - ti-secure { - content = <&atf>; - keyfile = "custMpk.pem"; - }; - atf: atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - ti-secure { - content = <&tee>; - keyfile = "custMpk.pem"; - }; - tee: tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; ti-secure { content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - ti-secure { - content = <&u_boot_spl_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_spl_nodtb: blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-am62a7-sk"; type = "flat_dt"; @@ -266,29 +202,12 @@ &binman { u-boot { - filename = "u-boot.img"; - pad-byte = <0xff>; + insert-template = <&u_boot_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM62Ax board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - ti-secure { - content = <&u_boot_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_nodtb: u-boot-nodtb { - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM62Ax Board"; }; fdt-0 { @@ -326,67 +245,16 @@ &binman { ti-spl_unsigned { - filename = "tispl.bin_unsigned"; - pad-byte = <0xff>; + insert-template = <&ti_spl_unsigned_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - atf-bl31 { - filename = "bl31.bin"; - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - tee-os { - filename = "tee-raw.bin"; - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - blob { - filename = "spl/u-boot-spl-nodtb.bin"; - }; - }; - fdt-0 { description = "k3-am62a7-sk"; type = "flat_dt"; @@ -414,26 +282,12 @@ &binman { u-boot_unsigned { - filename = "u-boot.img_unsigned"; - pad-byte = <0xff>; + insert-template = <&u_boot_unsigned_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM62Ax board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - blob { - filename = UBOOT_NODTB; - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM62Ax Board"; }; fdt-0 { diff --git a/arch/arm/dts/k3-am62a-thermal.dtsi b/arch/arm/dts/k3-am62a-thermal.dtsi new file mode 100644 index 00000000000..85ce545633e --- /dev/null +++ b/arch/arm/dts/k3-am62a-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/thermal/thermal.h> + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi index 99afac40e8d..4e8279fa01e 100644 --- a/arch/arm/dts/k3-am62a-wakeup.dtsi +++ b/arch/arm/dts/k3-am62a-wakeup.dtsi @@ -31,7 +31,7 @@ wkup_i2c0: i2c@2b200000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02b200000 0x00 0x100>; + reg = <0x00 0x2b200000 0x00 0x100>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -51,4 +51,23 @@ wakeup-source; status = "disabled"; }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi index 6eb87c3f9f3..61a210ecd5f 100644 --- a/arch/arm/dts/k3-am62a.dtsi +++ b/arch/arm/dts/k3-am62a.dtsi @@ -8,9 +8,10 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM62A SoC"; compatible = "ti,am62a7"; @@ -114,6 +115,8 @@ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; + + #include "k3-am62a-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index bbbd9e51d69..bc05dcb5efb 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -7,7 +7,6 @@ #include "k3-am62a7-sk.dts" #include "k3-am62a-ddr-1866mhz-32bit.dtsi" #include "k3-am62a-ddr.dtsi" -#include "k3-am62a-sk-binman.dtsi" #include "k3-am62a7-sk-u-boot.dtsi" @@ -15,33 +14,6 @@ aliases { remoteproc0 = &sysctrler; remoteproc1 = &a53_0; - serial0 = &wkup_uart0; - serial3 = &main_uart1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - tick-timer = &timer1; - }; - - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - bootph-pre-ram; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; }; a53_0: a53@0 { @@ -81,67 +53,39 @@ ti,secure-host; }; -&cbass_main { - sa3_secproxy: secproxy@44880000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg = <0x00 0x44880000 0x00 0x20000>, - <0x0 0x44860000 0x0 0x20000>, - <0x0 0x43600000 0x0 0x10000>; - reg-names = "rt", "scfg", "target_data"; - bootph-pre-ram; - }; +&secure_proxy_sa3 { + /* Needed for initial handshake with ROM */ + status = "okay"; + bootph-pre-ram; +}; +&cbass_main { sysctrler: sysctrler { compatible = "ti,am654-system-controller"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, - <&sa3_secproxy 0>; + <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; }; }; -&mcu_pmx0 { - status = "okay"; +&wkup_uart0_pins_default { bootph-pre-ram; - - wkup_uart0_pins_default: wkup-uart0-pins-default { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ - AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ - AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ - AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ - >; - bootph-pre-ram; - }; }; -&main_pmx0 { +&main_uart1_pins_default { bootph-pre-ram; - main_uart1_pins_default: main-uart1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ - AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ - AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ - AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ - >; - bootph-pre-ram; - }; }; /* WKUP UART0 is used for DM firmware logs */ &wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; status = "okay"; bootph-pre-ram; }; /* Main UART1 is used for TIFS firmware logs */ &main_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; status = "okay"; bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi index cf938c43b83..31b89b41748 100644 --- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi @@ -4,137 +4,186 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-am62a-sk-binman.dtsi" + / { chosen { stdout-path = "serial2:115200n8"; - tick-timer = &timer1; + tick-timer = &main_timer0; }; memory@80000000 { - bootph-pre-ram; + bootph-all; }; }; -&cbass_main{ - bootph-pre-ram; +&main_timer0 { + bootph-all; +}; - timer1: timer@2400000 { - compatible = "ti,omap5430-timer"; - reg = <0x00 0x2400000 0x00 0x80>; - ti,timer-alwon; - clock-frequency = <25000000>; - bootph-pre-ram; - }; +&cbass_main { + bootph-all; }; &dmss { - bootph-pre-ram; + bootph-all; }; &secure_proxy_main { - bootph-pre-ram; + bootph-all; }; &dmsc { - bootph-pre-ram; + bootph-all; }; &k3_pds { - bootph-pre-ram; + bootph-all; }; &k3_clks { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &wkup_conf { - bootph-pre-ram; + bootph-all; }; &chipid { - bootph-pre-ram; + bootph-all; }; &main_pmx0 { - bootph-pre-ram; + bootph-all; }; &main_uart0 { - bootph-pre-ram; + bootph-all; }; &main_uart0_pins_default { - bootph-pre-ram; -}; - -&main_uart1 { - bootph-pre-ram; + bootph-all; }; &cbass_mcu { - bootph-pre-ram; + bootph-all; }; &cbass_wakeup { - bootph-pre-ram; + bootph-all; }; &mcu_pmx0 { - bootph-pre-ram; -}; - -&wkup_uart0 { - bootph-pre-ram; + bootph-all; }; &main_gpio0 { - bootph-pre-ram; + bootph-all; }; &main_i2c0 { - bootph-pre-ram; + bootph-all; }; &main_i2c0_pins_default { - bootph-pre-ram; + bootph-all; }; &main_i2c1 { - bootph-pre-ram; + bootph-all; }; &main_i2c1_pins_default { - bootph-pre-ram; + bootph-all; }; &exp1 { - bootph-pre-ram; + bootph-all; }; &sdhci1 { - bootph-pre-ram; + bootph-all; }; &main_mmc1_pins_default { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &dmsc { - bootph-pre-ram; + bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - bootph-pre-ram; + bootph-all; }; }; &vdd_mmc1 { - bootph-pre-ram; + bootph-all; +}; + +&main_bcdma { + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", + "ringrt" , "cfg", "tchan", "rchan"; + bootph-all; +}; + +&main_pktdma { + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x20000>, + <0x00 0x4b800000 0x00 0x200000>, + <0x00 0x485e0000 0x00 0x10000>, + <0x00 0x484a0000 0x00 0x2000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x1000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", + "cfg", "tchan", "rchan", "rflow"; + bootph-all; +}; + +&main_mdio1_pins_default { + bootph-all; +}; + +&cpsw3g_mdio { + bootph-all; +}; + +&cpsw3g_phy0 { + bootph-all; +}; + +&main_rgmii1_pins_default { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + +&cpsw3g { + bootph-all; + ethernet-ports { + bootph-all; + }; +}; + +&cpsw_port1 { + bootph-all; }; diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts index 270e669f655..8f64ac2c756 100644 --- a/arch/arm/dts/k3-am62a7-sk.dts +++ b/arch/arm/dts/k3-am62a7-sk.dts @@ -9,15 +9,17 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> #include "k3-am62a7.dtsi" -#include "k3-am62a-sk-binman.dtsi" / { - compatible = "ti,am62a7-sk", "ti,am62a7"; + compatible = "ti,am62a7-sk", "ti,am62a7"; model = "Texas Instruments AM62A7 SK"; aliases { + serial0 = &wkup_uart0; serial2 = &main_uart0; + serial3 = &main_uart1; mmc1 = &sdhci1; }; @@ -77,10 +79,10 @@ regulator-boot-on; }; - vcc_3v3_sys: regulator-2 { + vcc_3v3_main: regulator-2 { /* output of LM5141-Q1 */ compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; + regulator-name = "vcc_3v3_main"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vmain_pd>; @@ -99,6 +101,17 @@ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; + vcc_3v3_sys: regulator-4 { + /* output of TPS222965DSGT */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_main>; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -112,38 +125,100 @@ default-state = "off"; }; }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62Ax-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; +}; + +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ + AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ + AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */ + AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ + >; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < - AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ + AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ + AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ + AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */ + AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -155,11 +230,64 @@ >; }; - usr_led_pins_default: usr-led-pins-default { + usr_led_pins_default: usr-led-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + main_mdio1_pins_default: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ + AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ + AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ + AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */ + AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */ + AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */ + AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */ + AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */ + AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */ + AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */ + AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */ + AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */ + AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ + >; + }; + + main_mcasp1_pins_default: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */ + AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */ + AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + >; + }; +}; + +&mcu_pmx0 { + status = "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ + >; + }; +}; + +&mcu_gpio0 { + status = "okay"; }; &main_i2c0 { @@ -167,13 +295,112 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + + typec_pd0: usb-power-controller@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + + tps659312: pmic@48 { + compatible = "ti,tps6593-q1"; + reg = <0x48>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&mcu_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + buck123-supply = <&vcc_3v3_sys>; + buck4-supply = <&vcc_3v3_sys>; + buck5-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&vcc_3v3_sys>; + ldo3-supply = <&buck5>; + ldo4-supply = <&vcc_3v3_sys>; + + regulators { + buck123: buck123 { + regulator-name = "vcc_core"; + regulator-min-microvolt = <715000>; + regulator-max-microvolt = <895000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "vcc_1v1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: buck5 { + regulator-name = "vcc_1v8_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "vddshv5_sdio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "vpp_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "vcc_0v85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: ldo4 { + regulator-name = "vdda_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &main_i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; + clock-frequency = <100000>; exp1: gpio@22 { compatible = "ti,tca6424"; @@ -194,6 +421,19 @@ "MCASP1_FET_SEL", "UART1_FET_SEL", "PD_I2C_IRQ", "IO_EXP_TEST_LED"; }; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + + /* Regulators */ + AVDD-supply = <&vcc_3v3_sys>; + IOVDD-supply = <&vcc_3v3_sys>; + DRVDD-supply = <&vcc_3v3_sys>; + DVDD-supply = <&buck5>; + }; }; &sdhci1 { @@ -223,3 +463,84 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "reserved"; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usbss1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi index 331d89fda29..58f1c43edcf 100644 --- a/arch/arm/dts/k3-am62a7.dtsi +++ b/arch/arm/dts/k3-am62a7.dtsi @@ -95,8 +95,9 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; }; diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi index 34c8ffc553e..19f57ead4eb 100644 --- a/arch/arm/dts/k3-am62x-sk-common.dtsi +++ b/arch/arm/dts/k3-am62x-sk-common.dtsi @@ -28,6 +28,7 @@ }; memory@80000000 { + bootph-pre-ram; device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; @@ -114,11 +115,23 @@ clocks = <&tlv320_mclk>; }; }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; }; &main_pmx0 { /* First pad number is ALW package and second is AMC package */ main_uart0_pins_default: main-uart0-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ @@ -126,6 +139,7 @@ }; main_uart1_pins_default: main-uart1-default-pins { + bootph-pre-ram; pinctrl-single,pins = < AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ @@ -156,6 +170,7 @@ }; main_mmc0_pins_default: main-mmc0-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ @@ -171,6 +186,7 @@ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ @@ -196,6 +212,7 @@ }; main_rgmii1_pins_default: main-rgmii1-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ @@ -226,10 +243,44 @@ AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ >; }; + + main_dss0_pins_default: main-dss0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ + AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ + AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ + AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ + AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; }; &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-pre-ram; pinctrl-single,pins = < AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ @@ -241,12 +292,14 @@ &wkup_uart0 { /* WKUP UART0 is used by DM firmware */ + bootph-pre-ram; status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -254,6 +307,7 @@ &main_uart1 { /* Main UART1 is used by TIFS firmware */ + bootph-pre-ram; status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; @@ -300,7 +354,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; + clock-frequency = <100000>; tlv320aic3106: audio-codec@1b { #sound-dai-cells = <0>; @@ -313,9 +367,40 @@ IOVDD-supply = <&vcc_3v3_sys>; DRVDD-supply = <&vcc_3v3_sys>; }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &sdhci0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; @@ -325,6 +410,7 @@ &sdhci1 { /* SD/MMC */ + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; @@ -333,21 +419,25 @@ }; &cpsw3g { + bootph-all; pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; }; &cpsw_port1 { + bootph-all; phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; }; &cpsw3g_mdio { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mdio1_pins_default>; cpsw3g_phy0: ethernet-phy@0 { + bootph-all; reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; @@ -410,3 +500,20 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi index a5e54006b44..88df2149545 100644 --- a/arch/arm/dts/k3-am64x-binman.dtsi +++ b/arch/arm/dts/k3-am64x-binman.dtsi @@ -118,87 +118,27 @@ #ifdef CONFIG_TARGET_AM642_A53_EVM -#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb" #define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb" -#define UBOOT_NODTB "u-boot-nodtb.bin" #define AM642_EVM_DTB "u-boot.dtb" #define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb" &binman { ti-spl { - filename = "tispl.bin"; - pad-byte = <0xff>; + insert-template = <&ti_spl_template>; fit { description = "Configuration to load ATF and SPL"; #address-cells = <1>; images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - ti-secure { - content = <&atf>; - keyfile = "custMpk.pem"; - }; - atf: atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - ti-secure { - content = <&tee>; - keyfile = "custMpk.pem"; - }; - tee: tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; blob-ext { filename = "/dev/null"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - ti-secure { - content = <&u_boot_spl_nodtb>; - keyfile = "custMpk.pem"; - - }; - u_boot_spl_nodtb: blob-ext { - filename = SPL_NODTB; - }; - }; fdt-0 { description = "k3-am642-evm"; @@ -254,29 +194,12 @@ &binman { u-boot { - filename = "u-boot.img"; - pad-byte = <0xff>; + insert-template = <&u_boot_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM64 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - ti-secure { - content = <&u_boot_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_nodtb: u-boot-nodtb { - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM64 Board"; }; fdt-0 { @@ -340,65 +263,17 @@ &binman { ti-spl_unsigned { - filename = "tispl.bin_unsigned"; - pad-byte = <0xff>; + insert-template = <&ti_spl_unsigned_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; blob-ext { filename = "/dev/null"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - blob { - filename = "spl/u-boot-spl-nodtb.bin"; - }; - }; - fdt-0 { description = "k3-am642-evm"; type = "flat_dt"; @@ -443,26 +318,12 @@ &binman { u-boot_unsigned { - filename = "u-boot.img_unsigned"; - pad-byte = <0xff>; + insert-template = <&u_boot_unsigned_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM64 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - blob { - filename = UBOOT_NODTB; - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM64 Board"; }; fdt-0 { diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi index 59605ca597b..8cc24da1f3f 100644 --- a/arch/arm/dts/k3-am65x-binman.dtsi +++ b/arch/arm/dts/k3-am65x-binman.dtsi @@ -42,77 +42,7 @@ }; itb { filename = "sysfw-am65x_sr2-hs-evm.itb"; - fit { - description = "SYSFW and Config fragments"; - #address-cells = <1>; - images { - sysfw.bin { - description = "sysfw"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "sysfw.bin"; - }; - }; - board-cfg.bin { - description = "board-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&board_cfg>; - keyfile = "custMpk.pem"; - }; - board_cfg: board-cfg { - filename = "board-cfg.bin"; - type = "blob-ext"; - }; - }; - pm-cfg.bin { - description = "pm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&pm_cfg>; - keyfile = "custMpk.pem"; - }; - pm_cfg: pm-cfg { - filename = "pm-cfg.bin"; - type = "blob-ext"; - }; - }; - rm-cfg.bin { - description = "rm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&rm_cfg>; - keyfile = "custMpk.pem";\ - }; - rm_cfg: rm-cfg { - filename = "rm-cfg.bin"; - type = "blob-ext"; - }; - }; - sec-cfg.bin { - description = "sec-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&sec_cfg>; - keyfile = "custMpk.pem"; - }; - sec_cfg: sec-cfg { - filename = "sec-cfg.bin"; - type = "blob-ext"; - }; - }; - }; - }; + insert-template = <&itb_template>; }; }; @@ -149,55 +79,14 @@ itb_gp { filename = "sysfw-am65x_sr2-gp-evm.itb"; symlink = "sysfw.itb"; + insert-template = <&itb_unsigned_template>; fit { - description = "SYSFW and Config fragments"; - #address-cells = <1>; images { sysfw.bin { - description = "sysfw"; - type = "firmware"; - arch = "arm"; - compression = "none"; blob-ext { filename = "sysfw.bin_gp"; }; }; - board-cfg.bin { - description = "board-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "board-cfg.bin"; - }; - }; - pm-cfg.bin { - description = "pm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "pm-cfg.bin"; - }; - }; - rm-cfg.bin { - description = "rm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "rm-cfg.bin"; - }; - }; - sec-cfg.bin { - description = "sec-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "sec-cfg.bin"; - }; - }; }; }; }; @@ -206,86 +95,22 @@ #ifdef CONFIG_TARGET_AM654_A53_EVM -#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb" - -#define UBOOT_NODTB "u-boot-nodtb.bin" #define AM654_EVM_DTB "u-boot.dtb" &binman { ti-spl { - filename = "tispl.bin"; - pad-byte = <0xff>; + insert-template = <&ti_spl_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - ti-secure { - content = <&atf>; - keyfile = "custMpk.pem"; - }; - atf: atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - ti-secure { - content = <&tee>; - keyfile = "custMpk.pem"; - }; - tee: tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; blob-ext { filename = "/dev/null"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - ti-secure { - content = <&u_boot_spl_nodtb>; - keyfile = "custMpk.pem"; - - }; - u_boot_spl_nodtb: blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-am654-base-board"; type = "flat_dt"; @@ -317,29 +142,12 @@ &binman { u-boot { - filename = "u-boot.img"; - pad-byte = <0xff>; + insert-template = <&u_boot_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM65 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - ti-secure { - content = <&u_boot_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_nodtb: u-boot-nodtb { - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM65 Board"; }; fdt-0 { @@ -378,67 +186,16 @@ &binman { ti-spl_unsigned { - filename = "tispl.bin_unsigned"; - pad-byte = <0xff>; + insert-template = <&ti_spl_unsigned_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - atf-bl31 { - filename = "bl31.bin"; - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - tee-os { - filename = "tee-raw.bin"; - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; blob-ext { filename = "/dev/null"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-j721e-common-proc-board"; type = "flat_dt"; @@ -466,26 +223,12 @@ &binman { u-boot_unsigned { - filename = "u-boot.img_unsigned"; - pad-byte = <0xff>; + insert-template = <&u_boot_unsigned_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for AM65 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - blob { - filename = UBOOT_NODTB; - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for AM65 Board"; }; fdt-0 { diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts index 5df5946687b..1e1a82f9d2b 100644 --- a/arch/arm/dts/k3-am68-sk-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-base-board.dts @@ -553,3 +553,59 @@ }; }; }; + +&serdes_ln_ctrl { + idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>, + <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_usb_link: phy@2 { + status = "okay"; + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_USB3>; + resets = <&serdes_wiz0 3>; + }; +}; + +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES lane 2 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi index 6c9139f7320..20861a0a46b 100644 --- a/arch/arm/dts/k3-am68-sk-som.dtsi +++ b/arch/arm/dts/k3-am68-sk-som.dtsi @@ -25,6 +25,108 @@ reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; }; @@ -49,3 +151,109 @@ reg = <0x51>; }; }; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi index 2ea2dd18a12..cd9926a0169 100644 --- a/arch/arm/dts/k3-binman.dtsi +++ b/arch/arm/dts/k3-binman.dtsi @@ -13,14 +13,14 @@ custMpk { filename = "custMpk.pem"; custmpk_pem: blob-ext { - filename = "../keys/custMpk.pem"; + filename = "arch/arm/mach-k3/keys/custMpk.pem"; }; }; ti-degenerate-key { filename = "ti-degenerate-key.pem"; dkey_pem: blob-ext { - filename = "../keys/ti-degenerate-key.pem"; + filename = "arch/arm/mach-k3/keys/ti-degenerate-key.pem"; }; }; }; @@ -32,28 +32,28 @@ filename = "board-cfg.bin"; bcfg_yaml: ti-board-config { config = "board-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; }; pm-cfg { filename = "pm-cfg.bin"; pcfg_yaml: ti-board-config { config = "pm-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; }; rm-cfg { filename = "rm-cfg.bin"; rcfg_yaml: ti-board-config { config = "rm-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; }; sec-cfg { filename = "sec-cfg.bin"; scfg_yaml: ti-board-config { config = "sec-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; }; combined-tifs-cfg { @@ -61,19 +61,19 @@ ti-board-config { bcfg_yaml_tifs: board-cfg { config = "board-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; scfg_yaml_tifs: sec-cfg { config = "sec-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; pcfg_yaml_tifs: pm-cfg { config = "pm-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; rcfg_yaml_tifs: rm-cfg { config = "rm-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; }; }; @@ -82,11 +82,11 @@ ti-board-config { pcfg_yaml_dm: pm-cfg { config = "pm-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; rcfg_yaml_dm: rm-cfg { config = "rm-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; }; }; @@ -95,22 +95,349 @@ ti-board-config { bcfg_yaml_sysfw: board-cfg { config = "board-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; scfg_yaml_sysfw: sec-cfg { config = "sec-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; pcfg_yaml_sysfw: pm-cfg { config = "pm-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; rcfg_yaml_sysfw: rm-cfg { config = "rm-cfg.yaml"; - schema = "../common/schema.yaml"; + schema = "arch/arm/mach-k3/schema.yaml"; }; }; }; }; +&binman { + itb_template: template-5 { + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&board_cfg>; + keyfile = "custMpk.pem"; + }; + board_cfg: board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&pm_cfg>; + keyfile = "custMpk.pem"; + }; + pm_cfg: pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&rm_cfg>; + keyfile = "custMpk.pem"; + }; + rm_cfg: rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&sec_cfg>; + keyfile = "custMpk.pem"; + }; + sec_cfg: sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; + + itb_unsigned_template: template-6 { + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_fs"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; +}; + +#else + +&binman { + ti_spl_template: template-1 { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = <CONFIG_K3_ATF_LOAD_ADDR>; + entry = <CONFIG_K3_ATF_LOAD_ADDR>; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SPL_TEXT_BASE>; + entry = <CONFIG_SPL_TEXT_BASE>; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + + }; + u_boot_spl_nodtb: blob-ext { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + + }; + }; + }; + ti_spl_unsigned_template: template-2 { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = <CONFIG_K3_ATF_LOAD_ADDR>; + entry = <CONFIG_K3_ATF_LOAD_ADDR>; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SPL_TEXT_BASE>; + entry = <CONFIG_SPL_TEXT_BASE>; + blob-ext { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + }; + }; + }; + u_boot_template: template-3 { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + }; + }; + }; + u_boot_unsigned_template: template-4 { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + blob { + filename = "u-boot-nodtb.bin"; + }; + hash { + algo = "crc32"; + }; + }; + }; + }; + }; + +}; + #endif diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 14f7dea65ee..38cccabaa71 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -180,10 +180,7 @@ #ifdef CONFIG_TARGET_J7200_A72_EVM -#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb" - -#define UBOOT_NODTB "u-boot-nodtb.bin" #define J7200_EVM_DTB "u-boot.dtb" &binman { @@ -194,82 +191,20 @@ }; }; ti-spl { - filename = "tispl.bin"; - pad-byte = <0xff>; + insert-template = <&ti_spl_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - ti-secure { - content = <&atf>; - keyfile = "custMpk.pem"; - }; - atf: atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - ti-secure { - content = <&tee>; - keyfile = "custMpk.pem"; - }; - tee: tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; ti-secure { content = <&dm>; keyfile = "custMpk.pem"; }; - - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - ti-secure { - content = <&u_boot_spl_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_spl_nodtb: blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-j7200-common-proc-board"; type = "flat_dt"; @@ -302,29 +237,12 @@ &binman { u-boot { - filename = "u-boot.img"; - pad-byte = <0xff>; + insert-template = <&u_boot_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for J7200 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - ti-secure { - content = <&u_boot_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_nodtb: u-boot-nodtb { - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for J7200 Board"; }; fdt-0 { @@ -362,67 +280,16 @@ &binman { ti-spl_unsigned { - filename = "tispl.bin_unsigned"; - pad-byte = <0xff>; + insert-template = <&ti_spl_unsigned_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - atf-bl31 { - filename = "bl31.bin"; - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - tee-os { - filename = "tee-raw.bin"; - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - blob { - filename = SPL_NODTB; - }; - }; - fdt-1 { description = "k3-j7200-common-proc-board"; type = "flat_dt"; @@ -450,26 +317,12 @@ &binman { u-boot_unsigned { - filename = "u-boot.img_unsigned"; - pad-byte = <0xff>; + insert-template = <&u_boot_unsigned_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for J7200 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - blob { - filename = UBOOT_NODTB; - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for J7200 Board"; }; fdt-1 { diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index cdb1d6b2a98..264913f8328 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -91,7 +91,7 @@ }; main_navss: bus@30000000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index 6ffaf85fa63..3fc588b848c 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -318,7 +318,7 @@ }; mcu_navss: bus@28380000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; @@ -637,4 +637,11 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi new file mode 100644 index 00000000000..f83caf79988 --- /dev/null +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleboard.org/ai-64 + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +#include "k3-binman.dtsi" + +/ { + memory@80000000 { + bootph-all; + }; + + /* Keep the LEDs on by default to indicate life */ + leds { + bootph-all; + led-0 { + default-state = "on"; + bootph-all; + }; + + led-1 { + default-state = "on"; + bootph-all; + }; + + led-2 { + default-state = "on"; + bootph-all; + }; + + led-3 { + default-state = "on"; + bootph-all; + }; + + led-4 { + default-state = "on"; + bootph-all; + }; + }; +}; + +&cbass_main { + bootph-all; +}; + +&main_navss { + bootph-all; +}; + +&cbass_mcu_wakeup { + bootph-all; + + chipid@43000014 { + bootph-all; + }; +}; + +&mcu_navss { + bootph-all; +}; + +&mcu_ringacc { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; +}; + +&mcu_udmap { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; + bootph-all; +}; + +&secure_proxy_main { + bootph-all; +}; + +&dmsc { + bootph-all; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + bootph-all; + }; +}; + +&k3_pds { + bootph-all; +}; + +&k3_clks { + bootph-all; +}; + +&k3_reset { + bootph-all; +}; + +&wkup_pmx0 { + bootph-all; +}; + +&main_pmx0 { + bootph-all; +}; + +&main_uart0 { + bootph-all; +}; + +&main_gpio0 { + bootph-all; +}; + +&main_uart0_pins_default { + bootph-all; +}; + +&main_sdhci0 { + bootph-all; +}; + +&main_sdhci1 { + bootph-all; + sdhci-caps-mask = <0x00000007 0x00000000>; + /delete-property/ cd-gpios; + /delete-property/ cd-debounce-delay-ms; + /delete-property/ ti,fails-without-test-cd; + /delete-property/ no-1-8-v; +}; + +&main_mmc1_pins_default { + bootph-all; +}; + +&mcu_cpsw { + bootph-all; +}; + +&davinci_mdio { + bootph-all; +}; + +&phy0 { + bootph-all; +}; + +&serdes2 { + bootph-all; +}; + +&serdes_ln_ctrl { + bootph-all; +}; + +&serdes2_usb_link { + bootph-all; +}; + +&usb_serdes_mux { + bootph-all; +}; + +&serdes_wiz2 { + bootph-all; +}; + +&main_usbss1_pins_default { + bootph-all; +}; + +&mcu_usbss1_pins_default { + bootph-all; +}; + +&usbss1 { + bootph-all; +}; + +&usb1 { + bootph-all; +}; + +&wkup_i2c0_pins_default { + bootph-all; +}; + +&wkup_i2c0 { + bootph-all; +}; + +#ifdef CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64 + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_J721E_BBAI64_DTB "spl/dts/k3-j721e-beagleboneai64.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define J721E_BBAI64_DTB "arch/arm/dts/k3-j721e-beagleboneai64.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = <CONFIG_K3_ATF_LOAD_ADDR>; + entry = <CONFIG_K3_ATF_LOAD_ADDR>; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-raw.bin"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SPL_TEXT_BASE>; + entry = <CONFIG_SPL_TEXT_BASE>; + blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-j721e-beagleboneai64"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = SPL_J721E_BBAI64_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721e-beagleboneai64"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; + + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for j721e board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-j721e-beagleboneai64"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = J721E_BBAI64_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j721e-beagleboneai64"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-j721e-beagleboneai64.dts b/arch/arm/dts/k3-j721e-beagleboneai64.dts new file mode 100644 index 00000000000..2f954729f35 --- /dev/null +++ b/arch/arm/dts/k3-j721e-beagleboneai64.dts @@ -0,0 +1,993 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleboard.org/ai-64 + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation + */ + +/dts-v1/; + +#include "k3-j721e.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-cadence.h> + +/ { + compatible = "beagle,j721e-beagleboneai64", "ti,j721e"; + model = "BeagleBoard.org BeagleBone AI-64"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; + i2c1 = &main_i2c6; + i2c2 = &main_i2c2; + i2c3 = &main_i2c4; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c66_1_dma_memory_region: c66-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: c66-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c66_0_dma_memory_region: c66-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: c66-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_pwr_pins_default>; + + button-1 { + label = "BOOT"; + linux,code = <BTN_0>; + gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; + }; + + button-2 { + label = "POWER"; + linux,code = <KEY_POWER>; + gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_default>; + + led-0 { + gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "mmc0"; + }; + + led-2 { + gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_CPU; + linux,default-trigger = "cpu"; + }; + + led-3 { + gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "mmc1"; + }; + + led-4 { + gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_WLAN; + default-state = "off"; + }; + }; + + evm_12v0: regulator-0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-1 { + /* Output of LMS140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: regulator-2 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pwr_en_pins_default>; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv_alt: regulator-4 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; + regulator-name = "tlv71033"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + dp_pwr_3v3: regulator-5 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_3v3_en_pins_default>; + regulator-name = "dp-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; +}; + +&main_pmx0 { + led_pins_default: led-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ + J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */ + J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ + J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ + J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ + J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ + J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ + J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + + sd_pwr_en_pins_default: sd-pwr-en-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + >; + }; + + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ + >; + }; + + main_usbss0_pins_default: main-usbss0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ + >; + }; + + main_usbss1_pins_default: main-usbss1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ + >; + }; + + dp0_3v3_en_pins_default:dp0-3v3-en-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ + >; + }; + + dp0_pins_default: dp0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ + J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ + J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ + J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ + J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ + J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ + >; + }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ + J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ + J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ + J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ + J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ + >; + }; + + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ + >; + }; + + main_i2c6_pins_default: main-i2c6-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ + J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ + J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ + J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ + >; + }; + + csi0_gpio_pins_default: csi0-gpio-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + >; + }; + + csi1_gpio_pins_default: csi1-gpio-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + >; + }; + + pcie1_rst_pins_default: pcie1-rst-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ + >; + }; +}; + +&wkup_pmx0 { + eeprom_wp_pins_default: eeprom-wp-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ + J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ + J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */ + J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */ + J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */ + J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ + J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ + >; + }; + + mikro_bus_pins_default: mikro-bus-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ + J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ + + J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */ + J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */ + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */ + J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */ + + J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ + + J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ + J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */ + J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */ + J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ + J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ + >; + }; + + sw_pwr_pins_default: sw-pwr-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_usbss1_pins_default: mcu-usbss1-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ + >; + }; +}; + +&wkup_uart0 { + /* Wakeup UART is used by TIFS firmware. */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + /* Shared with ATF on this platform */ + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +}; + +&main_sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci1 { + /* SD Card */ + status = "okay"; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv_alt>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c2 { + /* BBB Header: P9.19 and P9.20 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <100000>; +}; + +&main_i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c4 { + /* BBB Header: P9.24 and P9.26 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <100000>; +}; + +&main_i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c6 { + /* BBB Header: P9.17 and P9.18 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c6_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&eeprom_wp_pins_default>; + }; +}; + +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, + <&mikro_bus_pins_default>; +}; + +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; +}; + +&main_gpio1 { + status = "okay"; +}; + +&usb_serdes_mux { + idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ +}; + +&serdes_ln_ctrl { + idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, + <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, + <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, + <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, + <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, + <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; +}; + +&serdes_wiz3 { + typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>; + typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ +}; + +&serdes3 { + serdes3_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_USB3>; + resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + }; +}; + +&serdes4 { + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = <PHY_TYPE_DP>; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; +}; + +&mhdp { + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; +}; + +&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "peripheral"; + maximum-speed = "super-speed"; + phys = <&serdes3_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&serdes2 { + serdes2_usb_link: phy@1 { + reg = <1>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_USB3>; + resets = <&serdes_wiz2 2>; + }; +}; + +&usbss1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>; + ti,vbus-divider; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes2_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&tscadc0 { + status = "okay"; + /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ + adc { + ti,adc-channels = <0 1 2 3 4 5 6>; + }; +}; + +&tscadc1 { + status = "okay"; + /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ + adc { + ti,adc-channels = <0>; + }; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&dss { + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP0 - DisplayPort SST + * VP1 - DPI0 + * VP2 - DSI + * VP3 - DPI1 + */ + + assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ + <&k3_clks 152 4>, /* VP 2 pixel clock */ + <&k3_clks 152 9>, /* VP 3 pixel clock */ + <&k3_clks 152 13>; /* VP 4 pixel clock */ + assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ + <&k3_clks 152 6>, /* PLL19_HSDIV0 */ + <&k3_clks 152 11>, /* PLL18_HSDIV0 */ + <&k3_clks 152 18>; /* PLL23_HSDIV0 */ +}; + +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&pcie1_rc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_rst_pins_default>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + max-link-speed = <3>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; +}; + +&ufs_wrapper { + status = "disabled"; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c66_0 { + status = "okay"; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + memory-region = <&c66_0_dma_memory_region>, + <&c66_0_memory_region>; +}; + +&c66_1 { + status = "okay"; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + memory-region = <&c66_1_dma_memory_region>, + <&c66_1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 4f566c21a9a..dbc385a852d 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -42,78 +42,7 @@ }; itb { filename = "sysfw-j721e_sr1_1-hs-evm.itb"; - fit { - description = "SYSFW and Config fragments"; - #address-cells = <1>; - images { - sysfw.bin { - description = "sysfw"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "sysfw.bin"; - }; - }; - board-cfg.bin { - description = "board-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&board_cfg>; - keyfile = "custMpk.pem"; - }; - board_cfg: board-cfg { - filename = "board-cfg.bin"; - type = "blob-ext"; - }; - - }; - pm-cfg.bin { - description = "pm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&pm_cfg>; - keyfile = "custMpk.pem"; - }; - pm_cfg: pm-cfg { - filename = "pm-cfg.bin"; - type = "blob-ext"; - }; - }; - rm-cfg.bin { - description = "rm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&rm_cfg>; - keyfile = "custMpk.pem"; - }; - rm_cfg: rm-cfg { - filename = "rm-cfg.bin"; - type = "blob-ext"; - }; - }; - sec-cfg.bin { - description = "sec-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&sec_cfg>; - keyfile = "custMpk.pem"; - }; - sec_cfg: sec-cfg { - filename = "sec-cfg.bin"; - type = "blob-ext"; - }; - }; - }; - }; + insert-template = <&itb_template>; }; }; @@ -145,62 +74,7 @@ }; itb_fs { filename = "sysfw-j721e_sr2-hs-fs-evm.itb"; - fit { - description = "SYSFW and Config fragments"; - #address-cells = <1>; - images { - sysfw.bin { - description = "sysfw"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "sysfw.bin_fs"; - }; - }; - board-cfg.bin { - description = "board-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - board-cfg { - filename = "board-cfg.bin"; - type = "blob-ext"; - }; - - }; - pm-cfg.bin { - description = "pm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - pm-cfg { - filename = "pm-cfg.bin"; - type = "blob-ext"; - }; - }; - rm-cfg.bin { - description = "rm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - rm-cfg { - filename = "rm-cfg.bin"; - type = "blob-ext"; - }; - }; - sec-cfg.bin { - description = "sec-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - sec-cfg { - filename = "sec-cfg.bin"; - type = "blob-ext"; - }; - }; - }; - }; + insert-template = <&itb_unsigned_template>; }; }; @@ -237,55 +111,15 @@ itb_gp { filename = "sysfw-j721e-gp-evm.itb"; symlink = "sysfw.itb"; + insert-template = <&itb_unsigned_template>; + fit { - description = "SYSFW and Config fragments"; - #address-cells = <1>; images { sysfw.bin { - description = "sysfw"; - type = "firmware"; - arch = "arm"; - compression = "none"; blob-ext { filename = "sysfw.bin_gp"; }; }; - board-cfg.bin { - description = "board-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "board-cfg.bin"; - }; - }; - pm-cfg.bin { - description = "pm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "pm-cfg.bin"; - }; - }; - rm-cfg.bin { - description = "rm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "rm-cfg.bin"; - }; - }; - sec-cfg.bin { - description = "sec-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "sec-cfg.bin"; - }; - }; }; }; }; @@ -294,11 +128,9 @@ #ifdef CONFIG_TARGET_J721E_A72_EVM -#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb" #define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb" -#define UBOOT_NODTB "u-boot-nodtb.bin" #define J721E_EVM_DTB "u-boot.dtb" #define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb" @@ -310,82 +142,20 @@ }; }; ti-spl { - filename = "tispl.bin"; - pad-byte = <0xff>; + insert-template = <&ti_spl_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - ti-secure { - content = <&atf>; - keyfile = "custMpk.pem"; - }; - atf: atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - ti-secure { - content = <&tee>; - keyfile = "custMpk.pem"; - }; - tee: tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; ti-secure { content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - ti-secure { - content = <&u_boot_spl_nodtb>; - keyfile = "custMpk.pem"; - - }; - u_boot_spl_nodtb: blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-j721e-common-proc-board"; type = "flat_dt"; @@ -439,29 +209,12 @@ &binman { u-boot { - filename = "u-boot.img"; - pad-byte = <0xff>; - + insert-template = <&u_boot_template>; fit { - description = "FIT image with multiple configurations"; images { uboot { - description = "U-Boot for j721e board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - ti-secure { - content = <&u_boot_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_nodtb: u-boot-nodtb { - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for J721E Board"; }; fdt-0 { @@ -524,67 +277,16 @@ &binman { ti-spl_unsigned { - filename = "tispl.bin_unsigned"; - pad-byte = <0xff>; + insert-template = <&ti_spl_unsigned_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - atf-bl31 { - filename = "bl31.bin"; - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - tee-os { - filename = "tee-raw.bin"; - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-j721e-common-proc-board"; type = "flat_dt"; @@ -629,26 +331,12 @@ &binman { u-boot_unsigned { - filename = "u-boot.img_unsigned"; - pad-byte = <0xff>; + insert-template = <&u_boot_unsigned_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for j721e board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - blob { - filename = UBOOT_NODTB; - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for J721E Board"; }; fdt-0 { diff --git a/arch/arm/dts/k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi b/arch/arm/dts/k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi new file mode 100644 index 00000000000..89e17751ade --- /dev/null +++ b/arch/arm/dts/k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi @@ -0,0 +1,2200 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.1 + * This file was generated on 02/08/2023 + * Part Number: Kingston Q3222PM1WDGTK-U + * Configuration: LPDDR4-3200, wrDBI enabled, j721e-SK latencies + * Also common for: + * * Part Number: Samsung K4FBE3D4HM-MGC @ LPDDR4-3200 (instead of 3700) + */ + +#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 + +#define DDRSS_CTL_00_DATA 0x00000B00 +#define DDRSS_CTL_01_DATA 0x00000000 +#define DDRSS_CTL_02_DATA 0x00000000 +#define DDRSS_CTL_03_DATA 0x00000000 +#define DDRSS_CTL_04_DATA 0x00000000 +#define DDRSS_CTL_05_DATA 0x00000000 +#define DDRSS_CTL_06_DATA 0x00000000 +#define DDRSS_CTL_07_DATA 0x00002AF8 +#define DDRSS_CTL_08_DATA 0x0001ADAF +#define DDRSS_CTL_09_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x0000006E +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000C80 +#define DDRSS_CTL_19_DATA 0x01010000 +#define DDRSS_CTL_20_DATA 0x02011001 +#define DDRSS_CTL_21_DATA 0x02010000 +#define DDRSS_CTL_22_DATA 0x00020100 +#define DDRSS_CTL_23_DATA 0x0000000B +#define DDRSS_CTL_24_DATA 0x0000001C +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x03020200 +#define DDRSS_CTL_28_DATA 0x00004040 +#define DDRSS_CTL_29_DATA 0x00100000 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x040C0000 +#define DDRSS_CTL_35_DATA 0x0E380E38 +#define DDRSS_CTL_36_DATA 0x00050804 +#define DDRSS_CTL_37_DATA 0x09040008 +#define DDRSS_CTL_38_DATA 0x14000304 +#define DDRSS_CTL_39_DATA 0x15480068 +#define DDRSS_CTL_40_DATA 0x14004220 +#define DDRSS_CTL_41_DATA 0x15480068 +#define DDRSS_CTL_42_DATA 0x20004220 +#define DDRSS_CTL_43_DATA 0x000A0A09 +#define DDRSS_CTL_44_DATA 0x0400078A +#define DDRSS_CTL_45_DATA 0x17100D04 +#define DDRSS_CTL_46_DATA 0x0C00DB60 +#define DDRSS_CTL_47_DATA 0x17100D0C +#define DDRSS_CTL_48_DATA 0x0C00DB60 +#define DDRSS_CTL_49_DATA 0x0203040C +#define DDRSS_CTL_50_DATA 0x21040500 +#define DDRSS_CTL_51_DATA 0x08222122 +#define DDRSS_CTL_52_DATA 0x14000E0A +#define DDRSS_CTL_53_DATA 0x03010A0A +#define DDRSS_CTL_54_DATA 0x01010003 +#define DDRSS_CTL_55_DATA 0x04424208 +#define DDRSS_CTL_56_DATA 0x04252504 +#define DDRSS_CTL_57_DATA 0x00002525 +#define DDRSS_CTL_58_DATA 0x00010100 +#define DDRSS_CTL_59_DATA 0x03010000 +#define DDRSS_CTL_60_DATA 0x00001008 +#define DDRSS_CTL_61_DATA 0x000000CE +#define DDRSS_CTL_62_DATA 0x000001C0 +#define DDRSS_CTL_63_DATA 0x00001858 +#define DDRSS_CTL_64_DATA 0x000001C0 +#define DDRSS_CTL_65_DATA 0x00001858 +#define DDRSS_CTL_66_DATA 0x00000005 +#define DDRSS_CTL_67_DATA 0x00040000 +#define DDRSS_CTL_68_DATA 0x00700012 +#define DDRSS_CTL_69_DATA 0x00700304 +#define DDRSS_CTL_70_DATA 0x00400304 +#define DDRSS_CTL_71_DATA 0x00120103 +#define DDRSS_CTL_72_DATA 0x000C0005 +#define DDRSS_CTL_73_DATA 0x2408000C +#define DDRSS_CTL_74_DATA 0x05050124 +#define DDRSS_CTL_75_DATA 0x0301030A +#define DDRSS_CTL_76_DATA 0x03170C08 +#define DDRSS_CTL_77_DATA 0x0C080301 +#define DDRSS_CTL_78_DATA 0x00010317 +#define DDRSS_CTL_79_DATA 0x00100010 +#define DDRSS_CTL_80_DATA 0x01CC01CC +#define DDRSS_CTL_81_DATA 0x01CC01CC +#define DDRSS_CTL_82_DATA 0x03050505 +#define DDRSS_CTL_83_DATA 0x03010303 +#define DDRSS_CTL_84_DATA 0x18080C08 +#define DDRSS_CTL_85_DATA 0x03030C03 +#define DDRSS_CTL_86_DATA 0x18080C08 +#define DDRSS_CTL_87_DATA 0x03030C03 +#define DDRSS_CTL_88_DATA 0x03010000 +#define DDRSS_CTL_89_DATA 0x00010000 +#define DDRSS_CTL_90_DATA 0x00000000 +#define DDRSS_CTL_91_DATA 0x00000000 +#define DDRSS_CTL_92_DATA 0x01000000 +#define DDRSS_CTL_93_DATA 0x80104002 +#define DDRSS_CTL_94_DATA 0x00000000 +#define DDRSS_CTL_95_DATA 0x00040005 +#define DDRSS_CTL_96_DATA 0x00000000 +#define DDRSS_CTL_97_DATA 0x00050000 +#define DDRSS_CTL_98_DATA 0x00000004 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x00040005 +#define DDRSS_CTL_101_DATA 0x00000000 +#define DDRSS_CTL_102_DATA 0x00003380 +#define DDRSS_CTL_103_DATA 0x00003380 +#define DDRSS_CTL_104_DATA 0x00003380 +#define DDRSS_CTL_105_DATA 0x00003380 +#define DDRSS_CTL_106_DATA 0x00003380 +#define DDRSS_CTL_107_DATA 0x00000000 +#define DDRSS_CTL_108_DATA 0x000005A2 +#define DDRSS_CTL_109_DATA 0x00061600 +#define DDRSS_CTL_110_DATA 0x00061600 +#define DDRSS_CTL_111_DATA 0x00061600 +#define DDRSS_CTL_112_DATA 0x00061600 +#define DDRSS_CTL_113_DATA 0x00061600 +#define DDRSS_CTL_114_DATA 0x00000000 +#define DDRSS_CTL_115_DATA 0x0000AA68 +#define DDRSS_CTL_116_DATA 0x00061600 +#define DDRSS_CTL_117_DATA 0x00061600 +#define DDRSS_CTL_118_DATA 0x00061600 +#define DDRSS_CTL_119_DATA 0x00061600 +#define DDRSS_CTL_120_DATA 0x00061600 +#define DDRSS_CTL_121_DATA 0x00000000 +#define DDRSS_CTL_122_DATA 0x0000AA68 +#define DDRSS_CTL_123_DATA 0x00000000 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x00000000 +#define DDRSS_CTL_126_DATA 0x00000000 +#define DDRSS_CTL_127_DATA 0x00000000 +#define DDRSS_CTL_128_DATA 0x00000000 +#define DDRSS_CTL_129_DATA 0x00000000 +#define DDRSS_CTL_130_DATA 0x00000000 +#define DDRSS_CTL_131_DATA 0x08030500 +#define DDRSS_CTL_132_DATA 0x00030803 +#define DDRSS_CTL_133_DATA 0x0A090000 +#define DDRSS_CTL_134_DATA 0x0A090701 +#define DDRSS_CTL_135_DATA 0x0900000E +#define DDRSS_CTL_136_DATA 0x0907010A +#define DDRSS_CTL_137_DATA 0x00000E0A +#define DDRSS_CTL_138_DATA 0x07010A09 +#define DDRSS_CTL_139_DATA 0x000E0A09 +#define DDRSS_CTL_140_DATA 0x07000401 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x08080000 +#define DDRSS_CTL_149_DATA 0x01000000 +#define DDRSS_CTL_150_DATA 0x800000C0 +#define DDRSS_CTL_151_DATA 0x800000C0 +#define DDRSS_CTL_152_DATA 0x800000C0 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00001500 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000001 +#define DDRSS_CTL_157_DATA 0x00000002 +#define DDRSS_CTL_158_DATA 0x0000100E +#define DDRSS_CTL_159_DATA 0x00000000 +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x00000000 +#define DDRSS_CTL_162_DATA 0x00000000 +#define DDRSS_CTL_163_DATA 0x00000000 +#define DDRSS_CTL_164_DATA 0x000B0000 +#define DDRSS_CTL_165_DATA 0x000E0006 +#define DDRSS_CTL_166_DATA 0x000E0404 +#define DDRSS_CTL_167_DATA 0x00A00140 +#define DDRSS_CTL_168_DATA 0x0C0C0190 +#define DDRSS_CTL_169_DATA 0x01400190 +#define DDRSS_CTL_170_DATA 0x019000A0 +#define DDRSS_CTL_171_DATA 0x01900C0C +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x2DD40084 +#define DDRSS_CTL_176_DATA 0xAB002DD4 +#define DDRSS_CTL_177_DATA 0x0000ABAB +#define DDRSS_CTL_178_DATA 0x45450000 +#define DDRSS_CTL_179_DATA 0x27272745 +#define DDRSS_CTL_180_DATA 0x0F0F0F00 +#define DDRSS_CTL_181_DATA 0x1D000000 +#define DDRSS_CTL_182_DATA 0x00841D1D +#define DDRSS_CTL_183_DATA 0x2DD42DD4 +#define DDRSS_CTL_184_DATA 0xABABAB00 +#define DDRSS_CTL_185_DATA 0x00000000 +#define DDRSS_CTL_186_DATA 0x27454545 +#define DDRSS_CTL_187_DATA 0x0F002727 +#define DDRSS_CTL_188_DATA 0x00000F0F +#define DDRSS_CTL_189_DATA 0x1D1D1D00 +#define DDRSS_CTL_190_DATA 0x00000020 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000001 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x01000000 +#define DDRSS_CTL_195_DATA 0x00000001 +#define DDRSS_CTL_196_DATA 0x00000000 +#define DDRSS_CTL_197_DATA 0x00000000 +#define DDRSS_CTL_198_DATA 0x00000000 +#define DDRSS_CTL_199_DATA 0x00000000 +#define DDRSS_CTL_200_DATA 0x00000000 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x02000000 +#define DDRSS_CTL_207_DATA 0x01080101 +#define DDRSS_CTL_208_DATA 0x00000000 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000000 +#define DDRSS_CTL_212_DATA 0x00000000 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000000 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000000 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000000 +#define DDRSS_CTL_221_DATA 0x00000000 +#define DDRSS_CTL_222_DATA 0x00001000 +#define DDRSS_CTL_223_DATA 0x006403E8 +#define DDRSS_CTL_224_DATA 0x00000000 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x15110000 +#define DDRSS_CTL_228_DATA 0x00040C18 +#define DDRSS_CTL_229_DATA 0xF000C000 +#define DDRSS_CTL_230_DATA 0x0000F000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0xC0000000 +#define DDRSS_CTL_234_DATA 0xF000F000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0xF000C000 +#define DDRSS_CTL_239_DATA 0x0000F000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00030000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x01000200 +#define DDRSS_CTL_258_DATA 0x00370040 +#define DDRSS_CTL_259_DATA 0x00020008 +#define DDRSS_CTL_260_DATA 0x00400100 +#define DDRSS_CTL_261_DATA 0x00300640 +#define DDRSS_CTL_262_DATA 0x01000200 +#define DDRSS_CTL_263_DATA 0x06400040 +#define DDRSS_CTL_264_DATA 0x00000030 +#define DDRSS_CTL_265_DATA 0x00500003 +#define DDRSS_CTL_266_DATA 0x01000050 +#define DDRSS_CTL_267_DATA 0x03030303 +#define DDRSS_CTL_268_DATA 0x01010000 +#define DDRSS_CTL_269_DATA 0x00000202 +#define DDRSS_CTL_270_DATA 0x00000FFF +#define DDRSS_CTL_271_DATA 0x1FFF1000 +#define DDRSS_CTL_272_DATA 0x01FF0000 +#define DDRSS_CTL_273_DATA 0x000101FF +#define DDRSS_CTL_274_DATA 0x0FFF0B00 +#define DDRSS_CTL_275_DATA 0x01010001 +#define DDRSS_CTL_276_DATA 0x01010101 +#define DDRSS_CTL_277_DATA 0x01180101 +#define DDRSS_CTL_278_DATA 0x00030000 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000000 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00040101 +#define DDRSS_CTL_287_DATA 0x04010100 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x03030300 +#define DDRSS_CTL_291_DATA 0x00000101 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00000000 +#define DDRSS_CTL_312_DATA 0x00000000 +#define DDRSS_CTL_313_DATA 0x01000000 +#define DDRSS_CTL_314_DATA 0x00020201 +#define DDRSS_CTL_315_DATA 0x01000101 +#define DDRSS_CTL_316_DATA 0x01010001 +#define DDRSS_CTL_317_DATA 0x00010101 +#define DDRSS_CTL_318_DATA 0x05080803 +#define DDRSS_CTL_319_DATA 0x0C081818 +#define DDRSS_CTL_320_DATA 0x0009030C +#define DDRSS_CTL_321_DATA 0x090B030F +#define DDRSS_CTL_322_DATA 0x090B0306 +#define DDRSS_CTL_323_DATA 0x0B090006 +#define DDRSS_CTL_324_DATA 0x0100000B +#define DDRSS_CTL_325_DATA 0x06030601 +#define DDRSS_CTL_326_DATA 0x00000003 +#define DDRSS_CTL_327_DATA 0x00000000 +#define DDRSS_CTL_328_DATA 0x00010000 +#define DDRSS_CTL_329_DATA 0x00280D00 +#define DDRSS_CTL_330_DATA 0x00000001 +#define DDRSS_CTL_331_DATA 0x00030001 +#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_333_DATA 0x00000000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x01000000 +#define DDRSS_CTL_341_DATA 0x00000001 +#define DDRSS_CTL_342_DATA 0x00010100 +#define DDRSS_CTL_343_DATA 0x03030000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x000556AA +#define DDRSS_CTL_361_DATA 0x000AAAAA +#define DDRSS_CTL_362_DATA 0x000AA955 +#define DDRSS_CTL_363_DATA 0x00055555 +#define DDRSS_CTL_364_DATA 0x000B3133 +#define DDRSS_CTL_365_DATA 0x0004CD33 +#define DDRSS_CTL_366_DATA 0x0004CECC +#define DDRSS_CTL_367_DATA 0x000B32CC +#define DDRSS_CTL_368_DATA 0x00010300 +#define DDRSS_CTL_369_DATA 0x03000100 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00010000 +#define DDRSS_CTL_378_DATA 0x00000404 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x00000000 +#define DDRSS_CTL_384_DATA 0x00000000 +#define DDRSS_CTL_385_DATA 0x00000000 +#define DDRSS_CTL_386_DATA 0x00000000 +#define DDRSS_CTL_387_DATA 0x33331B00 +#define DDRSS_CTL_388_DATA 0x000A0000 +#define DDRSS_CTL_389_DATA 0x0000019C +#define DDRSS_CTL_390_DATA 0x00000200 +#define DDRSS_CTL_391_DATA 0x00000200 +#define DDRSS_CTL_392_DATA 0x00000200 +#define DDRSS_CTL_393_DATA 0x00000200 +#define DDRSS_CTL_394_DATA 0x000004D4 +#define DDRSS_CTL_395_DATA 0x00001018 +#define DDRSS_CTL_396_DATA 0x00000204 +#define DDRSS_CTL_397_DATA 0x000030B0 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00009210 +#define DDRSS_CTL_403_DATA 0x0001E6E0 +#define DDRSS_CTL_404_DATA 0x00000A10 +#define DDRSS_CTL_405_DATA 0x000030B0 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00009210 +#define DDRSS_CTL_411_DATA 0x0001E6E0 +#define DDRSS_CTL_412_DATA 0x02020A10 +#define DDRSS_CTL_413_DATA 0x03030202 +#define DDRSS_CTL_414_DATA 0x00000022 +#define DDRSS_CTL_415_DATA 0x00000000 +#define DDRSS_CTL_416_DATA 0x00000000 +#define DDRSS_CTL_417_DATA 0x00001403 +#define DDRSS_CTL_418_DATA 0x000007D0 +#define DDRSS_CTL_419_DATA 0x00000000 +#define DDRSS_CTL_420_DATA 0x00000000 +#define DDRSS_CTL_421_DATA 0x00030000 +#define DDRSS_CTL_422_DATA 0x0007001F +#define DDRSS_CTL_423_DATA 0x0016002E +#define DDRSS_CTL_424_DATA 0x0016002E +#define DDRSS_CTL_425_DATA 0x00000000 +#define DDRSS_CTL_426_DATA 0x00000000 +#define DDRSS_CTL_427_DATA 0x02000000 +#define DDRSS_CTL_428_DATA 0x01000404 +#define DDRSS_CTL_429_DATA 0x07160716 +#define DDRSS_CTL_430_DATA 0x00000105 +#define DDRSS_CTL_431_DATA 0x00010101 +#define DDRSS_CTL_432_DATA 0x00010101 +#define DDRSS_CTL_433_DATA 0x00010001 +#define DDRSS_CTL_434_DATA 0x00000101 +#define DDRSS_CTL_435_DATA 0x02000201 +#define DDRSS_CTL_436_DATA 0x02010000 +#define DDRSS_CTL_437_DATA 0x00000200 +#define DDRSS_CTL_438_DATA 0x1E060000 +#define DDRSS_CTL_439_DATA 0x0000011E +#define DDRSS_CTL_440_DATA 0xFFFFFFFF +#define DDRSS_CTL_441_DATA 0xFFFFFFFF +#define DDRSS_CTL_442_DATA 0x00000000 +#define DDRSS_CTL_443_DATA 0x00000000 +#define DDRSS_CTL_444_DATA 0x00000000 +#define DDRSS_CTL_445_DATA 0x00000000 +#define DDRSS_CTL_446_DATA 0x00000000 +#define DDRSS_CTL_447_DATA 0x00000000 +#define DDRSS_CTL_448_DATA 0x00000000 +#define DDRSS_CTL_449_DATA 0x00000000 +#define DDRSS_CTL_450_DATA 0x00000000 +#define DDRSS_CTL_451_DATA 0x00000000 +#define DDRSS_CTL_452_DATA 0x00000000 +#define DDRSS_CTL_453_DATA 0x00000000 +#define DDRSS_CTL_454_DATA 0x00000000 +#define DDRSS_CTL_455_DATA 0x00000000 +#define DDRSS_CTL_456_DATA 0x00000000 +#define DDRSS_CTL_457_DATA 0x00000000 +#define DDRSS_CTL_458_DATA 0x00000000 + +#define DDRSS_PI_00_DATA 0x00000B00 +#define DDRSS_PI_01_DATA 0x00000000 +#define DDRSS_PI_02_DATA 0x00000000 +#define DDRSS_PI_03_DATA 0x00000000 +#define DDRSS_PI_04_DATA 0x00000000 +#define DDRSS_PI_05_DATA 0x00000101 +#define DDRSS_PI_06_DATA 0x00640000 +#define DDRSS_PI_07_DATA 0x00000001 +#define DDRSS_PI_08_DATA 0x00000000 +#define DDRSS_PI_09_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000000 +#define DDRSS_PI_12_DATA 0x00000007 +#define DDRSS_PI_13_DATA 0x00010002 +#define DDRSS_PI_14_DATA 0x0800000F +#define DDRSS_PI_15_DATA 0x00000103 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010100 +#define DDRSS_PI_27_DATA 0x00280A00 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00003200 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x000000AA +#define DDRSS_PI_36_DATA 0x00000055 +#define DDRSS_PI_37_DATA 0x000000B5 +#define DDRSS_PI_38_DATA 0x0000004A +#define DDRSS_PI_39_DATA 0x00000056 +#define DDRSS_PI_40_DATA 0x000000A9 +#define DDRSS_PI_41_DATA 0x000000A9 +#define DDRSS_PI_42_DATA 0x000000B5 +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x000F0F00 +#define DDRSS_PI_46_DATA 0x00000019 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x00030000 +#define DDRSS_PI_55_DATA 0x0F000000 +#define DDRSS_PI_56_DATA 0x00000017 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x0A0A140A +#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_62_DATA 0x00020805 +#define DDRSS_PI_63_DATA 0x01000404 +#define DDRSS_PI_64_DATA 0x00000000 +#define DDRSS_PI_65_DATA 0x00000000 +#define DDRSS_PI_66_DATA 0x00000100 +#define DDRSS_PI_67_DATA 0x0001010F +#define DDRSS_PI_68_DATA 0x00340000 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x0000FFFF +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00080100 +#define DDRSS_PI_74_DATA 0x02000200 +#define DDRSS_PI_75_DATA 0x01000100 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x02000200 +#define DDRSS_PI_78_DATA 0x00000200 +#define DDRSS_PI_79_DATA 0x00000000 +#define DDRSS_PI_80_DATA 0x00000000 +#define DDRSS_PI_81_DATA 0x00000000 +#define DDRSS_PI_82_DATA 0x00000000 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000400 +#define DDRSS_PI_92_DATA 0x02010000 +#define DDRSS_PI_93_DATA 0x00080003 +#define DDRSS_PI_94_DATA 0x00080000 +#define DDRSS_PI_95_DATA 0x00000001 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x0000AA00 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x00000000 +#define DDRSS_PI_100_DATA 0x00010000 +#define DDRSS_PI_101_DATA 0x00000000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000008 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000002 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000000 +#define DDRSS_PI_137_DATA 0x0000000A +#define DDRSS_PI_138_DATA 0x00000019 +#define DDRSS_PI_139_DATA 0x00000100 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010001 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00000401 +#define DDRSS_PI_160_DATA 0x00000000 +#define DDRSS_PI_161_DATA 0x00010000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x20200200 +#define DDRSS_PI_164_DATA 0x00000034 +#define DDRSS_PI_165_DATA 0x00000058 +#define DDRSS_PI_166_DATA 0x00020058 +#define DDRSS_PI_167_DATA 0x02000200 +#define DDRSS_PI_168_DATA 0x380E0C04 +#define DDRSS_PI_169_DATA 0x0010380E +#define DDRSS_PI_170_DATA 0x000000CE +#define DDRSS_PI_171_DATA 0x000001C0 +#define DDRSS_PI_172_DATA 0x00001858 +#define DDRSS_PI_173_DATA 0x000001C0 +#define DDRSS_PI_174_DATA 0x04001858 +#define DDRSS_PI_175_DATA 0x01010404 +#define DDRSS_PI_176_DATA 0x00001501 +#define DDRSS_PI_177_DATA 0x00150015 +#define DDRSS_PI_178_DATA 0x01000100 +#define DDRSS_PI_179_DATA 0x00000100 +#define DDRSS_PI_180_DATA 0x00000000 +#define DDRSS_PI_181_DATA 0x01010101 +#define DDRSS_PI_182_DATA 0x00000101 +#define DDRSS_PI_183_DATA 0x00000000 +#define DDRSS_PI_184_DATA 0x00000000 +#define DDRSS_PI_185_DATA 0x10040000 +#define DDRSS_PI_186_DATA 0x0A0A0210 +#define DDRSS_PI_187_DATA 0x00040402 +#define DDRSS_PI_188_DATA 0x000D0035 +#define DDRSS_PI_189_DATA 0x001C0044 +#define DDRSS_PI_190_DATA 0x001C0044 +#define DDRSS_PI_191_DATA 0x01010101 +#define DDRSS_PI_192_DATA 0x0003000E +#define DDRSS_PI_193_DATA 0x00030190 +#define DDRSS_PI_194_DATA 0x01000190 +#define DDRSS_PI_195_DATA 0x000F000F +#define DDRSS_PI_196_DATA 0x01910100 +#define DDRSS_PI_197_DATA 0x01000191 +#define DDRSS_PI_198_DATA 0x01910191 +#define DDRSS_PI_199_DATA 0x32103200 +#define DDRSS_PI_200_DATA 0x01013210 +#define DDRSS_PI_201_DATA 0x0A070601 +#define DDRSS_PI_202_DATA 0x180F090D +#define DDRSS_PI_203_DATA 0x180F0911 +#define DDRSS_PI_204_DATA 0x0000C011 +#define DDRSS_PI_205_DATA 0x00C01000 +#define DDRSS_PI_206_DATA 0x00C01000 +#define DDRSS_PI_207_DATA 0x00021000 +#define DDRSS_PI_208_DATA 0x001E000E +#define DDRSS_PI_209_DATA 0x001E0190 +#define DDRSS_PI_210_DATA 0x00110190 +#define DDRSS_PI_211_DATA 0x32000056 +#define DDRSS_PI_212_DATA 0x00000301 +#define DDRSS_PI_213_DATA 0x005A0030 +#define DDRSS_PI_214_DATA 0x03013212 +#define DDRSS_PI_215_DATA 0x00003000 +#define DDRSS_PI_216_DATA 0x3212005A +#define DDRSS_PI_217_DATA 0x09000301 +#define DDRSS_PI_218_DATA 0x04010504 +#define DDRSS_PI_219_DATA 0x040006C9 +#define DDRSS_PI_220_DATA 0x0A032001 +#define DDRSS_PI_221_DATA 0x21250D0A +#define DDRSS_PI_222_DATA 0x00002216 +#define DDRSS_PI_223_DATA 0x4800C570 +#define DDRSS_PI_224_DATA 0x17182006 +#define DDRSS_PI_225_DATA 0x21250D10 +#define DDRSS_PI_226_DATA 0x00002216 +#define DDRSS_PI_227_DATA 0x4800C570 +#define DDRSS_PI_228_DATA 0x17182006 +#define DDRSS_PI_229_DATA 0x00019C10 +#define DDRSS_PI_230_DATA 0x00001018 +#define DDRSS_PI_231_DATA 0x000030B0 +#define DDRSS_PI_232_DATA 0x0001E6E0 +#define DDRSS_PI_233_DATA 0x000030B0 +#define DDRSS_PI_234_DATA 0x0001E6E0 +#define DDRSS_PI_235_DATA 0x01CC0010 +#define DDRSS_PI_236_DATA 0x030301CC +#define DDRSS_PI_237_DATA 0x002AF803 +#define DDRSS_PI_238_DATA 0x0001ADAF +#define DDRSS_PI_239_DATA 0x00000005 +#define DDRSS_PI_240_DATA 0x0000006E +#define DDRSS_PI_241_DATA 0x00000010 +#define DDRSS_PI_242_DATA 0x0004E200 +#define DDRSS_PI_243_DATA 0x0001ADAF +#define DDRSS_PI_244_DATA 0x00000005 +#define DDRSS_PI_245_DATA 0x00000C80 +#define DDRSS_PI_246_DATA 0x000001CC +#define DDRSS_PI_247_DATA 0x0004E200 +#define DDRSS_PI_248_DATA 0x0001ADAF +#define DDRSS_PI_249_DATA 0x00000005 +#define DDRSS_PI_250_DATA 0x00000C80 +#define DDRSS_PI_251_DATA 0x010001CC +#define DDRSS_PI_252_DATA 0x00370040 +#define DDRSS_PI_253_DATA 0x00010008 +#define DDRSS_PI_254_DATA 0x06400040 +#define DDRSS_PI_255_DATA 0x00010030 +#define DDRSS_PI_256_DATA 0x06400040 +#define DDRSS_PI_257_DATA 0x00000330 +#define DDRSS_PI_258_DATA 0x00500050 +#define DDRSS_PI_259_DATA 0x08040404 +#define DDRSS_PI_260_DATA 0x00000055 +#define DDRSS_PI_261_DATA 0x55083C5A +#define DDRSS_PI_262_DATA 0x5A000000 +#define DDRSS_PI_263_DATA 0x0055083C +#define DDRSS_PI_264_DATA 0x3C5A0000 +#define DDRSS_PI_265_DATA 0x00005508 +#define DDRSS_PI_266_DATA 0x0C3C5A00 +#define DDRSS_PI_267_DATA 0x080F0E0D +#define DDRSS_PI_268_DATA 0x000B0A09 +#define DDRSS_PI_269_DATA 0x00030201 +#define DDRSS_PI_270_DATA 0x01000000 +#define DDRSS_PI_271_DATA 0x04020201 +#define DDRSS_PI_272_DATA 0x00080804 +#define DDRSS_PI_273_DATA 0x00000000 +#define DDRSS_PI_274_DATA 0x00000000 +#define DDRSS_PI_275_DATA 0x45AB0084 +#define DDRSS_PI_276_DATA 0x001D0F27 +#define DDRSS_PI_277_DATA 0x45AB2DD4 +#define DDRSS_PI_278_DATA 0x001D0F27 +#define DDRSS_PI_279_DATA 0x45AB2DD4 +#define DDRSS_PI_280_DATA 0x001D0F27 +#define DDRSS_PI_281_DATA 0x45AB0084 +#define DDRSS_PI_282_DATA 0x001D0F27 +#define DDRSS_PI_283_DATA 0x45AB2DD4 +#define DDRSS_PI_284_DATA 0x001D0F27 +#define DDRSS_PI_285_DATA 0x45AB2DD4 +#define DDRSS_PI_286_DATA 0x001D0F27 +#define DDRSS_PI_287_DATA 0x45AB0084 +#define DDRSS_PI_288_DATA 0x001D0F27 +#define DDRSS_PI_289_DATA 0x45AB2DD4 +#define DDRSS_PI_290_DATA 0x001D0F27 +#define DDRSS_PI_291_DATA 0x45AB2DD4 +#define DDRSS_PI_292_DATA 0x001D0F27 +#define DDRSS_PI_293_DATA 0x45AB0084 +#define DDRSS_PI_294_DATA 0x001D0F27 +#define DDRSS_PI_295_DATA 0x45AB2DD4 +#define DDRSS_PI_296_DATA 0x001D0F27 +#define DDRSS_PI_297_DATA 0x45AB2DD4 +#define DDRSS_PI_298_DATA 0x001D0F27 +#define DDRSS_PI_299_DATA 0x00000000 + +#define DDRSS_PHY_00_DATA 0x000004F0 +#define DDRSS_PHY_01_DATA 0x00000000 +#define DDRSS_PHY_02_DATA 0x00030200 +#define DDRSS_PHY_03_DATA 0x00000000 +#define DDRSS_PHY_04_DATA 0x00000000 +#define DDRSS_PHY_05_DATA 0x01030000 +#define DDRSS_PHY_06_DATA 0x00010000 +#define DDRSS_PHY_07_DATA 0x01030004 +#define DDRSS_PHY_08_DATA 0x01000000 +#define DDRSS_PHY_09_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x01000001 +#define DDRSS_PHY_12_DATA 0x00000100 +#define DDRSS_PHY_13_DATA 0x000800C0 +#define DDRSS_PHY_14_DATA 0x060100CC +#define DDRSS_PHY_15_DATA 0x00030066 +#define DDRSS_PHY_16_DATA 0x00000000 +#define DDRSS_PHY_17_DATA 0x00000301 +#define DDRSS_PHY_18_DATA 0x0000AAAA +#define DDRSS_PHY_19_DATA 0x00005555 +#define DDRSS_PHY_20_DATA 0x0000B5B5 +#define DDRSS_PHY_21_DATA 0x00004A4A +#define DDRSS_PHY_22_DATA 0x00005656 +#define DDRSS_PHY_23_DATA 0x0000A9A9 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B5B5 +#define DDRSS_PHY_26_DATA 0x00000000 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x2A000000 +#define DDRSS_PHY_29_DATA 0x00000808 +#define DDRSS_PHY_30_DATA 0x0F000000 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x10400000 +#define DDRSS_PHY_33_DATA 0x0C002006 +#define DDRSS_PHY_34_DATA 0x00000000 +#define DDRSS_PHY_35_DATA 0x00000000 +#define DDRSS_PHY_36_DATA 0x55555555 +#define DDRSS_PHY_37_DATA 0xAAAAAAAA +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x00005555 +#define DDRSS_PHY_41_DATA 0x01000100 +#define DDRSS_PHY_42_DATA 0x00800180 +#define DDRSS_PHY_43_DATA 0x00000001 +#define DDRSS_PHY_44_DATA 0x00000000 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000104 +#define DDRSS_PHY_67_DATA 0x00000120 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x00000000 +#define DDRSS_PHY_75_DATA 0x00000001 +#define DDRSS_PHY_76_DATA 0x07FF0000 +#define DDRSS_PHY_77_DATA 0x0080081F +#define DDRSS_PHY_78_DATA 0x00081020 +#define DDRSS_PHY_79_DATA 0x04010000 +#define DDRSS_PHY_80_DATA 0x00000000 +#define DDRSS_PHY_81_DATA 0x00000000 +#define DDRSS_PHY_82_DATA 0x00000000 +#define DDRSS_PHY_83_DATA 0x00000100 +#define DDRSS_PHY_84_DATA 0x01BB0B01 +#define DDRSS_PHY_85_DATA 0x1003BB0B +#define DDRSS_PHY_86_DATA 0x20000140 +#define DDRSS_PHY_87_DATA 0x07FF0200 +#define DDRSS_PHY_88_DATA 0x0000DD01 +#define DDRSS_PHY_89_DATA 0x10100303 +#define DDRSS_PHY_90_DATA 0x10101010 +#define DDRSS_PHY_91_DATA 0x10101010 +#define DDRSS_PHY_92_DATA 0x00021010 +#define DDRSS_PHY_93_DATA 0x00100010 +#define DDRSS_PHY_94_DATA 0x00100010 +#define DDRSS_PHY_95_DATA 0x00100010 +#define DDRSS_PHY_96_DATA 0x00100010 +#define DDRSS_PHY_97_DATA 0x00050010 +#define DDRSS_PHY_98_DATA 0x51517041 +#define DDRSS_PHY_99_DATA 0x31C06000 +#define DDRSS_PHY_100_DATA 0x07AB0340 +#define DDRSS_PHY_101_DATA 0x00C0C001 +#define DDRSS_PHY_102_DATA 0x0B0A0001 +#define DDRSS_PHY_103_DATA 0x10001000 +#define DDRSS_PHY_104_DATA 0x0C073E42 +#define DDRSS_PHY_105_DATA 0x0F0C2D01 +#define DDRSS_PHY_106_DATA 0x01000140 +#define DDRSS_PHY_107_DATA 0x0C000420 +#define DDRSS_PHY_108_DATA 0x00000198 +#define DDRSS_PHY_109_DATA 0x0A0000D0 +#define DDRSS_PHY_110_DATA 0x00030200 +#define DDRSS_PHY_111_DATA 0x02800000 +#define DDRSS_PHY_112_DATA 0x80800000 +#define DDRSS_PHY_113_DATA 0x000B2010 +#define DDRSS_PHY_114_DATA 0x76543210 +#define DDRSS_PHY_115_DATA 0x00000008 +#define DDRSS_PHY_116_DATA 0x02800280 +#define DDRSS_PHY_117_DATA 0x02800280 +#define DDRSS_PHY_118_DATA 0x02800280 +#define DDRSS_PHY_119_DATA 0x02800280 +#define DDRSS_PHY_120_DATA 0x00000280 +#define DDRSS_PHY_121_DATA 0x0000A000 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00A000A0 +#define DDRSS_PHY_128_DATA 0x00A000A0 +#define DDRSS_PHY_129_DATA 0x00A000A0 +#define DDRSS_PHY_130_DATA 0x011900A0 +#define DDRSS_PHY_131_DATA 0x01A00004 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00080200 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x20202000 +#define DDRSS_PHY_137_DATA 0x20202020 +#define DDRSS_PHY_138_DATA 0xF0F02020 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x000004F0 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x01000001 +#define DDRSS_PHY_268_DATA 0x00000100 +#define DDRSS_PHY_269_DATA 0x000800C0 +#define DDRSS_PHY_270_DATA 0x060100CC +#define DDRSS_PHY_271_DATA 0x00030066 +#define DDRSS_PHY_272_DATA 0x00000000 +#define DDRSS_PHY_273_DATA 0x00000301 +#define DDRSS_PHY_274_DATA 0x0000AAAA +#define DDRSS_PHY_275_DATA 0x00005555 +#define DDRSS_PHY_276_DATA 0x0000B5B5 +#define DDRSS_PHY_277_DATA 0x00004A4A +#define DDRSS_PHY_278_DATA 0x00005656 +#define DDRSS_PHY_279_DATA 0x0000A9A9 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B5B5 +#define DDRSS_PHY_282_DATA 0x00000000 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x2A000000 +#define DDRSS_PHY_285_DATA 0x00000808 +#define DDRSS_PHY_286_DATA 0x0F000000 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x10400000 +#define DDRSS_PHY_289_DATA 0x0C002006 +#define DDRSS_PHY_290_DATA 0x00000000 +#define DDRSS_PHY_291_DATA 0x00000000 +#define DDRSS_PHY_292_DATA 0x55555555 +#define DDRSS_PHY_293_DATA 0xAAAAAAAA +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x00005555 +#define DDRSS_PHY_297_DATA 0x01000100 +#define DDRSS_PHY_298_DATA 0x00800180 +#define DDRSS_PHY_299_DATA 0x00000000 +#define DDRSS_PHY_300_DATA 0x00000000 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000104 +#define DDRSS_PHY_323_DATA 0x00000120 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x00000000 +#define DDRSS_PHY_331_DATA 0x00000001 +#define DDRSS_PHY_332_DATA 0x07FF0000 +#define DDRSS_PHY_333_DATA 0x0080081F +#define DDRSS_PHY_334_DATA 0x00081020 +#define DDRSS_PHY_335_DATA 0x04010000 +#define DDRSS_PHY_336_DATA 0x00000000 +#define DDRSS_PHY_337_DATA 0x00000000 +#define DDRSS_PHY_338_DATA 0x00000000 +#define DDRSS_PHY_339_DATA 0x00000100 +#define DDRSS_PHY_340_DATA 0x01BB0B01 +#define DDRSS_PHY_341_DATA 0x1003BB0B +#define DDRSS_PHY_342_DATA 0x20000140 +#define DDRSS_PHY_343_DATA 0x07FF0200 +#define DDRSS_PHY_344_DATA 0x0000DD01 +#define DDRSS_PHY_345_DATA 0x10100303 +#define DDRSS_PHY_346_DATA 0x10101010 +#define DDRSS_PHY_347_DATA 0x10101010 +#define DDRSS_PHY_348_DATA 0x00021010 +#define DDRSS_PHY_349_DATA 0x00100010 +#define DDRSS_PHY_350_DATA 0x00100010 +#define DDRSS_PHY_351_DATA 0x00100010 +#define DDRSS_PHY_352_DATA 0x00100010 +#define DDRSS_PHY_353_DATA 0x00050010 +#define DDRSS_PHY_354_DATA 0x51517041 +#define DDRSS_PHY_355_DATA 0x31C06000 +#define DDRSS_PHY_356_DATA 0x07AB0340 +#define DDRSS_PHY_357_DATA 0x00C0C001 +#define DDRSS_PHY_358_DATA 0x0B0A0001 +#define DDRSS_PHY_359_DATA 0x10001000 +#define DDRSS_PHY_360_DATA 0x0C073E42 +#define DDRSS_PHY_361_DATA 0x0F0C2D01 +#define DDRSS_PHY_362_DATA 0x01000140 +#define DDRSS_PHY_363_DATA 0x0C000420 +#define DDRSS_PHY_364_DATA 0x00000198 +#define DDRSS_PHY_365_DATA 0x0A0000D0 +#define DDRSS_PHY_366_DATA 0x00030200 +#define DDRSS_PHY_367_DATA 0x02800000 +#define DDRSS_PHY_368_DATA 0x80800000 +#define DDRSS_PHY_369_DATA 0x000B2010 +#define DDRSS_PHY_370_DATA 0x76543210 +#define DDRSS_PHY_371_DATA 0x00000008 +#define DDRSS_PHY_372_DATA 0x02800280 +#define DDRSS_PHY_373_DATA 0x02800280 +#define DDRSS_PHY_374_DATA 0x02800280 +#define DDRSS_PHY_375_DATA 0x02800280 +#define DDRSS_PHY_376_DATA 0x00000280 +#define DDRSS_PHY_377_DATA 0x0000A000 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00A000A0 +#define DDRSS_PHY_384_DATA 0x00A000A0 +#define DDRSS_PHY_385_DATA 0x00A000A0 +#define DDRSS_PHY_386_DATA 0x011900A0 +#define DDRSS_PHY_387_DATA 0x01A00004 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00080200 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x20202000 +#define DDRSS_PHY_393_DATA 0x20202020 +#define DDRSS_PHY_394_DATA 0xF0F02020 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x000004F0 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x01000001 +#define DDRSS_PHY_524_DATA 0x00000100 +#define DDRSS_PHY_525_DATA 0x000800C0 +#define DDRSS_PHY_526_DATA 0x060100CC +#define DDRSS_PHY_527_DATA 0x00030066 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000301 +#define DDRSS_PHY_530_DATA 0x0000AAAA +#define DDRSS_PHY_531_DATA 0x00005555 +#define DDRSS_PHY_532_DATA 0x0000B5B5 +#define DDRSS_PHY_533_DATA 0x00004A4A +#define DDRSS_PHY_534_DATA 0x00005656 +#define DDRSS_PHY_535_DATA 0x0000A9A9 +#define DDRSS_PHY_536_DATA 0x0000A9A9 +#define DDRSS_PHY_537_DATA 0x0000B5B5 +#define DDRSS_PHY_538_DATA 0x00000000 +#define DDRSS_PHY_539_DATA 0x00000000 +#define DDRSS_PHY_540_DATA 0x2A000000 +#define DDRSS_PHY_541_DATA 0x00000808 +#define DDRSS_PHY_542_DATA 0x0F000000 +#define DDRSS_PHY_543_DATA 0x00000F0F +#define DDRSS_PHY_544_DATA 0x10400000 +#define DDRSS_PHY_545_DATA 0x0C002006 +#define DDRSS_PHY_546_DATA 0x00000000 +#define DDRSS_PHY_547_DATA 0x00000000 +#define DDRSS_PHY_548_DATA 0x55555555 +#define DDRSS_PHY_549_DATA 0xAAAAAAAA +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x00005555 +#define DDRSS_PHY_553_DATA 0x01000100 +#define DDRSS_PHY_554_DATA 0x00800180 +#define DDRSS_PHY_555_DATA 0x00000001 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000104 +#define DDRSS_PHY_579_DATA 0x00000120 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000001 +#define DDRSS_PHY_588_DATA 0x07FF0000 +#define DDRSS_PHY_589_DATA 0x0080081F +#define DDRSS_PHY_590_DATA 0x00081020 +#define DDRSS_PHY_591_DATA 0x04010000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000100 +#define DDRSS_PHY_596_DATA 0x01BB0B01 +#define DDRSS_PHY_597_DATA 0x1003BB0B +#define DDRSS_PHY_598_DATA 0x20000140 +#define DDRSS_PHY_599_DATA 0x07FF0200 +#define DDRSS_PHY_600_DATA 0x0000DD01 +#define DDRSS_PHY_601_DATA 0x10100303 +#define DDRSS_PHY_602_DATA 0x10101010 +#define DDRSS_PHY_603_DATA 0x10101010 +#define DDRSS_PHY_604_DATA 0x00021010 +#define DDRSS_PHY_605_DATA 0x00100010 +#define DDRSS_PHY_606_DATA 0x00100010 +#define DDRSS_PHY_607_DATA 0x00100010 +#define DDRSS_PHY_608_DATA 0x00100010 +#define DDRSS_PHY_609_DATA 0x00050010 +#define DDRSS_PHY_610_DATA 0x51517041 +#define DDRSS_PHY_611_DATA 0x31C06000 +#define DDRSS_PHY_612_DATA 0x07AB0340 +#define DDRSS_PHY_613_DATA 0x00C0C001 +#define DDRSS_PHY_614_DATA 0x0B0A0001 +#define DDRSS_PHY_615_DATA 0x10001000 +#define DDRSS_PHY_616_DATA 0x0C073E42 +#define DDRSS_PHY_617_DATA 0x0F0C2D01 +#define DDRSS_PHY_618_DATA 0x01000140 +#define DDRSS_PHY_619_DATA 0x0C000420 +#define DDRSS_PHY_620_DATA 0x00000198 +#define DDRSS_PHY_621_DATA 0x0A0000D0 +#define DDRSS_PHY_622_DATA 0x00030200 +#define DDRSS_PHY_623_DATA 0x02800000 +#define DDRSS_PHY_624_DATA 0x80800000 +#define DDRSS_PHY_625_DATA 0x000B2010 +#define DDRSS_PHY_626_DATA 0x76543210 +#define DDRSS_PHY_627_DATA 0x00000008 +#define DDRSS_PHY_628_DATA 0x02800280 +#define DDRSS_PHY_629_DATA 0x02800280 +#define DDRSS_PHY_630_DATA 0x02800280 +#define DDRSS_PHY_631_DATA 0x02800280 +#define DDRSS_PHY_632_DATA 0x00000280 +#define DDRSS_PHY_633_DATA 0x0000A000 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00A000A0 +#define DDRSS_PHY_640_DATA 0x00A000A0 +#define DDRSS_PHY_641_DATA 0x00A000A0 +#define DDRSS_PHY_642_DATA 0x011900A0 +#define DDRSS_PHY_643_DATA 0x01A00004 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00080200 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x20202000 +#define DDRSS_PHY_649_DATA 0x20202020 +#define DDRSS_PHY_650_DATA 0xF0F02020 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x000004F0 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x01000001 +#define DDRSS_PHY_780_DATA 0x00000100 +#define DDRSS_PHY_781_DATA 0x000800C0 +#define DDRSS_PHY_782_DATA 0x060100CC +#define DDRSS_PHY_783_DATA 0x00030066 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000301 +#define DDRSS_PHY_786_DATA 0x0000AAAA +#define DDRSS_PHY_787_DATA 0x00005555 +#define DDRSS_PHY_788_DATA 0x0000B5B5 +#define DDRSS_PHY_789_DATA 0x00004A4A +#define DDRSS_PHY_790_DATA 0x00005656 +#define DDRSS_PHY_791_DATA 0x0000A9A9 +#define DDRSS_PHY_792_DATA 0x0000A9A9 +#define DDRSS_PHY_793_DATA 0x0000B5B5 +#define DDRSS_PHY_794_DATA 0x00000000 +#define DDRSS_PHY_795_DATA 0x00000000 +#define DDRSS_PHY_796_DATA 0x2A000000 +#define DDRSS_PHY_797_DATA 0x00000808 +#define DDRSS_PHY_798_DATA 0x0F000000 +#define DDRSS_PHY_799_DATA 0x00000F0F +#define DDRSS_PHY_800_DATA 0x10400000 +#define DDRSS_PHY_801_DATA 0x0C002006 +#define DDRSS_PHY_802_DATA 0x00000000 +#define DDRSS_PHY_803_DATA 0x00000000 +#define DDRSS_PHY_804_DATA 0x55555555 +#define DDRSS_PHY_805_DATA 0xAAAAAAAA +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x00005555 +#define DDRSS_PHY_809_DATA 0x01000100 +#define DDRSS_PHY_810_DATA 0x00800180 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000104 +#define DDRSS_PHY_835_DATA 0x00000120 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000001 +#define DDRSS_PHY_844_DATA 0x07FF0000 +#define DDRSS_PHY_845_DATA 0x0080081F +#define DDRSS_PHY_846_DATA 0x00081020 +#define DDRSS_PHY_847_DATA 0x04010000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000100 +#define DDRSS_PHY_852_DATA 0x01BB0B01 +#define DDRSS_PHY_853_DATA 0x1003BB0B +#define DDRSS_PHY_854_DATA 0x20000140 +#define DDRSS_PHY_855_DATA 0x07FF0200 +#define DDRSS_PHY_856_DATA 0x0000DD01 +#define DDRSS_PHY_857_DATA 0x10100303 +#define DDRSS_PHY_858_DATA 0x10101010 +#define DDRSS_PHY_859_DATA 0x10101010 +#define DDRSS_PHY_860_DATA 0x00021010 +#define DDRSS_PHY_861_DATA 0x00100010 +#define DDRSS_PHY_862_DATA 0x00100010 +#define DDRSS_PHY_863_DATA 0x00100010 +#define DDRSS_PHY_864_DATA 0x00100010 +#define DDRSS_PHY_865_DATA 0x00050010 +#define DDRSS_PHY_866_DATA 0x51517041 +#define DDRSS_PHY_867_DATA 0x31C06000 +#define DDRSS_PHY_868_DATA 0x07AB0340 +#define DDRSS_PHY_869_DATA 0x00C0C001 +#define DDRSS_PHY_870_DATA 0x0B0A0001 +#define DDRSS_PHY_871_DATA 0x10001000 +#define DDRSS_PHY_872_DATA 0x0C073E42 +#define DDRSS_PHY_873_DATA 0x0F0C2D01 +#define DDRSS_PHY_874_DATA 0x01000140 +#define DDRSS_PHY_875_DATA 0x0C000420 +#define DDRSS_PHY_876_DATA 0x00000198 +#define DDRSS_PHY_877_DATA 0x0A0000D0 +#define DDRSS_PHY_878_DATA 0x00030200 +#define DDRSS_PHY_879_DATA 0x02800000 +#define DDRSS_PHY_880_DATA 0x80800000 +#define DDRSS_PHY_881_DATA 0x000B2010 +#define DDRSS_PHY_882_DATA 0x76543210 +#define DDRSS_PHY_883_DATA 0x00000008 +#define DDRSS_PHY_884_DATA 0x02800280 +#define DDRSS_PHY_885_DATA 0x02800280 +#define DDRSS_PHY_886_DATA 0x02800280 +#define DDRSS_PHY_887_DATA 0x02800280 +#define DDRSS_PHY_888_DATA 0x00000280 +#define DDRSS_PHY_889_DATA 0x0000A000 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00A000A0 +#define DDRSS_PHY_896_DATA 0x00A000A0 +#define DDRSS_PHY_897_DATA 0x00A000A0 +#define DDRSS_PHY_898_DATA 0x011900A0 +#define DDRSS_PHY_899_DATA 0x01A00004 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00080200 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x20202000 +#define DDRSS_PHY_905_DATA 0x20202020 +#define DDRSS_PHY_906_DATA 0xF0F02020 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x00543210 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x00000000 +#define DDRSS_PHY_1062_DATA 0x00000000 +#define DDRSS_PHY_1063_DATA 0x00000000 +#define DDRSS_PHY_1064_DATA 0x000305FF +#define DDRSS_PHY_1065_DATA 0x00030000 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x00000300 +#define DDRSS_PHY_1069_DATA 0x00000300 +#define DDRSS_PHY_1070_DATA 0x00000300 +#define DDRSS_PHY_1071_DATA 0x42080010 +#define DDRSS_PHY_1072_DATA 0x0000803E +#define DDRSS_PHY_1073_DATA 0x00000001 +#define DDRSS_PHY_1074_DATA 0x01000102 +#define DDRSS_PHY_1075_DATA 0x00008000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00010100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00050000 +#define DDRSS_PHY_1285_DATA 0x04000000 +#define DDRSS_PHY_1286_DATA 0x00000055 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00002001 +#define DDRSS_PHY_1292_DATA 0x0000400F +#define DDRSS_PHY_1293_DATA 0x50020028 +#define DDRSS_PHY_1294_DATA 0x01010000 +#define DDRSS_PHY_1295_DATA 0x80080001 +#define DDRSS_PHY_1296_DATA 0x10200000 +#define DDRSS_PHY_1297_DATA 0x00000008 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x01090E00 +#define DDRSS_PHY_1300_DATA 0x00040101 +#define DDRSS_PHY_1301_DATA 0x0000010F +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x0000FFFF +#define DDRSS_PHY_1304_DATA 0x00000000 +#define DDRSS_PHY_1305_DATA 0x01010000 +#define DDRSS_PHY_1306_DATA 0x01080402 +#define DDRSS_PHY_1307_DATA 0x01200F02 +#define DDRSS_PHY_1308_DATA 0x00194280 +#define DDRSS_PHY_1309_DATA 0x00000004 +#define DDRSS_PHY_1310_DATA 0x00052000 +#define DDRSS_PHY_1311_DATA 0x00000000 +#define DDRSS_PHY_1312_DATA 0x00000000 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x01000000 +#define DDRSS_PHY_1318_DATA 0x00000705 +#define DDRSS_PHY_1319_DATA 0x00000054 +#define DDRSS_PHY_1320_DATA 0x00030820 +#define DDRSS_PHY_1321_DATA 0x00010820 +#define DDRSS_PHY_1322_DATA 0x00010820 +#define DDRSS_PHY_1323_DATA 0x00010820 +#define DDRSS_PHY_1324_DATA 0x00010820 +#define DDRSS_PHY_1325_DATA 0x00010820 +#define DDRSS_PHY_1326_DATA 0x00010820 +#define DDRSS_PHY_1327_DATA 0x00010820 +#define DDRSS_PHY_1328_DATA 0x00010820 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000074 +#define DDRSS_PHY_1331_DATA 0x00000400 +#define DDRSS_PHY_1332_DATA 0x00000108 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x03000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x04102006 +#define DDRSS_PHY_1343_DATA 0x00041020 +#define DDRSS_PHY_1344_DATA 0x01C98C98 +#define DDRSS_PHY_1345_DATA 0x3F400000 +#define DDRSS_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS_PHY_1347_DATA 0x0000001F +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00010000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x76543210 +#define DDRSS_PHY_1357_DATA 0x00010198 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00040700 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000002 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00080000 +#define DDRSS_PHY_1375_DATA 0x000007FF +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x000FFFFF +#define DDRSS_PHY_1383_DATA 0x000FFFFF +#define DDRSS_PHY_1384_DATA 0x0000FFFF +#define DDRSS_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS_PHY_1386_DATA 0x030FFFFF +#define DDRSS_PHY_1387_DATA 0x01FFFFFF +#define DDRSS_PHY_1388_DATA 0x0000FFFF +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x0001F7C0 +#define DDRSS_PHY_1394_DATA 0x00000003 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00001142 +#define DDRSS_PHY_1397_DATA 0x010207AB +#define DDRSS_PHY_1398_DATA 0x01000080 +#define DDRSS_PHY_1399_DATA 0x03900390 +#define DDRSS_PHY_1400_DATA 0x03900390 +#define DDRSS_PHY_1401_DATA 0x00000390 +#define DDRSS_PHY_1402_DATA 0x00000390 +#define DDRSS_PHY_1403_DATA 0x00000390 +#define DDRSS_PHY_1404_DATA 0x00000390 +#define DDRSS_PHY_1405_DATA 0x00000005 +#define DDRSS_PHY_1406_DATA 0x01813FFF +#define DDRSS_PHY_1407_DATA 0x000000FF +#define DDRSS_PHY_1408_DATA 0x0C000DFF +#define DDRSS_PHY_1409_DATA 0x30000DFF +#define DDRSS_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS_PHY_1411_DATA 0x000100F0 +#define DDRSS_PHY_1412_DATA 0x780DFFFF +#define DDRSS_PHY_1413_DATA 0x00007E31 +#define DDRSS_PHY_1414_DATA 0x000CBF11 +#define DDRSS_PHY_1415_DATA 0x01FF0010 +#define DDRSS_PHY_1416_DATA 0x000CBF11 +#define DDRSS_PHY_1417_DATA 0x01FF0010 +#define DDRSS_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS_PHY_1419_DATA 0x01FF00F0 +#define DDRSS_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS_PHY_1421_DATA 0x01FF00F0 +#define DDRSS_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index f6c7e161452..746b9f8b1c6 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -181,7 +181,7 @@ }; main_navss: bus@30000000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index 05d6ef127ba..f7ab7719fc0 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -440,7 +440,7 @@ }; mcu_navss: bus@28380000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; @@ -671,4 +671,11 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts new file mode 100644 index 00000000000..43da4dafba8 --- /dev/null +++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleboard.org/ai-64 + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +#include "k3-j721e-beagleboneai64.dts" +#include "k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi" +#include "k3-j721e-ddr.dtsi" + +#include "k3-j721e-beagleboneai64-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + chosen { + tick-timer = &mcu_timer0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; + assigned-clock-rates = <2000000000>, <200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_mcu 6>, + <&secure_proxy_mcu 8>, + <&secure_proxy_mcu 5>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&mcu_timer0 { + status = "okay"; + bootph-pre-ram; +}; + +&secure_proxy_mcu { + bootph-pre-ram; + /* We require this for boot handshake */ + status = "okay"; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx"; + bootph-pre-ram; + }; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; + +&wkup_uart0_pins_default { + bootph-pre-ram; +}; + +&wkup_i2c0 { + bootph-pre-ram; +}; + +&binman { + tiboot3-j721e-gp-evm.bin { + filename = "tiboot3-j721e-gp-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_unsigned>; + core = "public"; + load = <CONFIG_SPL_TEXT_BASE>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + }; + u_boot_spl_unsigned: u-boot-spl { + no-expanded; + }; + }; + + sysfw_gp { + filename = "sysfw.bin_gp"; + ti-secure-rom { + content = <&ti_fs>; + core = "secure"; + load = <0x40000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + }; + ti_fs: ti-fs.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + + itb_gp { + filename = "sysfw-j721e-gp-evm.itb"; + symlink = "sysfw.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_gp"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "board-cfg.bin"; + }; + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "pm-cfg.bin"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "rm-cfg.bin"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sec-cfg.bin"; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 5bca4e94ecf..f17dd8e04cf 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -141,11 +141,9 @@ #ifdef CONFIG_TARGET_J721S2_A72_EVM -#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" #define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb" #define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb" -#define UBOOT_NODTB "u-boot-nodtb.bin" #define J721S2_EVM_DTB "u-boot.dtb" #define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb" @@ -157,81 +155,20 @@ }; }; ti-spl { - filename = "tispl.bin"; - pad-byte = <0xff>; + insert-template = <&ti_spl_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - ti-secure { - content = <&atf>; - keyfile = "custMpk.pem"; - }; - atf: atf-bl31 { - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - ti-secure { - content = <&tee>; - keyfile = "custMpk.pem"; - }; - tee: tee-os { - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; ti-secure { content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - ti-secure { - content = <&u_boot_spl_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_spl_nodtb: blob-ext { - filename = SPL_NODTB; - }; - }; - fdt-0 { description = "k3-j721s2-common-proc-board"; type = "flat_dt"; @@ -285,29 +222,12 @@ &binman { u-boot { - filename = "u-boot.img"; - pad-byte = <0xff>; + insert-template = <&u_boot_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for J721S2 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - ti-secure { - content = <&u_boot_nodtb>; - keyfile = "custMpk.pem"; - }; - u_boot_nodtb: u-boot-nodtb { - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for J721S2 Board"; }; fdt-0 { @@ -371,67 +291,16 @@ &binman { ti-spl_unsigned { - filename = "tispl.bin_unsigned"; - pad-byte = <0xff>; + insert-template = <&ti_spl_unsigned_template>; fit { - description = "Configuration to load ATF and SPL"; - #address-cells = <1>; - images { - - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - os = "arm-trusted-firmware"; - load = <CONFIG_K3_ATF_LOAD_ADDR>; - entry = <CONFIG_K3_ATF_LOAD_ADDR>; - atf-bl31 { - filename = "bl31.bin"; - }; - }; - - tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <0x9e800000>; - entry = <0x9e800000>; - tee-os { - filename = "tee-raw.bin"; - }; - }; - dm { - description = "DM binary"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "DM"; - load = <0x89000000>; - entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; - spl { - description = "SPL (64-bit)"; - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_SPL_TEXT_BASE>; - entry = <CONFIG_SPL_TEXT_BASE>; - blob { - filename = "spl/u-boot-spl-nodtb.bin"; - }; - }; - fdt-0 { description = "k3-j721s2-common-proc-board"; type = "flat_dt"; @@ -475,26 +344,12 @@ &binman { u-boot_unsigned { - filename = "u-boot.img_unsigned"; - pad-byte = <0xff>; + insert-template = <&u_boot_unsigned_template>; fit { - description = "FIT image with multiple configurations"; - images { uboot { - description = "U-Boot for J721S2 board"; - type = "firmware"; - os = "u-boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - blob { - filename = UBOOT_NODTB; - }; - hash { - algo = "crc32"; - }; + description = "U-Boot for J721S2 Board"; }; fdt-0 { diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index 084f8f5b669..b03731b53a2 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -775,7 +775,7 @@ }; main_navss: bus@30000000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; @@ -807,6 +807,7 @@ ti,sci = <&sms>; ti,sci-dev-id = <265>; ti,interrupt-ranges = <0 0 256>; + ti,unmapped-event-sources = <&main_bcdma_csi>; }; secure_proxy_main: mailbox@32c00000 { @@ -1103,6 +1104,22 @@ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + main_bcdma_csi: dma-controller@311a0000 { + compatible = "ti,j721s2-dmss-bcdma-csi"; + reg = <0x00 0x311a0000 0x00 0x100>, + <0x00 0x35d00000 0x00 0x20000>, + <0x00 0x35c00000 0x00 0x10000>, + <0x00 0x35e00000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <3>; + ti,sci = <&sms>; + ti,sci-dev-id = <225>; + ti,sci-rm-range-rchan = <0x21>; + ti,sci-rm-range-tchan = <0x22>; + status = "disabled"; + }; + cpts@310d0000 { compatible = "ti,j721e-cpts"; reg = <0x0 0x310d0000 0x0 0x400>; @@ -1695,4 +1712,217 @@ dss_ports: ports { }; }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <279>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 279 1>; + firmware-name = "j721s2-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5d00000 0x00010000>, + <0x5d10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <280>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 280 1>; + firmware-name = "j721s2-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5e00000 0x00010000>, + <0x5e10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <281>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 281 1>; + firmware-name = "j721s2-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5f00000 0x00010000>, + <0x5f10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <282>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 282 1>; + firmware-name = "j721s2-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + c71_0: dsp@64800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <8>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 8 1>; + firmware-name = "j721s2-c71_0-fw"; + status = "disabled"; + }; + + c71_1: dsp@65800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <11>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 11 1>; + firmware-name = "j721s2-c71_1-fw"; + status = "disabled"; + }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x700000 0x00 0x1000>; + ti,esm-pins = <688>, <689>; + bootph-pre-ram; + }; + + watchdog0: watchdog@2200000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2200000 0x00 0x100>; + clocks = <&k3_clks 286 1>; + power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 286 1>; + assigned-clock-parents = <&k3_clks 286 5>; + }; + + watchdog1: watchdog@2210000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2210000 0x00 0x100>; + clocks = <&k3_clks 287 1>; + power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 287 1>; + assigned-clock-parents = <&k3_clks 287 5>; + }; + + /* + * The following RTI instances are coupled with MCU R5Fs, c7x and + * GPU so keeping them reserved as these will be used by their + * respective firmware + */ + watchdog2: watchdog@22f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x22f0000 0x00 0x100>; + clocks = <&k3_clks 290 1>; + power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 290 1>; + assigned-clock-parents = <&k3_clks 290 5>; + /* reserved for GPU */ + status = "reserved"; + }; + + watchdog3: watchdog@2300000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2300000 0x00 0x100>; + clocks = <&k3_clks 288 1>; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 288 1>; + assigned-clock-parents = <&k3_clks 288 5>; + /* reserved for C7X_0 */ + status = "reserved"; + }; + + watchdog4: watchdog@2310000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2310000 0x00 0x100>; + clocks = <&k3_clks 289 1>; + power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 289 1>; + assigned-clock-parents = <&k3_clks 289 5>; + /* reserved for C7X_1 */ + status = "reserved"; + }; + + watchdog5: watchdog@23c0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23c0000 0x00 0x100>; + clocks = <&k3_clks 291 1>; + power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 291 1>; + assigned-clock-parents = <&k3_clks 291 5>; + /* reserved for MAIN_R5F0_0 */ + status = "reserved"; + }; + + watchdog6: watchdog@23d0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23d0000 0x00 0x100>; + clocks = <&k3_clks 292 1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 292 1>; + assigned-clock-parents = <&k3_clks 292 5>; + /* reserved for MAIN_R5F0_1 */ + status = "reserved"; + }; + + watchdog7: watchdog@23e0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23e0000 0x00 0x100>; + clocks = <&k3_clks 293 1>; + power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 293 1>; + assigned-clock-parents = <&k3_clks 293 5>; + /* reserved for MAIN_R5F1_0 */ + status = "reserved"; + }; + + watchdog8: watchdog@23f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x23f0000 0x00 0x100>; + clocks = <&k3_clks 294 1>; + power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 294 1>; + assigned-clock-parents = <&k3_clks 294 5>; + /* reserved for MAIN_R5F1_1 */ + status = "reserved"; + }; }; diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi index 2ddad931855..7254f3bd363 100644 --- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi @@ -443,7 +443,7 @@ }; mcu_navss: bus@28380000 { - compatible = "simple-mfd"; + compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; @@ -655,4 +655,84 @@ power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <284>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 284 1>; + firmware-name = "j721s2-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <285>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 285 1>; + firmware-name = "j721s2-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; + + wkup_esm: esm@42080000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x42080000 0x00 0x1000>; + ti,esm-pins = <63>; + bootph-pre-ram; + }; + + /* + * The 2 RTI instances are couple with MCU R5Fs so keeping them + * reserved as these will be used by their respective firmware + */ + mcu_watchdog0: watchdog@40600000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40600000 0x00 0x100>; + clocks = <&k3_clks 295 1>; + power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 295 1>; + assigned-clock-parents = <&k3_clks 295 5>; + /* reserved for MCU_R5F0_0 */ + status = "reserved"; + }; + + mcu_watchdog1: watchdog@40610000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x40610000 0x00 0x100>; + clocks = <&k3_clks 296 1>; + power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 296 1>; + assigned-clock-parents = <&k3_clks 296 5>; + /* reserved for MCU_R5F0_1 */ + status = "reserved"; + }; }; diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi index a4006f32802..dcad372620b 100644 --- a/arch/arm/dts/k3-j721s2-som-p0.dtsi +++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi @@ -29,6 +29,108 @@ alignment = <0x1000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; mux0: mux-controller { @@ -151,3 +253,109 @@ cdns,read-delay = <4>; }; }; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; diff --git a/arch/arm/dts/k3-serdes.h b/arch/arm/dts/k3-serdes.h index 29167f85c1f..21b4886c47b 100644 --- a/arch/arm/dts/k3-serdes.h +++ b/arch/arm/dts/k3-serdes.h @@ -111,7 +111,7 @@ #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE2_USB_SWAP 0x2 #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi index fabe5925b70..1694ef88495 100644 --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi @@ -133,7 +133,16 @@ ranges = <0x0 0x0 0xf0000000 0x00300000>, <0xfff00000 0x0 0xfff00000 0x00016000>; - spi1: spi@201000 { + host_intf: host_intf@9f000 { + compatible = "nuvoton,npcm845-host-intf"; + reg = <0x9f000 0x1000>; + type = "espi"; + ioaddr = <0x4e>; + channel-support = <0xf>; + syscon = <&gcr>; + }; + + pspi: spi@201000 { compatible = "nuvoton,npcm845-pspi"; reg = <0x201000 0x1000>; pinctrl-names = "default"; diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts index a93666cb419..0d3aaa0fffe 100644 --- a/arch/arm/dts/nuvoton-npcm845-evb.dts +++ b/arch/arm/dts/nuvoton-npcm845-evb.dts @@ -2,6 +2,8 @@ // Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com /dts-v1/; + +#include <dt-bindings/phy/nuvoton,npcm-usbphy.h> #include "nuvoton-npcm845.dtsi" #include "nuvoton-npcm845-pincfg.dtsi" @@ -46,10 +48,10 @@ spi1 = &fiu1; spi3 = &fiu3; spi4 = &fiux; - spi5 = &spi1; + spi5 = &pspi; usb0 = &udc0; usb1 = &ehci1; - usb2 = &ehci2; + usb2 = &udc8; }; chosen { @@ -60,6 +62,17 @@ reg = <0x0 0x0 0x0 0x40000000>; }; + tpm@0 { + compatible = "microsoft,ftpm"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + vsbr2: vsbr2 { compatible = "regulator-npcm845"; regulator-name = "vr2"; @@ -149,6 +162,8 @@ snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; snps,reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; /* gpio162 */ + phy-supply = <&vsbr2>; + phy-supply-microvolt = <1800000>; status = "okay"; }; @@ -179,7 +194,7 @@ status = "okay"; }; -&spi1 { +&pspi { status = "okay"; }; @@ -197,7 +212,7 @@ &udc0 { status = "okay"; - phys = <&usbphy1 0>; + phys = <&usbphy1 NPCM_UDC0_7>; }; &sdhci0 { @@ -207,12 +222,12 @@ &ehci1 { status = "okay"; - phys = <&usbphy2 3>; + phys = <&usbphy2 NPCM_USBH1>; }; -&ehci2 { +&udc8 { status = "okay"; - phys = <&usbphy3 4>; + phys = <&usbphy3 NPCM_UDC8>; }; &rng { diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi index e49e564b790..4c6d5bed447 100644 --- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi @@ -174,7 +174,7 @@ compatible = "nuvoton,npcm845-usb-phy"; #phy-cells = <1>; reg = <3>; - resets = <&rstc3 NPCM8XX_RESET_USBPHY3>; + resets = <&rstc4 NPCM8XX_RESET_USBPHY3>; status = "disabled"; }; }; diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts deleted file mode 100644 index e57dfd368d6..00000000000 --- a/arch/arm/dts/phycore-imx8mm.dts +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet <t.remmet@phytec.de> - */ - -/dts-v1/; - -#include <dt-bindings/net/ti-dp83867.h> -#include "imx8mm.dtsi" - -/ { - model = "PHYTEC phyCORE-i.MX8MM"; - compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - chosen { - stdout-path = &uart3; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; -}; - -/* ethernet */ -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - phy-reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - phy-reset-duration = <1>; - phy-reset-post-delay = <1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; - enet-phy-lane-no-swap; - }; - }; -}; - -/* SPI nor flash */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - flash0: norflash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -/* i2c eeprom */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - - /* M24C32-D */ - i2c_eeprom: eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - u-boot,i2c-offset-len = <2>; - }; - - /* M24C32-D Identification page */ - i2c_eeprom_id: eeprom@59 { - compatible = "atmel,24c32"; - reg = <0x59>; - u-boot,i2c-offset-len = <2>; - }; -}; - -/* debug console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* sd-card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -/* watchdog */ -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp-gpio { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index c07e2022e4a..47ba9fa4a78 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -90,6 +90,13 @@ bootph-all; }; +&dsi { + clocks = <&rcc 0 STM32F4_APB2_CLOCK(DSI)>, + <&rcc 0 STM32F4_APB2_CLOCK(LTDC)>, + <&clk_hse>; + clock-names = "pclk", "px_clk", "ref"; +}; + &gpioa { bootph-all; }; @@ -134,6 +141,12 @@ bootph-all; }; +<dc { + bootph-all; + + clocks = <&rcc 0 STM32F4_APB2_CLOCK(LTDC)>; +}; + &pinctrl { bootph-all; diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts index 6e0ffc1903b..c9acabf0f53 100644 --- a/arch/arm/dts/stm32f469-disco.dts +++ b/arch/arm/dts/stm32f469-disco.dts @@ -119,7 +119,7 @@ }; }; - panel-dsi@0 { + panel@0 { compatible = "orisetech,otm8009a"; reg = <0>; /* dsi virtual channel (0..3) */ reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; @@ -138,7 +138,7 @@ status = "okay"; port { - ltdc_out_dsi: endpoint@0 { + ltdc_out_dsi: endpoint { remote-endpoint = <&dsi_in>; }; }; diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 2c823cce98b..add55c96e21 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -70,22 +70,17 @@ }; }; }; + }; +}; - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - resets = <&rcc STM32F7_APB2_RESET(LTDC)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; - - status = "okay"; - bootph-all; +<dc { + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; + bootph-all; - ports { - port@0 { - dp_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&dsi_in>; }; }; }; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 6f93fc7bcfc..d63cd2ba7eb 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -86,6 +86,10 @@ status = "okay"; }; +<dc { + status = "okay"; +}; + &rtc { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp25-pinctrl.dtsi b/arch/arm/dts/stm32mp25-pinctrl.dtsi new file mode 100644 index 00000000000..d34a1d5e79c --- /dev/null +++ b/arch/arm/dts/stm32mp25-pinctrl.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */ + }; + }; +}; diff --git a/arch/arm/dts/stm32mp25-u-boot.dtsi b/arch/arm/dts/stm32mp25-u-boot.dtsi new file mode 100644 index 00000000000..f4f26add2a4 --- /dev/null +++ b/arch/arm/dts/stm32mp25-u-boot.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2023 + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio25 = &gpioz; + pinctrl0 = &pinctrl; + pinctrl1 = &pinctrl_z; + }; + + firmware { + optee { + bootph-all; + }; + }; + + /* need PSCI for sysreset during board_f */ + psci { + bootph-all; + }; + + soc@0 { + bootph-all; + }; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&syscfg { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi new file mode 100644 index 00000000000..cf2f28dc158 --- /dev/null +++ b/arch/arm/dts/stm32mp251.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xb200005a>; + status = "disabled"; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_ls_mcu: ck-icn-ls-mcu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + rifsc: rifsc-bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + }; +}; diff --git a/arch/arm/dts/stm32mp253.dtsi b/arch/arm/dts/stm32mp253.dtsi new file mode 100644 index 00000000000..af48e82efe8 --- /dev/null +++ b/arch/arm/dts/stm32mp253.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp251.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + arm-pmu { + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm/dts/stm32mp255.dtsi b/arch/arm/dts/stm32mp255.dtsi new file mode 100644 index 00000000000..e6fa596211f --- /dev/null +++ b/arch/arm/dts/stm32mp255.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp253.dtsi" + +/ { +}; diff --git a/arch/arm/dts/stm32mp257.dtsi b/arch/arm/dts/stm32mp257.dtsi new file mode 100644 index 00000000000..5c5000d3d9d --- /dev/null +++ b/arch/arm/dts/stm32mp257.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp255.dtsi" + +/ { +}; diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi new file mode 100644 index 00000000000..a35a9b90388 --- /dev/null +++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + */ + +#include "stm32mp25-u-boot.dtsi" + +&usart2 { + bootph-all; +}; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/stm32mp257f-ev1.dts b/arch/arm/dts/stm32mp257f-ev1.dts new file mode 100644 index 00000000000..a88494eed34 --- /dev/null +++ b/arch/arm/dts/stm32mp257f-ev1.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp25xc.dtsi b/arch/arm/dts/stm32mp25xc.dtsi new file mode 100644 index 00000000000..5e83a692648 --- /dev/null +++ b/arch/arm/dts/stm32mp25xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm/dts/stm32mp25xf.dtsi b/arch/arm/dts/stm32mp25xf.dtsi new file mode 100644 index 00000000000..5e83a692648 --- /dev/null +++ b/arch/arm/dts/stm32mp25xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi new file mode 100644 index 00000000000..abdbc7aebc7 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AI>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@442d0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@442e0000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi new file mode 100644 index 00000000000..2e0d4d349d1 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AK>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi new file mode 100644 index 00000000000..2406e972554 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AL>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi index 15290e6892f..fc7315b9440 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi +++ b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi @@ -68,10 +68,7 @@ &emac0 { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index d83852e72f0..b5d713926a3 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -13,6 +13,9 @@ }; &emac0 { + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + phy-mode = "rgmii"; phy-supply = <®_dcdce>; }; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts index 00fe28caac9..b3b1b869212 100644 --- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts @@ -13,6 +13,8 @@ }; &emac0 { + allwinner,tx-delay-ps = <700>; + phy-mode = "rgmii-rxid"; phy-supply = <®_dldo1>; }; diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index ecf9fbd2ca7..5d8f21059f6 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -315,20 +315,19 @@ clock-frequency = <100000>; }; - nvec@7000c500 { + i2c@7000c500 { compatible = "nvidia,nvec"; - reg = <0x7000c500 0x100>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; + + /delete-property/ #address-cells; + /delete-property/ #size-cells; + /delete-property/ dmas; + /delete-property/ dma-names; + clock-frequency = <80000>; request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; slave-addr = <138>; - clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; + + status = "okay"; }; i2c@7000d000 { diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index fcf31e2dd09..c9277388c9a 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -71,6 +71,13 @@ dr_mode = "otg"; }; + usb-phy@7d000000 { + status = "okay"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + backlight: backlight { compatible = "pwm-backlight"; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts index 945ae404acc..bfc675ca926 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts @@ -35,6 +35,7 @@ regulator-name = "vcore_emmc"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; + regulator-boot-on; }; }; }; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts index 4363bfc87d8..cf03011bc1f 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts @@ -36,6 +36,7 @@ regulator-name = "vdd_emmc_core"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; }; }; }; diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts index 89348fde134..ef8b2b5049b 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts @@ -35,6 +35,7 @@ regulator-name = "vcore_emmc"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; + regulator-boot-on; }; }; }; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 39f7caf8d0b..19de984d5fe 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -101,6 +101,7 @@ regulator-name = "vdd_emmc_core"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; }; /* uSD slot VDD */ @@ -108,6 +109,7 @@ regulator-name = "vdd_usd"; regulator-min-microvolt = <3100000>; regulator-max-microvolt = <3100000>; + regulator-boot-on; }; /* uSD slot VDDIO */ @@ -148,17 +150,32 @@ dr_mode = "otg"; }; + usb-phy@7d000000 { + status = "okay"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + /* Mini USB port */ usb2: usb@7d004000 { status = "okay"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; }; + usb-phy@7d004000 { + status = "okay"; + }; + /* Dock's USB port */ usb3: usb@7d008000 { status = "okay"; }; + usb-phy@7d008000 { + status = "okay"; + }; + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ clk32k_in: clock-32k { compatible = "fixed-clock"; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index fd9d11ca19c..3f11d33bc4a 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -84,12 +84,14 @@ regulator-name = "vdd_1v2_backlight"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-boot-on; }; vcore_lcd: vdd2 { regulator-name = "vcore_lcd"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; + regulator-boot-on; }; vdd_1v8_vio: vddio { @@ -105,6 +107,7 @@ regulator-name = "vdd_emmc_core"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; }; /* uSD slot VDDIO */ @@ -119,6 +122,7 @@ regulator-name = "avdd_dsi_csi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-boot-on; }; }; }; @@ -161,11 +165,22 @@ dr_mode = "otg"; }; + usb-phy@7d000000 { + status = "okay"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + /* Dock's USB port */ usb3: usb@7d008000 { status = "okay"; }; + usb-phy@7d008000 { + status = "okay"; + }; + backlight: backlight { compatible = "pwm-backlight"; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index 888f9ca74e6..c4649eee79d 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -82,6 +82,7 @@ regulator-name = "vdd_emmc_core"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; }; /* uSD slot VDD */ @@ -89,6 +90,7 @@ regulator-name = "vdd_usd"; regulator-min-microvolt = <3100000>; regulator-max-microvolt = <3100000>; + regulator-boot-on; }; /* uSD slot VDDIO */ @@ -129,6 +131,13 @@ dr_mode = "otg"; }; + usb-phy@7d000000 { + status = "okay"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + /* Dock's USB port */ usb3: usb@7d008000 { status = "okay"; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index 5c7b2deae5d..21cd0f9207b 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -81,6 +81,7 @@ regulator-name = "avdd_dsi_csi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-boot-on; }; }; }; @@ -100,6 +101,13 @@ dr_mode = "otg"; }; + usb-phy@7d000000 { + status = "okay"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + backlight: backlight { compatible = "nvidia,tegra-pwm-backlight"; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 6e52fc5a53e..01936b872e0 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -110,6 +110,7 @@ regulator-name = "vdd_ddr_rx"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; + regulator-boot-on; }; }; }; @@ -152,6 +153,14 @@ dr_mode = "otg"; }; + usb-phy@7d000000 { + status = "okay"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&avdd_3v3_periph>; + }; + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ clk32k_in: clock-32k { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index 593ca4a49cf..ec39aad1c0c 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -49,7 +49,6 @@ ethernet_phy: ethernet-phy@1 { reg = <1>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-hub.dts index 99f248d4e5f..1b3eddc667d 100644 --- a/arch/arm/dts/zynq-syzygy-hub.dts +++ b/arch/arm/dts/zynq-syzygy-hub.dts @@ -48,7 +48,6 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 0106d7bb177..6083f99dc8d 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -88,7 +88,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index ceea982546e..bbdbf99aee9 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -49,7 +49,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 199384bec96..ff475f86824 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -46,7 +46,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index add75999f47..02298b98163 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -41,7 +41,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 70bc41822e3..1d967bd1a28 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -44,7 +44,6 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts index 83b84130979..b621860705c 100644 --- a/arch/arm/dts/zynq-zybo-z7.dts +++ b/arch/arm/dts/zynq-zybo-z7.dts @@ -55,7 +55,6 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index 0ce5238c9a8..c3d97858d7f 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -45,7 +45,6 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index bf7569c6dda..cc57c2a1b0b 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -311,13 +311,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */ - #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/ - compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ - reg = <0x6c>; - /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ - /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ - }; + /* u39 8T49N240 */ }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index c456c375ac8..9acccad40e7 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -532,15 +532,7 @@ /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ - clock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */ - #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/ - compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ - reg = <0x60>; - /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ - /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ - - }; - + /* u39 8T49N240 - pcie clocking 3 */ }; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 5a5c1efd6b9..8d0ddecdc14 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -87,7 +87,7 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - +#if 0 usbhub0: usb-hub { /* u36 */ i2c-bus = <&i2c1>; compatible = "microchip,usb5744"; @@ -98,6 +98,7 @@ compatible = "microchip,usb2244"; reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_0 { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 30a0230d476..95b1dc5aa57 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -139,7 +139,7 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - +#if 0 usbhub0: usb-hub { /* u43 */ i2c-bus = <&usbhub_i2c0>; compatible = "microchip,usb5744"; @@ -150,6 +150,7 @@ compatible = "microchip,usb2244"; reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_0 { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 8f4c52d6d64..e2387a2abb8 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -139,7 +139,7 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - +#if 0 usbhub0: usb-hub { /* u43 */ i2c-bus = <&usbhub_i2c0>; compatible = "microchip,usb5744"; @@ -150,6 +150,7 @@ compatible = "microchip,usb2244"; reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_0 { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index c4f1da92186..f43c159cdca 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -131,10 +131,12 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; +#if 0 usbhub: usb5744 { /* u43 */ compatible = "microchip,usb5744"; reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_0 { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 6c5e0e56606..3643569cc7c 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -113,13 +113,14 @@ phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; assigned-clock-rates = <250000000>, <20000000>; - +#if 0 usb5744: usb-hub { /* u43 */ status = "okay"; compatible = "microchip,usb5744"; i2c-bus = <&i2c1>; reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_0 { diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 58a56bc1bd8..21be909b1ab 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -148,6 +148,7 @@ ipi_mailbox_pmu1: mailbox@ff9905c0 { bootph-all; + compatible = "xlnx,zynqmp-ipi-dest-mailbox"; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index e7625c42985..405e9bd3d81 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -23,6 +23,7 @@ struct pass_over_info_t { extern unsigned long boot_pointer[]; void build_info(void); +int ahab_close(void); int print_bootinfo(void); int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate); int imx8_power_domain_lookup_name(const char *name, diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h index 44d40cade87..33d2ab5230f 100644 --- a/arch/arm/include/asm/arch-mxs/regs-base.h +++ b/arch/arm/include/asm/arch-mxs/regs-base.h @@ -60,7 +60,7 @@ * Register base addresses for i.MX28 */ #elif defined(CONFIG_MX28) -#define MXS_ICOL_BASE 0x80000000 +#define MXS_ICOLL_BASE 0x80000000 #define MXS_HSADC_BASE 0x80002000 #define MXS_APBH_BASE 0x80004000 #define MXS_PERFMON_BASE 0x80006000 diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 3f0182e7665..d2fbf919a5b 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -7,6 +7,7 @@ #ifndef _CPU_H #define _CPU_H +#include <asm/arch/omap.h> #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 0eae857e73a..43f7503571d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -513,14 +513,6 @@ enum dcache_option { }; #endif -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK -#endif - /* Size of an MMU section */ enum { #ifdef CONFIG_ARMV7_LPAE @@ -578,6 +570,14 @@ void psci_system_reset(void); #endif /* CONFIG_ARM64 */ +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif + #ifndef __ASSEMBLY__ /** * save_boot_params() - Save boot parameters before starting reset sequence diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 6dc27d1d589..9961472f69f 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -22,6 +22,7 @@ #include <cpu_func.h> #include <efi_loader.h> #include <irq_func.h> +#include <semihosting.h> #include <asm/global_data.h> #include <asm/proc-armv/ptrace.h> #include <asm/ptrace.h> @@ -135,6 +136,32 @@ static inline void fixup_pc(struct pt_regs *regs, int offset) regs->ARM_pc = pc | (regs->ARM_pc & PCMASK); } +/* + * Try to "emulate" a semihosting call in the event that we don't have a + * debugger attached. + */ +static bool smh_emulate_trap(struct pt_regs *regs) +{ + if (regs->ARM_cpsr & T_BIT) { + u16 *insn = (u16 *)(regs->ARM_pc - 2); + + if (*insn != SMH_T32_SVC) + return false; + } else { + u32 *insn = (u32 *)(regs->ARM_pc - 4); + + if (*insn != SMH_A32_SVC) + return false; + } + + /* Avoid future semihosting calls */ + disable_semihosting(); + + /* Just pretend the call failed */ + regs->ARM_r0 = -1; + return true; +} + void do_undefined_instruction (struct pt_regs *pt_regs) { efi_restore_gd(); @@ -147,6 +174,10 @@ void do_undefined_instruction (struct pt_regs *pt_regs) void do_software_interrupt (struct pt_regs *pt_regs) { + if (CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) && + smh_emulate_trap(pt_regs)) + return; + efi_restore_gd(); printf ("software interrupt\n"); fixup_pc(pt_regs, -4); diff --git a/arch/arm/lib/semihosting.S b/arch/arm/lib/semihosting.S index 393aade94a5..6e1691a832c 100644 --- a/arch/arm/lib/semihosting.S +++ b/arch/arm/lib/semihosting.S @@ -18,11 +18,17 @@ ENTRY(smh_trap) #elif defined(CONFIG_SYS_THUMB_BUILD) svc #0xab #else +#if CONFIG_SYS_ARM_ARCH < 7 + /* Before the ARMv7 exception model, svc (swi) clobbers lr */ + mov r2, lr +#endif svc #0x123456 #endif #if defined(CONFIG_ARM64) ret +#elif CONFIG_SYS_ARM_ARCH < 7 + bx r2 #else bx lr #endif diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 7cf7d1636f5..843f9b9c281 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -240,6 +240,18 @@ IRQ_STACK_START_IN: movs pc, lr @ jump to next instruction & switch modes. .endm + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, IRQ_STACK_START_IN @ get data regions start + str lr, [r0] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of saved stack + ldr lr, [r0] @ restore lr + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry + .endm + .macro get_irq_stack @ setup IRQ stack ldr sp, IRQ_STACK_START .endm @@ -260,9 +272,16 @@ undefined_instruction: .align 5 software_interrupt: - get_bad_stack + get_bad_stack_swi bad_save_user_regs bl do_software_interrupt +#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + movs pc, lr @ return & move spsr_svc into cpsr +#endif .align 5 prefetch_abort: diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 47393babbc6..7a6151a9722 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -372,6 +372,22 @@ static struct mm_region t6020_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x400000000, + .phys = 0x400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x480000000, + .phys = 0x480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x580000000, .phys = 0x580000000, .size = SZ_512M, @@ -473,6 +489,22 @@ static struct mm_region t6022_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x400000000, + .phys = 0x400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x480000000, + .phys = 0x480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x580000000, .phys = 0x580000000, .size = SZ_512M, @@ -553,6 +585,22 @@ static struct mm_region t6022_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x2400000000, + .phys = 0x2400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2480000000, + .phys = 0x2480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x2580000000, .phys = 0x2580000000, .size = SZ_512M, diff --git a/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h b/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h index eb1488e7442..0cd13d8aaa5 100644 --- a/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h +++ b/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h @@ -8,7 +8,6 @@ #ifndef __DM365_LOWLEVEL_H #define __DM365_LOWLEVEL_H -#include <common.h> #include <asm/arch/hardware.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index abd48d42583..c34bc25c0bf 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -54,6 +54,7 @@ config IMX_HAB bool "Support i.MX HAB features" depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP select FSL_CAAM if HAS_CAAM + select SPL_DRIVERS_MISC if SPL imply CMD_DEKBLOB if HAS_CAAM help This option enables the support for secure boot (HAB). diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 994becccefd..1c072f6af11 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -340,6 +340,32 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } +int ahab_close(void) +{ + int err; + u16 lc; + + err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); + if (err != SC_ERR_NONE) { + printf("Error in get lifecycle\n"); + return -EIO; + } + + if (lc != 0x20) { + puts("Current lifecycle is NOT NXP closed, can't move to OEM closed\n"); + display_life_cycle(lc); + return -EPERM; + } + + err = sc_seco_forward_lifecycle(-1, 16); + if (err != SC_ERR_NONE) { + printf("Error in forward lifecycle to OEM closed\n"); + return -EIO; + } + + return 0; +} + static int confirm_close(void) { puts("Warning: Please ensure your sample is in NXP closed state, " @@ -361,27 +387,14 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, { int confirmed = argc >= 2 && !strcmp(argv[1], "-y"); int err; - u16 lc; if (!confirmed && !confirm_close()) return -EACCES; - err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); + err = ahab_close(); if (err) { - printf("Error in get lifecycle\n"); - return -EIO; - } - - if (lc != 0x20) { - puts("Current lifecycle is NOT NXP closed, can't move to OEM closed\n"); - display_life_cycle(lc); - return -EPERM; - } - - err = sc_seco_forward_lifecycle(-1, 16); - if (err) { - printf("Error in forward lifecycle to OEM closed\n"); - return -EIO; + printf("Change to OEM closed failed\n"); + return err; } printf("Change to OEM closed successfully\n"); diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 3d62d7052e7..67da198956c 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -199,6 +199,13 @@ config TARGET_IMX8MP_BEACON select ARCH_MISC_INIT select SPL_CRYPTO if SPL +config TARGET_IMX8MP_DEBIX_MODEL_A + bool "Polyhex i.MX8M Plus Debix Model A SBC" + select BINMAN + select IMX8MP + select IMX8M_LPDDR4 + select SUPPORT_SPL + config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" select BINMAN @@ -249,7 +256,7 @@ config TARGET_PICO_IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MN_VAR_SOM - bool "imx8mn_var_som" + bool "Variscite imx8mn_var_som" select BINMAN select IMX8MN select SUPPORT_SPL @@ -384,6 +391,7 @@ source "board/msc/sm2s_imx8mp/Kconfig" source "board/mntre/imx8mq_reform2/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" +source "board/polyhex/imx8mp_debix_model_a/Kconfig" source "board/purism/librem5/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" source "board/technexion/pico-imx8mq/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 986870799d3..47219957b58 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -56,6 +56,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), + PLL_1443X_RATE(900000000U, 300, 8, 0, 0), PLL_1443X_RATE(800000000U, 300, 9, 0, 0), PLL_1443X_RATE(750000000U, 250, 8, 0, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), @@ -904,6 +905,13 @@ static int imx8mp_fec_interface_init(struct udevice *dev, return 0; } +#else +static int imx8mp_fec_interface_init(struct udevice *dev, + phy_interface_t interface_type, + bool mx8mp) +{ + return 0; +} #endif int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index fd436dd8851..c3722c60836 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -865,33 +865,29 @@ u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev) enum env_location env_get_location(enum env_operation op, int prio) { enum boot_device dev = get_boot_device(); - enum env_location env_loc = ENVL_UNKNOWN; if (prio) - return env_loc; + return ENVL_UNKNOWN; switch (dev) { -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH case QSPI_BOOT: - env_loc = ENVL_SPI_FLASH; - break; -#endif -#ifdef CONFIG_ENV_IS_IN_MMC + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + return ENVL_NOWHERE; case SD1_BOOT: case SD2_BOOT: case SD3_BOOT: case MMC1_BOOT: case MMC2_BOOT: case MMC3_BOOT: - env_loc = ENVL_MMC; - break; -#endif + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4)) + return ENVL_EXT4; + else if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) + return ENVL_FAT; + return ENVL_NOWHERE; default: -#if defined(CONFIG_ENV_IS_NOWHERE) - env_loc = ENVL_NOWHERE; -#endif - break; + return ENVL_NOWHERE; } - - return env_loc; } diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 766a8811c1f..92c41e9a67b 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -18,6 +18,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <log.h> +#include <phy.h> DECLARE_GLOBAL_DATA_PTR; @@ -832,6 +833,58 @@ u32 imx_get_fecclk(void) return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); } +#if defined(CONFIG_IMX93) && defined(CONFIG_DWC_ETH_QOS) +static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type) +{ + struct blk_ctrl_wakeupmix_regs *bctrl = + (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; + + clrbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_MODE_MASK | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_MII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + case PHY_INTERFACE_MODE_RMII: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_RMII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + setbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | + BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + break; + default: + return -EINVAL; + } + + return 0; +} +#else +static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type) +{ + return 0; +} +#endif + +int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) +{ + if (IS_ENABLED(CONFIG_IMX93) && + IS_ENABLED(CONFIG_DWC_ETH_QOS) && + device_is_compatible(dev, "nxp,imx93-dwmac-eqos")) + return imx93_eqos_interface_init(dev, interface_type); + + return -EINVAL; +} + int set_clk_enet(enum enet_freq type) { u32 div; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7529b311f80..50a9c3e4203 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -246,7 +246,7 @@ config TARGET_KOSAGI_NOVENA select DM_GPIO select DM_MMC select PCI - select DM_SCSI + select SCSI select VIDEO select OF_CONTROL select SUPPORT_SPL diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 5eb5a3d3c4a..b9ff9bb83b3 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -53,16 +53,10 @@ static int is_boot_from_stream_device(u32 boot) } static ulong spl_romapi_read_seekable(struct spl_load_info *load, - ulong sector, ulong count, + ulong offset, ulong byte, void *buf) { - u32 pagesize = *(u32 *)load->priv; - ulong byte = count * pagesize; - u32 offset; - - offset = sector * pagesize; - - return spl_romapi_raw_seekable_read(offset, byte, buf) / pagesize; + return spl_romapi_raw_seekable_read(offset, byte, buf); } static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, @@ -107,20 +101,18 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, struct spl_load_info load; memset(&load, 0, sizeof(load)); - load.bl_len = pagesize; + spl_set_bl_len(&load, pagesize); load.read = spl_romapi_read_seekable; - load.priv = &pagesize; - return spl_load_simple_fit(spl_image, &load, offset / pagesize, header); + return spl_load_simple_fit(spl_image, &load, offset, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; memset(&load, 0, sizeof(load)); - load.bl_len = pagesize; + spl_set_bl_len(&load, pagesize); load.read = spl_romapi_read_seekable; - load.priv = &pagesize; - ret = spl_load_imx_container(spl_image, &load, offset / pagesize); + ret = spl_load_imx_container(spl_image, &load, offset); } else { /* TODO */ puts("Can't support legacy image\n"); @@ -342,7 +334,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, ss.pagesize = pagesize; memset(&load, 0, sizeof(load)); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_romapi_read_stream; load.priv = &ss; @@ -366,7 +358,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, printf("ROM download failure %d\n", imagesize); memset(&load, 0, sizeof(load)); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_ram_load_read; if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h index 2341a713495..b4823a309fc 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h +++ b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h @@ -8,8 +8,6 @@ #ifndef _PINCTRL_SNAPDRAGON_H #define _PINCTRL_SNAPDRAGON_H -#include <common.h> - struct msm_pinctrl_data { int pin_count; int functions_count; diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 9168bf842dc..03898424c95 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -24,6 +24,11 @@ config SOC_K3_AM62A7 endchoice +if SOC_K3_J721E +config SOC_K3_J721E_J7200 + bool "TI's K3 based J7200 SoC variant Family Support" +endif + config SYS_SOC default "k3" @@ -109,56 +114,9 @@ config K3_EARLY_CONS_IDX Use this option to set the index of the serial device to be used for the early console during SPL execution. -config K3_LOAD_SYSFW - bool - depends on SPL - -config K3_SYSFW_IMAGE_NAME - string "File name of SYSFW firmware and configuration blob" - depends on K3_LOAD_SYSFW - default "sysfw.itb" - help - Filename of the combined System Firmware and configuration image tree - blob to be loaded when booting from a filesystem. - -config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT - hex "MMC sector to load SYSFW firmware and configuration blob from" - depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR - default 0x3600 - help - Address on the MMC to load the combined System Firmware and - configuration image tree blob from, when the MMC is being used - in raw mode. Units: MMC sectors (1 sector = 512 bytes). - -config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART - hex "MMC partition to load SYSFW firmware and configuration blob from" - depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - default 2 - help - Partition on the MMC to the combined System Firmware and configuration - image tree blob from, when the MMC is being used in raw mode. - -config K3_SYSFW_IMAGE_SIZE_MAX - int "Amount of memory dynamically allocated for loading SYSFW blob" - depends on K3_LOAD_SYSFW - default 280000 - help - Amount of memory (in bytes) reserved through dynamic allocation at - runtime for loading the combined System Firmware and configuration image - tree blob. Keep it as tight as possible, as this directly affects the - overall SPL memory footprint. - -config K3_SYSFW_IMAGE_SPI_OFFS - hex "SPI offset of SYSFW firmware and configuration blob" - depends on K3_LOAD_SYSFW - default 0x6C0000 - help - Offset of the combined System Firmware and configuration image tree - blob to be loaded when booting from a SPI flash memory. - config SYS_K3_SPL_ATF bool "Start Cortex-A from SPL" - depends on SPL && CPU_V7R + depends on CPU_V7R help Enabling this will try to start Cortex-A (typically with ATF) after SPL from R5. @@ -172,7 +130,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM @@ -187,12 +145,15 @@ config K3_X509_SWRV help SWRV for X509 certificate used for boot images -source "board/ti/am65x/Kconfig" -source "board/ti/am64x/Kconfig" -source "board/ti/am62x/Kconfig" -source "board/ti/am62ax/Kconfig" -source "board/ti/j721e/Kconfig" -source "board/siemens/iot2050/Kconfig" -source "board/ti/j721s2/Kconfig" -source "board/toradex/verdin-am62/Kconfig" +if CPU_V7R +source "arch/arm/mach-k3/r5/Kconfig" +endif + +source "arch/arm/mach-k3/am65x/Kconfig" +source "arch/arm/mach-k3/am64x/Kconfig" +source "arch/arm/mach-k3/am62x/Kconfig" +source "arch/arm/mach-k3/am62ax/Kconfig" +source "arch/arm/mach-k3/j721e/Kconfig" +source "arch/arm/mach-k3/j721s2/Kconfig" + endif diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index c7ca0fdce56..42161376469 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -3,12 +3,8 @@ # Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> -obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/ -obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ -obj-$(CONFIG_SOC_K3_AM625) += am62x/ -obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ +obj-$(CONFIG_CPU_V7R) += r5/ obj-$(CONFIG_ARM64) += arm64-mmu.o -obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_ARM64) += cache.o obj-$(CONFIG_OF_LIBFDT) += common_fdt.o ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy) @@ -24,6 +20,5 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o obj-$(CONFIG_SOC_K3_AM642) += am642_init.o obj-$(CONFIG_SOC_K3_AM625) += am625_init.o obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o -obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif obj-y += common.o security.o diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 8fa36f7b913..1d4ef35e7b4 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -209,7 +209,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); } - spl_enable_dcache(); + spl_enable_cache(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/am62ax/Kconfig b/arch/arm/mach-k3/am62ax/Kconfig new file mode 100644 index 00000000000..c5f1ef87126 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/Kconfig @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +if SOC_K3_AM62A7 + +choice + prompt "K3 AM62Ax based boards" + optional + +config TARGET_AM62A7_A53_EVM + bool "TI K3 based AM62A7 EVM running on A53" + select ARM64 + select BINMAN + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_AM62A7_R5_EVM + bool "TI K3 based AM62A7 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +source "board/ti/am62ax/Kconfig" + +endif diff --git a/arch/arm/mach-k3/am62x/Kconfig b/arch/arm/mach-k3/am62x/Kconfig new file mode 100644 index 00000000000..8091d720780 --- /dev/null +++ b/arch/arm/mach-k3/am62x/Kconfig @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +if SOC_K3_AM625 + +choice + prompt "K3 AM62x based boards" + optional + +config TARGET_AM625_A53_EVM + bool "TI K3 based AM625 EVM running on A53" + select ARM64 + select BINMAN + +config TARGET_AM625_R5_EVM + bool "TI K3 based AM625 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +config TARGET_VERDIN_AM62_A53 + bool "Toradex Verdin AM62 running on A53" + select ARM64 + select BINMAN + +config TARGET_VERDIN_AM62_R5 + bool "Toradex Verdin AM62 running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +source "board/beagle/beagleplay/Kconfig" +source "board/ti/am62x/Kconfig" +source "board/toradex/verdin-am62/Kconfig" + +endif diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index c871e92330b..6085379f1db 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -7,7 +7,6 @@ * Dave Gerlach <d-gerlach@ti.com> */ -#include <common.h> #include <fdt_support.h> #include <spl.h> #include <asm/io.h> diff --git a/arch/arm/mach-k3/am64x/Kconfig b/arch/arm/mach-k3/am64x/Kconfig new file mode 100644 index 00000000000..6f7b0039615 --- /dev/null +++ b/arch/arm/mach-k3/am64x/Kconfig @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +if SOC_K3_AM642 + +choice + prompt "K3 AM64 based boards" + optional + +config TARGET_AM642_A53_EVM + bool "TI K3 based AM642 EVM running on A53" + select ARM64 + select BINMAN + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_AM642_R5_EVM + bool "TI K3 based AM642 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +source "board/ti/am64x/Kconfig" + +endif diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c index 9353a475a49..7c2a143ed1b 100644 --- a/arch/arm/mach-k3/am654_init.c +++ b/arch/arm/mach-k3/am654_init.c @@ -6,7 +6,6 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> #include <fdt_support.h> #include <init.h> #include <asm/global_data.h> @@ -259,7 +258,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif - spl_enable_dcache(); + spl_enable_cache(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/am65x/Kconfig b/arch/arm/mach-k3/am65x/Kconfig new file mode 100644 index 00000000000..f17b641e136 --- /dev/null +++ b/arch/arm/mach-k3/am65x/Kconfig @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +if SOC_K3_AM654 + +choice + prompt "K3 AM65 based boards" + optional + +config TARGET_AM654_A53_EVM + bool "TI K3 based AM654 EVM running on A53" + select ARM64 + select SYS_DISABLE_DCACHE_OPS + select BOARD_LATE_INIT + select BINMAN + imply TI_I2C_BOARD_DETECT + +config TARGET_AM654_R5_EVM + bool "TI K3 based AM654 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select K3_AM654_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +config TARGET_IOT2050_A53 + bool "IOT2050 running on A53" + depends on SOC_K3_AM654 + select ARM64 + select BOARD_LATE_INIT + select SYS_DISABLE_DCACHE_OPS + select BINMAN + help + This builds U-Boot for the IOT2050 devices. + +endchoice + +source "board/ti/am65x/Kconfig" +source "board/siemens/iot2050/Kconfig" + +endif diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index f8087d2421e..b4308205b27 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -9,16 +9,10 @@ * */ -#include <common.h> #include <asm/system.h> #include <asm/armv8/mmu.h> -#ifdef CONFIG_SOC_K3_AM654 -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) - -/* ToDo: Add 64bit IO */ -struct mm_region am654_mem_map[NR_MMU_REGIONS] = { +struct mm_region k3_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -29,271 +23,12 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, + .size = 0x1e780000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { .virt = 0xa0000000UL, .phys = 0xa0000000UL, - .size = 0x02100000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa2100000UL, - .phys = 0xa2100000UL, - .size = 0x5df00000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = am654_mem_map; -#endif /* CONFIG_SOC_K3_AM654 */ - -#ifdef CONFIG_SOC_K3_J721E - -#ifdef CONFIG_TARGET_J721E_A72_EVM -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6) - -/* ToDo: Add 64bit IO */ -struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x1bc00000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_NON_SHARE - }, { - .virt = 0xbbc00000UL, - .phys = 0xbbc00000UL, - .size = 0x44400000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x4d80000000UL, - .phys = 0x4d80000000UL, - .size = 0x0002000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j721e_mem_map; -#endif /* CONFIG_TARGET_J721E_A72_EVM */ - -#ifdef CONFIG_TARGET_J7200_A72_EVM -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) - -/* ToDo: Add 64bit IO */ -struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x04800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_NON_SHARE - }, { - .virt = 0xa4800000UL, - .phys = 0xa4800000UL, - .size = 0x5b800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j7200_mem_map; -#endif /* CONFIG_TARGET_J7200_A72_EVM */ - -#endif /* CONFIG_SOC_K3_J721E */ - -#ifdef CONFIG_SOC_K3_J721S2 -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) - -/* ToDo: Add 64bit IO */ -struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j721s2_mem_map; - -#endif /* CONFIG_SOC_K3_J721S2 */ - -#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7) - -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) - -/* ToDo: Add 64bit IO */ -struct mm_region am62_mem_map[NR_MMU_REGIONS] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1E780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xA0000000UL, - .phys = 0xA0000000UL, - .size = 0x60000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = am62_mem_map; -#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ - -#ifdef CONFIG_SOC_K3_AM642 - -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) - -/* ToDo: Add 64bit IO */ -struct mm_region am64_mem_map[NR_MMU_REGIONS] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1E800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xA0000000UL, - .phys = 0xA0000000UL, .size = 0x60000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE @@ -316,5 +51,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { } }; -struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 */ +struct mm_region *mem_map = k3_mem_map; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index d8974d6c388..fd400e7e3dd 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -6,7 +6,6 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> #include <cpu_func.h> #include <image.h> #include <init.h> @@ -522,7 +521,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) } } -void spl_enable_dcache(void) +void spl_enable_cache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) phys_addr_t ram_top = CFG_SYS_SDRAM_BASE; @@ -543,7 +542,7 @@ void spl_enable_dcache(void) gd->arch.tlb_addr + gd->arch.tlb_size); gd->relocaddr = gd->arch.tlb_addr; - dcache_enable(); + enable_caches(); #endif } diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 04f3c0b85bd..e9db9fbfb63 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -37,7 +37,7 @@ void disable_linefill_optimization(void); void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr); void k3_sysfw_print_ver(void); -void spl_enable_dcache(void); +void spl_enable_cache(void); void mmr_unlock(uintptr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); enum k3_device_type get_device_type(void); diff --git a/arch/arm/mach-k3/j721e/Kconfig b/arch/arm/mach-k3/j721e/Kconfig new file mode 100644 index 00000000000..0761b82b15a --- /dev/null +++ b/arch/arm/mach-k3/j721e/Kconfig @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +if SOC_K3_J721E + +choice + prompt "K3 J721E based boards" + optional + +config TARGET_J721E_A72_EVM + bool "TI K3 based J721E EVM running on A72" + select ARM64 + select BOARD_LATE_INIT + imply TI_I2C_BOARD_DETECT + select SYS_DISABLE_DCACHE_OPS + select BINMAN + +config TARGET_J721E_R5_EVM + bool "TI K3 based J721E EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +config TARGET_J7200_A72_EVM + bool "TI K3 based J7200 EVM running on A72" + select ARM64 + select SOC_K3_J721E_J7200 + select BOARD_LATE_INIT + imply TI_I2C_BOARD_DETECT + select SYS_DISABLE_DCACHE_OPS + select BINMAN + +config TARGET_J7200_R5_EVM + bool "TI K3 based J7200 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +source "board/beagle/beagleboneai64/Kconfig" +source "board/ti/j721e/Kconfig" + +endif diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 18814c39ec3..c2976c4ea0d 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -6,7 +6,6 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> #include <init.h> #include <spl.h> #include <asm/io.h> @@ -287,14 +286,21 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif - spl_enable_dcache(); + spl_enable_cache(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { switch (boot_device) { case BOOT_DEVICE_MMC1: - return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS); + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) { + if (spl_mmc_emmc_boot_partition(mmc)) + return MMCSD_MODE_EMMCBOOT; + return MMCSD_MODE_FS; + } + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; + return MMCSD_MODE_EMMCBOOT; case BOOT_DEVICE_MMC2: return MMCSD_MODE_FS; default: diff --git a/arch/arm/mach-k3/j721s2/Kconfig b/arch/arm/mach-k3/j721s2/Kconfig new file mode 100644 index 00000000000..8b54c0401b6 --- /dev/null +++ b/arch/arm/mach-k3/j721s2/Kconfig @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +if SOC_K3_J721S2 + +choice + prompt "K3 J721S2 based boards" + optional + +config TARGET_J721S2_A72_EVM + bool "TI K3 based J721S2 EVM running on A72" + select ARM64 + select BOARD_LATE_INIT + imply TI_I2C_BOARD_DETECT + select SYS_DISABLE_DCACHE_OPS + select BINMAN + +config TARGET_J721S2_R5_EVM + bool "TI K3 based J721S2 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +source "board/ti/j721s2/Kconfig" + +endif diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 7170a808c4b..fb0708bae16 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -6,7 +6,6 @@ * David Huang <d-huang@ti.com> */ -#include <common.h> #include <init.h> #include <spl.h> #include <asm/io.h> @@ -232,7 +231,7 @@ void k3_mem_init(void) if (ret) panic("DRAM 1 init failed: %d\n", ret); } - spl_enable_dcache(); + spl_enable_cache(); } /* Support for the various EVM / SK families */ diff --git a/board/ti/keys/custMpk.crt b/arch/arm/mach-k3/keys/custMpk.crt index 01bd64aae57..01bd64aae57 100644 --- a/board/ti/keys/custMpk.crt +++ b/arch/arm/mach-k3/keys/custMpk.crt diff --git a/board/ti/keys/custMpk.key b/arch/arm/mach-k3/keys/custMpk.key index adba378c800..adba378c800 100644 --- a/board/ti/keys/custMpk.key +++ b/arch/arm/mach-k3/keys/custMpk.key diff --git a/board/ti/keys/custMpk.pem b/arch/arm/mach-k3/keys/custMpk.pem index adba378c800..adba378c800 100644 --- a/board/ti/keys/custMpk.pem +++ b/arch/arm/mach-k3/keys/custMpk.pem diff --git a/board/ti/keys/ti-degenerate-key.pem b/arch/arm/mach-k3/keys/ti-degenerate-key.pem index bd7d3745ade..bd7d3745ade 100644 --- a/board/ti/keys/ti-degenerate-key.pem +++ b/arch/arm/mach-k3/keys/ti-degenerate-key.pem diff --git a/arch/arm/mach-k3/r5/Kconfig b/arch/arm/mach-k3/r5/Kconfig new file mode 100644 index 00000000000..ae79f8ff6cd --- /dev/null +++ b/arch/arm/mach-k3/r5/Kconfig @@ -0,0 +1,45 @@ +config K3_LOAD_SYSFW + bool + +config K3_SYSFW_IMAGE_NAME + string "File name of SYSFW firmware and configuration blob" + depends on K3_LOAD_SYSFW + default "sysfw.itb" + help + Filename of the combined System Firmware and configuration image tree + blob to be loaded when booting from a filesystem. + +config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT + hex "MMC sector to load SYSFW firmware and configuration blob from" + depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + default 0x3600 + help + Address on the MMC to load the combined System Firmware and + configuration image tree blob from, when the MMC is being used + in raw mode. Units: MMC sectors (1 sector = 512 bytes). + +config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART + hex "MMC partition to load SYSFW firmware and configuration blob from" + depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + default 2 + help + Partition on the MMC to the combined System Firmware and configuration + image tree blob from, when the MMC is being used in raw mode. + +config K3_SYSFW_IMAGE_SIZE_MAX + int "Amount of memory dynamically allocated for loading SYSFW blob" + depends on K3_LOAD_SYSFW + default 280000 + help + Amount of memory (in bytes) reserved through dynamic allocation at + runtime for loading the combined System Firmware and configuration image + tree blob. Keep it as tight as possible, as this directly affects the + overall SPL memory footprint. + +config K3_SYSFW_IMAGE_SPI_OFFS + hex "SPI offset of SYSFW firmware and configuration blob" + depends on K3_LOAD_SYSFW + default 0x6C0000 + help + Offset of the combined System Firmware and configuration image tree + blob to be loaded when booting from a SPI flash memory. diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile new file mode 100644 index 00000000000..b99199d3374 --- /dev/null +++ b/arch/arm/mach-k3/r5/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_SOC_K3_J721E) += j721e/ +obj-$(CONFIG_SOC_K3_J721E) += j7200/ +obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ +obj-$(CONFIG_SOC_K3_AM625) += am62x/ +obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ + +obj-y += lowlevel_init.o +obj-y += r5_mpu.o + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o +endif diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/r5/am62ax/Makefile index 02a941805e9..02a941805e9 100644 --- a/arch/arm/mach-k3/am62ax/Makefile +++ b/arch/arm/mach-k3/r5/am62ax/Makefile diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c index 01b76f7493c..38db4f2f5c8 100644 --- a/arch/arm/mach-k3/am62ax/am62a_qos_data.c +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c @@ -5,7 +5,6 @@ * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <common.h> #include <asm/arch/hardware.h> #include "common.h" diff --git a/arch/arm/mach-k3/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c index d950b35e0be..d950b35e0be 100644 --- a/arch/arm/mach-k3/am62ax/clk-data.c +++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c index abf5d8e91aa..6cced9efd08 100644 --- a/arch/arm/mach-k3/am62ax/dev-data.c +++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c @@ -52,6 +52,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(161, &soc_lpsc_list[5]), PSC_DEV(162, &soc_lpsc_list[6]), PSC_DEV(75, &soc_lpsc_list[7]), + PSC_DEV(36, &soc_lpsc_list[8]), PSC_DEV(102, &soc_lpsc_list[8]), PSC_DEV(146, &soc_lpsc_list[8]), PSC_DEV(166, &soc_lpsc_list[9]), diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/r5/am62x/Makefile index d6c876df66d..d6c876df66d 100644 --- a/arch/arm/mach-k3/am62x/Makefile +++ b/arch/arm/mach-k3/r5/am62x/Makefile diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/r5/am62x/clk-data.c index d7bfed0e031..d7bfed0e031 100644 --- a/arch/arm/mach-k3/am62x/clk-data.c +++ b/arch/arm/mach-k3/r5/am62x/clk-data.c diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/r5/am62x/dev-data.c index 59c95df2a88..59c95df2a88 100644 --- a/arch/arm/mach-k3/am62x/dev-data.c +++ b/arch/arm/mach-k3/r5/am62x/dev-data.c diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/r5/j7200/Makefile index 0f91cf4daea..0f91cf4daea 100644 --- a/arch/arm/mach-k3/j7200/Makefile +++ b/arch/arm/mach-k3/r5/j7200/Makefile diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/r5/j7200/clk-data.c index 9b45786a2d4..9b45786a2d4 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/r5/j7200/clk-data.c diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/r5/j7200/dev-data.c index 8ce6796fd04..8ce6796fd04 100644 --- a/arch/arm/mach-k3/j7200/dev-data.c +++ b/arch/arm/mach-k3/r5/j7200/dev-data.c diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile index 0f91cf4daea..0f91cf4daea 100644 --- a/arch/arm/mach-k3/j721e/Makefile +++ b/arch/arm/mach-k3/r5/j721e/Makefile diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/r5/j721e/clk-data.c index e4511092c86..e4511092c86 100644 --- a/arch/arm/mach-k3/j721e/clk-data.c +++ b/arch/arm/mach-k3/r5/j721e/clk-data.c diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/r5/j721e/dev-data.c index b0adb1857be..b0adb1857be 100644 --- a/arch/arm/mach-k3/j721e/dev-data.c +++ b/arch/arm/mach-k3/r5/j721e/dev-data.c diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/r5/j721s2/Makefile index e794bffb3af..e794bffb3af 100644 --- a/arch/arm/mach-k3/j721s2/Makefile +++ b/arch/arm/mach-k3/r5/j721s2/Makefile diff --git a/arch/arm/mach-k3/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c index 0c5c321c1eb..0c5c321c1eb 100644 --- a/arch/arm/mach-k3/j721s2/clk-data.c +++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c index df70c5e5d7c..df70c5e5d7c 100644 --- a/arch/arm/mach-k3/j721s2/dev-data.c +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/r5/lowlevel_init.S index 463ab0de1bd..463ab0de1bd 100644 --- a/arch/arm/mach-k3/lowlevel_init.S +++ b/arch/arm/mach-k3/r5/lowlevel_init.S diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5/r5_mpu.c index 605f7931518..3dbbcaee5f3 100644 --- a/arch/arm/mach-k3/r5_mpu.c +++ b/arch/arm/mach-k3/r5/r5_mpu.c @@ -6,10 +6,10 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <linux/kernel.h> -#include "common.h" +#include <asm/armv7_mpu.h> struct mpu_region_config k3_mpu_regions[16] = { /* diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/r5/sysfw-loader.c index 73a17276e12..94d051ba0fb 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/r5/sysfw-loader.c @@ -6,7 +6,6 @@ * Andreas Dannenberg <dannenberg@ti.com> */ -#include <common.h> #include <dm.h> #include <image.h> #include <log.h> @@ -23,7 +22,7 @@ #include <spi_flash.h> #include <asm/io.h> -#include "common.h" +#include "../common.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ti/common/schema.yaml b/arch/arm/mach-k3/schema.yaml index c8dd2e79e7d..c8dd2e79e7d 100644 --- a/board/ti/common/schema.yaml +++ b/arch/arm/mach-k3/schema.yaml diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index ebc9704a33b..22697a263a8 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -7,7 +7,6 @@ */ #include <asm/io.h> -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <hang.h> diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 0c59515d2eb..4f193794efb 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h> #include <linux/bitops.h> diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c index 72dc394df5f..e9ecc05953a 100644 --- a/arch/arm/mach-keystone/cmd_clock.c +++ b/arch/arm/mach-keystone/cmd_clock.c @@ -6,7 +6,7 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> +#include <vsprintf.h> #include <command.h> #include <asm/arch/hardware.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index dc97bac8550..c6e7e2c3097 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <command.h> #include <image.h> #include <mach/mon.h> diff --git a/arch/arm/mach-keystone/cmd_poweroff.c b/arch/arm/mach-keystone/cmd_poweroff.c index f0ad9173b96..0ad31ef4e28 100644 --- a/arch/arm/mach-keystone/cmd_poweroff.c +++ b/arch/arm/mach-keystone/cmd_poweroff.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <command.h> #include <asm/arch/mon.h> #include <asm/arch/psc_defs.h> diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index ea7d0b903cf..ca0fb702d54 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -9,7 +9,7 @@ #include <cpu_func.h> #include <env.h> #include <asm/io.h> -#include <common.h> +#include <vsprintf.h> #include <asm/arch/msmc.h> #include <asm/arch/ddr3.h> #include <asm/arch/psc_defs.h> diff --git a/arch/arm/mach-keystone/ddr3_spd.c b/arch/arm/mach-keystone/ddr3_spd.c index 6f7f8ab7b40..d4ff442175b 100644 --- a/arch/arm/mach-keystone/ddr3_spd.c +++ b/arch/arm/mach-keystone/ddr3_spd.c @@ -5,8 +5,8 @@ * (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <log.h> +#include <string.h> #include <i2c.h> #include <ddr_spd.h> diff --git a/arch/arm/mach-keystone/include/mach/mux-k2g.h b/arch/arm/mach-keystone/include/mach/mux-k2g.h index 67d47f81721..dfb5ad43506 100644 --- a/arch/arm/mach-keystone/include/mach/mux-k2g.h +++ b/arch/arm/mach-keystone/include/mach/mux-k2g.h @@ -9,7 +9,6 @@ #ifndef __ASM_ARCH_MUX_K2G_H #define __ASM_ARCH_MUX_K2G_H -#include <common.h> #include <asm/io.h> #define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000) diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 1954e69e9f0..39afaaa63d6 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <ns16550.h> diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index efaabca5a7e..8846df3af48 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <env.h> #include <init.h> #include <asm/io.h> diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index e91b0d68f4d..b945e19ec77 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -8,7 +8,6 @@ #include <hang.h> #include <image.h> #include <asm/unaligned.h> -#include <common.h> #include <command.h> #include <mach/mon.h> #include <spl.h> diff --git a/arch/arm/mach-keystone/msmc.c b/arch/arm/mach-keystone/msmc.c index f5cadfbf669..a20e0c98865 100644 --- a/arch/arm/mach-keystone/msmc.c +++ b/arch/arm/mach-keystone/msmc.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <asm/arch/msmc.h> struct mpax { diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c index 145aff8ac66..84d64f3bc40 100644 --- a/arch/arm/mach-keystone/psc.c +++ b/arch/arm/mach-keystone/psc.c @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <linux/delay.h> #include <linux/errno.h> #include <asm/io.h> diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c index 2421acd817e..95a29da0722 100644 --- a/arch/arm/mach-meson/board-info.c +++ b/arch/arm/mach-meson/board-info.c @@ -168,7 +168,7 @@ static unsigned int get_socinfo(void) return socinfo; } -int show_board_info(void) +int checkboard(void) { unsigned int socinfo; diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 6deffb81836..8e0de935385 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -589,15 +589,6 @@ int board_ahci_enable(void) return 0; } -#ifdef CONFIG_SCSI_AHCI_PLAT -void scsi_init(void) -{ - printf("MVEBU SATA INIT\n"); - board_ahci_enable(); - ahci_init((void __iomem *)MVEBU_SATA0_BASE); -} -#endif - #ifdef CONFIG_USB_XHCI_MVEBU #define USB3_MAX_WINDOWS 4 #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8)) diff --git a/arch/arm/mach-mvebu/include/mach/efuse.h b/arch/arm/mach-mvebu/include/mach/efuse.h index b125c30beb8..fd8ebceb26c 100644 --- a/arch/arm/mach-mvebu/include/mach/efuse.h +++ b/arch/arm/mach-mvebu/include/mach/efuse.h @@ -6,8 +6,6 @@ #ifndef _MVEBU_EFUSE_H #define _MVEBU_EFUSE_H -#include <common.h> - struct efuse_val { union { struct { diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index bb01eab80e6..8c10c694dff 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -27,13 +27,6 @@ obj-y += vc.o obj-y += abb.o endif -ifneq ($(CONFIG_OMAP54XX),) -ifeq ($(CONFIG_DM_SCSI),) -obj-y += pipe3-phy.o -obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o -endif -endif - ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),) obj-y += omap-cache.o endif diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 8cb0c57163b..bd5129b04e0 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -105,15 +105,6 @@ config TARGET_CHILIBOARD select DM_SERIAL imply CMD_DM -config TARGET_DRACO - bool "Support draco" - select BOARD_LATE_INIT - select DM - select DM_GPIO - select DM_SERIAL - select FACTORYSET - imply CMD_DM - config TARGET_ETAMIN bool "Support etamin" select BOARD_LATE_INIT diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index a68b21aeacc..57917da25cf 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -309,13 +309,6 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) } #endif -#ifdef CONFIG_SCSI_AHCI_PLAT -void arch_preboot_os(void) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); -} -#endif - #ifdef CONFIG_TI_SECURE_DEVICE void board_fit_image_post_process(const void *fit, int node, void **p_image, size_t *p_size) diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 3e3e7bd259e..bd524f8c9f9 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -152,7 +152,7 @@ config SYS_SOC default "omap3" source "board/logicpd/am3517evm/Kconfig" -source "board/ti/beagle/Kconfig" +source "board/beagle/beagle/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/omap3evm/Kconfig" source "board/isee/igep00x0/Kconfig" diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index e6bee48dfcb..b39132222ee 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -485,9 +485,6 @@ void enable_basic_clocks(void) (*prcm)->cm_l4per_gpio6_clkctrl, (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, -#ifdef CONFIG_SCSI_AHCI_PLAT - (*prcm)->cm_l3init_ocp2scp3_clkctrl, -#endif 0 }; @@ -507,9 +504,6 @@ void enable_basic_clocks(void) #ifdef CONFIG_TI_QSPI (*prcm)->cm_l4per_qspi_clkctrl, #endif -#ifdef CONFIG_SCSI_AHCI_PLAT - (*prcm)->cm_l3init_sata_clkctrl, -#endif 0 }; @@ -542,12 +536,6 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); #endif -#ifdef CONFIG_SCSI_AHCI_PLAT - /* Enable optional functional clock for SATA */ - setbits_le32((*prcm)->cm_l3init_sata_clkctrl, - SATA_CLKCTRL_OPTFCLKEN_MASK); -#endif - /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); diff --git a/arch/arm/mach-omap2/pipe3-phy.c b/arch/arm/mach-omap2/pipe3-phy.c deleted file mode 100644 index 3dfb184c430..00000000000 --- a/arch/arm/mach-omap2/pipe3-phy.c +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - */ - -#include <common.h> -#include <sata.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <linux/bitops.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include "pipe3-phy.h" - -/* PLLCTRL Registers */ -#define PLL_STATUS 0x00000004 -#define PLL_GO 0x00000008 -#define PLL_CONFIGURATION1 0x0000000C -#define PLL_CONFIGURATION2 0x00000010 -#define PLL_CONFIGURATION3 0x00000014 -#define PLL_CONFIGURATION4 0x00000020 - -#define PLL_REGM_MASK 0x001FFE00 -#define PLL_REGM_SHIFT 9 -#define PLL_REGM_F_MASK 0x0003FFFF -#define PLL_REGM_F_SHIFT 0 -#define PLL_REGN_MASK 0x000001FE -#define PLL_REGN_SHIFT 1 -#define PLL_SELFREQDCO_MASK 0x0000000E -#define PLL_SELFREQDCO_SHIFT 1 -#define PLL_SD_MASK 0x0003FC00 -#define PLL_SD_SHIFT 10 -#define SET_PLL_GO 0x1 -#define PLL_TICOPWDN BIT(16) -#define PLL_LDOPWDN BIT(15) -#define PLL_LOCK 0x2 -#define PLL_IDLE 0x1 - -/* PHY POWER CONTROL Register */ -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE - -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 - -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 - - -#define PLL_IDLE_TIME 100 /* in milliseconds */ -#define PLL_LOCK_TIME 100 /* in milliseconds */ - -static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) -{ - return __raw_readl(addr + offset); -} - -static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, - u32 data) -{ - __raw_writel(data, addr + offset); -} - -static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 - *pipe3) -{ - u32 rate; - struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; - - rate = get_sys_clk_freq(); - - for (; dpll_map->rate; dpll_map++) { - if (rate == dpll_map->rate) - return &dpll_map->params; - } - - printf("%s: No DPLL configuration for %u Hz SYS CLK\n", - __func__, rate); - return NULL; -} - - -static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_LOCK_TIME; - - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (val & PLL_LOCK) - break; - } while (--timeout); - - if (!(val & PLL_LOCK)) { - printf("%s: DPLL failed to lock\n", __func__); - return -EBUSY; - } - - return 0; -} - -static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) -{ - u32 val; - struct pipe3_dpll_params *dpll_params; - - dpll_params = omap_pipe3_get_dpll_params(phy); - if (!dpll_params) { - printf("%s: Invalid DPLL parameters\n", __func__); - return -EINVAL; - } - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGN_MASK; - val |= dpll_params->n << PLL_REGN_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val &= ~PLL_SELFREQDCO_MASK; - val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGM_MASK; - val |= dpll_params->m << PLL_REGM_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); - val &= ~PLL_REGM_F_MASK; - val |= dpll_params->mf << PLL_REGM_F_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); - val &= ~PLL_SD_MASK; - val |= dpll_params->sd << PLL_SD_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); - - omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); - - return omap_pipe3_wait_lock(phy); -} - -static void omap_control_phy_power(struct omap_pipe3 *phy, int on) -{ - u32 val, rate; - - val = readl(phy->power_reg); - - rate = get_sys_clk_freq(); - rate = rate/1000000; - - if (on) { - val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - val |= rate << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; - } else { - val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - } - - writel(val, phy->power_reg); -} - -int phy_pipe3_power_on(struct omap_pipe3 *phy) -{ - int ret; - u32 val; - - /* Program the DPLL only if not locked */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (!(val & PLL_LOCK)) { - ret = omap_pipe3_dpll_program(phy); - if (ret) - return ret; - } else { - /* else just bring it out of IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - if (val & PLL_IDLE) { - val &= ~PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, - PLL_CONFIGURATION2, val); - ret = omap_pipe3_wait_lock(phy); - if (ret) - return ret; - } - } - - /* Power up the PHY */ - omap_control_phy_power(phy, 1); - - return 0; -} - -int phy_pipe3_power_off(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_IDLE_TIME; - - /* Power down the PHY */ - omap_control_phy_power(phy, 0); - - /* Put DPLL in IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val |= PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - /* wait for LDO and Oscillator to power down */ - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) - break; - } while (--timeout); - - if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { - printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", - __func__, val); - return -EBUSY; - } - - return 0; -} diff --git a/arch/arm/mach-omap2/pipe3-phy.h b/arch/arm/mach-omap2/pipe3-phy.h deleted file mode 100644 index 182bdcd4c81..00000000000 --- a/arch/arm/mach-omap2/pipe3-phy.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - */ - -#ifndef __OMAP_PIPE3_PHY_H -#define __OMAP_PIPE3_PHY_H - -struct pipe3_dpll_params { - u16 m; - u8 n; - u8 freq:3; - u8 sd; - u32 mf; -}; - -struct pipe3_dpll_map { - unsigned long rate; - struct pipe3_dpll_params params; -}; - -struct omap_pipe3 { - void __iomem *pll_ctrl_base; - void __iomem *power_reg; - struct pipe3_dpll_map *dpll_map; -}; - - -int phy_pipe3_power_on(struct omap_pipe3 *phy); -int phy_pipe3_power_off(struct omap_pipe3 *pipe3); - -#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/mach-omap2/sata.c b/arch/arm/mach-omap2/sata.c deleted file mode 100644 index 53c39ce1fb6..00000000000 --- a/arch/arm/mach-omap2/sata.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TI SATA platform driver - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - */ - -#include <common.h> -#include <ahci.h> -#include <scsi.h> -#include <asm/arch/clock.h> -#include <asm/arch/sata.h> -#include <sata.h> -#include <asm/io.h> -#include <asm/omap_common.h> -#include "pipe3-phy.h" - -static struct pipe3_dpll_map dpll_map_sata[] = { - {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ - {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ - {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ - {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ - {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ - {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ - { }, /* Terminator */ -}; - -struct omap_pipe3 sata_phy = { - .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, - /* .power_reg is updated at runtime */ - .dpll_map = dpll_map_sata, -}; - -int init_sata(int dev) -{ - int ret; - u32 val; - - sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; - - /* Power up the PHY */ - phy_pipe3_power_on(&sata_phy); - - /* Enable SATA module, No Idle, No Standby */ - val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; - writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); - - ret = ahci_init((void __iomem *)DWC_AHSATA_BASE); - - return ret; -} - -int reset_sata(int dev) -{ - return 0; -} - -/* On OMAP platforms SATA provides the SCSI subsystem */ -void scsi_init(void) -{ - init_sata(0); - scsi_scan(1); -} - -int scsi_bus_reset(struct udevice *dev) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); - ahci_init((void __iomem *)DWC_AHSATA_BASE); - - return 0; -} diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index db47baba6d1..5fc92d07fe6 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -76,6 +76,30 @@ config STM32MP15x STM32MP157, STM32MP153 or STM32MP151 STMicroelectronics MPU with core ARMv7 dual core A7 for STM32MP157/3, monocore for STM32MP151 + +config STM32MP25X + bool "Support STMicroelectronics STM32MP25x Soc" + select ARM64 + select CLK_STM32MP25 + select OF_BOARD + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SYS_ARCH_TIMER + select TFABOOT + imply CLK_SCMI + imply CMD_NVEDIT_INFO + imply DM_REGULATOR + imply DM_REGULATOR_SCMI + imply OPTEE + imply RESET_SCMI + imply SYSRESET_PSCI + imply TEE + imply VERSION_VARIABLE + help + Support of STMicroelectronics SOC STM32MP25x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core endchoice config NR_DRAM_BANKS @@ -128,6 +152,6 @@ config CMD_STM32KEY source "arch/arm/mach-stm32mp/Kconfig.13x" source "arch/arm/mach-stm32mp/Kconfig.15x" - +source "arch/arm/mach-stm32mp/Kconfig.25x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/Kconfig.25x b/arch/arm/mach-stm32mp/Kconfig.25x new file mode 100644 index 00000000000..2c0f691f8b5 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.25x @@ -0,0 +1,43 @@ +if STM32MP25X + +choice + prompt "STM32MP25x board select" + optional + +config TARGET_ST_STM32MP25X + bool "STMicroelectronics STM32MP25x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + help + target the STMicroelectronics board with SOC STM32MP25x + managed by board/st/stm32mp2 + The difference between board are managed with devicetree + +endchoice + +config TEXT_BASE + default 0x84000000 + +config PRE_CON_BUF_ADDR + default 0x84800000 + +config PRE_CON_BUF_SZ + default 4096 + +config BOOTSTAGE_STASH_ADDR + default 0x87000000 + +if DEBUG_UART + +config DEBUG_UART_BOARD_INIT + default y + +# debug on USART2 by default +config DEBUG_UART_BASE + default 0x400e0000 + +endif + +source "board/st/stm32mp2/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index a19b2797c8b..00dc25bb275 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -3,24 +3,17 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved # -obj-y += cpu.o obj-y += dram_init.o obj-y += syscon.o obj-y += bsec.o -obj-$(CONFIG_STM32MP13x) += stm32mp13x.o -obj-$(CONFIG_STM32MP15x) += stm32mp15x.o +obj-$(CONFIG_STM32MP15x) += stm32mp1/ +obj-$(CONFIG_STM32MP13x) += stm32mp1/ +obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -obj-y += tzc400.o -else +ifndef CONFIG_SPL_BUILD obj-y += cmd_stm32prog/ obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_TFABOOT) += boot_params.o endif - -obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o -obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 599e63a93dd..28a8280b280 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -110,7 +110,7 @@ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_lock(u32 address, u32 otp) +static bool bsec_read_lock(void __iomem *address, u32 otp) { u32 bit; u32 bank; @@ -118,7 +118,7 @@ static bool bsec_read_lock(u32 address, u32 otp) bit = 1 << (otp & OTP_LOCK_MASK); bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); - return !!(readl(address + bank) & bit); + return !!(readl((address + bank)) & bit); } /** @@ -127,7 +127,7 @@ static bool bsec_read_lock(u32 address, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error, -EAGAIN or -ENOTSUPP */ -static u32 bsec_check_error(u32 base, u32 otp) +static u32 bsec_check_error(void __iomem *base, u32 otp) { u32 bit; u32 bank; @@ -149,7 +149,7 @@ static u32 bsec_check_error(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SR_lock(u32 base, u32 otp) +static bool bsec_read_SR_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp); } @@ -160,7 +160,7 @@ static bool bsec_read_SR_lock(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SP_lock(u32 base, u32 otp) +static bool bsec_read_SP_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp); } @@ -171,7 +171,7 @@ static bool bsec_read_SP_lock(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SW_lock(u32 base, u32 otp) +static bool bsec_read_SW_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp); } @@ -182,7 +182,7 @@ static bool bsec_read_SW_lock(u32 base, u32 otp) * @power: true to power up , false to power down * Return: 0 if succeed */ -static int bsec_power_safmem(u32 base, bool power) +static int bsec_power_safmem(void __iomem *base, bool power) { u32 val; u32 mask; @@ -208,7 +208,7 @@ static int bsec_power_safmem(u32 base, bool power) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp) +static int bsec_shadow_register(struct udevice *dev, void __iomem *base, u32 otp) { u32 val; int ret; @@ -253,7 +253,8 @@ static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp) +static int bsec_read_shadow(struct udevice *dev, void __iomem *base, u32 *val, + u32 otp) { *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32)); @@ -268,7 +269,7 @@ static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp) +static int bsec_write_shadow(struct udevice *dev, void __iomem *base, u32 val, u32 otp) { /* check if programming of otp is locked */ if (bsec_read_SW_lock(base, otp)) @@ -288,7 +289,7 @@ static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp) * after the function the otp data is not refreshed in shadow * Return: 0 if no error */ -static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp) +static int bsec_program_otp(struct udevice *dev, void __iomem *base, u32 val, u32 otp) { u32 ret; bool power_up = false; @@ -338,7 +339,7 @@ static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp) +static int bsec_permanent_lock_otp(struct udevice *dev, void __iomem *base, uint32_t otp) { int ret; bool power_up = false; @@ -392,7 +393,7 @@ static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp) /* BSEC MISC driver *******************************************************/ struct stm32mp_bsec_plat { - u32 base; + void __iomem *base; }; struct stm32mp_bsec_priv { @@ -724,7 +725,7 @@ static int stm32mp_bsec_of_to_plat(struct udevice *dev) { struct stm32mp_bsec_plat *plat = dev_get_plat(dev); - plat->base = (u32)dev_read_addr_ptr(dev); + plat->base = dev_read_addr_ptr(dev); return 0; } diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 7f37b0d2aa2..fb1208fc5d5 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -24,8 +24,11 @@ int dram_init(void) int ret; ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - log_debug("RAM init failed: %d\n", ret); + /* in case there is no RAM driver, retrieve DDR size from DT */ + if (ret == -ENODEV) { + return fdtdec_setup_mem_size_base(); + } else if (ret) { + log_err("RAM init failed: %d\n", ret); return ret; } ret = ram_get_info(dev, &ram); @@ -33,7 +36,7 @@ int dram_init(void) log_debug("Cannot get RAM size: %d\n", ret); return ret; } - log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); + log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size); gd->ram_size = ram.size; @@ -49,9 +52,15 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) if (!total_size) return gd->ram_top; + /* + * make sure U-Boot uses address space below 4GB boundaries even + * if the effective available memory is bigger + */ + gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + /* found enough not-reserved memory to relocated U-Boot */ lmb_init(&lmb); - lmb_add(&lmb, gd->ram_base, get_effective_memsize()); + lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); /* add 8M for reserved memory for display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index ac0deced67e..46d469881b3 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -6,14 +6,72 @@ #ifndef _MACH_STM32_H_ #define _MACH_STM32_H_ +#include <linux/sizes.h> #ifndef __ASSEMBLY__ #include <linux/bitops.h> + +enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, + + BOOT_FLASH_SPINAND = 0x70, + BOOT_FLASH_SPINAND_1 = 0x71, +}; + +#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) +#define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16) +#define TAMP_BOOT_AUTH_SHIFT 16 +#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) +#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) +#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4) +#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0) +#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) + +enum forced_boot_mode { + BOOT_NORMAL = 0x00, + BOOT_FASTBOOT = 0x01, + BOOT_RECOVERY = 0x02, + BOOT_STM32PROG = 0x03, + BOOT_UMS_MMC0 = 0x10, + BOOT_UMS_MMC1 = 0x11, + BOOT_UMS_MMC2 = 0x12, +}; + #endif /* * Peripheral memory map * only address used before device tree parsing */ + +#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x) #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 @@ -58,12 +116,6 @@ #define STM32_DDR_SIZE SZ_1G #ifndef __ASSEMBLY__ -/* enumerated used to identify the SYSCON driver instance */ -enum { - STM32MP_SYSCON_UNKNOWN, - STM32MP_SYSCON_SYSCFG, -}; - /* * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT * - boot device = bit 8:4 @@ -74,40 +126,6 @@ enum { #define BOOT_INSTANCE_MASK 0x0F #define BOOT_INSTANCE_SHIFT 0 -enum boot_device { - BOOT_FLASH_SD = 0x10, - BOOT_FLASH_SD_1 = 0x11, - BOOT_FLASH_SD_2 = 0x12, - BOOT_FLASH_SD_3 = 0x13, - - BOOT_FLASH_EMMC = 0x20, - BOOT_FLASH_EMMC_1 = 0x21, - BOOT_FLASH_EMMC_2 = 0x22, - BOOT_FLASH_EMMC_3 = 0x23, - - BOOT_FLASH_NAND = 0x30, - BOOT_FLASH_NAND_FMC = 0x31, - - BOOT_FLASH_NOR = 0x40, - BOOT_FLASH_NOR_QSPI = 0x41, - - BOOT_SERIAL_UART = 0x50, - BOOT_SERIAL_UART_1 = 0x51, - BOOT_SERIAL_UART_2 = 0x52, - BOOT_SERIAL_UART_3 = 0x53, - BOOT_SERIAL_UART_4 = 0x54, - BOOT_SERIAL_UART_5 = 0x55, - BOOT_SERIAL_UART_6 = 0x56, - BOOT_SERIAL_UART_7 = 0x57, - BOOT_SERIAL_UART_8 = 0x58, - - BOOT_SERIAL_USB = 0x60, - BOOT_SERIAL_USB_OTG = 0x62, - - BOOT_FLASH_SPINAND = 0x70, - BOOT_FLASH_SPINAND_1 = 0x71, -}; - /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) @@ -123,7 +141,6 @@ enum boot_device { #define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) #define TAMP_FWU_BOOT_IDX_OFFSET 0 - #define TAMP_COPRO_STATE_OFF 0 #define TAMP_COPRO_STATE_INIT 1 #define TAMP_COPRO_STATE_CRUN 2 @@ -137,25 +154,23 @@ enum boot_device { #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif -#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) -#define TAMP_BOOT_MODE_SHIFT 8 -#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16) -#define TAMP_BOOT_AUTH_SHIFT 16 -#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) -#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) -#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4) -#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0) -#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ -enum forced_boot_mode { - BOOT_NORMAL = 0x00, - BOOT_FASTBOOT = 0x01, - BOOT_RECOVERY = 0x02, - BOOT_STM32PROG = 0x03, - BOOT_UMS_MMC0 = 0x10, - BOOT_UMS_MMC1 = 0x11, - BOOT_UMS_MMC2 = 0x12, -}; +#if CONFIG_STM32MP25X +#define STM32_RCC_BASE 0x44200000 +#define STM32_TAMP_BASE 0x46010000 + +#define STM32_DDR_BASE 0x80000000 + +#define STM32_DDR_SIZE SZ_4G + +/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x)) + +/* TAMP registers zone 3 RIF 1 (RW) at 96*/ +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) +#endif /* STM32MP25X */ /* offset used for BSEC driver: misc_read and misc_write */ #define STM32_BSEC_SHADOW_OFFSET 0x0 @@ -179,6 +194,20 @@ enum forced_boot_mode { #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 60 #endif +#ifdef CONFIG_STM32MP25X +#define BSEC_OTP_SERIAL 5 +#define BSEC_OTP_RPN 9 +#define BSEC_OTP_PKG 246 +#endif + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* enumerated used to identify the SYSCON driver instance */ +enum { + STM32MP_SYSCON_UNKNOWN, + STM32MP_SYSCON_SYSCFG, +}; +#endif /* __ASSEMBLY__*/ -#endif /* __ASSEMBLY__ */ #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 52aca1e23e1..83388fdb737 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -30,11 +30,30 @@ #define CPU_STM32MP131Fxx 0x05010EC8 #define CPU_STM32MP131Dxx 0x05010EC9 +/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ +#define CPU_STM32MP257Cxx 0x00002000 +#define CPU_STM32MP255Cxx 0x00082000 +#define CPU_STM32MP253Cxx 0x000B2004 +#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP257Axx 0x40002E00 +#define CPU_STM32MP255Axx 0x40082E00 +#define CPU_STM32MP253Axx 0x400B2E04 +#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP257Fxx 0x80002000 +#define CPU_STM32MP255Fxx 0x80082000 +#define CPU_STM32MP253Fxx 0x800B2004 +#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP257Dxx 0xC0002E00 +#define CPU_STM32MP255Dxx 0xC0082E00 +#define CPU_STM32MP253Dxx 0xC00B2E04 +#define CPU_STM32MP251Dxx 0xC00B3E65 + /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 #define CPU_DEV_STM32MP13 0x501 +#define CPU_DEV_STM32MP25 0x505 /* return CPU_DEV constants */ u32 get_cpu_dev(void); @@ -59,6 +78,13 @@ u32 get_cpu_package(void); #define STM32MP15_PKG_AD_TFBGA257 1 #define STM32MP15_PKG_UNKNOWN 0 +/* package used for STM32MP25x */ +#define STM32MP25_PKG_CUSTOM 0 +#define STM32MP25_PKG_AL_TBGA361 3 +#define STM32MP25_PKG_AK_TBGA424 4 +#define STM32MP25_PKG_AI_TBGA436 5 +#define STM32MP25_PKG_UNKNOWN 7 + /* Get SOC name */ #define SOC_NAME_SIZE 20 void get_soc_name(char name[SOC_NAME_SIZE]); diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile new file mode 100644 index 00000000000..94c7724127e --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o + +obj-$(CONFIG_STM32MP13x) += stm32mp13x.o +obj-$(CONFIG_STM32MP15x) += stm32mp15x.o + +obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += tzc400.o +else +obj-$(CONFIG_ARMV7_PSCI) += psci.o +endif + +obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 55574fd4beb..55574fd4beb 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c index de5c5a55ea0..de5c5a55ea0 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 8cdeb0ab3f2..8cdeb0ab3f2 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c index 846637ab162..846637ab162 100644 --- a/arch/arm/mach-stm32mp/pwr_regulator.c +++ b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 6c79259b2c8..6c79259b2c8 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c index 845d973ad1b..845d973ad1b 100644 --- a/arch/arm/mach-stm32mp/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index afc56b02eea..afc56b02eea 100644 --- a/arch/arm/mach-stm32mp/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c diff --git a/arch/arm/mach-stm32mp/tzc400.c b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c index cdc4a40edaf..cdc4a40edaf 100644 --- a/arch/arm/mach-stm32mp/tzc400.c +++ b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile new file mode 100644 index 00000000000..b579ce5a800 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +# +# Copyright (C) 2023, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o +obj-y += arm64-mmu.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c new file mode 100644 index 00000000000..36c631ef0c2 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <asm/system.h> +#include <asm/armv8/mmu.h> +#include <mach/stm32.h> + +#define MP2_MEM_MAP_MAX 10 + +#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \ + (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE)) +#error "invalid CONFIG_TEXT_BASE value" +#endif + +struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = { + { + /* PCIe */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Peripherals: alias1 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OSPI and FMC: memory-map area */ + .virt = 0x60000000UL, + .phys = 0x60000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* + * DDR = STM32_DDR_BASE / STM32_DDR_SIZE + * the beginning of DDR (before CONFIG_TEXT_BASE) is not + * mapped, protected by RIF and reserved for other firmware + * (OP-TEE / TF-M / Cube M33) + */ + .virt = CONFIG_TEXT_BASE, + .phys = CONFIG_TEXT_BASE, + .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE), + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = stm32mp2_mem_map; diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c new file mode 100644 index 00000000000..f43d1aaf72c --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <clk.h> +#include <cpu_func.h> +#include <debug_uart.h> +#include <env_internal.h> +#include <init.h> +#include <misc.h> +#include <wdt.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <asm/system.h> +#include <dm/device.h> +#include <dm/lists.h> +#include <dm/uclass.h> + +/* + * early TLB into the .data section so that it not get cleared + * with 16kB alignment + */ +#define EARLY_TLB_SIZE 0xA000 +u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); + +/* + * initialize the MMU and activate cache in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + */ +static void early_enable_caches(void) +{ + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { + gd->arch.tlb_size = EARLY_TLB_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + } + /* enable MMU (default configuration) */ + dcache_enable(); +} + +/* + * Early system init + */ +int arch_cpu_init(void) +{ + icache_enable(); + early_enable_caches(); + + return 0; +} + +void enable_caches(void) +{ + /* deactivate the data cache, early enabled in arch_cpu_init() */ + dcache_disable(); + /* + * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr + * to update the TLB location udpated in board_f.c::reserve_mmu + */ + gd->arch.tlb_fillptr = 0; + dcache_enable(); +} + +/* used when CONFIG_DISPLAY_CPUINFO is activated */ +int print_cpuinfo(void) +{ + char name[SOC_NAME_SIZE]; + + get_soc_name(name); + printf("CPU: %s\n", name); + + return 0; +} + +int arch_misc_init(void) +{ + return 0; +} + +/* + * Force data-section, as .bss will not be valid + * when save_boot_params is invoked. + */ +static uintptr_t nt_fw_dtb __section(".data"); + +uintptr_t get_stm32mp_bl2_dtb(void) +{ + return nt_fw_dtb; +} + +/* + * Save the FDT address provided by TF-A in r2 at boot time + * This function is called from start.S + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + nt_fw_dtb = r2; + + save_boot_params_ret(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/fdt.c b/arch/arm/mach-stm32mp/stm32mp2/fdt.c new file mode 100644 index 00000000000..31b127b465a --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/fdt.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <asm/u-boot.h> + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c new file mode 100644 index 00000000000..4b2f70af9cc --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* SYSCFG register */ +#define SYSCFG_DEVICEID_OFFSET 0x6400 +#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 +#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_DEVICEID_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP9 */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(31, 0) + +/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines + * - 000: Custom package + * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 0 +#define PKG_MASK GENMASK(2, 0) + +static u32 read_deviceid(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +u32 get_cpu_type(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +int get_eth_nb(void) +{ + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + fallthrough; + case CPU_STM32MP257Dxx: + fallthrough; + case CPU_STM32MP257Cxx: + fallthrough; + case CPU_STM32MP257Axx: + nb_eth = 5; /* dual ETH with TSN support */ + break; + case CPU_STM32MP253Fxx: + fallthrough; + case CPU_STM32MP253Dxx: + fallthrough; + case CPU_STM32MP253Cxx: + fallthrough; + case CPU_STM32MP253Axx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP251Fxx: + fallthrough; + case CPU_STM32MP251Dxx: + fallthrough; + case CPU_STM32MP251Cxx: + fallthrough; + case CPU_STM32MP251Axx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP25) { + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + cpu_s = "257F"; + break; + case CPU_STM32MP257Dxx: + cpu_s = "257D"; + break; + case CPU_STM32MP257Cxx: + cpu_s = "257C"; + break; + case CPU_STM32MP257Axx: + cpu_s = "257A"; + break; + case CPU_STM32MP255Fxx: + cpu_s = "255F"; + break; + case CPU_STM32MP255Dxx: + cpu_s = "255D"; + break; + case CPU_STM32MP255Cxx: + cpu_s = "255C"; + break; + case CPU_STM32MP255Axx: + cpu_s = "255A"; + break; + case CPU_STM32MP253Fxx: + cpu_s = "253F"; + break; + case CPU_STM32MP253Dxx: + cpu_s = "253D"; + break; + case CPU_STM32MP253Cxx: + cpu_s = "253C"; + break; + case CPU_STM32MP253Axx: + cpu_s = "253A"; + break; + case CPU_STM32MP251Fxx: + cpu_s = "251F"; + break; + case CPU_STM32MP251Dxx: + cpu_s = "251D"; + break; + case CPU_STM32MP251Cxx: + cpu_s = "251C"; + break; + case CPU_STM32MP251Axx: + cpu_s = "251A"; + break; + default: + cpu_s = "25??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP25_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP25_PKG_AL_TBGA361: + package = "AL"; + break; + case STM32MP25_PKG_AK_TBGA424: + package = "AK"; + break; + case STM32MP25_PKG_AI_TBGA436: + package = "AI"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index a0e8e1dfdc5..a2e351d74a7 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -10,8 +10,8 @@ #include <asm/arch/stm32.h> static const struct udevice_id stm32mp_syscon_ids[] = { - { .compatible = "st,stm32mp157-syscfg", - .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG}, { } }; diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index c2410dd7bb1..267cb0b1aba 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -354,10 +354,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT image\n"); - load.dev = NULL; - load.priv = NULL; - load.filename = NULL; - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spi_load_read; ret = spl_load_simple_fit(spl_image, &load, load_offset, header); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index cd405874d36..8ad76d5edf7 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -11,6 +11,7 @@ #include <init.h> #include <log.h> #include <ns16550.h> +#include <power/regulator.h> #include <usb.h> #include <asm/global_data.h> #include <asm/io.h> @@ -185,6 +186,10 @@ int board_init(void) /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif + + /* Set up boot-on regulators */ + regulators_enable_boot_on(_DEBUG); + return nvidia_board_init(); } diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h b/arch/arm/mach-tegra/xusb-padctl-common.h index e3fd613f2be..a576e6f6165 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.h +++ b/arch/arm/mach-tegra/xusb-padctl-common.h @@ -6,7 +6,6 @@ #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_ #define _TEGRA_XUSB_PADCTL_COMMON_H_ -#include <common.h> #include <fdtdec.h> #include <dm/ofnode.h> diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 1945f60e08f..e6a67326dd4 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -13,20 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -static const char * const clk_names[clk_max] = { - "armpll", "ddrpll", "iopll", - "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", - "ddr2x", "ddr3x", "dci", - "lqspi", "smc", "pcap", "gem0", "gem1", - "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", - "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", - "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", - "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", - "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", - "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", - "smc_aper", "swdt", "dbg_trc", "dbg_apb" -}; - /** * set_cpu_clk_info() - Setup clock information * @@ -65,46 +51,3 @@ int set_cpu_clk_info(void) return 0; } - -/** - * soc_clk_dump() - Print clock frequencies - * Returns zero on success - * - * Implementation for the clk dump command. - */ -int soc_clk_dump(void) -{ - struct udevice *dev; - int i, ret; - - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(zynq_clk), &dev); - if (ret) - return ret; - - printf("clk\t\tfrequency\n"); - for (i = 0; i < clk_max; i++) { - const char *name = clk_names[i]; - if (name) { - struct clk clk; - unsigned long rate; - - clk.id = i; - ret = clk_request(dev, &clk); - if (ret < 0) - return ret; - - rate = clk_get_rate(&clk); - - clk_free(&clk); - - if ((rate == (unsigned long)-ENOSYS) || - (rate == (unsigned long)-ENXIO)) - printf("%10s%20s\n", name, "unknown"); - else - printf("%10s%20lu\n", name, rate); - } - } - - return 0; -} diff --git a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h index 434a7fa20e4..783d7c45c7b 100644 --- a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h +++ b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h @@ -4,7 +4,6 @@ #define _PSU_INIT_GPL_H_ #include <asm/io.h> -#include <common.h> int mask_pollonvalue(unsigned long add, u32 mask, u32 value); diff --git a/arch/m68k/include/asm/fsl_mcdmafec.h b/arch/m68k/include/asm/fsl_mcdmafec.h deleted file mode 100644 index de6c548fafd..00000000000 --- a/arch/m68k/include/asm/fsl_mcdmafec.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef fsl_mcdmafec_h -#define fsl_mcdmafec_h - -/* Re-use of the definitions */ -#include <asm/fec.h> - -typedef struct fecdma { - u32 rsvd0; /* 0x000 */ - u32 eir; /* 0x004 */ - u32 eimr; /* 0x008 */ - u32 rsvd1[6]; /* 0x00C - 0x023 */ - u32 ecr; /* 0x024 */ - u32 rsvd2[6]; /* 0x028 - 0x03F */ - u32 mmfr; /* 0x040 */ - u32 mscr; /* 0x044 */ - u32 rsvd3[7]; /* 0x048 - 0x063 */ - u32 mibc; /* 0x064 */ - u32 rsvd4[7]; /* 0x068 - 0x083 */ - u32 rcr; /* 0x084 */ - u32 rhr; /* 0x088 */ - u32 rsvd5[14]; /* 0x08C - 0x0C3 */ - u32 tcr; /* 0x0C4 */ - u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */ - u32 palr; /* 0x0E4 */ - u32 paur; /* 0x0E8 */ - u32 opd; /* 0x0EC */ - u32 rsvd7[10]; /* 0x0F0 - 0x117 */ - u32 iaur; /* 0x118 */ - u32 ialr; /* 0x11C */ - u32 gaur; /* 0x120 */ - u32 galr; /* 0x124 */ - u32 rsvd8[7]; /* 0x128 - 0x143 */ - u32 tfwr; /* 0x144 */ - u32 rsvd9[14]; /* 0x148 - 0x17F */ - u32 fmc; /* 0x180 */ - u32 rfdr; /* 0x184 */ - u32 rfsr; /* 0x188 */ - u32 rfcr; /* 0x18C */ - u32 rlrfp; /* 0x190 */ - u32 rlwfp; /* 0x194 */ - u32 rfar; /* 0x198 */ - u32 rfrp; /* 0x19C */ - u32 rfwp; /* 0x1A0 */ - u32 tfdr; /* 0x1A4 */ - u32 tfsr; /* 0x1A8 */ - u32 tfcr; /* 0x1AC */ - u32 tlrfp; /* 0x1B0 */ - u32 tlwfp; /* 0x1B4 */ - u32 tfar; /* 0x1B8 */ - u32 tfrp; /* 0x1BC */ - u32 tfwp; /* 0x1C0 */ - u32 frst; /* 0x1C4 */ - u32 ctcwr; /* 0x1C8 */ -} fecdma_t; - -struct fec_info_dma { - int index; - u32 iobase; - u32 pinmux; - u32 miibase; - int phy_addr; - int dup_spd; - char *phy_name; - int phyname_init; - cbd_t *rxbd; /* Rx BD */ - cbd_t *txbd; /* Tx BD */ - uint rx_idx; - uint tx_idx; - char *txbuf; - int initialized; - struct fec_info_dma *next; - u16 rx_task; /* DMA receive Task Number */ - u16 tx_task; /* DMA Transmit Task Number */ - u16 rx_pri; /* DMA Receive Priority */ - u16 tx_pri; /* DMA Transmit Priority */ - u16 rx_init; /* DMA Receive Initiator */ - u16 tx_init; /* DMA Transmit Initiator */ - u16 used_tbd_idx; /* next transmit BD to clean */ - u16 clean_tbd_num; /* the number of available transmit BDs */ - int to_loop; - struct mii_dev *bus; -}; - -/* Bit definitions and macros for IEVENT */ -#define FEC_EIR_TXERR (0x00040000) -#define FEC_EIR_RXERR (0x00020000) -#undef FEC_EIR_CLEAR_ALL -#define FEC_EIR_CLEAR_ALL (0xFFFE0000) - -/* Bit definitions and macros for R_HASH */ -#define FEC_RHASH_FCE_DC (0x80000000) -#define FEC_RHASH_MULTCAST (0x40000000) -#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24) - -/* Bit definitions and macros for FEC_TFWR */ -#undef FEC_TFWR_X_WMRK -#undef FEC_TFWR_X_WMRK_64 -#undef FEC_TFWR_X_WMRK_128 -#undef FEC_TFWR_X_WMRK_192 - -#define FEC_TFWR_X_WMRK(x) ((x)&0x0F) -#define FEC_TFWR_X_WMRK_64 (0x00) -#define FEC_TFWR_X_WMRK_128 (0x01) -#define FEC_TFWR_X_WMRK_192 (0x02) -#define FEC_TFWR_X_WMRK_256 (0x03) -#define FEC_TFWR_X_WMRK_320 (0x04) -#define FEC_TFWR_X_WMRK_384 (0x05) -#define FEC_TFWR_X_WMRK_448 (0x06) -#define FEC_TFWR_X_WMRK_512 (0x07) -#define FEC_TFWR_X_WMRK_576 (0x08) -#define FEC_TFWR_X_WMRK_640 (0x09) -#define FEC_TFWR_X_WMRK_704 (0x0A) -#define FEC_TFWR_X_WMRK_768 (0x0B) -#define FEC_TFWR_X_WMRK_832 (0x0C) -#define FEC_TFWR_X_WMRK_896 (0x0D) -#define FEC_TFWR_X_WMRK_960 (0x0E) -#define FEC_TFWR_X_WMRK_1024 (0x0F) - -/* FIFO definitions */ -/* Bit definitions and macros for FSTAT */ -#define FIFO_STAT_IP (0x80000000) -#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24) -#define FIFO_STAT_FAE (0x00800000) -#define FIFO_STAT_RXW (0x00400000) -#define FIFO_STAT_UF (0x00200000) -#define FIFO_STAT_OF (0x00100000) -#define FIFO_STAT_FR (0x00080000) -#define FIFO_STAT_FULL (0x00040000) -#define FIFO_STAT_ALARM (0x00020000) -#define FIFO_STAT_EMPTY (0x00010000) - -/* Bit definitions and macros for FCTRL */ -#define FIFO_CTRL_WCTL (0x40000000) -#define FIFO_CTRL_WFR (0x20000000) -#define FIFO_CTRL_FRAME (0x08000000) -#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24) -#define FIFO_CTRL_IPMASK (0x00800000) -#define FIFO_CTRL_FAEMASK (0x00400000) -#define FIFO_CTRL_RXWMASK (0x00200000) -#define FIFO_CTRL_UFMASK (0x00100000) -#define FIFO_CTRL_OFMASK (0x00080000) - -#endif /* fsl_mcdmafec_h */ diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 411b00899c2..b118a917542 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -314,21 +314,6 @@ #include <asm/immap_547x_8x.h> #include <asm/m547x_8x.h> -#ifdef CONFIG_FSLDMAFEC -#define FEC0_RX_TASK 0 -#define FEC0_TX_TASK 1 -#define FEC0_RX_PRIORITY 6 -#define FEC0_TX_PRIORITY 7 -#define FEC0_RX_INIT 16 -#define FEC0_TX_INIT 17 -#define FEC1_RX_TASK 2 -#define FEC1_TX_TASK 3 -#define FEC1_RX_PRIORITY 6 -#define FEC1_TX_PRIORITY 7 -#define FEC1_RX_INIT 30 -#define FEC1_TX_INIT 31 -#endif - #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR diff --git a/arch/m68k/lib/fec.c b/arch/m68k/lib/fec.c index d6f238e4b34..ac36aec0ed7 100644 --- a/arch/m68k/lib/fec.c +++ b/arch/m68k/lib/fec.c @@ -10,7 +10,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC) +#if defined(CONFIG_MCFFEC) static int fec_get_node(int fec_idx) { char fec_alias[5] = {"fec"}; @@ -77,4 +77,4 @@ int fec_get_mii_base(int fec_idx, u32 *mii_base) return fec_get_fdt_prop(fec_idx, "mii-base", mii_base); } -#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC +#endif //CONFIG_MCFFEC diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index d3ad6693013..3774acaadc3 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -336,6 +336,22 @@ BUILDIO_MEM(b, u8) BUILDIO_MEM(w, u16) BUILDIO_MEM(l, u32) BUILDIO_MEM(q, u64) +#define __raw_readb __raw_readb +#define __raw_readw __raw_readw +#define __raw_readl __raw_readl +#define __raw_readq __raw_readq +#define __raw_writeb __raw_writeb +#define __raw_writew __raw_writew +#define __raw_writel __raw_writel +#define __raw_writeq __raw_writeq +#define readb readb +#define readw readw +#define readl readl +#define readq readq +#define writeb writeb +#define writew writew +#define writel writel +#define writeq writeq #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ __BUILD_IOPORT_SINGLE(bus, bwlq, type, ) \ @@ -405,7 +421,8 @@ static inline void writes##bwlq(volatile void __iomem *mem, \ } \ } \ \ -static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ +static inline void reads##bwlq(const volatile void __iomem *mem, \ + void *addr, \ unsigned int count) \ { \ volatile type *__addr = addr; \ @@ -448,8 +465,24 @@ __BUILD_IOPORT_STRING(bwlq, type) BUILDSTRING(b, u8) BUILDSTRING(w, u16) BUILDSTRING(l, u32) +#define readsb readsb +#define readsw readsw +#define readsl readsl +#define writesb writesb +#define writesw writesw +#define writesl writesl +#define outsb outsb +#define outsw outsw +#define outsl outsl +#define insb insb +#define insw insw +#define insl insl #ifdef CONFIG_64BIT BUILDSTRING(q, u64) +#define readsq readsq +#define writesq writesq +#define insq insq +#define outsq outsq #endif diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index d6d2f7d9d03..f1cff691f4f 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -246,8 +246,8 @@ static int boot_setup_fdt(struct bootm_headers *images) { images->initrd_start = virt_to_phys((void *)images->initrd_start); images->initrd_end = virt_to_phys((void *)images->initrd_end); - return image_setup_libfdt(images, images->ft_addr, images->ft_len, - &images->lmb); + + return image_setup_libfdt(images, images->ft_addr, &images->lmb); } static void boot_prep_linux(struct bootm_headers *images) diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c index dbf8c9cd221..3181a946a27 100644 --- a/arch/mips/mach-pic32/cpu.c +++ b/arch/mips/mach-pic32/cpu.c @@ -143,26 +143,3 @@ const char *get_core_name(void) return str; } #endif -#ifdef CONFIG_CMD_CLK - -int soc_clk_dump(void) -{ - int i; - - printf("PLL Speed: %lu MHz\n", - CLK_MHZ(rate(PLLCLK))); - - printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK))); - - printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); - - for (i = PB1CLK; i <= PB7CLK; i++) - printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1, - CLK_MHZ(rate(i))); - - for (i = REF1CLK; i <= REF5CLK; i++) - printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1, - CLK_MHZ(rate(i))); - return 0; -} -#endif diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h index 817cd72e00b..321e4fd1ca5 100644 --- a/arch/nios2/include/asm/io.h +++ b/arch/nios2/include/asm/io.h @@ -94,6 +94,9 @@ static inline void insl (unsigned long port, void *dst, unsigned long count) unsigned long *p = dst; while (count--) *p++ = inl (port); } +#define insb insb +#define insw insw +#define insl insl static inline void outsb (unsigned long port, const void *src, unsigned long count) { @@ -111,6 +114,9 @@ static inline void outsl (unsigned long port, const void *src, unsigned long cou const unsigned long *p = src; while (count--) outl (*p++, port); } +#define outsb outsb +#define outsw outsw +#define outsl outsl /* * Clear and set bits in one shot. These macros can be used to clear and diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index f5cb000de6b..340f9a0da56 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -3,7 +3,6 @@ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm-offsets.h> #include <mpc83xx.h> #include <system-constants.h> @@ -19,6 +18,8 @@ #ifdef CONFIG_QE #include <fsl_qe.h> #endif +#include <asm/ppc.h> +#include <asm/fsl_lbc.h> #include "lblaw/lblaw.h" #include "elbc/elbc.h" diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index d72d3147f63..ceb54867894 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -20,6 +20,7 @@ #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/fsl_lbc.h> #include <asm/u-boot.h> #include "hrcw/hrcw.h" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 96183ac2c84..b770d294e61 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -9,7 +9,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <display_options.h> #include <env.h> #include <init.h> diff --git a/arch/powerpc/cpu/mpc8xx/cache.c b/arch/powerpc/cpu/mpc8xx/cache.c index 41559009cac..525c87f37cd 100644 --- a/arch/powerpc/cpu/mpc8xx/cache.c +++ b/arch/powerpc/cpu/mpc8xx/cache.c @@ -4,7 +4,6 @@ * Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr */ -#include <common.h> #include <cpu_func.h> #include <asm/processor.h> #include <asm/ppc.h> diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 56383cecde2..b9afd312ec6 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -16,7 +16,6 @@ * Wolfgang Denk <wd@denx.de> */ -#include <common.h> #include <cpu_func.h> #include <display_options.h> #include <net.h> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index feef792ee77..aac4203a6e4 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <watchdog.h> diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index b4a26efe302..b204a3d7517 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -5,7 +5,6 @@ * Code copied & edited from Freescale mpc85xx stuff. */ -#include <common.h> #include <time.h> #include <asm/global_data.h> #include <linux/libfdt.h> diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c index 40793c26e12..8c85fc180b9 100644 --- a/arch/powerpc/cpu/mpc8xx/immap.c +++ b/arch/powerpc/cpu/mpc8xx/immap.c @@ -8,7 +8,6 @@ * MPC8xx Internal Memory Map Functions */ -#include <common.h> #include <command.h> #include <asm/global_data.h> @@ -16,6 +15,7 @@ #include <asm/cpm_8xx.h> #include <asm/iopin_8xx.h> #include <asm/io.h> +#include <asm/ppc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c index eef1951f2fd..babef07ffb1 100644 --- a/arch/powerpc/cpu/mpc8xx/interrupts.c +++ b/arch/powerpc/cpu/mpc8xx/interrupts.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> +#include <stdio.h> #include <irq_func.h> #include <mpc8xx.h> #include <mpc8xx_irq.h> diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index 1a882a38820..baf81381b39 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -4,12 +4,12 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <clock_legacy.h> #include <mpc8xx.h> #include <asm/global_data.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/immap_8xx.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c index 56794b08a15..5220c560e5f 100644 --- a/arch/powerpc/cpu/mpc8xx/traps.c +++ b/arch/powerpc/cpu/mpc8xx/traps.c @@ -15,7 +15,7 @@ * This file handles the architecture-dependent parts of hardware exceptions */ -#include <common.h> +#include <vsprintf.h> #include <asm/ptrace.h> #include <command.h> #include <asm/processor.h> diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index a03f091c305..95f0f559b4c 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -6,9 +6,6 @@ #ifndef __ASM_PPC_FSL_LBC_H #define __ASM_PPC_FSL_LBC_H -#include <config.h> -#include <common.h> - #ifdef CONFIG_MPC85xx void lbc_sdram_init(void); #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 6ed21c781fe..43d71f5caec 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -9,7 +9,7 @@ #define __ASM_GBL_DATA_H #include <config.h> -#include "asm/types.h" +#include <linux/types.h> /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index f63cae0bc80..2412bb9d7c1 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -138,26 +138,37 @@ static inline unsigned char __raw_readb(const volatile void __iomem *addr) { return *(volatile unsigned char *)PCI_FIX_ADDR(addr); } +#define __raw_readb __raw_readb + static inline unsigned short __raw_readw(const volatile void __iomem *addr) { return *(volatile unsigned short *)PCI_FIX_ADDR(addr); } +#define __raw_readw __raw_readw + static inline unsigned int __raw_readl(const volatile void __iomem *addr) { return *(volatile unsigned int *)PCI_FIX_ADDR(addr); } +#define __raw_readl __raw_readl + static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) { *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v; } +#define __raw_writeb __raw_writeb + static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) { *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v; } +#define __raw_writew __raw_writew + static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) { *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v; } +#define __raw_writel __raw_writel /* * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 6b4eb8dc7b9..9271de0ddfc 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -5,9 +5,6 @@ #include <config.h> -#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff) -#define U64_TO_U32_L(addr) ((addr) & 0xffffffff) - / { binman: binman { multiple-images; @@ -36,8 +33,7 @@ os = "U-Boot"; arch = "riscv"; compression = "none"; - load = <U64_TO_U32_H(CONFIG_TEXT_BASE) - U64_TO_U32_L(CONFIG_TEXT_BASE)>; + load = /bits/ 64 <CONFIG_TEXT_BASE>; uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; @@ -50,7 +46,7 @@ os = "Linux"; arch = "riscv"; compression = "none"; - load = <CONFIG_TEXT_BASE>; + load = /bits/ 64 <CONFIG_TEXT_BASE>; linux_blob: blob-ext { filename = "Image"; @@ -64,10 +60,8 @@ os = "opensbi"; arch = "riscv"; compression = "none"; - load = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR) - U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>; - entry = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR) - U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>; + load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; opensbi_blob: opensbi { filename = "fw_dynamic.bin"; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 13c47f7caa3..6d2675d6cea 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -533,6 +533,16 @@ #gpio-cells = <2>; }; + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + mmc0: mmc@16010000 { compatible = "starfive,jh7110-mmc"; reg = <0x0 0x16010000 0x0 0x10000>; diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 4170877a1ae..da165858034 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -218,7 +218,8 @@ static inline u64 readq(const volatile void __iomem *addr) #define insw(p, d, l) readsw(__io(p), d, l) #define insl(p, d, l) readsl(__io(p), d, l) -static inline void readsb(unsigned int *addr, void *data, int bytelen) +static inline void readsb(const volatile void __iomem *addr, void *data, + unsigned int bytelen) { unsigned char *ptr; unsigned char *ptr2; @@ -233,7 +234,8 @@ static inline void readsb(unsigned int *addr, void *data, int bytelen) } } -static inline void readsw(unsigned int *addr, void *data, int wordlen) +static inline void readsw(const volatile void __iomem *addr, void *data, + unsigned int wordlen) { unsigned short *ptr; unsigned short *ptr2; @@ -248,7 +250,8 @@ static inline void readsw(unsigned int *addr, void *data, int wordlen) } } -static inline void readsl(unsigned int *addr, void *data, int longlen) +static inline void readsl(const volatile void __iomem *addr, void *data, + unsigned int longlen) { unsigned int *ptr; unsigned int *ptr2; @@ -263,7 +266,8 @@ static inline void readsl(unsigned int *addr, void *data, int longlen) } } -static inline void writesb(unsigned int *addr, const void *data, int bytelen) +static inline void writesb(volatile void __iomem *addr, const void *data, + unsigned int bytelen) { unsigned char *ptr; unsigned char *ptr2; @@ -278,7 +282,8 @@ static inline void writesb(unsigned int *addr, const void *data, int bytelen) } } -static inline void writesw(unsigned int *addr, const void *data, int wordlen) +static inline void writesw(volatile void __iomem *addr, const void *data, + unsigned int wordlen) { unsigned short *ptr; unsigned short *ptr2; @@ -293,7 +298,8 @@ static inline void writesw(unsigned int *addr, const void *data, int wordlen) } } -static inline void writesl(unsigned int *addr, const void *data, int longlen) +static inline void writesl(volatile void __iomem *addr, const void *data, + unsigned int longlen) { unsigned int *ptr; unsigned int *ptr2; @@ -307,6 +313,14 @@ static inline void writesl(unsigned int *addr, const void *data, int longlen) longlen--; } } + +#define readsb readsb +#define readsw readsw +#define readsl readsl +#define writesb writesb +#define writesw writesw +#define writesl writesl + #endif #define outb_p(val, port) outb((val), (port)) diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 6a63661312a..c09e5c69bc3 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -21,41 +21,36 @@ #include <linux/err.h> /* pending register */ -#define PENDING_REG(base) ((ulong)(base) + 0x1000) +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32)) /* enable register */ -#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) +#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32)) /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) /* priority register */ #define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE) /* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */ -#define FIRST_AVAILABLE_BIT 0x2 -#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart)) #define PLICSW_PRIORITY_BASE 0x4 -#define PLICSW_INTERRUPT_PER_HART 0x1 DECLARE_GLOBAL_DATA_PTR; static int enable_ipi(int hart) { - unsigned int en; + u32 enable_bit = (hart + 1) % 32; - en = FIRST_AVAILABLE_BIT << hart; - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); + writel(BIT(enable_bit), (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); return 0; } static void init_priority_ipi(int hart_num) { - uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw); + u32 *priority = (void *)PRIORITY_REG(gd->arch.plicsw); - for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) { - writel(1, &priority[i]); - } + for (int i = 0; i < hart_num; i++) + writel(1, &priority[i]); - return; + return; } int riscv_init_ipi(void) @@ -104,9 +99,10 @@ int riscv_init_ipi(void) int riscv_send_ipi(int hart) { - unsigned int ipi = SEND_IPI_TO_HART(hart); + u32 interrupt_id = hart + 1; + u32 pending_bit = interrupt_id % 32; - writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw)); + writel(BIT(pending_bit), (void __iomem *)PENDING_REG(gd->arch.plicsw, hart)); return 0; } @@ -123,10 +119,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { - unsigned int ipi = SEND_IPI_TO_HART(hart); + u32 interrupt_id = hart + 1; + u32 pending_bit = interrupt_id % 32; - *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw)); - *pending = !!(*pending & ipi); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, hart)); + *pending = !!(*pending & BIT(pending_bit)); return 0; } diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 95c26d855ab..cbae5109e85 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -287,6 +287,23 @@ int os_persistent_file(char *buf, int maxsize, const char *fname) return 0; } +int os_mktemp(char *fname, off_t size) +{ + int fd; + + fd = mkostemp(fname, O_CLOEXEC); + if (fd < 0) + return -errno; + + if (unlink(fname) < 0) + return -errno; + + if (ftruncate(fd, size)) + return -errno; + + return fd; +} + /* Restore tty state when we exit */ static struct termios orig_term; static bool term_setup; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index c7197795efb..4fe72664c4b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -631,9 +631,10 @@ clocks = <&clk_fixed>, <&clk_sandbox 1>, <&clk_sandbox 0>, + <&ccf 11>, <&clk_sandbox 3>, <&clk_sandbox 2>; - clock-names = "fixed", "i2c", "spi", "uart2", "uart1"; + clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1"; }; clk-test2 { @@ -654,6 +655,7 @@ ccf: clk-ccf { compatible = "sandbox,clk-ccf"; + #clock-cells = <1>; }; efi-media { @@ -1914,6 +1916,71 @@ compatible = "sandbox,arm-ffa"; }; }; + + nand-controller { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sandbox,nand"; + + nand@0 { + reg = <0>; + nand-ecc-mode = "soft"; + sandbox,id = [00 e3]; + sandbox,erasesize = <(8 * 1024)>; + sandbox,oobsize = <16>; + sandbox,pagesize = <512>; + sandbox,pages = <0x2000>; + sandbox,err-count = <1>; + sandbox,err-step-size = <512>; + }; + + /* MT29F64G08AKABA */ + nand@1 { + reg = <1>; + nand-ecc-mode = "soft_bch"; + sandbox,id = [2C 48 00 26 89 00 00 00]; + sandbox,onfi = [ + 4f 4e 46 49 0e 00 5a 00 + ff 01 00 00 00 00 03 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 4d 49 43 52 4f 4e 20 20 + 20 20 20 20 4d 54 32 39 + 46 36 34 47 30 38 41 4b + 41 42 41 43 35 20 20 20 + 2c 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 10 00 00 e0 00 00 02 + 00 00 1c 00 80 00 00 00 + 00 10 00 00 02 23 01 50 + 00 01 05 01 00 00 04 00 + 04 01 1e 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 0e 1f 00 1f 00 f4 01 ac + 0d 19 00 c8 00 00 00 00 + 00 00 00 00 00 00 0a 07 + 19 00 00 00 00 00 00 00 + 00 00 00 00 01 00 01 00 + 00 00 04 10 01 81 04 02 + 02 01 1e 90 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 03 20 7d + ]; + sandbox,erasesize = <(512 * 1024)>; + sandbox,oobsize = <224>; + sandbox,pagesize = <4096>; + sandbox,pages = <0x200000>; + sandbox,err-count = <3>; + sandbox,err-step-size = <512>; + }; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/barrier.h b/arch/sandbox/include/asm/barrier.h new file mode 100644 index 00000000000..0928a78cbf8 --- /dev/null +++ b/arch/sandbox/include/asm/barrier.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#define nop() diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h index df7156fe317..d4e04ad1486 100644 --- a/arch/sandbox/include/asm/clk.h +++ b/arch/sandbox/include/asm/clk.h @@ -6,7 +6,6 @@ #ifndef __SANDBOX_CLK_H #define __SANDBOX_CLK_H -#include <common.h> #include <clk.h> #include <dt-structs.h> #include <linux/clk-provider.h> @@ -39,6 +38,7 @@ enum sandbox_clk_test_id { SANDBOX_CLK_TEST_ID_FIXED, SANDBOX_CLK_TEST_ID_SPI, SANDBOX_CLK_TEST_ID_I2C, + SANDBOX_CLK_TEST_ID_I2C_ROOT, SANDBOX_CLK_TEST_ID_DEVM1, SANDBOX_CLK_TEST_ID_DEVM2, SANDBOX_CLK_TEST_ID_DEVM_NULL, diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 31ab7289b4b..77a02e5f524 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -28,20 +28,6 @@ void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags); void unmap_physmem(const void *vaddr, unsigned long flags); #define unmap_physmem unmap_physmem -#include <asm-generic/io.h> - -/* For sandbox, we want addresses to point into our RAM buffer */ -static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) -{ - return map_physmem(paddr, len, MAP_WRBACK); -} - -/* Remove a previous mapping */ -static inline void unmap_sysmem(const void *vaddr) -{ - unmap_physmem(vaddr, MAP_WRBACK); -} - /* Map from a pointer to our RAM buffer */ phys_addr_t map_to_sysmem(const void *ptr); @@ -229,5 +215,19 @@ static inline void memcpy_toio(volatile void *dst, const void *src, int count) #include <iotrace.h> #include <asm/types.h> +#include <asm-generic/io.h> + +/* For sandbox, we want addresses to point into our RAM buffer */ +static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) +{ + return map_physmem(paddr, len, MAP_WRBACK); +} + +/* Remove a previous mapping */ +static inline void unmap_sysmem(const void *vaddr) +{ + unmap_physmem(vaddr, MAP_WRBACK); +} + #endif diff --git a/arch/sandbox/include/asm/mbox.h b/arch/sandbox/include/asm/mbox.h index 70f36d7afef..499e9a67f6a 100644 --- a/arch/sandbox/include/asm/mbox.h +++ b/arch/sandbox/include/asm/mbox.h @@ -6,8 +6,6 @@ #ifndef __SANDBOX_MBOX_H #define __SANDBOX_MBOX_H -#include <common.h> - #define SANDBOX_MBOX_PING_XOR 0x12345678 struct udevice; diff --git a/arch/sandbox/include/asm/power-domain.h b/arch/sandbox/include/asm/power-domain.h index 1845bc8d3ba..4d5e861dbce 100644 --- a/arch/sandbox/include/asm/power-domain.h +++ b/arch/sandbox/include/asm/power-domain.h @@ -6,8 +6,6 @@ #ifndef __SANDBOX_POWER_DOMAIN_H #define __SANDBOX_POWER_DOMAIN_H -#include <common.h> - struct udevice; int sandbox_power_domain_query(struct udevice *dev, unsigned long id); diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h index 40d3e61c110..f0709b41c09 100644 --- a/arch/sandbox/include/asm/reset.h +++ b/arch/sandbox/include/asm/reset.h @@ -6,8 +6,6 @@ #ifndef __SANDBOX_RESET_H #define __SANDBOX_RESET_H -#include <common.h> - struct udevice; int sandbox_reset_query(struct udevice *dev, unsigned long id); diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h index f349ea19971..4fab24cd156 100644 --- a/arch/sandbox/include/asm/spl.h +++ b/arch/sandbox/include/asm/spl.h @@ -15,6 +15,7 @@ enum { BOOT_DEVICE_CPGMAC, BOOT_DEVICE_NOR, BOOT_DEVICE_SPI, + BOOT_DEVICE_NAND, }; /** diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index dc8b8e46cb4..a748ba650b1 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -78,3 +78,10 @@ int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *image return 0; } + +/* used for testing 'booti' command */ +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc) +{ + return 0; +} diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 178f8ad1816..085302c0482 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -27,5 +27,7 @@ config SYS_COREBOOT imply X86_TSC_READ_BASE imply USE_PREBOOT select BINMAN if X86_64 + select SYSINFO + imply SYSINFO_EXTRA endif diff --git a/arch/x86/cpu/u-boot-64.lds b/arch/x86/cpu/u-boot-64.lds index d0398ff00d7..00a6d869121 100644 --- a/arch/x86/cpu/u-boot-64.lds +++ b/arch/x86/cpu/u-boot-64.lds @@ -11,10 +11,6 @@ ENTRY(_start) SECTIONS { -#ifndef CONFIG_CMDLINE - /DISCARD/ : { *(__u_boot_list_2_cmd_*) } -#endif - #ifdef CONFIG_TEXT_BASE . = CONFIG_TEXT_BASE; /* Location of bootcode in flash */ #endif diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds index a0a2a06a18c..50b4b160855 100644 --- a/arch/x86/cpu/u-boot-spl.lds +++ b/arch/x86/cpu/u-boot-spl.lds @@ -11,10 +11,6 @@ ENTRY(_start) SECTIONS { -#ifndef CONFIG_CMDLINE - /DISCARD/ : { *(__u_boot_list_2_cmd_*) } -#endif - . = IMAGE_TEXT_BASE; /* Location of bootcode in flash */ __text_start = .; .text : { diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index a31f4220a00..c418ff44aa0 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -11,10 +11,6 @@ ENTRY(_start) SECTIONS { -#ifndef CONFIG_CMDLINE - /DISCARD/ : { *(__u_boot_list_2_cmd_*) } -#endif - . = CONFIG_TEXT_BASE; /* Location of bootcode in flash */ __text_start = .; diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index 0eb31cae42c..dfce7c2d591 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -45,4 +45,8 @@ bootph-some-ram; compatible = "coreboot-fb"; }; + + sysinfo { + compatible = "coreboot,sysinfo"; + }; }; diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 226753b65d6..57e41654ce3 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -65,15 +65,6 @@ int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, int acpi_create_gnvs(struct acpi_global_nvs *gnvs); /** - * acpi_get_rsdp_addr() - get ACPI RSDP table address - * - * This routine returns the ACPI RSDP table address in the system memory. - * - * @return: ACPI RSDP table address - */ -ulong acpi_get_rsdp_addr(void); - -/** * arch_read_sci_irq_select() - Read the system-control interrupt number * * @returns value of IRQ register in the PMC diff --git a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h index 05dd1b2b447..460bfc4f2d4 100644 --- a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h +++ b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h @@ -6,7 +6,6 @@ #ifndef __SLIMBOOTLOADER_ARCH_H__ #define __SLIMBOOTLOADER_ARCH_H__ -#include <common.h> #include <asm/hob.h> /** diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h index 8be1003e6ba..c79ec64afd7 100644 --- a/arch/x86/include/asm/dma-mapping.h +++ b/arch/x86/include/asm/dma-mapping.h @@ -7,7 +7,6 @@ #ifndef __ASM_X86_DMA_MAPPING_H #define __ASM_X86_DMA_MAPPING_H -#include <common.h> #include <asm/cache.h> #include <cpu_func.h> #include <linux/dma-direction.h> diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 83dc09757e0..5efb2e1b21e 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -202,10 +202,16 @@ __OUT(l,,int) __INS(b) __INS(w) __INS(l) +#define insb insb +#define insw insw +#define insl insl __OUTS(b) __OUTS(w) __OUTS(l) +#define outsb outsb +#define outsw outsw +#define outsl outsl /* IO space accessors */ #define clrio(type, addr, clear) \ diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h index 76a646e8825..87ad9faa299 100644 --- a/arch/xtensa/include/asm/io.h +++ b/arch/xtensa/include/asm/io.h @@ -76,6 +76,12 @@ void insl(unsigned long port, void *dst, unsigned long count); void outsb(unsigned long port, const void *src, unsigned long count); void outsw(unsigned long port, const void *src, unsigned long count); void outsl(unsigned long port, const void *src, unsigned long count); +#define insb insb +#define insw insw +#define insl insl +#define outsb outsb +#define outsw outsw +#define outsl outsl #define IO_SPACE_LIMIT ~0 diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 63b86992194..3489bdd74bd 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -562,7 +562,7 @@ static void handle_reset_button(void) } } -int show_board_info(void) +int checkboard(void) { int i, ret, board_version, ram_size, is_sd; const char *pub_key, *model; diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 19c5043fcba..adeb69a205b 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -962,7 +962,7 @@ int board_late_init(void) return 0; } -int show_board_info(void) +int checkboard(void) { char serial[17]; int err; diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig index 47d9bae9468..f935cce4225 100644 --- a/board/asus/grouper/Kconfig +++ b/board/asus/grouper/Kconfig @@ -9,12 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "grouper" -config GROUPER_TPS65911 - bool "Enable support TI TPS65911 PMIC" - select CMD_POWEROFF - -config GROUPER_MAX77663 - bool "Enable support MAXIM MAX77663 PMIC" - select CMD_POWEROFF - endif diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile index e4a477a3669..d041cf80870 100644 --- a/board/asus/grouper/Makefile +++ b/board/asus/grouper/Makefile @@ -7,8 +7,8 @@ # Svyatoslav Ryhel <clamor95@gmail.com> ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_GROUPER_MAX77663) += grouper-spl-max.o -obj-$(CONFIG_GROUPER_TPS65911) += grouper-spl-ti.o +obj-$(CONFIG_DM_PMIC_MAX77663) += grouper-spl-max.o +obj-$(CONFIG_DM_PMIC_TPS65910) += grouper-spl-ti.o endif obj-y += grouper.o diff --git a/board/asus/grouper/configs/grouper_E1565.config b/board/asus/grouper/configs/grouper_E1565.config index 4d8d5263fa9..265295c8b3e 100644 --- a/board/asus/grouper/configs/grouper_E1565.config +++ b/board/asus/grouper/configs/grouper_E1565.config @@ -1,2 +1,6 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565" -CONFIG_GROUPER_MAX77663=y +CONFIG_CMD_POWEROFF=y +# CONFIG_MAX77663_GPIO is not set +CONFIG_DM_PMIC_MAX77663=y +CONFIG_DM_REGULATOR_MAX77663=y +CONFIG_SYSRESET_MAX77663=y diff --git a/board/asus/grouper/configs/grouper_PM269.config b/board/asus/grouper/configs/grouper_PM269.config index fc768b20517..a7ee3587edd 100644 --- a/board/asus/grouper/configs/grouper_PM269.config +++ b/board/asus/grouper/configs/grouper_PM269.config @@ -1,2 +1,6 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-PM269" -CONFIG_GROUPER_TPS65911=y +CONFIG_CMD_POWEROFF=y +CONFIG_DM_PMIC_TPS65910=y +# CONFIG_DM_REGULATOR_TPS65910 is not set +CONFIG_DM_REGULATOR_TPS65911=y +CONFIG_SYSRESET_TPS65910=y diff --git a/board/asus/grouper/configs/tilapia.config b/board/asus/grouper/configs/tilapia.config index 1fb0633e3a7..d461b4752a9 100644 --- a/board/asus/grouper/configs/tilapia.config +++ b/board/asus/grouper/configs/tilapia.config @@ -1,3 +1,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-tilapia-E1565" -CONFIG_GROUPER_MAX77663=y CONFIG_SYS_PROMPT="Tegra30 (Tilapia) # " +CONFIG_CMD_POWEROFF=y +# CONFIG_MAX77663_GPIO is not set +CONFIG_DM_PMIC_MAX77663=y +CONFIG_DM_REGULATOR_MAX77663=y +CONFIG_SYSRESET_MAX77663=y diff --git a/board/asus/grouper/grouper-spl-max.c b/board/asus/grouper/grouper-spl-max.c index 844383766a7..3e58bf97cc4 100644 --- a/board/asus/grouper/grouper-spl-max.c +++ b/board/asus/grouper/grouper-spl-max.c @@ -9,7 +9,7 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> +#include <asm/arch/tegra.h> #include <asm/arch-tegra/tegra_i2c.h> #include <linux/delay.h> diff --git a/board/asus/grouper/grouper-spl-ti.c b/board/asus/grouper/grouper-spl-ti.c index e5b78f01215..1dcce80b48c 100644 --- a/board/asus/grouper/grouper-spl-ti.c +++ b/board/asus/grouper/grouper-spl-ti.c @@ -9,7 +9,7 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> +#include <asm/arch/tegra.h> #include <asm/arch-tegra/tegra_i2c.h> #include <linux/delay.h> diff --git a/board/asus/grouper/grouper.c b/board/asus/grouper/grouper.c index 5398ec8b9f8..dc1d1102c3f 100644 --- a/board/asus/grouper/grouper.c +++ b/board/asus/grouper/grouper.c @@ -7,105 +7,12 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> #include <dm.h> #include <fdt_support.h> -#include <i2c.h> -#include <log.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> -#include <asm/arch/gpio.h> -#include <asm/gpio.h> -#include <linux/delay.h> -#include "pinmux-config-grouper.h" - -#define TPS65911_I2C_ADDRESS 0x2D - -#define TPS65911_REG_LDO1 0x30 -#define TPS65911_REG_DEVCTRL 0x3F -#define DEVCTRL_PWR_OFF_MASK BIT(7) -#define DEVCTRL_DEV_ON_MASK BIT(2) -#define DEVCTRL_DEV_OFF_MASK BIT(0) - -#define MAX77663_I2C_ADDRESS 0x3C - -#define MAX77663_REG_SD2 0x18 -#define MAX77663_REG_LDO3 0x29 -#define MAX77663_REG_ONOFF_CFG1 0x41 -#define ONOFF_PWR_OFF BIT(1) - -#ifdef CONFIG_CMD_POWEROFF -#ifdef CONFIG_GROUPER_TPS65911 -int do_poweroff(struct cmd_tbl *cmdtp, - int flag, int argc, char *const argv[]) -{ - struct udevice *dev; - uchar data_buffer[1]; - int ret; - - ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return 0; - } - - ret = dm_i2c_read(dev, TPS65911_REG_DEVCTRL, data_buffer, 1); - if (ret) - return ret; - - data_buffer[0] |= DEVCTRL_PWR_OFF_MASK; - - ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1); - if (ret) - return ret; - - data_buffer[0] |= DEVCTRL_DEV_OFF_MASK; - data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK; - - ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1); - if (ret) - return ret; - - // wait some time and then print error - mdelay(5000); - - printf("Failed to power off!!!\n"); - return 1; -} -#endif /* CONFIG_GROUPER_TPS65911 */ - -#ifdef CONFIG_GROUPER_MAX77663 -int do_poweroff(struct cmd_tbl *cmdtp, - int flag, int argc, char *const argv[]) -{ - struct udevice *dev; - uchar data_buffer[1]; - int ret; - - ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return 0; - } - - ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); - if (ret) - return ret; - - data_buffer[0] |= ONOFF_PWR_OFF; - - ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); - if (ret) - return ret; - // wait some time and then print error - mdelay(5000); - - printf("Failed to power off!!!\n"); - return 1; -} -#endif /* CONFIG_GROUPER_MAX77663 */ -#endif /* CONFIG_CMD_POWEROFF */ +#include "pinmux-config-grouper.h" /* * Routine: pinmux_init @@ -120,64 +27,6 @@ void pinmux_init(void) ARRAY_SIZE(grouper_padctrl)); } -#ifdef CONFIG_MMC_SDHCI_TEGRA -static void __maybe_unused tps65911_voltage_init(void) -{ - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return; - } - - /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */ - ret = dm_i2c_reg_write(dev, TPS65911_REG_LDO1, 0xC9); - if (ret) - log_debug("vcore_emmc set failed: %d\n", ret); -} - -static void __maybe_unused max77663_voltage_init(void) -{ - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return; - } - - /* 0x60 for 1.8v, bit7:0 = voltage */ - ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60); - if (ret) - log_debug("vdd_1v8_vio set failed: %d\n", ret); - - /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC); - if (ret) - log_debug("vcore_emmc set failed: %d\n", ret); -} - -/* - * Routine: pin_mux_mmc - * Description: setup the MMC muxes, power rails, etc. - */ -void pin_mux_mmc(void) -{ -#ifdef CONFIG_GROUPER_MAX77663 - /* Bring up eMMC power on MAX PMIC */ - max77663_voltage_init(); -#endif - -#ifdef CONFIG_GROUPER_TPS65911 - /* Bring up eMMC power on TI PMIC */ - tps65911_voltage_init(); -#endif -} -#endif /* MMC */ - #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig index accc999c435..915436ba6c5 100644 --- a/board/asus/transformer-t30/Kconfig +++ b/board/asus/transformer-t30/Kconfig @@ -9,14 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "transformer-t30" -config TRANSFORMER_SPI_BOOT - bool "Enable support for SPI based flash" - select TEGRA20_SLINK - select DM_SPI_FLASH - select SPI_FLASH_WINBOND - help - Tegra 3 based Transformers with Windows RT have core - boot sequence (BCT and EBT) on separate SPI FLASH - memory with 4MB size. - endif diff --git a/board/asus/transformer-t30/configs/tf600t.config b/board/asus/transformer-t30/configs/tf600t.config index 18ab4fbd878..e40d0fdd479 100644 --- a/board/asus/transformer-t30/configs/tf600t.config +++ b/board/asus/transformer-t30/configs/tf600t.config @@ -1,4 +1,4 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t" -CONFIG_TRANSFORMER_SPI_BOOT=y CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" +CONFIG_SPI_FLASH_WINBOND=y CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/transformer-t30-spl.c b/board/asus/transformer-t30/transformer-t30-spl.c index 89819b2b921..952e2c82241 100644 --- a/board/asus/transformer-t30/transformer-t30-spl.c +++ b/board/asus/transformer-t30/transformer-t30-spl.c @@ -9,7 +9,7 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> +#include <asm/arch/tegra.h> #include <asm/arch-tegra/tegra_i2c.h> #include <linux/delay.h> diff --git a/board/asus/transformer-t30/transformer-t30.c b/board/asus/transformer-t30/transformer-t30.c index ba795a802eb..7cac6fde6f4 100644 --- a/board/asus/transformer-t30/transformer-t30.c +++ b/board/asus/transformer-t30/transformer-t30.c @@ -9,70 +9,12 @@ /* T30 Transformers derive from Cardhu board */ -#include <common.h> #include <dm.h> #include <fdt_support.h> -#include <i2c.h> -#include <log.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> -#include <asm/arch/gpio.h> -#include <asm/gpio.h> -#include <linux/delay.h> -#include "pinmux-config-transformer.h" - -#define TPS65911_I2C_ADDRESS 0x2D - -#define TPS65911_VDD1 0x21 -#define TPS65911_VDD1_OP 0x22 -#define TPS65911_LDO1 0x30 -#define TPS65911_LDO2 0x31 -#define TPS65911_LDO3 0x37 -#define TPS65911_LDO5 0x32 -#define TPS65911_LDO6 0x35 - -#define TPS65911_DEVCTRL 0x3F -#define DEVCTRL_PWR_OFF_MASK BIT(7) -#define DEVCTRL_DEV_ON_MASK BIT(2) -#define DEVCTRL_DEV_OFF_MASK BIT(0) - -#ifdef CONFIG_CMD_POWEROFF -int do_poweroff(struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]) -{ - struct udevice *dev; - uchar data_buffer[1]; - int ret; - - ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return 0; - } - - ret = dm_i2c_read(dev, TPS65911_DEVCTRL, data_buffer, 1); - if (ret) - return ret; - data_buffer[0] |= DEVCTRL_PWR_OFF_MASK; - - ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1); - if (ret) - return ret; - - data_buffer[0] |= DEVCTRL_DEV_OFF_MASK; - data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK; - - ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1); - if (ret) - return ret; - - // wait some time and then print error - mdelay(5000); - printf("Failed to power off!!!\n"); - return 1; -} -#endif +#include "pinmux-config-transformer.h" /* * Routine: pinmux_init @@ -92,66 +34,6 @@ void pinmux_init(void) } } -#ifdef CONFIG_MMC_SDHCI_TEGRA -static void tps65911_voltage_init(void) -{ - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return; - } - - /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */ - ret = dm_i2c_reg_write(dev, TPS65911_LDO1, 0xc9); - if (ret) - log_debug("vcore_emmc set failed: %d\n", ret); - - if (of_machine_is_compatible("asus,tf600t")) { - /* TPS659110: VDD1_REG = 1.2v, ACTIVE to backlight */ - ret = dm_i2c_reg_write(dev, TPS65911_VDD1_OP, 0x33); - if (ret) - log_debug("vdd_bl set failed: %d\n", ret); - - ret = dm_i2c_reg_write(dev, TPS65911_VDD1, 0x0d); - if (ret) - log_debug("vdd_bl enable failed: %d\n", ret); - - /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 VIO */ - ret = dm_i2c_reg_write(dev, TPS65911_LDO5, 0x65); - if (ret) - log_debug("vdd_usd set failed: %d\n", ret); - - /* TPS659110: LDO6_REG = 1.2v, ACTIVE to MIPI */ - ret = dm_i2c_reg_write(dev, TPS65911_LDO6, 0x11); - if (ret) - log_debug("vdd_mipi set failed: %d\n", ret); - } else { - /* TPS659110: LDO2_REG = 3.1v, ACTIVE to SDMMC1 */ - ret = dm_i2c_reg_write(dev, TPS65911_LDO2, 0xb9); - if (ret) - log_debug("vdd_usd set failed: %d\n", ret); - - /* TPS659110: LDO3_REG = 3.1v, ACTIVE to SDMMC1 VIO */ - ret = dm_i2c_reg_write(dev, TPS65911_LDO3, 0x5d); - if (ret) - log_debug("vddio_usd set failed: %d\n", ret); - } -} - -/* - * Routine: pin_mux_mmc - * Description: setup the MMC muxes, power rails, etc. - */ -void pin_mux_mmc(void) -{ - /* Bring up uSD and eMMC power */ - tps65911_voltage_init(); -} -#endif /* MMC */ - #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/ti/beagle/Kconfig b/board/beagle/beagle/Kconfig index c2eff9e71b0..eade599dc93 100644 --- a/board/ti/beagle/Kconfig +++ b/board/beagle/beagle/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "beagle" config SYS_VENDOR - default "ti" + default "beagle" config SYS_CONFIG_NAME default "omap3_beagle" diff --git a/board/ti/beagle/MAINTAINERS b/board/beagle/beagle/MAINTAINERS index c1d81d4174e..c7fa87acfcc 100644 --- a/board/ti/beagle/MAINTAINERS +++ b/board/beagle/beagle/MAINTAINERS @@ -1,6 +1,6 @@ BEAGLE BOARD M: Tom Rini <trini@konsulko.com> S: Maintained -F: board/ti/beagle/ +F: board/beagle/beagle/ F: include/configs/omap3_beagle.h F: configs/omap3_beagle_defconfig diff --git a/board/ti/beagle/Makefile b/board/beagle/beagle/Makefile index fc9288cf186..fc9288cf186 100644 --- a/board/ti/beagle/Makefile +++ b/board/beagle/beagle/Makefile diff --git a/board/ti/beagle/beagle.c b/board/beagle/beagle/beagle.c index 847d596646e..847d596646e 100644 --- a/board/ti/beagle/beagle.c +++ b/board/beagle/beagle/beagle.c diff --git a/board/ti/beagle/beagle.h b/board/beagle/beagle/beagle.h index ce78ea661b9..ce78ea661b9 100644 --- a/board/ti/beagle/beagle.h +++ b/board/beagle/beagle/beagle.h diff --git a/board/ti/beagle/led.c b/board/beagle/beagle/led.c index e21c0169db7..e21c0169db7 100644 --- a/board/ti/beagle/led.c +++ b/board/beagle/beagle/led.c diff --git a/board/beagle/beagleboneai64/Kconfig b/board/beagle/beagleboneai64/Kconfig new file mode 100644 index 00000000000..7cfccf9baf0 --- /dev/null +++ b/board/beagle/beagleboneai64/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation +# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation +# + +choice + prompt "BeagleBoard.org J721E/TDA4VM based BeagleBone AI-64 board" + optional + +config TARGET_J721E_A72_BEAGLEBONEAI64 + bool "BeagleBoard.org J721E BeagleBone AI-64 running on A72" + select ARM64 + select SYS_DISABLE_DCACHE_OPS + select BINMAN + +config TARGET_J721E_R5_BEAGLEBONEAI64 + bool "BeagleBoard.org J721E BeagleBone AI-64 running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_J721E_A72_BEAGLEBONEAI64 + +config SYS_BOARD + default "beagleboneai64" + +config SYS_VENDOR + default "beagle" + +config SYS_CONFIG_NAME + default "j721e_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_J721E_R5_BEAGLEBONEAI64 + +config SYS_BOARD + default "beagleboneai64" + +config SYS_VENDOR + default "beagle" + +config SYS_CONFIG_NAME + default "j721e_evm" + +source "board/ti/common/Kconfig" + +endif diff --git a/board/beagle/beagleboneai64/MAINTAINERS b/board/beagle/beagleboneai64/MAINTAINERS new file mode 100644 index 00000000000..5866dcd833a --- /dev/null +++ b/board/beagle/beagleboneai64/MAINTAINERS @@ -0,0 +1,6 @@ +BEAGLEBONE-AI64 BOARD +M: Nishanth Menon <nm@ti.com> +M: Robert Nelson <robertcnelson@gmail.com> +M: Tom Rini <trini@konsulko.com> +S: Maintained +N: beagleboneai64 diff --git a/board/beagle/beagleboneai64/Makefile b/board/beagle/beagleboneai64/Makefile new file mode 100644 index 00000000000..f2a2526ae75 --- /dev/null +++ b/board/beagle/beagleboneai64/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# https://beagleboard.org/ai-64 +# +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation +# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation +# + +obj-y += beagleboneai64.o diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c new file mode 100644 index 00000000000..c8c1c78ae5a --- /dev/null +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleboard.org/ai-64 + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +#include <cpu_func.h> +#include <env.h> +#include <fdt_support.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/board/ti/am62x/beagleplay.env b/board/beagle/beagleboneai64/beagleboneai64.env index 4f0a94a8113..4f0a94a8113 100644 --- a/board/ti/am62x/beagleplay.env +++ b/board/beagle/beagleboneai64/beagleboneai64.env diff --git a/board/beagle/beagleboneai64/board-cfg.yaml b/board/beagle/beagleboneai64/board-cfg.yaml new file mode 100644 index 00000000000..1375dcad357 --- /dev/null +++ b/board/beagle/beagleboneai64/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J721E +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/beagle/beagleboneai64/pm-cfg.yaml b/board/beagle/beagleboneai64/pm-cfg.yaml new file mode 100644 index 00000000000..7ae52b3358e --- /dev/null +++ b/board/beagle/beagleboneai64/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for J721E +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/beagle/beagleboneai64/rm-cfg.yaml b/board/beagle/beagleboneai64/rm-cfg.yaml new file mode 100644 index 00000000000..9f604cf1aa6 --- /dev/null +++ b/board/beagle/beagleboneai64/rm-cfg.yaml @@ -0,0 +1,3174 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for J721E +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - #1 + host_id: 3 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 5 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 13 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #5 + host_id: 21 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #6 + host_id: 26 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #7 + host_id: 28 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #8 + host_id: 35 + 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15168 + host_id: 5 + reserved: 0 diff --git a/board/beagle/beagleboneai64/sec-cfg.yaml b/board/beagle/beagleboneai64/sec-cfg.yaml new file mode 100644 index 00000000000..1eab5883a78 --- /dev/null +++ b/board/beagle/beagleboneai64/sec-cfg.yaml @@ -0,0 +1,380 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for J721E +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + write_host_id: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0 + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig new file mode 100644 index 00000000000..7dbd833acb4 --- /dev/null +++ b/board/beagle/beagleplay/Kconfig @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation +# + +choice + prompt "BeagleBoard.org AM625 based BeaglePlay board" + optional + +config TARGET_AM625_A53_BEAGLEPLAY + bool "BeagleBoard.org AM625 BeaglePlay running on A53" + select ARM64 + select BINMAN + +config TARGET_AM625_R5_BEAGLEPLAY + bool "BeagleBoard.org AM625 BeaglePlay running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_AM625_A53_BEAGLEPLAY + +config SYS_BOARD + default "beagleplay" + +config SYS_VENDOR + default "beagle" + +config SYS_CONFIG_NAME + default "am62x_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_AM625_R5_BEAGLEPLAY + +config SYS_BOARD + default "beagleplay" + +config SYS_VENDOR + default "beagle" + +config SYS_CONFIG_NAME + default "am62x_evm" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +source "board/ti/common/Kconfig" + +endif diff --git a/board/beagle/beagleplay/MAINTAINERS b/board/beagle/beagleplay/MAINTAINERS new file mode 100644 index 00000000000..eed996a23dd --- /dev/null +++ b/board/beagle/beagleplay/MAINTAINERS @@ -0,0 +1,6 @@ +BEAGLEPLAY BOARD +M: Nishanth Menon <nm@ti.com> +M: Robert Nelson <robertcnelson@gmail.com> +M: Tom Rini <trini@konsulko.com> +S: Maintained +N: beagleplay diff --git a/board/beagle/beagleplay/Makefile b/board/beagle/beagleplay/Makefile new file mode 100644 index 00000000000..b7a3cdb2451 --- /dev/null +++ b/board/beagle/beagleplay/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# https://beagleboard.org/play +# +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation +# + +obj-y += beagleplay.o diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c new file mode 100644 index 00000000000..1c376dea372 --- /dev/null +++ b/board/beagle/beagleplay/beagleplay.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleplay.org/ + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +#include <cpu_func.h> +#include <env.h> +#include <fdt_support.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env new file mode 100644 index 00000000000..4f0a94a8113 --- /dev/null +++ b/board/beagle/beagleplay/beagleplay.env @@ -0,0 +1,19 @@ +#include <env/ti/ti_common.env> +#include <env/ti/default_findfdt.env> +#include <env/ti/mmc.env> + +name_kern=Image +console=ttyS2,115200n8 +args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 +run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} +set_led_state_fail_load= led led-0 off; led led-1 on; + led led-2 off; led led-3 on; led led-4 off +set_led_state_start_load=led led-0 on; led led-1 off; + led led-2 on; led led-3 off; led led-4 on +boot=mmc +mmcdev=1 +bootpart=1:1 +bootdir=/boot +boot_targets=mmc1 mmc0 usb pxe +bootmeths=script extlinux efi pxe +rd_spec=- diff --git a/board/beagle/beagleplay/board-cfg.yaml b/board/beagle/beagleplay/board-cfg.yaml new file mode 100644 index 00000000000..36cfb550adf --- /dev/null +++ b/board/beagle/beagleplay/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62 +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable : 0x5A + main_isolation_hostid : 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor : 0x1 + scaling_profile : 0x1 + disable_main_nav_secure_proxy : 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size : 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables : 0x00 + trace_src_enables : 0x00 diff --git a/board/beagle/beagleplay/pm-cfg.yaml b/board/beagle/beagleplay/pm-cfg.yaml new file mode 100644 index 00000000000..5d04cf82ef7 --- /dev/null +++ b/board/beagle/beagleplay/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62 +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 diff --git a/board/beagle/beagleplay/rm-cfg.yaml b/board/beagle/beagleplay/rm-cfg.yaml new file mode 100644 index 00000000000..c28707be8e2 --- /dev/null +++ b/board/beagle/beagleplay/rm-cfg.yaml @@ -0,0 +1,1088 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62 +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #2 + host_id: 30 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #3 + host_id: 36 + allowed_atype : 0x2A + allowed_qos : 0xAAAA + allowed_orderid : 0xAAAAAAAA + allowed_priority : 0xAAAA + allowed_sched_priority : 0xAA + - #4 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #5 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #6 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #7 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #8 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #9 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #10 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #11 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #12 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #13 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #14 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #15 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #16 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #17 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #18 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #19 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #20 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #21 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #22 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #23 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #24 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #25 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #26 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #27 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #28 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #29 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #30 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #31 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + - #32 + host_id: 0 + allowed_atype : 0 + allowed_qos : 0 + allowed_orderid : 0 + allowed_priority : 0 + allowed_sched_priority : 0 + resasg: + subhdr: + magic: 0x7B25 + size : 8 + resasg_entries_size: 960 + reserved : 0 + resasg_entries: + - + start_resource: 0 + num_resource: 16 + type: 64 + host_id: 12 + reserved: 0 + + - + start_resource: 16 + num_resource: 4 + type: 64 + host_id: 35 + reserved: 0 + + - + start_resource: 16 + num_resource: 4 + type: 64 + host_id: 36 + reserved: 0 + + - + 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num_resource: 22 + type: 1817 + host_id: 128 + reserved: 0 + + - + start_resource: 10240 + num_resource: 22 + type: 1818 + host_id: 128 + reserved: 0 + + - + start_resource: 10752 + num_resource: 22 + type: 1819 + host_id: 128 + reserved: 0 + + - + start_resource: 11264 + num_resource: 28 + type: 1820 + host_id: 128 + reserved: 0 + + - + start_resource: 11776 + num_resource: 28 + type: 1821 + host_id: 128 + reserved: 0 + + - + start_resource: 12288 + num_resource: 28 + type: 1822 + host_id: 128 + reserved: 0 + + - + start_resource: 0 + num_resource: 1 + type: 1923 + host_id: 128 + reserved: 0 + + - + start_resource: 0 + num_resource: 10 + type: 1936 + host_id: 12 + reserved: 0 + + - + start_resource: 10 + num_resource: 3 + type: 1936 + host_id: 35 + reserved: 0 + + - + start_resource: 10 + num_resource: 3 + type: 1936 + host_id: 36 + reserved: 0 + + - + start_resource: 13 + num_resource: 3 + type: 1936 + host_id: 30 + reserved: 0 + + - + start_resource: 16 + num_resource: 3 + type: 1936 + host_id: 128 + reserved: 0 + + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 12 + reserved: 0 + + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 36 + reserved: 0 + + - + start_resource: 83 + num_resource: 8 + type: 1938 + host_id: 12 + reserved: 0 + + - + start_resource: 91 + num_resource: 8 + type: 1939 + host_id: 12 + reserved: 0 + + - + start_resource: 99 + num_resource: 10 + type: 1942 + host_id: 12 + reserved: 0 + + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 35 + reserved: 0 + + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 36 + reserved: 0 + + - + start_resource: 112 + num_resource: 3 + type: 1942 + host_id: 30 + reserved: 0 + + - + start_resource: 115 + num_resource: 3 + type: 1942 + host_id: 128 + reserved: 0 + + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 12 + reserved: 0 + + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 36 + reserved: 0 + + - + start_resource: 134 + num_resource: 8 + type: 1944 + host_id: 12 + reserved: 0 + + - + start_resource: 134 + num_resource: 8 + type: 1945 + host_id: 12 + reserved: 0 + + - + start_resource: 142 + num_resource: 8 + type: 1946 + host_id: 12 + reserved: 0 + + - + start_resource: 142 + num_resource: 8 + type: 1947 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 10 + type: 1955 + host_id: 12 + reserved: 0 + + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 35 + reserved: 0 + + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 36 + reserved: 0 + + - + start_resource: 13 + num_resource: 3 + type: 1955 + host_id: 30 + reserved: 0 + + - + start_resource: 16 + num_resource: 3 + type: 1955 + host_id: 128 + reserved: 0 + + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 12 + reserved: 0 + + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 36 + reserved: 0 + + - + start_resource: 27 + num_resource: 1 + type: 1957 + host_id: 12 + reserved: 0 + + - + start_resource: 28 + num_resource: 1 + type: 1958 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 10 + type: 1961 + host_id: 12 + reserved: 0 + + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 35 + reserved: 0 + + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 36 + reserved: 0 + + - + start_resource: 13 + num_resource: 3 + type: 1961 + host_id: 30 + reserved: 0 + + - + start_resource: 16 + num_resource: 3 + type: 1961 + host_id: 128 + reserved: 0 + + - + start_resource: 0 + num_resource: 10 + type: 1962 + host_id: 12 + reserved: 0 + + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 35 + reserved: 0 + + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 36 + reserved: 0 + + - + start_resource: 13 + num_resource: 3 + type: 1962 + host_id: 30 + reserved: 0 + + - + start_resource: 16 + num_resource: 3 + type: 1962 + host_id: 128 + reserved: 0 + + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 12 + reserved: 0 + + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 36 + reserved: 0 + + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 12 + reserved: 0 + + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 36 + reserved: 0 + + - + start_resource: 20 + num_resource: 1 + type: 1965 + host_id: 12 + reserved: 0 + + - + start_resource: 35 + num_resource: 8 + type: 1966 + host_id: 12 + reserved: 0 + + - + start_resource: 21 + num_resource: 1 + type: 1967 + host_id: 12 + reserved: 0 + + - + start_resource: 35 + num_resource: 8 + type: 1968 + host_id: 12 + reserved: 0 + + - + start_resource: 22 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 + + - + start_resource: 43 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 + + - + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + + - + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 diff --git a/board/beagle/beagleplay/sec-cfg.yaml b/board/beagle/beagleplay/sec-cfg.yaml new file mode 100644 index 00000000000..07081ce06ca --- /dev/null +++ b/board/beagle/beagleplay/sec-cfg.yaml @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security management configuration for AM62 +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id : 0 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci : 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size : 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock : 0x5A + allow_wildcard_unlock : 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev : 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender : 0 + handover_to_host_id : 0 + rsvd: [0, 0, 0, 0] diff --git a/board/bsh/imx8mn_smm_s2/MAINTAINERS b/board/bsh/imx8mn_smm_s2/MAINTAINERS index 1de816ca871..c7898278359 100644 --- a/board/bsh/imx8mn_smm_s2/MAINTAINERS +++ b/board/bsh/imx8mn_smm_s2/MAINTAINERS @@ -1,5 +1,4 @@ ARM i.MX8MN BSH SMM S2 BOARDS -M: Ariel D'Alessandro <ariel.dalessandro@collabora.com> M: Michael Trimarchi <michael@amarulasolutions.com> S: Maintained F: arch/arm/dts/imx8mn-bsh-smm-s2* diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index d292b7032c2..75bfbd18943 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -11,3 +11,4 @@ # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. obj-y += coreboot.o +obj-$(CONFIG_$(SPL_TPL_)SMBIOS_PARSER) += sysinfo.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index db855c11ae6..e58dce37477 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -23,50 +23,6 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_SMBIOS_PARSER -int show_board_info(void) -{ - const struct smbios_entry *smbios = smbios_entry(lib_sysinfo.smbios_start, lib_sysinfo.smbios_size); - - if (!smbios) - goto fallback; - - const struct smbios_header *bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION); - const struct smbios_header *system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION); - const struct smbios_type0 *t0 = (struct smbios_type0 *)bios; - const struct smbios_type1 *t1 = (struct smbios_type1 *)system; - - if (!t0 || !t1) - goto fallback; - - const char *bios_ver = smbios_string(bios, t0->bios_ver); - const char *bios_date = smbios_string(bios, t0->bios_release_date); - const char *model = smbios_string(system, t1->product_name); - const char *manufacturer = smbios_string(system, t1->manufacturer); - - if (!model || !manufacturer || !bios_ver) - goto fallback; - - printf("Vendor: %s\n", manufacturer); - printf("Model: %s\n", model); - printf("BIOS Version: %s\n", bios_ver); - if (bios_date) - printf("BIOS date: %s\n", bios_date); - - return 0; - -fallback: - if (IS_ENABLED(CONFIG_OF_CONTROL)) { - model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - - if (model) - printf("Model: %s\n", model); - } - - return checkboard(); -} -#endif - static struct splash_location coreboot_splash_locations[] = { { .name = "virtio_fs", diff --git a/board/coreboot/coreboot/sysinfo.c b/board/coreboot/coreboot/sysinfo.c new file mode 100644 index 00000000000..e0bdc7a5a88 --- /dev/null +++ b/board/coreboot/coreboot/sysinfo.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * coreboot sysinfo driver + * + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <dm.h> +#include <smbios.h> +#include <sysinfo.h> +#include <asm/cb_sysinfo.h> + +struct cb_sysinfo_priv { + const struct smbios_header *bios; + const struct smbios_header *system; + const struct smbios_type0 *t0; + const struct smbios_type1 *t1; +}; + +static int cb_get_str(struct udevice *dev, int id, size_t size, char *val) +{ + struct cb_sysinfo_priv *priv = dev_get_priv(dev); + const char *str = NULL; + + switch (id) { + case SYSINFO_ID_BOARD_MODEL: + if (priv->t1) + str = smbios_string(priv->system, + priv->t1->product_name); + break; + case SYSINFO_ID_BOARD_MANUFACTURER: + if (priv->t1) + str = smbios_string(priv->system, + priv->t1->manufacturer); + break; + case SYSINFO_ID_PRIOR_STAGE_VERSION: + if (priv->t0) + str = smbios_string(priv->bios, priv->t0->bios_ver); + break; + case SYSINFO_ID_PRIOR_STAGE_DATE: + if (priv->t0) + str = smbios_string(priv->bios, + priv->t0->bios_release_date); + break; + } + if (!str) + return -ENOTSUPP; + + strlcpy(val, str, size); + + return 0; +} + +static int cb_detect(struct udevice *dev) +{ + struct cb_sysinfo_priv *priv = dev_get_priv(dev); + const struct smbios_entry *smbios; + + smbios = smbios_entry(lib_sysinfo.smbios_start, + lib_sysinfo.smbios_size); + if (!smbios) + return 0; + + priv->bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION); + priv->system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION); + priv->t0 = (struct smbios_type0 *)priv->bios; + priv->t1 = (struct smbios_type1 *)priv->system; + + return 0; +} + +static const struct udevice_id sysinfo_coreboot_ids[] = { + { .compatible = "coreboot,sysinfo" }, + { /* sentinel */ } +}; + +static const struct sysinfo_ops sysinfo_coreboot_ops = { + .detect = cb_detect, + .get_str = cb_get_str, +}; + +U_BOOT_DRIVER(sysinfo_coreboot) = { + .name = "sysinfo_coreboot", + .id = UCLASS_SYSINFO, + .of_match = sysinfo_coreboot_ids, + .ops = &sysinfo_coreboot_ops, + .priv_auto = sizeof(struct cb_sysinfo_priv), +}; diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index 5e6aa8b8cfa..e11cfafaa58 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -9,7 +9,6 @@ */ #include <env.h> -#include <common.h> #include <mpc8xx.h> #include <asm/cpm_8xx.h> #include <asm/io.h> diff --git a/board/cssi/cmpc885/nand.c b/board/cssi/cmpc885/nand.c index 38100046df8..b8989f226b0 100644 --- a/board/cssi/cmpc885/nand.c +++ b/board/cssi/cmpc885/nand.c @@ -7,7 +7,6 @@ */ #include <config.h> -#include <common.h> #include <nand.h> #include <linux/bitops.h> #include <linux/mtd/rawnand.h> diff --git a/board/cssi/cmpc885/sdram.c b/board/cssi/cmpc885/sdram.c index 7349b85ed2a..11a50c3a52d 100644 --- a/board/cssi/cmpc885/sdram.c +++ b/board/cssi/cmpc885/sdram.c @@ -4,13 +4,14 @@ * Charles Frey <charles.frey@c-s.fr> */ -#include <common.h> #include <linux/sizes.h> #include <linux/delay.h> #include <init.h> #include <asm/io.h> #include <mpc8xx.h> #include <watchdog.h> +#include <asm/ppc.h> +#include <asm/immap_8xx.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/cssi/cmpcpro/cmpcpro.c b/board/cssi/cmpcpro/cmpcpro.c index 8a30c48e35b..ef304124564 100644 --- a/board/cssi/cmpcpro/cmpcpro.c +++ b/board/cssi/cmpcpro/cmpcpro.c @@ -4,7 +4,6 @@ */ #include <command.h> -#include <common.h> #include <dm.h> #include <env.h> #include <env_internal.h> diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c index 3514f674901..8857c9e42c7 100644 --- a/board/cssi/mcr3000/mcr3000.c +++ b/board/cssi/mcr3000/mcr3000.c @@ -7,7 +7,6 @@ * Board specific routines for the MCR3000 board */ -#include <common.h> #include <env.h> #include <hwconfig.h> #include <init.h> diff --git a/board/cssi/mcr3000/nand.c b/board/cssi/mcr3000/nand.c index 11aca4ff736..5b01d30fef1 100644 --- a/board/cssi/mcr3000/nand.c +++ b/board/cssi/mcr3000/nand.c @@ -6,7 +6,6 @@ */ #include <config.h> -#include <common.h> #include <nand.h> #include <linux/mtd/rawnand.h> #include <asm/io.h> diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index bf9a11472d1..a6761c21d40 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -30,6 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7 + u8 dmo_get_memcfg(void) { struct gpio_desc gpio[4]; @@ -58,8 +60,16 @@ u8 dmo_get_memcfg(void) int board_phys_sdram_size(phys_size_t *size) { u8 memcfg = dmo_get_memcfg(); + u8 ecc = 0; + + *size = 4ULL >> ((memcfg >> 1) & 0x3); + + if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) { + /* 896 MiB, i.e. 1 GiB without 12.5% reserved for in-band ECC */ + ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK; + } - *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G; + *size *= SZ_1G - (ecc ? (SZ_1G / 8) : 0); return 0; } @@ -100,6 +110,12 @@ static void spl_dram_init(struct dram_timing_info *dram_timing_info[8]) } ddr_init(dram_timing_info[memcfg]); + + if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) { + printf("DDR: Inline ECC %sabled\n", + (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ? + "en" : "dis"); + } } void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad, diff --git a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c index 04cef3a8b9f..0ad40002d4e 100644 --- a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c +++ b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c @@ -19,47 +19,66 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400030, 0x1 }, { 0x3d400000, 0xa3080020 }, { 0x3d400020, 0x1303 }, - { 0x3d400024, 0x1c79100 }, + { 0x3d400024, 0x1c7cf80 }, { 0x3d400064, 0x710106 }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400070, 0x7027fd4 }, +#else { 0x3d400070, 0x7027f90 }, +#endif { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc0030720 }, + { 0x3d4000d0, 0xc0030721 }, { 0x3d4000d4, 0xb80000 }, - { 0x3d4000dc, 0xe40036 }, - { 0x3d4000e0, 0x330000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0xf30000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x1e262028 }, - { 0x3d400104, 0x7073b }, + { 0x3d400100, 0x1f262028 }, + { 0x3d400104, 0x8083b }, { 0x3d40010c, 0xe0e000 }, { 0x3d400110, 0x11040a11 }, - { 0x3d400114, 0x2050e0e }, - { 0x3d400118, 0x1010008 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20700 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, { 0x3d400138, 0x10d }, { 0x3d400144, 0xbb005e }, - { 0x3d400180, 0x3a5001c }, - { 0x3d400184, 0x2f071e5 }, + { 0x3d400180, 0x3a6001d }, + { 0x3d400184, 0x2f071f4 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49b820c }, + { 0x3d400190, 0x4a3820e }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1b0c }, + { 0x3d4001b4, 0x230e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, + { 0x3d4001c0, 0x7 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x810191a }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9141c1c }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400200, 0x14 }, +#else { 0x3d400200, 0x17 }, +#endif + { 0x3d400208, 0x0 }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d40020c, 0x14141400 }, +#else { 0x3d40020c, 0x0 }, +#endif { 0x3d400210, 0x1f1f }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400204, 0x50505 }, + { 0x3d400214, 0x4040404 }, + { 0x3d400218, 0x4040404 }, +#else { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, +#endif { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x1705 }, { 0x3d400254, 0x2c }, @@ -78,7 +97,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, + { 0x3d4020e0, 0xf30000 }, { 0x3d4020e8, 0x660048 }, { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, @@ -88,7 +107,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, { 0x3d402138, 0x1d }, @@ -97,13 +116,13 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, + { 0x3d4020f4, 0x599 }, { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, + { 0x3d4030e0, 0xf30000 }, { 0x3d4030e8, 0x660048 }, { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, @@ -113,7 +132,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, { 0x3d403138, 0x8 }, @@ -122,7 +141,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -260,16 +279,16 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x212149, 0xeba }, { 0x213049, 0xeba }, { 0x213149, 0xeba }, - { 0x43, 0xe7 }, - { 0x1043, 0xe7 }, - { 0x2043, 0xe7 }, - { 0x3043, 0xe7 }, - { 0x4043, 0xe7 }, - { 0x5043, 0xe7 }, - { 0x6043, 0xe7 }, - { 0x7043, 0xe7 }, - { 0x8043, 0xe7 }, - { 0x9043, 0xe7 }, + { 0x43, 0x3ff }, + { 0x1043, 0x3ff }, + { 0x2043, 0x3ff }, + { 0x3043, 0x3ff }, + { 0x4043, 0x3ff }, + { 0x5043, 0x3ff }, + { 0x6043, 0x3ff }, + { 0x7043, 0x3ff }, + { 0x8043, 0x3ff }, + { 0x9043, 0x3ff }, { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, @@ -319,19 +338,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x2002d, 0x1 }, + { 0x12002d, 0x1 }, + { 0x22002d, 0x1 }, { 0x2007d, 0x212 }, { 0x12007d, 0x212 }, { 0x22007d, 0x212 }, { 0x2007c, 0x61 }, { 0x12007c, 0x61 }, { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, { 0x2002c, 0x0 }, }; @@ -1061,7 +1076,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xe94 }, + { 0x54003, 0xe96 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1070,26 +1085,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0x3336 }, + { 0x54032, 0xf400 }, + { 0x54033, 0xf33f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0x3336 }, + { 0x54038, 0xf400 }, + { 0x54039, 0xf33f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1111,25 +1126,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x310 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1151,25 +1166,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x310 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1180,7 +1195,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xe94 }, + { 0x54003, 0xe96 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1190,26 +1205,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0x3336 }, + { 0x54032, 0xf400 }, + { 0x54033, 0xf33f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0x3336 }, + { 0x54038, 0xf400 }, + { 0x54039, 0xf33f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1699,9 +1714,9 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x200be, 0x3 }, - { 0x2000b, 0x419 }, + { 0x2000b, 0x41a }, { 0x2000c, 0xe9 }, - { 0x2000d, 0x91c }, + { 0x2000d, 0x91d }, { 0x2000e, 0x2c }, { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, @@ -1804,8 +1819,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 3733mts 1D */ - .drate = 3733, + /* P0 3600mts 1D */ + .drate = 3600, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1840,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 3733mts 2D */ - .drate = 3733, + /* P0 3600mts 2D */ + .drate = 3600, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1845,5 +1860,19 @@ struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32 = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3733, 400, 100, }, + .fsp_table = { 3600, 400, 100, }, }; + +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); + ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); + ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); +} +#endif diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index cfc4b65e0f9..a3600c8568a 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -68,6 +68,11 @@ int data_modul_imx_edm_sbc_board_power_init(void) /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); + /* DRAM Vdd1 always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d); + /* DRAM Vdd2/Vddq always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d); + /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig index 09c95413a54..ac2d078f42a 100644 --- a/board/emulation/qemu-arm/Kconfig +++ b/board/emulation/qemu-arm/Kconfig @@ -5,8 +5,7 @@ config TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CMD_QFW - select QFW_MMIO + select QFW_MMIO if CMD_QFW imply VIRTIO_MMIO imply VIRTIO_PCI imply VIRTIO_NET diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index d56b4b5bc1e..cdd0d0d95f6 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -54,12 +54,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SCSI_AHCI imply AHCI_PCI imply E1000 - imply NVME imply PCI + imply NVME_PCI imply PCIE_ECAM_GENERIC imply DM_RNG imply SCSI - imply DM_SCSI imply SYS_NS16550 imply SIFIVE_SERIAL imply HTIF_CONSOLE if 64BIT @@ -82,5 +81,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply USB_XHCI_PCI imply USB_KEYBOARD imply CMD_USB + imply UFS + imply UFS_PCI endif diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig index 787751abba4..01dc1d497ae 100644 --- a/board/emulation/qemu-x86/Kconfig +++ b/board/emulation/qemu-x86/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select QEMU - select QFW_PIO + select QFW_PIO if CMD_QFW select BOARD_ROMSIZE_KB_1024 imply VIRTIO_PCI imply VIRTIO_NET diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 46ffd817b44..228f07502f7 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> #include <log.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index d3323b9ec1e..d4ca278e883 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -3,8 +3,8 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> #include <log.h> +#include <asm/cache.h> #include <asm/global_data.h> #include <asm/immap_85xx.h> #include "sleep.h" diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 5ec3f2a76b1..fc5d400cfe1 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -793,4 +793,4 @@ U_BOOT_CMD( vdd_read, 1, 0, do_vdd_read, "read VDD", " - Read the voltage specified in mV" -) +); diff --git a/board/freescale/imx8mp_evk/MAINTAINERS b/board/freescale/imx8mp_evk/MAINTAINERS index 2759652cc42..c2c7c830b5d 100644 --- a/board/freescale/imx8mp_evk/MAINTAINERS +++ b/board/freescale/imx8mp_evk/MAINTAINERS @@ -1,4 +1,5 @@ i.MX8MP EVK BOARD +M: Fabio Estevm <festevam@gmail.com> M: Peng Fan <peng.fan@nxp.com> S: Maintained F: board/freescale/imx8mp_evk/ diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index a24b8c1d860..024b46ef8bc 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -3,50 +3,11 @@ * Copyright 2019 NXP */ -#include <common.h> #include <env.h> -#include <errno.h> -#include <init.h> -#include <miiphy.h> -#include <netdev.h> -#include <linux/delay.h> -#include <asm/global_data.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm-generic/gpio.h> -#include <asm/arch/imx8mp_pins.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-imx/gpio.h> - -DECLARE_GLOBAL_DATA_PTR; - -static void setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Enable RGMII TX clk output */ - setbits_le32(&gpr->gpr[1], BIT(22)); -} - -#if CONFIG_IS_ENABLED(NET) -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} -#endif int board_init(void) { - int ret = 0; - - if (IS_ENABLED(CONFIG_FEC_MXC)) { - setup_fec(); - } - - return ret; + return 0; } int board_late_init(void) diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 246826a0d48..9dd2cbc799c 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -67,40 +67,44 @@ struct i2c_pads_info i2c_pad_info1 = { }, }; -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* - * increase VDD_SOC to typical value 0.95V before first - * DRAM access, set DVS1 to 0.85v for suspend. + * Increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85V for suspend. * Enable DVS control through PMIC_STBY_REQ and * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ -#ifdef CONFIG_IMX8M_VDD_SOC_850MV - /* set DVS0 to 0.85v for special case*/ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); -#else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); -#endif - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); - /* Kernel uses OD/OD freq for SOC */ - /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* + * Kernel uses OD/OD freq for SOC. + * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD + * voltage 0.95V. + */ + + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); return 0; } @@ -135,8 +139,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index f4297f8fd4d..c54dc9d05c5 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -49,27 +49,11 @@ int board_phy_config(struct phy_device *phydev) return 0; } -static int setup_eqos(void) -{ - struct blk_ctrl_wakeupmix_regs *bctrl = - (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&bctrl->eqos_gpr, - BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, - BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); - - return set_clk_eqos(ENET_125MHZ); -} - int board_init(void) { if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec(); - if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) - setup_eqos(); - return 0; } diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index a618ce11a58..930ef6be385 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -4,7 +4,6 @@ * Copyright 2019, 2021 NXP */ -#include <common.h> #include <clock_legacy.h> #include <fdt_support.h> #include <i2c.h> diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index d0e4e796c60..b7e043b2e62 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright 2016-2019, 2021 NXP */ -#include <common.h> #include <clock_legacy.h> #include <fdt_support.h> #include <init.h> diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 27b9d79e5f0..78006afce86 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -4,7 +4,6 @@ * Copyright 2019, 2021-2022 NXP */ -#include <common.h> #include <clock_legacy.h> #include <command.h> #include <fdt_support.h> diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 18869d8c1df..cf84ff9e638 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -4,7 +4,6 @@ * Copyright 2021-2022 NXP */ -#include <common.h> #include <i2c.h> #include <init.h> #include <asm/global_data.h> diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index f62f5fd2745..2fece3a1b09 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -3,6 +3,8 @@ * Copyright 2017 NXP */ +#include <vsprintf.h> +#include <linux/string.h> #include <asm/io.h> #include <asm/arch/fsl_serdes.h> #include <fsl-mc/fsl_mc.h> diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 0d0d5de1562..048ab44c591 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -3,6 +3,8 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ +#include <vsprintf.h> +#include <linux/string.h> #include <asm/io.h> #include <asm/arch/fsl_serdes.h> #include <fsl-mc/fsl_mc.h> diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index cff2e6a8717..4fe23b51cd1 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -267,7 +267,7 @@ int power_init_board(void) struct udevice *dev; int ret, dev_id, rev_id; - ret = pmic_get("pfuze3000@8", &dev); + ret = pmic_get("pmic@8", &dev); if (ret == -ENODEV) return 0; if (ret != 0) diff --git a/board/friendlyarm/nanopi2/onewire.c b/board/friendlyarm/nanopi2/onewire.c index 56f0f2dfceb..4f0b1e33c2d 100644 --- a/board/friendlyarm/nanopi2/onewire.c +++ b/board/friendlyarm/nanopi2/onewire.c @@ -11,16 +11,13 @@ #include <asm/arch/clk.h> #include <asm/arch/pwm.h> #include <i2c.h> +#include <linux/time.h> #include <irq_func.h> #include <asm/arch/nexell.h> #include <asm/arch/nx_gpio.h> -#ifndef NSEC_PER_SEC -#define NSEC_PER_SEC 1000000000L -#endif - #define SAMPLE_BPS 9600 #define SAMPLE_IN_US 101 /* (1000000 / BPS) */ diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 7bfd1b556bb..56c6e2b5cff 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1211,9 +1211,9 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x200be, 0x3 }, - { 0x2000b, 0x34b }, - { 0x2000c, 0xbb }, - { 0x2000d, 0x753 }, + { 0x2000b, 0x465 }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, { 0x2000e, 0x2c }, { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, @@ -1323,42 +1323,42 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x1203 }, - { 0x3d400024, 0x16e3600 }, - { 0x3d400064, 0x5b0087 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a00b4 }, { 0x3d400070, 0x7027f90 }, { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x402 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0x8d }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0xbc }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, + { 0x3d400190, 0x49f820e }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, + { 0x3d4001b4, 0x1f0e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0x699 }, - { 0x3d400108, 0x70e1617 }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, { 0x3d400200, 0x1f }, { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, @@ -1379,7 +1379,7 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1001 }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc0012 }, @@ -1404,7 +1404,7 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0x599 }, - { 0x3d403020, 0x1001 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30005 }, @@ -1436,36 +1436,36 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x100a0, 0x0 }, { 0x100a1, 0x1 }, - { 0x100a2, 0x3 }, - { 0x100a3, 0x2 }, - { 0x100a4, 0x5 }, - { 0x100a5, 0x4 }, - { 0x100a6, 0x7 }, - { 0x100a7, 0x6 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x2 }, - { 0x120a3, 0x3 }, - { 0x120a4, 0x4 }, - { 0x120a5, 0x5 }, - { 0x120a6, 0x6 }, - { 0x120a7, 0x7 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x3 }, - { 0x130a3, 0x4 }, - { 0x130a4, 0x5 }, - { 0x130a5, 0x2 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -1500,7 +1500,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, + { 0x200c5, 0x18 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -1509,11 +1509,11 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1a3 }, + { 0x20024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1a3 }, + { 0x120024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1a3 }, + { 0x220024, 0x1e3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -1579,7 +1579,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, + { 0x20008, 0x3e8 }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -1644,7 +1644,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1653,26 +1653,26 @@ struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1763,7 +1763,7 @@ struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = { /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1773,26 +1773,26 @@ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1802,8 +1802,8 @@ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { { - /* P0 3000mts 1D */ - .drate = 3000, + /* P0 4000mts 1D */ + .drate = 4000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg_1gb_single_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die), @@ -1823,8 +1823,8 @@ struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die), }, { - /* P0 3000mts 2D */ - .drate = 3000, + /* P0 4000mts 2D */ + .drate = 4000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die), @@ -1843,7 +1843,7 @@ struct dram_timing_info dram_timing_1gb_single_die = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 4000, 400, 100, }, }; /* @@ -1856,43 +1856,44 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa3080020 }, - { 0x3d400020, 0x1203 }, - { 0x3d400024, 0x16e3600 }, - { 0x3d400064, 0x5b00d2 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, { 0x3d400070, 0x7027f90 }, { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x401 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0xd8 }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, + { 0x3d400190, 0x49f820e}, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, + { 0x3d4001b4, 0x1f0e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x70e1617 }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, { 0x3d400200, 0x17 }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, @@ -1911,7 +1912,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1001 }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, @@ -1926,7 +1927,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, { 0x3d402138, 0x1d }, @@ -1935,8 +1936,8 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1001 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, @@ -1951,7 +1952,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, { 0x3d403138, 0x8 }, @@ -1960,7 +1961,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -1968,36 +1969,36 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x100a0, 0x0 }, { 0x100a1, 0x1 }, - { 0x100a2, 0x3 }, - { 0x100a3, 0x2 }, - { 0x100a4, 0x5 }, - { 0x100a5, 0x4 }, - { 0x100a6, 0x7 }, - { 0x100a7, 0x6 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x2 }, - { 0x120a3, 0x3 }, - { 0x120a4, 0x4 }, - { 0x120a5, 0x5 }, - { 0x120a6, 0x6 }, - { 0x120a7, 0x7 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x3 }, - { 0x130a3, 0x4 }, - { 0x130a4, 0x5 }, - { 0x130a5, 0x2 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -2032,7 +2033,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, + { 0x200c5, 0x18 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -2041,11 +2042,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1a3 }, + { 0x20024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1a3 }, + { 0x120024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1a3 }, + { 0x220024, 0x1e3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -2111,7 +2112,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, + { 0x20008, 0x3e8 }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -2175,7 +2176,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -2184,26 +2185,26 @@ static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x310 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -2294,7 +2295,7 @@ static struct dram_cfg_param ddr_fsp2_cfg_4gb_dual_die[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -2304,26 +2305,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -2333,8 +2334,8 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { { - /* P0 3000mts 1D */ - .drate = 3000, + /* P0 4000mts 1D */ + .drate = 4000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg_4gb_dual_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4gb_dual_die), @@ -2354,8 +2355,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4gb_dual_die), }, { - /* P0 3000mts 2D */ - .drate = 3000, + /* P0 4000mts 2D */ + .drate = 4000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg_4gb_dual_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4gb_dual_die), @@ -2374,5 +2375,5 @@ struct dram_timing_info dram_timing_4gb_dual_die = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 4000, 400, 100, }, }; diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index a39ae58c8a0..0902a1da3e2 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -238,12 +238,12 @@ int ft_board_setup(void *fdt, struct bd_info *bd) if (!strncmp(base_model, "GW73", 4)) { pcbrev = get_pcb_rev(base_model); - if (pcbrev > 'B') { + if (pcbrev > 'B' && pcbrev < 'E') { printf("adjusting dt for %s\n", base_model); /* - * revC replaced PCIe 5-port switch with 4-port - * which changed ethernet1 PCIe GbE + * revC/D/E has PCIe 4-port switch which changes + * ethernet1 PCIe GbE: * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0 * to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0 */ diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index b5fa5101e88..7f67d1e4530 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -52,19 +52,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_SCSI_AHCI_PLAT -void scsi_init(void) -{ - u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); - - cphy_disable_overrides(); - if (reg & PWRDOM_STAT_SATA) { - ahci_init((void __iomem *)HB_AHCI_BASE); - scsi_scan(true); - } -} -#endif - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/htc/endeavoru/endeavoru-spl.c b/board/htc/endeavoru/endeavoru-spl.c index 7921ff1a733..2525b50d3e8 100644 --- a/board/htc/endeavoru/endeavoru-spl.c +++ b/board/htc/endeavoru/endeavoru-spl.c @@ -9,7 +9,7 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> +#include <asm/arch/tegra.h> #include <asm/arch-tegra/tegra_i2c.h> #include <linux/delay.h> diff --git a/board/htc/endeavoru/endeavoru.c b/board/htc/endeavoru/endeavoru.c index e1a0b242e2c..7fb6125b143 100644 --- a/board/htc/endeavoru/endeavoru.c +++ b/board/htc/endeavoru/endeavoru.c @@ -7,48 +7,11 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> #include <dm.h> #include <fdt_support.h> -#include <i2c.h> -#include <log.h> #include <asm/arch/pinmux.h> -#include <asm/arch/gp_padctrl.h> -#include <asm/arch/gpio.h> -#include <asm/gpio.h> -#include <linux/delay.h> -#include "pinmux-config-endeavoru.h" - -#define TPS80032_CTL1_I2C_ADDR 0x48 -#define TPS80032_PHOENIX_DEV_ON 0x25 -#define DEVOFF BIT(0) -#define TPS80032_LDO1_CFG_STATE 0x9E -#define TPS80032_LDO1_CFG_VOLTAGE 0x9F - -#ifdef CONFIG_CMD_POWEROFF -int do_poweroff(struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]) -{ - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return 0; - } - - ret = dm_i2c_reg_write(dev, TPS80032_PHOENIX_DEV_ON, DEVOFF); - if (ret) - return ret; - // wait some time and then print error - mdelay(5000); - - printf("Failed to power off!!!\n"); - return 1; -} -#endif +#include "pinmux-config-endeavoru.h" /* * Routine: pinmux_init @@ -60,38 +23,6 @@ void pinmux_init(void) ARRAY_SIZE(endeavoru_pinmux_common)); } -#ifdef CONFIG_MMC_SDHCI_TEGRA -static void tps80032_voltage_init(void) -{ - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev); - if (ret) - log_debug("cannot find PMIC I2C chip\n"); - - /* TPS80032: LDO1_REG = 1.2v to DSI */ - ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_VOLTAGE, 0x03); - if (ret) - log_debug("avdd_dsi_csi voltage set failed: %d\n", ret); - - /* TPS80032: LDO1_REG enable */ - ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_STATE, 0x01); - if (ret) - log_debug("avdd_dsi_csi enable failed: %d\n", ret); -} - -/* - * Routine: pin_mux_mmc - * Description: setup the MMC muxes, power rails, etc. - */ -void pin_mux_mmc(void) -{ - /* Bring up DSI power */ - tps80032_voltage_init(); -} -#endif /* MMC */ - #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 21c21aac221..cc3611e2dec 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -3,7 +3,7 @@ * Copyright 2020 Hitachi Power Grids. All rights reserved. */ -#include <common.h> +#include <config.h> #include <event.h> #include <i2c.h> #include <asm/io.h> diff --git a/board/lg/x3-t30/x3-t30-spl.c b/board/lg/x3-t30/x3-t30-spl.c index 864f2de45f1..00f79dd1db4 100644 --- a/board/lg/x3-t30/x3-t30-spl.c +++ b/board/lg/x3-t30/x3-t30-spl.c @@ -9,7 +9,7 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> +#include <asm/arch/tegra.h> #include <asm/arch-tegra/tegra_i2c.h> #include <linux/delay.h> diff --git a/board/lg/x3-t30/x3-t30.c b/board/lg/x3-t30/x3-t30.c index a08e00dd87c..6b9169be6a1 100644 --- a/board/lg/x3-t30/x3-t30.c +++ b/board/lg/x3-t30/x3-t30.c @@ -7,60 +7,13 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> #include <dm.h> #include <fdt_support.h> -#include <i2c.h> -#include <log.h> #include <asm/arch/pinmux.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/tegra.h> #include <asm/arch-tegra/fuse.h> -#include <asm/gpio.h> -#include <linux/delay.h> -#include "pinmux-config-x3.h" - -#define MAX77663_I2C_ADDR 0x1C - -#define MAX77663_REG_SD2 0x18 -#define MAX77663_REG_LDO2 0x27 -#define MAX77663_REG_LDO3 0x29 -#define MAX77663_REG_LDO5 0x2D -#define MAX77663_REG_ONOFF_CFG1 0x41 -#define ONOFF_PWR_OFF BIT(1) - -#ifdef CONFIG_CMD_POWEROFF -int do_poweroff(struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]) -{ - struct udevice *dev; - uchar data_buffer[1]; - int ret; - - ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return 0; - } - - ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); - if (ret) - return ret; - data_buffer[0] |= ONOFF_PWR_OFF; - - ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); - if (ret) - return ret; - - /* wait some time and then print error */ - mdelay(5000); - - printf("Failed to power off!!!\n"); - return 1; -} -#endif +#include "pinmux-config-x3.h" /* * Routine: pinmux_init @@ -82,50 +35,6 @@ void pinmux_init(void) #endif } -#ifdef CONFIG_MMC_SDHCI_TEGRA -static void max77663_voltage_init(void) -{ - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev); - if (ret) { - log_debug("cannot find PMIC I2C chip\n"); - return; - } - - /* 0x60 for 1.8v, bit7:0 = voltage */ - ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60); - if (ret) - log_debug("vdd_1v8_vio set failed: %d\n", ret); - - /* 0xF2 for 3.30v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO2, 0xF2); - if (ret) - log_debug("avdd_usb set failed: %d\n", ret); - - /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC); - if (ret) - log_debug("vdd_usd set failed: %d\n", ret); - - /* 0xE9 for 2.85v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO5, 0xE9); - if (ret) - log_debug("vcore_emmc set failed: %d\n", ret); -} - -/* - * Routine: pin_mux_mmc - * Description: setup the MMC muxes, power rails, etc. - */ -void pin_mux_mmc(void) -{ - /* Bring up uSD and eMMC power */ - max77663_voltage_init(); -} -#endif /* MMC */ - int nvidia_board_init(void) { /* Set up panel bridge clocks */ diff --git a/board/nuvoton/arbel_evb/Kconfig b/board/nuvoton/arbel_evb/Kconfig index 33c589f1fb3..ed1c1ad8ee6 100644 --- a/board/nuvoton/arbel_evb/Kconfig +++ b/board/nuvoton/arbel_evb/Kconfig @@ -15,4 +15,5 @@ config SYS_MEM_TOP_HIDE help Reserve memory for ECC/GFX/OPTEE/TIP/CP. +source "board/nuvoton/common/Kconfig" endif diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 59e1a425646..8fc56c18397 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -7,6 +7,7 @@ #include <dm.h> #include <asm/io.h> #include <asm/arch/gcr.h> +#include "../common/uart.h" #define SR_MII_CTRL_SWR_BIT15 15 @@ -90,3 +91,9 @@ int dram_init_banksize(void) return 0; } +int last_stage_init(void) +{ + board_set_console(); + + return 0; +} diff --git a/board/nuvoton/common/Kconfig b/board/nuvoton/common/Kconfig new file mode 100644 index 00000000000..61de7bc5f88 --- /dev/null +++ b/board/nuvoton/common/Kconfig @@ -0,0 +1,9 @@ +if ARCH_NPCM + +config SYS_SKIP_UART_INIT + bool "Skip UART initialization" + depends on NPCM_SERIAL + help + Select this if the UART you want to use is already + initialized by the time U-Boot starts its execution. +endif diff --git a/board/nuvoton/common/Makefile b/board/nuvoton/common/Makefile new file mode 100644 index 00000000000..8fd83b229b5 --- /dev/null +++ b/board/nuvoton/common/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SYS_SKIP_UART_INIT) += uart.o diff --git a/board/nuvoton/common/uart.c b/board/nuvoton/common/uart.c new file mode 100644 index 00000000000..b35c795704a --- /dev/null +++ b/board/nuvoton/common/uart.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Nuvoton Technology Corp. + */ + +#include <clk.h> +#include <dm.h> +#include <env.h> +#include <serial.h> +#include <linux/delay.h> + +#define UART_DLL 0x0 +#define UART_DLM 0x4 +#define UART_LCR 0xc +#define LCR_DLAB BIT(7) + +void board_set_console(void) +{ + const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE; + struct udevice *dev = gd->cur_serial_dev; + unsigned int baudrate, max_delta; + void __iomem *uart_reg; + struct clk clk; + char string[32]; + u32 uart_clk; + u8 dll, dlm; + u16 divisor; + int ret, i; + + if (!dev) + return; + + uart_reg = dev_read_addr_ptr(dev); + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return; + + uart_clk = clk_get_rate(&clk); + setbits_8(uart_reg + UART_LCR, LCR_DLAB); + dll = readb(uart_reg + UART_DLL); + dlm = readb(uart_reg + UART_DLM); + clrbits_8(uart_reg + UART_LCR, LCR_DLAB); + divisor = dll | (dlm << 8); + baudrate = uart_clk / ((16 * (divisor + 2))); + for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) { + max_delta = baudrate_table[i] / 20; + if (abs(baudrate - baudrate_table[i]) < max_delta) { + /* The baudrate is supported */ + gd->baudrate = baudrate_table[i]; + break; + } + } + + if (i == ARRAY_SIZE(baudrate_table)) { + /* current baudrate is not suitable, set to default */ + divisor = DIV_ROUND_CLOSEST(uart_clk, 16 * gd->baudrate) - 2; + setbits_8(uart_reg + UART_LCR, LCR_DLAB); + writeb(divisor & 0xff, uart_reg + UART_DLL); + writeb(divisor >> 8, uart_reg + UART_DLM); + clrbits_8(uart_reg + UART_LCR, LCR_DLAB); + udelay(100); + printf("\r\nUART(source %u): change baudrate from %u to %u\n", + uart_clk, baudrate, uart_clk / ((16 * (divisor + 2)))); + } + + debug("Set env baudrate=%u\n", gd->baudrate); + snprintf(string, sizeof(string), "ttyS0,%un8", gd->baudrate); + env_set("console", string); + +} diff --git a/board/nuvoton/common/uart.h b/board/nuvoton/common/uart.h new file mode 100644 index 00000000000..9cc895251b3 --- /dev/null +++ b/board/nuvoton/common/uart.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Nuvoton Technology Corp. + */ + +#ifndef _NUVOTON_UART_H +#define _NUVOTON_UART_H + +void board_set_console(void); + +#endif /* _NUVOTON_COMMON_H */ diff --git a/board/nuvoton/poleg_evb/Kconfig b/board/nuvoton/poleg_evb/Kconfig index d3f4c1dd812..6f7f1ef1578 100644 --- a/board/nuvoton/poleg_evb/Kconfig +++ b/board/nuvoton/poleg_evb/Kconfig @@ -22,4 +22,5 @@ config TARGET_POLEG_EVB endchoice +source "board/nuvoton/common/Kconfig" endif diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index 2052af6649a..7421911a416 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/arch/gcr.h> #include <asm/mach-types.h> +#include "../common/uart.h" DECLARE_GLOBAL_DATA_PTR; @@ -53,3 +54,10 @@ int dram_init(void) return 0; } + +int last_stage_init(void) +{ + board_set_console(); + + return 0; +} diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS index 9edec7b7d28..acffda61c04 100644 --- a/board/phytec/phycore_imx8mm/MAINTAINERS +++ b/board/phytec/phycore_imx8mm/MAINTAINERS @@ -2,8 +2,9 @@ phyCORE-i.MX8M Mini M: Teresa Remmet <t.remmet@phytec.de> W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/ S: Maintained -F: arch/arm/dts/phycore-imx8mm.dts -F: arch/arm/dts/phycore-imx8mm-u-boot.dtsi +F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts +F: arch/arm/dts/imx8mm-phycore-som.dtsi +F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi F: board/phytec/phycore_imx8mm/ F: configs/phycore-imx8mm_defconfig F: include/configs/phycore_imx8mm.h diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS index 303db144aab..220ee21f230 100644 --- a/board/pine64/rockpro64_rk3399/MAINTAINERS +++ b/board/pine64/rockpro64_rk3399/MAINTAINERS @@ -1,5 +1,4 @@ ROCKPRO64 -M: Akash Gajjar <akash@openedev.com> M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: board/pine64/rockpro64_rk3399 diff --git a/board/polyhex/imx8mp_debix_model_a/Kconfig b/board/polyhex/imx8mp_debix_model_a/Kconfig new file mode 100644 index 00000000000..3ebb6bc5557 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MP_DEBIX_MODEL_A + +config SYS_BOARD + default "imx8mp_debix_model_a" + +config SYS_VENDOR + default "polyhex" + +config SYS_CONFIG_NAME + default "imx8mp_debix_model_a" + +config IMX_CONFIG + default "board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg" + +endif diff --git a/board/polyhex/imx8mp_debix_model_a/MAINTAINERS b/board/polyhex/imx8mp_debix_model_a/MAINTAINERS new file mode 100644 index 00000000000..d3afa91c118 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/MAINTAINERS @@ -0,0 +1,8 @@ +DEBIX MODEL A BOARD (i.MX8M Plus) +M: Gilles Talis <gilles.talis@gmail.com> +S: Maintained +F: arch/arm/dts/imx8mp-debix-model-a.dts +F: arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi +F: board/polyhex/imx8mp_debix_model_a/ +F: include/configs/imx8mp_debix_model_a.h +F: configs/imx8mp_debix_model_a_defconfig diff --git a/board/polyhex/imx8mp_debix_model_a/Makefile b/board/polyhex/imx8mp_debix_model_a/Makefile new file mode 100644 index 00000000000..e5cdc850878 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2019 NXP +# Copyright 2023 Gilles Talis <gilles.talis@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mp_debix_model_a.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c new file mode 100644 index 00000000000..14b94c9e33c --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2023 Gilles Talis <gilles.talis@gmail.com> + */ + +#include <asm-generic/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8mp_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/iomux-v3.h> +#include <common.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <linux/delay.h> +#include <miiphy.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +#if CONFIG_IS_ENABLED(NET) +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + int ret = 0; + + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return ret; +} + +int board_late_init(void) +{ + return 0; +} diff --git a/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg b/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg new file mode 100644 index 00000000000..23fd05204a6 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021, 2023 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c b/board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c index 8803fbfdc7d..518daa39f94 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c +++ b/board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c @@ -1,49 +1,44 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Generated code from MX8M_DDR_tool v3.20 using RPAv20 - * - 1x Micron MT53E128M32D2DS-046 32bit dual-channel for total of 512MiB - * - imx8mm-gw7903 - * - * Align with uboot version: - * imx_v2019.04_5.4.x and above version - * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: - * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h> + * Copyright 2019, 2023 NXP */ #include <linux/kernel.h> #include <asm/arch/ddr.h> -static struct dram_cfg_param ddr_ddrc_cfg[] = { +struct dram_cfg_param ddr_ddrc_cfg[] = { /** Initialize DDRC registers **/ { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x203 }, - { 0x3d400024, 0x3a980 }, - { 0x3d400064, 0x5b0062 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, - { 0x3d4000e8, 0x66004d }, - { 0x3d4000ec, 0x16004d }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x401 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0x68 }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1c61a00 }, + { 0x3d400064, 0x710105 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc003071a }, + { 0x3d4000d4, 0xb70000 }, + { 0x3d4000dc, 0xe40036 }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x1e261f28 }, + { 0x3d400104, 0x7073b }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x11040a11 }, + { 0x3d400114, 0x2050e0e }, + { 0x3d400118, 0x1010008 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20700 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x10c }, + { 0x3d400144, 0xba005d }, + { 0x3d400180, 0x3a2001c }, + { 0x3d400184, 0x2f07187 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, + { 0x3d400190, 0x49b820c }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, + { 0x3d4001b4, 0x1b0c }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, @@ -51,33 +46,34 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x70e1617 }, + { 0x3d400108, 0x810191a }, { 0x3d400200, 0x1f }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0xf0f0707 }, + { 0x3d400218, 0x7070707 }, { 0x3d40021c, 0xf0f }, - { 0x3d400250, 0x29001701 }, + { 0x3d400250, 0x1705 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, { 0x3d400264, 0x900093e7 }, { 0x3d40026c, 0x2005574 }, { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, { 0x3d400408, 0x72ff }, { 0x3d400494, 0x2100e07 }, { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1 }, - { 0x3d402024, 0x7d00 }, - { 0x3d402050, 0x20d040 }, - { 0x3d402064, 0xc000d }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, - { 0x3d4020ec, 0x16004d }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, { 0x3d402104, 0x30407 }, { 0x3d402108, 0x203060b }, @@ -88,21 +84,21 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40211c, 0x301 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0xe }, + { 0x3d402138, 0x1d }, { 0x3d402144, 0x14000a }, { 0x3d402180, 0x640004 }, { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1 }, - { 0x3d403024, 0x1f40 }, - { 0x3d403050, 0x20d040 }, - { 0x3d403064, 0x30004 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, - { 0x3d4030ec, 0x16004d }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, { 0x3d403104, 0x30404 }, { 0x3d403108, 0x203060b }, @@ -113,7 +109,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40311c, 0x301 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x4 }, + { 0x3d403138, 0x8 }, { 0x3d403144, 0x50003 }, { 0x3d403180, 0x190004 }, { 0x3d403190, 0x3818200 }, @@ -124,7 +120,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { }; /* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { +struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x100a0, 0x0 }, { 0x100a1, 0x1 }, { 0x100a2, 0x2 }, @@ -144,9 +140,9 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, { 0x120a2, 0x3 }, - { 0x120a3, 0x4 }, + { 0x120a3, 0x2 }, { 0x120a4, 0x5 }, - { 0x120a5, 0x2 }, + { 0x120a5, 0x4 }, { 0x120a6, 0x7 }, { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, @@ -200,12 +196,12 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x120024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x220024, 0x1ab }, - { 0x2003a, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, { 0x220056, 0x3 }, @@ -270,11 +266,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, + { 0x20008, 0x3a2 }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, - { 0x200b2, 0xdc }, + { 0x200b2, 0x104 }, { 0x10043, 0x5a1 }, { 0x10143, 0x5a1 }, { 0x11043, 0x5a1 }, @@ -283,7 +279,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x12143, 0x5a1 }, { 0x13043, 0x5a1 }, { 0x13143, 0x5a1 }, - { 0x1200b2, 0xdc }, + { 0x1200b2, 0x104 }, { 0x110043, 0x5a1 }, { 0x110143, 0x5a1 }, { 0x111043, 0x5a1 }, @@ -292,7 +288,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x112143, 0x5a1 }, { 0x113043, 0x5a1 }, { 0x113143, 0x5a1 }, - { 0x2200b2, 0xdc }, + { 0x2200b2, 0x104 }, { 0x210043, 0x5a1 }, { 0x210143, 0x5a1 }, { 0x211043, 0x5a1 }, @@ -319,16 +315,21 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x2002d, 0x0 }, { 0x12002d, 0x0 }, { 0x22002d, 0x0 }, - { 0x200c7, 0x21 }, - { 0x1200c7, 0x21 }, - { 0x2200c7, 0x21 }, - { 0x200ca, 0x24 }, - { 0x1200ca, 0x24 }, - { 0x2200ca, 0x24 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, }; /* ddr phy trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { { 0x200b2, 0x0 }, { 0x1200b2, 0x0 }, { 0x2200b2, 0x0 }, @@ -1051,163 +1052,166 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { }; /* P0 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { +struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xe88 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, + { 0x54006, 0x14 }, { 0x54008, 0x131f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* P1 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { +struct dram_cfg_param ddr_fsp1_cfg[] = { { 0xd0000, 0x0 }, { 0x54002, 0x101 }, { 0x54003, 0x190 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, + { 0x54006, 0x14 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, + { 0x54033, 0x3300 }, { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, + { 0x54039, 0x3300 }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* P2 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { +struct dram_cfg_param ddr_fsp2_cfg[] = { { 0xd0000, 0x0 }, { 0x54002, 0x102 }, { 0x54003, 0x64 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, + { 0x54006, 0x14 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, + { 0x54033, 0x3300 }, { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, + { 0x54039, 0x3300 }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* P0 2D message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xe88 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, + { 0x54006, 0x14 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { +struct dram_cfg_param ddr_phy_pie[] = { { 0xd0000, 0x0 }, { 0x90000, 0x10 }, { 0x90001, 0x400 }, @@ -1230,20 +1234,20 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90035, 0x2 }, { 0x90036, 0x10 }, { 0x90037, 0x139 }, - { 0x90038, 0xf }, + { 0x90038, 0xb }, { 0x90039, 0x7c0 }, { 0x9003a, 0x139 }, { 0x9003b, 0x44 }, - { 0x9003c, 0x630 }, + { 0x9003c, 0x633 }, { 0x9003d, 0x159 }, { 0x9003e, 0x14f }, { 0x9003f, 0x630 }, { 0x90040, 0x159 }, { 0x90041, 0x47 }, - { 0x90042, 0x630 }, + { 0x90042, 0x633 }, { 0x90043, 0x149 }, { 0x90044, 0x4f }, - { 0x90045, 0x630 }, + { 0x90045, 0x633 }, { 0x90046, 0x179 }, { 0x90047, 0x8 }, { 0x90048, 0xe0 }, @@ -1261,25 +1265,25 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90054, 0x448 }, { 0x90055, 0x109 }, { 0x90056, 0x40 }, - { 0x90057, 0x630 }, + { 0x90057, 0x633 }, { 0x90058, 0x179 }, { 0x90059, 0x1 }, { 0x9005a, 0x618 }, { 0x9005b, 0x109 }, { 0x9005c, 0x40c0 }, - { 0x9005d, 0x630 }, + { 0x9005d, 0x633 }, { 0x9005e, 0x149 }, { 0x9005f, 0x8 }, { 0x90060, 0x4 }, { 0x90061, 0x48 }, { 0x90062, 0x4040 }, - { 0x90063, 0x630 }, + { 0x90063, 0x633 }, { 0x90064, 0x149 }, { 0x90065, 0x0 }, { 0x90066, 0x4 }, { 0x90067, 0x48 }, { 0x90068, 0x40 }, - { 0x90069, 0x630 }, + { 0x90069, 0x633 }, { 0x9006a, 0x149 }, { 0x9006b, 0x10 }, { 0x9006c, 0x4 }, @@ -1288,22 +1292,22 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x9006f, 0x4 }, { 0x90070, 0x78 }, { 0x90071, 0x549 }, - { 0x90072, 0x630 }, + { 0x90072, 0x633 }, { 0x90073, 0x159 }, { 0x90074, 0xd49 }, - { 0x90075, 0x630 }, + { 0x90075, 0x633 }, { 0x90076, 0x159 }, { 0x90077, 0x94a }, - { 0x90078, 0x630 }, + { 0x90078, 0x633 }, { 0x90079, 0x159 }, { 0x9007a, 0x441 }, - { 0x9007b, 0x630 }, + { 0x9007b, 0x633 }, { 0x9007c, 0x149 }, { 0x9007d, 0x42 }, - { 0x9007e, 0x630 }, + { 0x9007e, 0x633 }, { 0x9007f, 0x149 }, { 0x90080, 0x1 }, - { 0x90081, 0x630 }, + { 0x90081, 0x633 }, { 0x90082, 0x149 }, { 0x90083, 0x0 }, { 0x90084, 0xe0 }, @@ -1329,18 +1333,15 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90098, 0x18 }, { 0x90099, 0x4 }, { 0x9009a, 0x58 }, - { 0x9009b, 0xa }, + { 0x9009b, 0xb }, { 0x9009c, 0x10 }, { 0x9009d, 0x109 }, - { 0x9009e, 0x2 }, + { 0x9009e, 0x1 }, { 0x9009f, 0x10 }, { 0x900a0, 0x109 }, { 0x900a1, 0x5 }, { 0x900a2, 0x7c0 }, { 0x900a3, 0x109 }, - { 0x900a4, 0x10 }, - { 0x900a5, 0x10 }, - { 0x900a6, 0x109 }, { 0x40000, 0x811 }, { 0x40020, 0x880 }, { 0x40040, 0x0 }, @@ -1385,7 +1386,7 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x4002a, 0xc15 }, { 0x4004a, 0x0 }, { 0x4006a, 0x0 }, - { 0x4000b, 0x623 }, + { 0x4000b, 0x625 }, { 0x4002b, 0x15 }, { 0x4004b, 0x0 }, { 0x4006b, 0x0 }, @@ -1397,7 +1398,7 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x4002d, 0xc1a }, { 0x4004d, 0x0 }, { 0x4006d, 0x0 }, - { 0x4000e, 0x623 }, + { 0x4000e, 0x625 }, { 0x4002e, 0x1a }, { 0x4004e, 0x0 }, { 0x4006e, 0x0 }, @@ -1449,17 +1450,20 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x4003a, 0x880 }, { 0x4005a, 0x0 }, { 0x4007a, 0x0 }, - { 0x900a7, 0x0 }, - { 0x900a8, 0x790 }, - { 0x900a9, 0x11a }, - { 0x900aa, 0x8 }, - { 0x900ab, 0x7aa }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, { 0x900ac, 0x2a }, - { 0x900ad, 0x10 }, - { 0x900ae, 0x7b2 }, - { 0x900af, 0x2a }, - { 0x900b0, 0x0 }, - { 0x900b1, 0x7c8 }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, { 0x900b2, 0x109 }, { 0x900b3, 0x10 }, { 0x900b4, 0x2a8 }, @@ -1557,7 +1561,7 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90110, 0x0 }, { 0x90111, 0x8b10 }, { 0x90112, 0x168 }, - { 0x90113, 0x0 }, + { 0x90113, 0x1 }, { 0x90114, 0xab10 }, { 0x90115, 0x168 }, { 0x90116, 0x0 }, @@ -1608,7 +1612,7 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90143, 0xf }, { 0x90144, 0x408 }, { 0x90145, 0x169 }, - { 0x90146, 0xc }, + { 0x90146, 0xd }, { 0x90147, 0x0 }, { 0x90148, 0x68 }, { 0x90149, 0x0 }, @@ -1626,67 +1630,58 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90155, 0x20 }, { 0x90156, 0x2aa }, { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x0 }, - { 0x90169, 0x8 }, - { 0x9016a, 0x8 }, - { 0x9016b, 0x448 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, { 0x9016c, 0x109 }, - { 0x9016d, 0xf }, - { 0x9016e, 0x7c0 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, { 0x9016f, 0x109 }, - { 0x90170, 0x0 }, - { 0x90171, 0xe8 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, { 0x90172, 0x109 }, - { 0x90173, 0x47 }, - { 0x90174, 0x630 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, { 0x90175, 0x109 }, { 0x90176, 0x8 }, - { 0x90177, 0x618 }, - { 0x90178, 0x109 }, - { 0x90179, 0x8 }, - { 0x9017a, 0xe0 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, { 0x9017b, 0x109 }, { 0x9017c, 0x0 }, - { 0x9017d, 0x7c8 }, - { 0x9017e, 0x109 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, { 0x9017f, 0x8 }, - { 0x90180, 0x8140 }, - { 0x90181, 0x10c }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, - { 0x9001f, 0x2a }, - { 0x90026, 0x6a }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1696,9 +1691,10 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, - { 0x2000b, 0x5d }, - { 0x2000c, 0xbb }, - { 0x2000d, 0x753 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x74 }, + { 0x2000c, 0xe8 }, + { 0x2000d, 0x915 }, { 0x2000e, 0x2c }, { 0x12000b, 0xc }, { 0x12000c, 0x19 }, @@ -1714,14 +1710,10 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x9000f, 0x6110 }, { 0x90010, 0x2152 }, { 0x90011, 0xdfbd }, - { 0x90012, 0x60 }, + { 0x90012, 0x2060 }, { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, - { 0x120010, 0x5a }, - { 0x120011, 0x3 }, - { 0x220010, 0x5a }, - { 0x220011, 0x3 }, { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, @@ -1797,15 +1789,16 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x136b4, 0x1 }, { 0x137b4, 0x1 }, { 0x138b4, 0x1 }, - { 0x2003a, 0x2 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, { 0xc0080, 0x2 }, { 0xd0000, 0x1 } }; -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { +struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 3000mts 1D */ - .drate = 3000, + /* P0 3732mts 1D */ + .drate = 3732, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1818,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 3000mts 2D */ - .drate = 3000, + /* P0 3732mts 2D */ + .drate = 3732, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1834,7 +1827,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_512mb = { +struct dram_timing_info dram_timing = { .ddrc_cfg = ddr_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), .ddrphy_cfg = ddr_ddrphy_cfg, @@ -1845,5 +1838,6 @@ struct dram_timing_info dram_timing_512mb = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 3732, 400, 100, }, }; + diff --git a/board/polyhex/imx8mp_debix_model_a/spl.c b/board/polyhex/imx8mp_debix_model_a/spl.c new file mode 100644 index 00000000000..eb904e116b1 --- /dev/null +++ b/board/polyhex/imx8mp_debix_model_a/spl.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018-2019, 2021 NXP + * Copyright 2023 Gilles Talis <gilles.talis@gmail.com> + */ + +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mp_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/sections.h> +#include <common.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <hang.h> +#include <init.h> +#include <log.h> +#include <power/pca9450.h> +#include <power/pmic.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + + puts("Normal Boot\n"); +} + +static int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("Failed to get PMIC\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output. */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */ + if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) + /* Set DVS0 to 0.85V for special case. */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); + + /* Set DVS1 to 0.85v for suspend. */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + + /* + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H). + */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* + * Kernel uses OD/OD frequency for SoC. + * To avoid timing risk from SoC to ARM, + * increase VDD_ARM to OD voltage 0.95V + */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + if (is_imx8mp() && + !strcmp(name, "imx8mp-debix-model-a")) + return 0; + + return -1; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index 386ed1b4fb2..d0249e71f09 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -399,21 +399,46 @@ int board_init(void) int board_late_init(void) { if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { - u32 rev; + /* + * Use the r4 dtb by default as those are the most + * widespread devices. + */ + u32 rev, dtb_rev = 4; char rev_str[3]; + char fdt_str[50]; env_set("board_name", "librem5"); if (fuse_read(9, 0, &rev)) { env_set("board_rev", BOARD_REV_ERROR); } else if (rev == 0) { + /* + * If the fuses aren't burnt we should use either the + * r2 or r3 DTB. The latter makes more sense as there + * are far more r3 devices out there. + */ + dtb_rev = 3; env_set("board_rev", BOARD_REV_UNKNOWN); } else if (rev > 0) { + if (rev == 1) + dtb_rev = 2; + else if (rev < dtb_rev) + dtb_rev = rev; + /* + * FCC-approved devices report '5' as their board + * revision but use the r4 DTB as the PCB's are + * functionally identical. + */ + else if (rev == 5) + dtb_rev = 4; sprintf(rev_str, "%u", rev); env_set("board_rev", rev_str); } printf("Board name: %s\n", env_get("board_name")); printf("Board rev: %s\n", env_get("board_rev")); + + sprintf(fdt_str, "freescale/imx8mq-librem5-r%u.dtb", dtb_rev); + env_set("fdtfile", fdt_str); } if (is_usb_boot()) { diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index c7e412b54ee..acdb840f209 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -93,7 +93,6 @@ F: configs/rock-4se-rk3399_defconfig F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi ROCK-PI-4 -M: Akash Gajjar <akash@openedev.com> M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/rock-pi-4-rk3399_defconfig diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index 1eb8a4886f4..0cdf5bc9812 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -1,19 +1,3 @@ -if TARGET_DRACO - -config SYS_BOARD - default "draco" - -config SYS_VENDOR - default "siemens" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "draco" - -endif - if TARGET_THUBAN config SYS_BOARD @@ -26,7 +10,7 @@ config SYS_SOC default "am33xx" config SYS_CONFIG_NAME - default "thuban" + default "draco-thuban" endif @@ -42,7 +26,7 @@ config SYS_SOC default "am33xx" config SYS_CONFIG_NAME - default "rastaban" + default "draco-rastaban" endif @@ -58,7 +42,7 @@ config SYS_SOC default "am33xx" config SYS_CONFIG_NAME - default "etamin" + default "draco-etamin" config NAND_CS_INIT def_bool y diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS index c73f18c002f..82e01eb62ed 100644 --- a/board/siemens/draco/MAINTAINERS +++ b/board/siemens/draco/MAINTAINERS @@ -1,11 +1,10 @@ DRACO BOARD -M: Samuel Egli <samuel.egli@siemens.com> +M: Enrico Leto <enrico.leto@siemens.com> S: Maintained F: board/siemens/draco/ -F: include/configs/draco.h -F: configs/draco_defconfig -F: configs/etamin_defconfig -F: include/configs/thuban.h -F: configs/thuban_defconfig -F: include/configs/rastaban.h -F: configs/rastaban_defconfig +F: configs/draco-etamin_defconfig +F: configs/draco-rastaban_defconfig +F: configs/draco-thuban_defconfig +F: include/configs/draco-etamin.h +F: include/configs/draco-rastaban.h +F: include/configs/draco-thuban.h diff --git a/board/siemens/iot2050/Kconfig b/board/siemens/iot2050/Kconfig index a6170aae807..96dcfc41000 100644 --- a/board/siemens/iot2050/Kconfig +++ b/board/siemens/iot2050/Kconfig @@ -6,16 +6,6 @@ # Le Jin <le.jin@siemens.com> # Jan Kiszka <jan.kiszka@siemens.com> -config TARGET_IOT2050_A53 - bool "IOT2050 running on A53" - select ARM64 - select SOC_K3_AM654 - select BOARD_LATE_INIT - select SYS_DISABLE_DCACHE_OPS - select BINMAN - help - This builds U-Boot for the IOT2050 devices. - if TARGET_IOT2050_A53 config SYS_BOARD diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index e119330bc0c..8edabf4404c 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -381,6 +381,7 @@ static bool has_emmc(void) return (mmc_get_op_cond(mmc, true) < 0) ? 0 : 1; } +/* Override the default implementation, DT model is not accurate */ int checkboard(void) { request_detect_gpios(); @@ -496,12 +497,6 @@ int ft_board_setup(void *fdt, struct bd_info *bd) } #endif -/* Override the default implementation, DT model is not accurate */ -int show_board_info(void) -{ - return checkboard(); -} - int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c index a8eb8d5cae2..77edb86e78c 100644 --- a/board/st/common/stm32mp_dfu.c +++ b/board/st/common/stm32mp_dfu.c @@ -73,7 +73,6 @@ static void board_get_alt_info_mmc(struct udevice *dev, char *buf) static void board_get_alt_info_mtd(struct mtd_info *mtd, char *buf) { struct mtd_info *part; - bool first = true; const char *name; int len, partnum = 0; @@ -86,17 +85,13 @@ static void board_get_alt_info_mtd(struct mtd_info *mtd, char *buf) "mtd %s=", name); len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, - "%s raw 0x0 0x%llx ", + "%s raw 0x0 0x%llx", name, mtd->size); list_for_each_entry(part, &mtd->partitions, node) { partnum++; - if (!first) - len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, ";"); - first = false; - len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, - "%s_%s part %d", + ";%s_%s part %d", name, part->name, partnum); } } @@ -128,24 +123,9 @@ void set_dfu_alt_info(char *interface, char *devstr) /* probe all MTD devices */ mtd_probe_devices(); - /* probe SPI flash device on a bus */ - if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) { - mtd = get_mtd_device_nm("nor0"); - if (!IS_ERR_OR_NULL(mtd)) + mtd_for_each_device(mtd) + if (!mtd_is_partition(mtd)) board_get_alt_info_mtd(mtd, buf); - - mtd = get_mtd_device_nm("nor1"); - if (!IS_ERR_OR_NULL(mtd)) - board_get_alt_info_mtd(mtd, buf); - } - - mtd = get_mtd_device_nm("nand0"); - if (!IS_ERR_OR_NULL(mtd)) - board_get_alt_info_mtd(mtd, buf); - - mtd = get_mtd_device_nm("spi-nand0"); - if (!IS_ERR_OR_NULL(mtd)) - board_get_alt_info_mtd(mtd, buf); } if (IS_ENABLED(CONFIG_DFU_VIRT)) { diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig new file mode 100644 index 00000000000..89039f068a2 --- /dev/null +++ b/board/st/stm32mp2/Kconfig @@ -0,0 +1,13 @@ +if TARGET_ST_STM32MP25X + +config SYS_BOARD + default "stm32mp2" + +config SYS_VENDOR + default "st" + +config SYS_CONFIG_NAME + default "stm32mp25_common" + +source "board/st/common/Kconfig" +endif diff --git a/board/st/stm32mp2/MAINTAINERS b/board/st/stm32mp2/MAINTAINERS new file mode 100644 index 00000000000..e6bea910f92 --- /dev/null +++ b/board/st/stm32mp2/MAINTAINERS @@ -0,0 +1,9 @@ +STM32MP2 BOARD +M: Patrice Chotard <patrice.chotard@st.com> +M: Patrick Delaunay <patrick.delaunay@st.com> +L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) +S: Maintained +F: arch/arm/dts/stm32mp25* +F: board/st/stm32mp2/ +F: configs/stm32mp25_defconfig +F: include/configs/stm32mp25_common.h diff --git a/board/st/stm32mp2/Makefile b/board/st/stm32mp2/Makefile new file mode 100644 index 00000000000..50352fb71b4 --- /dev/null +++ b/board/st/stm32mp2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +# +# Copyright (C) 2023, STMicroelectronics - All Rights Reserved +# + +obj-y += stm32mp2.o diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c new file mode 100644 index 00000000000..c97a7efff46 --- /dev/null +++ b/board/st/stm32mp2/stm32mp2.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_BOARD + +#include <config.h> +#include <env.h> +#include <fdt_support.h> +#include <asm/global_data.h> +#include <asm/arch/sys_proto.h> + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +/* board dependent setup after realloc */ +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + const void *fdt_compat; + int fdt_compat_len; + char dtb_name[256]; + int buf_len; + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) { + if (strncmp(fdt_compat, "st,", 3) != 0) { + env_set("board_name", fdt_compat); + } else { + env_set("board_name", fdt_compat + 3); + + buf_len = sizeof(dtb_name); + strlcpy(dtb_name, fdt_compat + 3, buf_len); + buf_len -= strlen(fdt_compat + 3); + strlcat(dtb_name, ".dtb", buf_len); + env_set("fdtfile", dtb_name); + } + } + } + + return 0; +} diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 00614372119..f556857a391 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -455,6 +455,11 @@ M: Jernej Skrabec <jernej.skrabec@siol.net> S: Maintained F: configs/orangepi_zero2_defconfig +ORANGEPI ZERO 3 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/orangepi_zero3_defconfig + ORANGEPI PC 2 BOARD M: Andre Przywara <andre.przywara@arm.com> S: Maintained diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile index 4ae3d606b58..61b55fcc55a 100644 --- a/board/technexion/pico-imx7d/Makefile +++ b/board/technexion/pico-imx7d/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2017 NXP Semiconductors -obj-y := pico-imx7d.o spl.o +obj-y := pico-imx7d.o spl.o ../../freescale/common/mmc.o diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 6e98b85b287..b12941ccf82 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -13,6 +13,7 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/io.h> #include <common.h> #include <miiphy.h> @@ -25,6 +26,11 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) +#define PICO_MMC0 0 +#define PICO_MMC0_BLK 2 +#define PICO_MMC1 1 +#define PICO_MMC1_BLK 0 + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -101,32 +107,6 @@ static int setup_fec(void) return set_clk_enet(ENET_125MHZ); } - -int board_phy_config(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe7; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} #endif static void setup_iomux_uart(void) @@ -176,6 +156,12 @@ int board_late_init(void) set_wdog_reset(wdog); +#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX) +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE) + board_late_mmc_env_init(); +#endif /* CONFIG_ENV_IS_IN_MMC or CONFIG_ENV_IS_NOWHERE */ +#endif + /* * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), * since we use PMIC_PWRON to reset the board. @@ -210,3 +196,53 @@ int board_ehci_hcd_init(int port) } return 0; } + +#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX) +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE) +int board_mmc_get_env_dev(int devno) +{ + int dev_env = 0; + + switch (get_boot_device()) { + case SD3_BOOT: + case MMC3_BOOT: + env_set("bootdev", "MMC3"); + dev_env = PICO_MMC0; + break; + case SD1_BOOT: + env_set("bootdev", "SD1"); + dev_env = PICO_MMC1; + break; + default: + printf("Wrong boot device!"); + } + + return dev_env; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + int blk_no = 0; + + switch (dev_no) { + case PICO_MMC0: + blk_no = PICO_MMC0_BLK; + break; + case PICO_MMC1: + blk_no = PICO_MMC1_BLK; + break; + default: + printf("Invalid MMC device!"); + } + + return blk_no; +} +#endif + +#if CONFIG_IS_ENABLED(ENV_IS_NOWHERE) +int mmc_get_env_dev(void) +{ + return board_mmc_get_env_dev(0); +} +#endif +#endif /* CONFIG_FSL_ESDHC_IMX */ diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index c6b21aaa42d..0192eafbaa1 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -15,6 +15,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch-mx7/mx7-ddr.h> #include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/gpio.h> #include <asm/sections.h> #include <fsl_esdhc_imx.h> @@ -159,7 +160,20 @@ void reset_cpu(void) #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) -static iomux_v3_cfg_t const usdhc3_pads[] = { +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +/* EMMC/SD */ +static const iomux_v3_cfg_t usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14) +static const iomux_v3_cfg_t usdhc3_emmc_pads[] = { MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -173,20 +187,83 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { - /* Assume uSDHC3 emmc is always present */ - return 1; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(struct bd_info *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + int ret; + u32 index; + + /* + * Following map is done: + * (USDHC) (Physical Port) + * usdhc3 SOM MicroSD/MMC + * usdhc1 Carrier board MicroSD + * Always set boot USDHC as mmc0 + */ + + imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads, + ARRAY_SIZE(usdhc3_emmc_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + + switch (get_boot_device()) { + case SD1_BOOT: + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case MMC3_BOOT: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case SD3_BOOT: + default: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + } + + for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) { + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; } #endif diff --git a/board/ti/am62ax/Kconfig b/board/ti/am62ax/Kconfig index 61f289faccd..51e7b3e0eab 100644 --- a/board/ti/am62ax/Kconfig +++ b/board/ti/am62ax/Kconfig @@ -3,32 +3,6 @@ # Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ # -choice - prompt "TI K3 AM62Ax based boards" - optional - -config TARGET_AM62A7_A53_EVM - bool "TI K3 based AM62A7 EVM running on A53" - select ARM64 - select BINMAN - imply BOARD - imply SPL_BOARD - imply TI_I2C_BOARD_DETECT - -config TARGET_AM62A7_R5_EVM - bool "TI K3 based AM62A7 EVM running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - imply TI_I2C_BOARD_DETECT - -endchoice - if TARGET_AM62A7_R5_EVM || TARGET_AM62A7_A53_EVM config SYS_BOARD diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env index bfed7f36084..a6d967e982d 100644 --- a/board/ti/am62ax/am62ax.env +++ b/board/ti/am62ax/am62ax.env @@ -1,16 +1,14 @@ #include <env/ti/ti_common.env> +#include <env/ti/default_findfdt.env> #include <env/ti/mmc.env> -default_device_tree=ti/k3-am62a7-sk.dtb -findfdt= - setenv name_fdt ${default_device_tree}; - setenv fdtfile ${name_fdt} name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 ${mtdparts} run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} +boot_targets=mmc1 mmc0 usb pxe dhcp boot=mmc mmcdev=1 bootpart=1:2 diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index f2dd3b4192e..cd3360a4302 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -8,7 +8,6 @@ #include <asm/arch/hardware.h> #include <asm/io.h> -#include <common.h> #include <dm/uclass.h> #include <env.h> #include <fdt_support.h> diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml index 15c4017bdac..1fb7d64cb89 100644 --- a/board/ti/am62ax/rm-cfg.yaml +++ b/board/ti/am62ax/rm-cfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM62ax +# Resource management configuration for AM62A # --- @@ -18,234 +18,234 @@ rm-cfg: host_cfg_entries: - #1 host_id: 12 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #2 - host_id: 30 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + host_id: 20 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #3 - host_id: 36 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #4 - host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #5 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #6 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #7 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #8 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #9 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #10 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #11 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #12 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #13 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #14 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #15 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #16 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #17 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #18 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #19 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #20 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #21 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #22 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #23 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #24 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #25 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #26 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #27 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #28 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #29 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #30 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #31 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #32 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 resasg: subhdr: magic: 0x7B25 - size : 8 - resasg_entries_size: 1032 - reserved : 0 + size: 8 + resasg_entries_size: 1064 + reserved: 0 resasg_entries: - start_resource: 0 @@ -253,896 +253,792 @@ rm-cfg: type: 64 host_id: 12 reserved: 0 - - start_resource: 16 num_resource: 4 type: 64 host_id: 35 reserved: 0 - - start_resource: 16 num_resource: 4 type: 64 host_id: 36 reserved: 0 - - start_resource: 20 num_resource: 22 type: 64 host_id: 30 reserved: 0 - - start_resource: 0 num_resource: 16 type: 192 host_id: 12 reserved: 0 - - start_resource: 34 num_resource: 2 type: 192 host_id: 30 reserved: 0 - - start_resource: 0 - num_resource: 4 + num_resource: 2 type: 320 host_id: 12 reserved: 0 - + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 36 + reserved: 0 - start_resource: 4 num_resource: 4 type: 320 host_id: 30 reserved: 0 - - start_resource: 0 num_resource: 26 type: 384 host_id: 128 reserved: 0 - - start_resource: 50176 num_resource: 164 type: 1666 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1 type: 1667 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1677 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1677 - host_id: 35 + host_id: 20 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1677 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1677 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 6 type: 1677 host_id: 128 reserved: 0 - - start_resource: 54 num_resource: 18 type: 1678 host_id: 12 reserved: 0 - - start_resource: 72 num_resource: 6 type: 1678 - host_id: 35 + host_id: 20 reserved: 0 - - start_resource: 72 num_resource: 6 type: 1678 host_id: 36 reserved: 0 - - start_resource: 78 num_resource: 2 type: 1678 host_id: 30 reserved: 0 - - start_resource: 80 num_resource: 2 type: 1678 host_id: 128 reserved: 0 - - start_resource: 32 num_resource: 12 type: 1679 host_id: 12 reserved: 0 - - start_resource: 44 num_resource: 6 type: 1679 - host_id: 35 + host_id: 20 reserved: 0 - - start_resource: 44 num_resource: 6 type: 1679 host_id: 36 reserved: 0 - - start_resource: 50 num_resource: 2 type: 1679 host_id: 30 reserved: 0 - - start_resource: 52 num_resource: 2 type: 1679 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1696 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1696 - host_id: 35 + host_id: 20 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1696 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1696 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 6 type: 1696 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1697 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1697 - host_id: 35 + host_id: 20 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1697 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1697 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 2 type: 1697 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 12 type: 1698 host_id: 12 reserved: 0 - - start_resource: 12 num_resource: 6 type: 1698 - host_id: 35 + host_id: 20 reserved: 0 - - start_resource: 12 num_resource: 6 type: 1698 host_id: 36 reserved: 0 - - start_resource: 18 num_resource: 2 type: 1698 host_id: 30 reserved: 0 - - start_resource: 20 num_resource: 2 type: 1698 host_id: 128 reserved: 0 - - start_resource: 6 - num_resource: 34 + num_resource: 26 type: 1802 host_id: 12 reserved: 0 - + - + start_resource: 32 + num_resource: 8 + type: 1802 + host_id: 20 + reserved: 0 - start_resource: 44 num_resource: 36 type: 1802 host_id: 35 reserved: 0 - - start_resource: 44 num_resource: 36 type: 1802 host_id: 36 reserved: 0 - - start_resource: 168 num_resource: 8 type: 1802 host_id: 30 reserved: 0 - - start_resource: 14 num_resource: 512 type: 1805 host_id: 12 reserved: 0 - - start_resource: 526 num_resource: 256 type: 1805 host_id: 35 reserved: 0 - - start_resource: 526 num_resource: 256 type: 1805 host_id: 36 reserved: 0 - - start_resource: 782 num_resource: 128 type: 1805 host_id: 30 reserved: 0 - - start_resource: 910 - num_resource: 626 + num_resource: 128 + type: 1805 + host_id: 20 + reserved: 0 + - + start_resource: 1038 + num_resource: 498 type: 1805 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1024 type: 1807 host_id: 128 reserved: 0 - - start_resource: 4096 num_resource: 29 type: 1808 host_id: 128 reserved: 0 - - start_resource: 4608 num_resource: 99 type: 1809 host_id: 128 reserved: 0 - - start_resource: 5120 num_resource: 24 type: 1810 host_id: 128 reserved: 0 - - start_resource: 5632 num_resource: 51 type: 1811 host_id: 128 reserved: 0 - - start_resource: 6144 num_resource: 51 type: 1812 host_id: 128 reserved: 0 - - start_resource: 6656 num_resource: 51 type: 1813 host_id: 128 reserved: 0 - - start_resource: 8192 num_resource: 32 type: 1814 host_id: 128 reserved: 0 - - start_resource: 8704 num_resource: 32 type: 1815 host_id: 128 reserved: 0 - - start_resource: 9216 num_resource: 32 type: 1816 host_id: 128 reserved: 0 - - start_resource: 9728 num_resource: 22 type: 1817 host_id: 128 reserved: 0 - - start_resource: 10240 num_resource: 22 type: 1818 host_id: 128 reserved: 0 - - start_resource: 10752 num_resource: 22 type: 1819 host_id: 128 reserved: 0 - - start_resource: 11264 num_resource: 28 type: 1820 host_id: 128 reserved: 0 - - start_resource: 11776 num_resource: 28 type: 1821 host_id: 128 reserved: 0 - - start_resource: 12288 num_resource: 28 type: 1822 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1 type: 1923 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1936 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1936 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1936 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1936 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1936 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 64 type: 1937 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 64 type: 1937 host_id: 30 reserved: 0 - - start_resource: 83 num_resource: 8 type: 1938 host_id: 12 reserved: 0 - - start_resource: 91 num_resource: 8 type: 1939 host_id: 12 reserved: 0 - - start_resource: 99 num_resource: 10 type: 1942 host_id: 12 reserved: 0 - - start_resource: 109 num_resource: 3 type: 1942 host_id: 35 reserved: 0 - - start_resource: 109 num_resource: 3 type: 1942 host_id: 36 reserved: 0 - - start_resource: 112 num_resource: 3 type: 1942 host_id: 30 reserved: 0 - - start_resource: 115 num_resource: 3 type: 1942 host_id: 128 reserved: 0 - - start_resource: 118 num_resource: 16 type: 1943 host_id: 12 reserved: 0 - - start_resource: 118 num_resource: 16 type: 1943 host_id: 30 reserved: 0 - - start_resource: 134 num_resource: 8 type: 1944 host_id: 12 reserved: 0 - - start_resource: 134 num_resource: 8 type: 1945 host_id: 12 reserved: 0 - - start_resource: 142 num_resource: 8 type: 1946 host_id: 12 reserved: 0 - - start_resource: 142 num_resource: 8 type: 1947 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1955 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1955 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1955 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1955 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1955 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 8 type: 1956 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 8 type: 1956 host_id: 30 reserved: 0 - - start_resource: 27 num_resource: 1 type: 1957 host_id: 12 reserved: 0 - - start_resource: 28 num_resource: 1 type: 1958 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1961 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1961 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1961 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1961 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1961 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1962 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1962 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1962 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1962 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1962 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 1 type: 1963 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 1 type: 1963 host_id: 30 reserved: 0 - - start_resource: 19 num_resource: 16 type: 1964 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 16 type: 1964 host_id: 30 reserved: 0 - - start_resource: 20 num_resource: 1 type: 1965 host_id: 12 reserved: 0 - - start_resource: 35 num_resource: 8 type: 1966 host_id: 12 reserved: 0 - - start_resource: 21 num_resource: 1 type: 1967 host_id: 12 reserved: 0 - - start_resource: 35 num_resource: 8 type: 1968 host_id: 12 reserved: 0 - - start_resource: 22 num_resource: 1 type: 1969 host_id: 12 reserved: 0 - - start_resource: 43 num_resource: 8 type: 1970 host_id: 12 reserved: 0 - - start_resource: 23 num_resource: 1 type: 1971 host_id: 12 reserved: 0 - - start_resource: 43 num_resource: 8 type: 1972 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 1 type: 2112 host_id: 128 reserved: 0 - - start_resource: 2 num_resource: 2 type: 2122 host_id: 12 reserved: 0 - - start_resource: 51200 num_resource: 12 type: 12738 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1 type: 12739 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 6 type: 12750 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 6 type: 12769 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 8 type: 12810 host_id: 12 reserved: 0 - - start_resource: 12288 num_resource: 128 type: 12813 host_id: 12 reserved: 0 - - start_resource: 3072 num_resource: 6 type: 12828 host_id: 128 reserved: 0 - - start_resource: 3584 num_resource: 6 type: 12829 host_id: 128 reserved: 0 - - start_resource: 4096 num_resource: 6 diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig index cd17e939e5a..610dacfdc08 100644 --- a/board/ti/am62x/Kconfig +++ b/board/ti/am62x/Kconfig @@ -3,28 +3,6 @@ # Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ # Suman Anna <s-anna@ti.com> -choice - prompt "TI K3 AM62x based boards" - optional - -config TARGET_AM625_A53_EVM - bool "TI K3 based AM625 EVM running on A53" - select ARM64 - select BINMAN - -config TARGET_AM625_R5_EVM - bool "TI K3 based AM625 EVM running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - -endchoice - if TARGET_AM625_A53_EVM config SYS_BOARD diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS index 6ac4e65f5af..105e741995e 100644 --- a/board/ti/am62x/MAINTAINERS +++ b/board/ti/am62x/MAINTAINERS @@ -6,10 +6,3 @@ F: board/ti/am62x/ F: include/configs/am62x_evm.h F: configs/am62x_evm_r5_defconfig F: configs/am62x_evm_a53_defconfig - -BEAGLEPLAY BOARD -M: Nishanth Menon <nm@ti.com> -M: Robert Nelson <robertcnelson@gmail.com> -M: Tom Rini <trini@konsulko.com> -S: Maintained -N: beagleplay diff --git a/board/ti/am62x/beagleplay_a53.config b/board/ti/am62x/beagleplay_a53.config deleted file mode 100644 index f0380416cc5..00000000000 --- a/board/ti/am62x/beagleplay_a53.config +++ /dev/null @@ -1,55 +0,0 @@ -# Defconfig fragment to apply on top of am62x_evm_a53_defconfig - -CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay" -CONFIG_OF_LIST="k3-am625-beagleplay" -CONFIG_SPL_OF_LIST="k3-am625-beagleplay" -CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load" -CONFIG_EXT4_WRITE=y -CONFIG_LZO=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -# Use the Beagleplay env file -CONFIG_ENV_SOURCE_FILE="beagleplay" -# Do not use emmc boot - we will use FS only -CONFIG_SUPPORT_EMMC_BOOT=n -CONFIG_MMC_IO_VOLTAGE=y -# CONFIG_SPL_MMC_IO_VOLTAGE is not set -CONFIG_MMC_UHS_SUPPORT=y -# CONFIG_SPL_MMC_UHS_SUPPORT is not set -CONFIG_MMC_HS200_SUPPORT=y -# CONFIG_SPL_MMC_HS200_SUPPORT is not set -# Enable GPIO control -CONFIG_DM_GPIO=y -CONFIG_SPL_GPIO=y -CONFIG_DA8XX_GPIO=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPIO_READ=y -# Enable LEDs -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_SPL_LED=y -CONFIG_SPL_LED_GPIO=y -# Enable I2C bus -CONFIG_SPL_I2C=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_OMAP24XX=y -CONFIG_CMD_I2C=y -# Regulator -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_CMD_REGULATOR=y -CONFIG_DM_REGULATOR_TPS65219=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_TPS65219=y -CONFIG_CMD_PMIC=y -# Uses Realtek phy rather than TI phy -CONFIG_PHY_TI_DP83867=n -CONFIG_PHY_REALTEK=y -# No SPI flash on Beagleplay -CONFIG_SPI=n -CONFIG_SPI_FLASH=n -CONFIG_SPL_DM_SPI_FLASH=n -CONFIG_SPL_SPI_FLASH_SUPPORT=n diff --git a/board/ti/am62x/beagleplay_r5.config b/board/ti/am62x/beagleplay_r5.config deleted file mode 100644 index 4ee0375a2a1..00000000000 --- a/board/ti/am62x/beagleplay_r5.config +++ /dev/null @@ -1,15 +0,0 @@ -# Defconfig fragment to apply on top of: -# am62x_evm_r5_defconfig -# -CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay" -CONFIG_OF_LIST="k3-am625-r5-beagleplay" -CONFIG_SPL_OF_LIST="k3-am625-r5-beagleplay" -# Do spl board init -CONFIG_SPL_BOARD_INIT=y -# Do not use emmc boot - we will use FS only -CONFIG_SUPPORT_EMMC_BOOT=n -# No SPI flash on Beagleplay -CONFIG_SPI=n -CONFIG_SPI_FLASH=n -CONFIG_SPL_DM_SPI_FLASH=n -CONFIG_SPL_SPI_FLASH_SUPPORT=n diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml index c28707be8e2..5a265ed1e8e 100644 --- a/board/ti/am62x/rm-cfg.yaml +++ b/board/ti/am62x/rm-cfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM62 +# Resource management configuration for AM62X # --- @@ -18,234 +18,234 @@ rm-cfg: host_cfg_entries: - #1 host_id: 12 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #2 host_id: 30 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #3 host_id: 36 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #4 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #5 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #6 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #7 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #8 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #9 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #10 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #11 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #12 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #13 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #14 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #15 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #16 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #17 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #18 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #19 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #20 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #21 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #22 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #23 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #24 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #25 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #26 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #27 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #28 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #29 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #30 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #31 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #32 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 resasg: subhdr: magic: 0x7B25 - size : 8 - resasg_entries_size: 960 - reserved : 0 + size: 8 + resasg_entries_size: 976 + reserved: 0 resasg_entries: - start_resource: 0 @@ -253,833 +253,726 @@ rm-cfg: type: 64 host_id: 12 reserved: 0 - - start_resource: 16 num_resource: 4 type: 64 host_id: 35 reserved: 0 - - start_resource: 16 num_resource: 4 type: 64 host_id: 36 reserved: 0 - - start_resource: 20 num_resource: 22 type: 64 host_id: 30 reserved: 0 - - start_resource: 0 num_resource: 16 type: 192 host_id: 12 reserved: 0 - - start_resource: 34 num_resource: 2 type: 192 host_id: 30 reserved: 0 - - start_resource: 0 - num_resource: 4 + num_resource: 2 type: 320 host_id: 12 reserved: 0 - + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 36 + reserved: 0 - start_resource: 4 num_resource: 4 type: 320 host_id: 30 reserved: 0 - - start_resource: 0 num_resource: 26 type: 384 host_id: 128 reserved: 0 - - start_resource: 50176 num_resource: 164 type: 1666 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1 type: 1667 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1677 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1677 host_id: 35 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1677 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1677 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 6 type: 1677 host_id: 128 reserved: 0 - - start_resource: 54 num_resource: 18 type: 1678 host_id: 12 reserved: 0 - - start_resource: 72 num_resource: 6 type: 1678 host_id: 35 reserved: 0 - - start_resource: 72 num_resource: 6 type: 1678 host_id: 36 reserved: 0 - - start_resource: 78 num_resource: 2 type: 1678 host_id: 30 reserved: 0 - - start_resource: 80 num_resource: 2 type: 1678 host_id: 128 reserved: 0 - - start_resource: 32 num_resource: 12 type: 1679 host_id: 12 reserved: 0 - - start_resource: 44 num_resource: 6 type: 1679 host_id: 35 reserved: 0 - - start_resource: 44 num_resource: 6 type: 1679 host_id: 36 reserved: 0 - - start_resource: 50 num_resource: 2 type: 1679 host_id: 30 reserved: 0 - - start_resource: 52 num_resource: 2 type: 1679 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1696 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1696 host_id: 35 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1696 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1696 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 6 type: 1696 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1697 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1697 host_id: 35 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1697 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1697 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 2 type: 1697 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 12 type: 1698 host_id: 12 reserved: 0 - - start_resource: 12 num_resource: 6 type: 1698 host_id: 35 reserved: 0 - - start_resource: 12 num_resource: 6 type: 1698 host_id: 36 reserved: 0 - - start_resource: 18 num_resource: 2 type: 1698 host_id: 30 reserved: 0 - - start_resource: 20 num_resource: 2 type: 1698 host_id: 128 reserved: 0 - - start_resource: 5 num_resource: 35 type: 1802 host_id: 12 reserved: 0 - - start_resource: 44 num_resource: 36 type: 1802 host_id: 35 reserved: 0 - - start_resource: 44 num_resource: 36 type: 1802 host_id: 36 reserved: 0 - - start_resource: 168 num_resource: 8 type: 1802 host_id: 30 reserved: 0 - - start_resource: 13 num_resource: 512 type: 1805 host_id: 12 reserved: 0 - - start_resource: 525 num_resource: 256 type: 1805 host_id: 35 reserved: 0 - - start_resource: 525 num_resource: 256 type: 1805 host_id: 36 reserved: 0 - - start_resource: 781 num_resource: 128 type: 1805 host_id: 30 reserved: 0 - - start_resource: 909 num_resource: 627 type: 1805 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1024 type: 1807 host_id: 128 reserved: 0 - - start_resource: 4096 num_resource: 29 type: 1808 host_id: 128 reserved: 0 - - start_resource: 4608 num_resource: 99 type: 1809 host_id: 128 reserved: 0 - - start_resource: 5120 num_resource: 24 type: 1810 host_id: 128 reserved: 0 - - start_resource: 5632 num_resource: 51 type: 1811 host_id: 128 reserved: 0 - - start_resource: 6144 num_resource: 51 type: 1812 host_id: 128 reserved: 0 - - start_resource: 6656 num_resource: 51 type: 1813 host_id: 128 reserved: 0 - - start_resource: 8192 num_resource: 32 type: 1814 host_id: 128 reserved: 0 - - start_resource: 8704 num_resource: 32 type: 1815 host_id: 128 reserved: 0 - - start_resource: 9216 num_resource: 32 type: 1816 host_id: 128 reserved: 0 - - start_resource: 9728 num_resource: 22 type: 1817 host_id: 128 reserved: 0 - - start_resource: 10240 num_resource: 22 type: 1818 host_id: 128 reserved: 0 - - start_resource: 10752 num_resource: 22 type: 1819 host_id: 128 reserved: 0 - - start_resource: 11264 num_resource: 28 type: 1820 host_id: 128 reserved: 0 - - start_resource: 11776 num_resource: 28 type: 1821 host_id: 128 reserved: 0 - - start_resource: 12288 num_resource: 28 type: 1822 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1 type: 1923 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1936 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1936 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1936 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1936 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1936 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 64 type: 1937 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 64 type: 1937 host_id: 36 reserved: 0 - - start_resource: 83 num_resource: 8 type: 1938 host_id: 12 reserved: 0 - - start_resource: 91 num_resource: 8 type: 1939 host_id: 12 reserved: 0 - - start_resource: 99 num_resource: 10 type: 1942 host_id: 12 reserved: 0 - - start_resource: 109 num_resource: 3 type: 1942 host_id: 35 reserved: 0 - - start_resource: 109 num_resource: 3 type: 1942 host_id: 36 reserved: 0 - - start_resource: 112 num_resource: 3 type: 1942 host_id: 30 reserved: 0 - - start_resource: 115 num_resource: 3 type: 1942 host_id: 128 reserved: 0 - - start_resource: 118 num_resource: 16 type: 1943 host_id: 12 reserved: 0 - - start_resource: 118 num_resource: 16 type: 1943 host_id: 36 reserved: 0 - - start_resource: 134 num_resource: 8 type: 1944 host_id: 12 reserved: 0 - - start_resource: 134 num_resource: 8 type: 1945 host_id: 12 reserved: 0 - - start_resource: 142 num_resource: 8 type: 1946 host_id: 12 reserved: 0 - - start_resource: 142 num_resource: 8 type: 1947 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1955 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1955 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1955 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1955 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1955 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 8 type: 1956 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 8 type: 1956 host_id: 36 reserved: 0 - - start_resource: 27 num_resource: 1 type: 1957 host_id: 12 reserved: 0 - - start_resource: 28 num_resource: 1 type: 1958 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1961 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1961 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1961 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1961 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1961 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1962 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1962 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1962 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1962 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1962 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 1 type: 1963 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 1 type: 1963 host_id: 36 reserved: 0 - - start_resource: 19 num_resource: 16 type: 1964 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 16 type: 1964 host_id: 36 reserved: 0 - - start_resource: 20 num_resource: 1 type: 1965 host_id: 12 reserved: 0 - - start_resource: 35 num_resource: 8 type: 1966 host_id: 12 reserved: 0 - - start_resource: 21 num_resource: 1 type: 1967 host_id: 12 reserved: 0 - - start_resource: 35 num_resource: 8 type: 1968 host_id: 12 reserved: 0 - - start_resource: 22 num_resource: 1 type: 1969 host_id: 12 reserved: 0 - - start_resource: 43 num_resource: 8 type: 1970 host_id: 12 reserved: 0 - - start_resource: 23 num_resource: 1 type: 1971 host_id: 12 reserved: 0 - - start_resource: 43 num_resource: 8 type: 1972 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 1 type: 2112 host_id: 128 reserved: 0 - - start_resource: 2 num_resource: 2 diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig index fb596e4adfc..b873476a9d5 100644 --- a/board/ti/am64x/Kconfig +++ b/board/ti/am64x/Kconfig @@ -2,32 +2,6 @@ # # Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ -choice - prompt "K3 AM64 based boards" - optional - -config TARGET_AM642_A53_EVM - bool "TI K3 based AM642 EVM running on A53" - select ARM64 - select BINMAN - imply BOARD - imply SPL_BOARD - imply TI_I2C_BOARD_DETECT - -config TARGET_AM642_R5_EVM - bool "TI K3 based AM642 EVM running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - imply TI_I2C_BOARD_DETECT - -endchoice - if TARGET_AM642_A53_EVM config SYS_BOARD diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index a080b2b0d25..a6dcff2eb43 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -7,7 +7,6 @@ * */ -#include <common.h> #include <asm/io.h> #include <dm/uclass.h> #include <k3-ddrss.h> diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index 78c7040c3da..eb47a25c70a 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -3,30 +3,6 @@ # Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> -choice - prompt "K3 AM65 based boards" - optional - -config TARGET_AM654_A53_EVM - bool "TI K3 based AM654 EVM running on A53" - select ARM64 - select SYS_DISABLE_DCACHE_OPS - select BOARD_LATE_INIT - select BINMAN - imply TI_I2C_BOARD_DETECT - -config TARGET_AM654_R5_EVM - bool "TI K3 based AM654 EVM running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select K3_AM654_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - imply TI_I2C_BOARD_DETECT - -endchoice - if TARGET_AM654_A53_EVM config SYS_BOARD diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 9de3ddaa280..df209021c1b 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -7,7 +7,6 @@ * */ -#include <common.h> #include <dm.h> #include <fdt_support.h> #include <image.h> @@ -74,13 +73,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = 0x80000000; gd->bd->bi_dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = 0x880000000; gd->bd->bi_dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index 9505330ef30..6990f6ef4a4 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -3,52 +3,6 @@ # Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> -choice - prompt "K3 J721E based boards" - optional - -config TARGET_J721E_A72_EVM - bool "TI K3 based J721E EVM running on A72" - select ARM64 - select BOARD_LATE_INIT - imply TI_I2C_BOARD_DETECT - select SYS_DISABLE_DCACHE_OPS - select BINMAN - -config TARGET_J721E_R5_EVM - bool "TI K3 based J721E EVM running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - imply TI_I2C_BOARD_DETECT - -config TARGET_J7200_A72_EVM - bool "TI K3 based J7200 EVM running on A72" - select ARM64 - select BOARD_LATE_INIT - imply TI_I2C_BOARD_DETECT - select SYS_DISABLE_DCACHE_OPS - select BINMAN - -config TARGET_J7200_R5_EVM - bool "TI K3 based J7200 EVM running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - imply TI_I2C_BOARD_DETECT - -endchoice - if TARGET_J721E_A72_EVM config SYS_BOARD diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index c13c6b2533a..c541880107e 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -7,22 +7,13 @@ * */ -#include <common.h> -#include <env.h> -#include <fdt_support.h> #include <generic-phy.h> #include <image.h> -#include <init.h> -#include <log.h> #include <net.h> #include <asm/arch/hardware.h> -#include <asm/global_data.h> #include <asm/gpio.h> -#include <asm/io.h> #include <spl.h> #include <dm.h> -#include <dm/uclass-internal.h> -#include <linux/printk.h> #include "../common/board_detect.h" @@ -70,13 +61,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = 0x80000000; gd->bd->bi_dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = 0x880000000; gd->bd->bi_dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif @@ -308,53 +299,54 @@ static int probe_daughtercards(void) printf("Detected: %s rev %s\n", ep.name, ep.version); daughter_card_detect_flags[i] = true; -#ifndef CONFIG_SPL_BUILD - int j; - /* - * Populate any MAC addresses from daughtercard into the U-Boot - * environment, starting with a card-specific offset so we can - * have multiple ext_cards contribute to the MAC pool in a well- - * defined manner. - */ - for (j = 0; j < mac_addr_cnt; j++) { - if (!is_valid_ethaddr((u8 *)mac_addr[j])) - continue; - - eth_env_set_enetaddr_by_index("eth", - ext_cards[i].eth_offset + j, - (uchar *)mac_addr[j]); + if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + int j; + /* + * Populate any MAC addresses from daughtercard into the U-Boot + * environment, starting with a card-specific offset so we can + * have multiple ext_cards contribute to the MAC pool in a well- + * defined manner. + */ + for (j = 0; j < mac_addr_cnt; j++) { + if (!is_valid_ethaddr((u8 *)mac_addr[j])) + continue; + + eth_env_set_enetaddr_by_index("eth", + ext_cards[i].eth_offset + j, + (uchar *)mac_addr[j]); + } } -#endif } -#ifndef CONFIG_SPL_BUILD - char name_overlays[1024] = { 0 }; - for (i = 0; i < ARRAY_SIZE(ext_cards); i++) { - if (!daughter_card_detect_flags[i]) - continue; + if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + char name_overlays[1024] = { 0 }; - /* Skip if no overlays are to be added */ - if (!strlen(ext_cards[i].dtbo_name)) - continue; + for (i = 0; i < ARRAY_SIZE(ext_cards); i++) { + if (!daughter_card_detect_flags[i]) + continue; - /* - * Make sure we are not running out of buffer space by checking - * if we can fit the new overlay, a trailing space to be used - * as a separator, plus the terminating zero. - */ - if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 > - sizeof(name_overlays)) - return -ENOMEM; - - /* Append to our list of overlays */ - strcat(name_overlays, ext_cards[i].dtbo_name); - strcat(name_overlays, " "); - } + /* Skip if no overlays are to be added */ + if (!strlen(ext_cards[i].dtbo_name)) + continue; - /* Apply device tree overlay(s) to the U-Boot environment, if any */ - if (strlen(name_overlays)) - return env_set("name_overlays", name_overlays); -#endif + /* + * Make sure we are not running out of buffer space by checking + * if we can fit the new overlay, a trailing space to be used + * as a separator, plus the terminating zero. + */ + if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 > + sizeof(name_overlays)) + return -ENOMEM; + + /* Append to our list of overlays */ + strcat(name_overlays, ext_cards[i].dtbo_name); + strcat(name_overlays, " "); + } + + /* Apply device tree overlay(s) to the U-Boot environment, if any */ + if (strlen(name_overlays)) + return env_set("name_overlays", name_overlays); + } return 0; } @@ -531,10 +523,8 @@ err_free_gpio: void spl_board_init(void) { -#if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC) struct udevice *dev; int ret; -#endif if ((IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM)) && @@ -543,24 +533,20 @@ void spl_board_init(void) probe_daughtercards(); } -#ifdef CONFIG_ESM_K3 - if (board_ti_k3_is("J721EX-PM2-SOM")) { + if (IS_ENABLED(CONFIG_ESM_K3)) { ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_esm), &dev); if (ret) printf("ESM init failed: %d\n", ret); } -#endif -#ifdef CONFIG_ESM_PMIC - if (board_ti_k3_is("J721EX-PM2-SOM")) { + if (IS_ENABLED(CONFIG_ESM_PMIC)) { ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(pmic_esm), &dev); if (ret) printf("ESM PMIC init failed: %d\n", ret); } -#endif if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) && IS_ENABLED(CONFIG_HBMC_AM654)) { struct udevice *dev; diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index 8cc8232fc13..cb27bf5e2b2 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -31,6 +31,7 @@ addr_mcur5f0_0load=0x89000000 name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw #endif +boot_targets=mmc1 mmc0 usb pxe dhcp boot=mmc mmcdev=1 bootpart=1:2 diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig index f6d1cb57653..40853a8fd66 100644 --- a/board/ti/j721s2/Kconfig +++ b/board/ti/j721s2/Kconfig @@ -3,32 +3,6 @@ # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ # David Huang <d-huang@ti.com> -choice - prompt "K3 J721S2 board" - optional - -config TARGET_J721S2_A72_EVM - bool "TI K3 based J721S2 EVM running on A72" - select ARM64 - select BOARD_LATE_INIT - imply TI_I2C_BOARD_DETECT - select SYS_DISABLE_DCACHE_OPS - select BINMAN - -config TARGET_J721S2_R5_EVM - bool "TI K3 based J721S2 EVM running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - imply TI_I2C_BOARD_DETECT - -endchoice - if TARGET_J721S2_A72_EVM config SYS_BOARD diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 01eb4965d92..1220cd84519 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -7,7 +7,6 @@ * */ -#include <common.h> #include <env.h> #include <fdt_support.h> #include <generic-phy.h> @@ -57,13 +56,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = 0x80000000; gd->bd->bi_dram[0].size = 0x7fffffff; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = 0x880000000; gd->bd->bi_dram[1].size = 0x37fffffff; gd->ram_size = 0x400000000; #endif diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index e2bbaba8b8c..b351ce64abf 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -215,7 +215,7 @@ int checkboard(void) build_info(); print_bootinfo(); - return 0; + return tdx_checkboard(); } static enum pcb_rev_t get_pcb_revision(void) diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index 85134315918..79a1c92da0a 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -95,7 +95,7 @@ int checkboard(void) { puts("Model: Toradex Apalis TK1 2GB\n"); - return 0; + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index fa6b7226fed..164fcc41f55 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -701,13 +701,16 @@ int board_late_init(void) env_set("board_rev", env_str); #endif /* CONFIG_BOARD_LATE_INIT */ -#ifdef CONFIG_CMD_USB_SDP - if (is_boot_from_usb()) { - printf("Serial Downloader recovery mode, using sdp command\n"); + if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { env_set("bootdelay", "0"); - env_set("bootcmd", "sdp 0"); + if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootcmd", "sdp 0"); + } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { + printf("Fastboot recovery mode, using fastboot command\n"); + env_set("bootcmd", "fastboot usb 0"); + } } -#endif /* CONFIG_CMD_USB_SDP */ return 0; } @@ -730,7 +733,8 @@ int checkboard(void) is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad", (gd->ram_size == 0x80000000) ? "2GB" : (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it); - return 0; + + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index ef71270d9f2..b9a2af33f19 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -50,7 +50,7 @@ int checkboard(void) printf("Model: Toradex Apalis T30 %dGB\n", (gd->ram_size == 0x40000000) ? 1 : 2); - return 0; + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 48fdb1e0971..a775f54eb3f 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -187,13 +187,16 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif -#ifdef CONFIG_CMD_USB_SDP - if (is_boot_from_usb()) { - printf("Serial Downloader recovery mode, using sdp command\n"); + if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { env_set("bootdelay", "0"); - env_set("bootcmd", "sdp 0"); + if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootcmd", "sdp 0"); + } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { + printf("Fastboot recovery mode, using fastboot command\n"); + env_set("bootcmd", "fastboot usb 0"); + } } -#endif /* CONFIG_CMD_USB_SDP */ #if defined(CONFIG_VIDEO) setup_lcd(); @@ -206,7 +209,7 @@ int checkboard(void) { printf("Model: Toradex Colibri iMX6ULL\n"); - return 0; + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 6c0b09787c8..d8cc72f323c 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -121,7 +121,7 @@ int checkboard(void) build_info(); print_bootinfo(); - return 0; + return tdx_checkboard(); } static void select_dt_from_module_version(void) diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index e6c9b10570d..784ca7f65f7 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -621,13 +621,16 @@ int board_late_init(void) env_set("board_rev", env_str); #endif -#ifdef CONFIG_CMD_USB_SDP - if (is_boot_from_usb()) { - printf("Serial Downloader recovery mode, using sdp command\n"); + if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { env_set("bootdelay", "0"); - env_set("bootcmd", "sdp 0"); + if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootcmd", "sdp 0"); + } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { + printf("Fastboot recovery mode, using fastboot command\n"); + env_set("bootcmd", "fastboot usb 0"); + } } -#endif /* CONFIG_CMD_USB_SDP */ return 0; } @@ -649,7 +652,8 @@ int checkboard(void) printf("Model: Toradex Colibri iMX6 %s %sMB%s\n", is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo", (gd->ram_size == 0x20000000) ? "512" : "256", it); - return 0; + + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index f0356af0082..7a59a786d98 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -66,7 +66,7 @@ int dram_init(void) } static iomux_v3_cfg_t const flash_detection_pads[] = { - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL) | MUX_MODE_SION, }; static iomux_v3_cfg_t const uart1_pads[] = { @@ -193,9 +193,9 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; /* - * Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST + * Enable GPIO SION on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST * is pulled high with 4.7k for eMMC devices. This allows to reliably - * detect eMMC/NAND flash + * detect eMMC vs NAND flash. */ imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads)); gpio_request(FLASH_DET_GPIO, "flash-detection-gpio"); @@ -279,7 +279,7 @@ int checkboard(void) printf("Model: Toradex Colibri iMX7%c\n", is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S'); - return 0; + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) @@ -360,13 +360,17 @@ int board_late_init(void) setup_lcd(); #endif -#if defined(CONFIG_CMD_USB_SDP) - if (is_boot_from_usb()) { - printf("Serial Downloader recovery mode, using sdp command\n"); + if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { env_set("bootdelay", "0"); - env_set("bootcmd", "sdp 0"); + if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootcmd", "sdp 0"); + } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { + printf("Fastboot recovery mode, using fastboot command\n"); + env_set("bootcmd", "fastboot usb 0"); + } } -#endif + if (is_emmc) env_set("variant", "-emmc"); else diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 1df9697b97c..5861cf7dc93 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -77,7 +77,7 @@ int checkboard(void) (get_nand_dev_by_index(0)->erasesize >> 10 == 512) ? ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A"); - return 0; + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index b6b004669c2..8cef098c8e5 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -32,7 +32,7 @@ int checkboard(void) { puts("Model: Toradex Colibri T30 1GB\n"); - return 0; + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index dcef2db360a..af9f2d379cf 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -373,7 +373,7 @@ int checkboard(void) else puts("Model: Toradex Colibri VF50\n"); - return 0; + return tdx_checkboard(); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index d1449143977..ed8f0a6a475 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -96,7 +96,7 @@ static const char *get_board_assembly(u16 ver_assembly) return ver_name; } -int show_board_info(void) +int tdx_checkboard(void) { unsigned char ethaddr[6]; diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h index d446e9f1d5c..44234dc49cd 100644 --- a/board/toradex/common/tdx-common.h +++ b/board/toradex/common/tdx-common.h @@ -11,5 +11,6 @@ int ft_common_board_setup(void *blob, struct bd_info *bd); u32 get_board_revision(void); +int tdx_checkboard(void); #endif /* _TDX_COMMON_H */ diff --git a/board/toradex/verdin-am62/Kconfig b/board/toradex/verdin-am62/Kconfig index e7522244070..fd65a96b3df 100644 --- a/board/toradex/verdin-am62/Kconfig +++ b/board/toradex/verdin-am62/Kconfig @@ -3,28 +3,6 @@ # Copyright 2023 Toradex # -choice - prompt "Toradex Verdin AM62 based boards" - optional - -config TARGET_VERDIN_AM62_A53 - bool "Toradex Verdin AM62 running on A53" - select ARM64 - select BINMAN - -config TARGET_VERDIN_AM62_R5 - bool "Toradex Verdin AM62 running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - -endchoice - if TARGET_VERDIN_AM62_A53 config SYS_BOARD diff --git a/board/tq/tqma6/tqma6q.cfg b/board/tq/tqma6/tqma6q.cfg index a49489aed3f..a345c4de93d 100644 --- a/board/tq/tqma6/tqma6q.cfg +++ b/board/tq/tqma6/tqma6q.cfg @@ -36,7 +36,7 @@ DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00003030 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index 730e266469b..d99d93b44ae 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -212,7 +212,7 @@ static char *board_string(int type) } /* Override the default implementation, DT model is not accurate */ -int show_board_info(void) +int checkboard(void) { int *board_type = (int *)OCRAM_START; diff --git a/board/variscite/imx8mn_var_som/MAINTAINERS b/board/variscite/imx8mn_var_som/MAINTAINERS index 068f807ae69..a0fb1546f2f 100644 --- a/board/variscite/imx8mn_var_som/MAINTAINERS +++ b/board/variscite/imx8mn_var_som/MAINTAINERS @@ -1,5 +1,5 @@ ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE -M: Ariel D'Alessandro <ariel.dalessandro@collabora.com> +M: Hugo Villeneuve <hvilleneuve@dimonoff.com> S: Maintained F: arch/arm/dts/imx8mn-var-som* F: board/variscite/imx8mn_var_som/ diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 61b9455a8f4..994fd4f7058 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -12,7 +12,6 @@ #include <fdt_support.h> #include <i2c_eeprom.h> #include <malloc.h> -#include <asm/io.h> #include <asm/global_data.h> #include <dt-bindings/gpio/gpio.h> #include <linux/libfdt.h> @@ -46,20 +45,8 @@ struct var_imx8_eeprom_info { u8 partnumber2[5]; /* Part number 2 */ } __packed; -static void setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); -} - int board_init(void) { - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - return 0; } diff --git a/board/xilinx/common/fru.c b/board/xilinx/common/fru.c index c916c3d6b4c..12b21317496 100644 --- a/board/xilinx/common/fru.c +++ b/board/xilinx/common/fru.c @@ -85,4 +85,4 @@ U_BOOT_CMD( fru, 8, 1, do_fru, "FRU table info", fru_help_text -) +); diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c index 9cc2cdcebf1..2a74e49aede 100644 --- a/board/xilinx/versal/cmds.c +++ b/board/xilinx/versal/cmds.c @@ -98,4 +98,4 @@ U_BOOT_LONGHELP(versal, U_BOOT_CMD(versal, 4, 1, do_versal, "versal sub-system", versal_help_text -) +); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 3b6581e3046..6c365910011 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -184,6 +184,7 @@ void set_dfu_alt_info(char *interface, char *devstr) "mmc 0=boot.bin fat 0 1;" "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); break; +#if defined(CONFIG_SPL_SPI_LOAD) case ZYNQ_BM_QSPI: snprintf(buf, DFU_ALT_BUF_LEN, "sf 0:0=boot.bin raw 0 0x1500000;" @@ -191,6 +192,7 @@ void set_dfu_alt_info(char *interface, char *devstr) CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, CONFIG_SYS_SPI_U_BOOT_OFFS); break; +#endif default: return; } diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index f1f3eff501e..9524688f27d 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -427,4 +427,4 @@ U_BOOT_CMD( zynqmp, 9, 1, do_zynqmp, "ZynqMP sub-system", zynqmp_help_text -) +); diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f1628030848..59feaaf6f32 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -681,3 +681,18 @@ void set_dfu_alt_info(char *interface, char *devstr) puts("DFU alt info setting: done\n"); } #endif + +#if defined(CONFIG_SPL_SPI_LOAD) +unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) +{ + u32 offset; + int multiboot = multi_boot(); + + offset = multiboot * SZ_32K; + offset += CONFIG_SYS_SPI_U_BOOT_OFFS; + + log_info("SPI offset:\t0x%x\n", offset); + + return offset; +} +#endif diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env new file mode 100644 index 00000000000..70384538ab1 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -0,0 +1,66 @@ +autoload=no +baudrate=115200 +boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr} +boot_efi_binary=if fdt addr ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr ${fdtcontroladdr};fi;load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/bootaa64.efi; if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r};else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi +boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}${boot_syslinux_conf} +boot_net_usb_start=usb start +boot_prefixes=/ /boot/ +boot_script_dhcp=boot.scr.uimg +boot_scripts=boot.scr.uimg boot.scr +boot_syslinux_conf=extlinux/extlinux.conf +bootcmd_dhcp=run boot_net_usb_start; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;setenv efi_fdtfile ${fdtfile}; setenv efi_old_vci ${bootp_vci};setenv efi_old_arch ${bootp_arch};setenv bootp_vci PXEClient:Arch:00011:UNDI:003000;setenv bootp_arch 0xb;if dhcp ${kernel_addr_r}; then tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r}; else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi;fi;setenv bootp_vci ${efi_old_vci};setenv bootp_arch ${efi_old_arch};setenv efi_fdtfile;setenv efi_old_arch;setenv efi_old_vci; +bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...; +bootcmd_mmc0=devnum=0; run mmc_boot +bootcmd_mmc1=devnum=1; run mmc_boot +bootcmd_pxe=run boot_net_usb_start; dhcp; if pxe get; then pxe boot; fi +bootcmd_usb0=devnum=0; run usb_boot +bootcmd_usb1=devnum=1; run usb_boot +bootcmd_usb2=devnum=2; run usb_boot +bootcmd_usb3=devnum=3; run usb_boot +bootdelay=2 +bootfstype=fat +bootm_low=0 +bootm_size=0x80000000 +distro_bootcmd=scsi_need_init=; for target in ${boot_targets}; do run bootcmd_${target}; done +efi_dtb_prefixes=/ /dtb/ /dtb/current/ +fdt_addr_r=0x40000000 +fdt_high=0x10000000 +fileaddr=0x18000000 +initrd_high=0x79000000 +kernel_addr_r=0x18000000 +load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile} +mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi +pxefile_addr_r=0x10000000 +ramdisk_addr_r=0x02100000 +scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_extlinux; run scan_dev_for_scripts; done;run scan_dev_for_efi; +scan_dev_for_boot_part=part list ${devtype} ${devnum} -bootable devplist; env exists devplist || setenv devplist 1; for distro_bootpart in ${devplist}; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then run scan_dev_for_boot; fi; done; setenv devplist +scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; for prefix in ${efi_dtb_prefixes}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${efi_fdtfile}; then run load_efi_dtb; fi;done;if test -e ${devtype} ${devnum}:${distro_bootpart} efi/boot/bootaa64.efi; then echo Found EFI removable media binary efi/boot/bootaa64.efi; run boot_efi_binary; echo EFI LOAD FAILED: continuing...; fi; setenv efi_fdtfile +scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${boot_syslinux_conf}; then echo Found ${prefix}${boot_syslinux_conf}; run boot_extlinux; echo SCRIPT FAILED: continuing...; fi +scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done +script_offset_f=0x3e80000 +script_size_f=0x80000 +scriptaddr=0x20000000 +usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi +preboot=setenv boot_targets; setenv modeboot; run board_setup + +# SOM specific boot methods +som_cc_boot=if test ${card1_name} = SCK-KV-G; then setenv boot_targets mmc1 usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; elif test ${card1_name} = SCK-KR-G; then setenv boot_targets usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; else test ${card1_name} = SCK-KD-G; setenv boot_targets usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; fi;" +som_mmc_boot=setenv boot_targets mmc0 && run distro_bootcmd + +k26_starter=SMK-K26-XCL2G +k24_starter=SMK-K24-XCL2G +bootcmd=setenv model $board_name && if setexpr model gsub .*$k24_starter* $k24_starter || setexpr model gsub .*$k26_starter* $k26_starter; then run som_cc_boot; else run som_mmc_boot; run som_cc_boot; fi + +usb_hub_init=mw 1000 0056 && sleep 1 && i2c write 1000 2d aa 2 -s + +# usb hub init +kv260_setup=i2c dev 1 && run usb_hub_init +# usb hub init +kr260_setup=i2c dev 1 && run usb_hub_init; i2c dev 2 && run usb_hub_init; +# usb hub init with enabling PM nodes for ... +kd240_setup=i2c dev 0 && run usb_hub_init;zynqmp pmufw node 33; zynqmp pmufw node 47 + +board_setup=\ +if test ${card1_name} = SCK-KV-G; then run kv260_setup; fi;\ +if test ${card1_name} = SCK-KR-G; then run kr260_setup; fi;\ +if test ${card1_name} = SCK-KD-G; then run kd240_setup; fi; diff --git a/boot/Kconfig b/boot/Kconfig index fbc49c5bca4..987ca731411 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -346,8 +346,16 @@ config PXE_UTILS help Utilities for parsing PXE file formats. -config BOOT_DEFAULTS - bool # Common defaults for standard boot and distroboot +config BOOT_DEFAULTS_FEATURES + bool + select SUPPORT_RAW_INITRD + select ENV_VARS_UBOOT_CONFIG + imply USB_STORAGE + imply EFI_PARTITION + imply ISO_PARTITION + +config BOOT_DEFAULTS_CMDS + bool imply USE_BOOTCOMMAND select CMD_ENV_EXISTS select CMD_EXT2 @@ -358,14 +366,14 @@ config BOOT_DEFAULTS select CMD_DHCP if CMD_NET select CMD_PING if CMD_NET select CMD_PXE if CMD_NET - select SUPPORT_RAW_INITRD - select ENV_VARS_UBOOT_CONFIG select CMD_BOOTI if ARM64 select CMD_BOOTZ if ARM && !ARM64 imply CMD_MII if NET - imply USB_STORAGE - imply EFI_PARTITION - imply ISO_PARTITION + +config BOOT_DEFAULTS + bool # Common defaults for standard boot and distroboot + select BOOT_DEFAULTS_FEATURES + select BOOT_DEFAULTS_CMDS if CMDLINE help These are not required but are commonly needed to support a good selection of booting methods. Enable this to improve the capability @@ -431,7 +439,6 @@ config BOOTSTD_FULL config BOOTSTD_DEFAULTS bool "Select some common defaults for standard boot" depends on BOOTSTD - imply USE_BOOTCOMMAND select BOOT_DEFAULTS select BOOTMETH_DISTRO help @@ -452,6 +459,18 @@ config BOOTSTD_BOOTCOMMAND standard boot does not support all of the features of distro boot yet. +config BOOTSTD_PROG + bool "Use programmatic boot" + depends on !CMDLINE + default y + help + Enable this to provide a board_run_command() function which can boot + a systen without using commands. If the boot fails, then U-Boot will + panic. + + Note: This currently has many limitations and is not a useful booting + solution. Future work will eventually make this a viable option. + config BOOTMETH_GLOBAL bool help @@ -504,7 +523,7 @@ config BOOTMETH_EXTLINUX_PXE config BOOTMETH_EFILOADER bool "Bootdev support for EFI boot" - depends on EFI_LOADER + depends on BOOTEFI_BOOTMGR default y help Enables support for EFI boot using bootdevs. This makes the @@ -536,10 +555,10 @@ config BOOTMETH_VBE config BOOTMETH_DISTRO bool # Options needed to boot any distro - select BOOTMETH_SCRIPT # E.g. Armbian uses scripts + select BOOTMETH_SCRIPT if CMDLINE # E.g. Armbian uses scripts select BOOTMETH_EXTLINUX # E.g. Debian uses these select BOOTMETH_EXTLINUX_PXE if CMD_PXE && CMD_NET && DM_ETH - select BOOTMETH_EFILOADER if EFI_LOADER # E.g. Ubuntu uses this + select BOOTMETH_EFILOADER if BOOTEFI_BOOTMGR # E.g. Ubuntu uses this config SPL_BOOTMETH_VBE bool "Bootdev support for Verified Boot for Embedded (SPL)" @@ -664,6 +683,7 @@ config BOOTMETH_SANDBOX config BOOTMETH_SCRIPT bool "Bootdev support for U-Boot scripts" default y if BOOTSTD_FULL + depends on CMDLINE select HUSH_PARSER help Enables support for booting a distro via a U-Boot script. This makes @@ -717,6 +737,17 @@ if MEASURED_BOOT event log memory region. endif # MEASURED_BOOT +config SYS_BOOTM_LEN + hex "Maximum size of a decompresed OS image" + depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \ + LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT + default 0x4000000 if PPC || ARM64 + default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7 + default 0x800000 + help + This is the maximum size of the buffer that is used to decompress the OS + image in to if attempting to boot a compressed image. + config SUPPORT_RAW_INITRD bool "Enable raw initrd images" help @@ -809,6 +840,7 @@ endmenu # Boot images config DISTRO_DEFAULTS bool "(deprecated) Script-based booting of Linux distributions" + select CMDLINE select BOOT_DEFAULTS select AUTO_COMPLETE select CMDLINE_EDITING @@ -1194,14 +1226,16 @@ menu "Autoboot options" config AUTOBOOT bool "Autoboot" + depends on CMDLINE default y help This enables the autoboot. See doc/README.autoboot for detail. +if AUTOBOOT + config BOOTDELAY int "delay in seconds before automatically booting" default 2 - depends on AUTOBOOT help Delay before automatically running bootcmd; set to 0 to autoboot with no delay, but you can stop it by key input. @@ -1223,9 +1257,11 @@ config AUTOBOOT_KEYED U-Boot automatic booting process and bring the device to the U-Boot prompt for user input. +if AUTOBOOT_KEYED + config AUTOBOOT_FLUSH_STDIN bool "Enable flushing stdin before starting to read the password" - depends on AUTOBOOT_KEYED && !SANDBOX + depends on !SANDBOX help When this option is enabled stdin buffer will be flushed before starting to read the password. @@ -1234,7 +1270,6 @@ config AUTOBOOT_FLUSH_STDIN config AUTOBOOT_PROMPT string "Autoboot stop prompt" - depends on AUTOBOOT_KEYED default "Autoboot in %d seconds\\n" help This string is displayed before the boot delay selected by @@ -1250,7 +1285,6 @@ config AUTOBOOT_PROMPT config AUTOBOOT_ENCRYPTION bool "Enable encryption in autoboot stopping" - depends on AUTOBOOT_KEYED help This option allows a string to be entered into U-Boot to stop the autoboot. @@ -1277,7 +1311,7 @@ config AUTOBOOT_SHA256_FALLBACK config AUTOBOOT_DELAY_STR string "Delay autobooting via specific input key / string" - depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION + depends on !AUTOBOOT_ENCRYPTION help This option delays the automatic boot feature by issuing a specific input key or string. If CONFIG_AUTOBOOT_DELAY_STR @@ -1289,7 +1323,7 @@ config AUTOBOOT_DELAY_STR config AUTOBOOT_STOP_STR string "Stop autobooting via specific input key / string" - depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION + depends on !AUTOBOOT_ENCRYPTION help This option enables stopping (aborting) of the automatic boot feature only by issuing a specific input key or @@ -1301,7 +1335,7 @@ config AUTOBOOT_STOP_STR config AUTOBOOT_KEYED_CTRLC bool "Enable Ctrl-C autoboot interruption" - depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION + depends on !AUTOBOOT_ENCRYPTION help This option allows for the boot sequence to be interrupted by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey". @@ -1310,7 +1344,7 @@ config AUTOBOOT_KEYED_CTRLC config AUTOBOOT_NEVER_TIMEOUT bool "Make the password entry never time-out" - depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION && CRYPT_PW + depends on AUTOBOOT_ENCRYPTION && CRYPT_PW help This option removes the timeout from the password entry when the user first presses the <Enter> key before entering @@ -1318,7 +1352,7 @@ config AUTOBOOT_NEVER_TIMEOUT config AUTOBOOT_STOP_STR_ENABLE bool "Enable fixed string to stop autobooting" - depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION + depends on AUTOBOOT_ENCRYPTION help This option enables the feature to add a fixed stop string that is defined at compile time. @@ -1349,9 +1383,12 @@ config AUTOBOOT_STOP_STR_SHA256 includes a ":", the portion prior to the ":" will be treated as a salt value. +endif # AUTOBOOT_KEYED + +if !AUTOBOOT_KEYED + config AUTOBOOT_USE_MENUKEY bool "Allow a specify key to run a menu from the environment" - depends on !AUTOBOOT_KEYED help If a specific key is pressed to stop autoboot, then the commands in the environment variable 'menucmd' are executed before boot starts. @@ -1366,6 +1403,10 @@ config AUTOBOOT_MENUKEY For example, 33 means "!" in ASCII, so pressing ! at boot would take this action. +endif + +endif # AUTOBOOT + config AUTOBOOT_MENU_SHOW bool "Show a menu on boot" depends on CMD_BOOTMENU @@ -1561,6 +1602,7 @@ config BOOTARGS_SUBST config USE_BOOTCOMMAND bool "Enable a default value for bootcmd" + depends on CMDLINE help Provide a default value for the bootcmd entry in the environment. If autoboot is enabled this is what will be run automatically. Enable @@ -1580,6 +1622,7 @@ config BOOTCOMMAND config USE_PREBOOT bool "Enable preboot" + depends on CMDLINE help When this option is enabled, the existence of the environment variable "preboot" will be checked immediately before starting the diff --git a/boot/Makefile b/boot/Makefile index ad608598d29..a90ebea5a86 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -25,14 +25,16 @@ obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow.o obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootmeth-uclass.o obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootstd-uclass.o +obj-$(CONFIG_$(SPL_TPL_)BOOTSTD_PROG) += prog_boot.o + obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX) += bootmeth_extlinux.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX_PXE) += bootmeth_pxe.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFILOADER) += bootmeth_efi.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootmeth_cros.o +obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL -obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += bootmeth_efi_mgr.o +obj-$(CONFIG_BOOTEFI_BOOTMGR) += bootmeth_efi_mgr.o obj-$(CONFIG_$(SPL_TPL_)EXPO) += bootflow_menu.o obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow_menu.o obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o diff --git a/boot/bootm.c b/boot/bootm.c index cb61485c226..301cfded05c 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -44,14 +44,200 @@ DECLARE_GLOBAL_DATA_PTR; struct bootm_headers images; /* pointers to os/initrd/fdt images */ -static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[], struct bootm_headers *images, - ulong *os_data, ulong *os_len); - __weak void board_quiesce_devices(void) { } +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) +/** + * image_get_kernel - verify legacy format kernel image + * @img_addr: in RAM address of the legacy format image to be verified + * @verify: data CRC verification flag + * + * image_get_kernel() verifies legacy image integrity and returns pointer to + * legacy image header if image verification was completed successfully. + * + * returns: + * pointer to a legacy image header if valid image was found + * otherwise return NULL + */ +static struct legacy_img_hdr *image_get_kernel(ulong img_addr, int verify) +{ + struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)img_addr; + + if (!image_check_magic(hdr)) { + puts("Bad Magic Number\n"); + bootstage_error(BOOTSTAGE_ID_CHECK_MAGIC); + return NULL; + } + bootstage_mark(BOOTSTAGE_ID_CHECK_HEADER); + + if (!image_check_hcrc(hdr)) { + puts("Bad Header Checksum\n"); + bootstage_error(BOOTSTAGE_ID_CHECK_HEADER); + return NULL; + } + + bootstage_mark(BOOTSTAGE_ID_CHECK_CHECKSUM); + image_print_contents(hdr); + + if (verify) { + puts(" Verifying Checksum ... "); + if (!image_check_dcrc(hdr)) { + printf("Bad Data CRC\n"); + bootstage_error(BOOTSTAGE_ID_CHECK_CHECKSUM); + return NULL; + } + puts("OK\n"); + } + bootstage_mark(BOOTSTAGE_ID_CHECK_ARCH); + + if (!image_check_target_arch(hdr)) { + printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr)); + bootstage_error(BOOTSTAGE_ID_CHECK_ARCH); + return NULL; + } + return hdr; +} +#endif + +/** + * boot_get_kernel() - find kernel image + * + * @addr_fit: first argument to bootm: address, fit configuration, etc. + * @os_data: pointer to a ulong variable, will hold os data start address + * @os_len: pointer to a ulong variable, will hold os data length + * address and length, otherwise NULL + * pointer to image header if valid image was found, plus kernel start + * @kernp: image header if valid image was found, otherwise NULL + * + * boot_get_kernel() tries to find a kernel image, verifies its integrity + * and locates kernel data. + * + * Return: 0 on success, -ve on error. -EPROTOTYPE means that the image is in + * a wrong or unsupported format + */ +static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images, + ulong *os_data, ulong *os_len, const void **kernp) +{ +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) + struct legacy_img_hdr *hdr; +#endif + ulong img_addr; + const void *buf; + const char *fit_uname_config = NULL, *fit_uname_kernel = NULL; +#if CONFIG_IS_ENABLED(FIT) + int os_noffset; +#endif + +#ifdef CONFIG_ANDROID_BOOT_IMAGE + const void *boot_img; + const void *vendor_boot_img; +#endif + img_addr = genimg_get_kernel_addr_fit(addr_fit, &fit_uname_config, + &fit_uname_kernel); + + if (IS_ENABLED(CONFIG_CMD_BOOTM_PRE_LOAD)) + img_addr += image_load_offset; + + bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC); + + /* check image type, for FIT images get FIT kernel node */ + *os_data = *os_len = 0; + buf = map_sysmem(img_addr, 0); + switch (genimg_get_format(buf)) { +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) + case IMAGE_FORMAT_LEGACY: + printf("## Booting kernel from Legacy Image at %08lx ...\n", + img_addr); + hdr = image_get_kernel(img_addr, images->verify); + if (!hdr) + return -EINVAL; + bootstage_mark(BOOTSTAGE_ID_CHECK_IMAGETYPE); + + /* get os_data and os_len */ + switch (image_get_type(hdr)) { + case IH_TYPE_KERNEL: + case IH_TYPE_KERNEL_NOLOAD: + *os_data = image_get_data(hdr); + *os_len = image_get_data_size(hdr); + break; + case IH_TYPE_MULTI: + image_multi_getimg(hdr, 0, os_data, os_len); + break; + case IH_TYPE_STANDALONE: + *os_data = image_get_data(hdr); + *os_len = image_get_data_size(hdr); + break; + default: + bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE); + return -EPROTOTYPE; + } + + /* + * copy image header to allow for image overwrites during + * kernel decompression. + */ + memmove(&images->legacy_hdr_os_copy, hdr, + sizeof(struct legacy_img_hdr)); + + /* save pointer to image header */ + images->legacy_hdr_os = hdr; + + images->legacy_hdr_valid = 1; + bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE); + break; +#endif +#if CONFIG_IS_ENABLED(FIT) + case IMAGE_FORMAT_FIT: + os_noffset = fit_image_load(images, img_addr, + &fit_uname_kernel, &fit_uname_config, + IH_ARCH_DEFAULT, IH_TYPE_KERNEL, + BOOTSTAGE_ID_FIT_KERNEL_START, + FIT_LOAD_IGNORED, os_data, os_len); + if (os_noffset < 0) + return -ENOENT; + + images->fit_hdr_os = map_sysmem(img_addr, 0); + images->fit_uname_os = fit_uname_kernel; + images->fit_uname_cfg = fit_uname_config; + images->fit_noffset_os = os_noffset; + break; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + case IMAGE_FORMAT_ANDROID: { + int ret; + + boot_img = buf; + vendor_boot_img = NULL; + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { + boot_img = map_sysmem(get_abootimg_addr(), 0); + vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0); + } + printf("## Booting Android Image at 0x%08lx ...\n", img_addr); + ret = android_image_get_kernel(boot_img, vendor_boot_img, + images->verify, os_data, os_len); + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { + unmap_sysmem(vendor_boot_img); + unmap_sysmem(boot_img); + } + if (ret) + return ret; + break; + } +#endif + default: + bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE); + return -EPROTOTYPE; + } + + debug(" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n", + *os_data, *os_len, *os_len); + *kernp = buf; + + return 0; +} + #ifdef CONFIG_LMB static void boot_start_lmb(struct bootm_headers *images) { @@ -69,8 +255,7 @@ static void boot_start_lmb(struct bootm_headers *images) static inline void boot_start_lmb(struct bootm_headers *images) { } #endif -static int bootm_start(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +static int bootm_start(void) { memset((void *)&images, 0, sizeof(images)); images.verify = env_get_yesno("verify"); @@ -83,22 +268,31 @@ static int bootm_start(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } -static ulong bootm_data_addr(int argc, char *const argv[]) +static ulong bootm_data_addr(const char *addr_str) { ulong addr; - if (argc > 0) - addr = simple_strtoul(argv[0], NULL, 16); + if (addr_str) + addr = hextoul(addr_str, NULL); else addr = image_load_addr; return addr; } -static int bootm_pre_load(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +/** + * bootm_pre_load() - Handle the pre-load processing + * + * This can be used to do a full signature check of the image, for example. + * It calls image_pre_load() with the data address of the image to check. + * + * @addr_str: String containing load address in hex, or NULL to use + * image_load_addr + * Return: 0 if OK, CMD_RET_FAILURE on failure + */ +static int bootm_pre_load(const char *addr_str) { - ulong data_addr = bootm_data_addr(argc, argv); + ulong data_addr = bootm_data_addr(addr_str); int ret = 0; if (IS_ENABLED(CONFIG_CMD_BOOTM_PRE_LOAD)) @@ -110,8 +304,14 @@ static int bootm_pre_load(struct cmd_tbl *cmdtp, int flag, int argc, return ret; } -static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +/** + * bootm_find_os(): Find the OS to boot + * + * @cmd_name: Command name that started this boot, e.g. "bootm" + * @addr_fit: Address and/or FIT specifier (first arg of bootm command) + * Return: 0 on success, -ve on error + */ +static int bootm_find_os(const char *cmd_name, const char *addr_fit) { const void *os_hdr; #ifdef CONFIG_ANDROID_BOOT_IMAGE @@ -122,10 +322,13 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, int ret; /* get kernel image header, start address and length */ - os_hdr = boot_get_kernel(cmdtp, flag, argc, argv, - &images, &images.os.image_start, &images.os.image_len); - if (images.os.image_len == 0) { - puts("ERROR: can't get kernel image!\n"); + ret = boot_get_kernel(addr_fit, &images, &images.os.image_start, + &images.os.image_len, &os_hdr); + if (ret) { + if (ret == -EPROTOTYPE) + printf("Wrong Image Type for %s command\n", cmd_name); + + printf("ERROR %dE: can't get kernel image!\n", ret); return 1; } @@ -240,24 +443,8 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, } if (images.os.type == IH_TYPE_KERNEL_NOLOAD) { - if (IS_ENABLED(CONFIG_CMD_BOOTI) && - images.os.arch == IH_ARCH_ARM64 && - images.os.os == IH_OS_LINUX) { - ulong image_addr; - ulong image_size; - - ret = booti_setup(images.os.image_start, &image_addr, - &image_size, true); - if (ret != 0) - return 1; - - images.os.type = IH_TYPE_KERNEL; - images.os.load = image_addr; - images.ep = image_addr; - } else { - images.os.load = images.os.image_start; - images.ep += images.os.image_start; - } + images.os.load = images.os.image_start; + images.ep += images.os.image_start; } images.os.start = map_to_sysmem(os_hdr); @@ -266,30 +453,58 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, } /** - * bootm_find_images - wrapper to find and locate various images - * @flag: Ignored Argument - * @argc: command argument count - * @argv: command argument list - * @start: OS image start address - * @size: OS image size + * check_overlap() - Check if an image overlaps the OS * - * boot_find_images() will attempt to load an available ramdisk, - * flattened device tree, as well as specifically marked - * "loadable" images (loadables are FIT only) - * - * Note: bootm_find_images will skip an image if it is not found - * - * @return: - * 0, if all existing images were loaded correctly - * 1, if an image is found but corrupted, or invalid + * @name: Name of image to check (used to print error) + * @base: Base address of image + * @end: End address of image (+1) + * @os_start: Start of OS + * @os_size: Size of OS in bytes + * Return: 0 if OK, -EXDEV if the image overlaps the OS */ -int bootm_find_images(int flag, int argc, char *const argv[], ulong start, - ulong size) +static int check_overlap(const char *name, ulong base, ulong end, + ulong os_start, ulong os_size) { + ulong os_end; + + if (!base) + return 0; + os_end = os_start + os_size; + + if ((base >= os_start && base < os_end) || + (end > os_start && end <= os_end) || + (base < os_start && end >= os_end)) { + printf("ERROR: %s image overlaps OS image (OS=%lx..%lx)\n", + name, os_start, os_end); + + return -EXDEV; + } + + return 0; +} + +int bootm_find_images(ulong img_addr, const char *conf_ramdisk, + const char *conf_fdt, ulong start, ulong size) +{ + const char *select = conf_ramdisk; + char addr_str[17]; + void *buf; int ret; + if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { + /* Look for an Android boot image */ + buf = map_sysmem(images.os.start, 0); + if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) { + strcpy(addr_str, simple_xtoa(img_addr)); + select = addr_str; + } + } + + if (conf_ramdisk) + select = conf_ramdisk; + /* find ramdisk */ - ret = boot_get_ramdisk(argc, argv, &images, IH_INITRD_ARCH, + ret = boot_get_ramdisk(select, &images, IH_INITRD_ARCH, &images.rd_start, &images.rd_end); if (ret) { puts("Ramdisk image is corrupt or invalid\n"); @@ -297,46 +512,33 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start, } /* check if ramdisk overlaps OS image */ - if (images.rd_start && (((ulong)images.rd_start >= start && - (ulong)images.rd_start < start + size) || - ((ulong)images.rd_end > start && - (ulong)images.rd_end <= start + size) || - ((ulong)images.rd_start < start && - (ulong)images.rd_end >= start + size))) { - printf("ERROR: RD image overlaps OS image (OS=0x%lx..0x%lx)\n", - start, start + size); + if (check_overlap("RD", images.rd_start, images.rd_end, start, size)) return 1; - } -#if CONFIG_IS_ENABLED(OF_LIBFDT) - /* find flattened device tree */ - ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images, - &images.ft_addr, &images.ft_len); - if (ret) { - puts("Could not find a valid device tree\n"); - return 1; - } + if (CONFIG_IS_ENABLED(OF_LIBFDT)) { + buf = map_sysmem(img_addr, 0); - /* check if FDT overlaps OS image */ - if (images.ft_addr && - (((ulong)images.ft_addr >= start && - (ulong)images.ft_addr < start + size) || - ((ulong)images.ft_addr + images.ft_len >= start && - (ulong)images.ft_addr + images.ft_len < start + size))) { - printf("ERROR: FDT image overlaps OS image (OS=0x%lx..0x%lx)\n", - start, start + size); - return 1; - } + /* find flattened device tree */ + ret = boot_get_fdt(buf, conf_fdt, IH_ARCH_DEFAULT, &images, + &images.ft_addr, &images.ft_len); + if (ret) { + puts("Could not find a valid device tree\n"); + return 1; + } - if (IS_ENABLED(CONFIG_CMD_FDT)) - set_working_fdt_addr(map_to_sysmem(images.ft_addr)); -#endif + /* check if FDT overlaps OS image */ + if (check_overlap("FDT", map_to_sysmem(images.ft_addr), + images.ft_len, start, size)) + return 1; + + if (IS_ENABLED(CONFIG_CMD_FDT)) + set_working_fdt_addr(map_to_sysmem(images.ft_addr)); + } #if CONFIG_IS_ENABLED(FIT) if (IS_ENABLED(CONFIG_FPGA)) { /* find bitstreams */ - ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT, - NULL, NULL); + ret = boot_get_fpga(&images); if (ret) { printf("FPGA image is corrupted or invalid\n"); return 1; @@ -344,8 +546,7 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start, } /* find all of the loadables */ - ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT, - NULL, NULL); + ret = boot_get_loadable(&images); if (ret) { printf("Loadable(s) is corrupt or invalid\n"); return 1; @@ -355,15 +556,17 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start, return 0; } -static int bootm_find_other(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +static int bootm_find_other(ulong img_addr, const char *conf_ramdisk, + const char *conf_fdt) { - if (((images.os.type == IH_TYPE_KERNEL) || - (images.os.type == IH_TYPE_KERNEL_NOLOAD) || - (images.os.type == IH_TYPE_MULTI)) && - (images.os.os == IH_OS_LINUX || - images.os.os == IH_OS_VXWORKS)) - return bootm_find_images(flag, argc, argv, 0, 0); + if ((images.os.type == IH_TYPE_KERNEL || + images.os.type == IH_TYPE_KERNEL_NOLOAD || + images.os.type == IH_TYPE_MULTI) && + (images.os.os == IH_OS_LINUX || images.os.os == IH_OS_VXWORKS || + images.os.os == IH_OS_EFI || images.os.os == IH_OS_TEE)) { + return bootm_find_images(img_addr, conf_ramdisk, conf_fdt, 0, + 0); + } return 0; } @@ -426,6 +629,24 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) void *load_buf, *image_buf; int err; + /* + * For a "noload" compressed kernel we need to allocate a buffer large + * enough to decompress in to and use that as the load address now. + * Assume that the kernel compression is at most a factor of 4 since + * zstd almost achieves that. + * Use an alignment of 2MB since this might help arm64 + */ + if (os.type == IH_TYPE_KERNEL_NOLOAD && os.comp != IH_COMP_NONE) { + ulong req_size = ALIGN(image_len * 4, SZ_1M); + + load = lmb_alloc(&images->lmb, req_size, SZ_2M); + if (!load) + return 1; + os.load = load; + debug("Allocated %lx bytes at %lx for kernel (size %lx) decompression\n", + req_size, load, image_len); + } + load_buf = map_sysmem(load, 0); image_buf = map_sysmem(os.image_start, image_len); err = image_decomp(os.comp, load, os.image_start, os.type, @@ -466,6 +687,31 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) } } + if (IS_ENABLED(CONFIG_CMD_BOOTI) && images->os.arch == IH_ARCH_ARM64 && + images->os.os == IH_OS_LINUX) { + ulong relocated_addr; + ulong image_size; + int ret; + + ret = booti_setup(load, &relocated_addr, &image_size, false); + if (ret) { + printf("Failed to prep arm64 kernel (err=%d)\n", ret); + return BOOTM_ERR_RESET; + } + + /* Handle BOOTM_STATE_LOADOS */ + if (relocated_addr != load) { + printf("Moving Image from 0x%lx to 0x%lx, end=%lx\n", + load, relocated_addr, + relocated_addr + image_size); + memmove((void *)relocated_addr, load_buf, image_size); + } + + images->ep = relocated_addr; + images->os.start = relocated_addr; + images->os.end = relocated_addr + image_size; + } + lmb_reserve(&images->lmb, images->os.load, (load_end - images->os.load)); return 0; @@ -783,16 +1029,21 @@ int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc, * any error. */ if (states & BOOTM_STATE_START) - ret = bootm_start(cmdtp, flag, argc, argv); + ret = bootm_start(); if (!ret && (states & BOOTM_STATE_PRE_LOAD)) - ret = bootm_pre_load(cmdtp, flag, argc, argv); + ret = bootm_pre_load(argv[0]); if (!ret && (states & BOOTM_STATE_FINDOS)) - ret = bootm_find_os(cmdtp, flag, argc, argv); + ret = bootm_find_os(cmdtp->name, argv[0]); - if (!ret && (states & BOOTM_STATE_FINDOTHER)) - ret = bootm_find_other(cmdtp, flag, argc, argv); + if (!ret && (states & BOOTM_STATE_FINDOTHER)) { + ulong img_addr; + + img_addr = argc ? hextoul(argv[0], NULL) : image_load_addr; + ret = bootm_find_other(img_addr, cmd_arg1(argc, argv), + cmd_arg2(argc, argv)); + } if (IS_ENABLED(CONFIG_MEASURED_BOOT) && !ret && (states & BOOTM_STATE_MEASURE)) @@ -934,193 +1185,6 @@ int bootm_boot_start(ulong addr, const char *cmdline) return ret; } -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) -/** - * image_get_kernel - verify legacy format kernel image - * @img_addr: in RAM address of the legacy format image to be verified - * @verify: data CRC verification flag - * - * image_get_kernel() verifies legacy image integrity and returns pointer to - * legacy image header if image verification was completed successfully. - * - * returns: - * pointer to a legacy image header if valid image was found - * otherwise return NULL - */ -static struct legacy_img_hdr *image_get_kernel(ulong img_addr, int verify) -{ - struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)img_addr; - - if (!image_check_magic(hdr)) { - puts("Bad Magic Number\n"); - bootstage_error(BOOTSTAGE_ID_CHECK_MAGIC); - return NULL; - } - bootstage_mark(BOOTSTAGE_ID_CHECK_HEADER); - - if (!image_check_hcrc(hdr)) { - puts("Bad Header Checksum\n"); - bootstage_error(BOOTSTAGE_ID_CHECK_HEADER); - return NULL; - } - - bootstage_mark(BOOTSTAGE_ID_CHECK_CHECKSUM); - image_print_contents(hdr); - - if (verify) { - puts(" Verifying Checksum ... "); - if (!image_check_dcrc(hdr)) { - printf("Bad Data CRC\n"); - bootstage_error(BOOTSTAGE_ID_CHECK_CHECKSUM); - return NULL; - } - puts("OK\n"); - } - bootstage_mark(BOOTSTAGE_ID_CHECK_ARCH); - - if (!image_check_target_arch(hdr)) { - printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr)); - bootstage_error(BOOTSTAGE_ID_CHECK_ARCH); - return NULL; - } - return hdr; -} -#endif - -/** - * boot_get_kernel - find kernel image - * @os_data: pointer to a ulong variable, will hold os data start address - * @os_len: pointer to a ulong variable, will hold os data length - * - * boot_get_kernel() tries to find a kernel image, verifies its integrity - * and locates kernel data. - * - * returns: - * pointer to image header if valid image was found, plus kernel start - * address and length, otherwise NULL - */ -static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[], struct bootm_headers *images, - ulong *os_data, ulong *os_len) -{ -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - struct legacy_img_hdr *hdr; -#endif - ulong img_addr; - const void *buf; - const char *fit_uname_config = NULL; - const char *fit_uname_kernel = NULL; -#if CONFIG_IS_ENABLED(FIT) - int os_noffset; -#endif - -#ifdef CONFIG_ANDROID_BOOT_IMAGE - const void *boot_img; - const void *vendor_boot_img; -#endif - img_addr = genimg_get_kernel_addr_fit(argc < 1 ? NULL : argv[0], - &fit_uname_config, - &fit_uname_kernel); - - if (IS_ENABLED(CONFIG_CMD_BOOTM_PRE_LOAD)) - img_addr += image_load_offset; - - bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC); - - /* check image type, for FIT images get FIT kernel node */ - *os_data = *os_len = 0; - buf = map_sysmem(img_addr, 0); - switch (genimg_get_format(buf)) { -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - case IMAGE_FORMAT_LEGACY: - printf("## Booting kernel from Legacy Image at %08lx ...\n", - img_addr); - hdr = image_get_kernel(img_addr, images->verify); - if (!hdr) - return NULL; - bootstage_mark(BOOTSTAGE_ID_CHECK_IMAGETYPE); - - /* get os_data and os_len */ - switch (image_get_type(hdr)) { - case IH_TYPE_KERNEL: - case IH_TYPE_KERNEL_NOLOAD: - *os_data = image_get_data(hdr); - *os_len = image_get_data_size(hdr); - break; - case IH_TYPE_MULTI: - image_multi_getimg(hdr, 0, os_data, os_len); - break; - case IH_TYPE_STANDALONE: - *os_data = image_get_data(hdr); - *os_len = image_get_data_size(hdr); - break; - default: - printf("Wrong Image Type for %s command\n", - cmdtp->name); - bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE); - return NULL; - } - - /* - * copy image header to allow for image overwrites during - * kernel decompression. - */ - memmove(&images->legacy_hdr_os_copy, hdr, - sizeof(struct legacy_img_hdr)); - - /* save pointer to image header */ - images->legacy_hdr_os = hdr; - - images->legacy_hdr_valid = 1; - bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE); - break; -#endif -#if CONFIG_IS_ENABLED(FIT) - case IMAGE_FORMAT_FIT: - os_noffset = fit_image_load(images, img_addr, - &fit_uname_kernel, &fit_uname_config, - IH_ARCH_DEFAULT, IH_TYPE_KERNEL, - BOOTSTAGE_ID_FIT_KERNEL_START, - FIT_LOAD_IGNORED, os_data, os_len); - if (os_noffset < 0) - return NULL; - - images->fit_hdr_os = map_sysmem(img_addr, 0); - images->fit_uname_os = fit_uname_kernel; - images->fit_uname_cfg = fit_uname_config; - images->fit_noffset_os = os_noffset; - break; -#endif -#ifdef CONFIG_ANDROID_BOOT_IMAGE - case IMAGE_FORMAT_ANDROID: - boot_img = buf; - vendor_boot_img = NULL; - if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { - boot_img = map_sysmem(get_abootimg_addr(), 0); - vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0); - } - printf("## Booting Android Image at 0x%08lx ...\n", img_addr); - if (android_image_get_kernel(boot_img, vendor_boot_img, images->verify, - os_data, os_len)) - return NULL; - if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { - unmap_sysmem(vendor_boot_img); - unmap_sysmem(boot_img); - } - break; -#endif - default: - printf("Wrong Image Format for %s command\n", cmdtp->name); - bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO); - return NULL; - } - - debug(" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n", - *os_data, *os_len, *os_len); - - return buf; -} - /** * switch_to_non_secure_mode() - switch to non-secure mode * diff --git a/boot/bootm_os.c b/boot/bootm_os.c index 9c035b5be88..dc4046ad082 100644 --- a/boot/bootm_os.c +++ b/boot/bootm_os.c @@ -317,13 +317,6 @@ static int do_bootm_vxworks_legacy(int flag, int argc, char *const argv[], if (flag != BOOTM_STATE_OS_GO) return 0; -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset("VxWorks"); - return 1; - } -#endif - do_bootvx_fdt(images); return 1; @@ -467,11 +460,6 @@ static int do_bootm_tee(int flag, int argc, char *const argv[], { int ret; - /* Verify OS type */ - if (images->os.os != IH_OS_TEE) { - return 1; - }; - /* Validate OPTEE header */ ret = optee_verify_bootm_image(images->os.image_start, images->os.load, @@ -479,11 +467,6 @@ static int do_bootm_tee(int flag, int argc, char *const argv[], if (ret) return ret; - /* Locate FDT etc */ - ret = bootm_find_images(flag, argc, argv, 0, 0); - if (ret) - return ret; - /* From here we can run the regular linux boot path */ return do_bootm_linux(flag, argc, argv, images); } @@ -494,48 +477,26 @@ static int do_bootm_efi(int flag, int argc, char *const argv[], struct bootm_headers *images) { int ret; - efi_status_t efi_ret; void *image_buf; if (flag != BOOTM_STATE_OS_GO) return 0; - /* Locate FDT, if provided */ - ret = bootm_find_images(flag, argc, argv, 0, 0); - if (ret) - return ret; - - /* Initialize EFI drivers */ - efi_ret = efi_init_obj_list(); - if (efi_ret != EFI_SUCCESS) { - printf("## Failed to initialize UEFI sub-system: r = %lu\n", - efi_ret & ~EFI_ERROR_MASK); - return 1; - } + /* We expect to return */ + images->os.type = IH_TYPE_STANDALONE; - /* Install device tree */ - efi_ret = efi_install_fdt(images->ft_len - ? images->ft_addr : EFI_FDT_USE_INTERNAL); - if (efi_ret != EFI_SUCCESS) { - printf("## Failed to install device tree: r = %lu\n", - efi_ret & ~EFI_ERROR_MASK); - return 1; - } + image_buf = map_sysmem(images->ep, images->os.image_len); /* Run EFI image */ printf("## Transferring control to EFI (at address %08lx) ...\n", images->ep); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - /* We expect to return */ - images->os.type = IH_TYPE_STANDALONE; - - image_buf = map_sysmem(images->ep, images->os.image_len); + ret = efi_binary_run(image_buf, images->os.image_len, + images->ft_len + ? images->ft_addr : EFI_FDT_USE_INTERNAL); - efi_ret = efi_run_image(image_buf, images->os.image_len); - if (efi_ret != EFI_SUCCESS) - return 1; - return 0; + return ret; } #endif diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index 9ba7734911e..00060f7d25a 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -160,7 +160,6 @@ static int efiload_read_file(struct bootflow *bflow, ulong addr) if (ret) return log_msg_ret("read", ret); bflow->buf = map_sysmem(addr, bflow->size); - bflow->flags |= BOOTFLOWF_STATIC_BUF; set_efi_bootdev(desc, bflow); @@ -313,6 +312,7 @@ static int distro_efi_try_bootflow_files(struct udevice *dev, */ } else { log_debug("No device tree available\n"); + bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT; } return 0; @@ -323,7 +323,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) char file_addr[17], fname[256]; char *tftp_argv[] = {"tftp", file_addr, fname, NULL}; struct cmd_tbl cmdtp = {}; /* dummy */ - const char *addr_str, *fdt_addr_str; + const char *addr_str, *fdt_addr_str, *bootfile_name; int ret, arch, size; ulong addr, fdt_addr; char str[36]; @@ -339,7 +339,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) ret = env_set("bootp_vci", str); if (ret) return log_msg_ret("vcs", ret); - ret = env_set_ulong("bootp_arch", arch); + ret = env_set_hex("bootp_arch", arch); if (ret) return log_msg_ret("ars", ret); @@ -360,6 +360,12 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) return log_msg_ret("sz", -EINVAL); bflow->size = size; + /* bootfile should be setup by dhcp*/ + bootfile_name = env_get("bootfile"); + if (!bootfile_name) + return log_msg_ret("bootfile_name", ret); + bflow->fname = strdup(bootfile_name); + /* do the hideous EFI hack */ efi_set_bootdev("Net", "", bflow->fname, map_sysmem(addr, 0), bflow->size); @@ -385,6 +391,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) bflow->fdt_addr = fdt_addr; } else { log_debug("No device tree available\n"); + bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT; } bflow->state = BOOTFLOWST_READY; @@ -396,6 +403,12 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow) { int ret; + /* + * bootmeth_efi doesn't allocate any buffer neither for blk nor net device + * set flag to avoid freeing static buffer. + */ + bflow->flags |= BOOTFLOWF_STATIC_BUF; + if (bootmeth_uses_network(bflow)) { /* we only support reading from one device, so ignore 'dev' */ ret = distro_efi_read_bootflow_net(bflow); @@ -413,7 +426,6 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow) static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) { ulong kernel, fdt; - char cmd[50]; int ret; kernel = env_get_hex("kernel_addr_r", 0); @@ -423,13 +435,11 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) return log_msg_ret("read", ret); /* - * use the provided device tree if available, else fall back to - * the control FDT + * use the provided device tree if not using the built-in fdt */ - if (bflow->fdt_fname) + if (bflow->flags & ~BOOTFLOWF_USE_BUILTIN_FDT) fdt = bflow->fdt_addr; - else - fdt = (ulong)map_to_sysmem(gd->fdt_blob); + } else { /* * This doesn't actually work for network devices: @@ -442,13 +452,17 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) fdt = env_get_hex("fdt_addr_r", 0); } - /* - * At some point we can add a real interface to bootefi so we can call - * this directly. For now, go through the CLI, like distro boot. - */ - snprintf(cmd, sizeof(cmd), "bootefi %lx %lx", kernel, fdt); - if (run_command(cmd, 0)) - return log_msg_ret("run", -EINVAL); + if (bflow->flags & BOOTFLOWF_USE_BUILTIN_FDT) { + log_debug("Booting with built-in fdt\n"); + if (efi_binary_run(map_sysmem(kernel, 0), 0, + EFI_FDT_USE_INTERNAL)) + return log_msg_ret("run", -EINVAL); + } else { + log_debug("Booting with external fdt\n"); + if (efi_binary_run(map_sysmem(kernel, 0), 0, + map_sysmem(fdt, 0))) + return log_msg_ret("run", -EINVAL); + } return 0; } diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c index e6c42d41fb8..ed29d7ef021 100644 --- a/boot/bootmeth_efi_mgr.c +++ b/boot/bootmeth_efi_mgr.c @@ -16,6 +16,7 @@ #include <dm.h> #include <efi_loader.h> #include <efi_variable.h> +#include <malloc.h> /** * struct efi_mgr_priv - private info for the efi-mgr driver @@ -65,6 +66,7 @@ static int efi_mgr_read_bootflow(struct udevice *dev, struct bootflow *bflow) bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid, &size); if (bootorder) { + free(bootorder); bflow->state = BOOTFLOWST_READY; return 0; } @@ -85,7 +87,7 @@ static int efi_mgr_boot(struct udevice *dev, struct bootflow *bflow) int ret; /* Booting is handled by the 'bootefi bootmgr' command */ - ret = run_command("bootefi bootmgr", 0); + ret = efi_bootmgr_run(EFI_FDT_USE_INTERNAL); return 0; } diff --git a/boot/fdt_support.c b/boot/fdt_support.c index b15d07765fe..090d82ee80a 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -667,7 +667,6 @@ int fdt_record_loadable(void *blob, u32 index, const char *name, return node; } -/* Resize the fdt to its actual size + a bit of padding */ int fdt_shrink_to_minimum(void *blob, uint extrasize) { int i; diff --git a/boot/image-board.c b/boot/image-board.c index d500da1b4b9..75f6906cd56 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -198,22 +198,7 @@ void memmove_wd(void *to, void *from, size_t len, ulong chunksz) } } -/** - * genimg_get_kernel_addr_fit - get the real kernel address and return 2 - * FIT strings - * @img_addr: a string might contain real image address - * @fit_uname_config: double pointer to a char, will hold pointer to a - * configuration unit name - * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage - * name - * - * genimg_get_kernel_addr_fit get the real kernel start address from a string - * which is normally the first argv of bootm/bootz - * - * returns: - * kernel start address - */ -ulong genimg_get_kernel_addr_fit(char * const img_addr, +ulong genimg_get_kernel_addr_fit(const char *const img_addr, const char **fit_uname_config, const char **fit_uname_kernel) { @@ -471,49 +456,14 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a return 0; } -/** - * boot_get_ramdisk - main ramdisk handling routine - * @argc: command argument count - * @argv: command argument list - * @images: pointer to the bootm images structure - * @arch: expected ramdisk architecture - * @rd_start: pointer to a ulong variable, will hold ramdisk start address - * @rd_end: pointer to a ulong variable, will hold ramdisk end - * - * boot_get_ramdisk() is responsible for finding a valid ramdisk image. - * Currently supported are the following ramdisk sources: - * - multicomponent kernel/ramdisk image, - * - commandline provided address of decicated ramdisk image. - * - * returns: - * 0, if ramdisk image was found and valid, or skiped - * rd_start and rd_end are set to ramdisk start/end addresses if - * ramdisk image is found and valid - * - * 1, if ramdisk image is found but corrupted, or invalid - * rd_start and rd_end are set to 0 if no ramdisk exists - */ -int boot_get_ramdisk(int argc, char *const argv[], struct bootm_headers *images, - u8 arch, ulong *rd_start, ulong *rd_end) +int boot_get_ramdisk(char const *select, struct bootm_headers *images, + uint arch, ulong *rd_start, ulong *rd_end) { ulong rd_data, rd_len; - const char *select = NULL; *rd_start = 0; *rd_end = 0; - if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { - char *buf; - - /* Look for an Android boot image */ - buf = map_sysmem(images->os.start, 0); - if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) - select = (argc == 0) ? env_get("loadaddr") : argv[0]; - } - - if (argc >= 2) - select = argv[1]; - /* * Look for a '-' which indicates to ignore the * ramdisk argument @@ -666,8 +616,7 @@ int boot_get_setup(struct bootm_headers *images, u8 arch, return boot_get_setup_fit(images, arch, setup_start, setup_len); } -int boot_get_fpga(int argc, char *const argv[], struct bootm_headers *images, - u8 arch, const ulong *ld_start, ulong * const ld_len) +int boot_get_fpga(struct bootm_headers *images) { ulong tmp_img_addr, img_data, img_len; void *buf; @@ -709,7 +658,7 @@ int boot_get_fpga(int argc, char *const argv[], struct bootm_headers *images, tmp_img_addr, (const char **)&uname, &images->fit_uname_cfg, - arch, + IH_ARCH_DEFAULT, IH_TYPE_FPGA, BOOTSTAGE_ID_FPGA_INIT, FIT_LOAD_OPTIONAL_NON_ZERO, @@ -769,8 +718,7 @@ static void fit_loadable_process(u8 img_type, fit_loadable_handler->handler(img_data, img_len); } -int boot_get_loadable(int argc, char *const argv[], struct bootm_headers *images, - u8 arch, const ulong *ld_start, ulong * const ld_len) +int boot_get_loadable(struct bootm_headers *images) { /* * These variables are used to hold the current image location @@ -816,7 +764,8 @@ int boot_get_loadable(int argc, char *const argv[], struct bootm_headers *images fit_img_result = fit_image_load(images, tmp_img_addr, &uname, &images->fit_uname_cfg, - arch, IH_TYPE_LOADABLE, + IH_ARCH_DEFAULT, + IH_TYPE_LOADABLE, BOOTSTAGE_ID_FIT_LOADABLE_START, FIT_LOAD_OPTIONAL_NON_ZERO, &img_data, &img_len); @@ -959,7 +908,7 @@ int image_setup_linux(struct bootm_headers *images) } if (CONFIG_IS_ENABLED(OF_LIBFDT) && of_size) { - ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb); + ret = image_setup_libfdt(images, *of_flat_tree, lmb); if (ret) return ret; } diff --git a/boot/image-fdt.c b/boot/image-fdt.c index f10200f6474..2b166c0ff94 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -24,9 +24,6 @@ #include <dm/ofnode.h> #include <tee/optee.h> -/* adding a ramdisk needs 0x44 bytes in version 2008.10 */ -#define FDT_RAMDISK_OVERHEAD 0x80 - DECLARE_GLOBAL_DATA_PTR; static void fdt_error(const char *msg) @@ -447,45 +444,16 @@ static int select_fdt(struct bootm_headers *images, const char *select, u8 arch, return 0; } -/** - * boot_get_fdt - main fdt handling routine - * @argc: command argument count - * @argv: command argument list - * @arch: architecture (IH_ARCH_...) - * @images: pointer to the bootm images structure - * @of_flat_tree: pointer to a char* variable, will hold fdt start address - * @of_size: pointer to a ulong variable, will hold fdt length - * - * boot_get_fdt() is responsible for finding a valid flat device tree image. - * Currently supported are the following ramdisk sources: - * - multicomponent kernel/ramdisk image, - * - commandline provided address of decicated ramdisk image. - * - * returns: - * 0, if fdt image was found and valid, or skipped - * of_flat_tree and of_size are set to fdt start address and length if - * fdt image is found and valid - * - * 1, if fdt image is found but corrupted - * of_flat_tree and of_size are set to 0 if no fdt exists - */ -int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, - struct bootm_headers *images, char **of_flat_tree, ulong *of_size) +int boot_get_fdt(void *buf, const char *select, uint arch, + struct bootm_headers *images, char **of_flat_tree, + ulong *of_size) { - ulong img_addr; - ulong fdt_addr; - char *fdt_blob = NULL; - void *buf; - const char *select = NULL; + char *fdt_blob = NULL; + ulong fdt_addr; *of_flat_tree = NULL; *of_size = 0; - img_addr = (argc == 0) ? image_load_addr : hextoul(argv[0], NULL); - buf = map_sysmem(img_addr, 0); - - if (argc > 2) - select = argv[2]; if (select || genimg_has_config(images)) { int ret; @@ -604,12 +572,13 @@ __weak int arch_fixup_fdt(void *blob) } int image_setup_libfdt(struct bootm_headers *images, void *blob, - int of_size, struct lmb *lmb) + struct lmb *lmb) { ulong *initrd_start = &images->initrd_start; ulong *initrd_end = &images->initrd_end; int ret = -EPERM; int fdt_ret; + int of_size; if (fdt_root(blob) < 0) { printf("ERROR: root node setup failed\n"); @@ -666,6 +635,14 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, goto err; } } + + if (fdt_initrd(blob, *initrd_start, *initrd_end)) + goto err; + + if (!ft_verify_fdt(blob)) + goto err; + + /* after here we are using a livetree */ if (!of_live_active() && CONFIG_IS_ENABLED(EVENT)) { struct event_ft_fixup fixup; @@ -683,25 +660,16 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, /* Delete the old LMB reservation */ if (lmb) - lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob, - (phys_size_t)fdt_totalsize(blob)); + lmb_free(lmb, map_to_sysmem(blob), fdt_totalsize(blob)); ret = fdt_shrink_to_minimum(blob, 0); if (ret < 0) goto err; of_size = ret; - if (*initrd_start && *initrd_end) { - of_size += FDT_RAMDISK_OVERHEAD; - fdt_set_totalsize(blob, of_size); - } /* Create a new LMB reservation */ if (lmb) - lmb_reserve(lmb, (ulong)blob, of_size); - - fdt_initrd(blob, *initrd_start, *initrd_end); - if (!ft_verify_fdt(blob)) - goto err; + lmb_reserve(lmb, map_to_sysmem(blob), of_size); #if defined(CONFIG_ARCH_KEYSTONE) if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) diff --git a/boot/image.c b/boot/image.c index 88b67bc3a19..675b5dd77f9 100644 --- a/boot/image.c +++ b/boot/image.c @@ -415,15 +415,20 @@ void image_print_contents(const void *ptr) * @type: OS type (IH_OS_...) * @comp_type: Compression type being used (IH_COMP_...) * @is_xip: true if the load address matches the image start + * @load: Load address for printing */ -static void print_decomp_msg(int comp_type, int type, bool is_xip) +static void print_decomp_msg(int comp_type, int type, bool is_xip, + ulong load) { const char *name = genimg_get_type_name(type); + /* Shows "Loading Kernel Image" for example */ if (comp_type == IH_COMP_NONE) - printf(" %s %s\n", is_xip ? "XIP" : "Loading", name); + printf(" %s %s", is_xip ? "XIP" : "Loading", name); else - printf(" Uncompressing %s\n", name); + printf(" Uncompressing %s", name); + + printf(" to %lx\n", load); } int image_decomp_type(const unsigned char *buf, ulong len) @@ -448,7 +453,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, int ret = -ENOSYS; *load_end = load; - print_decomp_msg(comp, type, load == image_start); + print_decomp_msg(comp, type, load == image_start, load); /* * Load the image to the right place, decompressing if needed. After diff --git a/boot/prog_boot.c b/boot/prog_boot.c new file mode 100644 index 00000000000..045554b93db --- /dev/null +++ b/boot/prog_boot.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY UCLASS_BOOTSTD + +#include <bootflow.h> +#include <bootstd.h> +#include <command.h> +#include <dm.h> + +/* + * show_bootmeths() - List available bootmeths + * + * We could refactor this to use do_bootmeth_list() if more detail (or ordering) + * are needed + */ +static void show_bootmeths(void) +{ + struct udevice *dev; + struct uclass *uc; + + printf("Bootmeths: "); + uclass_id_foreach_dev(UCLASS_BOOTMETH, dev, uc) + printf(" %s", dev->name); + printf("\n"); +} + +int bootstd_prog_boot(void) +{ + struct bootflow_iter iter; + struct bootflow bflow; + int ret, flags, i; + + printf("Programmatic boot starting\n"); + show_bootmeths(); + flags = BOOTFLOWIF_HUNT | BOOTFLOWIF_SHOW | BOOTFLOWIF_SKIP_GLOBAL; + + bootstd_clear_glob(); + for (i = 0, ret = bootflow_scan_first(NULL, NULL, &iter, flags, &bflow); + i < 1000 && ret != -ENODEV; + i++, ret = bootflow_scan_next(&iter, &bflow)) { + if (!bflow.err) + bootflow_run_boot(&iter, &bflow); + bootflow_free(&bflow); + } + + return -EFAULT; +} diff --git a/cmd/Kconfig b/cmd/Kconfig index df6d71c103f..24bfbe50572 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1,7 +1,5 @@ -menu "Command line interface" - -config CMDLINE - bool "Support U-Boot commands" +menuconfig CMDLINE + bool "Command line interface" default y help Enable U-Boot's command-line functions. This provides a means @@ -11,9 +9,10 @@ config CMDLINE Depending on the number of commands enabled, this can add substantially to the size of U-Boot. +if CMDLINE + config HUSH_PARSER bool "Use hush shell" - depends on CMDLINE help This option enables the "hush" shell (from Busybox) as command line interpreter, thus enabling powerful command line syntax like @@ -25,7 +24,6 @@ config HUSH_PARSER config CMDLINE_EDITING bool "Enable command line editing" - depends on CMDLINE default y help Enable editing and History functions for interactive command line @@ -40,15 +38,13 @@ config CMDLINE_PS_SUPPORT config AUTO_COMPLETE bool "Enable auto complete using TAB" - depends on CMDLINE default y help Enable auto completion of commands using TAB. config SYS_LONGHELP bool "Enable long help messages" - depends on CMDLINE - default y if CMDLINE + default y help Defined when you want long help messages included Do not set this option when short of memory. @@ -75,24 +71,9 @@ config SYS_MAXARGS int "Maximum number arguments accepted by commands" default 16 -config SYS_CBSIZE - int "Console input buffer size" - default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \ - RCAR_GEN3 || TARGET_SOCFPGA_SOC64 - default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \ - FSL_LSCH3 || X86 - default 256 if M68K || PPC - default 1024 - -config SYS_PBSIZE - int "Buffer size for console output" - default 1024 if ARCH_SUNXI - default 1044 - config SYS_XTRACE bool "Command execution tracer" - depends on CMDLINE - default y if CMDLINE + default y help This option enables the possiblity to print all commands before executing them and after all variables are evaluated (similar @@ -292,7 +273,7 @@ config CMD_BOOTMETH config BOOTM_EFI bool "Support booting UEFI FIT images" - depends on CMD_BOOTEFI && CMD_BOOTM && FIT + depends on BOOTEFI_BOOTMGR && CMD_BOOTM && FIT default y help Support booting UEFI FIT images via the bootm command. @@ -304,7 +285,7 @@ config CMD_BOOTZ config CMD_BOOTI bool "booti" - depends on ARM64 || RISCV + depends on ARM64 || RISCV || SANDBOX default y help Boot an AArch64 Linux Kernel image from memory. @@ -374,17 +355,6 @@ config BOOTM_VXWORKS help Support booting VxWorks images via the bootm command. -config SYS_BOOTM_LEN - hex "Maximum size of a decompresed OS image" - depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \ - LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT - default 0x4000000 if PPC || ARM64 - default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7 - default 0x800000 - help - This is the maximum size of the buffer that is used to decompress the OS - image in to, if passing a compressed image to bootm/booti/bootz. - config CMD_BOOTEFI bool "bootefi" depends on EFI_LOADER @@ -392,9 +362,27 @@ config CMD_BOOTEFI help Boot an EFI image from memory. +if CMD_BOOTEFI +config CMD_BOOTEFI_BINARY + bool "Allow booting an EFI binary directly" + depends on BOOTEFI_BOOTMGR + default y + help + Select this option to enable direct execution of binary at 'bootefi'. + This subcommand will allow you to load the UEFI binary using + other U-Boot commands or external methods and then run it. + +config CMD_BOOTEFI_BOOTMGR + bool "UEFI Boot Manager command" + depends on BOOTEFI_BOOTMGR + default y + help + Select this option to enable the 'bootmgr' subcommand of 'bootefi'. + This subcommand will allow you to select the UEFI binary to be booted + via UEFI variables Boot####, BootOrder, and BootNext. + config CMD_BOOTEFI_HELLO_COMPILE bool "Compile a standard EFI hello world binary for testing" - depends on CMD_BOOTEFI && !CPU_V7M default y help This compiles a standard EFI hello world application with U-Boot so @@ -416,6 +404,7 @@ config CMD_BOOTEFI_HELLO up EFI support on a new architecture. source lib/efi_selftest/Kconfig +endif config CMD_BOOTMENU bool "bootmenu" @@ -981,7 +970,6 @@ config CMD_ADC config CMD_BCB bool "bcb" - depends on MMC depends on PARTITIONS help Read/modify/write the fields of Bootloader Control Block, usually @@ -999,7 +987,7 @@ config CMD_BCB config CMD_BIND bool "bind/unbind - Bind or unbind a device to/from a driver" depends on DM - default y if USB_ETHER + imply CMD_DM help Bind or unbind a device to/from a driver from the command line. This is useful in situations where a device may be handled by several @@ -1152,13 +1140,6 @@ config CMD_GPT Enable the 'gpt' command to ready and write GPT style partition tables. -config RANDOM_UUID - bool "GPT Random UUID generation" - select LIB_UUID - help - Enable the generation of partitions with random UUIDs if none - are provided. - config CMD_GPT_RENAME bool "GPT partition renaming commands" depends on CMD_GPT @@ -1549,7 +1530,7 @@ config CMD_TSI148 Turndra tsi148 device. See the command help for full details. config CMD_UFS - bool "Enable UFS - Universal Flash Subsystem commands" + bool "ufs - Universal Flash Storage commands" depends on UFS help "This provides commands to initialise and configure universal flash @@ -1710,7 +1691,6 @@ if NET menuconfig CMD_NET bool "Network commands" default y - imply NETDEVICES if CMD_NET @@ -2142,7 +2122,7 @@ config CMD_EFIDEBUG config CMD_EFICONFIG bool "eficonfig - provide menu-driven uefi variables maintenance interface" default y if !HAS_BOARD_SIZE_LIMIT - depends on CMD_BOOTEFI_BOOTMGR + depends on BOOTEFI_BOOTMGR select MENU help Enable the 'eficonfig' command which provides the menu-driven UEFI @@ -2257,6 +2237,8 @@ config CMD_SYSBOOT config CMD_QFW bool "qfw" select QFW + default y if TARGET_QEMU_ARM_32BIT || TARGET_QEMU_ARM_64BIT || \ + TARGET_QEMU_X86 || TARGET_QEMU_X86_64 help This provides access to the QEMU firmware interface. The main feature is to allow easy loading of files passed to qemu-system @@ -2370,6 +2352,7 @@ config CMD_VIDCONSOLE config CMD_SELECT_FONT bool "select font size" depends on VIDEO + default y if CONSOLE_TRUETYPE help Enabling this will provide 'font' command. Allows font selection at runtime. @@ -2559,6 +2542,15 @@ config CMD_CROS_EC a number of sub-commands for performing EC tasks such as updating its flash, accessing a small saved context area and talking to the I2C bus behind the EC (if there is one). + +config CMD_SCMI + bool "Enable scmi command" + depends on SCMI_FIRMWARE + default n + help + This command provides user interfaces to several SCMI (System + Control and Management Interface) protocols available on Arm + platforms to manage system resources. endmenu menu "Filesystem commands" @@ -2902,4 +2894,5 @@ config CMD_MESON default y help Enable useful commands for the Meson Soc family developed by Amlogic Inc. -endmenu + +endif diff --git a/cmd/Makefile b/cmd/Makefile index 9a6790cc170..5ed0e4011d0 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -128,6 +128,7 @@ endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o obj-$(CONFIG_CMD_NET) += net.o +obj-$(CONFIG_ENV_SUPPORT) += nvedit.o obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o obj-$(CONFIG_CMD_ONENAND) += onenand.o obj-$(CONFIG_CMD_OSD) += osd.o @@ -159,6 +160,7 @@ obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_CMD_NVME) += nvme.o obj-$(CONFIG_SANDBOX) += sb.o obj-$(CONFIG_CMD_SF) += sf.o +obj-$(CONFIG_CMD_SCMI) += scmi.o obj-$(CONFIG_CMD_SCSI) += scsi.o disk.o obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o obj-$(CONFIG_CMD_SEAMA) += seama.o @@ -245,9 +247,6 @@ endif # !CONFIG_SPL_BUILD obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o -# core command -obj-y += nvedit.o - obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/ filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";") diff --git a/cmd/acpi.c b/cmd/acpi.c index 7e397d1a74e..0c144092420 100644 --- a/cmd/acpi.c +++ b/cmd/acpi.c @@ -17,7 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; /** * dump_hdr() - Dump an ACPI header * - * If the header is for FACS then it shows the revision information as well + * Except for the Firmware ACPI Control Structure (FACS) + * additionally show the revision information. * * @hdr: ACPI header to dump */ @@ -25,7 +26,7 @@ static void dump_hdr(struct acpi_table_header *hdr) { bool has_hdr = memcmp(hdr->signature, "FACS", ACPI_NAME_LEN); - printf("%.*s %08lx %5x", ACPI_NAME_LEN, hdr->signature, + printf("%.*s %16lx %5x", ACPI_NAME_LEN, hdr->signature, (ulong)map_to_sysmem(hdr), hdr->length); if (has_hdr) { printf(" v%02d %.6s %.8s %x %.4s %x\n", hdr->revision, @@ -43,7 +44,7 @@ static int dump_table_name(const char *sig) hdr = acpi_find_table(sig); if (!hdr) return -ENOENT; - printf("%.*s @ %08lx\n", ACPI_NAME_LEN, hdr->signature, + printf("%.*s @ %16lx\n", ACPI_NAME_LEN, hdr->signature, (ulong)map_to_sysmem(hdr)); print_buffer(0, hdr, 1, hdr->length, 0); @@ -58,47 +59,50 @@ static void list_fadt(struct acpi_fadt *fadt) dump_hdr(map_sysmem(fadt->firmware_ctrl, 0)); } -static int list_rsdt(struct acpi_rsdt *rsdt, struct acpi_xsdt *xsdt) +static void list_rsdt(struct acpi_rsdp *rsdp) { int len, i, count; + struct acpi_rsdt *rsdt; + struct acpi_xsdt *xsdt; - dump_hdr(&rsdt->header); - if (xsdt) + if (rsdp->rsdt_address) { + rsdt = map_sysmem(rsdp->rsdt_address, 0); + dump_hdr(&rsdt->header); + } + if (rsdp->xsdt_address) { + xsdt = map_sysmem(rsdp->xsdt_address, 0); dump_hdr(&xsdt->header); - len = rsdt->header.length - sizeof(rsdt->header); - count = len / sizeof(u32); + len = xsdt->header.length - sizeof(xsdt->header); + count = len / sizeof(u64); + } else if (rsdp->rsdt_address) { + len = rsdt->header.length - sizeof(rsdt->header); + count = len / sizeof(u32); + } else { + return; + } + for (i = 0; i < count; i++) { struct acpi_table_header *hdr; + u64 entry; - if (!rsdt->entry[i]) + if (rsdp->xsdt_address) + entry = xsdt->entry[i]; + else + entry = rsdt->entry[i]; + if (!entry) break; - hdr = map_sysmem(rsdt->entry[i], 0); + hdr = map_sysmem(entry, 0); dump_hdr(hdr); if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) list_fadt((struct acpi_fadt *)hdr); - if (xsdt) { - if (xsdt->entry[i] != rsdt->entry[i]) { - printf(" (xsdt mismatch %llx)\n", - xsdt->entry[i]); - } - } } - - return 0; } -static int list_rsdp(struct acpi_rsdp *rsdp) +static void list_rsdp(struct acpi_rsdp *rsdp) { - struct acpi_rsdt *rsdt; - struct acpi_xsdt *xsdt; - - printf("RSDP %08lx %5x v%02d %.6s\n", (ulong)map_to_sysmem(rsdp), + printf("RSDP %16lx %5x v%02d %.6s\n", (ulong)map_to_sysmem(rsdp), rsdp->length, rsdp->revision, rsdp->oem_id); - rsdt = map_sysmem(rsdp->rsdt_address, 0); - xsdt = map_sysmem(rsdp->xsdt_address, 0); - list_rsdt(rsdt, xsdt); - - return 0; + list_rsdt(rsdp); } static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc, @@ -111,8 +115,8 @@ static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc, printf("No ACPI tables present\n"); return 0; } - printf("Name Base Size Detail\n"); - printf("---- -------- ----- ------\n"); + printf("Name Base Size Detail\n" + "---- ---------------- ----- ----------------------------\n"); list_rsdp(rsdp); return 0; @@ -156,6 +160,9 @@ static int do_acpi_dump(struct cmd_tbl *cmdtp, int flag, int argc, char sig[ACPI_NAME_LEN]; int ret; + if (argc < 2) + return CMD_RET_USAGE; + name = argv[1]; if (strlen(name) != ACPI_NAME_LEN) { printf("Table name '%s' must be four characters\n", name); diff --git a/cmd/bcb.c b/cmd/bcb.c index 02d0c70d87e..f3b92564d10 100644 --- a/cmd/bcb.c +++ b/cmd/bcb.c @@ -25,9 +25,18 @@ enum bcb_cmd { BCB_CMD_STORE, }; -static int bcb_dev = -1; -static int bcb_part = -1; +static const char * const fields[] = { + "command", + "status", + "recovery", + "stage" +}; + static struct bootloader_message bcb __aligned(ARCH_DMA_MINALIGN) = { { 0 } }; +static struct disk_partition partition_data; + +static struct blk_desc *block; +static struct disk_partition *partition = &partition_data; static int bcb_cmd_get(char *cmd) { @@ -53,6 +62,9 @@ static int bcb_is_misused(int argc, char *const argv[]) switch (cmd) { case BCB_CMD_LOAD: + if (argc != 3 && argc != 4) + goto err; + break; case BCB_CMD_FIELD_SET: if (argc != 3) goto err; @@ -78,7 +90,7 @@ static int bcb_is_misused(int argc, char *const argv[]) return -1; } - if (cmd != BCB_CMD_LOAD && (bcb_dev < 0 || bcb_part < 0)) { + if (cmd != BCB_CMD_LOAD && !block) { printf("Error: Please, load BCB first!\n"); return -1; } @@ -90,7 +102,7 @@ err: return -1; } -static int bcb_field_get(char *name, char **fieldp, int *sizep) +static int bcb_field_get(const char *name, char **fieldp, int *sizep) { if (!strcmp(name, "command")) { *fieldp = bcb.command; @@ -115,25 +127,30 @@ static int bcb_field_get(char *name, char **fieldp, int *sizep) return 0; } -static int __bcb_load(int devnum, const char *partp) +static void __bcb_reset(void) +{ + block = NULL; + partition = &partition_data; + memset(&partition_data, 0, sizeof(struct disk_partition)); + memset(&bcb, 0, sizeof(struct bootloader_message)); +} + +static int __bcb_initialize(const char *iface, int devnum, const char *partp) { - struct blk_desc *desc; - struct disk_partition info; - u64 cnt; char *endp; int part, ret; - desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, devnum); - if (!desc) { + block = blk_get_dev(iface, devnum); + if (!block) { ret = -ENODEV; goto err_read_fail; } /* - * always select the USER mmc hwpart in case another + * always select the first hwpart in case another * blk operation selected a different hwpart */ - ret = blk_dselect_hwpart(desc, 0); + ret = blk_dselect_hwpart(block, 0); if (IS_ERR_VALUE(ret)) { ret = -ENODEV; goto err_read_fail; @@ -141,59 +158,84 @@ static int __bcb_load(int devnum, const char *partp) part = simple_strtoul(partp, &endp, 0); if (*endp == '\0') { - ret = part_get_info(desc, part, &info); + ret = part_get_info(block, part, partition); if (ret) goto err_read_fail; } else { - part = part_get_info_by_name(desc, partp, &info); + part = part_get_info_by_name(block, partp, partition); if (part < 0) { ret = part; goto err_read_fail; } } - cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz); - if (cnt > info.size) + return CMD_RET_SUCCESS; + +err_read_fail: + printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id, + block->devnum, partition->name, ret); + __bcb_reset(); + return CMD_RET_FAILURE; +} + +static int __bcb_load(void) +{ + u64 cnt; + int ret; + + cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), partition->blksz); + if (cnt > partition->size) goto err_too_small; - if (blk_dread(desc, info.start, cnt, &bcb) != cnt) { + if (blk_dread(block, partition->start, cnt, &bcb) != cnt) { ret = -EIO; goto err_read_fail; } - bcb_dev = desc->devnum; - bcb_part = part; - debug("%s: Loaded from mmc %d:%d\n", __func__, bcb_dev, bcb_part); + debug("%s: Loaded from %d %d:%s\n", __func__, block->uclass_id, + block->devnum, partition->name); return CMD_RET_SUCCESS; err_read_fail: - printf("Error: mmc %d:%s read failed (%d)\n", devnum, partp, ret); + printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id, + block->devnum, partition->name, ret); goto err; err_too_small: - printf("Error: mmc %d:%s too small!", devnum, partp); - goto err; + printf("Error: %d %d:%s too small!", block->uclass_id, + block->devnum, partition->name); err: - bcb_dev = -1; - bcb_part = -1; - + __bcb_reset(); return CMD_RET_FAILURE; } static int do_bcb_load(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { + int ret; + int devnum; char *endp; - int devnum = simple_strtoul(argv[1], &endp, 0); + char *iface = "mmc"; + + if (argc == 4) { + iface = argv[1]; + argc--; + argv++; + } + devnum = simple_strtoul(argv[1], &endp, 0); if (*endp != '\0') { printf("Error: Device id '%s' not a number\n", argv[1]); return CMD_RET_FAILURE; } - return __bcb_load(devnum, argv[2]); + ret = __bcb_initialize(iface, devnum, argv[2]); + if (ret != CMD_RET_SUCCESS) + return ret; + + return __bcb_load(); } -static int __bcb_set(char *fieldp, const char *valp) +static int __bcb_set(const char *fieldp, const char *valp) { int size, len; char *field, *str, *found, *tmp; @@ -293,31 +335,20 @@ static int do_bcb_dump(struct cmd_tbl *cmdtp, int flag, int argc, static int __bcb_store(void) { - struct blk_desc *desc; - struct disk_partition info; u64 cnt; int ret; - desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, bcb_dev); - if (!desc) { - ret = -ENODEV; - goto err; - } - - ret = part_get_info(desc, bcb_part, &info); - if (ret) - goto err; + cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), partition->blksz); - cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz); - - if (blk_dwrite(desc, info.start, cnt, &bcb) != cnt) { + if (blk_dwrite(block, partition->start, cnt, &bcb) != cnt) { ret = -EIO; goto err; } return CMD_RET_SUCCESS; err: - printf("Error: mmc %d:%d write failed (%d)\n", bcb_dev, bcb_part, ret); + printf("Error: %d %d:%s write failed (%d)\n", block->uclass_id, + block->devnum, partition->name, ret); return CMD_RET_FAILURE; } @@ -328,23 +359,59 @@ static int do_bcb_store(struct cmd_tbl *cmdtp, int flag, int argc, return __bcb_store(); } -int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp) +int bcb_find_partition_and_load(const char *iface, int devnum, char *partp) { int ret; - ret = __bcb_load(devnum, partp); - if (ret != CMD_RET_SUCCESS) - return ret; + __bcb_reset(); - ret = __bcb_set("command", reasonp); + ret = __bcb_initialize(iface, devnum, partp); if (ret != CMD_RET_SUCCESS) return ret; - ret = __bcb_store(); - if (ret != CMD_RET_SUCCESS) - return ret; + return __bcb_load(); +} - return 0; +int bcb_load(struct blk_desc *block_description, struct disk_partition *disk_partition) +{ + __bcb_reset(); + + block = block_description; + partition = disk_partition; + + return __bcb_load(); +} + +int bcb_set(enum bcb_field field, const char *value) +{ + if (field > BCB_FIELD_STAGE) + return CMD_RET_FAILURE; + return __bcb_set(fields[field], value); +} + +int bcb_get(enum bcb_field field, char *value_out, size_t value_size) +{ + int size; + char *field_value; + + if (field > BCB_FIELD_STAGE) + return CMD_RET_FAILURE; + if (bcb_field_get(fields[field], &field_value, &size)) + return CMD_RET_FAILURE; + + strlcpy(value_out, field_value, value_size); + + return CMD_RET_SUCCESS; +} + +int bcb_store(void) +{ + return __bcb_store(); +} + +void bcb_reset(void) +{ + __bcb_reset(); } static struct cmd_tbl cmd_bcb_sub[] = { @@ -385,21 +452,23 @@ static int do_bcb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) U_BOOT_CMD( bcb, CONFIG_SYS_MAXARGS, 1, do_bcb, "Load/set/clear/test/dump/store Android BCB fields", - "load <dev> <part> - load BCB from mmc <dev>:<part>\n" - "bcb set <field> <val> - set BCB <field> to <val>\n" - "bcb clear [<field>] - clear BCB <field> or all fields\n" - "bcb test <field> <op> <val> - test BCB <field> against <val>\n" - "bcb dump <field> - dump BCB <field>\n" - "bcb store - store BCB back to mmc\n" + "load <interface> <dev> <part> - load BCB from <interface> <dev>:<part>\n" + "load <dev> <part> - load BCB from mmc <dev>:<part>\n" + "bcb set <field> <val> - set BCB <field> to <val>\n" + "bcb clear [<field>] - clear BCB <field> or all fields\n" + "bcb test <field> <op> <val> - test BCB <field> against <val>\n" + "bcb dump <field> - dump BCB <field>\n" + "bcb store - store BCB back to <interface>\n" "\n" "Legend:\n" - "<dev> - MMC device index containing the BCB partition\n" - "<part> - MMC partition index or name containing the BCB\n" - "<field> - one of {command,status,recovery,stage,reserved}\n" - "<op> - the binary operator used in 'bcb test':\n" - " '=' returns true if <val> matches the string stored in <field>\n" - " '~' returns true if <val> matches a subset of <field>'s string\n" - "<val> - string/text provided as input to bcb {set,test}\n" - " NOTE: any ':' character in <val> will be replaced by line feed\n" - " during 'bcb set' and used as separator by upper layers\n" + "<interface> - storage device interface (virtio, mmc, etc)\n" + "<dev> - storage device index containing the BCB partition\n" + "<part> - partition index or name containing the BCB\n" + "<field> - one of {command,status,recovery,stage,reserved}\n" + "<op> - the binary operator used in 'bcb test':\n" + " '=' returns true if <val> matches the string stored in <field>\n" + " '~' returns true if <val> matches a subset of <field>'s string\n" + "<val> - string/text provided as input to bcb {set,test}\n" + " NOTE: any ':' character in <val> will be replaced by line feed\n" + " during 'bcb set' and used as separator by upper layers\n" ); diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 1fe13ca13a0..79106caeec2 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -10,6 +10,7 @@ #include <command.h> #include <dm.h> #include <env.h> +#include <getopt.h> #include <lmb.h> #include <mapmem.h> #include <net.h> @@ -133,10 +134,8 @@ static void print_serial(struct udevice *dev) bdinfo_print_num_l(" clock", info.clock); } -int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +static int bdinfo_print_all(struct bd_info *bd) { - struct bd_info *bd = gd->bd; - #ifdef DEBUG bdinfo_print_num_l("bd address", (ulong)bd); #endif @@ -184,8 +183,38 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return 0; } +int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct bd_info *bd = gd->bd; + struct getopt_state gs; + int opt; + + if (!CONFIG_IS_ENABLED(GETOPT) || argc == 1) + return bdinfo_print_all(bd); + + getopt_init_state(&gs); + while ((opt = getopt(&gs, argc, argv, "aem")) > 0) { + switch (opt) { + case 'a': + return bdinfo_print_all(bd); + case 'e': + if (!IS_ENABLED(CONFIG_CMD_NET)) + return CMD_RET_USAGE; + print_eth(); + return CMD_RET_SUCCESS; + case 'm': + print_bi_dram(bd); + return CMD_RET_SUCCESS; + default: + return CMD_RET_USAGE; + } + } + + return CMD_RET_USAGE; +} + U_BOOT_CMD( - bdinfo, 1, 1, do_bdinfo, + bdinfo, 2, 1, do_bdinfo, "print Board Info structure", "" ); diff --git a/cmd/bind.c b/cmd/bind.c index 4d1b7885e60..be0d4d2a711 100644 --- a/cmd/bind.c +++ b/cmd/bind.c @@ -246,6 +246,8 @@ U_BOOT_CMD( "Bind a device to a driver", "<node path> <driver>\n" "bind <class> <index> <driver>\n" + "Use 'dm tree' to list all devices registered in the driver model,\n" + "their path, class, index and current driver.\n" ); U_BOOT_CMD( @@ -254,4 +256,6 @@ U_BOOT_CMD( "<node path>\n" "unbind <class> <index>\n" "unbind <class> <index> <driver>\n" + "Use 'dm tree' to list all devices registered in the driver model,\n" + "their path, class, index and current driver.\n" ); diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 20e5c94a33a..9cf9027bf40 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -7,543 +7,23 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> -#include <bootm.h> -#include <charset.h> #include <command.h> -#include <dm.h> +#include <efi.h> #include <efi_loader.h> -#include <efi_selftest.h> -#include <env.h> -#include <errno.h> -#include <image.h> +#include <exports.h> #include <log.h> #include <malloc.h> -#include <asm/global_data.h> -#include <linux/libfdt.h> -#include <linux/libfdt_env.h> #include <mapmem.h> -#include <memalign.h> +#include <vsprintf.h> #include <asm-generic/sections.h> -#include <linux/linkage.h> +#include <asm/global_data.h> +#include <linux/string.h> DECLARE_GLOBAL_DATA_PTR; -static struct efi_device_path *bootefi_image_path; -static struct efi_device_path *bootefi_device_path; -static void *image_addr; -static size_t image_size; - -/** - * efi_get_image_parameters() - return image parameters - * - * @img_addr: address of loaded image in memory - * @img_size: size of loaded image - */ -void efi_get_image_parameters(void **img_addr, size_t *img_size) -{ - *img_addr = image_addr; - *img_size = image_size; -} - -/** - * efi_clear_bootdev() - clear boot device - */ -static void efi_clear_bootdev(void) -{ - efi_free_pool(bootefi_device_path); - efi_free_pool(bootefi_image_path); - bootefi_device_path = NULL; - bootefi_image_path = NULL; - image_addr = NULL; - image_size = 0; -} - -/** - * efi_set_bootdev() - set boot device - * - * This function is called when a file is loaded, e.g. via the 'load' command. - * We use the path to this file to inform the UEFI binary about the boot device. - * - * @dev: device, e.g. "MMC" - * @devnr: number of the device, e.g. "1:2" - * @path: path to file loaded - * @buffer: buffer with file loaded - * @buffer_size: size of file loaded - */ -void efi_set_bootdev(const char *dev, const char *devnr, const char *path, - void *buffer, size_t buffer_size) -{ - struct efi_device_path *device, *image; - efi_status_t ret; - - log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev, - devnr, path, buffer, buffer_size); - - /* Forget overwritten image */ - if (buffer + buffer_size >= image_addr && - image_addr + image_size >= buffer) - efi_clear_bootdev(); - - /* Remember only PE-COFF and FIT images */ - if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) { - if (IS_ENABLED(CONFIG_FIT) && - !fit_check_format(buffer, IMAGE_SIZE_INVAL)) { - /* - * FIT images of type EFI_OS are started via command - * bootm. We should not use their boot device with the - * bootefi command. - */ - buffer = 0; - buffer_size = 0; - } else { - log_debug("- not remembering image\n"); - return; - } - } - - /* efi_set_bootdev() is typically called repeatedly, recover memory */ - efi_clear_bootdev(); - - image_addr = buffer; - image_size = buffer_size; - - ret = efi_dp_from_name(dev, devnr, path, &device, &image); - if (ret == EFI_SUCCESS) { - bootefi_device_path = device; - if (image) { - /* FIXME: image should not contain device */ - struct efi_device_path *image_tmp = image; - - efi_dp_split_file_path(image, &device, &image); - efi_free_pool(image_tmp); - } - bootefi_image_path = image; - log_debug("- boot device %pD\n", device); - if (image) - log_debug("- image %pD\n", image); - } else { - log_debug("- efi_dp_from_name() failed, err=%lx\n", ret); - efi_clear_bootdev(); - } -} - -/** - * efi_env_set_load_options() - set load options from environment variable - * - * @handle: the image handle - * @env_var: name of the environment variable - * @load_options: pointer to load options (output) - * Return: status code - */ -static efi_status_t efi_env_set_load_options(efi_handle_t handle, - const char *env_var, - u16 **load_options) -{ - const char *env = env_get(env_var); - size_t size; - u16 *pos; - efi_status_t ret; - - *load_options = NULL; - if (!env) - return EFI_SUCCESS; - size = sizeof(u16) * (utf8_utf16_strlen(env) + 1); - pos = calloc(size, 1); - if (!pos) - return EFI_OUT_OF_RESOURCES; - *load_options = pos; - utf8_utf16_strcpy(&pos, env); - ret = efi_set_load_options(handle, size, *load_options); - if (ret != EFI_SUCCESS) { - free(*load_options); - *load_options = NULL; - } - return ret; -} - -#if !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) - -/** - * copy_fdt() - Copy the device tree to a new location available to EFI - * - * The FDT is copied to a suitable location within the EFI memory map. - * Additional 12 KiB are added to the space in case the device tree needs to be - * expanded later with fdt_open_into(). - * - * @fdtp: On entry a pointer to the flattened device tree. - * On exit a pointer to the copy of the flattened device tree. - * FDT start - * Return: status code - */ -static efi_status_t copy_fdt(void **fdtp) -{ - unsigned long fdt_ram_start = -1L, fdt_pages; - efi_status_t ret = 0; - void *fdt, *new_fdt; - u64 new_fdt_addr; - uint fdt_size; - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - u64 ram_start = gd->bd->bi_dram[i].start; - u64 ram_size = gd->bd->bi_dram[i].size; - - if (!ram_size) - continue; - - if (ram_start < fdt_ram_start) - fdt_ram_start = ram_start; - } - - /* - * Give us at least 12 KiB of breathing room in case the device tree - * needs to be expanded later. - */ - fdt = *fdtp; - fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000); - fdt_size = fdt_pages << EFI_PAGE_SHIFT; - - ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, - EFI_ACPI_RECLAIM_MEMORY, fdt_pages, - &new_fdt_addr); - if (ret != EFI_SUCCESS) { - log_err("ERROR: Failed to reserve space for FDT\n"); - goto done; - } - new_fdt = (void *)(uintptr_t)new_fdt_addr; - memcpy(new_fdt, fdt, fdt_totalsize(fdt)); - fdt_set_totalsize(new_fdt, fdt_size); - - *fdtp = (void *)(uintptr_t)new_fdt_addr; -done: - return ret; -} - -/** - * get_config_table() - get configuration table - * - * @guid: GUID of the configuration table - * Return: pointer to configuration table or NULL - */ -static void *get_config_table(const efi_guid_t *guid) -{ - size_t i; - - for (i = 0; i < systab.nr_tables; i++) { - if (!guidcmp(guid, &systab.tables[i].guid)) - return systab.tables[i].table; - } - return NULL; -} - -#endif /* !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) */ - -/** - * efi_install_fdt() - install device tree - * - * If fdt is not EFI_FDT_USE_INTERNAL, the device tree located at that memory - * address will will be installed as configuration table, otherwise the device - * tree located at the address indicated by environment variable fdt_addr or as - * fallback fdtcontroladdr will be used. - * - * On architectures using ACPI tables device trees shall not be installed as - * configuration table. - * - * @fdt: address of device tree or EFI_FDT_USE_INTERNAL to use the - * the hardware device tree as indicated by environment variable - * fdt_addr or as fallback the internal device tree as indicated by - * the environment variable fdtcontroladdr - * Return: status code - */ -efi_status_t efi_install_fdt(void *fdt) -{ - /* - * The EBBR spec requires that we have either an FDT or an ACPI table - * but not both. - */ -#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) - if (fdt) { - log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n"); - return EFI_SUCCESS; - } -#else - struct bootm_headers img = { 0 }; - efi_status_t ret; - - if (fdt == EFI_FDT_USE_INTERNAL) { - const char *fdt_opt; - uintptr_t fdt_addr; - - /* Look for device tree that is already installed */ - if (get_config_table(&efi_guid_fdt)) - return EFI_SUCCESS; - /* Check if there is a hardware device tree */ - fdt_opt = env_get("fdt_addr"); - /* Use our own device tree as fallback */ - if (!fdt_opt) { - fdt_opt = env_get("fdtcontroladdr"); - if (!fdt_opt) { - log_err("ERROR: need device tree\n"); - return EFI_NOT_FOUND; - } - } - fdt_addr = hextoul(fdt_opt, NULL); - if (!fdt_addr) { - log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n"); - return EFI_LOAD_ERROR; - } - fdt = map_sysmem(fdt_addr, 0); - } - - /* Install device tree */ - if (fdt_check_header(fdt)) { - log_err("ERROR: invalid device tree\n"); - return EFI_LOAD_ERROR; - } - - /* Prepare device tree for payload */ - ret = copy_fdt(&fdt); - if (ret) { - log_err("ERROR: out of memory\n"); - return EFI_OUT_OF_RESOURCES; - } - - if (image_setup_libfdt(&img, fdt, 0, NULL)) { - log_err("ERROR: failed to process device tree\n"); - return EFI_LOAD_ERROR; - } - - /* Create memory reservations as indicated by the device tree */ - efi_carve_out_dt_rsv(fdt); - - efi_try_purge_kaslr_seed(fdt); - - if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) { - ret = efi_tcg2_measure_dtb(fdt); - if (ret == EFI_SECURITY_VIOLATION) { - log_err("ERROR: failed to measure DTB\n"); - return ret; - } - } - - /* Install device tree as UEFI table */ - ret = efi_install_configuration_table(&efi_guid_fdt, fdt); - if (ret != EFI_SUCCESS) { - log_err("ERROR: failed to install device tree\n"); - return ret; - } -#endif /* GENERATE_ACPI_TABLE */ - - return EFI_SUCCESS; -} - -/** - * do_bootefi_exec() - execute EFI binary - * - * The image indicated by @handle is started. When it returns the allocated - * memory for the @load_options is freed. - * - * @handle: handle of loaded image - * @load_options: load options - * Return: status code - * - * Load the EFI binary into a newly assigned memory unwinding the relocation - * information, install the loaded image protocol, and call the binary. - */ -static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options) -{ - efi_status_t ret; - efi_uintn_t exit_data_size = 0; - u16 *exit_data = NULL; - - /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */ - switch_to_non_secure_mode(); - - /* - * The UEFI standard requires that the watchdog timer is set to five - * minutes when invoking an EFI boot option. - * - * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A - * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer - */ - ret = efi_set_watchdog(300); - if (ret != EFI_SUCCESS) { - log_err("ERROR: Failed to set watchdog timer\n"); - goto out; - } - - /* Call our payload! */ - ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data)); - if (ret != EFI_SUCCESS) { - log_err("## Application failed, r = %lu\n", - ret & ~EFI_ERROR_MASK); - if (exit_data) { - log_err("## %ls\n", exit_data); - efi_free_pool(exit_data); - } - } - - efi_restore_gd(); - -out: - free(load_options); - - if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) { - if (efi_initrd_deregister() != EFI_SUCCESS) - log_err("Failed to remove loadfile2 for initrd\n"); - } - - /* Control is returned to U-Boot, disable EFI watchdog */ - efi_set_watchdog(0); +static struct efi_device_path *test_image_path; +static struct efi_device_path *test_device_path; - return ret; -} - -/** - * do_efibootmgr() - execute EFI boot manager - * - * Return: status code - */ -static int do_efibootmgr(void) -{ - efi_handle_t handle; - efi_status_t ret; - void *load_options; - - ret = efi_bootmgr_load(&handle, &load_options); - if (ret != EFI_SUCCESS) { - log_notice("EFI boot manager: Cannot load any image\n"); - return CMD_RET_FAILURE; - } - - ret = do_bootefi_exec(handle, load_options); - - if (ret != EFI_SUCCESS) - return CMD_RET_FAILURE; - - return CMD_RET_SUCCESS; -} - -/** - * do_bootefi_image() - execute EFI binary - * - * Set up memory image for the binary to be loaded, prepare device path, and - * then call do_bootefi_exec() to execute it. - * - * @image_opt: string with image start address - * @size_opt: string with image size or NULL - * Return: status code - */ -static int do_bootefi_image(const char *image_opt, const char *size_opt) -{ - void *image_buf; - unsigned long addr, size; - efi_status_t ret; - -#ifdef CONFIG_CMD_BOOTEFI_HELLO - if (!strcmp(image_opt, "hello")) { - image_buf = __efi_helloworld_begin; - size = __efi_helloworld_end - __efi_helloworld_begin; - efi_clear_bootdev(); - } else -#endif - { - addr = strtoul(image_opt, NULL, 16); - /* Check that a numeric value was passed */ - if (!addr) - return CMD_RET_USAGE; - image_buf = map_sysmem(addr, 0); - - if (size_opt) { - size = strtoul(size_opt, NULL, 16); - if (!size) - return CMD_RET_USAGE; - efi_clear_bootdev(); - } else { - if (image_buf != image_addr) { - log_err("No UEFI binary known at %s\n", - image_opt); - return CMD_RET_FAILURE; - } - size = image_size; - } - } - ret = efi_run_image(image_buf, size); - - if (ret != EFI_SUCCESS) - return CMD_RET_FAILURE; - - return CMD_RET_SUCCESS; -} - -/** - * efi_run_image() - run loaded UEFI image - * - * @source_buffer: memory address of the UEFI image - * @source_size: size of the UEFI image - * Return: status code - */ -efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) -{ - efi_handle_t mem_handle = NULL, handle; - struct efi_device_path *file_path = NULL; - struct efi_device_path *msg_path; - efi_status_t ret, ret2; - u16 *load_options; - - if (!bootefi_device_path || !bootefi_image_path) { - log_debug("Not loaded from disk\n"); - /* - * Special case for efi payload not loaded from disk, - * such as 'bootefi hello' or for example payload - * loaded directly into memory via JTAG, etc: - */ - file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, - (uintptr_t)source_buffer, - source_size); - /* - * Make sure that device for device_path exist - * in load_image(). Otherwise, shell and grub will fail. - */ - ret = efi_install_multiple_protocol_interfaces(&mem_handle, - &efi_guid_device_path, - file_path, NULL); - if (ret != EFI_SUCCESS) - goto out; - msg_path = file_path; - } else { - file_path = efi_dp_append(bootefi_device_path, - bootefi_image_path); - msg_path = bootefi_image_path; - log_debug("Loaded from disk\n"); - } - - log_info("Booting %pD\n", msg_path); - - ret = EFI_CALL(efi_load_image(false, efi_root, file_path, source_buffer, - source_size, &handle)); - if (ret != EFI_SUCCESS) { - log_err("Loading image failed\n"); - goto out; - } - - /* Transfer environment variable as load options */ - ret = efi_env_set_load_options(handle, "bootargs", &load_options); - if (ret != EFI_SUCCESS) - goto out; - - ret = do_bootefi_exec(handle, load_options); - -out: - ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle, - &efi_guid_device_path, - file_path, NULL); - efi_free_pool(file_path); - return (ret != EFI_SUCCESS) ? ret : ret2; -} - -#ifdef CONFIG_CMD_BOOTEFI_SELFTEST static efi_status_t bootefi_run_prepare(const char *load_options_path, struct efi_device_path *device_path, struct efi_device_path *image_path, @@ -585,23 +65,26 @@ static efi_status_t bootefi_test_prepare efi_status_t ret; /* Construct a dummy device path */ - bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, 0, 0); - if (!bootefi_device_path) + test_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, 0, 0); + if (!test_device_path) return EFI_OUT_OF_RESOURCES; - bootefi_image_path = efi_dp_from_file(NULL, path); - if (!bootefi_image_path) { + test_image_path = efi_dp_from_file(NULL, path); + if (!test_image_path) { ret = EFI_OUT_OF_RESOURCES; goto failure; } - ret = bootefi_run_prepare(load_options_path, bootefi_device_path, - bootefi_image_path, image_objp, + ret = bootefi_run_prepare(load_options_path, test_device_path, + test_image_path, image_objp, loaded_image_infop); if (ret == EFI_SUCCESS) return ret; failure: + efi_free_pool(test_device_path); + efi_free_pool(test_image_path); + /* TODO: not sure calling clear function is necessary */ efi_clear_bootdev(); return ret; } @@ -626,6 +109,8 @@ static int do_efi_selftest(void) ret = EFI_CALL(efi_selftest(&image_obj->header, &systab)); efi_restore_gd(); free(loaded_image_info->load_options); + efi_free_pool(test_device_path); + efi_free_pool(test_image_path); if (ret != EFI_SUCCESS) efi_delete_handle(&image_obj->header); else @@ -633,7 +118,6 @@ static int do_efi_selftest(void) return ret != EFI_SUCCESS; } -#endif /* CONFIG_CMD_BOOTEFI_SELFTEST */ /** * do_bootefi() - execute `bootefi` command @@ -648,20 +132,15 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { efi_status_t ret; - char *img_addr, *img_size, *str_copy, *pos; - void *fdt; + char *p; + void *fdt, *image_buf; + unsigned long addr, size; + void *image_addr; + size_t image_size; if (argc < 2) return CMD_RET_USAGE; - /* Initialize EFI drivers */ - ret = efi_init_obj_list(); - if (ret != EFI_SUCCESS) { - log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n", - ret & ~EFI_ERROR_MASK); - return CMD_RET_FAILURE; - } - if (argc > 2) { uintptr_t fdt_addr; @@ -670,32 +149,81 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, } else { fdt = EFI_FDT_USE_INTERNAL; } - ret = efi_install_fdt(fdt); - if (ret == EFI_INVALID_PARAMETER) - return CMD_RET_USAGE; - else if (ret != EFI_SUCCESS) - return CMD_RET_FAILURE; - if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) { - if (!strcmp(argv[1], "bootmgr")) - return do_efibootmgr(); + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) && + !strcmp(argv[1], "bootmgr")) { + ret = efi_bootmgr_run(fdt); + + if (ret == EFI_INVALID_PARAMETER) + return CMD_RET_USAGE; + else if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; } -#ifdef CONFIG_CMD_BOOTEFI_SELFTEST - if (!strcmp(argv[1], "selftest")) + + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_SELFTEST) && + !strcmp(argv[1], "selftest")) { + /* Initialize EFI drivers */ + ret = efi_init_obj_list(); + if (ret != EFI_SUCCESS) { + log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n", + ret & ~EFI_ERROR_MASK); + return CMD_RET_FAILURE; + } + + ret = efi_install_fdt(fdt); + if (ret == EFI_INVALID_PARAMETER) + return CMD_RET_USAGE; + else if (ret != EFI_SUCCESS) + return CMD_RET_FAILURE; + return do_efi_selftest(); -#endif - str_copy = strdup(argv[1]); - if (!str_copy) { - log_err("Out of memory\n"); - return CMD_RET_FAILURE; } - pos = str_copy; - img_addr = strsep(&pos, ":"); - img_size = strsep(&pos, ":"); - ret = do_bootefi_image(img_addr, img_size); - free(str_copy); - return ret; + if (!IS_ENABLED(CONFIG_CMD_BOOTEFI_BINARY)) + return CMD_RET_SUCCESS; + + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_HELLO) && + !strcmp(argv[1], "hello")) { + image_buf = __efi_helloworld_begin; + size = __efi_helloworld_end - __efi_helloworld_begin; + /* TODO: not sure calling clear function is necessary */ + efi_clear_bootdev(); + } else { + addr = strtoul(argv[1], NULL, 16); + /* Check that a numeric value was passed */ + if (!addr) + return CMD_RET_USAGE; + image_buf = map_sysmem(addr, 0); + + p = strchr(argv[1], ':'); + if (p) { + size = strtoul(++p, NULL, 16); + if (!size) + return CMD_RET_USAGE; + efi_clear_bootdev(); + } else { + /* Image should be already loaded */ + efi_get_image_parameters(&image_addr, &image_size); + + if (image_buf != image_addr) { + log_err("No UEFI binary known at %s\n", + argv[1]); + return CMD_RET_FAILURE; + } + size = image_size; + } + } + + ret = efi_binary_run(image_buf, size, fdt); + + if (ret == EFI_INVALID_PARAMETER) + return CMD_RET_USAGE; + else if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; } U_BOOT_LONGHELP(bootefi, diff --git a/cmd/bootflow.c b/cmd/bootflow.c index 3aeb40d690f..4a47265ebd5 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -135,7 +135,7 @@ static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc, struct udevice *dev = NULL; struct bootflow bflow; bool all = false, boot = false, errors = false, no_global = false; - bool list = false, no_hunter = false; + bool list = false, no_hunter = false, menu = false, text_mode = false; int num_valid = 0; const char *label = NULL; bool has_args; @@ -155,6 +155,8 @@ static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc, no_global = strchr(argv[1], 'G'); list = strchr(argv[1], 'l'); no_hunter = strchr(argv[1], 'H'); + menu = strchr(argv[1], 'm'); + text_mode = strchr(argv[1], 't'); argc--; argv++; } @@ -213,15 +215,32 @@ static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc, } if (list) show_bootflow(i, &bflow, errors); - if (boot && !bflow.err) + if (!menu && boot && !bflow.err) bootflow_run_boot(&iter, &bflow); } bootflow_iter_uninit(&iter); if (list) show_footer(i, num_valid); - if (IS_ENABLED(CONFIG_CMD_BOOTFLOW_FULL) && !num_valid && !list) - printf("No bootflows found; try again with -l\n"); + if (IS_ENABLED(CONFIG_CMD_BOOTFLOW_FULL) && IS_ENABLED(CONFIG_EXPO)) { + if (!num_valid && !list) { + printf("No bootflows found; try again with -l\n"); + } else if (menu) { + struct bootflow *sel_bflow; + + ret = bootflow_handle_menu(std, text_mode, &sel_bflow); + if (!ret && boot) { + ret = console_clear(); + if (ret) { + log_err("Failed to clear console: %dE\n", + ret); + return ret; + } + + bootflow_run_boot(NULL, sel_bflow); + } + } + } return 0; } diff --git a/cmd/booti.c b/cmd/booti.c index a6c7db272c5..41d40c962ec 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -75,7 +75,7 @@ static int booti_start(struct cmd_tbl *cmdtp, int flag, int argc, unmap_sysmem((void *)ld); ret = booti_setup(ld, &relocated_addr, &image_size, false); - if (ret != 0) + if (ret || IS_ENABLED(CONFIG_SANDBOX)) return 1; /* Handle BOOTM_STATE_LOADOS */ @@ -95,7 +95,9 @@ static int booti_start(struct cmd_tbl *cmdtp, int flag, int argc, * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not * have a header that provide this informaiton. */ - if (bootm_find_images(flag, argc, argv, relocated_addr, image_size)) + if (bootm_find_images(image_load_addr, cmd_arg1(argc, argv), + cmd_arg2(argc, argv), relocated_addr, + image_size)) return 1; return 0; diff --git a/cmd/bootz.c b/cmd/bootz.c index dd6fe4904b0..a652879ea5e 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -54,7 +54,9 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc, * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not * have a header that provide this informaiton. */ - if (bootm_find_images(flag, argc, argv, images->ep, zi_end - zi_start)) + if (bootm_find_images(image_load_addr, cmd_arg1(argc, argv), + cmd_arg2(argc, argv), images->ep, + zi_end - zi_start)) return 1; return 0; diff --git a/cmd/btrfs.c b/cmd/btrfs.c index 98daea99e9e..2843835d08b 100644 --- a/cmd/btrfs.c +++ b/cmd/btrfs.c @@ -24,4 +24,4 @@ U_BOOT_CMD(btrsubvol, 3, 1, do_btrsubvol, "list subvolumes of a BTRFS filesystem", "<interface> <dev[:part]>\n" " - List subvolumes of a BTRFS filesystem." -) +); diff --git a/cmd/clk.c b/cmd/clk.c index c7c379d7a61..7bbcbfeda33 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -59,9 +59,10 @@ static void show_clks(struct udevice *dev, int depth, int last_flag) } } -int __weak soc_clk_dump(void) +static int soc_clk_dump(void) { struct udevice *dev; + const struct clk_ops *ops; printf(" Rate Usecnt Name\n"); printf("------------------------------------------\n"); @@ -69,10 +70,18 @@ int __weak soc_clk_dump(void) uclass_foreach_dev_probe(UCLASS_CLK, dev) show_clks(dev, -1, 0); + uclass_foreach_dev_probe(UCLASS_CLK, dev) { + ops = dev_get_driver_ops(dev); + if (ops && ops->dump) { + printf("\n%s %s:\n", dev->driver->name, dev->name); + ops->dump(dev); + } + } + return 0; } #else -int __weak soc_clk_dump(void) +static int soc_clk_dump(void) { puts("Not implemented\n"); return 1; diff --git a/cmd/cls.c b/cmd/cls.c index 1125a3f81bb..80d0558d467 100644 --- a/cmd/cls.c +++ b/cmd/cls.c @@ -7,33 +7,14 @@ */ #include <common.h> #include <command.h> +#include <console.h> #include <dm.h> -#include <video_console.h> - -#define CSI "\x1b[" static int do_video_clear(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - __maybe_unused struct udevice *dev; - - /* - * Send clear screen and home - * - * FIXME(Heinrich Schuchardt <xypron.glpk@gmx.de>): This should go - * through an API and only be written to serial terminals, not video - * displays - */ - printf(CSI "2J" CSI "1;1H"); - if (IS_ENABLED(CONFIG_VIDEO_ANSI)) - return 0; - - if (IS_ENABLED(CONFIG_VIDEO)) { - if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev)) - return CMD_RET_FAILURE; - if (vidconsole_clear_and_reset(dev)) - return CMD_RET_FAILURE; - } + if (console_clear()) + return CMD_RET_FAILURE; return CMD_RET_SUCCESS; } diff --git a/cmd/disk.c b/cmd/disk.c index 3d7bc2f6018..92eaa02f4a1 100644 --- a/cmd/disk.c +++ b/cmd/disk.c @@ -40,8 +40,8 @@ int common_diskboot(struct cmd_tbl *cmdtp, const char *intf, int argc, bootstage_mark(BOOTSTAGE_ID_IDE_BOOT_DEVICE); - part = blk_get_device_part_str(intf, (argc == 3) ? argv[2] : NULL, - &dev_desc, &info, 1); + part = blk_get_device_part_str(intf, cmd_arg2(argc, argv), + &dev_desc, &info, 1); if (part < 0) { bootstage_error(BOOTSTAGE_ID_IDE_TYPE); return 1; diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 0b6ca8c505f..322765ad02a 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -435,4 +435,4 @@ U_BOOT_CMD( "The values which can be provided with the -l option are:\n" CONFIG_EEPROM_LAYOUT_HELP_STRING"\n" #endif -) +); diff --git a/cmd/efi_common.c b/cmd/efi_common.c index f4056096cd3..1aa2351fcdf 100644 --- a/cmd/efi_common.c +++ b/cmd/efi_common.c @@ -17,10 +17,8 @@ void efi_show_tables(struct efi_system_table *systab) for (i = 0; i < systab->nr_tables; i++) { struct efi_configuration_table *tab = &systab->tables[i]; - char guid_str[37]; - uuid_bin_to_str(tab->guid.b, guid_str, 1); - printf("%p %pUl %s\n", tab->table, guid_str, + printf("%p %pUl %s\n", tab->table, tab->guid.b, uuid_guid_get_str(tab->guid.b) ?: "(unknown)"); } } diff --git a/cmd/efidebug.c b/cmd/efidebug.c index 201531ac19f..e10fbf891a4 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -19,6 +19,7 @@ #include <log.h> #include <malloc.h> #include <mapmem.h> +#include <net.h> #include <part.h> #include <search.h> #include <linux/ctype.h> @@ -708,6 +709,65 @@ out: } /** + * efi_boot_add_uri() - set URI load option + * + * @argc: Number of arguments + * @argv: Argument array + * @var_name16: variable name buffer + * @var_name16_size: variable name buffer size + * @lo: pointer to the load option + * @file_path: buffer to set the generated device path pointer + * @fp_size: file_path size + * Return: CMD_RET_SUCCESS on success, + * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure + */ +static int efi_boot_add_uri(int argc, char *const argv[], u16 *var_name16, + size_t var_name16_size, struct efi_load_option *lo, + struct efi_device_path **file_path, + efi_uintn_t *fp_size) +{ + int id; + char *pos; + char *endp; + u16 *label; + efi_uintn_t uridp_len; + struct efi_device_path_uri *uridp; + + if (argc < 3 || lo->label) + return CMD_RET_USAGE; + + id = (int)hextoul(argv[1], &endp); + if (*endp != '\0' || id > 0xffff) + return CMD_RET_USAGE; + + label = efi_convert_string(argv[2]); + if (!label) + return CMD_RET_FAILURE; + + if (!wget_validate_uri(argv[3])) { + printf("ERROR: invalid URI\n"); + return CMD_RET_FAILURE; + } + + efi_create_indexed_name(var_name16, var_name16_size, "Boot", id); + lo->label = label; + + uridp_len = sizeof(struct efi_device_path) + strlen(argv[3]) + 1; + uridp = efi_alloc(uridp_len + sizeof(END)); + uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE; + uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI; + uridp->dp.length = uridp_len; + strcpy(uridp->uri, argv[3]); + pos = (char *)uridp + uridp_len; + memcpy(pos, &END, sizeof(END)); + + *file_path = &uridp->dp; + *fp_size += uridp_len + sizeof(END); + + return CMD_RET_SUCCESS; +} + +/** * do_efi_boot_add() - set UEFI load option * * @cmdtp: Command table @@ -829,6 +889,21 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, argc -= 1; argv += 1; break; + case 'u': + if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT)) { + r = efi_boot_add_uri(argc, argv, var_name16, + sizeof(var_name16), &lo, + &file_path, &fp_size); + if (r != CMD_RET_SUCCESS) + goto out; + fp_free = file_path; + argc -= 3; + argv += 3; + } else{ + r = CMD_RET_USAGE; + goto out; + } + break; default: r = CMD_RET_USAGE; goto out; @@ -1335,7 +1410,7 @@ static __maybe_unused int do_efi_test_bootmgr(struct cmd_tbl *cmdtp, int flag, } static struct cmd_tbl cmd_efidebug_test_sub[] = { -#ifdef CONFIG_CMD_BOOTEFI_BOOTMGR +#ifdef CONFIG_BOOTEFI_BOOTMGR U_BOOT_CMD_MKENT(bootmgr, CONFIG_SYS_MAXARGS, 1, do_efi_test_bootmgr, "", ""), #endif @@ -1491,6 +1566,9 @@ U_BOOT_LONGHELP(efidebug, " -b|-B <bootid> <label> <interface> <devnum>[:<part>] <file path>\n" " -i|-I <interface> <devnum>[:<part>] <initrd file path>\n" " (-b, -i for short form device path)\n" +#if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT)) + " -u <bootid> <label> <uri>\n" +#endif " -s '<optional data>'\n" "efidebug boot rm <bootid#1> [<bootid#2> [<bootid#3> [...]]]\n" " - delete UEFI BootXXXX variables\n" @@ -1526,7 +1604,7 @@ U_BOOT_LONGHELP(efidebug, " - show UEFI memory map\n" "efidebug tables\n" " - show UEFI configuration tables\n" -#ifdef CONFIG_CMD_BOOTEFI_BOOTMGR +#ifdef CONFIG_BOOTEFI_BOOTMGR "efidebug test bootmgr\n" " - run simple bootmgr for test\n" #endif diff --git a/cmd/ext2.c b/cmd/ext2.c index 57a99516a6a..a0ce0cf5796 100644 --- a/cmd/ext2.c +++ b/cmd/ext2.c @@ -42,7 +42,7 @@ U_BOOT_CMD( "list files in a directory (default /)", "<interface> <dev[:part]> [directory]\n" " - list files from 'dev' on 'interface' in a 'directory'" -) +); U_BOOT_CMD( ext2load, 6, 0, do_ext2load, @@ -50,4 +50,4 @@ U_BOOT_CMD( "<interface> [<dev[:part]> [addr [filename [bytes [pos]]]]]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" " to address 'addr' from ext2 filesystem." -) +); @@ -39,7 +39,7 @@ U_BOOT_CMD( " If 'bytes' is 0 or omitted, the file is read until the end.\n" " 'pos' gives the file byte position to start reading from.\n" " If 'pos' is 0 or omitted, the file is read from the start." -) +); static int do_save_wrapper(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -56,7 +56,7 @@ U_BOOT_CMD( " 'bytes' gives the size to save in bytes and is mandatory.\n" " 'pos' gives the file byte position to start writing to.\n" " If 'pos' is 0 or omitted, the file is written from the start." -) +); static int do_ls_wrapper(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -70,7 +70,7 @@ U_BOOT_CMD( "<interface> [<dev[:part]> [directory]]\n" " - List files in directory 'directory' of partition 'part' on\n" " device type 'interface' instance 'dev'." -) +); static int do_ln_wrapper(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -84,7 +84,7 @@ U_BOOT_CMD( "<interface> <dev[:part]> target linkname\n" " - create a symbolic link to 'target' with the name 'linkname' on\n" " device type 'interface' instance 'dev'." -) +); static int do_fstype_wrapper(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/fuse.c b/cmd/fuse.c index 0676bb7a812..f884c894fb0 100644 --- a/cmd/fuse.c +++ b/cmd/fuse.c @@ -44,7 +44,7 @@ static int confirm_prog(void) static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - const char *op = argc >= 2 ? argv[1] : NULL; + const char *op = cmd_arg1(argc, argv); int confirmed = argc >= 3 && !strcmp(argv[2], "-y"); u32 bank, word, cnt, val, cmp; ulong addr; diff --git a/cmd/mmc.c b/cmd/mmc.c index 96befb27eec..2d5430a5307 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -946,7 +946,7 @@ static int do_mmc_partconf(struct cmd_tbl *cmdtp, int flag, } if (argc == 2 || argc == 3) - return mmc_partconf_print(mmc, argc == 3 ? argv[2] : NULL); + return mmc_partconf_print(mmc, cmd_arg2(argc, argv)); ack = dectoul(argv[2], NULL); part_num = dectoul(argv[3], NULL); diff --git a/cmd/nand.c b/cmd/nand.c index 71b8f964429..fe834c4ac5c 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -34,6 +34,7 @@ #include <env.h> #include <watchdog.h> #include <malloc.h> +#include <mapmem.h> #include <asm/byteorder.h> #include <jffs2/jffs2.h> #include <nand.h> @@ -432,7 +433,7 @@ static void nand_print_and_set_info(int idx) env_set_hex("nand_erasesize", mtd->erasesize); } -static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off, +static int raw_access(struct mtd_info *mtd, void *buf, loff_t off, ulong count, int read, int no_verify) { int ret = 0; @@ -440,8 +441,8 @@ static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off, while (count--) { /* Raw access */ mtd_oob_ops_t ops = { - .datbuf = (u8 *)addr, - .oobbuf = ((u8 *)addr) + mtd->writesize, + .datbuf = buf, + .oobbuf = buf + mtd->writesize, .len = mtd->writesize, .ooblen = mtd->oobsize, .mode = MTD_OPS_RAW @@ -461,7 +462,7 @@ static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off, break; } - addr += mtd->writesize + mtd->oobsize; + buf += mtd->writesize + mtd->oobsize; off += mtd->writesize; } @@ -675,6 +676,7 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc, int read; int raw = 0; int no_verify = 0; + void *buf; if (argc < 4) goto usage; @@ -730,32 +732,32 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc, } mtd = get_nand_dev_by_index(dev); + buf = map_sysmem(addr, maxsize); if (!s || !strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")) { if (read) ret = nand_read_skip_bad(mtd, off, &rwsize, - NULL, maxsize, - (u_char *)addr); + NULL, maxsize, buf); else ret = nand_write_skip_bad(mtd, off, &rwsize, - NULL, maxsize, - (u_char *)addr, + NULL, maxsize, buf, WITH_WR_VERIFY); #ifdef CONFIG_CMD_NAND_TRIMFFS } else if (!strcmp(s, ".trimffs")) { if (read) { printf("Unknown nand command suffix '%s'\n", s); + unmap_sysmem(buf); return 1; } ret = nand_write_skip_bad(mtd, off, &rwsize, NULL, - maxsize, (u_char *)addr, + maxsize, buf, WITH_DROP_FFS | WITH_WR_VERIFY); #endif } else if (!strcmp(s, ".oob")) { /* out-of-band data */ mtd_oob_ops_t ops = { - .oobbuf = (u8 *)addr, + .oobbuf = buf, .ooblen = rwsize, .mode = MTD_OPS_RAW }; @@ -765,13 +767,15 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc, else ret = mtd_write_oob(mtd, off, &ops); } else if (raw) { - ret = raw_access(mtd, addr, off, pagecount, read, + ret = raw_access(mtd, buf, off, pagecount, read, no_verify); } else { printf("Unknown nand command suffix '%s'.\n", s); + unmap_sysmem(buf); return 1; } + unmap_sysmem(buf); printf(" %zu bytes %s: %s\n", rwsize, read ? "read" : "written", ret ? "ERROR" : "OK"); diff --git a/cmd/nvedit.c b/cmd/nvedit.c index daf1ad37f9b..e77338f8139 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -49,20 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; */ #define MAX_ENV_SIZE (1 << 20) /* 1 MiB */ -/* - * This variable is incremented on each do_env_set(), so it can - * be used via env_get_id() as an indication, if the environment - * has changed or not. So it is possible to reread an environment - * variable only if the environment was changed ... done so for - * example in NetInitLoop() - */ -static int env_id = 1; - -int env_get_id(void) -{ - return env_id; -} - #ifndef CONFIG_SPL_BUILD /* * Command interface: print one or all environment variables @@ -198,104 +184,6 @@ DONE: #endif #endif /* CONFIG_SPL_BUILD */ -/* - * Set a new environment variable, - * or replace or delete an existing one. - */ -static int _do_env_set(int flag, int argc, char *const argv[], int env_flag) -{ - int i, len; - char *name, *value, *s; - struct env_entry e, *ep; - - debug("Initial value for argc=%d\n", argc); - -#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_CMD_NVEDIT_EFI) - if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e') - return do_env_set_efi(NULL, flag, --argc, ++argv); -#endif - - while (argc > 1 && **(argv + 1) == '-') { - char *arg = *++argv; - - --argc; - while (*++arg) { - switch (*arg) { - case 'f': /* force */ - env_flag |= H_FORCE; - break; - default: - return CMD_RET_USAGE; - } - } - } - debug("Final value for argc=%d\n", argc); - name = argv[1]; - - if (strchr(name, '=')) { - printf("## Error: illegal character '='" - "in variable name \"%s\"\n", name); - return 1; - } - - env_id++; - - /* Delete only ? */ - if (argc < 3 || argv[2] == NULL) { - int rc = hdelete_r(name, &env_htab, env_flag); - - /* If the variable didn't exist, don't report an error */ - return rc && rc != -ENOENT ? 1 : 0; - } - - /* - * Insert / replace new value - */ - for (i = 2, len = 0; i < argc; ++i) - len += strlen(argv[i]) + 1; - - value = malloc(len); - if (value == NULL) { - printf("## Can't malloc %d bytes\n", len); - return 1; - } - for (i = 2, s = value; i < argc; ++i) { - char *v = argv[i]; - - while ((*s++ = *v++) != '\0') - ; - *(s - 1) = ' '; - } - if (s != value) - *--s = '\0'; - - e.key = name; - e.data = value; - hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag); - free(value); - if (!ep) { - printf("## Error inserting \"%s\" variable, errno=%d\n", - name, errno); - return 1; - } - - return 0; -} - -int env_set(const char *varname, const char *varvalue) -{ - const char * const argv[4] = { "setenv", varname, varvalue, NULL }; - - /* before import into hashtable */ - if (!(gd->flags & GD_FLG_ENV_READY)) - return 1; - - if (varvalue == NULL || varvalue[0] == '\0') - return _do_env_set(0, 2, (char * const *)argv, H_PROGRAMMATIC); - else - return _do_env_set(0, 3, (char * const *)argv, H_PROGRAMMATIC); -} - #ifndef CONFIG_SPL_BUILD static int do_env_set(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -303,7 +191,7 @@ static int do_env_set(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 2) return CMD_RET_USAGE; - return _do_env_set(flag, argc, argv, H_INTERACTIVE); + return env_do_env_set(flag, argc, argv, H_INTERACTIVE); } /* @@ -381,7 +269,7 @@ int do_env_ask(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } /* Continue calling setenv code */ - return _do_env_set(flag, len, local_args, H_INTERACTIVE); + return env_do_env_set(flag, len, local_args, H_INTERACTIVE); } #endif @@ -561,12 +449,12 @@ static int do_env_edit(struct cmd_tbl *cmdtp, int flag, int argc, if (buffer[0] == '\0') { const char * const _argv[3] = { "setenv", argv[1], NULL }; - return _do_env_set(0, 2, (char * const *)_argv, H_INTERACTIVE); + return env_do_env_set(0, 2, (char * const *)_argv, H_INTERACTIVE); } else { const char * const _argv[4] = { "setenv", argv[1], buffer, NULL }; - return _do_env_set(0, 3, (char * const *)_argv, H_INTERACTIVE); + return env_do_env_set(0, 3, (char * const *)_argv, H_INTERACTIVE); } } #endif /* CONFIG_CMD_EDITENV */ @@ -679,7 +567,7 @@ static int do_env_delete(struct cmd_tbl *cmdtp, int flag, } debug("Final value for argc=%d\n", argc); - env_id++; + env_inc_id(); while (--argc > 0) { char *name = *++argv; diff --git a/cmd/pinmux.c b/cmd/pinmux.c index f17cf4110d9..105f01eaaff 100644 --- a/cmd/pinmux.c +++ b/cmd/pinmux.c @@ -178,4 +178,4 @@ U_BOOT_CMD(pinmux, CONFIG_SYS_MAXARGS, 1, do_pinmux, "list - list UCLASS_PINCTRL devices\n" "pinmux dev [pincontroller-name] - select pin-controller device\n" "pinmux status [-a | pin-name] - print pin-controller muxing [for all | for pin-name]\n" -) +); diff --git a/cmd/qfw.c b/cmd/qfw.c index d6ecfa60d5a..1b8c775ebf5 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -121,4 +121,4 @@ U_BOOT_CMD( " - list : print firmware(s) currently loaded\n" " - cpus : print online cpu number\n" " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n" -) +); diff --git a/cmd/scmi.c b/cmd/scmi.c new file mode 100644 index 00000000000..664062c4eff --- /dev/null +++ b/cmd/scmi.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SCMI (System Control and Management Interface) utility command + * + * Copyright (c) 2023 Linaro Limited + * Author: AKASHI Takahiro + */ + +#include <command.h> +#include <exports.h> +#include <scmi_agent.h> +#include <scmi_agent-uclass.h> +#include <stdlib.h> +#include <asm/types.h> +#include <dm/device.h> +#include <dm/uclass.h> /* uclass_get_device */ +#include <linux/bitfield.h> +#include <linux/bitops.h> + +struct { + enum scmi_std_protocol id; + const char *name; +} protocol_name[] = { + {SCMI_PROTOCOL_ID_BASE, "Base"}, + {SCMI_PROTOCOL_ID_POWER_DOMAIN, "Power domain management"}, + {SCMI_PROTOCOL_ID_SYSTEM, "System power management"}, + {SCMI_PROTOCOL_ID_PERF, "Performance domain management"}, + {SCMI_PROTOCOL_ID_CLOCK, "Clock management"}, + {SCMI_PROTOCOL_ID_SENSOR, "Sensor management"}, + {SCMI_PROTOCOL_ID_RESET_DOMAIN, "Reset domain management"}, + {SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, "Voltage domain management"}, +}; + +/** + * get_agent() - get SCMI agent device + * + * Return: Pointer to SCMI agent device on success, NULL on failure + */ +static struct udevice *get_agent(void) +{ + struct udevice *agent; + + if (uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent)) { + printf("Cannot find any SCMI agent\n"); + return NULL; + } + + return agent; +} + +/** + * get_base_proto() - get SCMI base protocol device + * @agent: SCMI agent device + * + * Return: Pointer to SCMI base protocol device on success, + * NULL on failure + */ +static struct udevice *get_base_proto(struct udevice *agent) +{ + struct udevice *base_proto; + + if (!agent) { + agent = get_agent(); + if (!agent) + return NULL; + } + + base_proto = scmi_get_protocol(agent, SCMI_PROTOCOL_ID_BASE); + if (!base_proto) { + printf("SCMI base protocol not found\n"); + return NULL; + } + + return base_proto; +} + +/** + * get_proto_name() - get the name of SCMI protocol + * + * @id: SCMI Protocol ID + * + * Get the printable name of the protocol, @id + * + * Return: Name string on success, NULL on failure + */ +static const char *get_proto_name(enum scmi_std_protocol id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(protocol_name); i++) + if (id == protocol_name[i].id) + return protocol_name[i].name; + + return NULL; +} + +/** + * do_scmi_info() - get the information of SCMI services + * + * @cmdtp: Command table + * @flag: Command flag + * @argc: Number of arguments + * @argv: Argument array + * + * Get the information of SCMI services using various interfaces + * provided by the Base protocol. + * + * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure + */ +static int do_scmi_info(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct udevice *agent, *base_proto; + u32 agent_id, num_protocols; + u8 *agent_name, *protocols; + int i, ret; + + if (argc != 1) + return CMD_RET_USAGE; + + agent = get_agent(); + if (!agent) + return CMD_RET_FAILURE; + base_proto = get_base_proto(agent); + if (!base_proto) + return CMD_RET_FAILURE; + + printf("SCMI device: %s\n", agent->name); + printf(" protocol version: 0x%x\n", scmi_version(agent)); + printf(" # of agents: %d\n", scmi_num_agents(agent)); + for (i = 0; i < scmi_num_agents(agent); i++) { + ret = scmi_base_discover_agent(base_proto, i, &agent_id, + &agent_name); + if (ret) { + if (ret != -EOPNOTSUPP) + printf("base_discover_agent() failed for id: %d (%d)\n", + i, ret); + break; + } + printf(" %c%2d: %s\n", i == scmi_agent_id(agent) ? '>' : ' ', + i, agent_name); + free(agent_name); + } + printf(" # of protocols: %d\n", scmi_num_protocols(agent)); + num_protocols = scmi_num_protocols(agent); + protocols = scmi_protocols(agent); + if (protocols) + for (i = 0; i < num_protocols; i++) + printf(" %s\n", get_proto_name(protocols[i])); + printf(" vendor: %s\n", scmi_vendor(agent)); + printf(" sub vendor: %s\n", scmi_sub_vendor(agent)); + printf(" impl version: 0x%x\n", scmi_impl_version(agent)); + + return CMD_RET_SUCCESS; +} + +/** + * do_scmi_set_dev() - set access permission to device + * + * @cmdtp: Command table + * @flag: Command flag + * @argc: Number of arguments + * @argv: Argument array + * + * Set access permission to device with SCMI_BASE_SET_DEVICE_PERMISSIONS + * + * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure + */ +static int do_scmi_set_dev(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 agent_id, device_id, flags, attributes; + char *end; + struct udevice *base_proto; + int ret; + + if (argc != 4) + return CMD_RET_USAGE; + + agent_id = simple_strtoul(argv[1], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + device_id = simple_strtoul(argv[2], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + flags = simple_strtoul(argv[3], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + base_proto = get_base_proto(NULL); + if (!base_proto) + return CMD_RET_FAILURE; + + ret = scmi_base_protocol_message_attrs(base_proto, + SCMI_BASE_SET_DEVICE_PERMISSIONS, + &attributes); + if (ret) { + printf("This operation is not supported\n"); + return CMD_RET_FAILURE; + } + + ret = scmi_base_set_device_permissions(base_proto, agent_id, + device_id, flags); + if (ret) { + printf("%s access to device:%u failed (%d)\n", + flags ? "Allowing" : "Denying", device_id, ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +/** + * do_scmi_set_proto() - set protocol permission to device + * + * @cmdtp: Command table + * @flag: Command flag + * @argc: Number of arguments + * @argv: Argument array + * + * Set protocol permission to device with SCMI_BASE_SET_PROTOCOL_PERMISSIONS + * + * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure + */ +static int do_scmi_set_proto(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 agent_id, device_id, protocol_id, flags, attributes; + char *end; + struct udevice *base_proto; + int ret; + + if (argc != 5) + return CMD_RET_USAGE; + + agent_id = simple_strtoul(argv[1], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + device_id = simple_strtoul(argv[2], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + protocol_id = simple_strtoul(argv[3], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + flags = simple_strtoul(argv[4], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + base_proto = get_base_proto(NULL); + if (!base_proto) + return CMD_RET_FAILURE; + + ret = scmi_base_protocol_message_attrs(base_proto, + SCMI_BASE_SET_PROTOCOL_PERMISSIONS, + &attributes); + if (ret) { + printf("This operation is not supported\n"); + return CMD_RET_FAILURE; + } + + ret = scmi_base_set_protocol_permissions(base_proto, agent_id, + device_id, protocol_id, + flags); + if (ret) { + printf("%s access to protocol:0x%x on device:%u failed (%d)\n", + flags ? "Allowing" : "Denying", protocol_id, device_id, + ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +/** + * do_scmi_reset() - reset platform resource settings + * + * @cmdtp: Command table + * @flag: Command flag + * @argc: Number of arguments + * @argv: Argument array + * + * Reset platform resource settings with BASE_RESET_AGENT_CONFIGURATION + * + * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure + */ +static int do_scmi_reset(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 agent_id, flags, attributes; + char *end; + struct udevice *base_proto; + int ret; + + if (argc != 3) + return CMD_RET_USAGE; + + agent_id = simple_strtoul(argv[1], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + flags = simple_strtoul(argv[2], &end, 16); + if (*end != '\0') + return CMD_RET_USAGE; + + base_proto = get_base_proto(NULL); + if (!base_proto) + return CMD_RET_FAILURE; + + ret = scmi_base_protocol_message_attrs(base_proto, + SCMI_BASE_RESET_AGENT_CONFIGURATION, + &attributes); + if (ret) { + printf("Reset is not supported\n"); + return CMD_RET_FAILURE; + } + + ret = scmi_base_reset_agent_configuration(base_proto, agent_id, flags); + if (ret) { + printf("Reset failed (%d)\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static struct cmd_tbl cmd_scmi_sub[] = { + U_BOOT_CMD_MKENT(info, CONFIG_SYS_MAXARGS, 1, + do_scmi_info, "", ""), + U_BOOT_CMD_MKENT(perm_dev, CONFIG_SYS_MAXARGS, 1, + do_scmi_set_dev, "", ""), + U_BOOT_CMD_MKENT(perm_proto, CONFIG_SYS_MAXARGS, 1, + do_scmi_set_proto, "", ""), + U_BOOT_CMD_MKENT(reset, CONFIG_SYS_MAXARGS, 1, + do_scmi_reset, "", ""), +}; + +/** + * do_scmi() - SCMI utility + * + * @cmdtp: Command table + * @flag: Command flag + * @argc: Number of arguments + * @argv: Argument array + * + * Provide user interfaces to SCMI protocols. + * + * Return: CMD_RET_SUCCESS on success, + * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure + */ +static int do_scmi(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct cmd_tbl *cp; + + if (argc < 2) + return CMD_RET_USAGE; + + argc--; argv++; + + cp = find_cmd_tbl(argv[0], cmd_scmi_sub, ARRAY_SIZE(cmd_scmi_sub)); + if (!cp) + return CMD_RET_USAGE; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +static char scmi_help_text[] = + " - SCMI utility\n" + " info - get the info of SCMI services\n" + " perm_dev <agent-id in hex> <device-id in hex> <flags in hex>\n" + " - set access permission to device\n" + " perm_proto <agent-id in hex> <device-id in hex> <protocol-id in hex> <flags in hex>\n" + " - set protocol permission to device\n" + " reset <agent-id in hex> <flags in hex>\n" + " - reset platform resource settings\n" + ""; + +U_BOOT_CMD(scmi, CONFIG_SYS_MAXARGS, 0, do_scmi, "SCMI utility", + scmi_help_text); diff --git a/cmd/scsi.c b/cmd/scsi.c index 4549995ba73..c501d7f456d 100644 --- a/cmd/scsi.c +++ b/cmd/scsi.c @@ -34,9 +34,6 @@ static int do_scsi(struct cmd_tbl *cmdtp, int flag, int argc, if (argc == 2) { if (strncmp(argv[1], "res", 3) == 0) { printf("\nReset SCSI\n"); -#ifndef CONFIG_DM_SCSI - scsi_bus_reset(NULL); -#endif ret = scsi_scan(true); if (ret) return CMD_RET_FAILURE; diff --git a/cmd/ufs.c b/cmd/ufs.c index 282b4146e92..536bd85b75d 100644 --- a/cmd/ufs.c +++ b/cmd/ufs.c @@ -32,6 +32,6 @@ static int do_ufs(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } U_BOOT_CMD(ufs, 3, 1, do_ufs, - "UFS sub system", + "UFS sub-system", "init [dev] - init UFS subsystem\n" ); diff --git a/cmd/version.c b/cmd/version.c index 87e1fa4159c..d99a44f19fb 100644 --- a/cmd/version.c +++ b/cmd/version.c @@ -7,21 +7,12 @@ #include <common.h> #include <command.h> #include <display_options.h> -#include <timestamp.h> -#include <version.h> #include <version_string.h> #include <linux/compiler.h> #ifdef CONFIG_SYS_COREBOOT #include <asm/cb_sysinfo.h> #endif -#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \ - U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING - -const char version_string[] = U_BOOT_VERSION_STRING; -const unsigned short version_num = U_BOOT_VERSION_NUM; -const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH; - static int do_version(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/common/Kconfig b/common/Kconfig index 0f548195197..0283701f1d0 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -52,6 +52,29 @@ config CONSOLE_RECORD_IN_SIZE The buffer is allocated immediately after the malloc() region is ready. +config SYS_CBSIZE + int "Console input buffer size" + default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \ + RCAR_GEN3 || TARGET_SOCFPGA_SOC64 + default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \ + FSL_LSCH3 || X86 + default 256 if M68K || PPC + default 1024 + help + Set the size of the console input buffer. This is used both in the + case of reading input literally from the user in some manner as well + as when we need to construct or modify that type of input, for + example when constructing "bootargs" for the OS. + +config SYS_PBSIZE + int "Console output buffer size" + default 1024 if ARCH_SUNXI + default 1044 + help + Set the size of the console output buffer. This is used when we need + to work with some form of a buffer while providing output in some + form to the user. + config DISABLE_CONSOLE bool "Add functionality to disable console completely" help diff --git a/common/Makefile b/common/Makefile index cdeadf72026..1495436d5d4 100644 --- a/common/Makefile +++ b/common/Makefile @@ -8,8 +8,10 @@ ifndef CONFIG_SPL_BUILD obj-y += init/ obj-y += main.o obj-y += exports.o +obj-y += cli_getch.o cli_simple.o cli_readline.o obj-$(CONFIG_HUSH_PARSER) += cli_hush.o obj-$(CONFIG_AUTOBOOT) += autoboot.o +obj-y += version.o # # boards obj-y += board_f.o @@ -37,7 +39,6 @@ obj-$(CONFIG_SPLASH_SOURCE) += splash_source.o obj-$(CONFIG_MENU) += menu.o obj-$(CONFIG_UPDATE_COMMON) += update.o obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o -obj-$(CONFIG_CMDLINE) += cli_getch.o cli_readline.o cli_simple.o endif # !CONFIG_SPL_BUILD diff --git a/common/board_info.c b/common/board_info.c index e0f2d939220..f4c385add90 100644 --- a/common/board_info.c +++ b/common/board_info.c @@ -15,41 +15,65 @@ int __weak checkboard(void) return 0; } -/* - * Check sysinfo for board information. Failing that if the root node of the DTB - * has a "model" property, show it. - * - * Then call checkboard(). - */ -int __weak show_board_info(void) +static const struct to_show { + const char *name; + enum sysinfo_id id; +} to_show[] = { + { "Manufacturer", SYSINFO_ID_BOARD_MANUFACTURER}, + { "Prior-stage version", SYSINFO_ID_PRIOR_STAGE_VERSION }, + { "Prior-stage date", SYSINFO_ID_PRIOR_STAGE_DATE }, + { /* sentinel */ } +}; + +static int try_sysinfo(void) +{ + struct udevice *dev; + char str[80]; + int ret; + + /* This might provide more detail */ + ret = sysinfo_get(&dev); + if (ret) + return ret; + + ret = sysinfo_detect(dev); + if (ret) + return ret; + + ret = sysinfo_get_str(dev, SYSINFO_ID_BOARD_MODEL, sizeof(str), str); + if (ret) + return ret; + printf("Model: %s\n", str); + + if (IS_ENABLED(CONFIG_SYSINFO_EXTRA)) { + const struct to_show *item; + + for (item = to_show; item->id; item++) { + ret = sysinfo_get_str(dev, item->id, sizeof(str), str); + if (!ret) + printf("%s: %s\n", item->name, str); + } + } + + return 0; +} + +int show_board_info(void) { if (IS_ENABLED(CONFIG_OF_CONTROL)) { - struct udevice *dev; - const char *model; - char str[80]; int ret = -ENOSYS; - if (IS_ENABLED(CONFIG_SYSINFO)) { - /* This might provide more detail */ - ret = sysinfo_get(&dev); - if (!ret) { - ret = sysinfo_detect(dev); - if (!ret) { - ret = sysinfo_get_str(dev, - SYSINFO_ID_BOARD_MODEL, - sizeof(str), str); - } - } - } + if (IS_ENABLED(CONFIG_SYSINFO)) + ret = try_sysinfo(); /* Fail back to the main 'model' if available */ - if (ret) - model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - else - model = str; + if (ret) { + const char *model; - if (model) - printf("Model: %s\n", model); + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (model) + printf("Model: %s\n", model); + } } return checkboard(); diff --git a/common/board_r.c b/common/board_r.c index a7967849dc0..da0b80f24ff 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -472,17 +472,6 @@ static int initr_status_led(void) } #endif -#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI) -static int initr_scsi(void) -{ - puts("SCSI: "); - scsi_init(); - puts("\n"); - - return 0; -} -#endif - #ifdef CONFIG_CMD_NET static int initr_net(void) { @@ -732,10 +721,6 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_BOARD_LATE_INIT board_late_init, #endif -#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI) - INIT_FUNC_WATCHDOG_RESET - initr_scsi, -#endif #ifdef CONFIG_BITBANGMII bb_miiphy_init, #endif diff --git a/common/cli_simple.c b/common/cli_simple.c index e80ba488a5e..f89ba92d1b0 100644 --- a/common/cli_simple.c +++ b/common/cli_simple.c @@ -22,44 +22,6 @@ #define debug_parser(fmt, args...) \ debug_cond(DEBUG_PARSER, fmt, ##args) - -int cli_simple_parse_line(char *line, char *argv[]) -{ - int nargs = 0; - - debug_parser("%s: \"%s\"\n", __func__, line); - while (nargs < CONFIG_SYS_MAXARGS) { - /* skip any white space */ - while (isblank(*line)) - ++line; - - if (*line == '\0') { /* end of line, no more args */ - argv[nargs] = NULL; - debug_parser("%s: nargs=%d\n", __func__, nargs); - return nargs; - } - - argv[nargs++] = line; /* begin of argument string */ - - /* find end of string */ - while (*line && !isblank(*line)) - ++line; - - if (*line == '\0') { /* end of line, no more args */ - argv[nargs] = NULL; - debug_parser("parse_line: nargs=%d\n", nargs); - return nargs; - } - - *line++ = '\0'; /* terminate current arg */ - } - - printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS); - - debug_parser("%s: nargs=%d\n", __func__, nargs); - return nargs; -} - int cli_simple_process_macros(const char *input, char *output, int max_size) { char c, prev; @@ -172,6 +134,44 @@ int cli_simple_process_macros(const char *input, char *output, int max_size) return ret; } +#ifdef CONFIG_CMDLINE +int cli_simple_parse_line(char *line, char *argv[]) +{ + int nargs = 0; + + debug_parser("%s: \"%s\"\n", __func__, line); + while (nargs < CONFIG_SYS_MAXARGS) { + /* skip any white space */ + while (isblank(*line)) + ++line; + + if (*line == '\0') { /* end of line, no more args */ + argv[nargs] = NULL; + debug_parser("%s: nargs=%d\n", __func__, nargs); + return nargs; + } + + argv[nargs++] = line; /* begin of argument string */ + + /* find end of string */ + while (*line && !isblank(*line)) + ++line; + + if (*line == '\0') { /* end of line, no more args */ + argv[nargs] = NULL; + debug_parser("parse_line: nargs=%d\n", nargs); + return nargs; + } + + *line++ = '\0'; /* terminate current arg */ + } + + printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS); + + debug_parser("%s: nargs=%d\n", __func__, nargs); + return nargs; +} + /* * WARNING: * @@ -346,3 +346,4 @@ int cli_simple_run_command_list(char *cmd, int flag) return rcode; } +#endif diff --git a/common/console.c b/common/console.c index 98c3ee6ca6b..1ffda49c87e 100644 --- a/common/console.c +++ b/common/console.c @@ -19,12 +19,15 @@ #include <stdio_dev.h> #include <exports.h> #include <env_internal.h> +#include <video_console.h> #include <watchdog.h> #include <asm/global_data.h> #include <linux/delay.h> DECLARE_GLOBAL_DATA_PTR; +#define CSI "\x1b[" + static int on_console(const char *name, const char *value, enum env_op op, int flags) { @@ -1010,6 +1013,34 @@ int console_init_f(void) return 0; } +int console_clear(void) +{ + /* + * Send clear screen and home + * + * FIXME(Heinrich Schuchardt <xypron.glpk@gmx.de>): This should go + * through an API and only be written to serial terminals, not video + * displays + */ + printf(CSI "2J" CSI "1;1H"); + if (IS_ENABLED(CONFIG_VIDEO_ANSI)) + return 0; + + if (IS_ENABLED(CONFIG_VIDEO)) { + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev); + if (ret) + return ret; + ret = vidconsole_clear_and_reset(dev); + if (ret) + return ret; + } + + return 0; +} + static void stdio_print_current_devices(void) { char *stdinname, *stdoutname, *stderrname; diff --git a/common/main.c b/common/main.c index 7c70de2e59a..6dba6cba144 100644 --- a/common/main.c +++ b/common/main.c @@ -9,6 +9,7 @@ #include <common.h> #include <autoboot.h> #include <bootstage.h> +#include <bootstd.h> #include <cli.h> #include <command.h> #include <console.h> @@ -67,6 +68,16 @@ void main_loop(void) autoboot_command(s); + /* if standard boot if enabled, assume that it will be able to boot */ + if (IS_ENABLED(CONFIG_BOOTSTD_PROG)) { + int ret; + + ret = bootstd_prog_boot(); + printf("Standard boot failed (err=%dE)\n", ret); + panic("Failed to boot"); + } + cli_loop(); + panic("No CLI available"); } diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 25cd18afda7..cf7ffc9b112 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -183,6 +183,7 @@ config SPL_SYS_REPORT_STACK_F_USAGE config SPL_SHOW_ERRORS bool "Show more information when something goes wrong" + depends on SPL_LIBCOMMON_SUPPORT help This enabled more verbose error messages and checking when something goes wrong in SPL. For example, it shows the error code when U-Boot @@ -279,8 +280,15 @@ config SPL_BOARD_INIT spl_board_init() from board_init_r(). This function should be provided by the board. +config SPL_LOAD_BLOCK + bool + help + Support loading images from block devices. This adds a bl_len member + to struct spl_load_info. + config SPL_BOOTROM_SUPPORT bool "Support returning to the BOOTROM" + select SPL_LOAD_BLOCK if MACH_IMX help Some platforms (e.g. the Rockchip RK3368) provide support in their ROM for loading the next boot-stage after performing basic setup @@ -370,7 +378,7 @@ config SPL_STACK default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB default 0x118000 if MACH_SUN50I_H6 - default 0x58000 if MACH_SUN50I_H616 + default 0x52a00 if MACH_SUN50I_H616 default 0x40000 if MACH_SUN8I_R528 default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5 default 0x18000 if MACH_SUN9I @@ -473,6 +481,11 @@ config SPL_DISPLAY_PRINT banner ("U-Boot SPL ..."). This function should be provided by the board. +config SPL_SYS_MMCSD_RAW_MODE + bool + help + Support booting from an MMC without a filesystem. + config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR bool "MMC raw mode: by sector" default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \ @@ -481,6 +494,8 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ OMAP44XX || OMAP54XX || AM33XX || AM43XX || \ TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED + select SPL_LOAD_BLOCK if SPL_MMC + select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC help Use sector number for specifying U-Boot location on MMC/SD in raw mode. @@ -517,6 +532,8 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION bool "MMC Raw mode: by partition" + select SPL_LOAD_BLOCK if SPL_MMC + select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC help Use a partition for loading U-Boot when using MMC/SD in raw mode. @@ -683,6 +700,22 @@ config SPL_FS_FAT filesystem from within SPL. Support for the underlying block device (e.g. MMC or USB) must be enabled separately. +config SPL_FS_FAT_DMA_ALIGN + bool "Use DMA-aligned buffers with FAT" + depends on SPL_FS_FAT + select SPL_LOAD_BLOCK + default y if SPL_LOAD_FIT + help + The FAT filesystem driver tries to ensure that the reads it issues to + the block subsystem use DMA-aligned buffers. If the supplied buffer is + not DMA-aligned, the FAT driver will use a bounce-buffer and read + block-by-block. This is separate from the bounce-buffer used by the + block subsystem (CONFIG_BOUNCE_BUFFER). + + Enable this config to align buffers passed to the FAT filesystem + driver. This will speed up reads, but will increase the size of U-Boot + by around 60 bytes. + config SPL_FS_LOAD_PAYLOAD_NAME string "File to load for U-Boot from the filesystem" depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS || SPL_SEMIHOSTING @@ -857,7 +890,7 @@ config SPL_MPC8XXX_INIT_DDR allows DRAM to be set up before loading U-Boot into that DRAM, where it can run. -config SPL_MTD_SUPPORT +config SPL_MTD bool "Support MTD drivers" help Enable support for MTD (Memory Technology Device) within SPL. MTD @@ -876,6 +909,7 @@ config SPL_MUSB_NEW config SPL_NAND_SUPPORT bool "Support NAND flash" + select SPL_LOAD_BLOCK help Enable support for NAND (Negative AND) flash in SPL. NAND flash can be used to allow SPL to load U-Boot from supported devices. @@ -1101,6 +1135,8 @@ config SYS_OS_BASE config SPL_FALCON_BOOT_MMCSD bool "Enable Falcon boot from MMC or SD media" depends on SPL_OS_BOOT && SPL_MMC + select SPL_LOAD_BLOCK + select SPL_SYS_MMCSD_RAW_MODE help Select this if the Falcon mode OS image mode is on MMC or SD media. @@ -1259,7 +1295,6 @@ config SPL_SATA_RAW_U_BOOT_SECTOR config SPL_NVME bool "NVM Express device support" depends on BLK - select HAVE_BLOCK_DEVICE select FS_LOADER select SPL_BLK_FS help diff --git a/common/spl/spl.c b/common/spl/spl.c index 732d90d39e6..3ce5bfeec8b 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -19,6 +19,7 @@ #include <mapmem.h> #include <serial.h> #include <spl.h> +#include <spl_load.h> #include <system-constants.h> #include <asm/global_data.h> #include <asm-generic/gpio.h> @@ -352,6 +353,15 @@ int spl_parse_image_header(struct spl_image_info *spl_image, return 0; } +#if SPL_LOAD_USERS > 1 +int spl_load(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, struct spl_load_info *info, + size_t size, size_t offset) +{ + return _spl_load(spl_image, bootdev, info, size, offset); +} +#endif + __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); @@ -718,8 +728,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) ret = boot_from_devices(&spl_image, spl_boot_list, ARRAY_SIZE(spl_boot_list)); if (ret) { - if (CONFIG_IS_ENABLED(SHOW_ERRORS) && - CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)) + if (CONFIG_IS_ENABLED(SHOW_ERRORS)) printf(SPL_TPL_PROMPT "failed to boot from all boot devices (err=%d)\n", ret); else diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c index 63825d620d1..04eac6f306b 100644 --- a/common/spl/spl_blk_fs.c +++ b/common/spl/spl_blk_fs.c @@ -7,12 +7,15 @@ #include <common.h> #include <spl.h> +#include <spl_load.h> #include <image.h> #include <fs.h> +#include <asm/cache.h> #include <asm/io.h> struct blk_dev { const char *ifname; + const char *filename; char dev_part_str[8]; }; @@ -30,11 +33,11 @@ static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, return ret; } - ret = fs_read(load->filename, virt_to_phys(buf), file_offset, size, + ret = fs_read(dev->filename, virt_to_phys(buf), file_offset, size, &actlen); if (ret < 0) { printf("spl: error reading image %s. Err - %d\n", - load->filename, ret); + dev->filename, ret); return ret; } @@ -46,10 +49,10 @@ int spl_blk_load_image(struct spl_image_info *spl_image, enum uclass_id uclass_id, int devnum, int partnum) { const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME; - struct legacy_img_hdr *header; struct blk_desc *blk_desc; - loff_t actlen, filesize; + loff_t filesize; struct blk_dev dev; + struct spl_load_info load; int ret; blk_desc = blk_get_devnum_by_uclass_id(uclass_id, devnum); @@ -59,8 +62,8 @@ int spl_blk_load_image(struct spl_image_info *spl_image, } blk_show_device(uclass_id, devnum); - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + dev.filename = filename; dev.ifname = blk_get_uclass_name(uclass_id); snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%x:%x", devnum, partnum); @@ -68,63 +71,21 @@ int spl_blk_load_image(struct spl_image_info *spl_image, if (ret) { printf("spl: unable to set blk_dev %s %s. Err - %d\n", dev.ifname, dev.dev_part_str, ret); - goto out; - } - - ret = fs_read(filename, virt_to_phys(header), 0, - sizeof(struct legacy_img_hdr), &actlen); - if (ret) { - printf("spl: unable to read file %s. Err - %d\n", filename, - ret); - goto out; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.read = spl_fit_read; - load.bl_len = 1; - load.filename = (void *)filename; - load.priv = &dev; - - return spl_load_simple_fit(spl_image, &load, 0, header); - } - - ret = spl_parse_image_header(spl_image, bootdev, header); - if (ret) { - printf("spl: unable to parse image header. Err - %d\n", - ret); - goto out; - } - - ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); - if (ret) { - printf("spl: unable to set blk_dev %s %s. Err - %d\n", - dev.ifname, dev.dev_part_str, ret); - goto out; + return ret; } ret = fs_size(filename, &filesize); if (ret) { printf("spl: unable to get file size: %s. Err - %d\n", filename, ret); - goto out; - } - - ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); - if (ret) { - printf("spl: unable to set blk_dev %s %s. Err - %d\n", - dev.ifname, dev.dev_part_str, ret); - goto out; + return ret; } - ret = fs_read(filename, (ulong)spl_image->load_addr, 0, filesize, - &actlen); - if (ret) - printf("spl: unable to read file %s. Err - %d\n", - filename, ret); -out: - return ret; + load.read = spl_fit_read; + if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN)) + spl_set_bl_len(&load, ARCH_DMA_MINALIGN); + else + spl_set_bl_len(&load, 1); + load.priv = &dev; + return spl_load(spl_image, bootdev, &load, filesize, 0); } diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index af836ca15b8..2be6f04b02c 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -2,25 +2,35 @@ #include <common.h> #include <env.h> -#include <mapmem.h> #include <part.h> #include <spl.h> +#include <spl_load.h> #include <asm/u-boot.h> #include <ext4fs.h> #include <errno.h> #include <image.h> +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, + ulong size, void *buf) +{ + int ret; + loff_t actlen; + + ret = ext4fs_read(buf, file_offset, size, &actlen); + if (ret) + return ret; + return actlen; +} + int spl_load_image_ext(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct blk_desc *block_dev, int partition, const char *filename) { s32 err; - struct legacy_img_hdr *header; - loff_t filelen, actlen; + loff_t filelen; struct disk_partition part_info = {}; - - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + struct spl_load_info load; if (part_get_info(block_dev, partition, &part_info)) { printf("spl: no partition table found\n"); @@ -29,7 +39,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image, ext4fs_set_blk_dev(block_dev, &part_info); - err = ext4fs_mount(part_info.size); + err = ext4fs_mount(); if (!err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT printf("%s: ext4fs mount err - %d\n", __func__, err); @@ -42,20 +52,10 @@ int spl_load_image_ext(struct spl_image_info *spl_image, puts("spl: ext4fs_open failed\n"); goto end; } - err = ext4fs_read((char *)header, 0, sizeof(struct legacy_img_hdr), &actlen); - if (err < 0) { - puts("spl: ext4fs_read failed\n"); - goto end; - } - - err = spl_parse_image_header(spl_image, bootdev, header); - if (err < 0) { - puts("spl: ext: failed to parse image header\n"); - goto end; - } - err = ext4fs_read(map_sysmem(spl_image->load_addr, filelen), 0, filelen, - &actlen); + spl_set_bl_len(&load, 1); + load.read = spl_fit_read; + err = spl_load(spl_image, bootdev, &load, filelen, 0); end: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT @@ -84,7 +84,7 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image, ext4fs_set_blk_dev(block_dev, &part_info); - err = ext4fs_mount(part_info.size); + err = ext4fs_mount(); if (!err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT printf("%s: ext4fs mount err - %d\n", __func__, err); diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index 014074f85be..a52f9e178e6 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -11,8 +11,8 @@ #include <common.h> #include <env.h> #include <log.h> -#include <mapmem.h> #include <spl.h> +#include <spl_load.h> #include <asm/u-boot.h> #include <fat.h> #include <errno.h> @@ -51,7 +51,7 @@ static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, { loff_t actread; int ret; - char *filename = (char *)load->filename; + char *filename = load->priv; ret = fat_read_file(filename, buf, file_offset, size, &actread); if (ret) @@ -66,59 +66,41 @@ int spl_load_image_fat(struct spl_image_info *spl_image, const char *filename) { int err; - struct legacy_img_hdr *header; + loff_t size; + struct spl_load_info load; err = spl_register_fat_device(block_dev, partition); if (err) goto end; - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); - - err = file_fat_read(filename, header, sizeof(struct legacy_img_hdr)); - if (err <= 0) - goto end; - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) && - image_get_magic(header) == FDT_MAGIC) { - err = file_fat_read(filename, - map_sysmem(CONFIG_SYS_LOAD_ADDR, 0), 0); - if (err <= 0) - goto end; - err = spl_parse_image_header(spl_image, bootdev, - map_sysmem(CONFIG_SYS_LOAD_ADDR, - err)); - if (err == -EAGAIN) - return err; - if (err == 0) - err = 1; - } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.read = spl_fit_read; - load.bl_len = 1; - load.filename = (void *)filename; - load.priv = NULL; - - return spl_load_simple_fit(spl_image, &load, 0, header); - } else { - err = spl_parse_image_header(spl_image, bootdev, header); + /* + * Avoid pulling in this function for other image types since we are + * very short on space on some boards. + */ + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + err = fat_size(filename, &size); if (err) goto end; - - err = file_fat_read(filename, map_sysmem(spl_image->load_addr, - spl_image->size), 0); + } else { + size = 0; } + load.read = spl_fit_read; + if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN)) + spl_set_bl_len(&load, ARCH_DMA_MINALIGN); + else + spl_set_bl_len(&load, 1); + load.priv = (void *)filename; + err = spl_load(spl_image, bootdev, &load, size, 0); + end: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - if (err <= 0) + if (err < 0) printf("%s: error reading image %s, err - %d\n", __func__, filename, err); #endif - return (err <= 0); + return err; } #if CONFIG_IS_ENABLED(OS_BOOT) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 70d8d5942d9..872df0c0fe8 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -14,7 +14,6 @@ #include <mapmem.h> #include <spl.h> #include <sysinfo.h> -#include <asm/cache.h> #include <asm/global_data.h> #include <asm/io.h> #include <linux/libfdt.h> @@ -172,29 +171,12 @@ static int spl_fit_get_image_node(const struct spl_fit_info *ctx, static int get_aligned_image_offset(struct spl_load_info *info, int offset) { - /* - * If it is a FS read, get the first address before offset which is - * aligned to ARCH_DMA_MINALIGN. If it is raw read return the - * block number to which offset belongs. - */ - if (info->filename) - return offset & ~(ARCH_DMA_MINALIGN - 1); - - return offset / info->bl_len; + return ALIGN_DOWN(offset, spl_get_bl_len(info)); } static int get_aligned_image_overhead(struct spl_load_info *info, int offset) { - /* - * If it is a FS read, get the difference between the offset and - * the first address before offset which is aligned to - * ARCH_DMA_MINALIGN. If it is raw read return the offset within the - * block. - */ - if (info->filename) - return offset & (ARCH_DMA_MINALIGN - 1); - - return offset % info->bl_len; + return offset & (spl_get_bl_len(info) - 1); } static int get_aligned_image_size(struct spl_load_info *info, int data_size, @@ -202,10 +184,7 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, { data_size = data_size + get_aligned_image_overhead(info, offset); - if (info->filename) - return data_size; - - return (data_size + info->bl_len - 1) / info->bl_len; + return ALIGN(data_size, spl_get_bl_len(info)); } /** @@ -222,7 +201,7 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, * * Return: 0 on success or a negative error number. */ -static int load_simple_fit(struct spl_load_info *info, ulong sector, +static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, const struct spl_fit_info *ctx, int node, struct spl_image_info *image_info) { @@ -234,7 +213,6 @@ static int load_simple_fit(struct spl_load_info *info, ulong sector, void *load_ptr; void *src; ulong overhead; - int nr_sectors; uint8_t image_comp = -1, type = -1; const void *data; const void *fit = ctx->fit; @@ -291,11 +269,12 @@ static int load_simple_fit(struct spl_load_info *info, ulong sector, length = len; overhead = get_aligned_image_overhead(info, offset); - nr_sectors = get_aligned_image_size(info, length, offset); + size = get_aligned_image_size(info, length, offset); if (info->read(info, - sector + get_aligned_image_offset(info, offset), - nr_sectors, src_ptr) != nr_sectors) + fit_offset + + get_aligned_image_offset(info, offset), size, + src_ptr) < length) return -EIO; debug("External data: dst=%p, offset=%x, size=%lx\n", @@ -380,7 +359,7 @@ __weak int board_spl_fit_append_fdt_skip(const char *name) } static int spl_fit_append_fdt(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector, + struct spl_load_info *info, ulong offset, const struct spl_fit_info *ctx) { struct spl_image_info image_info; @@ -414,7 +393,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, spl_image->fdt_addr = map_sysmem(image_info.load_addr, size); memcpy(spl_image->fdt_addr, gd->fdt_blob, size); } else { - ret = load_simple_fit(info, sector, ctx, node, &image_info); + ret = load_simple_fit(info, offset, ctx, node, &image_info); if (ret < 0) return ret; @@ -465,7 +444,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, __func__); } image_info.load_addr = (ulong)tmpbuffer; - ret = load_simple_fit(info, sector, ctx, node, + ret = load_simple_fit(info, offset, ctx, node, &image_info); if (ret < 0) break; @@ -642,7 +621,7 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node, } static int spl_fit_load_fpga(struct spl_fit_info *ctx, - struct spl_load_info *info, ulong sector) + struct spl_load_info *info, ulong offset) { int node, ret; @@ -657,7 +636,7 @@ static int spl_fit_load_fpga(struct spl_fit_info *ctx, warn_deprecated("'fpga' property in config node. Use 'loadables'"); /* Load the image and set up the fpga_image structure */ - ret = load_simple_fit(info, sector, ctx, node, &fpga_image); + ret = load_simple_fit(info, offset, ctx, node, &fpga_image); if (ret) { printf("%s: Cannot load the FPGA: %i\n", __func__, ret); return ret; @@ -667,11 +646,10 @@ static int spl_fit_load_fpga(struct spl_fit_info *ctx, } static int spl_simple_fit_read(struct spl_fit_info *ctx, - struct spl_load_info *info, ulong sector, + struct spl_load_info *info, ulong offset, const void *fit_header) { unsigned long count, size; - int sectors; void *buf; /* @@ -690,13 +668,13 @@ static int spl_simple_fit_read(struct spl_fit_info *ctx, * For FIT with data embedded, data is loaded as part of FIT image. * For FIT with external data, data is not loaded in this step. */ - sectors = get_aligned_image_size(info, size, 0); - buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len); + size = get_aligned_image_size(info, size, 0); + buf = board_spl_fit_buffer_addr(size, size, 1); - count = info->read(info, sector, sectors, buf); + count = info->read(info, offset, size, buf); ctx->fit = buf; - debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n", - sector, sectors, buf, count, size); + debug("fit read offset %lx, size=%lu, dst=%p, count=%lu\n", + offset, size, buf, count); return (count == 0) ? -EIO : 0; } @@ -728,7 +706,7 @@ static int spl_simple_fit_parse(struct spl_fit_info *ctx) } int spl_load_simple_fit(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector, void *fit) + struct spl_load_info *info, ulong offset, void *fit) { struct spl_image_info image_info; struct spl_fit_info ctx; @@ -737,7 +715,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, int index = 0; int firmware_node; - ret = spl_simple_fit_read(&ctx, info, sector, fit); + ret = spl_simple_fit_read(&ctx, info, offset, fit); if (ret < 0) return ret; @@ -752,7 +730,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, return ret; if (IS_ENABLED(CONFIG_SPL_FPGA)) - spl_fit_load_fpga(&ctx, info, sector); + spl_fit_load_fpga(&ctx, info, offset); /* * Find the U-Boot image using the following search order: @@ -782,7 +760,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, } /* Load the image and set up the spl_image structure */ - ret = load_simple_fit(info, sector, &ctx, node, spl_image); + ret = load_simple_fit(info, offset, &ctx, node, spl_image); if (ret) return ret; @@ -800,7 +778,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, * We allow this to fail, as the U-Boot image might embed its FDT. */ if (os_takes_devicetree(spl_image->os)) { - ret = spl_fit_append_fdt(spl_image, info, sector, &ctx); + ret = spl_fit_append_fdt(spl_image, info, offset, &ctx); if (ret < 0 && spl_image->os != IH_OS_U_BOOT) return ret; } @@ -823,7 +801,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, continue; image_info.load_addr = 0; - ret = load_simple_fit(info, sector, &ctx, node, &image_info); + ret = load_simple_fit(info, offset, &ctx, node, &image_info); if (ret < 0) { printf("%s: can't load image loadables index %d (ret = %d)\n", __func__, index, ret); @@ -837,7 +815,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, debug("Loadable is %s\n", genimg_get_os_name(os_type)); if (os_takes_devicetree(os_type)) { - spl_fit_append_fdt(&image_info, info, sector, &ctx); + spl_fit_append_fdt(&image_info, info, offset, &ctx); spl_image->fdt_addr = image_info.fdt_addr; } diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c index 127802f5cb7..b4ea9241d68 100644 --- a/common/spl/spl_imx_container.c +++ b/common/spl/spl_imx_container.c @@ -19,11 +19,10 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, struct spl_load_info *info, struct container_hdr *container, int image_index, - u32 container_sector) + ulong container_offset) { struct boot_img_t *images; - ulong sector; - u32 sectors; + ulong offset, overhead, size; if (image_index > container->num_images) { debug("Invalid image number\n"); @@ -33,22 +32,21 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, images = (struct boot_img_t *)((u8 *)container + sizeof(struct container_hdr)); - if (images[image_index].offset % info->bl_len) { + if (!IS_ALIGNED(images[image_index].offset, spl_get_bl_len(info))) { printf("%s: image%d offset not aligned to %u\n", - __func__, image_index, info->bl_len); + __func__, image_index, spl_get_bl_len(info)); return NULL; } - sectors = roundup(images[image_index].size, info->bl_len) / - info->bl_len; - sector = images[image_index].offset / info->bl_len + - container_sector; + size = ALIGN(images[image_index].size, spl_get_bl_len(info)); + offset = images[image_index].offset + container_offset; - debug("%s: container: %p sector: %lu sectors: %u\n", __func__, - container, sector, sectors); - if (info->read(info, sector, sectors, - map_sysmem(images[image_index].dst, - images[image_index].size)) != sectors) { + debug("%s: container: %p offset: %lu size: %lu\n", __func__, + container, offset, size); + if (info->read(info, offset, size, + map_sysmem(images[image_index].dst - overhead, + images[image_index].size)) < + images[image_index].size) { printf("%s wrong\n", __func__); return NULL; } @@ -62,15 +60,13 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, } static int read_auth_container(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector) + struct spl_load_info *info, ulong offset) { struct container_hdr *container = NULL; u16 length; - u32 sectors; int i, size, ret = 0; - size = roundup(CONTAINER_HDR_ALIGNMENT, info->bl_len); - sectors = size / info->bl_len; + size = ALIGN(CONTAINER_HDR_ALIGNMENT, spl_get_bl_len(info)); /* * It will not override the ATF code, so safe to use it here, @@ -80,9 +76,10 @@ static int read_auth_container(struct spl_image_info *spl_image, if (!container) return -ENOMEM; - debug("%s: container: %p sector: %lu sectors: %u\n", __func__, - container, sector, sectors); - if (info->read(info, sector, sectors, container) != sectors) { + debug("%s: container: %p offset: %lu size: %u\n", __func__, + container, offset, size); + if (info->read(info, offset, size, container) < + CONTAINER_HDR_ALIGNMENT) { ret = -EIO; goto end; } @@ -103,18 +100,16 @@ static int read_auth_container(struct spl_image_info *spl_image, debug("Container length %u\n", length); if (length > CONTAINER_HDR_ALIGNMENT) { - size = roundup(length, info->bl_len); - sectors = size / info->bl_len; + size = ALIGN(length, spl_get_bl_len(info)); free(container); container = malloc(size); if (!container) return -ENOMEM; - debug("%s: container: %p sector: %lu sectors: %u\n", - __func__, container, sector, sectors); - if (info->read(info, sector, sectors, container) != - sectors) { + debug("%s: container: %p offset: %lu size: %u\n", + __func__, container, offset, size); + if (info->read(info, offset, size, container) < length) { ret = -EIO; goto end; } @@ -129,7 +124,7 @@ static int read_auth_container(struct spl_image_info *spl_image, for (i = 0; i < container->num_images; i++) { struct boot_img_t *image = read_auth_image(spl_image, info, container, i, - sector); + offset); if (!image) { ret = -EINVAL; @@ -154,7 +149,7 @@ end: } int spl_load_imx_container(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector) + struct spl_load_info *info, ulong offset) { - return read_auth_container(spl_image, info, sector); + return read_auth_container(spl_image, info, offset); } diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 51656fb9617..08687ca8f6c 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -82,89 +82,39 @@ int spl_parse_legacy_header(struct spl_image_info *spl_image, return 0; } -/* - * This function is added explicitly to avoid code size increase, when - * no compression method is enabled. The compiler will optimize the - * following switch/case statement in spl_load_legacy_img() away due to - * Dead Code Elimination. - */ -static inline int spl_image_get_comp(const struct legacy_img_hdr *hdr) -{ - if (IS_ENABLED(CONFIG_SPL_LZMA)) - return image_get_comp(hdr); - - return IH_COMP_NONE; -} - -int spl_load_legacy_img(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct spl_load_info *load, ulong offset, - struct legacy_img_hdr *hdr) +int spl_load_legacy_lzma(struct spl_image_info *spl_image, + struct spl_load_info *load, ulong offset) { - __maybe_unused SizeT lzma_len; - __maybe_unused void *src; - ulong dataptr; + SizeT lzma_len = LZMA_LEN; + void *src; + ulong dataptr, overhead, size; int ret; - /* - * If the payload is compressed, the decompressed data should be - * directly write to its load address. - */ - if (spl_image_get_comp(hdr) != IH_COMP_NONE) - spl_image->flags |= SPL_COPY_PAYLOAD_ONLY; + /* dataptr points to compressed payload */ + dataptr = ALIGN_DOWN(sizeof(struct legacy_img_hdr), + spl_get_bl_len(load)); + overhead = sizeof(struct legacy_img_hdr) - dataptr; + size = ALIGN(spl_image->size + overhead, spl_get_bl_len(load)); + dataptr += offset; + + debug("LZMA: Decompressing %08lx to %08lx\n", + dataptr, spl_image->load_addr); + src = malloc(size); + if (!src) { + printf("Unable to allocate %d bytes for LZMA\n", + spl_image->size); + return -ENOMEM; + } - ret = spl_parse_image_header(spl_image, bootdev, hdr); - if (ret) + load->read(load, dataptr, size, src); + ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr, + spl_image->size), &lzma_len, + src + overhead, spl_image->size); + if (ret) { + printf("LZMA decompression error: %d\n", ret); return ret; - - /* Read image */ - switch (spl_image_get_comp(hdr)) { - case IH_COMP_NONE: - dataptr = offset; - - /* - * Image header will be skipped only if SPL_COPY_PAYLOAD_ONLY - * is set - */ - if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) - dataptr += sizeof(*hdr); - - load->read(load, dataptr, spl_image->size, - map_sysmem(spl_image->load_addr, spl_image->size)); - break; - - case IH_COMP_LZMA: - lzma_len = LZMA_LEN; - - /* dataptr points to compressed payload */ - dataptr = offset + sizeof(*hdr); - - debug("LZMA: Decompressing %08lx to %08lx\n", - dataptr, spl_image->load_addr); - src = malloc(spl_image->size); - if (!src) { - printf("Unable to allocate %d bytes for LZMA\n", - spl_image->size); - return -ENOMEM; - } - - load->read(load, dataptr, spl_image->size, src); - ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr, - spl_image->size), - &lzma_len, src, spl_image->size); - if (ret) { - printf("LZMA decompression error: %d\n", ret); - return ret; - } - - spl_image->size = lzma_len; - break; - - default: - debug("Compression method %s is not supported\n", - genimg_get_comp_short_name(image_get_comp(hdr))); - return -EINVAL; } + spl_image->size = lzma_len; return 0; } diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 82689da1401..3d032bb27ce 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -8,9 +8,9 @@ #include <common.h> #include <dm.h> #include <log.h> -#include <mapmem.h> #include <part.h> #include <spl.h> +#include <spl_load.h> #include <linux/compiler.h> #include <errno.h> #include <asm/u-boot.h> @@ -19,55 +19,14 @@ #include <image.h> #include <imx_container.h> -static int mmc_load_legacy(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc, - ulong sector, struct legacy_img_hdr *header) +static ulong h_spl_load_read(struct spl_load_info *load, ulong off, + ulong size, void *buf) { - u32 image_offset_sectors; - u32 image_size_sectors; - unsigned long count; - u32 image_offset; - int ret; - - ret = spl_parse_image_header(spl_image, bootdev, header); - if (ret) - return ret; - - /* convert offset to sectors - round down */ - image_offset_sectors = spl_image->offset / mmc->read_bl_len; - /* calculate remaining offset */ - image_offset = spl_image->offset % mmc->read_bl_len; + struct blk_desc *bd = load->priv; + lbaint_t sector = off >> bd->log2blksz; + lbaint_t count = size >> bd->log2blksz; - /* convert size to sectors - round up */ - image_size_sectors = (spl_image->size + mmc->read_bl_len - 1) / - mmc->read_bl_len; - - /* Read the header too to avoid extra memcpy */ - count = blk_dread(mmc_get_blk_desc(mmc), - sector + image_offset_sectors, - image_size_sectors, - map_sysmem(spl_image->load_addr, - image_size_sectors * mmc->read_bl_len)); - debug("read %x sectors to %lx\n", image_size_sectors, - spl_image->load_addr); - if (count != image_size_sectors) - return -EIO; - - if (image_offset) - memmove((void *)(ulong)spl_image->load_addr, - (void *)(ulong)spl_image->load_addr + image_offset, - spl_image->size); - - return 0; -} - -static ulong h_spl_load_read(struct spl_load_info *load, ulong sector, - ulong count, void *buf) -{ - struct mmc *mmc = load->dev; - - return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf); + return blk_dread(bd, sector, count, buf) << bd->log2blksz; } static __maybe_unused unsigned long spl_mmc_raw_uboot_offset(int part) @@ -85,48 +44,14 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct mmc *mmc, unsigned long sector) { - unsigned long count; - struct legacy_img_hdr *header; + int ret; struct blk_desc *bd = mmc_get_blk_desc(mmc); - int ret = 0; - - header = spl_get_load_buffer(-sizeof(*header), bd->blksz); - - /* read image header to find the image size & load address */ - count = blk_dread(bd, sector, 1, header); - debug("hdr read sector %lx, count=%lu\n", sector, count); - if (count == 0) { - ret = -EIO; - goto end; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.dev = mmc; - load.priv = NULL; - load.filename = NULL; - load.bl_len = mmc->read_bl_len; - load.read = h_spl_load_read; - ret = spl_load_simple_fit(spl_image, &load, sector, header); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && - valid_container_hdr((void *)header)) { - struct spl_load_info load; - - load.dev = mmc; - load.priv = NULL; - load.filename = NULL; - load.bl_len = mmc->read_bl_len; - load.read = h_spl_load_read; - - ret = spl_load_imx_container(spl_image, &load, sector); - } else { - ret = mmc_load_legacy(spl_image, bootdev, mmc, sector, header); - } + struct spl_load_info load; -end: + load.priv = bd; + spl_set_bl_len(&load, bd->blksz); + load.read = h_spl_load_read; + ret = spl_load(spl_image, bootdev, &load, 0, sector << bd->log2blksz); if (ret) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("mmc_load_image_raw_sector: mmc block read error\n"); diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 07916bedbb9..3b0a1524238 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -10,7 +10,9 @@ #include <imx_container.h> #include <log.h> #include <spl.h> +#include <spl_load.h> #include <asm/io.h> +#include <mapmem.h> #include <nand.h> #include <linux/libfdt_env.h> #include <fdt.h> @@ -32,7 +34,8 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, nand_spl_load_image(spl_nand_get_uboot_raw_page(), CFG_SYS_NAND_U_BOOT_SIZE, - (void *)CFG_SYS_NAND_U_BOOT_DST); + map_sysmem(CFG_SYS_NAND_U_BOOT_DST, + CFG_SYS_NAND_U_BOOT_SIZE)); spl_set_header_raw_uboot(spl_image); nand_deselect(); @@ -40,104 +43,45 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, } #else -static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs, - ulong size, void *dst) +__weak u32 nand_spl_adjust_offset(u32 sector, u32 offs) { - int err; - ulong sector; - - sector = *(int *)load->priv; - offs *= load->bl_len; - size *= load->bl_len; - offs = sector + nand_spl_adjust_offset(sector, offs - sector); - err = nand_spl_load_image(offs, size, dst); - if (err) - return 0; - - return size / load->bl_len; + return offs; } -static ulong spl_nand_legacy_read(struct spl_load_info *load, ulong offs, - ulong size, void *dst) +static ulong spl_nand_read(struct spl_load_info *load, ulong offs, ulong size, + void *dst) { int err; + ulong sector; debug("%s: offs %lx, size %lx, dst %p\n", __func__, offs, size, dst); + sector = *(int *)load->priv; + offs = sector + nand_spl_adjust_offset(sector, offs - sector); err = nand_spl_load_image(offs, size, dst); + spl_set_bl_len(load, nand_page_size()); if (err) return 0; return size; } -struct mtd_info * __weak nand_get_mtd(void) -{ - return NULL; -} - static int spl_nand_load_element(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - int offset, struct legacy_img_hdr *header) + struct spl_boot_device *bootdev, int offset) { - struct mtd_info *mtd = nand_get_mtd(); - int bl_len = mtd ? mtd->writesize : 1; - int err; + struct spl_load_info load; - err = nand_spl_load_image(offset, sizeof(*header), (void *)header); - if (err) - return err; - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.dev = NULL; - load.priv = &offset; - load.filename = NULL; - load.bl_len = bl_len; - load.read = spl_nand_fit_read; - return spl_load_simple_fit(spl_image, &load, offset / bl_len, header); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && - valid_container_hdr((void *)header)) { - struct spl_load_info load; - - load.dev = NULL; - load.priv = NULL; - load.filename = NULL; - load.bl_len = bl_len; - load.read = spl_nand_fit_read; - return spl_load_imx_container(spl_image, &load, offset / bl_len); - } else if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT) && - image_get_magic(header) == IH_MAGIC) { - struct spl_load_info load; - - debug("Found legacy image\n"); - load.dev = NULL; - load.priv = NULL; - load.filename = NULL; - load.bl_len = 1; - load.read = spl_nand_legacy_read; - - return spl_load_legacy_img(spl_image, bootdev, &load, offset, header); - } else { - err = spl_parse_image_header(spl_image, bootdev, header); - if (err) - return err; - return nand_spl_load_image(offset, spl_image->size, - (void *)(ulong)spl_image->load_addr); - } + load.priv = &offset; + spl_set_bl_len(&load, 1); + load.read = spl_nand_read; + return spl_load(spl_image, bootdev, &load, 0, offset); } static int spl_nand_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int err; - struct legacy_img_hdr *header; - int *src __attribute__((unused)); - int *dst __attribute__((unused)); #ifdef CONFIG_SPL_NAND_SOFTECC debug("spl: nand - using sw ecc\n"); @@ -146,10 +90,12 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, #endif nand_init(); - header = spl_get_load_buffer(0, sizeof(*header)); - #if CONFIG_IS_ENABLED(OS_BOOT) if (!spl_start_uboot()) { + int *src, *dst; + struct legacy_img_hdr *header = + spl_get_load_buffer(0, sizeof(*header)); + /* * load parameter image * load to temp position since nand_spl_load_image reads @@ -192,20 +138,18 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, } #endif #ifdef CONFIG_NAND_ENV_DST - spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET, header); + spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET); #ifdef CONFIG_ENV_OFFSET_REDUND - spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET_REDUND, header); + spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET_REDUND); #endif #endif /* Load u-boot */ - err = spl_nand_load_element(spl_image, bootdev, spl_nand_get_uboot_raw_page(), - header); + err = spl_nand_load_element(spl_image, bootdev, spl_nand_get_uboot_raw_page()); #ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND #if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND if (err) err = spl_nand_load_element(spl_image, bootdev, - CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND, - header); + CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND); #endif #endif nand_deselect(); diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index f01d4df8bc6..898f9df705a 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -11,8 +11,8 @@ #include <errno.h> #include <image.h> #include <log.h> -#include <mapmem.h> #include <spl.h> +#include <spl_load.h> #include <net.h> #include <linux/libfdt.h> @@ -29,8 +29,7 @@ static ulong spl_net_load_read(struct spl_load_info *load, ulong sector, static int spl_net_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { - struct legacy_img_hdr *header = map_sysmem(image_load_addr, - sizeof(*header)); + struct spl_load_info load; int rv; env_init(); @@ -49,27 +48,9 @@ static int spl_net_load_image(struct spl_image_info *spl_image, return rv; } - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.bl_len = 1; - load.read = spl_net_load_read; - rv = spl_load_simple_fit(spl_image, &load, 0, header); - } else { - debug("Legacy image\n"); - - rv = spl_parse_image_header(spl_image, bootdev, header); - if (rv) - return rv; - - memcpy(map_sysmem(spl_image->load_addr, spl_image->size), - map_sysmem(image_load_addr, spl_image->size), - spl_image->size); - } - - return rv; + spl_set_bl_len(&load, 1); + load.read = spl_net_load_read; + return spl_load(spl_image, bootdev, &load, 0, 0); } #endif diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 236b0718283..70745114efe 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -7,8 +7,8 @@ #include <image.h> #include <imx_container.h> #include <log.h> -#include <mapmem.h> #include <spl.h> +#include <spl_load.h> static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) @@ -28,8 +28,7 @@ unsigned long __weak spl_nor_get_uboot_base(void) static int spl_nor_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { - struct legacy_img_hdr *header; - __maybe_unused struct spl_load_info load; + struct spl_load_info load; /* * Loading of the payload to SDRAM is done with skipping of @@ -43,13 +42,14 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, * Load Linux from its location in NOR flash to its defined * location in SDRAM */ - header = (void *)CONFIG_SYS_OS_BASE; + const struct legacy_img_hdr *header = + (const struct legacy_img_hdr *)CONFIG_SYS_OS_BASE; #ifdef CONFIG_SPL_LOAD_FIT if (image_get_magic(header) == FDT_MAGIC) { int ret; debug("Found FIT\n"); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_nor_load_read; ret = spl_load_simple_fit(spl_image, &load, @@ -93,34 +93,8 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, * Load real U-Boot from its location in NOR flash to its * defined location in SDRAM */ - header = map_sysmem(spl_nor_get_uboot_base(), sizeof(*header)); -#ifdef CONFIG_SPL_LOAD_FIT - if (image_get_magic(header) == FDT_MAGIC) { - debug("Found FIT format U-Boot\n"); - load.bl_len = 1; - load.read = spl_nor_load_read; - return spl_load_simple_fit(spl_image, &load, - spl_nor_get_uboot_base(), - (void *)header); - } -#endif - if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && - valid_container_hdr((void *)header)) { - load.bl_len = 1; - load.read = spl_nor_load_read; - return spl_load_imx_container(spl_image, &load, - spl_nor_get_uboot_base()); - } - - /* Legacy image handling */ - if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT)) { - load.bl_len = 1; - load.read = spl_nor_load_read; - return spl_load_legacy_img(spl_image, bootdev, &load, - spl_nor_get_uboot_base(), - header); - } - - return -EINVAL; + spl_set_bl_len(&load, 1); + load.read = spl_nor_load_read; + return spl_load(spl_image, bootdev, &load, 0, spl_nor_get_uboot_base()); } SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image); diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 4158ed1c32d..8aeda237be1 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -70,7 +70,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_ram_load_read; ret = spl_load_simple_fit(spl_image, &load, 0, header); } else { diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c index f7dd289286d..941fa911040 100644 --- a/common/spl/spl_semihosting.c +++ b/common/spl/spl_semihosting.c @@ -8,34 +8,19 @@ #include <log.h> #include <semihosting.h> #include <spl.h> - -static int smh_read_full(long fd, void *memp, size_t len) -{ - long read; - - read = smh_read(fd, memp, len); - if (read < 0) - return read; - if (read != len) - return -EIO; - return 0; -} +#include <spl_load.h> static ulong smh_fit_read(struct spl_load_info *load, ulong file_offset, ulong size, void *buf) { - long fd; + long fd = *(long *)load->priv; ulong ret; - fd = smh_open(load->filename, MODE_READ | MODE_BINARY); - if (fd < 0) { - log_debug("could not open %s: %ld\n", load->filename, fd); + if (smh_seek(fd, file_offset)) return 0; - } - ret = smh_read(fd, buf, size); - smh_close(fd); - return ret; + ret = smh_read(fd, buf, size); + return ret < 0 ? 0 : ret; } static int spl_smh_load_image(struct spl_image_info *spl_image, @@ -44,8 +29,7 @@ static int spl_smh_load_image(struct spl_image_info *spl_image, const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME; int ret; long fd, len; - struct legacy_img_hdr *header = - spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + struct spl_load_info load; fd = smh_open(filename, MODE_READ | MODE_BINARY); if (fd < 0) { @@ -60,39 +44,10 @@ static int spl_smh_load_image(struct spl_image_info *spl_image, } len = ret; - ret = smh_read_full(fd, header, sizeof(struct legacy_img_hdr)); - if (ret) { - log_debug("could not read image header: %d\n", ret); - goto out; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.read = smh_fit_read; - load.bl_len = 1; - load.filename = filename; - load.priv = NULL; - smh_close(fd); - - return spl_load_simple_fit(spl_image, &load, 0, header); - } - - ret = spl_parse_image_header(spl_image, bootdev, header); - if (ret) { - log_debug("failed to parse image header: %d\n", ret); - goto out; - } - - ret = smh_seek(fd, 0); - if (ret) { - log_debug("could not seek to start of image: %d\n", ret); - goto out; - } - - ret = smh_read_full(fd, (void *)spl_image->load_addr, len); + load.read = smh_fit_read; + spl_set_bl_len(&load, 1); + load.priv = &fd; + ret = spl_load(spl_image, bootdev, &load, len, 0); if (ret) log_debug("could not read %s: %d\n", filename, ret); out: diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 3ac4b1b5091..89de73c726c 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -12,54 +12,19 @@ #include <image.h> #include <imx_container.h> #include <log.h> -#include <mapmem.h> #include <spi.h> #include <spi_flash.h> #include <errno.h> #include <spl.h> +#include <spl_load.h> #include <asm/global_data.h> #include <asm/io.h> #include <dm/ofnode.h> -#if CONFIG_IS_ENABLED(OS_BOOT) -/* - * Load the kernel, check for a valid header we can parse, and if found load - * the kernel and then device tree. - */ -static int spi_load_image_os(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct spi_flash *flash, - struct legacy_img_hdr *header) -{ - int err; - - /* Read for a header, parse or error out. */ - spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, sizeof(*header), - (void *)header); - - if (image_get_magic(header) != IH_MAGIC) - return -1; - - err = spl_parse_image_header(spl_image, bootdev, header); - if (err) - return err; - - spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, - spl_image->size, (void *)spl_image->load_addr); - - /* Read device tree. */ - spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS, - CFG_SYS_SPI_ARGS_SIZE, - (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR); - - return 0; -} -#endif - static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { - struct spi_flash *flash = load->dev; + struct spi_flash *flash = load->priv; ulong ret; ret = spi_flash_read(flash, sector, count, buf); @@ -95,9 +60,9 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, int err = 0; unsigned int payload_offs; struct spi_flash *flash; - struct legacy_img_hdr *header; unsigned int sf_bus = spl_spi_boot_bus(); unsigned int sf_cs = spl_spi_boot_cs(); + struct spl_load_info load; /* * Load U-Boot image from SPI flash into RAM @@ -112,81 +77,32 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, return -ENODEV; } - payload_offs = spl_spi_get_uboot_offs(flash); + load.priv = flash; + spl_set_bl_len(&load, 1); + load.read = spl_spi_fit_read; - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); +#if CONFIG_IS_ENABLED(OS_BOOT) + if (spl_start_uboot()) { + int err = spl_load(spl_image, bootdev, &load, 0, + CFG_SYS_SPI_KERNEL_OFFS); + + if (!err) + /* Read device tree. */ + return spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS, + CFG_SYS_SPI_ARGS_SIZE, + (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR); + } +#endif + payload_offs = spl_spi_get_uboot_offs(flash); if (CONFIG_IS_ENABLED(OF_REAL)) { payload_offs = ofnode_conf_read_int("u-boot,spl-payload-offset", payload_offs); } -#if CONFIG_IS_ENABLED(OS_BOOT) - if (spl_start_uboot() || spi_load_image_os(spl_image, bootdev, flash, header)) -#endif - { - /* Load u-boot, mkimage header is 64 bytes. */ - err = spi_flash_read(flash, payload_offs, sizeof(*header), - (void *)header); - if (err) { - debug("%s: Failed to read from SPI flash (err=%d)\n", - __func__, err); - return err; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) && - image_get_magic(header) == FDT_MAGIC) { - u32 size = roundup(fdt_totalsize(header), 4); - - err = spi_flash_read(flash, payload_offs, - size, - map_sysmem(CONFIG_SYS_LOAD_ADDR, - size)); - if (err) - return err; - err = spl_parse_image_header(spl_image, bootdev, - phys_to_virt(CONFIG_SYS_LOAD_ADDR)); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.dev = flash; - load.priv = NULL; - load.filename = NULL; - load.bl_len = 1; - load.read = spl_spi_fit_read; - err = spl_load_simple_fit(spl_image, &load, - payload_offs, - header); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && - valid_container_hdr((void *)header)) { - struct spl_load_info load; - - load.dev = flash; - load.priv = NULL; - load.filename = NULL; - load.bl_len = 1; - load.read = spl_spi_fit_read; - - err = spl_load_imx_container(spl_image, &load, - payload_offs); - } else { - err = spl_parse_image_header(spl_image, bootdev, header); - if (err) - return err; - err = spi_flash_read(flash, payload_offs + spl_image->offset, - spl_image->size, - map_sysmem(spl_image->load_addr, - spl_image->size)); - } - if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) { - err = spi_nor_remove(flash); - if (err) - return err; - } - } - + err = spl_load(spl_image, bootdev, &load, 0, payload_offs); + if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) + err = spi_nor_remove(flash); return err; } /* Use priorty 1 so that boards can override this */ diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 038b4438457..1faaa2c938d 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -134,10 +134,8 @@ int spl_ymodem_load_image(struct spl_image_info *spl_image, struct ymodem_fit_info info; debug("Found FIT\n"); - load.dev = NULL; load.priv = (void *)&info; - load.filename = NULL; - load.bl_len = 1; + spl_set_bl_len(&load, 1); info.buf = buf; info.image_read = BUF_SIZE; load.read = ymodem_read_fit; diff --git a/common/stackprot.c b/common/stackprot.c index d5b70616655..6495951a773 100644 --- a/common/stackprot.c +++ b/common/stackprot.c @@ -18,3 +18,8 @@ void __stack_chk_fail(void) panic("Stack smashing detected in function:\n%p relocated from %p", ra, ra - gd->reloc_off); } + +void __stack_chk_fail_local(void) +{ + __stack_chk_fail(); +} diff --git a/common/version.c b/common/version.c new file mode 100644 index 00000000000..6e27bb80e39 --- /dev/null +++ b/common/version.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include <timestamp.h> +#include <version.h> +#include <version_string.h> + +#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \ + U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING + +const char version_string[] = U_BOOT_VERSION_STRING; +const unsigned short version_num = U_BOOT_VERSION_NUM; +const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH; diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 16993ef5386..0599ae217e6 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y @@ -67,7 +67,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index f048e60f7f3..5d38dad35bb 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -26,7 +26,7 @@ CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_ETH=y # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_MUSB_NEW=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y @@ -84,7 +84,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 9866246aa51..fff5265e56a 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -13,6 +13,7 @@ CONFIG_CLOCK_SYNTHESIZER=y # CONFIG_OF_LIBFDT_OVERLAY is not set # CONFIG_SPL_MMC is not set CONFIG_SPL=y +# CONFIG_SPL_FS_FAT is not set CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_TIMESTAMP=y @@ -27,8 +28,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 01d848ceede..5369e46bc1b 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -99,7 +99,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0x100 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index b961b6c41f0..ea46e58be2d 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -27,7 +27,7 @@ CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_ENV_SUPPORT is not set # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index b5d8eac9f3d..7886557c8da 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -29,7 +29,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_ENV_SUPPORT is not set # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 4dd6366ef67..e2c5b70c405 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -24,7 +24,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y @@ -85,7 +85,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_MTD_UBI_FASTMAP=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 9ba376feda8..fb61dd71c69 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -28,7 +28,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 0a83ac9378c..a96936c92d2 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -26,7 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y @@ -75,7 +75,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 6571afd345e..d5ce2995548 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_ETH=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y @@ -72,7 +72,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index e84aed4d54d..a0a9e8ac584 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -21,7 +21,7 @@ CONFIG_SPL_MAX_SIZE=0x439e0 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y @@ -62,7 +62,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 0cae3242b04..cd47806204e 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -20,7 +20,7 @@ CONFIG_SPL_MAX_SIZE=0x37690 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y @@ -75,7 +75,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 370ee967258..d721664ecb1 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -28,7 +28,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_ETH=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y @@ -68,7 +68,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index d0a34c75505..38083586a3e 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -21,8 +21,9 @@ CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -42,7 +43,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -# CONFIG_NET is not set CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y @@ -51,6 +51,8 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y # CONFIG_GPIO is not set # CONFIG_I2C is not set @@ -60,6 +62,10 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_FIXED=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index d52de8bf8be..40704151255 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig new file mode 100644 index 00000000000..03ca3ac0c81 --- /dev/null +++ b/configs/am62x_beagleplay_a53_defconfig @@ -0,0 +1,118 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 +CONFIG_TARGET_AM625_A53_BEAGLEPLAY=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay" +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +# CONFIG_PSCI_RESET is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load" +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80c80000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x800000 +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPIO_READ=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_LED=y +CONFIG_SPL_LED=y +CONFIG_LED_GPIO=y +CONFIG_SPL_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_FIXED=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65219=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_TPS65219=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_EXT4_WRITE=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_LZO=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig new file mode 100644 index 00000000000..2f3264b7ede --- /dev/null +++ b/configs/am62x_beagleplay_r5_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x08000000 +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_AM625_R5_BEAGLEPLAY=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay" +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 +CONFIG_SPL_SIZE_LIMIT=0x3A7F0 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c3b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y +CONFIG_ESM_K3=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index f4369865bf6..55289b967b7 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -52,7 +52,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index f610b2dd94e..6b0bb120d10 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 -CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 056c1fbacfc..d11a31ee641 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -65,6 +65,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y CONFIG_CPU=y +CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index aa9cf77960b..4a27738eb70 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -87,6 +88,9 @@ CONFIG_DWC_AHSATA=y CONFIG_LBA48=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x14420000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -105,7 +109,7 @@ CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 6cfb5a7d321..e2714d1e1a1 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -4,6 +4,8 @@ CONFIG_TEXT_BASE=0x06208000 CONFIG_SYS_MALLOC_LEN=0x240000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x06208000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -19,10 +21,12 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run common_bootargs; run romboot" +CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" CONFIG_SYS_MAXARGS=32 CONFIG_SYS_BOOTM_LEN=0x1400000 +CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -31,6 +35,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -39,6 +44,7 @@ CONFIG_CMD_RNG=y CONFIG_CMD_UUID=y CONFIG_CMD_HASH=y CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -49,6 +55,7 @@ CONFIG_NPCM_AES=y CONFIG_NPCM_SHA=y CONFIG_NPCM_GPIO=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_NPCM=y # CONFIG_INPUT is not set CONFIG_MISC=y CONFIG_NPCM_HOST=y @@ -87,12 +94,17 @@ CONFIG_TPM2_FTPM_TEE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_NPCM=y -CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_OHCI_NPCM=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Nuvoton" +CONFIG_USB_GADGET_VENDOR_NUM=0x0416 +CONFIG_USB_GADGET_PRODUCT_NUM=0xffff +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_LIB_HW_RAND=y CONFIG_TPM=y CONFIG_SHA_HW_ACCEL=y # CONFIG_EFI_LOADER is not set +CONFIG_SYS_SKIP_UART_INIT=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index f9c02144c4a..e1a01b24b88 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -86,7 +86,6 @@ CONFIG_MTD=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig index 2a3958b0fd0..755bccb4a72 100644 --- a/configs/bananapi-m2-pro_defconfig +++ b/configs/bananapi-m2-pro_defconfig @@ -56,6 +56,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig index 405ce3a93a9..af8daced622 100644 --- a/configs/bananapi-m2s_defconfig +++ b/configs/bananapi-m2s_defconfig @@ -61,6 +61,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index b8c9afd9cfc..5c9b97819b1 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -42,7 +42,6 @@ CONFIG_SYS_PBSIZE=2075 CONFIG_CMD_BOOTZ=y CONFIG_SYS_BOOTM_LEN=0x3c00000 # CONFIG_CMD_ELF is not set -# CONFIG_CMD_DM is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y @@ -50,6 +49,7 @@ CONFIG_CMD_FPGA_LOADMK=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_PART=y # CONFIG_CMD_SETEXPR is not set @@ -60,11 +60,15 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SPREAD=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y @@ -74,6 +78,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_BOOTP_SERVERIP=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DFU_TIMEOUT=y +CONFIG_DFU_MMC=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_MMC_SDHCI=y @@ -93,4 +99,6 @@ CONFIG_ZYNQ_SERIAL=y CONFIG_WDT=y CONFIG_WDT_CDNS=y CONFIG_SYS_TIMER_COUNTS_DOWN=y -# CONFIG_EFI_LOADER is not set +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_TOOLS_MKEFICAPSULE=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 06642d282d1..0cd649d643a 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -63,7 +63,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 73ccefd269a..1a558b030fe 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -37,7 +37,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index 2fead59f5f2..20cba723ee0 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -64,6 +64,9 @@ CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x81100000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 5164374c67f..d904621f5e2 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -75,6 +75,9 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x81100000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 51f3eeca754..cd68264eca1 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -85,6 +85,9 @@ CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x14420000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index eba2b41c842..e24a606bc45 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -72,6 +72,9 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x81100000 +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 49a51e9272f..687dbb5e3e7 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -62,9 +62,9 @@ CONFIG_SERVERIP="192.168.10.1" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_BUF_ADDR=0x81100000 CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index ecf61f0d1e6..5eaa6dbb5fc 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -81,7 +81,6 @@ CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 5f6f5d788d0..62b8edde248 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -88,7 +88,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index ec4031da51d..569b156c997 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -73,7 +73,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_LPC32XX_SLC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 # CONFIG_SYS_NAND_5_ADDR_CYCLE is not set diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index ef16da176a9..a7f82442eb0 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -77,7 +77,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 5a83b6a08a2..071898b1e39 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -52,9 +52,13 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SATA=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_WDT=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -71,6 +75,10 @@ CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y @@ -99,7 +107,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 19ca89fa867..c3a3ec2cd42 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -104,7 +104,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/etamin_defconfig b/configs/draco-etamin_defconfig index c0ce7a33569..ef7c7c1a549 100644 --- a/configs/etamin_defconfig +++ b/configs/draco-etamin_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 @@ -10,7 +9,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x980000 -CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 @@ -22,8 +20,6 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xB80000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 @@ -36,7 +32,6 @@ CONFIG_RESET_TO_RETRY=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y @@ -45,9 +40,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set @@ -76,7 +68,6 @@ CONFIG_MTDIDS_DEFAULT="nand2=omap2-nand_concat" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand_concat:512k(spl),512k(spl.backup1),512k(spl.backup2),512k(spl.backup3),7680k(u-boot),2048k(u-boot.env0),2048k(u-boot.env1),2048k(mtdoops),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y @@ -91,6 +82,8 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_I2C_LEGACY=y @@ -104,13 +97,10 @@ CONFIG_SYS_MAX_NAND_DEVICE=3 CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x80 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHY_SMSC=y diff --git a/configs/rastaban_defconfig b/configs/draco-rastaban_defconfig index 9f538a2f83d..b293ed5ef70 100644 --- a/configs/rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -2,27 +2,22 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x2000 -CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_RASTABAN=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 @@ -35,18 +30,15 @@ CONFIG_RESET_TO_RETRY=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set @@ -59,7 +51,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -75,7 +66,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),300m(rootfs),512k(mtdoops),-(configuration)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y @@ -90,23 +80,21 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y -# CONFIG_SPL_DM_MMC is not set -CONFIG_MMC_OMAP_HS=y +# CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHY_SMSC=y diff --git a/configs/thuban_defconfig b/configs/draco-thuban_defconfig index 116700e0df0..6c03732d4a9 100644 --- a/configs/thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -2,27 +2,22 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x2000 -CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_THUBAN=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 @@ -35,18 +30,15 @@ CONFIG_RESET_TO_RETRY=y CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BSS_START_ADDR=0x80000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set @@ -59,7 +51,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -75,7 +66,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y @@ -90,23 +80,21 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y -# CONFIG_SPL_DM_MMC is not set -CONFIG_MMC_OMAP_HS=y +# CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHY_SMSC=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig deleted file mode 100644 index ee19920a703..00000000000 --- a/configs/draco_defconfig +++ /dev/null @@ -1,127 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TEXT_BASE=0x80100000 -CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" -CONFIG_AM33XX=y -CONFIG_SYS_MPUCLK=300 -CONFIG_TARGET_DRACO=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2E0000 -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -CONFIG_SYS_LOAD_ADDR=0x81000000 -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" -CONFIG_BOOT_RETRY=y -CONFIG_BOOT_RETRY_TIME=60 -CONFIG_RESET_TO_RETRY=y -CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_BSS_START_ADDR=0x80000000 -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 -CONFIG_SPL_I2C=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 -CONFIG_SPL_WATCHDOG=y -CONFIG_SPL_YMODEM_SUPPORT=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_PBSIZE=1049 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_DNS2=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RETRY_COUNT=10 -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_USE_ROOTPATH=y -CONFIG_ROOTPATH="/opt/eldk" -CONFIG_SPL_DM=y -# CONFIG_SPL_BLK is not set -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_ENV=y -CONFIG_DFU_NAND=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -# CONFIG_SPL_DM_MMC is not set -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHY_SMSC=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -# CONFIG_SPL_DM_USB is not set -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" -CONFIG_USB_GADGET_VENDOR_NUM=0x0908 -CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index f134680e412..db2e35f388b 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_TIMER=y CONFIG_CMD_HASH=y CONFIG_CMD_EXT4=y diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig index dfc315774a5..e2e6f42c9a9 100644 --- a/configs/efi-x86_app32_defconfig +++ b/configs/efi-x86_app32_defconfig @@ -20,7 +20,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_PART=y -# CONFIG_CMD_NET is not set +# CONFIG_CMD_SCSI is not set CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y @@ -35,7 +35,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" -CONFIG_USE_ROOTPATH=y +# CONFIG_NET is not set CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_REGEX is not set diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig index e0cfe3ee243..14b5cd0fa0e 100644 --- a/configs/efi-x86_app64_defconfig +++ b/configs/efi-x86_app64_defconfig @@ -21,7 +21,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_PART=y -# CONFIG_CMD_NET is not set +# CONFIG_CMD_SCSI is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y @@ -37,7 +37,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" -CONFIG_USE_ROOTPATH=y +# CONFIG_NET is not set CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig index d605acdfc87..7212675546b 100644 --- a/configs/endeavoru_defconfig +++ b/configs/endeavoru_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_UMS_ABORT_KEYED=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set @@ -61,10 +62,13 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_TEGRA=y CONFIG_BUTTON_KEYBOARD=y CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_TPS80031=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_TPS80031=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_TPS80031=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_TEGRA=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 3eb1917454d..35f7fb77e63 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index 439fcc05753..0fb92ff1638 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -99,7 +99,6 @@ CONFIG_MTD=y CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/grouper_common_defconfig b/configs/grouper_common_defconfig index 258d7b1139c..616540f7d50 100644 --- a/configs/grouper_common_defconfig +++ b/configs/grouper_common_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_UMS_ABORT_KEYED=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 993bbe29c6b..34439cf77be 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -24,7 +24,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y @@ -78,7 +78,6 @@ CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index 05bab034e0f..6abb7954ba2 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -63,7 +63,6 @@ CONFIG_CMD_PART=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set # CONFIG_CMD_BLOCK_CACHE is not set # CONFIG_CMD_SLEEP is not set # CONFIG_CMD_MP is not set @@ -82,7 +81,7 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y -CONFIG_TFTP_BLOCKSIZE=512 +# CONFIG_NET is not set CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig index d6edc719004..c471e04d9bd 100644 --- a/configs/imx6ulz_smm_m2_defconfig +++ b/configs/imx6ulz_smm_m2_defconfig @@ -25,7 +25,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BSS_START_ADDR=0x84100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_DMA=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_DM=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 031470c1692..b33e113580b 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -86,6 +86,11 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y @@ -142,6 +147,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y +# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index e724607c6ee..6a4244e3084 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -108,6 +108,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y @@ -148,6 +151,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -157,6 +162,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 9409d5142c7..d1c27ce22ca 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -34,6 +34,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" +# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x950000 @@ -149,4 +150,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 657eb354c1b..a9c02976f8c 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_NAND_IDENT=y diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index b686af8d188..c758ff371d3 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -42,6 +42,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb" +# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set # CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index ae1a48c6812..f5914ac2a80 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -114,6 +114,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y @@ -155,6 +158,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -164,6 +169,8 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_IMX8M_DRAM_INLINE_ECC=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig new file mode 100644 index 00000000000..5de80233bd5 --- /dev/null +++ b/configs/imx8mp_debix_model_a_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-debix-model-a" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-debix-model-a.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_SPL_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index a77139ab06a..3f9b0e3733c 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -109,6 +109,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y @@ -151,6 +154,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -160,6 +165,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index c1f8fbd3ec3..50c21d51b8d 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -111,6 +111,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y @@ -153,6 +156,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -162,6 +167,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index d538b85c1f8..683053b42f6 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" CONFIG_SPL_TEXT_BASE=0x920000 @@ -74,6 +71,7 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y @@ -88,8 +86,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -110,15 +106,16 @@ CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig index 01eabc43fb3..017a5419134 100644 --- a/configs/imx8qm_dmsse20a1_defconfig +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -20,6 +20,7 @@ CONFIG_TARGET_IMX8QM_DMSSE20_A1=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x13e000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y @@ -32,8 +33,16 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x1f000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x128000 CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index cb4a141675d..c0f31f53ae3 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -29,10 +29,11 @@ CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -50,7 +51,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y @@ -138,7 +139,6 @@ CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y -CONFIG_HBMC_AM654=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index d25dd8134b6..069b2acd1f6 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -48,7 +48,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y @@ -114,7 +114,6 @@ CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y -CONFIG_HBMC_AM654=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig new file mode 100644 index 00000000000..9e16c98d15c --- /dev/null +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -0,0 +1,171 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_J721E=y +CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-beagleboneai64" +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +# CONFIG_PSCI_RESET is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load" +CONFIG_LOGLEVEL=7 +CONFIG_SPL_MAX_SIZE=0xc0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPIO_READ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MMC_SPEED_MODE_SET=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_LED=y +CONFIG_SPL_LED=y +CONFIG_LED_GPIO=y +CONFIG_SPL_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD_UBI=y +CONFIG_MULTIPLEXER=y +CONFIG_MUX_MMIO=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_FIXED=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_RESET_TI_SCI=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6163 +CONFIG_SPL_DFU=y +CONFIG_LZO=y diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig new file mode 100644 index 00000000000..5e6ad7bc2f0 --- /dev/null +++ b/configs/j721e_beagleboneai64_r5_defconfig @@ -0,0 +1,131 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x70000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_J721E=y +CONFIG_K3_EARLY_CONS=y +CONFIG_TARGET_J721E_R5_BEAGLEBONEAI64=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-beagleboneai64" +CONFIG_SPL_TEXT_BASE=0x41c00000 +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0xf59f0 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0xf59f0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x41cf59f0 +CONFIG_SPL_BSS_MAX_SIZE=0xa000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIST="k3-j721e-r5-common-proc-board" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_OF_LIST="k3-j721e-r5-beagleboneai64" +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65941=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_TPS65941=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 99e0e168ebf..82fa1b1f629 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -29,10 +29,11 @@ CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -50,7 +51,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index e76ab5997fe..55169bb1391 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -53,7 +53,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 876f07816a2..a7adb9282b0 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -49,7 +49,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 4990e271c3f..c0fdd86e1f0 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -55,7 +55,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index ba74b241ab9..b1c267a7917 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MESON_SPIFC=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index ef9e15d1520..e1ddc0af5db 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -90,7 +90,6 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXC=y CONFIG_MXC_NAND_HWECC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig index e8fa22b648b..0a9adcc0399 100644 --- a/configs/mvebu_ac5_rd_defconfig +++ b/configs/mvebu_ac5_rd_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -72,7 +73,7 @@ CONFIG_PINCTRL_ARMADA_8K=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_SYS_NS16550=y CONFIG_MVEBU_A3700_SPI=y CONFIG_DM_THERMAL=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 278e3fd8adb..23899911882 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig index bc0bf9b8961..49d628b76ab 100644 --- a/configs/odroid-go-ultra_defconfig +++ b/configs/odroid-go-ultra_defconfig @@ -63,6 +63,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 539b0cfa4f7..5040af058dd 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -30,7 +30,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y @@ -74,7 +74,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index f14ce3d23db..1ea35c7cfab 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y @@ -83,7 +83,6 @@ CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index cabd3659385..c8c9ae02f16 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y @@ -83,7 +83,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 33ff39ff548..93427f3691c 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y @@ -74,7 +74,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 7d3d602c9d9..729586bfdc1 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -29,7 +29,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y @@ -73,7 +73,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 0141a425e07..f0f326d2f9c 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y @@ -84,7 +84,6 @@ CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 47feff21bd4..63554d56016 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -84,7 +84,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index f13735e91c7..98aed846f1f 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_USB1_VBUS_PIN="PC16" CONFIG_R_I2C_ENABLE=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -19,6 +20,7 @@ CONFIG_SYS_I2C_SPEED=400000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y +CONFIG_AXP305_POWER=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig new file mode 100644 index 00000000000..5a019fed84b --- /dev/null +++ b/configs/orangepi_zero3_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e +CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee +CONFIG_DRAM_SUN50I_H616_TPR6=0x44000000 +CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 +CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624 +CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_CLK=792 +CONFIG_USB1_VBUS_PIN="PC16" +CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP313_POWER=y +CONFIG_SPI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 3a71d6e582a..5e55b712df9 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -35,13 +35,13 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_MMC_DW=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index 4bdf8822181..cbfe1cf7985 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -28,7 +28,7 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y @@ -76,7 +76,6 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 7644fbec273..b91b9665cc2 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -28,7 +28,7 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y @@ -76,7 +76,6 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index bff35e739c4..3ac250270d1 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm" +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 1eee1e6c2ff..3af968d5512 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -70,6 +70,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 48364c7548e..5b615daf4a8 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -76,6 +76,8 @@ CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -95,3 +97,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig index f0ab2319a47..b6e0c3166c1 100644 --- a/configs/poplar_defconfig +++ b/configs/poplar_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_USB=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x20000000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 2ea007d0de5..e1d1066815b 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -99,7 +99,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig index e9415762ff3..b795681b3f0 100644 --- a/configs/radxa-zero2_defconfig +++ b/configs/radxa-zero2_defconfig @@ -52,6 +52,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index ccf25667b50..248073be1f2 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -99,7 +99,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index f585c510635..ac236c82a1f 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_CMD_EXT4_WRITE=y @@ -42,6 +41,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +# CONFIG_NET is not set CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_SYS_I2C_S3C24X0=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index a1b6122f8eb..a0802f9c5fe 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -86,7 +86,6 @@ CONFIG_PMECC_CAP=4 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 6278a6c68a7..d96bb91e65d 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -90,7 +90,6 @@ CONFIG_PMECC_CAP=4 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index d12f749d7f4..68101a12fc2 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -84,7 +84,6 @@ CONFIG_PMECC_CAP=8 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 27bfcdf0084..b8062db775d 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -81,7 +81,6 @@ CONFIG_PMECC_CAP=8 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 6c488bac2b3..a29100ed506 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -1,4 +1,5 @@ CONFIG_TEXT_BASE=0 +CONFIG_SYS_MALLOC_LEN=0x6000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="sandbox64" @@ -14,7 +15,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_BOOTSTAGE_FDT=y @@ -50,6 +50,7 @@ CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_LOADM=y +CONFIG_CMD_MTD=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y @@ -167,6 +168,13 @@ CONFIG_PWRSEQ=y CONFIG_I2C_EEPROM=y CONFIG_MMC_SANDBOX=y CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_MAX_NAND_DEVICE=8 +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_SANDBOX=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_PAGE_SIZE=0x200 CONFIG_SPI_FLASH_SANDBOX=y CONFIG_BOOTDEV_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y @@ -262,6 +270,7 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y CONFIG_ERRNO_STR=y +CONFIG_GETOPT=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index bc5bcb2a623..af3e7d85be3 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -1,4 +1,5 @@ CONFIG_TEXT_BASE=0 +CONFIG_SYS_MALLOC_LEN=0x6000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="sandbox" @@ -15,7 +16,6 @@ CONFIG_FIT_CIPHER=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_MEASURED_BOOT=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_BOOTSTAGE_FDT=y @@ -74,6 +74,7 @@ CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_LOADM=y CONFIG_CMD_LSBLK=y +CONFIG_CMD_MTD=y CONFIG_CMD_MUX=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y @@ -121,6 +122,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AES=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_SCMI=y CONFIG_CMD_BTRFS=y CONFIG_CMD_CBFS=y CONFIG_CMD_CRAMFS=y @@ -216,6 +218,13 @@ CONFIG_MMC_PCI=y CONFIG_MMC_SANDBOX=y CONFIG_MMC_SDHCI=y CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_MAX_NAND_DEVICE=8 +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_SANDBOX=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_PAGE_SIZE=0x200 CONFIG_SPI_FLASH_SANDBOX=y CONFIG_BOOTDEV_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y @@ -339,6 +348,7 @@ CONFIG_ECDSA=y CONFIG_ECDSA_VERIFY=y CONFIG_TPM=y CONFIG_ERRNO_STR=y +CONFIG_GETOPT=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 0b637727d9f..9c774bb684a 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -12,7 +12,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_BOOTSTAGE_FDT=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index cd412ee2693..8cfe30bd01b 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -25,7 +25,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_BOOTSTAGE_FDT=y @@ -51,6 +50,13 @@ CONFIG_SPL_ETH=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_DRIVERS=y +CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_SOFTECC=y +CONFIG_SPL_NAND_BASE=y +CONFIG_SPL_NAND_IDENT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NET=y CONFIG_SPL_NOR_SUPPORT=y @@ -80,6 +86,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y @@ -180,6 +187,18 @@ CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_FS_LOADER=y CONFIG_MMC_SANDBOX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_MAX_NAND_DEVICE=8 +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_SANDBOX=y +CONFIG_SYS_NAND_BLOCK_SIZE=0x2000 +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_PAGE_SIZE=0x200 +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 CONFIG_SPI_FLASH_SANDBOX=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index eeccee62b8c..f1cca13d5f3 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -20,7 +20,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_BOOTSTAGE_FDT=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 293e294d57a..62df03e7bf7 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -27,7 +27,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_BOOTSTAGE_FDT=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 10cbccb69b0..80d2c0f1cc1 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -84,7 +84,6 @@ CONFIG_MTD=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index b8052f1deea..6a4106a559e 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -43,7 +43,7 @@ CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_BOOTM_LEN=0x4000000 diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index b15e7d24db1..7b39a63359d 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -72,6 +72,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y @@ -133,3 +134,7 @@ CONFIG_USB_EHCI_PCI=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_PCI=y CONFIG_USB_KEYBOARD=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_STARFIVE=y diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig index b2c30b847c3..ce00f0d6ad2 100644 --- a/configs/stm32746g-eval_defconfig +++ b/configs/stm32746g-eval_defconfig @@ -19,12 +19,11 @@ CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " -CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y -# CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_SNTP=y @@ -66,3 +65,4 @@ CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +# CONFIG_RANDOM_UUID is not set diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index 3864e21a180..f9711bedd7d 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -34,7 +34,7 @@ CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_XIP_SUPPORT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000 CONFIG_SPL_DM_RESET=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 682d2973462..aae6cebd40d 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -16,12 +16,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " -CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIMER=y diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index f460c6f9d1f..75f6a4d0ba8 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -12,13 +12,12 @@ CONFIG_TARGET_STM32F429_EVALUATION=y CONFIG_SYS_LOAD_ADDR=0x400000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " -CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_IMLS=y CONFIG_CMD_GPT=y -# CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y @@ -32,3 +31,4 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_STM32_FLASH=y CONFIG_SYS_MAX_FLASH_SECT=12 CONFIG_SYS_MAX_FLASH_BANKS=2 +# CONFIG_RANDOM_UUID is not set diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 21c5498466c..9b5f38b9efa 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -12,15 +12,15 @@ CONFIG_TARGET_STM32F469_DISCOVERY=y CONFIG_SYS_LOAD_ADDR=0x400000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " -CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_IMLS=y CONFIG_CMD_GPT=y -# CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set @@ -37,6 +37,21 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_PINCTRL_FULL is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LOGO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y +CONFIG_VIDEO_STM32=y +CONFIG_VIDEO_STM32_DSI=y +CONFIG_VIDEO_STM32_MAX_XRES=480 +CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 3c3a0d25d4d..7a2387519b2 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -19,12 +19,11 @@ CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " -CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y -# CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_SNTP=y @@ -66,3 +65,4 @@ CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +# CONFIG_RANDOM_UUID is not set diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index b2a786121c5..a2b740c9cce 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -34,7 +34,7 @@ CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_XIP_SUPPORT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000 CONFIG_SPL_DM_RESET=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 3514a78bb8f..a0d2aa043c8 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -19,11 +19,10 @@ CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="U-Boot > " -CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y -# CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_SNTP=y @@ -68,3 +67,4 @@ CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +# CONFIG_RANDOM_UUID is not set diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 34622032210..37d22f8d95f 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -33,7 +33,7 @@ CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_XIP_SUPPORT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x81c0000 CONFIG_SPL_DM_RESET=y diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index a8bf3329742..89d79e98b6f 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -17,10 +17,10 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco" -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SYS_PROMPT="U-Boot > " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 387dc6aac52..2d79bf0eb05 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -16,11 +16,11 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PROMPT="STM32MP> " -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 6df09352400..be553ad3c36 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -40,7 +40,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_FLASH_MTD=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 1d241529be7..f4dbbf36d7c 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -49,7 +49,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_RAM_SUPPORT=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 6e0c4a8cf9f..d4ead98826b 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -47,7 +47,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_RAM_SUPPORT=y diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig new file mode 100644 index 00000000000..75f27c98b44 --- /dev/null +++ b/configs/stm32mp25_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x400000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000 +CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1" +CONFIG_STM32MP25X=y +CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_TARGET_ST_STM32MP25X=y +CONFIG_SYS_LOAD_ADDR=0x84000000 +CONFIG_SYS_MEMTEST_START=0x84000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_BOOTDELAY=1 +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="STM32MP> " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ADTIMG=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADB is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_OF_LIVE=y +# CONFIG_NET is not set +CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +# CONFIG_MMC is not set +CONFIG_PINCONF=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +# CONFIG_STM32MP1_DDR is not set +CONFIG_DM_RNG=y +CONFIG_SERIAL_RX_BUFFER=y +# CONFIG_OPTEE_TA_AVB is not set +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_WDT_ARM_SMC=y +CONFIG_ERRNO_STR=y +# CONFIG_LMB_USE_MAX_REGIONS is not set +CONFIG_LMB_MEMORY_REGIONS=2 +CONFIG_LMB_RESERVED_REGIONS=32 diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index cc5755178b7..9be30c8d8a4 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -94,7 +94,6 @@ CONFIG_MTD=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 5c24b38bb1f..0c71b298ada 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -32,8 +32,8 @@ CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_NET is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set # CONFIG_MMC is not set CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SKIP_INIT=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index fa1ff4a73f2..b54d2cefa10 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -16,6 +16,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXTENSION is not set # CONFIG_CMD_DATE is not set diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig index 092c0aa2b01..8d828c1fa6c 100644 --- a/configs/transformer_t30_defconfig +++ b/configs/transformer_t30_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_UMS_ABORT_KEYED=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set @@ -65,10 +66,14 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_GPIO=y CONFIG_BUTTON_KEYBOARD=y CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_TPS65910=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_TPS65911=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y +CONFIG_SYSRESET_TPS65910=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_TEGRA=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 6c4909f12be..045c74f95ef 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_CMD_EXT4_WRITE=y @@ -44,6 +43,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +# CONFIG_NET is not set CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_DM_I2C_GPIO=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index 78484c07194..b1adaef17a0 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_CMD_EXT4_WRITE=y @@ -43,6 +42,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +# CONFIG_NET is not set CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 CONFIG_DM_I2C_GPIO=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index e128a62cd00..f89b163ddf5 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SATA=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -54,7 +55,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 7c1727f8b12..c9ec962201b 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SATA=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y @@ -71,7 +72,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PFUZE100=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/x240_defconfig b/configs/x240_defconfig index 4b1a761a908..152413de0e5 100644 --- a/configs/x240_defconfig +++ b/configs/x240_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -68,7 +69,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_MAX313XX=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_SYS_NS16550=y CONFIG_MVEBU_A3700_SPI=y CONFIG_DM_THERMAL=y diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig index a151f585240..90cbc2078a3 100644 --- a/configs/x3_t30_defconfig +++ b/configs/x3_t30_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_UMS_ABORT_KEYED=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set @@ -64,11 +65,14 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_TEGRA=y CONFIG_BUTTON_KEYBOARD=y CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_MAX77663=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_MAX77663=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y +CONFIG_SYSRESET_MAX77663=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_TEGRA=y diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index 318951e19c2..e805e0952b3 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 +CONFIG_AXP305_POWER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig new file mode 100644 index 00000000000..a20df1a4072 --- /dev/null +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -0,0 +1,227 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_LEN=0x4040000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SOURCE_FILE="zynqmp_kria" +CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x2200000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_SPL_STACK=0xfffffffc +CONFIG_SPL_SIZE_LIMIT=0x2a000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x2220000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_CMD_FRU=y +CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_ENV_ADDR=0x2200000 +CONFIG_AHCI=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_FS_LOAD_KERNEL_NAME="" +CONFIG_SPL_FS_LOAD_ARGS_NAME="" +CONFIG_SPL_FPGA=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000 +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2073 +CONFIG_SYS_BOOTM_LEN=0x6400000 +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_SMC=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SPREAD=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_CMD_UBI=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_BOARD=y +CONFIG_OF_LIST="" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SATA=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_TIMEOUT=y +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 +CONFIG_DMA=y +CONFIG_XILINX_DPDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_GPIO_HOG=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SLG7XL45106_I2C_GPO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADIN=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_XILINX_GMII2RGMII=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_XILINX_AXIEMAC=y +CONFIG_ZYNQ_GEM=y +CONFIG_PHY=y +CONFIG_PHY_XILINX_ZYNQMP=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_POWER_DOMAIN=y +CONFIG_ZYNQMP_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_CADENCE_TTC=y +CONFIG_RESET_ZYNQMP=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_RTC_ZYNQMP=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_ARM_DCC=y +CONFIG_XILINX_UARTLITE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SOC_XILINX_ZYNQMP=y +CONFIG_SPI=y +CONFIG_ZYNQ_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y +CONFIG_TPM2_TIS_SPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_COPY=y +CONFIG_I2C_EDID=y +CONFIG_VIDEO_ZYNQMP_DPSUB=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y +CONFIG_PANIC_HANG=y +CONFIG_TPM=y +CONFIG_SPL_GZIP=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index a6f36fe30a5..afbf6f6934d 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -11,6 +11,8 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi" CONFIG_SPL_STACK=0xfffffffc CONFIG_SPL=y +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_NO_DDR=y # CONFIG_PSCI_RESET is not set @@ -89,7 +91,6 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_ARM_DCC=y CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y -# CONFIG_FAT_WRITE is not set CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 1d8e5f6fd0a..f7b75812b43 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL=y +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_REMAKE_ELF=y CONFIG_SYS_CUSTOM_LDSCRIPT=y diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index db7cb632d54..2a50f38998b 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL=y +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_REMAKE_ELF=y CONFIG_SYS_CUSTOM_LDSCRIPT=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index dcb22ed3641..db1fc532d15 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x0 CONFIG_DEBUG_UART_CLOCK=0 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set # CONFIG_ZYNQ_DDRC_INIT is not set # CONFIG_CMD_ZYNQ is not set CONFIG_SYS_LOAD_ADDR=0x0 diff --git a/doc/android/bcb.rst b/doc/android/bcb.rst index 88616083005..2226517d39f 100644 --- a/doc/android/bcb.rst +++ b/doc/android/bcb.rst @@ -41,23 +41,25 @@ requirements enumerated above. Below is the command's help message:: bcb - Load/set/clear/test/dump/store Android BCB fields Usage: - bcb load <dev> <part> - load BCB from mmc <dev>:<part> - bcb set <field> <val> - set BCB <field> to <val> - bcb clear [<field>] - clear BCB <field> or all fields - bcb test <field> <op> <val> - test BCB <field> against <val> - bcb dump <field> - dump BCB <field> - bcb store - store BCB back to mmc + bcb load <interface> <dev> <part> - load BCB from <interface> <dev>:<part> + load <dev> <part> - load BCB from mmc <dev>:<part> + bcb set <field> <val> - set BCB <field> to <val> + bcb clear [<field>] - clear BCB <field> or all fields + bcb test <field> <op> <val> - test BCB <field> against <val> + bcb dump <field> - dump BCB <field> + bcb store - store BCB back to <interface> Legend: - <dev> - MMC device index containing the BCB partition - <part> - MMC partition index or name containing the BCB - <field> - one of {command,status,recovery,stage,reserved} - <op> - the binary operator used in 'bcb test': - '=' returns true if <val> matches the string stored in <field> - '~' returns true if <val> matches a subset of <field>'s string - <val> - string/text provided as input to bcb {set,test} - NOTE: any ':' character in <val> will be replaced by line feed - during 'bcb set' and used as separator by upper layers + <interface> - storage device interface (virtio, mmc, etc) + <dev> - storage device index containing the BCB partition + <part> - partition index or name containing the BCB + <field> - one of {command,status,recovery,stage,reserved} + <op> - the binary operator used in 'bcb test': + '=' returns true if <val> matches the string stored in <field> + '~' returns true if <val> matches a subset of <field>'s string + <val> - string/text provided as input to bcb {set,test} + NOTE: any ':' character in <val> will be replaced by line feed + during 'bcb set' and used as separator by upper layers 'bcb'. Example of getting reboot reason @@ -91,7 +93,7 @@ The following Kconfig options must be enabled:: CONFIG_PARTITIONS=y CONFIG_MMC=y - CONFIG_BCB=y + CONFIG_CMD_BCB=y .. [1] https://android.googlesource.com/platform/bootable/recovery .. [2] https://source.android.com/devices/bootloader diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index 23902dee89e..5f8db126657 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -424,15 +424,59 @@ space. See existing code for examples. VPL (Verifying Program Loader) ------------------------------ -Sandbox provides an example build of vpl called `sandbox_vpl`. This can be run -using:: +Sandbox provides an example build of vpl called `sandbox_vpl`. To build it: - /path/to/sandbox_vpl/tpl/u-boot-tpl -D +.. code-block:: bash + + make sandbox_vpl_defconfig all + +This can be run using: + +.. code-block:: bash + + ./tpl/u-boot-tpl -d u-boot.dtb It starts up TPL (first-stage init), then VPL, then runs SPL and finally U-Boot proper, following the normal flow for a verified boot. At present, no verification is actually implemented. +Here is an example trace:: + + U-Boot TPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + U-Boot VPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from vbe_simple + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + U-Boot SPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from vbe_simple + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + + U-Boot 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + + Reset Status: COLD + Model: sandbox + DRAM: 256 MiB + using memory 0x1b576000-0x1f578000 for malloc() + + Warning: host_lo MAC addresses don't match: + Address in ROM is 96:cd:ef:82:78:51 + Address in environment is 02:00:11:22:33:44 + Core: 103 devices, 51 uclasses, devicetree: board + MMC: + Loading Environment from nowhere... OK + In: serial,cros-ec-keyb,usbkbd + Out: serial,vidconsole + Err: serial,vidconsole + Model: sandbox + Net: eth0: host_lo, eth1: host_enp14s0, eth2: host_eth6, eth3: host_wlp15s0, eth4: host_virbr0, eth5: host_docker0, eth6: eth@10002000 + Hit any key to stop autoboot: 1 + Debugging the init sequence --------------------------- diff --git a/doc/board/allwinner/sunxi.rst b/doc/board/allwinner/sunxi.rst index 797222d8d34..d0c89b956b1 100644 --- a/doc/board/allwinner/sunxi.rst +++ b/doc/board/allwinner/sunxi.rst @@ -251,8 +251,7 @@ the SPI flash content from Linux, using the `MTD utils`_:: # apt-get install mtd-utils # mtdinfo - # mtd_debug erase /dev/mtdX 0 0xf0000 - # mtd_debug write /dev/mtdX 0 0xf0000 u-boot-sunxi-with-spl.bin + # flashcp -v u-boot-sunxi-with-spl.bin /dev/mtdX ``/dev/mtdX`` needs to be replaced with the respective device name, as listed in the output of ``mtdinfo``. diff --git a/doc/board/ti/am62x_beagleplay.rst b/doc/board/beagle/am62x_beagleplay.rst index 44e728de210..7784e62b0b7 100644 --- a/doc/board/ti/am62x_beagleplay.rst +++ b/doc/board/beagle/am62x_beagleplay.rst @@ -23,7 +23,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. image:: img/boot_diagram_k3_current.svg +.. image:: ../ti/img/boot_diagram_k3_current.svg :alt: Boot flow diagram - On this platform, 'TI Foundational Security' (TIFS) functions as the @@ -34,7 +34,7 @@ Below is the pictorial representation of boot flow: Sources: -------- -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources @@ -42,30 +42,30 @@ Build procedure: ---------------- 0. Setup the environment variables: -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_common_env_vars_desc :end-before: .. k3_rst_include_end_common_env_vars_desc -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_board_env_vars_desc :end-before: .. k3_rst_include_end_board_env_vars_desc Set the variables corresponding to this platform: -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_common_env_vars_defn :end-before: .. k3_rst_include_end_common_env_vars_defn .. prompt:: bash $ - export UBOOT_CFG_CORTEXR="am62x_evm_r5_defconfig beagleplay_r5.config" - export UBOOT_CFG_CORTEXA="am62x_evm_a53_defconfig beagleplay_a53.config" + export UBOOT_CFG_CORTEXR=am62x_beagleplay_r5_defconfig + export UBOOT_CFG_CORTEXA=am62x_beagleplay_a53_defconfig export TFA_BOARD=lite # we dont use any extra TFA parameters unset TFA_EXTRA_ARGS export OPTEE_PLATFORM=k3-am62x export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y" -.. include:: am62x_sk.rst +.. include:: ../ti/am62x_sk.rst :start-after: .. am62x_evm_rst_include_start_build_steps :end-before: .. am62x_evm_rst_include_end_build_steps @@ -82,12 +82,12 @@ Image formats - tiboot3.bin -.. image:: img/multi_cert_tiboot3.bin.svg +.. image:: ../ti/img/multi_cert_tiboot3.bin.svg :alt: tiboot3.bin image format - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: ../ti/img/dm_tispl.bin.svg :alt: tispl.bin image format Additional hardware for U-Boot development @@ -240,7 +240,7 @@ LED patterns during boot A53 SPL DDR Memory Layout ------------------------- -.. include:: am62x_sk.rst +.. include:: ../ti/am62x_sk.rst :start-after: .. am62x_evm_rst_include_start_ddr_mem_layout :end-before: .. am62x_evm_rst_include_end_ddr_mem_layout @@ -284,11 +284,11 @@ detailed setup and debugging information. environment's distribution needs to be updated, it might be necessary to build OpenOCD from the source. -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_openocd_connect_tag_connect :end-before: .. k3_rst_include_end_openocd_connect_tag_connect -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_openocd_cfg_external_intro :end-before: .. k3_rst_include_end_openocd_cfg_external_intro diff --git a/doc/board/ti/img/beagleplay_emmc.svg b/doc/board/beagle/img/beagleplay_emmc.svg index c6ff19b7738..c6ff19b7738 100644 --- a/doc/board/ti/img/beagleplay_emmc.svg +++ b/doc/board/beagle/img/beagleplay_emmc.svg diff --git a/doc/board/beagle/index.rst b/doc/board/beagle/index.rst new file mode 100644 index 00000000000..9124546ebc7 --- /dev/null +++ b/doc/board/beagle/index.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +BeagleBoard.org +############### + + +ARM based boards +---------------- + +.. toctree:: + :maxdepth: 2 + + am62x_beagleplay + j721e_beagleboneai64 diff --git a/doc/board/beagle/j721e_beagleboneai64.rst b/doc/board/beagle/j721e_beagleboneai64.rst new file mode 100644 index 00000000000..d6b9c8ca606 --- /dev/null +++ b/doc/board/beagle/j721e_beagleboneai64.rst @@ -0,0 +1,327 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Nishanth Menon <nm@ti.com> + +J721E/TDA4VM Beagleboard.org BeagleBone AI-64 +============================================= + +Introduction: +------------- + +BeagleBoard.org BeagleBone AI-64 is an open source hardware single +board computer based on the Texas Instruments TDA4VM SoC featuring +dual-core 2.0GHz Arm Cortex-A72 processor, C7x+MMA and 2 C66x +floating-point VLIW DSPs, 3x dual ARM Cortex-R5 co-processors, +2x 6-core Programmable Real-Time Unit and Industrial Communication +SubSystem, PowerVR Rogue 8XE GE8430 3D GPU. The board features 4GB +DDR4, USB3.0 Type-C, 2x USB SS Type-A, miniDisplayPort, 2x 4-lane +CSI, DSI, 16GB eMMC flash, 1G Ethernet, M.2 E-key for WiFi/BT, and +BeagleBone expansion headers. + +Further information can be found at: + +* Product Page: https://beagleboard.org/ai-64 +* Hardware documentation: https://git.beagleboard.org/beagleboard/beaglebone-ai-64 + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. image:: ../ti/img/boot_diagram_j721e.svg + :alt: Boot flow diagram + +- On this platform, DMSC runs 'TI Foundational Security' (TIFS) which + functions as the security enclave master. The 'Device Manager' (DM), + also known as the 'TISCI server' in "TI terminology", running on boot + R5F, offers all the essential services required for device management. + The A72, C7x, C6x or R5F (Aux cores) sends requests to TIFS/DM to + accomplish the needed services, as illustrated in the diagram above. + +Sources: +-------- +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_sources + :end-before: .. k3_rst_include_end_boot_sources + +Build procedure: +---------------- +0. Setup the environment variables: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_desc + :end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_board_env_vars_desc + :end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_defn + :end-before: .. k3_rst_include_end_common_env_vars_defn +.. prompt:: bash $ + + export UBOOT_CFG_CORTEXR=j721e_beagleboneai64_r5_defconfig + export UBOOT_CFG_CORTEXA=j721e_beagleboneai64_a72_defconfig + export TFA_BOARD=generic + # we dont use any extra TFA parameters + unset TFA_EXTRA_ARGS + export OPTEE_PLATFORM=k3-j721e + # we dont use any extra OP-TEE parameters + unset OPTEE_EXTRA_ARGS + +.. include:: ../ti/j721e_evm.rst + :start-after: .. j721e_evm_rst_include_start_build_steps + :end-before: .. j721e_evm_rst_include_end_build_steps + +Target Images +-------------- +Copy the below images to an SD card and boot: + +* tiboot3-j721e-gp-evm.bin from R5 build as tiboot3.bin +* tispl.bin_unsigned from Cortex-A build as tispl.bin +* u-boot.img_unsigned from Cortex-A build as u-boot.img + +Image formats +------------- + +- tiboot3.bin + +.. image:: ../ti/img/no_multi_cert_tiboot3.bin.svg + :alt: tiboot3.bin image format + +- tispl.bin + +.. image:: ../ti/img/dm_tispl.bin.svg + :alt: tispl.bin image format + +- sysfw.itb + +.. image:: ../ti/img/sysfw.itb.svg + :alt: sysfw.itb image format + +Additional hardware for U-Boot development +------------------------------------------ + +* Serial Console is critical for U-Boot development on BeagleBone AI-64. See + `BeagleBone AI-64 connector documentation + <https://docs.beagleboard.org/latest/boards/beaglebone/ai-64/ch07.html>`_. +* uSD is preferred option over eMMC, and a SD/MMC reader will be needed. +* (optionally) JTAG is useful when working with very early stages of boot. + +Default storage options +----------------------- + +There are multiple storage media options on BeagleBone AI-64, but primarily: + +* Onboard eMMC (default) - reliable, fast and meant for deployment use. +* SD/MMC card interface (hold 'BOOT' switch and power on) - Entirely + depends on the SD card quality. + +Flash to uSD card or how to deal with "bricked" Board +-------------------------------------------------------- + +When deploying or working on Linux, it's common to use the onboard +eMMC. However, avoiding the eMMC and using the uSD card is safer when +working with U-Boot. + +If you choose to hand format your own bootable uSD card, be +aware that it can be difficult. The following information +may be helpful, but remember that it is only sometimes +reliable, and partition options can cause issues. These +can potentially help: + +* https://git.ti.com/cgit/arago-project/tisdk-setup-scripts/tree/create-sdcard.sh +* https://elinux.org/Beagleboard:Expanding_File_System_Partition_On_A_microSD + +The simplest option is to start with a standard distribution +image like those in `BeagleBoard.org Distros Page +<https://www.beagleboard.org/distros>`_ and download a disk image for +BeagleBone AI-64. Pick a 16GB+ uSD card to be on the safer side. + +With an SD/MMC Card reader and `Balena Etcher +<https://etcher.balena.io/>`_, having a functional setup in minutes is +a trivial matter, and it works on almost all Host Operating Systems. +Yes Windows users, Windows Subsystem for Linux(WSL) based development +with U-Boot and update uSD card is practical. + +Updating U-Boot is a matter of copying the tiboot3.bin, tispl.bin and +u-boot.img to the "BOOT" partition of the uSD card. Remember to sync +and unmount (or Eject - depending on the Operating System) the uSD +card prior to physically removing from SD card reader. + +Also see following section on switch setting used for booting using +uSD card. + +.. note:: + Great news! If the board has not been damaged physically, there's no + need to worry about it being "bricked" on this platform. You only have + to flash an uSD card, plug it in, and reinstall the image on eMMC. This + means that even if you make a mistake, you can quickly fix it and rest + easy. + + If you are frequently working with uSD cards, you might find the + following useful: + + * `USB-SD-Mux <https://www.linux-automation.com/en/products/usb-sd-mux.html>`_ + * `SD-Wire <https://wiki.tizen.org/SDWire>`_ + +Flash to eMMC +------------- + +The eMMC layout selected is user-friendly for developers. The +boot hardware partition of the eMMC only contains the fixed-size +tiboot3.bin image. This is because the contents of the boot partitions +need to run from the SoC's internal SRAM, which remains a fixed size +constant. The other components of the boot sequence, such as tispl.bin +and u-boot.img, are located in the /BOOT partition in the User Defined +Area (UDA) hardware partition of the eMMC. These components can vary +significantly in size. The choice of keeping tiboot3.bin in boot0 or +boot1 partition depends on A/B update requirements. + +.. image:: img/beagleplay_emmc.svg + :alt: eMMC partitions and boot file organization for BeagleBone AI-64 + +The following are the steps from Linux shell to program eMMC: + +.. prompt:: bash # + + # Enable Boot0 boot + mmc bootpart enable 1 2 /dev/mmcblk0 + mmc bootbus set single_backward x1 x8 /dev/mmcblk0 + mmc hwreset enable /dev/mmcblk0 + + # Clear eMMC boot0 + echo '0' >> /sys/class/block/mmcblk0boot0/force_ro + dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k + # Write tiboot3.bin + dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k + + # Copy the rest of the boot binaries + mount /dev/mmcblk0p1 /boot/firmware + cp tispl.bin /boot/firmware + cp u-boot.img /boot/firmware + sync + +.. warning :: + + U-Boot is configured to prioritize booting from an SD card if it + detects a valid boot partition and boot files on it, even if the + system initially booted from eMMC. The boot order is set as follows: + + * SD/MMC + * eMMC + * USB + * PXE + +LED patterns during boot +------------------------ + +.. list-table:: USR LED status indication + :widths: 16 16 + :header-rows: 1 + + * - USR LEDs (012345) + - Indicates + + * - 00000 + - Boot failure or R5 image not started up + + * - 11111 + - A53 SPL/U-boot has started up + + * - 10101 + - OS boot process has been initiated + + * - 01010 + - OS boot process failed and drops to U-Boot shell + +.. note :: + + In the table above, 0 indicates LED switched off and 1 indicates LED + switched ON. + +.. warning :: + + The green LED very next to the serial connector labelled "WKUP UART0" + is the power LED (LED6). This is the same color as the rest of the USR + LEDs. If the "green" LED6 power LED is not glowing, the system power + supply is not functional. Please refer to `BeagleBone AI-64 documentation + <https://beagleboard.org/ai-64/>`_ for further information. + +Switch Setting for Boot Mode +---------------------------- + +The boot time option is configured via "BOOT" button on the board. +See `BeagleBone AI-64 Schematics <https://git.beagleboard.org/beagleboard/beaglebone-ai-64/-/blob/main/BeagleBone_AI-64_SCH.pdf>`_ +for details. + +.. list-table:: Boot Modes + :widths: 16 16 16 + :header-rows: 1 + + * - BOOT Switch Position + - Primary Boot + - Secondary Boot + + * - Not Pressed + - eMMC + - SD Card + + * - Pressed + - SD Card + - SD Card + +To switch to SD card boot mode, hold the BOOT button while powering on +with Type-C power supply, then release when power LED lights up. + +Debugging U-Boot +---------------- + +See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for +detailed setup and debugging information. + +.. warning:: + + **OpenOCD support since**: v0.12.0 + + If the default package version of OpenOCD in your development + environment's distribution needs to be updated, it might be necessary to + build OpenOCD from the source. + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_tag_connect + :end-before: .. k3_rst_include_end_openocd_connect_tag_connect + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_openocd_cfg_external_intro + :end-before: .. k3_rst_include_end_openocd_cfg_external_intro + +For example, with BeagleBone AI-64 (J721e platform), the openocd_connect.cfg: + +.. code-block:: tcl + + # TUMPA example: + # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual + source [find interface/ftdi/tumpa.cfg] + + transport select jtag + + # default JTAG configuration has only SRST and no TRST + reset_config srst_only srst_push_pull + + # delay after SRST goes inactive + adapter srst delay 20 + + if { ![info exists SOC] } { + # Set the SoC of interest + set SOC j721e + } + + source [find target/ti_k3.cfg] + + ftdi tdo_sample_edge falling + + # Speeds for FT2232H are in multiples of 2, and 32MHz is tops + # max speed we seem to achieve is ~20MHz.. so we pick 16MHz + adapter speed 16000 diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst index 61137bcbf1c..8a5eb1eda56 100644 --- a/doc/board/emulation/qemu-riscv.rst +++ b/doc/board/emulation/qemu-riscv.rst @@ -131,7 +131,13 @@ An attached disk can be emulated in RISC-V virt machine by adding:: -drive if=none,file=riscv64.img,format=raw,id=mydisk \ -device ide-hd,drive=mydisk,bus=ahci.0 -You will have to run 'scsi scan' to use it. +or alternatively attach an emulated UFS:: + + -device ufs,id=ufs0 \ + -drive if=none,file=test.img,format=raw,id=lun0 \ + -device ufs-lu,drive=lun0,bus=ufs0 + +You will have to run 'scsi scan' to use them. A video console can be emulated in RISC-V virt machine by removing "-nographic" and adding:: diff --git a/doc/board/index.rst b/doc/board/index.rst index 531e547e7e3..c96e5fda281 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -17,6 +17,7 @@ Board-specific doc asus/index atmel/index beacon/index + beagle/index broadcom/index bsh/index cloos/index diff --git a/doc/board/ti/am62ax_sk.rst b/doc/board/ti/am62ax_sk.rst new file mode 100644 index 00000000000..60726b6652c --- /dev/null +++ b/doc/board/ti/am62ax_sk.rst @@ -0,0 +1,213 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Jai Luthra <j-luthra@ti.com> + +AM62A Platforms +=============== + +Introduction: +------------- +The AM62A SoC family is built on the K3 Multicore SoC architecture platform, +providing a deep learning accelerator, multi-camera support with ISP, video +transcoder and other BOM-saving integrations. +The AM62A SoC enables cost-sensitive automotive applications including driver +and in-cabin monitoring systems, next generation of eMirror system, as well as +a broad set of industrial applications in Factory Automation, Building +Automation, Robotics and more. + +Some highlights of this SoC are: + +* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. +* Cortex-R5F for general-purpose or safety usage. +* Deep Learning Accelerator with Single-core C7x Vector DSP with MMA (up to + 1.0GHz). +* Vision Processing Accelerator (VPAC) with a 315MPixel/s ISP (up to 5MP @ + 60fps) supporting 16-bit RAW input with RGB-IR separation. +* 4K Video encoder and decoder for HEVC (Level 5.1 High-tier) and H.264 (Level + 5.2) supporting upto 240MPixels/s and MJPEG encoder at 416MPixels/s +* Single display with 24-bit RGB parallel (DPI) interface supporting upto + 165Mhz pixel clock for 2K resolution. +* Integrated Giga-bit Ethernet switch supporting up to a total of two + external ports (TSN capable). +* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for + NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, + 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. +* Dedicated Centralized System Controller for Security, Power, and + Resource Management. +* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, + enabling battery powered system design. + +More details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruj16 + +Platform information: + +* https://www.ti.com/tool/SK-AM62A-LP + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. image:: img/boot_diagram_k3_current.svg + :alt: Boot flow diagram + +- Here TIFS acts as master and provides all the critical services. R5/A53 + requests TIFS to get these services done as shown in the above diagram. + +Sources: +-------- + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_sources + :end-before: .. k3_rst_include_end_boot_sources + +Build procedure: +---------------- +0. Setup the environment variables: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_desc + :end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_board_env_vars_desc + :end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_defn + :end-before: .. k3_rst_include_end_common_env_vars_defn +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=am62ax_evm_r5_defconfig + $ export UBOOT_CFG_CORTEXA=am62ax_evm_a53_defconfig + $ export TFA_BOARD=lite + $ # we dont use any extra TFA parameters + $ unset TFA_EXTRA_ARGS + $ export OPTEE_PLATFORM=k3-am62ax + $ # we dont use any extra OPTEE parameters + $ unset OPTEE_EXTRA_ARGS + +1. Trusted Firmware-A: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_tfa + :end-before: .. k3_rst_include_end_build_steps_tfa + +2. OP-TEE: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_optee + :end-before: .. k3_rst_include_end_build_steps_optee + +3. U-Boot: + +* 3.1 R5: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_spl_r5 + :end-before: .. k3_rst_include_end_build_steps_spl_r5 + +* 3.2 A53: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_uboot + :end-before: .. k3_rst_include_end_build_steps_uboot + +Target Images +-------------- +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC +variant (GP, HS-FS, HS-SE) requires a different source for these files. + + - GP + + * tiboot3-am62ax-gp-evm.bin from step 3.1 + * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2 + + - HS-FS + + * tiboot3-am62ax-hs-fs-evm.bin from step 3.1 + * tispl.bin, u-boot.img from step 3.2 + + - HS-SE + + * tiboot3-am62ax-hs-evm.bin from step 3.1 + * tispl.bin, u-boot.img from step 3.2 + +Image formats: +-------------- + +- tiboot3.bin + +.. image:: img/multi_cert_tiboot3.bin.svg + :alt: tiboot3.bin image format + +- tispl.bin + +.. image:: img/dm_tispl.bin.svg + :alt: tispl.bin image format + +Switch Setting for Boot Mode +---------------------------- + +Boot Mode pins provide means to select the boot mode and options before the +device is powered up. After every POR, they are the main source to populate +the Boot Parameter Tables. + +The following table shows some common boot modes used on AM62 platform. More +details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruj16 under the `Boot Mode Pins` section. + +.. list-table:: Boot Modes + :widths: 16 16 16 + :header-rows: 1 + + * - Switch Label + - SW2: 12345678 + - SW3: 12345678 + + * - SD + - 01000000 + - 11000010 + + * - OSPI + - 00000000 + - 11001110 + + * - EMMC + - 00000000 + - 11010010 + + * - UART + - 00000000 + - 11011100 + + * - USB DFU + - 00000000 + - 11001010 + +For SW2 and SW1, the switch state in the "ON" position = 1. + +Debugging U-Boot +---------------- + +See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. warning:: + + **OpenOCD support since**: August 2023 (git master) + + Until the next stable release of OpenOCD is available in your development + environment's distribution, it might be necessary to build OpenOCD `from the + source <https://github.com/openocd-org/openocd>`_. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_XDS110 + :end-before: .. k3_rst_include_end_openocd_connect_XDS110 + +To start OpenOCD and connect to the board + +.. code-block:: bash + + openocd -f board/ti_am62a7evm.cfg diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index 113475d7c9d..a422a9bf1a0 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -48,7 +48,7 @@ support. Below is the pictorial representation of boot flow: Sources: -------- -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources @@ -56,17 +56,17 @@ Build procedure: ---------------- 0. Setup the environment variables: -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_common_env_vars_desc :end-before: .. k3_rst_include_end_common_env_vars_desc -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_board_env_vars_desc :end-before: .. k3_rst_include_end_board_env_vars_desc Set the variables corresponding to this platform: -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_common_env_vars_defn :end-before: .. k3_rst_include_end_common_env_vars_defn .. prompt:: bash $ @@ -84,14 +84,14 @@ Set the variables corresponding to this platform: 1. Trusted Firmware-A: -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_build_steps_tfa :end-before: .. k3_rst_include_end_build_steps_tfa 2. OP-TEE: -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_build_steps_optee :end-before: .. k3_rst_include_end_build_steps_optee @@ -99,13 +99,13 @@ Set the variables corresponding to this platform: * 3.1 R5: -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_build_steps_spl_r5 :end-before: .. k3_rst_include_end_build_steps_spl_r5 * 3.2 A72: -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_build_steps_uboot :end-before: .. k3_rst_include_end_build_steps_uboot .. j721e_evm_rst_include_end_build_steps @@ -249,7 +249,7 @@ detailed setup information. environment's distribution needs to be updated, it might be necessary to build OpenOCD from the source. -.. include:: k3.rst +.. include:: ../ti/k3.rst :start-after: .. k3_rst_include_start_openocd_connect_XDS110 :end-before: .. k3_rst_include_end_openocd_connect_XDS110 diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 5167925c9c6..f19ee56f296 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -30,12 +30,14 @@ K3 Based SoCs .. toctree:: :maxdepth: 1 - am62x_beagleplay + am62ax_sk am62x_sk + ../beagle/am62x_beagleplay ../toradex/verdin-am62 am64x_evm am65x_evm j7200_evm + ../beagle/j721e_beagleboneai64 j721e_evm j721s2_evm @@ -318,6 +320,13 @@ use the `lite` option. make CROSS_COMPILE=$CC64 BINMAN_INDIRS=$LNX_FW_PATH \ BL31=$TFA_PATH/build/k3/$TFA_BOARD/release/bl31.bin \ TEE=$OPTEE_PATH/out/arm-plat-k3/core/tee-raw.bin + +.. note:: + It is also possible to pick up a custom DM binary by adding TI_DM argument + pointing to the file. If not provided, it defaults to picking up the DM + binary from BINMAN_INDIRS. This is only applicable to devices that utilize + split firmware. + .. k3_rst_include_end_build_steps_uboot At this point you should have every binary needed initialize both the diff --git a/doc/build/clang.rst b/doc/build/clang.rst index cc265506c2f..09bb988e923 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -11,14 +11,6 @@ The ARM backend can be instructed not to use the r9 and x18 registers using supported inline assembly is needed to get and set the r9 or x18 value. This leads to larger code then strictly necessary, but at least works. -**NOTE:** target compilation only work for _some_ ARM boards at the moment. -Also AArch64 is not supported currently due to a lack of private libgcc -support. Boards which reassign gd in c will also fail to compile, but there is -in no strict reason to do so in the ARM world, since crt0.S takes care of this. -These assignments can be avoided by changing the init calls but this is not in -mainline yet. - - Debian based ------------ @@ -28,14 +20,20 @@ Required packages can be installed via apt, e.g. sudo apt-get install clang -Note that we still use binutils for some tools so we must continue to set -CROSS_COMPILE. To compile U-Boot with Clang on Linux without IAS use e.g. +We make use of the CROSS_COMPILE variable to derive the build target which is +passed as the --target parameter to clang. + +The CROSS_COMPILE variable further determines the paths to other build +tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as' +instead of the LLVM integrated assembler (IAS). + +Here is an example demonstrating building U-Boot for the Raspberry Pi 2 +using clang: .. code-block:: bash make HOSTCC=clang rpi_2_defconfig - make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- \ - CC="clang -target arm-linux-gnueabi" -j8 + make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- CC=clang -j8 It can also be used to compile sandbox: diff --git a/doc/build/documentation.rst b/doc/build/documentation.rst index 20b0fefa2d8..098c96a4c4f 100644 --- a/doc/build/documentation.rst +++ b/doc/build/documentation.rst @@ -37,7 +37,7 @@ The *htmldocs* target is used to build the HTML documentation. It uses the # Display the documentation in a graphical web browser x-www-browser doc/output/index.html -The HTML documentation is published at https://u-boot.readthedocs.io. The build +The HTML documentation is published at https://docs.u-boot.org. The build process for that site is controlled by the file *.readthedocs.yml*. Infodoc documentation diff --git a/doc/chromium/files/chromebook_jerry.its b/doc/chromium/files/chromebook_jerry.its index 7505a20535b..02e5e1340f3 100644 --- a/doc/chromium/files/chromebook_jerry.its +++ b/doc/chromium/files/chromebook_jerry.its @@ -15,7 +15,7 @@ load = <0>; entry = <0>; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -26,7 +26,7 @@ arch = "arm"; compression = "none"; hash-1{ - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/chromium/files/nyan-big.its b/doc/chromium/files/nyan-big.its index bd412915e95..60bdffbb829 100644 --- a/doc/chromium/files/nyan-big.its +++ b/doc/chromium/files/nyan-big.its @@ -15,7 +15,7 @@ load = <0>; entry = <0>; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -26,7 +26,7 @@ arch = "arm"; compression = "none"; hash-1{ - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 37e9fc1a34d..8fe77f23b6e 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -72,7 +72,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2024.01-rc4 was released on Mon 04 December 2023. -.. * U-Boot v2024.01-rc5 was released on Mon 18 December 2023. +* U-Boot v2024.01-rc5 was released on Mon 18 December 2023. .. * U-Boot v2024.01-rc6 was released on Tue 02 January 2024. diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index ba73d0d11b4..5a6962f1021 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -363,7 +363,7 @@ A Custodian has additional privileges and can: * Awaiting Upstream - * Superseeded + * Superseded * Deferred @@ -399,7 +399,7 @@ today. Not all states are used by all custodians. and has not merged yet to master, or has queued the patch up to be submitted to be merged, but has not yet. -* Superseeded: Patches are marked as 'superseeded' when the poster submits a +* Superseded: Patches are marked as 'superseded' when the poster submits a new version of these patches. * Deferred: Deferred usually means the patch depends on something else that diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index fb16ac743a0..6bc9d92285b 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -642,6 +642,40 @@ UEFI variables. Booting according to these variables is possible via:: As of U-Boot v2020.10 UEFI variables cannot be set at runtime. The U-Boot command 'efidebug' can be used to set the variables. +UEFI HTTP Boot +~~~~~~~~~~~~~~ + +HTTP Boot provides the capability for system deployment and configuration +over the network. HTTP Boot can be activated by specifying:: + + CONFIG_EFI_HTTP_BOOT + +Enabling that will automatically select:: + + CONFIG_CMD_DNS + CONFIG_CMD_WGET + CONFIG_BLKMAP + +Set up the load option specifying the target URI:: + + efidebug boot add -u 1 netinst http://foo/bar + +When this load option is selected as boot selection, resolve the +host ip address by dns, then download the file with wget. +If the downloaded file extension is .iso or .img file, efibootmgr tries to +mount the image and boot with the default file(e.g. EFI/BOOT/BOOTAA64.EFI). +If the downloaded file is PE-COFF image, load the downloaded file and +start it. + +The current implementation tries to resolve the IP address as a host name. +If the uri is like "http://192.168.1.1/foobar", +the dns process tries to resolve the host "192.168.1.1" and it will +end up with "host not found". + +We need to preset the "httpserverip" environment variable to proceed the wget:: + + setenv httpserverip 192.168.1.1 + Executing the built in hello world application ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/device-tree-bindings/leds/leds-lp5562.txt b/doc/device-tree-bindings/leds/leds-lp5562.txt new file mode 100644 index 00000000000..4e0c742959a --- /dev/null +++ b/doc/device-tree-bindings/leds/leds-lp5562.txt @@ -0,0 +1,63 @@ +LEDs connected to TI LP5562 controller + +This driver works with a TI LP5562 4-channel LED controller. +CONFIG_LED_BLINK is supported using the controller engines. However +there are only 3 engines available for the 4 channels. This means +that the blue and white channels share the same engine. When both +blue and white LEDs are set to blink, they will share the same blink +rate. Changing the blink rate of the blue LED will affect the white +LED and vice-versa. Manual on/off is handled independently for all 4 +channels. + +Required properties: + - compatible : should be "ti,lp5562". + - #address-cells : must be 1. + - #size-cells : must be 0. + - reg : LP5562 LED controller I2C address. + +Optional properties: + - enable-gpios : Enable GPIO + - clock-mode : u8, configures the clock mode: + - 0 # automode + - 1 # internal + - 2 # external + +Each LED is represented as a sub-node of the ti,lp5562 device. + +LED sub-node required properties: + - reg : Zero-based channel identifier: + - 0 red + - 1 green + - 2 blue + - 3 white + +LED sub-node optional properties: + - chan-name : name of LED + - max-cur : LED current at max brightness in 100uA steps (0x00 - 0xFF) + Default : 100 (10 mA) + +Example: + leds0: lp5562@30 { + compatible = "ti,lp5562"; + #address-cells = <1>; + #size-cells = <0>; + enable-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + reg = <0x30>; + clock-mode = /bits/8 <1>; + + led@0 { + reg = <0>; + chan-name = "red"; + max-cur = /bits/ 8 <200>; /* 20mA */ + }; + led@1 { + reg = <1>; + chan-name = "green"; + max-cur = /bits/ 8 <200>; /* 20mA */ + }; + led@2 { + reg = <2>; + chan-name = "blue"; + max-cur = /bits/ 8 <200>; /* 20mA */ + }; + }; diff --git a/doc/device-tree-bindings/misc/esm-k3.txt b/doc/device-tree-bindings/misc/esm-k3.txt deleted file mode 100644 index 01c8b6b294b..00000000000 --- a/doc/device-tree-bindings/misc/esm-k3.txt +++ /dev/null @@ -1,25 +0,0 @@ -Texas Instruments K3 ESM Binding -====================== - -ESM (Error Signaling Module) is an IP block on TI K3 devices that allows -handling of safety events somewhat similar to what interrupt controller -would do. The safety signals have their separate paths within the SoC, -and they are handled by the ESM, which routes them to the proper -destination, which can be system reset, interrupt controller, etc. In -the simplest configuration the signals are just routed to reset the -SoC. - -Required properties : -- compatible : "ti,j721e-esm" -- ti,esm-pins : integer array of esm events IDs to route to external event - pin which can be used to reset the SoC. The array can - have arbitrary amount of event IDs listed on it. - -Example -======= - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x700000 0x0 0x1000>; - ti,esm-pins = <344>, <345>; - }; diff --git a/doc/device-tree-bindings/misc/ti,j721e-esm.yaml b/doc/device-tree-bindings/misc/ti,j721e-esm.yaml new file mode 100644 index 00000000000..0c9a8444844 --- /dev/null +++ b/doc/device-tree-bindings/misc/ti,j721e-esm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 ESM + +maintainers: + - Neha Malcom Francis <n-francis@ti.com> + +description: + The ESM (Error Signaling Module) is an IP block on TI K3 devices + that allows handling of safety events somewhat similar to what interrupt + controller would do. The safety signals have their separate paths within + the SoC, and they are handled by the ESM, which routes them to the proper + destination, which can be system reset, interrupt controller, etc. In the + simplest configuration the signals are just routed to reset the SoC. + +properties: + compatible: + const: ti,j721e-esm + + reg: + maxItems: 1 + + ti,esm-pins: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + integer array of ESM interrupt pins to route to external event pin + which can be used to reset the SoC. + minItems: 1 + maxItems: 255 + +required: + - compatible + - reg + - ti,esm-pins + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; + }; diff --git a/doc/device-tree-bindings/nand/sandbox,nand.txt b/doc/device-tree-bindings/nand/sandbox,nand.txt new file mode 100644 index 00000000000..0a723d7c058 --- /dev/null +++ b/doc/device-tree-bindings/nand/sandbox,nand.txt @@ -0,0 +1,57 @@ +Sandbox NAND +============ + +The sandbox NAND controller emulates a NAND controller and attached devices. + +Required properties: +- compatible: "sandbox,nand" +- #address-cells: Must be 1 +- #size-cells: Must be 0 + +Any number of child nodes may be present, each representing a NAND device: + +Required Properties: +- reg: The chip-select(s) to use. Only single-die devices are supported for now. +- sandbox,id: An array of bytes to be reported by the READID (0x90) command +- sandbox,erasesize: The block size (erase size) of the device, in bytes. Must + be a power-of-two multiple of the page size. +- sandbox,oobsize: The size of the OOB area per page, in bytes. +- sandbox,pagesize: The page size (write size) of the device, in bytes. Must be + a power of two. +- sandbox,pages: The total number of pages in the device. +- sandbox,err-count: Number of bit errors to inject per step. +- sandbox,err-step-size: Size of the step to use when injecting errors, in + bytes. Must evenly divide the page size. + +Optional properties: +- sandbox,onfi: The complete ONFI parameter page, including the CRC. Should be + exactly 256 bytes. +- Any common NAND chip properties as documented by Linux's + Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml + +To match U-Boot's error correction capabilities, errors are only injected into +the data area and the ECC codes. Other data in the OOB area is never corrupted. +Generally, sandbox,err-step-size should be the same as the ECC step size, and +sandbox,err-count should be less than the number of correctable bit errors (the +ECC strength). + +Example +------- + +nand-controller { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sandbox,nand"; + + nand@0 { + reg = <0>; + nand-ecc-mode = "soft"; + sandbox,id = [00 e3]; + sandbox,erasesize = <(8 * 1024)>; + sandbox,oobsize = <16>; + sandbox,pagesize = <512>; + sandbox,pages = <0x2000>; + sandbox,err-count = <1>; + sandbox,err-step-size = <512>; + }; +}; diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst index 2198ff60493..27e1330ad8a 100644 --- a/doc/usage/cmd/bootflow.rst +++ b/doc/usage/cmd/bootflow.rst @@ -52,6 +52,8 @@ Flags are: matters, since by then the system boots in the OS and U-Boot is no-longer running. `bootflow scan -b` is a quick way to boot the first available OS. A valid bootflow is one that made it all the way to the `loaded` state. + Note that if `-m` is provided as well, booting is delayed until the user + selects a bootflow. -e Used with -l to also show errors for each bootflow. The shows detailed error @@ -71,6 +73,9 @@ Flags are: priority or label is tried, to see if more bootdevs can be discovered, but this flag disables that process. +-m + Show a menu of available bootflows for the user to select. When used with + -b it then boots the one that was selected, if any. The optional argument specifies a particular bootdev to scan. This can either be the name of a bootdev or its sequence number (both shown with `bootdev list`). diff --git a/doc/usage/cmd/imxtract.rst b/doc/usage/cmd/imxtract.rst index eb64b1cefab..16be60b4aab 100644 --- a/doc/usage/cmd/imxtract.rst +++ b/doc/usage/cmd/imxtract.rst @@ -45,14 +45,14 @@ Examples With verify=no incorrect hashes, signatures, or check sums don't stop the extraction. But correct hashes are still indicated in the output -(here: md5, sha1). +(here: sha256, sha512). .. code-block:: console => setenv verify no => imxtract $loadaddr kernel-1 $kernel_addr_r ## Copying 'kernel-1' subimage from FIT image at 40200000 ... - md5+ sha1+ Loading part 0 ... OK + sha256+ sha512+ Loading part 0 ... OK => With verify=yes incorrect hashes, signatures, or check sums stop the extraction. @@ -62,7 +62,7 @@ With verify=yes incorrect hashes, signatures, or check sums stop the extraction. => setenv verify yes => imxtract $loadaddr kernel-1 $kernel_addr_r ## Copying 'kernel-1' subimage from FIT image at 40200000 ... - md5 error! + sha256 error! Bad hash value for 'hash-1' hash node in 'kernel-1' image node Bad Data Hash => diff --git a/doc/usage/cmd/scmi.rst b/doc/usage/cmd/scmi.rst new file mode 100644 index 00000000000..9ea7e0e41da --- /dev/null +++ b/doc/usage/cmd/scmi.rst @@ -0,0 +1,126 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +scmi command +============ + +Synopsis +-------- + +:: + + scmi info + scmi perm_dev <agent id> <device id> <flags> + scmi perm_proto <agent id> <device id> <protocol id> <flags> + scmi reset <agent id> <flags> + +Description +----------- + +Arm System Control and Management Interface (SCMI hereafter) is a set of +standardised interfaces to manage system resources, like clocks, power +domains, pin controls, reset and so on, in a system-wide manner. + +An entity which provides those services is called a SCMI firmware (or +SCMI server if you like) may be placed/implemented by EL3 software or +by a dedicated system control processor (SCP) or else. + +A user of SCMI interfaces, including U-Boot, is called a SCMI agent and +may issues commands, which are defined in each protocol for specific system +resources, to SCMI server via a communication channel, called a transport. +Those interfaces are independent from the server's implementation thanks to +a transport layer. + +For more details, see the `SCMI specification`_. + +While most of system resources managed under SCMI protocols are implemented +and handled as standard U-Boot devices, for example clk_scmi, scmi command +provides additional management functionality against SCMI server. + +scmi info +~~~~~~~~~ + Show base information about SCMI server and supported protocols + +scmi perm_dev +~~~~~~~~~~~~~ + Allow or deny access permission to the device + +scmi perm_proto +~~~~~~~~~~~~~~~ + Allow or deny access to the protocol on the device + +scmi reset +~~~~~~~~~~ + Reset the already-configured permissions against the device + +Parameters are used as follows: + +<agent id> + SCMI Agent ID, hex value + +<device id> + SCMI Device ID, hex value + + Please note that what a device means is not defined + in the specification. + +<protocol id> + SCMI Protocol ID, hex value + + It must not be 0x10 (base protocol) + +<flags> + Flags to control the action, hex value + + 0 to deny, 1 to allow. The other values are reserved and allowed + values may depend on the implemented version of SCMI server in + the future. See SCMI specification for more details. + +Example +------- + +Obtain basic information about SCMI server: + +:: + + => scmi info + SCMI device: scmi + protocol version: 0x20000 + # of agents: 3 + 0: platform + > 1: OSPM + 2: PSCI + # of protocols: 4 + Power domain management + Performance domain management + Clock management + Sensor management + vendor: Linaro + sub vendor: PMWG + impl version: 0x20b0000 + +Ask for access permission to device#0: + +:: + + => scmi perm_dev 1 0 1 + +Reset configurations with all access permission settings retained: + +:: + + => scmi reset 1 0 + +Configuration +------------- + +The scmi command is only available if CONFIG_CMD_SCMI=y. +Default n because this command is mainly for debug purpose. + +Return value +------------ + +The return value ($?) is set to 0 if the operation succeeded, +1 if the operation failed or -1 if the operation failed due to +a syntax error. + +.. _`SCMI specification`: https://developer.arm.com/documentation/den0056/e/?lang=en diff --git a/doc/usage/fit/beaglebone_vboot.rst b/doc/usage/fit/beaglebone_vboot.rst index a102be187bd..cd6bb141910 100644 --- a/doc/usage/fit/beaglebone_vboot.rst +++ b/doc/usage/fit/beaglebone_vboot.rst @@ -145,7 +145,7 @@ Put this into a file in that directory called sign.its:: load = <0x80008000>; entry = <0x80008000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; fdt-1 { @@ -155,7 +155,7 @@ Put this into a file in that directory called sign.its:: arch = "arm"; compression = "none"; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; }; @@ -165,7 +165,7 @@ Put this into a file in that directory called sign.its:: kernel = "kernel"; fdt = "fdt-1"; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; }; @@ -227,8 +227,8 @@ You should see something like this:: OS: Linux Load Address: 0x80008000 Entry Point: 0x80008000 - Hash algo: sha1 - Hash value: c94364646427e10f423837e559898ef02c97b988 + Hash algo: sha256 + Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1 Image 1 (fdt-1) Description: beaglebone-black Created: Sun Jun 1 12:50:30 2014 @@ -236,8 +236,8 @@ You should see something like this:: Compression: uncompressed Data Size: 31547 Bytes = 30.81 kB = 0.03 MB Architecture: ARM - Hash algo: sha1 - Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Hash algo: sha256 + Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd Default Configuration: 'conf-1' Configuration 0 (conf-1) Description: unavailable @@ -255,11 +255,11 @@ You can also run fit_check_sign to check it:: which results in:: - Verifying Hash Integrity ... sha1,rsa2048:dev+ + Verifying Hash Integrity ... sha256,rsa2048:dev+ ## Loading kernel from FIT Image at 7fc6ee469000 ... Using 'conf-1' configuration Verifying Hash Integrity ... - sha1,rsa2048:dev+ + sha256,rsa2048:dev+ OK Trying 'kernel' kernel subimage @@ -272,10 +272,10 @@ which results in:: OS: Linux Load Address: 0x80008000 Entry Point: 0x80008000 - Hash algo: sha1 - Hash value: c94364646427e10f423837e559898ef02c97b988 + Hash algo: sha256 + Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1 Verifying Hash Integrity ... - sha1+ + sha256+ OK Unimplemented compression type 4 @@ -288,10 +288,10 @@ which results in:: Compression: uncompressed Data Size: 31547 Bytes = 30.81 kB = 0.03 MB Architecture: ARM - Hash algo: sha1 - Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Hash algo: sha256 + Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd Verifying Hash Integrity ... - sha1+ + sha256+ OK Loading Flat Device Tree ... OK @@ -303,14 +303,14 @@ which results in:: Signature check OK -At the top, you see "sha1,rsa2048:dev+". This means that it checked an RSA key -of size 2048 bits using SHA1 as the hash algorithm. The key name checked was +At the top, you see "sha256,rsa2048:dev+". This means that it checked an RSA key +of size 2048 bits using SHA256 as the hash algorithm. The key name checked was 'dev' and the '+' means that it verified. If it showed '-' that would be bad. Once the configuration is verified it is then possible to rely on the hashes in each image referenced by that configuration. So fit_check_sign goes on to load each of the images. We have a kernel and an FDT but no ramkdisk. In each -case fit_check_sign checks the hash and prints sha1+ meaning that the SHA1 +case fit_check_sign checks the hash and prints sha256+ meaning that the SHA256 hash verified. This means that none of the images has been tampered with. There is a test in test/vboot which uses U-Boot's sandbox build to verify that @@ -328,11 +328,11 @@ This tells us that the kernel starts at byte offset 168 (decimal) in image.fit and extends for about 7MB. Try changing a byte at 0x2000 (say) and run fit_check_sign again. You should see something like:: - Verifying Hash Integrity ... sha1,rsa2048:dev+ + Verifying Hash Integrity ... sha256,rsa2048:dev+ ## Loading kernel from FIT Image at 7f5a39571000 ... Using 'conf-1' configuration Verifying Hash Integrity ... - sha1,rsa2048:dev+ + sha256,rsa2048:dev+ OK Trying 'kernel' kernel subimage @@ -345,10 +345,10 @@ fit_check_sign again. You should see something like:: OS: Linux Load Address: 0x80008000 Entry Point: 0x80008000 - Hash algo: sha1 - Hash value: c94364646427e10f423837e559898ef02c97b988 + Hash algo: sha256 + Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1 Verifying Hash Integrity ... - sha1 error + sha256 error Bad hash value for 'hash-1' hash node in 'kernel' image node Bad Data Hash @@ -361,10 +361,10 @@ fit_check_sign again. You should see something like:: Compression: uncompressed Data Size: 31547 Bytes = 30.81 kB = 0.03 MB Architecture: ARM - Hash algo: sha1 - Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Hash algo: sha256 + Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd Verifying Hash Integrity ... - sha1+ + sha256+ OK Loading Flat Device Tree ... OK @@ -419,13 +419,13 @@ need to change the hash to match. Let's simulate that by changing a byte of the hash:: fdtget -tx image.fit /images/kernel/hash-1 value - c9436464 6427e10f 423837e5 59898ef0 2c97b988 - fdtput -tx image.fit /images/kernel/hash-1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981 + 51b2adf9 c1016ed4 6f424d85 dcc6c34c 46a20b9b ee7227e0 6a6b6320 ca5d35c1 + fdtput -tx image.fit /images/kernel/hash-1 value 51b2adf9 c1016ed4 6f424d85 dcc6c34c 46a20b9b ee7227e0 6a6b6320 ca5d35c8 Now check it again:: $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb - Verifying Hash Integrity ... sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 + Verifying Hash Integrity ... sha256,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 rsa_verify_with_keynode: RSA failed to verify: -13 - Failed to verify required signature 'key-dev' @@ -446,7 +446,7 @@ running the mkimage link again. Then:: fdtput -p image.fit /configurations/conf-1/signature-1 value fred $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb Verifying Hash Integrity ... - - sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 + sha256,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 rsa_verify_with_keynode: RSA failed to verify: -13 - Failed to verify required signature 'key-dev' @@ -528,7 +528,7 @@ You should then see something like this:: U-Boot# bootm 82000000 ## Loading kernel from FIT Image at 82000000 ... Using 'conf-1' configuration - Verifying Hash Integrity ... sha1,rsa2048:dev+ OK + Verifying Hash Integrity ... sha256,rsa2048:dev+ OK Trying 'kernel' kernel subimage Description: unavailable Created: 2014-06-01 19:32:54 UTC @@ -540,9 +540,9 @@ You should then see something like this:: OS: Linux Load Address: 0x80008000 Entry Point: 0x80008000 - Hash algo: sha1 - Hash value: c94364646427e10f423837e559898ef02c97b988 - Verifying Hash Integrity ... sha1+ OK + Hash algo: sha256 + Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1 + Verifying Hash Integrity ... sha256+ OK ## Loading fdt from FIT Image at 82000000 ... Using 'conf-1' configuration Trying 'fdt-1' fdt subimage @@ -553,9 +553,9 @@ You should then see something like this:: Data Start: 0x8276e2ec Data Size: 31547 Bytes = 30.8 KiB Architecture: ARM - Hash algo: sha1 - Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d - Verifying Hash Integrity ... sha1+ OK + Hash algo: sha256 + Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd + Verifying Hash Integrity ... sha256+ OK Booting using the fdt blob at 0x8276e2ec Uncompressing Kernel Image ... OK Loading Device Tree to 8fff5000, end 8ffffb3a ... OK diff --git a/doc/usage/fit/howto.rst b/doc/usage/fit/howto.rst index def12a70f7b..b5097d4460b 100644 --- a/doc/usage/fit/howto.rst +++ b/doc/usage/fit/howto.rst @@ -8,7 +8,7 @@ Overview The new uImage format allows more flexibility in handling images of various types (kernel, ramdisk, etc.), it also enhances integrity protection of images -with sha1 and md5 checksums. +with cryptographic checksums. Two auxiliary tools are needed on the development host system in order to create an uImage in the new format: mkimage and dtc, although only one @@ -99,7 +99,7 @@ started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware). load = <0x8 0x8000000>; entry = <0x8 0x8000000>; hash { - algo = "md5"; + algo = "sha256"; }; }; atf { @@ -112,7 +112,7 @@ started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware). load = <0xfffea000>; entry = <0xfffea000>; hash { - algo = "md5"; + algo = "sha256"; }; }; fdt_1 { @@ -123,7 +123,7 @@ started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware). compression = "none"; load = <0x100000>; hash { - algo = "md5"; + algo = "sha256"; }; }; }; @@ -190,8 +190,8 @@ its contents: Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2ae2bb40 - Hash algo: sha1 - Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4 + Hash algo: sha256 + Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f Default Configuration: 'config-1' Configuration 0 (config-1) Description: Boot Linux kernel @@ -236,8 +236,8 @@ specific to the new image format). Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2ae2bb40 - Hash algo: sha1 - Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4 + Hash algo: sha256 + Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f Default Configuration: 'config-1' Configuration 0 (config-1) Description: Boot Linux kernel @@ -258,8 +258,8 @@ specific to the new image format). Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2ae2bb40 - Hash algo: sha1 - Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4 + Hash algo: sha256 + Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f Verifying Hash Integrity ... crc32+ sha1+ OK Uncompressing Kernel Image ... OK Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb @@ -302,8 +302,8 @@ modified to take the files from some other location if needed): Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2c0cc807 - Hash algo: sha1 - Hash value: 264b59935470e42c418744f83935d44cdf59a3bb + Hash algo: sha256 + Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c Image 1 (fdt-1) Description: Flattened Device Tree blob Type: Flat Device Tree @@ -312,8 +312,8 @@ modified to take the files from some other location if needed): Architecture: PowerPC Hash algo: crc32 Hash value: 0d655d71 - Hash algo: sha1 - Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def + Hash algo: sha256 + Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214 Default Configuration: 'conf-1' Configuration 0 (conf-1) Description: Boot Linux kernel with FDT blob @@ -353,8 +353,8 @@ inspected and booted: Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2c0cc807 - Hash algo: sha1 - Hash value: 264b59935470e42c418744f83935d44cdf59a3bb + Hash algo: sha256 + Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c Image 1 (fdt-1) Description: Flattened Device Tree blob Type: Flat Device Tree @@ -364,8 +364,8 @@ inspected and booted: Architecture: PowerPC Hash algo: crc32 Hash value: 0d655d71 - Hash algo: sha1 - Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def + Hash algo: sha256 + Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214 Default Configuration: 'conf-1' Configuration 0 (conf-1) Description: Boot Linux kernel with FDT blob @@ -387,7 +387,7 @@ inspected and booted: Hash algo: crc32 Hash value: 2c0cc807 Hash algo: sha1 - Hash value: 264b59935470e42c418744f83935d44cdf59a3bb + Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c Verifying Hash Integrity ... crc32+ sha1+ OK Uncompressing Kernel Image ... OK ## Flattened Device Tree from FIT Image at 00900000 @@ -402,7 +402,7 @@ inspected and booted: Hash algo: crc32 Hash value: 0d655d71 Hash algo: sha1 - Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def + Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214 Verifying Hash Integrity ... crc32+ sha1+ OK Booting using the fdt blob at 0xa0abdc Loading Device Tree to 007fc000, end 007fffff ... OK diff --git a/doc/usage/fit/kernel.rst b/doc/usage/fit/kernel.rst index 012a81efead..e56017985b2 100644 --- a/doc/usage/fit/kernel.rst +++ b/doc/usage/fit/kernel.rst @@ -25,7 +25,7 @@ Single kernel algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; }; @@ -59,7 +59,7 @@ For x86 a setup node is also required: see x86-fit-boot:: load = <0x01000000>; entry = <0x00000000>; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -73,7 +73,7 @@ For x86 a setup node is also required: see x86-fit-boot:: load = <0x00090000>; entry = <0x00090000>; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/kernel_fdt.rst b/doc/usage/fit/kernel_fdt.rst index 8eee13af780..9cc26fb7831 100644 --- a/doc/usage/fit/kernel_fdt.rst +++ b/doc/usage/fit/kernel_fdt.rst @@ -25,7 +25,7 @@ Single kernel and FDT blob algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; fdt-1 { @@ -38,7 +38,7 @@ Single kernel and FDT blob algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/kernel_fdts_compressed.rst b/doc/usage/fit/kernel_fdts_compressed.rst index 0b169c7c27c..b57871da58b 100644 --- a/doc/usage/fit/kernel_fdts_compressed.rst +++ b/doc/usage/fit/kernel_fdts_compressed.rst @@ -28,7 +28,7 @@ string to match directly. algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; fdt@1 { @@ -41,7 +41,7 @@ string to match directly. algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; fdt@2 { @@ -54,7 +54,7 @@ string to match directly. algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/multi-with-fpga.rst b/doc/usage/fit/multi-with-fpga.rst index 28d7d5d2626..4c7f1bebd5a 100644 --- a/doc/usage/fit/multi-with-fpga.rst +++ b/doc/usage/fit/multi-with-fpga.rst @@ -20,7 +20,7 @@ This example makes use of the 'loadables' field:: compression = "none"; load = <0x10000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -33,7 +33,7 @@ This example makes use of the 'loadables' field:: load = <0x30000000>; compatible = "u-boot,fpga-legacy" hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -47,7 +47,7 @@ This example makes use of the 'loadables' field:: load = <0x8000>; entry = <0x8000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/multi-with-loadables.rst b/doc/usage/fit/multi-with-loadables.rst index a0241df96ca..7849cb544f1 100644 --- a/doc/usage/fit/multi-with-loadables.rst +++ b/doc/usage/fit/multi-with-loadables.rst @@ -22,7 +22,7 @@ This example makes use of the 'loadables' field:: load = <0xa0000000>; entry = <0xa0000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -34,7 +34,7 @@ This example makes use of the 'loadables' field:: compression = "none"; load = <0xb0000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -46,7 +46,7 @@ This example makes use of the 'loadables' field:: compression = "none"; load = <0xb0400000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -60,7 +60,7 @@ This example makes use of the 'loadables' field:: load = <0xa0000000>; entry = <0xa0000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/multi.rst b/doc/usage/fit/multi.rst index 2e6ae58c409..e68752b2ad0 100644 --- a/doc/usage/fit/multi.rst +++ b/doc/usage/fit/multi.rst @@ -22,10 +22,10 @@ Multiple kernels, ramdisks and FDT blobs load = <00000000>; entry = <00000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; hash-2 { - algo = "sha1"; + algo = "sha512"; }; }; @@ -39,7 +39,7 @@ Multiple kernels, ramdisks and FDT blobs load = <00000000>; entry = <00000000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -53,7 +53,7 @@ Multiple kernels, ramdisks and FDT blobs load = <00000000>; entry = <00000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -67,7 +67,7 @@ Multiple kernels, ramdisks and FDT blobs load = <00000000>; entry = <00000000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -104,7 +104,7 @@ Multiple kernels, ramdisks and FDT blobs compression = "none"; load = <00700000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; diff --git a/doc/usage/fit/sign-configs.rst b/doc/usage/fit/sign-configs.rst index 6a3df8f2c5b..6d98d44430c 100644 --- a/doc/usage/fit/sign-configs.rst +++ b/doc/usage/fit/sign-configs.rst @@ -22,7 +22,7 @@ Signed configurations entry = <0x8>; kernel-version = <1>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; fdt-1 { @@ -33,7 +33,7 @@ Signed configurations compression = "none"; fdt-version = <1>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; }; @@ -43,7 +43,7 @@ Signed configurations kernel = "kernel"; fdt = "fdt-1"; signature { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; }; diff --git a/doc/usage/fit/sign-images.rst b/doc/usage/fit/sign-images.rst index 7d54d702c97..ca7d10fab83 100644 --- a/doc/usage/fit/sign-images.rst +++ b/doc/usage/fit/sign-images.rst @@ -22,7 +22,7 @@ Signed Images entry = <0x8>; kernel-version = <1>; signature { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; @@ -34,7 +34,7 @@ Signed Images compression = "none"; fdt-version = <1>; signature { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; diff --git a/doc/usage/fit/signature.rst b/doc/usage/fit/signature.rst index 0804bffd1ed..39edba14630 100644 --- a/doc/usage/fit/signature.rst +++ b/doc/usage/fit/signature.rst @@ -93,7 +93,7 @@ Public keys should be stored as sub-nodes in a /signature node. Required properties are: algo - Algorithm name (e.g. "sha1,rsa2048" or "sha256,ecdsa256") + Algorithm name (e.g. "sha256,rsa2048" or "sha512,ecdsa256") Optional properties are: @@ -219,28 +219,28 @@ As an example, consider this FIT:: kernel-1 { data = <data for kernel1> signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...kernel signature 1...> }; }; kernel-2 { data = <data for kernel2> signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...kernel signature 2...> }; }; fdt-1 { data = <data for fdt1>; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...fdt signature 1...> }; }; fdt-2 { data = <data for fdt2>; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...fdt signature 2...> }; }; @@ -291,28 +291,28 @@ So the above example is adjusted to look like this:: kernel-1 { data = <data for kernel1> hash-1 { - algo = "sha1"; + algo = "sha256"; value = <...kernel hash 1...> }; }; kernel-2 { data = <data for kernel2> hash-1 { - algo = "sha1"; + algo = "sha256"; value = <...kernel hash 2...> }; }; fdt-1 { data = <data for fdt1>; hash-1 { - algo = "sha1"; + algo = "sha256"; value = <...fdt hash 1...> }; }; fdt-2 { data = <data for fdt2>; hash-1 { - algo = "sha1"; + algo = "sha256"; value = <...fdt hash 2...> }; }; @@ -323,7 +323,7 @@ So the above example is adjusted to look like this:: kernel = "kernel-1"; fdt = "fdt-1"; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...conf 1 signature...>; }; }; @@ -331,7 +331,7 @@ So the above example is adjusted to look like this:: kernel = "kernel-2"; fdt = "fdt-2"; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...conf 1 signature...>; }; }; diff --git a/doc/usage/fit/update3.rst b/doc/usage/fit/update3.rst index 4ff3950c01e..24235801470 100644 --- a/doc/usage/fit/update3.rst +++ b/doc/usage/fit/update3.rst @@ -19,7 +19,7 @@ Automatic software update: multiple files type = "firmware"; load = <FF700000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; update-2 { @@ -29,7 +29,7 @@ Automatic software update: multiple files type = "firmware"; load = <FF8E0000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -40,7 +40,7 @@ Automatic software update: multiple files type = "firmware"; load = <FFAC0000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/update_uboot.rst b/doc/usage/fit/update_uboot.rst index a9288ee6367..811d008d13d 100644 --- a/doc/usage/fit/update_uboot.rst +++ b/doc/usage/fit/update_uboot.rst @@ -21,7 +21,7 @@ Make sure the flashing addresses ('load' prop) is correct for your board! type = "firmware"; load = <0xFFFC0000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/x86-fit-boot.rst b/doc/usage/fit/x86-fit-boot.rst index 93b73bb9019..9e3e32204d5 100644 --- a/doc/usage/fit/x86-fit-boot.rst +++ b/doc/usage/fit/x86-fit-boot.rst @@ -207,16 +207,16 @@ You can take a look at the resulting fit file if you like:: OS: Linux Load Address: 0x01000000 Entry Point: 0x00000000 - Hash algo: sha1 - Hash value: 446b5163ebfe0fb6ee20cbb7a8501b263cd92392 + Hash algo: sha256 + Hash value: 4bbf49981ade163ed089f8525236fedfe44508e9b02a21a48294a96a1518107b Image 1 (setup) Description: Linux setup.bin Created: Tue Oct 7 10:57:24 2014 Type: x86 setup.bin Compression: uncompressed Data Size: 12912 Bytes = 12.61 kB = 0.01 MB - Hash algo: sha1 - Hash value: a1f2099cf47ff9816236cd534c77af86e713faad + Hash algo: sha256 + Hash value: 6aa50c2e0392cb119cdf0971dce8339f100608ed3757c8200b0e39e889e432d2 Default Configuration: 'config-1' Configuration 0 (config-1) Description: Boot Linux kernel diff --git a/doc/usage/index.rst b/doc/usage/index.rst index d8e23fcacff..1a626c03c23 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -94,6 +94,7 @@ Shell commands cmd/rng cmd/saves cmd/sbi + cmd/scmi cmd/scp03 cmd/seama cmd/setexpr diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 049f7efd10b..9bc5283c268 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -20,14 +20,6 @@ config SATA See also CMD_SATA which provides command-line support. -config SYS_SATA_MAX_PORTS - int "Maximum supported SATA ports" - depends on SCSI_AHCI && !DM_SCSI - default 1 - help - Sets the maximum number of ports to scan when looking for devices. - Ports from 0 to (this value - 1) are scanned. - config LIBATA bool help @@ -44,7 +36,7 @@ menu "SATA/SCSI device support" config AHCI_PCI bool "Support for PCI-based AHCI controller" depends on PCI - depends on DM_SCSI + depends on SCSI depends on SCSI_AHCI help Enables support for the PCI-based AHCI controller. @@ -55,13 +47,13 @@ config SPL_AHCI_PCI bool "Support for PCI-based AHCI controller for SPL" depends on SPL depends on SPL_PCI - depends on SPL_SATA && DM_SCSI + depends on SPL_SATA && SCSI config DWC_AHCI bool "Enable Synopsys DWC AHCI driver support" select SCSI_AHCI select PHY - depends on DM_SCSI + depends on SCSI help Enable this driver to support Sata devices through Synopsys DWC AHCI module. @@ -91,7 +83,7 @@ config AHCI_MVEBU bool "Marvell EBU AHCI SATA support" depends on ARCH_MVEBU || ARCH_OCTEON select SCSI_AHCI - select DM_SCSI + select SCSI help This option enables support for the Marvell EBU SoC's onboard AHCI SATA. @@ -112,7 +104,7 @@ if SATA config SATA_CEVA bool "Ceva Sata controller" depends on AHCI - depends on DM_SCSI + depends on SCSI help This option enables Ceva Sata controller hard IP available on Xilinx ZynqMP. Support up to 2 external devices. Compliant with SATA 3.1 and diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 0b6f91098a3..af6f0bf2780 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_SATA) += sata.o sata_bootdev.o obj-$(CONFIG_SATA_CEVA) += sata_ceva.o obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL) += sata_sil.o -obj-$(CONFIG_SANDBOX) += sata_sandbox.o obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index cb2c648a91f..04ddc339464 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -33,10 +33,6 @@ static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port); -#ifndef CONFIG_DM_SCSI -struct ahci_uc_priv *probe_ent = NULL; -#endif - #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) /* @@ -169,11 +165,6 @@ int ahci_reset(void __iomem *base) static int ahci_host_init(struct ahci_uc_priv *uc_priv) { -#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) - struct udevice *dev = uc_priv->dev; - struct pci_child_plat *pplat = dev_get_parent_plat(dev); - u16 tmp16; -#endif void __iomem *mmio = uc_priv->mmio_base; u32 tmp, cap_save, cmd; int i, j, ret; @@ -194,14 +185,6 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) writel(cap_save, mmio + HOST_CAP); writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); -#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) - if (pplat->vendor == PCI_VENDOR_ID_INTEL) { - u16 tmp16; - - dm_pci_read_config16(dev, 0x92, &tmp16); - dm_pci_write_config16(dev, 0x92, tmp16 | 0xf); - } -#endif uc_priv->cap = readl(mmio + HOST_CAP); uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL); port_map = uc_priv->port_map; @@ -210,11 +193,6 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) debug("cap 0x%x port_map 0x%x n_ports %d\n", uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); -#if !defined(CONFIG_DM_SCSI) - if (uc_priv->n_ports > CONFIG_SYS_SATA_MAX_PORTS) - uc_priv->n_ports = CONFIG_SYS_SATA_MAX_PORTS; -#endif - for (i = 0; i < uc_priv->n_ports; i++) { if (!(port_map & (1 << i))) continue; @@ -313,23 +291,12 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); tmp = readl(mmio + HOST_CTL); debug("HOST_CTL 0x%x\n", tmp); -#if !defined(CONFIG_DM_SCSI) -#ifndef CONFIG_SCSI_AHCI_PLAT - dm_pci_read_config16(dev, PCI_COMMAND, &tmp16); - tmp |= PCI_COMMAND_MASTER; - dm_pci_write_config16(dev, PCI_COMMAND, tmp16); -#endif -#endif return 0; } static void ahci_print_info(struct ahci_uc_priv *uc_priv) { -#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) - struct udevice *dev = uc_priv->dev; - u16 cc; -#endif void __iomem *mmio = uc_priv->mmio_base; u32 vers, cap, cap2, impl, speed; const char *speed_s; @@ -350,19 +317,7 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv) else speed_s = "?"; -#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI) scc_s = "SATA"; -#else - dm_pci_read_config16(dev, 0x0a, &cc); - if (cc == 0x0101) - scc_s = "IDE"; - else if (cc == 0x0106) - scc_s = "SATA"; - else if (cc == 0x0104) - scc_s = "RAID"; - else - scc_s = "unknown"; -#endif printf("AHCI %02x%02x.%02x%02x " "%u slots %u ports %s Gbps 0x%x impl %s mode\n", (vers >> 24) & 0xff, @@ -397,12 +352,8 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv) cap2 & (1 << 0) ? "boh " : ""); } -#if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT) static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) { -#if !defined(CONFIG_DM_SCSI) - u16 vendor; -#endif int rc; uc_priv->dev = dev; @@ -415,21 +366,8 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) uc_priv->pio_mask = 0x1f; uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ -#if !defined(CONFIG_DM_SCSI) - uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 0, 0, - PCI_REGION_TYPE, PCI_REGION_MEM); - - /* Take from kernel: - * JMicron-specific fixup: - * make sure we're in AHCI mode - */ - dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor); - if (vendor == 0x197b) - dm_pci_write_config8(dev, 0x41, 0xa1); -#else struct scsi_plat *plat = dev_get_uclass_plat(dev); uc_priv->mmio_base = (void *)plat->base; -#endif debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base); /* initialize adapter */ @@ -444,7 +382,6 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) err_out: return rc; } -#endif #define MAX_DATA_BYTE_COUNT (4*1024*1024) @@ -893,12 +830,7 @@ static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv, static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) { - struct ahci_uc_priv *uc_priv; -#ifdef CONFIG_DM_SCSI - uc_priv = dev_get_uclass_priv(dev->parent); -#else - uc_priv = probe_ent; -#endif + struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent); int ret; switch (pccb->cmd[0]) { @@ -953,41 +885,12 @@ static int ahci_start_ports(struct ahci_uc_priv *uc_priv) return 0; } -#ifndef CONFIG_DM_SCSI -void scsi_low_level_init(int busdevfunc) -{ - struct ahci_uc_priv *uc_priv; - -#ifndef CONFIG_SCSI_AHCI_PLAT - probe_ent = calloc(1, sizeof(struct ahci_uc_priv)); - if (!probe_ent) { - printf("%s: No memory for uc_priv\n", __func__); - return; - } - uc_priv = probe_ent; - struct udevice *dev; - int ret; - - ret = dm_pci_bus_find_bdf(busdevfunc, &dev); - if (ret) - return; - ahci_init_one(uc_priv, dev); -#else - uc_priv = probe_ent; -#endif - - ahci_start_ports(uc_priv); -} -#endif - -#ifndef CONFIG_SCSI_AHCI_PLAT int ahci_init_one_dm(struct udevice *dev) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); return ahci_init_one(uc_priv, dev); } -#endif int ahci_start_ports_dm(struct udevice *dev) { @@ -996,65 +899,6 @@ int ahci_start_ports_dm(struct udevice *dev) return ahci_start_ports(uc_priv); } -#ifdef CONFIG_SCSI_AHCI_PLAT -static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base) -{ - int rc; - - uc_priv->host_flags = ATA_FLAG_SATA - | ATA_FLAG_NO_LEGACY - | ATA_FLAG_MMIO - | ATA_FLAG_PIO_DMA - | ATA_FLAG_NO_ATAPI; - uc_priv->pio_mask = 0x1f; - uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ - - uc_priv->mmio_base = base; - - /* initialize adapter */ - rc = ahci_host_init(uc_priv); - if (rc) - goto err_out; - - ahci_print_info(uc_priv); - - rc = ahci_start_ports(uc_priv); - -err_out: - return rc; -} - -#ifndef CONFIG_DM_SCSI -int ahci_init(void __iomem *base) -{ - struct ahci_uc_priv *uc_priv; - - probe_ent = malloc(sizeof(struct ahci_uc_priv)); - if (!probe_ent) { - printf("%s: No memory for uc_priv\n", __func__); - return -ENOMEM; - } - - uc_priv = probe_ent; - memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); - - return ahci_init_common(uc_priv, base); -} -#endif - -int ahci_init_dm(struct udevice *dev, void __iomem *base) -{ - struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); - - return ahci_init_common(uc_priv, base); -} - -void __weak scsi_init(void) -{ -} - -#endif /* CONFIG_SCSI_AHCI_PLAT */ - /* * In the general case of generic rotating media it makes sense to have a * flush capability. It probably even makes sense in the case of SSDs because @@ -1098,7 +942,6 @@ static int ahci_scsi_bus_reset(struct udevice *dev) return 0; } -#ifdef CONFIG_DM_SCSI int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp) { struct udevice *dev; @@ -1190,16 +1033,3 @@ U_BOOT_DRIVER(ahci_scsi) = { .id = UCLASS_SCSI, .ops = &scsi_ops, }; -#else -int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) -{ - return ahci_scsi_exec(dev, pccb); -} - -__weak int scsi_bus_reset(struct udevice *dev) -{ - return ahci_scsi_bus_reset(dev); - - return 0; -} -#endif diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c index 64fc078bada..784d9bbeacb 100644 --- a/drivers/ata/sata.c +++ b/drivers/ata/sata.c @@ -18,10 +18,6 @@ #include <dm/device-internal.h> #include <dm/uclass-internal.h> -#ifndef CONFIG_AHCI -struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; -#endif - int sata_reset(struct udevice *dev) { struct ahci_ops *ops = ahci_get_ops(dev); @@ -88,15 +84,6 @@ int sata_rescan(bool verbose) return ret; } -#ifndef CONFIG_AHCI -#ifdef CONFIG_PARTITIONS -struct blk_desc *sata_get_dev(int dev) -{ - return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL; -} -#endif -#endif - static unsigned long sata_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) { @@ -109,51 +96,6 @@ static unsigned long sata_bwrite(struct udevice *dev, lbaint_t start, return -ENOSYS; } -#ifndef CONFIG_AHCI -int __sata_initialize(void) -{ - int rc, ret = -1; - int i; - - for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) { - memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc)); - sata_dev_desc[i].uclass_id = UCLASS_AHCI; - sata_dev_desc[i].devnum = i; - sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN; - sata_dev_desc[i].type = DEV_TYPE_HARDDISK; - sata_dev_desc[i].lba = 0; - sata_dev_desc[i].blksz = 512; - sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz); - rc = init_sata(i); - if (!rc) { - rc = scan_sata(i); - if (!rc && sata_dev_desc[i].lba > 0 && - sata_dev_desc[i].blksz > 0) { - part_init(&sata_dev_desc[i]); - ret = i; - } - } - } - - return ret; -} -int sata_initialize(void) __attribute__((weak, alias("__sata_initialize"))); - -__weak int __sata_stop(void) -{ - int i, err = 0; - - for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) - err |= reset_sata(i); - - if (err) - printf("Could not reset some SATA devices\n"); - - return err; -} -int sata_stop(void) __attribute__((weak, alias("__sata_stop"))); -#endif - static const struct blk_ops sata_blk_ops = { .read = sata_bread, .write = sata_bwrite, diff --git a/drivers/ata/sata_sandbox.c b/drivers/ata/sata_sandbox.c deleted file mode 100644 index e64cc4a5c10..00000000000 --- a/drivers/ata/sata_sandbox.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Google, Inc - * Written by Simon Glass <sjg@chromium.org> - */ - -#include <common.h> -#include <blk.h> - -int init_sata(int dev) -{ - return 0; -} - -int reset_sata(int dev) -{ - return 0; -} - -int scan_sata(int dev) -{ - return 0; -} - -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) -{ - return 0; -} - -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) -{ - return 0; -} diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 048a6caef00..6ad18889f61 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -13,7 +13,7 @@ config BLK config SPL_LEGACY_BLOCK bool # "Enable Legacy Block Device" - depends on SPL && !DM_SPL + depends on SPL default y if SPL_MMC || SPL_USB_STORAGE || SCSI || NVME || IDE default y if SPL_AHCI_PCI help @@ -265,6 +265,7 @@ config SYS_64BIT_LBA config RKMTD bool "Rockchip rkmtd virtual block device" + select RANDOM_UUID help Enable "rkmtd" class and driver to create a virtual block device to transfer Rockchip boot block data to and from NAND with block diff --git a/drivers/block/Makefile b/drivers/block/Makefile index fdcba5c8318..fe6a1fcf486 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -15,7 +15,8 @@ obj-$(CONFIG_RKMTD) += rkmtd.o endif obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o -obj-$(CONFIG_BLKMAP) += blkmap.o +obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap.o +obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap_helper.o obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c index 149a4cac3ea..21201409ed4 100644 --- a/drivers/block/blkmap.c +++ b/drivers/block/blkmap.c @@ -66,21 +66,6 @@ struct blkmap_slice { void (*destroy)(struct blkmap *bm, struct blkmap_slice *bms); }; -/** - * struct blkmap - Block map - * - * Data associated with a blkmap. - * - * @label: Human readable name of this blkmap - * @blk: Underlying block device - * @slices: List of slices associated with this blkmap - */ -struct blkmap { - char *label; - struct udevice *blk; - struct list_head slices; -}; - static bool blkmap_slice_contains(struct blkmap_slice *bms, lbaint_t blknr) { return (blknr >= bms->blknr) && (blknr < (bms->blknr + bms->blkcnt)); diff --git a/drivers/block/blkmap_helper.c b/drivers/block/blkmap_helper.c new file mode 100644 index 00000000000..bfba14110d2 --- /dev/null +++ b/drivers/block/blkmap_helper.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * blkmap helper function + * + * Copyright (c) 2023, Linaro Limited + */ + +#include <blk.h> +#include <blkmap.h> +#include <dm/device.h> +#include <dm/device-internal.h> + +int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size, + struct udevice **devp) +{ + int ret; + lbaint_t blknum; + struct blkmap *bm; + struct blk_desc *desc; + struct udevice *bm_dev; + + ret = blkmap_create(label, &bm_dev); + if (ret) { + log_err("failed to create blkmap\n"); + return ret; + } + + bm = dev_get_plat(bm_dev); + desc = dev_get_uclass_plat(bm->blk); + blknum = image_size >> desc->log2blksz; + ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr); + if (ret) { + log_err("Unable to map %#llx at block %d : %d\n", + (unsigned long long)image_addr, 0, ret); + goto err; + } + log_info("Block %d+0x" LBAF " mapped to %#llx\n", 0, blknum, + (unsigned long long)image_addr); + + ret = device_probe(bm->blk); + if (ret) + goto err; + + if (devp) + *devp = bm_dev; + + return 0; + +err: + blkmap_destroy(bm_dev); + + return ret; +} diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index e5ada5b6d49..eecfacd7fc0 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1104,46 +1104,12 @@ static int ast2600_clk_enable(struct clk *clk) return 0; } -struct clk_ops ast2600_clk_ops = { - .get_rate = ast2600_clk_get_rate, - .set_rate = ast2600_clk_set_rate, - .enable = ast2600_clk_enable, -}; - -static int ast2600_clk_probe(struct udevice *dev) -{ - struct ast2600_clk_priv *priv = dev_get_priv(dev); - - priv->scu = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->scu)) - return PTR_ERR(priv->scu); - - ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); - ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); - ast2600_configure_mac12_clk(priv->scu); - ast2600_configure_mac34_clk(priv->scu); - ast2600_configure_rsa_ecc_clk(priv->scu); - - return 0; -} - -static int ast2600_clk_bind(struct udevice *dev) -{ - int ret; - - /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); - if (ret) - debug("Warning: No reset driver: ret=%d\n", ret); - - return 0; -} - struct aspeed_clks { ulong id; const char *name; }; +#if IS_ENABLED(CONFIG_CMD_CLK) static struct aspeed_clks aspeed_clk_names[] = { { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, @@ -1158,18 +1124,12 @@ static struct aspeed_clks aspeed_clk_names[] = { { ASPEED_CLK_HUARTX, "huxclk" }, }; -int soc_clk_dump(void) +static void ast2600_clk_dump(struct udevice *dev) { - struct udevice *dev; struct clk clk; unsigned long rate; int i, ret; - ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_scu), - &dev); - if (ret) - return ret; - printf("Clk\t\tHz\n"); for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { @@ -1202,6 +1162,45 @@ int soc_clk_dump(void) return 0; } +#endif + +struct clk_ops ast2600_clk_ops = { + .get_rate = ast2600_clk_get_rate, + .set_rate = ast2600_clk_set_rate, + .enable = ast2600_clk_enable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = ast2600_clk_dump, +#endif +}; + +static int ast2600_clk_probe(struct udevice *dev) +{ + struct ast2600_clk_priv *priv = dev_get_priv(dev); + + priv->scu = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); + + ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); + ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); + ast2600_configure_mac12_clk(priv->scu); + ast2600_configure_mac34_clk(priv->scu); + ast2600_configure_rsa_ecc_clk(priv->scu); + + return 0; +} + +static int ast2600_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); + if (ret) + debug("Warning: No reset driver: ret=%d\n", ret); + + return 0; +} static const struct udevice_id ast2600_clk_ids[] = { { .compatible = "aspeed,ast2600-scu", }, diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index b52d926f339..025c7a7aa26 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -17,6 +17,7 @@ #include <linux/clk/at91_pmc.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/time.h> #include "pmc.h" #define UBOOT_DM_CLK_AT91_MAIN_RC "at91-main-rc-clk" @@ -25,7 +26,6 @@ #define UBOOT_DM_CLK_AT91_SAM9X5_MAIN "at91-sam9x5-main-clk" #define MOR_KEY_MASK GENMASK(23, 16) -#define USEC_PER_SEC 1000000UL #define SLOW_CLOCK_FREQ 32768 #define clk_main_parent_select(s) (((s) & \ diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 6eb2b8133a3..d2e5a1ae401 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -66,7 +66,7 @@ static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate) const struct clk_ops *rate_ops = composite->rate_ops; struct clk *clk_rate = composite->rate; - if (rate && rate_ops) + if (rate && rate_ops && rate_ops->set_rate) return rate_ops->set_rate(clk_rate, rate); else return clk_get_rate(clk); diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 3b5e3f9c86b..3e9d68feb3c 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -640,6 +640,7 @@ int clk_enable(struct clk *clk) if (CONFIG_IS_ENABLED(CLK_CCF)) { /* Take id 0 as a non-valid clk, such as dummy */ if (clk->id && !clk_get_by_id(clk->id, &clkp)) { + ops = clk_dev_ops(clkp->dev); if (clkp->enable_count) { clkp->enable_count++; return 0; @@ -699,6 +700,7 @@ int clk_disable(struct clk *clk) if (CONFIG_IS_ENABLED(CLK_CCF)) { if (clk->id && !clk_get_by_id(clk->id, &clkp)) { + ops = clk_dev_ops(clkp->dev); if (clkp->flags & CLK_IS_CRITICAL) return 0; diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index a5a3461b66c..6ede1b4d4dc 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -18,17 +18,19 @@ int clk_register(struct clk *clk, const char *drv_name, const char *name, const char *parent_name) { - struct udevice *parent; + struct udevice *parent = NULL; struct driver *drv; int ret; - ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); - if (ret) { - log_err("%s: failed to get %s device (parent of %s)\n", - __func__, parent_name, name); - } else { - log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, - parent->name, parent); + if (parent_name) { + ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); + if (ret) { + log_err("%s: failed to get %s device (parent of %s)\n", + __func__, parent_name, name); + } else { + log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, + parent->name, parent); + } } drv = lists_driver_lookup_name(drv_name); diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index c534cc07e09..7432ae8f064 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -16,6 +16,7 @@ #include <dt-bindings/mfd/k210-sysctl.h> #include <k210/pll.h> #include <linux/bitfield.h> +#include <asm/barrier.h> DECLARE_GLOBAL_DATA_PTR; @@ -1238,52 +1239,6 @@ static int k210_clk_request(struct clk *clk) return 0; } -static const struct clk_ops k210_clk_ops = { - .request = k210_clk_request, - .set_rate = k210_clk_set_rate, - .get_rate = k210_clk_get_rate, - .set_parent = k210_clk_set_parent, - .enable = k210_clk_enable, - .disable = k210_clk_disable, -}; - -static int k210_clk_probe(struct udevice *dev) -{ - int ret; - struct k210_clk_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr_ptr(dev_get_parent(dev)); - if (!priv->base) - return -EINVAL; - - ret = clk_get_by_index(dev, 0, &priv->in0); - if (ret) - return ret; - - /* - * Force setting defaults, even before relocation. This is so we can - * set the clock rate for PLL1 before we relocate into aisram. - */ - if (!(gd->flags & GD_FLG_RELOC)) - clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE); - - return 0; -} - -static const struct udevice_id k210_clk_ids[] = { - { .compatible = "canaan,k210-clk" }, - { }, -}; - -U_BOOT_DRIVER(k210_clk) = { - .name = "k210_clk", - .id = UCLASS_CLK, - .of_match = k210_clk_ids, - .ops = &k210_clk_ops, - .probe = k210_clk_probe, - .priv_auto = sizeof(struct k210_clk_priv), -}; - #if IS_ENABLED(CONFIG_CMD_CLK) static char show_enabled(struct k210_clk_priv *priv, int id) { @@ -1322,16 +1277,10 @@ static void show_clks(struct k210_clk_priv *priv, int id, int depth) } } -int soc_clk_dump(void) +static void k210_clk_dump(struct udevice *dev) { - int ret; - struct udevice *dev; struct k210_clk_priv *priv; - ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk), - &dev); - if (ret) - return ret; priv = dev_get_priv(dev); puts(" Rate Enabled Name\n"); @@ -1339,6 +1288,54 @@ int soc_clk_dump(void) printf(" %-9lu %-7c %*s%s\n", clk_get_rate(&priv->in0), 'y', 0, "", priv->in0.dev->name); show_clks(priv, K210_CLK_IN0, 1); - return 0; } #endif + +static const struct clk_ops k210_clk_ops = { + .request = k210_clk_request, + .set_rate = k210_clk_set_rate, + .get_rate = k210_clk_get_rate, + .set_parent = k210_clk_set_parent, + .enable = k210_clk_enable, + .disable = k210_clk_disable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = k210_clk_dump, +#endif +}; + +static int k210_clk_probe(struct udevice *dev) +{ + int ret; + struct k210_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev_get_parent(dev)); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &priv->in0); + if (ret) + return ret; + + /* + * Force setting defaults, even before relocation. This is so we can + * set the clock rate for PLL1 before we relocate into aisram. + */ + if (!(gd->flags & GD_FLG_RELOC)) + clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE); + + return 0; +} + +static const struct udevice_id k210_clk_ids[] = { + { .compatible = "canaan,k210-clk" }, + { }, +}; + +U_BOOT_DRIVER(k210_clk) = { + .name = "k210_clk", + .id = UCLASS_CLK, + .of_match = k210_clk_ids, + .ops = &k210_clk_ops, + .probe = k210_clk_probe, + .priv_auto = sizeof(struct k210_clk_priv), +}; diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c index ef06a7fb9f6..a77d0e7419c 100644 --- a/drivers/clk/clk_pic32.c +++ b/drivers/clk/clk_pic32.c @@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define CLK_MHZ(x) ((x) / 1000000) + /* Primary oscillator */ #define SYS_POSC_CLK_HZ 24000000 @@ -385,9 +387,44 @@ static ulong pic32_set_rate(struct clk *clk, ulong rate) return rate; } +#if IS_ENABLED(CONFIG_CMD_CLK) +static void pic32_dump(struct udevice *dev) +{ + int i; + struct clk clk; + + clk.dev = dev; + + clk.id = PLLCLK; + printf("PLL Speed: %lu MHz\n", + CLK_MHZ(pic32_get_rate(&clk))); + + clk.id = PB7CLK; + printf("CPU Speed: %lu MHz\n", CLK_MHZ(pic32_get_rate(&clk))); + + clk.id = MPLL; + printf("MPLL Speed: %lu MHz\n", CLK_MHZ(pic32_get_rate(&clk))); + + for (i = PB1CLK; i <= PB7CLK; i++) { + clk.id = i; + printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1, + CLK_MHZ(pic32_get_rate(&clk))); + } + + for (i = REF1CLK; i <= REF5CLK; i++) { + clk.id = i; + printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1, + CLK_MHZ(pic32_get_rate(&clk))); + } +} +#endif + static struct clk_ops pic32_pic32_clk_ops = { .set_rate = pic32_set_rate, .get_rate = pic32_get_rate, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = pic32_dump, +#endif }; static int pic32_clk_probe(struct udevice *dev) diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index fedcdd40448..38184e27aa4 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -284,6 +284,7 @@ static int sandbox_clk_ccf_probe(struct udevice *dev) U_BOOT_DRIVER(sandbox_clk_ccf) = { .name = "sandbox_clk_ccf", .id = UCLASS_CLK, + .ops = &ccf_clk_ops, .probe = sandbox_clk_ccf_probe, .of_match = sandbox_clk_ccf_test_ids, }; diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index 5807a454f3b..c695b69321e 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -15,6 +15,7 @@ static const char * const sandbox_clk_test_names[] = { [SANDBOX_CLK_TEST_ID_FIXED] = "fixed", [SANDBOX_CLK_TEST_ID_SPI] = "spi", [SANDBOX_CLK_TEST_ID_I2C] = "i2c", + [SANDBOX_CLK_TEST_ID_I2C_ROOT] = "i2c_root", }; int sandbox_clk_test_get(struct udevice *dev) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index c473643603a..42ab032bf7e 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -555,7 +555,8 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) return 0; } -int soc_clk_dump(void) +#if IS_ENABLED(CONFIG_CMD_CLK) +static void versal_clk_dump(struct udevice __always_unused *dev) { u64 clk_rate = 0; u32 type, ret, i = 0; @@ -575,9 +576,8 @@ int soc_clk_dump(void) printf("clk: %s freq:%lld\n", clock[i].clk_name, clk_rate); } - - return 0; } +#endif static void versal_get_clock_info(void) { @@ -769,6 +769,9 @@ static struct clk_ops versal_clk_ops = { .set_rate = versal_clk_set_rate, .get_rate = versal_clk_get_rate, .enable = versal_clk_enable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = versal_clk_dump, +#endif }; static const struct udevice_id versal_clk_ids[] = { diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index e80500e382b..34f964d72af 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -454,12 +454,64 @@ static int dummy_enable(struct clk *clk) return 0; } +#if IS_ENABLED(CONFIG_CMD_CLK) +static const char * const clk_names[clk_max] = { + "armpll", "ddrpll", "iopll", + "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", + "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", + "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", + "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", + "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", + "smc_aper", "swdt", "dbg_trc", "dbg_apb" +}; + +static void zynq_clk_dump(struct udevice *dev) +{ + int i, ret; + + printf("clk\t\tfrequency\n"); + for (i = 0; i < clk_max; i++) { + const char *name = clk_names[i]; + + if (name) { + struct clk clk; + unsigned long rate; + + clk.id = i; + ret = clk_request(dev, &clk); + if (ret < 0) { + printf("%s clk_request() failed: %d\n", + __func__, ret); + break; + } + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO)) + printf("%10s%20s\n", name, "unknown"); + else + printf("%10s%20lu\n", name, rate); + } + } +} +#endif + static struct clk_ops zynq_clk_ops = { .get_rate = zynq_clk_get_rate, #ifndef CONFIG_SPL_BUILD .set_rate = zynq_clk_set_rate, #endif .enable = dummy_enable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = zynq_clk_dump, +#endif }; static int zynq_clk_probe(struct udevice *dev) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 1cfe0e25b10..0ffac194a19 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -735,16 +735,11 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) } } -int soc_clk_dump(void) +#if IS_ENABLED(CONFIG_CMD_CLK) +static void zynqmp_clk_dump(struct udevice *dev) { - struct udevice *dev; int i, ret; - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(zynqmp_clk), &dev); - if (ret) - return ret; - printf("clk\t\tfrequency\n"); for (i = 0; i < clk_max; i++) { const char *name = clk_names[i]; @@ -754,8 +749,11 @@ int soc_clk_dump(void) clk.id = i; ret = clk_request(dev, &clk); - if (ret < 0) - return ret; + if (ret < 0) { + printf("%s clk_request() failed: %d\n", + __func__, ret); + break; + } rate = clk_get_rate(&clk); @@ -769,9 +767,8 @@ int soc_clk_dump(void) printf("%10s%20lu\n", name, rate); } } - - return 0; } +#endif static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq) { @@ -844,6 +841,7 @@ static int zynqmp_clk_enable(struct clk *clk) break; case qspi_ref ... can1_ref: case lpd_lsbus: + case topsw_lsbus: clkact_shift = 24; mask = 0x1; break; @@ -871,6 +869,9 @@ static struct clk_ops zynqmp_clk_ops = { .set_rate = zynqmp_clk_set_rate, .get_rate = zynqmp_clk_get_rate, .enable = zynqmp_clk_enable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = zynqmp_clk_dump, +#endif }; static const struct udevice_id zynqmp_clk_ids[] = { diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index ceeead34349..9600672e071 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -43,18 +43,12 @@ static int imx8_clk_enable(struct clk *clk) } #if IS_ENABLED(CONFIG_CMD_CLK) -int soc_clk_dump(void) +static void imx8_clk_dump(struct udevice *dev) { - struct udevice *dev; struct clk clk; unsigned long rate; int i, ret; - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(imx8_clk), &dev); - if (ret) - return ret; - printf("Clk\t\tHz\n"); for (i = 0; i < num_clks; i++) { @@ -84,8 +78,6 @@ int soc_clk_dump(void) printf("%s(%3lu):\t%lu\n", imx8_clk_names[i].name, imx8_clk_names[i].id, rate); } - - return 0; } #endif @@ -94,6 +86,9 @@ static struct clk_ops imx8_clk_ops = { .get_rate = imx8_clk_get_rate, .enable = imx8_clk_enable, .disable = imx8_clk_disable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = imx8_clk_dump, +#endif }; static int imx8_clk_probe(struct udevice *dev) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 692823e74b8..457acb8a401 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -83,6 +83,20 @@ static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_ static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +#ifndef CONFIG_SPL_BUILD +static const char *imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; +#endif + static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -330,6 +344,22 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0)); + clk_dm(IMX8MN_CLK_PWM1, + imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380)); + clk_dm(IMX8MN_CLK_PWM2, + imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400)); + clk_dm(IMX8MN_CLK_PWM3, + imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480)); + clk_dm(IMX8MN_CLK_PWM4, + imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500)); + clk_dm(IMX8MN_CLK_PWM1_ROOT, + imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); + clk_dm(IMX8MN_CLK_PWM2_ROOT, + imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); + clk_dm(IMX8MN_CLK_PWM3_ROOT, + imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + clk_dm(IMX8MN_CLK_PWM4_ROOT, + imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif #if CONFIG_IS_ENABLED(DM_SPI) diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index d0f5bb37530..5220a337a8b 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -607,14 +607,6 @@ static int meson_clk_set_parent(struct clk *clk, struct clk *parent_clk) return meson_mux_set_parent_by_id(clk, parent_clk->id); } -static struct clk_ops meson_clk_ops = { - .disable = meson_clk_disable, - .enable = meson_clk_enable, - .get_rate = meson_clk_get_rate, - .set_rate = meson_clk_set_rate, - .set_parent = meson_clk_set_parent, -}; - static int meson_clk_probe(struct udevice *dev) { struct meson_clk *priv = dev_get_priv(dev); @@ -644,15 +636,7 @@ static const struct udevice_id meson_clk_ids[] = { { } }; -U_BOOT_DRIVER(meson_clk) = { - .name = "meson-clk-a1", - .id = UCLASS_CLK, - .of_match = meson_clk_ids, - .priv_auto = sizeof(struct meson_clk), - .ops = &meson_clk_ops, - .probe = meson_clk_probe, -}; - +#if IS_ENABLED(CONFIG_CMD_CLK) static const char *meson_clk_get_name(struct clk *clk, int id) { const struct meson_clk_info *info; @@ -662,7 +646,7 @@ static const char *meson_clk_get_name(struct clk *clk, int id) return IS_ERR(info) ? "unknown" : info->name; } -static int meson_clk_dump(struct clk *clk) +static int meson_clk_dump_single(struct clk *clk) { const struct meson_clk_info *info; struct meson_clk *priv; @@ -697,7 +681,7 @@ static int meson_clk_dump(struct clk *clk) return 0; } -static int meson_clk_dump_dev(struct udevice *dev) +static void meson_clk_dump(struct udevice *dev) { int i; struct meson_clk_data *data; @@ -710,26 +694,30 @@ static int meson_clk_dump_dev(struct udevice *dev) data = (struct meson_clk_data *)dev_get_driver_data(dev); for (i = 0; i < data->num_clocks; i++) { - meson_clk_dump(&(struct clk){ + meson_clk_dump_single(&(struct clk){ .dev = dev, .id = i }); } - - return 0; } +#endif -int soc_clk_dump(void) -{ - struct udevice *dev; - int i = 0; - - while (!uclass_get_device(UCLASS_CLK, i++, &dev)) { - if (dev->driver == DM_DRIVER_GET(meson_clk)) { - meson_clk_dump_dev(dev); - printf("\n"); - } - } +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, + .get_rate = meson_clk_get_rate, + .set_rate = meson_clk_set_rate, + .set_parent = meson_clk_set_parent, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = meson_clk_dump, +#endif +}; - return 0; -} +U_BOOT_DRIVER(meson_clk) = { + .name = "meson-clk-a1", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +}; diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index e75052f383c..1a7097029ae 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -488,33 +488,36 @@ static int armada_37xx_periph_clk_dump(struct udevice *dev) static int clk_dump(const char *name, int (*func)(struct udevice *)) { struct udevice *dev; + int ret; if (uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { printf("Cannot find device %s\n", name); return -ENODEV; } - return func(dev); + ret = func(dev); + if (ret) + printf("Dump failed for %s: %d\n", name, ret); + + return ret; } int armada_37xx_tbg_clk_dump(struct udevice *); -int soc_clk_dump(void) +static void armada37xx_clk_dump(struct udevice __always_unused *dev) { printf(" xtal at %u000000 Hz\n\n", get_ref_clk()); if (clk_dump("tbg@13200", armada_37xx_tbg_clk_dump)) - return 1; + return; if (clk_dump("nb-periph-clk@13000", armada_37xx_periph_clk_dump)) - return 1; + return; if (clk_dump("sb-periph-clk@18000", armada_37xx_periph_clk_dump)) - return 1; - - return 0; + return; } #endif @@ -605,6 +608,9 @@ static const struct clk_ops armada_37xx_periph_clk_ops = { .set_parent = armada_37xx_periph_clk_set_parent, .enable = armada_37xx_periph_clk_enable, .disable = armada_37xx_periph_clk_disable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = armada37xx_clk_dump, +#endif }; static const struct udevice_id armada_37xx_periph_clk_ids[] = { diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c index 8d71f2a24b8..18cb9cddbf3 100644 --- a/drivers/clk/nuvoton/clk_npcm.c +++ b/drivers/clk/nuvoton/clk_npcm.c @@ -135,7 +135,7 @@ static u32 npcm_clk_get_div(struct clk *clk) return div; } -static u32 npcm_clk_set_div(struct clk *clk, u32 div) +static int npcm_clk_set_div(struct clk *clk, u32 div) { struct npcm_clk_priv *priv = dev_get_priv(clk->dev); struct npcm_clk_div *divider; @@ -145,6 +145,9 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div) if (!divider) return -EINVAL; + if (divider->flags & DIV_RO) + return 0; + if (divider->flags & PRE_DIV2) div = div >> 1; @@ -153,6 +156,12 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div) else clkdiv = ilog2(div); + if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) { + printf("clkdiv(%d) for clk(%ld) is over limit\n", + clkdiv, clk->id); + return -EINVAL; + } + val = readl(priv->base + divider->reg); val &= ~divider->mask; val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask; @@ -253,8 +262,8 @@ static ulong npcm_clk_set_rate(struct clk *clk, ulong rate) if (ret) return ret; - debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, parent_rate, div); - return (parent_rate / div); + debug("%s: rate %lu, new rate %lu\n", __func__, rate, npcm_clk_get_rate(clk)); + return npcm_clk_get_rate(clk); } static int npcm_clk_set_parent(struct clk *clk, struct clk *parent) diff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h index 06b60dc8b8d..b4726d8381e 100644 --- a/drivers/clk/nuvoton/clk_npcm.h +++ b/drivers/clk/nuvoton/clk_npcm.h @@ -50,6 +50,7 @@ #define PRE_DIV2 BIT(2) /* Pre divisor = 2 */ #define POST_DIV2 BIT(3) /* Post divisor = 2 */ #define FIXED_PARENT BIT(4) /* clock source is fixed */ +#define DIV_RO BIT(5) /* divider is read-only */ /* Parameters of PLL configuration */ struct npcm_clk_pll { diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c b/drivers/clk/nuvoton/clk_npcm8xx.c index 27e3cfcf553..d1b32e32371 100644 --- a/drivers/clk/nuvoton/clk_npcm8xx.c +++ b/drivers/clk/nuvoton/clk_npcm8xx.c @@ -45,12 +45,12 @@ static struct npcm_clk_select npcm8xx_clk_selectors[] = { }; static struct npcm_clk_div npcm8xx_clk_dividers[] = { - {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2}, - {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2}, - {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2}, - {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1}, - {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1}, - {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1}, + {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO}, + {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO}, + {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO}, + {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO}, + {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO}, + {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO}, {NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1}, {NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1}, {NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1}, diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a835541e48e..a38694809a0 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "i2c5_apb", "apb0", OFFSET(JH7110_SYSCLK_I2C5_APB))); + /* Watchdog clocks */ + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB), + starfive_clk_gate(priv->reg, + "wdt_apb", "apb0", + OFFSET(JH7110_SYSCLK_WDT_APB))); + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE), + starfive_clk_gate(priv->reg, + "wdt_core", "oscillator", + OFFSET(JH7110_SYSCLK_WDT_CORE))); /* enable noc_bus_stg_axi clock */ if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk)) diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index ed7660196ef..d68c75ed201 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -522,17 +522,20 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* get the current PLLSAIR output freq */ pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); - best_div = pllsair_rate / rate; - - /* look into pllsaidivr_table if this divider is available*/ - for (i = 0 ; i < sizeof(pllsaidivr_table); i++) - if (best_div == pllsaidivr_table[i]) { - /* set pll_saidivr with found value */ - clrsetbits_le32(®s->dckcfgr, - RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i]); - return rate; - } + if ((pllsair_rate % rate) == 0) { + best_div = pllsair_rate / rate; + + /* look into pllsaidivr_table if this divider is available */ + for (i = 0 ; i < sizeof(pllsaidivr_table); i++) + if (best_div == pllsaidivr_table[i]) { + /* set pll_saidivr with found value */ + clrsetbits_le32(®s->dckcfgr, + RCC_DCKCFGR_PLLSAIDIVR_MASK, + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); + return rate; + } + } /* * As no pllsaidivr value is suitable to obtain requested freq, diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index f3ac8c75831..6f000c8e444 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -2225,10 +2225,13 @@ static void stm32mp1_osc_init(struct udevice *dev) } } -static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) +static void __maybe_unused stm32mp1_clk_dump(struct udevice *dev) { char buf[32]; int i, s, p; + struct stm32mp1_clk_priv *priv; + + priv = dev_get_priv(dev); printf("Clocks:\n"); for (i = 0; i < _PARENT_NB; i++) { @@ -2252,27 +2255,6 @@ static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) } } -#ifdef CONFIG_CMD_CLK -int soc_clk_dump(void) -{ - struct udevice *dev; - struct stm32mp1_clk_priv *priv; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(stm32mp1_clock), - &dev); - if (ret) - return ret; - - priv = dev_get_priv(dev); - - stm32mp1_clk_dump(priv); - - return 0; -} -#endif - static int stm32mp1_clk_probe(struct udevice *dev) { int result = 0; @@ -2302,7 +2284,7 @@ static int stm32mp1_clk_probe(struct udevice *dev) #if defined(VERBOSE_DEBUG) /* display debug information for probe after relocation */ if (gd->flags & GD_FLG_RELOC) - stm32mp1_clk_dump(priv); + stm32mp1_clk_dump(dev); #endif gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU); @@ -2333,6 +2315,9 @@ static const struct clk_ops stm32mp1_clk_ops = { .disable = stm32mp1_clk_disable, .get_rate = stm32mp1_clk_get_rate, .set_rate = stm32mp1_clk_set_rate, +#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_SPL_BUILD) + .dump = stm32mp1_clk_dump, +#endif }; U_BOOT_DRIVER(stm32mp1_clock) = { diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 737d4590d5b..1081d61fcf0 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -87,7 +87,7 @@ config DM_STATS config SPL_DM_STATS bool "Collect and show driver model stats in SPL" - depends on DM_SPL + depends on SPL_DM help Enable this to collect and display memory statistics about driver model. This can help to figure out where all the memory is going and diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index f72ea416cf1..21a233f90f0 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -83,6 +83,11 @@ static oftree oftree_ensure(void *fdt) if (check_tree_count()) return oftree_null(); + if (fdt_check_header(fdt)) { + log_err("Invalid device tree blob header\n"); + return oftree_null(); + } + /* register the new tree */ i = oftree_count++; oftree_list[i] = fdt; diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index fd8b4113b7b..45e1a70dbd4 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -111,11 +111,16 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(1000)); dram_disable_bypass(); break; + case 3734: case 3733: case 3732: dram_pll_init(MHZ(933)); dram_disable_bypass(); break; + case 3600: + dram_pll_init(MHZ(900)); + dram_disable_bypass(); + break; case 3200: dram_pll_init(MHZ(800)); dram_disable_bypass(); diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c index 855a874ac1e..b9b2403012d 100644 --- a/drivers/ddr/imx/phy/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -49,6 +49,13 @@ void ddr_load_train_firmware(enum fw_type type) unsigned long imem_start = (unsigned long)_end + fw_offset; unsigned long dmem_start; unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN; + static enum fw_type last_type = -1; + + /* If FW doesn't change, we can save the loading. */ + if (last_type == type) + return; + + last_type = type; #ifdef CONFIG_SPL_OF_CONTROL if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 4e80e85d10d..0360d9da142 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -19,6 +19,7 @@ config DFU_WRITE_ALT config DFU_TFTP bool "DFU via TFTP" + depends on NETDEVICES select UPDATE_COMMON select DFU_OVER_TFTP help @@ -111,5 +112,14 @@ config SYS_DFU_MAX_FILE_SIZE the buffer once we've been given the whole file. Define this to the maximum filesize (in bytes) for the buffer. If undefined it defaults to the CONFIG_SYS_DFU_DATA_BUF_SIZE. + +config DFU_NAME_MAX_SIZE + int "Size of the name to be added in dfu entity" + default 32 + depends on DFU + help + This value is used to maximum size. If name is longer than default size, + we need to change the proper maximum size. + endif endmenu diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 0af54604211..3c64e894646 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -87,7 +87,6 @@ endif config DMA_LEGACY bool "Legacy DMA support" - default y if FSLDMAFEC help Enable legacy DMA support. This does not use driver model and should be migrated to the new API. diff --git a/drivers/dma/MCD_dmaApi.c b/drivers/dma/MCD_dmaApi.c deleted file mode 100644 index af0e1345220..00000000000 --- a/drivers/dma/MCD_dmaApi.c +++ /dev/null @@ -1,1010 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -/*Main C file for multi-channel DMA API. */ - -#include <common.h> - -#include <MCD_dma.h> -#include <MCD_tasksInit.h> -#include <MCD_progCheck.h> - -/********************************************************************/ -/* This is an API-internal pointer to the DMA's registers */ -dmaRegs *MCD_dmaBar; - -/* - * These are the real and model task tables as generated by the - * build process - */ -extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS]; -extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS]; - -/* - * However, this (usually) gets relocated to on-chip SRAM, at which - * point we access them as these tables - */ -volatile TaskTableEntry *MCD_taskTable; -TaskTableEntry *MCD_modelTaskTable; - -/* - * MCD_chStatus[] is an array of status indicators for remembering - * whether a DMA has ever been attempted on each channel, pausing - * status, etc. - */ -static int MCD_chStatus[NCHANNELS] = { - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA -}; - -/* Prototypes for local functions */ -static void MCD_memcpy(int *dest, int *src, u32 size); -static void MCD_resmActions(int channel); - -/* - * Buffer descriptors used for storage of progress info for single Dmas - * Also used as storage for the DMA for CRCs for single DMAs - * Otherwise, the DMA does not parse these buffer descriptors - */ -#ifdef MCD_INCLUDE_EU -extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#else -MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#endif -MCD_bufDesc *MCD_relocBuffDesc; - -/* Defines for the debug control register's functions */ -#define DBG_CTL_COMP1_TASK (0x00002000) -#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \ - DBG_CTL_BREAK | \ - DBG_CTL_INT_BREAK | \ - DBG_CTL_COMP1_TASK) -#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \ - DBG_CTL_INT_BREAK | \ - DBG_CTL_COMP1_TASK) -#define DBG_KILL_ALL_STAT (0xFFFFFFFF) - -/* Offset to context save area where progress info is stored */ -#define CSAVE_OFFSET 10 - -/* Defines for Byte Swapping */ -#define MCD_BYTE_SWAP_KILLER 0xFFF8888F -#define MCD_NO_BYTE_SWAP_ATALL 0x00040000 - -/* Execution Unit Identifiers */ -#define MAC 0 /* legacy - not used */ -#define LUAC 1 /* legacy - not used */ -#define CRC 2 /* legacy - not used */ -#define LURC 3 /* Logic Unit with CRC */ - -/* Task Identifiers */ -#define TASK_CHAINNOEU 0 -#define TASK_SINGLENOEU 1 -#ifdef MCD_INCLUDE_EU -#define TASK_CHAINEU 2 -#define TASK_SINGLEEU 3 -#define TASK_FECRX 4 -#define TASK_FECTX 5 -#else -#define TASK_CHAINEU 0 -#define TASK_SINGLEEU 1 -#define TASK_FECRX 2 -#define TASK_FECTX 3 -#endif - -/* - * Structure to remember which variant is on which channel - * TBD- need this? - */ -typedef struct MCD_remVariants_struct MCD_remVariant; -struct MCD_remVariants_struct { - int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */ - int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */ - s16 remDestIncr[NCHANNELS]; /* DestIncr */ - s16 remSrcIncr[NCHANNELS]; /* srcIncr */ - u32 remXferSize[NCHANNELS]; /* xferSize */ -}; - -/* Structure to remember the startDma parameters for each channel */ -MCD_remVariant MCD_remVariants; -/********************************************************************/ -/* Function: MCD_initDma - * Purpose: Initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task - * structures, and setting up some global settings - * Arguments: - * dmaBarAddr - pointer to the multichannel DMA registers - * taskTableDest - location to move DMA task code and structs to - * flags - operational parameters - * Return Value: - * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned - * MCD_OK otherwise - */ -extern u32 MCD_funcDescTab0[]; - -int MCD_initDma(dmaRegs * dmaBarAddr, void *taskTableDest, u32 flags) -{ - int i; - TaskTableEntry *entryPtr; - - /* setup the local pointer to register set */ - MCD_dmaBar = dmaBarAddr; - - /* do we need to move/create a task table */ - if ((flags & MCD_RELOC_TASKS) != 0) { - int fixedSize; - u32 *fixedPtr; - /*int *tablePtr = taskTableDest;TBD */ - int varTabsOffset, funcDescTabsOffset, contextSavesOffset; - int taskDescTabsOffset; - int taskTableSize, varTabsSize, funcDescTabsSize, - contextSavesSize; - int taskDescTabSize; - - int i; - - /* check if physical address is aligned on 512 byte boundary */ - if (((u32) taskTableDest & 0x000001ff) != 0) - return (MCD_TABLE_UNALIGNED); - - /* set up local pointer to task Table */ - MCD_taskTable = taskTableDest; - - /* - * Create a task table: - * - compute aligned base offsets for variable tables and - * function descriptor tables, then - * - loop through the task table and setup the pointers - * - copy over model task table with the the actual task - * descriptor tables - */ - - taskTableSize = NCHANNELS * sizeof(TaskTableEntry); - /* align variable tables to size */ - varTabsOffset = taskTableSize + (u32) taskTableDest; - if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0) - varTabsOffset = - (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE); - /* align function descriptor tables */ - varTabsSize = NCHANNELS * VAR_TAB_SIZE; - funcDescTabsOffset = varTabsOffset + varTabsSize; - - if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0) - funcDescTabsOffset = - (funcDescTabsOffset + - FUNCDESC_TAB_SIZE) & (~FUNCDESC_TAB_SIZE); - - funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE; - contextSavesOffset = funcDescTabsOffset + funcDescTabsSize; - contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE); - fixedSize = - taskTableSize + varTabsSize + funcDescTabsSize + - contextSavesSize; - - /* zero the thing out */ - fixedPtr = (u32 *) taskTableDest; - for (i = 0; i < (fixedSize / 4); i++) - fixedPtr[i] = 0; - - entryPtr = (TaskTableEntry *) MCD_taskTable; - /* set up fixed pointers */ - for (i = 0; i < NCHANNELS; i++) { - /* update ptr to local value */ - entryPtr[i].varTab = (u32) varTabsOffset; - entryPtr[i].FDTandFlags = - (u32) funcDescTabsOffset | MCD_TT_FLAGS_DEF; - entryPtr[i].contextSaveSpace = (u32) contextSavesOffset; - varTabsOffset += VAR_TAB_SIZE; -#ifdef MCD_INCLUDE_EU - /* if not there is only one, just point to the - same one */ - funcDescTabsOffset += FUNCDESC_TAB_SIZE; -#endif - contextSavesOffset += CONTEXT_SAVE_SIZE; - } - /* copy over the function descriptor table */ - for (i = 0; i < FUNCDESC_TAB_NUM; i++) { - MCD_memcpy((void *)(entryPtr[i]. - FDTandFlags & ~MCD_TT_FLAGS_MASK), - (void *)MCD_funcDescTab0, FUNCDESC_TAB_SIZE); - } - - /* copy model task table to where the context saves stuff - leaves off */ - MCD_modelTaskTable = (TaskTableEntry *) contextSavesOffset; - - MCD_memcpy((void *)MCD_modelTaskTable, - (void *)MCD_modelTaskTableSrc, - NUMOFVARIANTS * sizeof(TaskTableEntry)); - - /* point to local version of model task table */ - entryPtr = MCD_modelTaskTable; - taskDescTabsOffset = (u32) MCD_modelTaskTable + - (NUMOFVARIANTS * sizeof(TaskTableEntry)); - - /* copy actual task code and update TDT ptrs in local - model task table */ - for (i = 0; i < NUMOFVARIANTS; i++) { - taskDescTabSize = - entryPtr[i].TDTend - entryPtr[i].TDTstart + 4; - MCD_memcpy((void *)taskDescTabsOffset, - (void *)entryPtr[i].TDTstart, - taskDescTabSize); - entryPtr[i].TDTstart = (u32) taskDescTabsOffset; - taskDescTabsOffset += taskDescTabSize; - entryPtr[i].TDTend = (u32) taskDescTabsOffset - 4; - } -#ifdef MCD_INCLUDE_EU - /* Tack single DMA BDs onto end of code so API controls - where they are since DMA might write to them */ - MCD_relocBuffDesc = - (MCD_bufDesc *) (entryPtr[NUMOFVARIANTS - 1].TDTend + 4); -#else - /* DMA does not touch them so they can be wherever and we - don't need to waste SRAM on them */ - MCD_relocBuffDesc = MCD_singleBufDescs; -#endif - } else { - /* point the would-be relocated task tables and the - buffer descriptors to the ones the linker generated */ - - if (((u32) MCD_realTaskTableSrc & 0x000001ff) != 0) - return (MCD_TABLE_UNALIGNED); - - /* need to add code to make sure that every thing else is - aligned properly TBD. this is problematic if we init - more than once or after running tasks, need to add - variable to see if we have aleady init'd */ - entryPtr = MCD_realTaskTableSrc; - for (i = 0; i < NCHANNELS; i++) { - if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) || - ((entryPtr[i]. - FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0)) - return (MCD_TABLE_UNALIGNED); - } - - MCD_taskTable = MCD_realTaskTableSrc; - MCD_modelTaskTable = MCD_modelTaskTableSrc; - MCD_relocBuffDesc = MCD_singleBufDescs; - } - - /* Make all channels as totally inactive, and remember them as such: */ - - MCD_dmaBar->taskbar = (u32) MCD_taskTable; - for (i = 0; i < NCHANNELS; i++) { - MCD_dmaBar->taskControl[i] = 0x0; - MCD_chStatus[i] = MCD_NO_DMA; - } - - /* Set up pausing mechanism to inactive state: */ - /* no particular values yet for either comparator registers */ - MCD_dmaBar->debugComp1 = 0; - MCD_dmaBar->debugComp2 = 0; - MCD_dmaBar->debugControl = DBG_CTL_DISABLE; - MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT; - - /* enable or disable commbus prefetch, really need an ifdef or - something to keep from trying to set this in the 8220 */ - if ((flags & MCD_COMM_PREFETCH_EN) != 0) - MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH; - else - MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH; - - return (MCD_OK); -} - -/*********************** End of MCD_initDma() ***********************/ - -/********************************************************************/ -/* Function: MCD_dmaStatus - * Purpose: Returns the status of the DMA on the requested channel - * Arguments: channel - channel number - * Returns: Predefined status indicators - */ -int MCD_dmaStatus(int channel) -{ - u16 tcrValue; - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - tcrValue = MCD_dmaBar->taskControl[channel]; - if ((tcrValue & TASK_CTL_EN) == 0) { /* nothing running */ - /* if last reported with task enabled */ - if (MCD_chStatus[channel] == MCD_RUNNING - || MCD_chStatus[channel] == MCD_IDLE) - MCD_chStatus[channel] = MCD_DONE; - } else { /* something is running */ - - /* There are three possibilities: paused, running or idle. */ - if (MCD_chStatus[channel] == MCD_RUNNING - || MCD_chStatus[channel] == MCD_IDLE) { - MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; - /* This register is selected to know which initiator is - actually asserted. */ - if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) - MCD_chStatus[channel] = MCD_RUNNING; - else - MCD_chStatus[channel] = MCD_IDLE; - /* do not change the status if it is already paused. */ - } - } - return MCD_chStatus[channel]; -} - -/******************** End of MCD_dmaStatus() ************************/ - -/********************************************************************/ -/* Function: MCD_startDma - * Ppurpose: Starts a particular kind of DMA - * Arguments: - * srcAddr - the channel on which to run the DMA - * srcIncr - the address to move data from, or buffer-descriptor address - * destAddr - the amount to increment the source address per transfer - * destIncr - the address to move data to - * dmaSize - the amount to increment the destination address per transfer - * xferSize - the number bytes in of each data movement (1, 2, or 4) - * initiator - what device initiates the DMA - * priority - priority of the DMA - * flags - flags describing the DMA - * funcDesc - description of byte swapping, bit swapping, and CRC actions - * srcAddrVirt - virtual buffer descriptor address TBD - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ - -int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr, - s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator, - int priority, u32 flags, u32 funcDesc -#ifdef MCD_NEED_ADDR_TRANS - s8 * srcAddrVirt -#endif - ) -{ - int srcRsdIncr, destRsdIncr; - int *cSave; - short xferSizeIncr; - int tcrCount = 0; -#ifdef MCD_INCLUDE_EU - u32 *realFuncArray; -#endif - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - /* tbd - need to determine the proper response to a bad funcDesc when - not including EU functions, for now, assign a benign funcDesc, but - maybe should return an error */ -#ifndef MCD_INCLUDE_EU - funcDesc = MCD_FUNC_NOEU1; -#endif - -#ifdef MCD_DEBUG - printf("startDma:Setting up params\n"); -#endif - /* Set us up for task-wise priority. We don't technically need to do - this on every start, but since the register involved is in the same - longword as other registers that users are in control of, setting - it more than once is probably preferable. That since the - documentation doesn't seem to be completely consistent about the - nature of the PTD control register. */ - MCD_dmaBar->ptdControl |= (u16) 0x8000; - - /* Not sure what we need to keep here rtm TBD */ -#if 1 - /* Calculate additional parameters to the regular DMA calls. */ - srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0); - destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0); - - xferSizeIncr = (xferSize & 0xffff) | 0x20000000; - - /* Remember for each channel which variant is running. */ - MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr; - MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr; - MCD_remVariants.remDestIncr[channel] = destIncr; - MCD_remVariants.remSrcIncr[channel] = srcIncr; - MCD_remVariants.remXferSize[channel] = xferSize; -#endif - - cSave = - (int *)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + - CURRBD; - -#ifdef MCD_INCLUDE_EU - /* may move this to EU specific calls */ - realFuncArray = - (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00); - /* Modify the LURC's normal and byte-residue-loop functions according - to parameter. */ - realFuncArray[(LURC * 16)] = xferSize == 4 ? - funcDesc : xferSize == 2 ? - funcDesc & 0xfffff00f : funcDesc & 0xffff000f; - realFuncArray[(LURC * 16 + 1)] = - (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL; -#endif - /* Write the initiator field in the TCR, and also set the - initiator-hold bit. Note that,due to a hardware quirk, this could - collide with an MDE access to the initiator-register file, so we - have to verify that the write reads back correctly. */ - - MCD_dmaBar->taskControl[channel] = - (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM; - - while (((MCD_dmaBar->taskControl[channel] & 0x1fff) != - ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) - && (tcrCount < 1000)) { - tcrCount++; - /*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020; */ - MCD_dmaBar->taskControl[channel] = - (initiator << 8) | TASK_CTL_HIPRITSKEN | - TASK_CTL_HLDINITNUM; - } - - MCD_dmaBar->priority[channel] = (u8) priority & PRIORITY_PRI_MASK; - /* should be albe to handle this stuff with only one write to ts reg - - tbd */ - if (channel < 8 && channel >= 0) { - MCD_dmaBar->taskSize0 &= ~(0xf << (7 - channel) * 4); - MCD_dmaBar->taskSize0 |= - (xferSize & 3) << (((7 - channel) * 4) + 2); - MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel) * 4); - } else { - MCD_dmaBar->taskSize1 &= ~(0xf << (15 - channel) * 4); - MCD_dmaBar->taskSize1 |= - (xferSize & 3) << (((15 - channel) * 4) + 2); - MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel) * 4); - } - - /* setup task table flags/options which mostly control the line - buffers */ - MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK; - MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags); - - if (flags & MCD_FECTX_DMA) { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_FECTX].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_FECTX].TDTend; - MCD_startDmaENetXmit((char *)srcAddr, (char *)srcAddr, - (char *)destAddr, MCD_taskTable, - channel); - } else if (flags & MCD_FECRX_DMA) { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_FECRX].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_FECRX].TDTend; - MCD_startDmaENetRcv((char *)srcAddr, (char *)srcAddr, - (char *)destAddr, MCD_taskTable, - channel); - } else if (flags & MCD_SINGLE_DMA) { - /* this buffer descriptor is used for storing off initial - parameters for later progress query calculation and for the - DMA to write the resulting checksum. The DMA does not use - this to determine how to operate, that info is passed with - the init routine */ - MCD_relocBuffDesc[channel].srcAddr = srcAddr; - MCD_relocBuffDesc[channel].destAddr = destAddr; - - /* definitely not its final value */ - MCD_relocBuffDesc[channel].lastDestAddr = destAddr; - - MCD_relocBuffDesc[channel].dmaSize = dmaSize; - MCD_relocBuffDesc[channel].flags = 0; /* not used */ - MCD_relocBuffDesc[channel].csumResult = 0; /* not used */ - MCD_relocBuffDesc[channel].next = 0; /* not used */ - - /* Initialize the progress-querying stuff to show no - progress: */ - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[CURRBD + CSAVE_OFFSET] = -(u32) & (MCD_relocBuffDesc[channel]); - /* tbd - need to keep the user from trying to call the EU - routine when MCD_INCLUDE_EU is not defined */ - if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_SINGLENOEU].TDTend; - MCD_startDmaSingleNoEu((char *)srcAddr, srcIncr, - (char *)destAddr, destIncr, - (int)dmaSize, xferSizeIncr, - flags, (int *) - &(MCD_relocBuffDesc[channel]), - cSave, MCD_taskTable, channel); - } else { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_SINGLEEU].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_SINGLEEU].TDTend; - MCD_startDmaSingleEu((char *)srcAddr, srcIncr, - (char *)destAddr, destIncr, - (int)dmaSize, xferSizeIncr, - flags, (int *) - &(MCD_relocBuffDesc[channel]), - cSave, MCD_taskTable, channel); - } - } else { /* chained DMAS */ - /* Initialize the progress-querying stuff to show no - progress: */ -#if 1 - /* (!defined(MCD_NEED_ADDR_TRANS)) */ - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc *) srcAddr)->srcAddr; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc *) srcAddr)->destAddr; -#else - /* if using address translation, need the virtual addr of the - first buffdesc */ - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc *) srcAddrVirt)->destAddr; -#endif - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr; - - if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) { - /*TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_CHAINNOEU].TDTend; - MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, - destIncr, xferSize, - xferSizeIncr, cSave, - MCD_taskTable, channel); - } else { - /*TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_CHAINEU].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_CHAINEU].TDTend; - MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, - xferSize, xferSizeIncr, cSave, - MCD_taskTable, channel); - } - } - MCD_chStatus[channel] = MCD_IDLE; - return (MCD_OK); -} - -/************************ End of MCD_startDma() *********************/ - -/********************************************************************/ -/* Function: MCD_XferProgrQuery - * Purpose: Returns progress of DMA on requested channel - * Arguments: channel - channel to retrieve progress for - * progRep - pointer to user supplied MCD_XferProg struct - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * MCD_XferProgrQuery() upon completing or after aborting a DMA, or - * while the DMA is in progress, this function returns the first - * DMA-destination address not (or not yet) used in the DMA. When - * encountering a non-ready buffer descriptor, the information for - * the last completed descriptor is returned. - * - * MCD_XferProgQuery() has to avoid the possibility of getting - * partially-updated information in the event that we should happen - * to query DMA progress just as the DMA is updating it. It does that - * by taking advantage of the fact context is not saved frequently for - * the most part. We therefore read it at least twice until we get the - * same information twice in a row. - * - * Because a small, but not insignificant, amount of time is required - * to write out the progress-query information, especially upon - * completion of the DMA, it would be wise to guarantee some time lag - * between successive readings of the progress-query information. - */ - -/* How many iterations of the loop below to execute to stabilize values */ -#define STABTIME 0 - -int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep) -{ - MCD_XferProg prevRep; - int again; /* true if we are to try again to ge - consistent results */ - int i; /* used as a time-waste counter */ - int destDiffBytes; /* Total no of bytes that we think actually - got xfered. */ - int numIterations; /* number of iterations */ - int bytesNotXfered; /* bytes that did not get xfered. */ - s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr; - int subModVal, addModVal; /* Mode values to added and subtracted - from the final destAddr */ - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - /* Read a trial value for the progress-reporting values */ - prevRep.lastSrcAddr = - (s8 *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; - prevRep.lastDestAddr = - (s8 *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; - prevRep.dmaSize = - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + - CSAVE_OFFSET]; - prevRep.currBufDesc = - (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[CURRBD + CSAVE_OFFSET]; - /* Repeatedly reread those values until they match previous values: */ - do { - /* Waste a little bit of time to ensure stability: */ - for (i = 0; i < STABTIME; i++) { - /* make sure this loop does something so that it - doesn't get optimized out */ - i += i >> 2; - } - /* Check them again: */ - progRep->lastSrcAddr = - (s8 *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; - progRep->lastDestAddr = - (s8 *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; - progRep->dmaSize = - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DCOUNT + CSAVE_OFFSET]; - progRep->currBufDesc = - (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[CURRBD + CSAVE_OFFSET]; - /* See if they match: */ - if (prevRep.lastSrcAddr != progRep->lastSrcAddr - || prevRep.lastDestAddr != progRep->lastDestAddr - || prevRep.dmaSize != progRep->dmaSize - || prevRep.currBufDesc != progRep->currBufDesc) { - /* If they don't match, remember previous values and - try again: */ - prevRep.lastSrcAddr = progRep->lastSrcAddr; - prevRep.lastDestAddr = progRep->lastDestAddr; - prevRep.dmaSize = progRep->dmaSize; - prevRep.currBufDesc = progRep->currBufDesc; - again = MCD_TRUE; - } else - again = MCD_FALSE; - } while (again == MCD_TRUE); - - /* Update the dCount, srcAddr and destAddr */ - /* To calculate dmaCount, we consider destination address. C - overs M1,P1,Z for destination */ - switch (MCD_remVariants.remDestRsdIncr[channel]) { - case MINUS1: - subModVal = - ((int)progRep-> - lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - - 1); - addModVal = - ((int)progRep->currBufDesc-> - destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); - LWAlignedInitDestAddr = - (progRep->currBufDesc->destAddr) - addModVal; - LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal; - destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr; - bytesNotXfered = - (destDiffBytes / MCD_remVariants.remDestIncr[channel]) * - (MCD_remVariants.remDestIncr[channel] - + MCD_remVariants.remXferSize[channel]); - progRep->dmaSize = - destDiffBytes - bytesNotXfered + addModVal - subModVal; - break; - case ZERO: - progRep->lastDestAddr = progRep->currBufDesc->destAddr; - break; - case PLUS1: - /* This value has to be subtracted from the final - calculated dCount. */ - subModVal = - ((int)progRep->currBufDesc-> - destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); - /* These bytes are already in lastDestAddr. */ - addModVal = - ((int)progRep-> - lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - - 1); - LWAlignedInitDestAddr = - (progRep->currBufDesc->destAddr) - subModVal; - LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal; - destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr); - numIterations = - (LWAlignedCurrDestAddr - - LWAlignedInitDestAddr) / - MCD_remVariants.remDestIncr[channel]; - bytesNotXfered = - numIterations * (MCD_remVariants.remDestIncr[channel] - - MCD_remVariants.remXferSize[channel]); - progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal; - break; - default: - break; - } - - /* This covers M1,P1,Z for source */ - switch (MCD_remVariants.remSrcRsdIncr[channel]) { - case MINUS1: - progRep->lastSrcAddr = - progRep->currBufDesc->srcAddr + - (MCD_remVariants.remSrcIncr[channel] * - (progRep->dmaSize / MCD_remVariants.remXferSize[channel])); - break; - case ZERO: - progRep->lastSrcAddr = progRep->currBufDesc->srcAddr; - break; - case PLUS1: - progRep->lastSrcAddr = - progRep->currBufDesc->srcAddr + - (MCD_remVariants.remSrcIncr[channel] * - (progRep->dmaSize / MCD_remVariants.remXferSize[channel])); - break; - default: - break; - } - - return (MCD_OK); -} - -/******************* End of MCD_XferProgrQuery() ********************/ - -/********************************************************************/ -/* MCD_resmActions() does the majority of the actions of a DMA resume. - * It is called from MCD_killDma() and MCD_resumeDma(). It has to be - * a separate function because the kill function has to negate the task - * enable before resuming it, but the resume function has to do nothing - * if there is no DMA on that channel (i.e., if the enable bit is 0). - */ -static void MCD_resmActions(int channel) -{ - MCD_dmaBar->debugControl = DBG_CTL_DISABLE; - MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus; - /* This register is selected to know which initiator is - actually asserted. */ - MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; - - if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) - MCD_chStatus[channel] = MCD_RUNNING; - else - MCD_chStatus[channel] = MCD_IDLE; -} - -/********************* End of MCD_resmActions() *********************/ - -/********************************************************************/ -/* Function: MCD_killDma - * Purpose: Halt the DMA on the requested channel, without any - * intention of resuming the DMA. - * Arguments: channel - requested channel - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * A DMA may be killed from any state, including paused state, and it - * always goes to the MCD_HALTED state even if it is killed while in - * the MCD_NO_DMA or MCD_IDLE states. - */ -int MCD_killDma(int channel) -{ - /* MCD_XferProg progRep; */ - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - MCD_dmaBar->taskControl[channel] = 0x0; - MCD_resumeDma(channel); - /* - * This must be after the write to the TCR so that the task doesn't - * start up again momentarily, and before the status assignment so - * as to override whatever MCD_resumeDma() may do to the channel - * status. - */ - MCD_chStatus[channel] = MCD_HALTED; - - /* - * Update the current buffer descriptor's lastDestAddr field - * - * MCD_XferProgrQuery (channel, &progRep); - * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr; - */ - return (MCD_OK); -} - -/************************ End of MCD_killDma() **********************/ - -/********************************************************************/ -/* Function: MCD_continDma - * Purpose: Continue a DMA which as stopped due to encountering an - * unready buffer descriptor. - * Arguments: channel - channel to continue the DMA on - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * This routine does not check to see if there is a task which can - * be continued. Also this routine should not be used with single DMAs. - */ -int MCD_continDma(int channel) -{ - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN; - MCD_chStatus[channel] = MCD_RUNNING; - - return (MCD_OK); -} - -/********************** End of MCD_continDma() **********************/ - -/********************************************************************* - * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit - * to freeze a task and resume it. We freeze a task by breakpointing - * on the stated task. That is, not any specific place in the task, - * but any time that task executes. In particular, when that task - * executes, we want to freeze that task and only that task. - * - * The bits of the debug control register influence interrupts vs. - * breakpoints as follows: - * - Bits 14 and 0 enable or disable debug functions. If enabled, you - * will get the interrupt but you may or may not get a breakpoint. - * - Bits 2 and 1 decide whether you also get a breakpoint in addition - * to an interrupt. - * - * The debug unit can do these actions in response to either internally - * detected breakpoint conditions from the comparators, or in response - * to the external breakpoint pin, or both. - * - Bits 14 and 1 perform the above-described functions for - * internally-generated conditions, i.e., the debug comparators. - * - Bits 0 and 2 perform the above-described functions for external - * conditions, i.e., the breakpoint external pin. - * - * Note that, although you "always" get the interrupt when you turn - * the debug functions, the interrupt can nevertheless, if desired, be - * masked by the corresponding bit in the PTD's IMR. Note also that - * this means that bits 14 and 0 must enable debug functions before - * bits 1 and 2, respectively, have any effect. - * - * NOTE: It's extremely important to not pause more than one DMA channel - * at a time. - ********************************************************************/ - -/********************************************************************/ -/* Function: MCD_pauseDma - * Purpose: Pauses the DMA on a given channel (if any DMA is running - * on that channel). - * Arguments: channel - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ -int MCD_pauseDma(int channel) -{ - /* MCD_XferProg progRep; */ - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) { - MCD_dmaBar->debugComp1 = channel; - MCD_dmaBar->debugControl = - DBG_CTL_ENABLE | (1 << (channel + 16)); - MCD_chStatus[channel] = MCD_PAUSED; - - /* - * Update the current buffer descriptor's lastDestAddr field - * - * MCD_XferProgrQuery (channel, &progRep); - * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr; - */ - } - return (MCD_OK); -} - -/************************* End of MCD_pauseDma() ********************/ - -/********************************************************************/ -/* Function: MCD_resumeDma - * Purpose: Resumes the DMA on a given channel (if any DMA is - * running on that channel). - * Arguments: channel - channel on which to resume DMA - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ -int MCD_resumeDma(int channel) -{ - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) - MCD_resmActions(channel); - - return (MCD_OK); -} - -/************************ End of MCD_resumeDma() ********************/ - -/********************************************************************/ -/* Function: MCD_csumQuery - * Purpose: Provide the checksum after performing a non-chained DMA - * Arguments: channel - channel to report on - * csum - pointer to where to write the checksum/CRC - * Returns: MCD_ERROR if the channel is invalid, else MCD_OK - * - * Notes: - * - */ -int MCD_csumQuery(int channel, u32 * csum) -{ -#ifdef MCD_INCLUDE_EU - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - *csum = MCD_relocBuffDesc[channel].csumResult; - return (MCD_OK); -#else - return (MCD_ERROR); -#endif -} - -/*********************** End of MCD_resumeDma() *********************/ - -/********************************************************************/ -/* Function: MCD_getCodeSize - * Purpose: Provide the size requirements of the microcoded tasks - * Returns: Size in bytes - */ -int MCD_getCodeSize(void) -{ -#ifdef MCD_INCLUDE_EU - return (0x2b5c); -#else - return (0x173c); -#endif -} - -/********************** End of MCD_getCodeSize() ********************/ - -/********************************************************************/ -/* Function: MCD_getVersion - * Purpose: Provide the version string and number - * Arguments: longVersion - user supplied pointer to a pointer to a char - * which points to the version string - * Returns: Version number and version string (by reference) - */ -char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)"; -#define MCD_REV_MAJOR 0x00 -#define MCD_REV_MINOR 0x03 - -int MCD_getVersion(char **longVersion) -{ - *longVersion = MCD_versionString; - return ((MCD_REV_MAJOR << 8) | MCD_REV_MINOR); -} - -/********************** End of MCD_getVersion() *********************/ - -/********************************************************************/ -/* Private version of memcpy() - * Note that everything this is used for is longword-aligned. - */ -static void MCD_memcpy(int *dest, int *src, u32 size) -{ - u32 i; - - for (i = 0; i < size; i += sizeof(int), dest++, src++) - *dest = *src; -} diff --git a/drivers/dma/MCD_tasks.c b/drivers/dma/MCD_tasks.c deleted file mode 100644 index 453d95413da..00000000000 --- a/drivers/dma/MCD_tasks.c +++ /dev/null @@ -1,2413 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -/* Contains task code and structures for Multi-channel DMA */ - -#include <common.h> - -#include <MCD_dma.h> - -u32 MCD_varTab0[]; -u32 MCD_varTab1[]; -u32 MCD_varTab2[]; -u32 MCD_varTab3[]; -u32 MCD_varTab4[]; -u32 MCD_varTab5[]; -u32 MCD_varTab6[]; -u32 MCD_varTab7[]; -u32 MCD_varTab8[]; -u32 MCD_varTab9[]; -u32 MCD_varTab10[]; -u32 MCD_varTab11[]; -u32 MCD_varTab12[]; -u32 MCD_varTab13[]; -u32 MCD_varTab14[]; -u32 MCD_varTab15[]; - -u32 MCD_funcDescTab0[]; -#ifdef MCD_INCLUDE_EU -u32 MCD_funcDescTab1[]; -u32 MCD_funcDescTab2[]; -u32 MCD_funcDescTab3[]; -u32 MCD_funcDescTab4[]; -u32 MCD_funcDescTab5[]; -u32 MCD_funcDescTab6[]; -u32 MCD_funcDescTab7[]; -u32 MCD_funcDescTab8[]; -u32 MCD_funcDescTab9[]; -u32 MCD_funcDescTab10[]; -u32 MCD_funcDescTab11[]; -u32 MCD_funcDescTab12[]; -u32 MCD_funcDescTab13[]; -u32 MCD_funcDescTab14[]; -u32 MCD_funcDescTab15[]; -#endif - -u32 MCD_contextSave0[]; -u32 MCD_contextSave1[]; -u32 MCD_contextSave2[]; -u32 MCD_contextSave3[]; -u32 MCD_contextSave4[]; -u32 MCD_contextSave5[]; -u32 MCD_contextSave6[]; -u32 MCD_contextSave7[]; -u32 MCD_contextSave8[]; -u32 MCD_contextSave9[]; -u32 MCD_contextSave10[]; -u32 MCD_contextSave11[]; -u32 MCD_contextSave12[]; -u32 MCD_contextSave13[]; -u32 MCD_contextSave14[]; -u32 MCD_contextSave15[]; - -u32 MCD_realTaskTableSrc[] = { - 0x00000000, - 0x00000000, - (u32) MCD_varTab0, /* Task 0 Variable Table */ - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ - 0x00000000, - 0x00000000, - (u32) MCD_contextSave0, /* Task 0 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab1, /* Task 1 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab1, /* Task 1 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave1, /* Task 1 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab2, /* Task 2 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab2, /* Task 2 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave2, /* Task 2 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab3, /* Task 3 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab3, /* Task 3 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave3, /* Task 3 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab4, /* Task 4 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab4, /* Task 4 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave4, /* Task 4 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab5, /* Task 5 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab5, /* Task 5 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave5, /* Task 5 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab6, /* Task 6 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab6, /* Task 6 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave6, /* Task 6 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab7, /* Task 7 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab7, /* Task 7 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave7, /* Task 7 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab8, /* Task 8 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab8, /* Task 8 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave8, /* Task 8 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab9, /* Task 9 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab9, /* Task 9 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave9, /* Task 9 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab10, /* Task 10 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab10, /* Task 10 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave10, /* Task 10 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab11, /* Task 11 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab11, /* Task 11 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave11, /* Task 11 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab12, /* Task 12 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab12, /* Task 12 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave12, /* Task 12 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab13, /* Task 13 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab13, /* Task 13 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave13, /* Task 13 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab14, /* Task 14 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab14, /* Task 14 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave14, /* Task 14 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab15, /* Task 15 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab15, /* Task 15 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave15, /* Task 15 context save space */ - 0x00000000, -}; - -u32 MCD_varTab0[] = { /* Task 0 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab1[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab2[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab3[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab4[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab5[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab6[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab7[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab8[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab9[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab10[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab11[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab12[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab13[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab14[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab15[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_funcDescTab0[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -#ifdef MCD_INCLUDE_EU -u32 MCD_funcDescTab1[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab2[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab3[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab4[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab5[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab6[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab7[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab8[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab9[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab10[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab11[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab12[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab13[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab14[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab15[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; -#endif /*MCD_INCLUDE_EU */ - -u32 MCD_contextSave0[128]; /* Task 0 context save space */ -u32 MCD_contextSave1[128]; /* Task 1 context save space */ -u32 MCD_contextSave2[128]; /* Task 2 context save space */ -u32 MCD_contextSave3[128]; /* Task 3 context save space */ -u32 MCD_contextSave4[128]; /* Task 4 context save space */ -u32 MCD_contextSave5[128]; /* Task 5 context save space */ -u32 MCD_contextSave6[128]; /* Task 6 context save space */ -u32 MCD_contextSave7[128]; /* Task 7 context save space */ -u32 MCD_contextSave8[128]; /* Task 8 context save space */ -u32 MCD_contextSave9[128]; /* Task 9 context save space */ -u32 MCD_contextSave10[128]; /* Task 10 context save space */ -u32 MCD_contextSave11[128]; /* Task 11 context save space */ -u32 MCD_contextSave12[128]; /* Task 12 context save space */ -u32 MCD_contextSave13[128]; /* Task 13 context save space */ -u32 MCD_contextSave14[128]; /* Task 14 context save space */ -u32 MCD_contextSave15[128]; /* Task 15 context save space */ - -u32 MCD_ChainNoEu_TDT[]; -u32 MCD_SingleNoEu_TDT[]; -#ifdef MCD_INCLUDE_EU -u32 MCD_ChainEu_TDT[]; -u32 MCD_SingleEu_TDT[]; -#endif -u32 MCD_ENetRcv_TDT[]; -u32 MCD_ENetXmit_TDT[]; - -u32 MCD_modelTaskTableSrc[] = { - (u32) MCD_ChainNoEu_TDT, - (u32) & ((u8 *) MCD_ChainNoEu_TDT)[0x0000016c], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_SingleNoEu_TDT, - (u32) & ((u8 *) MCD_SingleNoEu_TDT)[0x000000d4], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -#ifdef MCD_INCLUDE_EU - (u32) MCD_ChainEu_TDT, - (u32) & ((u8 *) MCD_ChainEu_TDT)[0x000001b4], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_SingleEu_TDT, - (u32) & ((u8 *) MCD_SingleEu_TDT)[0x00000124], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -#endif - (u32) MCD_ENetRcv_TDT, - (u32) & ((u8 *) MCD_ENetRcv_TDT)[0x0000009c], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_ENetXmit_TDT, - (u32) & ((u8 *) MCD_ENetXmit_TDT)[0x000000d0], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_ChainNoEu_TDT[] = { - 0x80004000, - 0x8118801b, - 0xb8c60018, - 0x10002b10, - 0x7000000d, - 0x018cf89f, - 0x6000000a, - 0x080cf89f, - 0x000001f8, - 0x98180364, - 0x8118801b, - 0xf8c6001a, - 0xb8c6601b, - 0x10002710, - 0x00000f18, - 0xb8c6001d, - 0x10001310, - 0x60000007, - 0x014cf88b, - 0x98c6001c, - 0x00000710, - 0x98c70018, - 0x10001f10, - 0x0000c818, - 0x000001f8, - 0xc1476018, - 0xc003231d, - 0x811a601b, - 0xc1862102, - 0x849be009, - 0x03fed7b8, - 0xda9b001b, - 0x9b9be01b, - 0x1000cb20, - 0x70000006, - 0x088cf88f, - 0x1000cb28, - 0x70000006, - 0x088cf88f, - 0x1000cb30, - 0x70000006, - 0x088cf88f, - 0x1000cb38, - 0x0000c728, - 0x000001f8, - 0xc1476018, - 0xc003241d, - 0x811a601b, - 0xda9b001b, - 0x9b9be01b, - 0x0000d3a0, - 0xc1862102, - 0x849be009, - 0x0bfed7b8, - 0xda9b001b, - 0x9b9be01b, - 0x1000cb20, - 0x70000006, - 0x088cf88f, - 0x1000cb28, - 0x70000006, - 0x088cf88f, - 0x1000cb30, - 0x70000006, - 0x088cf88f, - 0x1000cb38, - 0x0000c728, - 0x000001f8, - 0x8118801b, - 0xd8c60018, - 0x98c6601c, - 0x6000000b, - 0x0c8cfc9f, - 0x000001f8, - 0xa146001e, - 0x10000b08, - 0x10002050, - 0xb8c60018, - 0x10002b10, - 0x7000000a, - 0x080cf89f, - 0x6000000d, - 0x018cf89f, - 0x000001f8, - 0x8618801b, - 0x7000000e, - 0x084cf21f, - 0xd8990336, - 0x8019801b, - 0x040001f8, - 0x000001f8, - 0x000001f8, -}; - -u32 MCD_SingleNoEu_TDT[] = { - 0x8198001b, - 0x7000000d, - 0x080cf81f, - 0x8198801b, - 0x6000000e, - 0x084cf85f, - 0x000001f8, - 0x8298001b, - 0x7000000d, - 0x010cf81f, - 0x6000000e, - 0x018cf81f, - 0xc202601b, - 0xc002221c, - 0x809a601b, - 0xc10420c2, - 0x839be009, - 0x03fed7b8, - 0xda9b001b, - 0x9b9be01b, - 0x70000006, - 0x088cf889, - 0x1000cb28, - 0x70000006, - 0x088cf889, - 0x1000cb30, - 0x70000006, - 0x088cf889, - 0x0000cb38, - 0x000001f8, - 0xc202601b, - 0xc002229c, - 0x809a601b, - 0xda9b001b, - 0x9b9be01b, - 0x0000d3a0, - 0xc10420c2, - 0x839be009, - 0x0bfed7b8, - 0xda9b001b, - 0x9b9be01b, - 0x70000006, - 0x088cf889, - 0x1000cb28, - 0x70000006, - 0x088cf889, - 0x1000cb30, - 0x70000006, - 0x088cf889, - 0x0000cb38, - 0x000001f8, - 0xc318022d, - 0x8018801b, - 0x040001f8, -}; - -#ifdef MCD_INCLUDE_EU -u32 MCD_ChainEu_TDT[] = { - 0x80004000, - 0x8198801b, - 0xb8c68018, - 0x10002f10, - 0x7000000d, - 0x01ccf89f, - 0x6000000a, - 0x080cf89f, - 0x000001f8, - 0x981803a4, - 0x8198801b, - 0xf8c6801a, - 0xb8c6e01b, - 0x10002b10, - 0x00001318, - 0xb8c6801d, - 0x10001710, - 0x60000007, - 0x018cf88c, - 0x98c6801c, - 0x00000b10, - 0x98c78018, - 0x10002310, - 0x0000c820, - 0x000001f8, - 0x8698801b, - 0x7000000f, - 0x084cf2df, - 0xd899042d, - 0x8019801b, - 0x60000003, - 0x2cd7c7df, - 0xd8990364, - 0x8019801b, - 0x60000003, - 0x2c17c7df, - 0x000001f8, - 0xc1c7e018, - 0xc003a35e, - 0x819a601b, - 0xc206a142, - 0x851be009, - 0x63fe0000, - 0x0d4cfddf, - 0xda9b001b, - 0x9b9be01b, - 0x70000002, - 0x004cf81f, - 0x1000cb20, - 0x70000006, - 0x088cf891, - 0x1000cb28, - 0x70000006, - 0x088cf891, - 0x1000cb30, - 0x70000006, - 0x088cf891, - 0x1000cb38, - 0x0000c728, - 0x000001f8, - 0xc1c7e018, - 0xc003a49e, - 0x819a601b, - 0xda9b001b, - 0x9b9be01b, - 0x0000d3a0, - 0xc206a142, - 0x851be009, - 0x6bfe0000, - 0x0d4cfddf, - 0xda9b001b, - 0x9b9be01b, - 0x70000002, - 0x004cf81f, - 0x1000cb20, - 0x70000006, - 0x088cf891, - 0x1000cb28, - 0x70000006, - 0x088cf891, - 0x1000cb30, - 0x70000006, - 0x088cf891, - 0x1000cb38, - 0x0000c728, - 0x000001f8, - 0x8198801b, - 0xd8c68018, - 0x98c6e01c, - 0x6000000b, - 0x0c8cfc9f, - 0x0000cc08, - 0xa1c6801e, - 0x10000f08, - 0x10002458, - 0xb8c68018, - 0x10002f10, - 0x7000000a, - 0x080cf89f, - 0x6000000d, - 0x01ccf89f, - 0x000001f8, - 0x8698801b, - 0x7000000e, - 0x084cf25f, - 0xd899037f, - 0x8019801b, - 0x040001f8, - 0x000001f8, - 0x000001f8, -}; - -u32 MCD_SingleEu_TDT[] = { - 0x8218001b, - 0x7000000d, - 0x080cf81f, - 0x8218801b, - 0x6000000e, - 0x084cf85f, - 0x000001f8, - 0x8318001b, - 0x7000000d, - 0x014cf81f, - 0x6000000e, - 0x01ccf81f, - 0x8498001b, - 0x7000000f, - 0x080cf19f, - 0xd81882a4, - 0x8019001b, - 0x60000003, - 0x2c97c7df, - 0xd818826d, - 0x8019001b, - 0x60000003, - 0x2c17c7df, - 0x000001f8, - 0xc282e01b, - 0xc002a25e, - 0x811a601b, - 0xc184a102, - 0x841be009, - 0x63fe0000, - 0x0d4cfddf, - 0xda9b001b, - 0x9b9be01b, - 0x70000002, - 0x004cf99f, - 0x70000006, - 0x088cf88b, - 0x1000cb28, - 0x70000006, - 0x088cf88b, - 0x1000cb30, - 0x70000006, - 0x088cf88b, - 0x0000cb38, - 0x000001f8, - 0xc282e01b, - 0xc002a31e, - 0x811a601b, - 0xda9b001b, - 0x9b9be01b, - 0x0000d3a0, - 0xc184a102, - 0x841be009, - 0x6bfe0000, - 0x0d4cfddf, - 0xda9b001b, - 0x9b9be01b, - 0x70000002, - 0x004cf99f, - 0x70000006, - 0x088cf88b, - 0x1000cb28, - 0x70000006, - 0x088cf88b, - 0x1000cb30, - 0x70000006, - 0x088cf88b, - 0x0000cb38, - 0x000001f8, - 0x8144801c, - 0x0000c008, - 0xc398027f, - 0x8018801b, - 0x040001f8, -}; -#endif -u32 MCD_ENetRcv_TDT[] = { - 0x80004000, - 0x81988000, - 0x10000788, - 0x6000000a, - 0x080cf05f, - 0x98180209, - 0x81c40004, - 0x7000000e, - 0x010cf05f, - 0x7000000c, - 0x01ccf05f, - 0x70000004, - 0x014cf049, - 0x70000004, - 0x004cf04a, - 0x00000b88, - 0xc4030150, - 0x8119e012, - 0x03e0cf90, - 0x81188000, - 0x000ac788, - 0xc4030000, - 0x8199e000, - 0x70000004, - 0x084cfc8b, - 0x60000005, - 0x0cccf841, - 0x81c60000, - 0xc399021b, - 0x80198000, - 0x00008400, - 0x00000f08, - 0x81988000, - 0x10000788, - 0x6000000a, - 0x080cf05f, - 0xc2188209, - 0x80190000, - 0x040001f8, - 0x000001f8, -}; - -u32 MCD_ENetXmit_TDT[] = { - 0x80004000, - 0x81988000, - 0x10000788, - 0x6000000a, - 0x080cf05f, - 0x98180309, - 0x80004003, - 0x81c60004, - 0x7000000e, - 0x014cf05f, - 0x7000000c, - 0x028cf05f, - 0x7000000d, - 0x018cf05f, - 0x70000004, - 0x01ccf04d, - 0x10000b90, - 0x60000004, - 0x020cf0a1, - 0xc3188312, - 0x83c70000, - 0x00001f10, - 0xc583a3c3, - 0x81042325, - 0x03e0c798, - 0xd8990000, - 0x9999e000, - 0x000acf98, - 0xd8992306, - 0x9999e03f, - 0x03eac798, - 0xd8990000, - 0x9999e000, - 0x000acf98, - 0xd8990000, - 0x99832302, - 0x0beac798, - 0x81988000, - 0x6000000b, - 0x0c4cfc5f, - 0x81c80000, - 0xc5190312, - 0x80198000, - 0x00008400, - 0x00000f08, - 0x81988000, - 0x10000788, - 0x6000000a, - 0x080cf05f, - 0xc2988309, - 0x80190000, - 0x040001f8, - 0x000001f8, -}; - -#ifdef MCD_INCLUDE_EU -MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#endif diff --git a/drivers/dma/MCD_tasksInit.c b/drivers/dma/MCD_tasksInit.c deleted file mode 100644 index 079cd0af3c0..00000000000 --- a/drivers/dma/MCD_tasksInit.c +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -/* Functions for initializing variable tables of different types of tasks. */ - -/* - * Do not edit! - */ - -#include <MCD_dma.h> - -extern dmaRegs *MCD_dmaBar; - -/* Task 0 */ - -void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, - int xferSize, short xferSizeIncr, int *cSave, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */ - MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskChan, 11, (u32) xferSize); /* var[11] */ - MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */ - MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */ - MCD_SET_VAR(taskChan, 13, (u32) 0x80000000); /* var[13] */ - MCD_SET_VAR(taskChan, 14, (u32) 0x00000010); /* var[14] */ - MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */ - MCD_SET_VAR(taskChan, 16, (u32) 0x08000000); /* var[16] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0x80000001); /* inc[5] */ - MCD_SET_VAR(taskChan, 30, (u32) 0x40000000); /* inc[6] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 1 */ - -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, - short destIncr, int dmaSize, short xferSizeIncr, - int flags, int *currBD, int *cSave, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 7, (u32) srcAddr); /* var[7] */ - MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskChan, 2, (u32) destAddr); /* var[2] */ - MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskChan, 3, (u32) dmaSize); /* var[3] */ - MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskChan, 5, (u32) flags); /* var[5] */ - MCD_SET_VAR(taskChan, 1, (u32) currBD); /* var[1] */ - MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000004); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x08000000); /* var[10] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0x80000001); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0x40000000); /* inc[5] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 2 */ - -void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, - int xferSize, short xferSizeIncr, int *cSave, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */ - MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskChan, 12, (u32) xferSize); /* var[12] */ - MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */ - MCD_SET_VAR(taskChan, 11, (u32) 0x00000000); /* var[11] */ - MCD_SET_VAR(taskChan, 13, (u32) 0x00000000); /* var[13] */ - MCD_SET_VAR(taskChan, 14, (u32) 0x80000000); /* var[14] */ - MCD_SET_VAR(taskChan, 15, (u32) 0x00000010); /* var[15] */ - MCD_SET_VAR(taskChan, 16, (u32) 0x00000001); /* var[16] */ - MCD_SET_VAR(taskChan, 17, (u32) 0x00000004); /* var[17] */ - MCD_SET_VAR(taskChan, 18, (u32) 0x08000000); /* var[18] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0xc0000000); /* inc[5] */ - MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */ - MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 3 */ - -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, - short destIncr, int dmaSize, short xferSizeIncr, - int flags, int *currBD, int *cSave, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 8, (u32) srcAddr); /* var[8] */ - MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskChan, 3, (u32) destAddr); /* var[3] */ - MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskChan, 4, (u32) dmaSize); /* var[4] */ - MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskChan, 6, (u32) flags); /* var[6] */ - MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */ - MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x00000001); /* var[10] */ - MCD_SET_VAR(taskChan, 11, (u32) 0x00000004); /* var[11] */ - MCD_SET_VAR(taskChan, 12, (u32) 0x08000000); /* var[12] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0xc0000000); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */ - MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */ - MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 4 */ - -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */ - MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */ - MCD_SET_VAR(taskChan, 6, (u32) rcvFifoPtr); /* var[6] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x0000ffff); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x30000000); /* var[10] */ - MCD_SET_VAR(taskChan, 11, (u32) 0x0fffffff); /* var[11] */ - MCD_SET_VAR(taskChan, 12, (u32) 0x00000008); /* var[12] */ - MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */ - MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */ - MCD_SET_VAR(taskChan, 26, (u32) 0x20000004); /* inc[2] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x40000000); /* inc[3] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 5 */ - -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */ - MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */ - MCD_SET_VAR(taskChan, 11, (u32) xmitFifoPtr); /* var[11] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */ - MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */ - MCD_SET_VAR(taskChan, 13, (u32) 0x0000ffff); /* var[13] */ - MCD_SET_VAR(taskChan, 14, (u32) 0xffffffff); /* var[14] */ - MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */ - MCD_SET_VAR(taskChan, 16, (u32) 0x00000008); /* var[16] */ - MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */ - MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */ - MCD_SET_VAR(taskChan, 26, (u32) 0x40000000); /* inc[2] */ - MCD_SET_VAR(taskChan, 27, (u32) 0xc000fffc); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0xe0000004); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */ - MCD_SET_VAR(taskChan, 30, (u32) 0x4000ffff); /* inc[6] */ - MCD_SET_VAR(taskChan, 31, (u32) 0xe0000001); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index a75572fe5de..48811eaaeb3 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_DMA) += dma-uclass.o -obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 6807eb8e8b2..f4e0271efbf 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -8,3 +8,4 @@ k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o +k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o diff --git a/drivers/dma/ti/k3-psil-am62a.c b/drivers/dma/ti/k3-psil-am62a.c new file mode 100644 index 00000000000..ca9d71f9142 --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62a.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com + */ + +#include <linux/kernel.h> + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = -1, \ + .default_flow_id = -1, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = -1, \ + .default_flow_id = -1, \ + .pkt_mode = 1, \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 64, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = default_flow, \ + .notdpkt = tx, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .pdma_acc32 = 1, \ + .pdma_burst = 1, \ + }, \ + } + +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62a_src_ep_map[] = { + /* SAUL */ + PSIL_SAUL(0x7504, 20, 35, 8, 35, 0), + PSIL_SAUL(0x7505, 21, 35, 8, 36, 0), + PSIL_SAUL(0x7506, 22, 43, 8, 43, 0), + PSIL_SAUL(0x7507, 23, 43, 8, 44, 0), + /* PDMA_MAIN0 - SPI0-3 */ + PSIL_PDMA_XY_PKT(0x4302), + PSIL_PDMA_XY_PKT(0x4303), + PSIL_PDMA_XY_PKT(0x4304), + PSIL_PDMA_XY_PKT(0x4305), + PSIL_PDMA_XY_PKT(0x4306), + PSIL_PDMA_XY_PKT(0x4307), + PSIL_PDMA_XY_PKT(0x4308), + PSIL_PDMA_XY_PKT(0x4309), + PSIL_PDMA_XY_PKT(0x430a), + PSIL_PDMA_XY_PKT(0x430b), + PSIL_PDMA_XY_PKT(0x430c), + PSIL_PDMA_XY_PKT(0x430d), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400), + PSIL_PDMA_XY_PKT(0x4401), + PSIL_PDMA_XY_PKT(0x4402), + PSIL_PDMA_XY_PKT(0x4403), + PSIL_PDMA_XY_PKT(0x4404), + PSIL_PDMA_XY_PKT(0x4405), + PSIL_PDMA_XY_PKT(0x4406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500), + PSIL_PDMA_MCASP(0x4501), + PSIL_PDMA_MCASP(0x4502), + /* CPSW3G */ + PSIL_ETHERNET(0x4600, 19, 19, 16), + /* CSI2RX */ + PSIL_CSI2RX(0x5000), + PSIL_CSI2RX(0x5001), + PSIL_CSI2RX(0x5002), + PSIL_CSI2RX(0x5003), + PSIL_CSI2RX(0x5004), + PSIL_CSI2RX(0x5005), + PSIL_CSI2RX(0x5006), + PSIL_CSI2RX(0x5007), + PSIL_CSI2RX(0x5008), + PSIL_CSI2RX(0x5009), + PSIL_CSI2RX(0x500a), + PSIL_CSI2RX(0x500b), + PSIL_CSI2RX(0x500c), + PSIL_CSI2RX(0x500d), + PSIL_CSI2RX(0x500e), + PSIL_CSI2RX(0x500f), + PSIL_CSI2RX(0x5010), + PSIL_CSI2RX(0x5011), + PSIL_CSI2RX(0x5012), + PSIL_CSI2RX(0x5013), + PSIL_CSI2RX(0x5014), + PSIL_CSI2RX(0x5015), + PSIL_CSI2RX(0x5016), + PSIL_CSI2RX(0x5017), + PSIL_CSI2RX(0x5018), + PSIL_CSI2RX(0x5019), + PSIL_CSI2RX(0x501a), + PSIL_CSI2RX(0x501b), + PSIL_CSI2RX(0x501c), + PSIL_CSI2RX(0x501d), + PSIL_CSI2RX(0x501e), + PSIL_CSI2RX(0x501f), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62a_dst_ep_map[] = { + /* SAUL */ + PSIL_SAUL(0xf500, 27, 83, 8, 83, 1), + PSIL_SAUL(0xf501, 28, 91, 8, 91, 1), + /* PDMA_MAIN0 - SPI0-3 */ + PSIL_PDMA_XY_PKT(0xc302), + PSIL_PDMA_XY_PKT(0xc303), + PSIL_PDMA_XY_PKT(0xc304), + PSIL_PDMA_XY_PKT(0xc305), + PSIL_PDMA_XY_PKT(0xc306), + PSIL_PDMA_XY_PKT(0xc307), + PSIL_PDMA_XY_PKT(0xc308), + PSIL_PDMA_XY_PKT(0xc309), + PSIL_PDMA_XY_PKT(0xc30a), + PSIL_PDMA_XY_PKT(0xc30b), + PSIL_PDMA_XY_PKT(0xc30c), + PSIL_PDMA_XY_PKT(0xc30d), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xc400), + PSIL_PDMA_XY_PKT(0xc401), + PSIL_PDMA_XY_PKT(0xc402), + PSIL_PDMA_XY_PKT(0xc403), + PSIL_PDMA_XY_PKT(0xc404), + PSIL_PDMA_XY_PKT(0xc405), + PSIL_PDMA_XY_PKT(0xc406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xc500), + PSIL_PDMA_MCASP(0xc501), + PSIL_PDMA_MCASP(0xc502), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 19, 19, 8), + PSIL_ETHERNET(0xc601, 20, 27, 8), + PSIL_ETHERNET(0xc602, 21, 35, 8), + PSIL_ETHERNET(0xc603, 22, 43, 8), + PSIL_ETHERNET(0xc604, 23, 51, 8), + PSIL_ETHERNET(0xc605, 24, 59, 8), + PSIL_ETHERNET(0xc606, 25, 67, 8), + PSIL_ETHERNET(0xc607, 26, 75, 8), +}; + +struct psil_ep_map am62a_ep_map = { + .name = "am62a", + .src = am62a_src_ep_map, + .src_count = ARRAY_SIZE(am62a_src_ep_map), + .dst = am62a_dst_ep_map, + .dst_count = ARRAY_SIZE(am62a_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index 563bc57e206..83f873b84ce 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -42,5 +42,6 @@ extern struct psil_ep_map j721e_ep_map; extern struct psil_ep_map j721s2_ep_map; extern struct psil_ep_map am64_ep_map; extern struct psil_ep_map am62_ep_map; +extern struct psil_ep_map am62a_ep_map; #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index 963321aa1e3..d4d4fede8fa 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -26,6 +26,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id) soc_ep_map = &am64_ep_map; else if (IS_ENABLED(CONFIG_SOC_K3_AM625)) soc_ep_map = &am62_ep_map; + else if (IS_ENABLED(CONFIG_SOC_K3_AM62A7)) + soc_ep_map = &am62a_ep_map; } if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) { diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 837c6f1180d..11fc0fe1c80 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -1,4 +1,5 @@ menu "Fastboot support" + depends on CMDLINE config FASTBOOT bool diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 4e9d9b719c6..3576b067729 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -91,6 +91,7 @@ void fastboot_okay(const char *reason, char *response) */ int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) { + int ret; static const char * const boot_cmds[] = { [FASTBOOT_REBOOT_REASON_BOOTLOADER] = "bootonce-bootloader", [FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot", @@ -105,7 +106,18 @@ int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) if (reason >= FASTBOOT_REBOOT_REASONS_COUNT) return -EINVAL; - return bcb_write_reboot_reason(mmc_dev, "misc", boot_cmds[reason]); + ret = bcb_find_partition_and_load("mmc", mmc_dev, "misc"); + if (ret) + goto out; + + ret = bcb_set(BCB_FIELD_COMMAND, boot_cmds[reason]); + if (ret) + goto out; + + ret = bcb_store(); +out: + bcb_reset(); + return ret; } /** diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 8ea15c7ed33..dfad798a2e7 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -8,6 +8,7 @@ #include <common.h> #include <cpu_func.h> #include <dm.h> +#include <dm/device_compat.h> #include <dm/lists.h> #include <log.h> #include <zynqmp_firmware.h> @@ -290,10 +291,31 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) static int zynqmp_power_probe(struct udevice *dev) { + struct udevice *ipi_dev; + ofnode ipi_node; int ret; debug("%s, (dev=%p)\n", __func__, dev); + /* + * Probe all IPI parent node driver. It is important to have IPI + * devices available when requested by mbox_get_by* API. + * If IPI device isn't available, then mailbox request fails and + * that causes system boot failure. + * To avoid this make sure all IPI parent drivers are probed here, + * and IPI parent driver binds each child node to mailbox driver. + * This way mbox_get_by_* API will have correct mailbox device + * driver probed. + */ + ofnode_for_each_compatible_node(ipi_node, "xlnx,zynqmp-ipi-mailbox") { + ret = uclass_get_device_by_ofnode(UCLASS_NOP, ipi_node, &ipi_dev); + if (ret) { + dev_err(dev, "failed to get IPI device from node %s\n", + ofnode_get_name(ipi_node)); + return ret; + } + } + ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan); if (ret) { debug("%s: Cannot find tx mailbox\n", __func__); diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index d1318096266..cc9011c7312 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -66,10 +66,10 @@ struct scmi_channel { }; static u8 protocols[] = { - SCMI_PROTOCOL_ID_POWER_DOMAIN, - SCMI_PROTOCOL_ID_CLOCK, - SCMI_PROTOCOL_ID_RESET_DOMAIN, - SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, + CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN, (SCMI_PROTOCOL_ID_POWER_DOMAIN,)) + CONFIG_IS_ENABLED(CLK_SCMI, (SCMI_PROTOCOL_ID_CLOCK,)) + CONFIG_IS_ENABLED(RESET_SCMI, (SCMI_PROTOCOL_ID_RESET_DOMAIN,)) + CONFIG_IS_ENABLED(DM_REGULATOR_SCMI, (SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN,)) }; #define NUM_PROTOCOLS ARRAY_SIZE(protocols) @@ -1124,6 +1124,13 @@ unsigned int sandbox_scmi_channel_id(struct udevice *dev) return chan->channel_id; } +static int sandbox_proto_not_supported(struct scmi_msg *msg) +{ + *(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED; + + return 0; +} + static int sandbox_scmi_test_process_msg(struct udevice *dev, struct scmi_channel *channel, struct scmi_msg *msg) @@ -1160,6 +1167,9 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev, } break; case SCMI_PROTOCOL_ID_POWER_DOMAIN: + if (!CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN)) + return sandbox_proto_not_supported(msg); + switch (msg->message_id) { case SCMI_PROTOCOL_VERSION: return sandbox_scmi_pwd_protocol_version(dev, msg); @@ -1180,6 +1190,9 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev, } break; case SCMI_PROTOCOL_ID_CLOCK: + if (!CONFIG_IS_ENABLED(CLK_SCMI)) + return sandbox_proto_not_supported(msg); + switch (msg->message_id) { case SCMI_PROTOCOL_ATTRIBUTES: return sandbox_scmi_clock_protocol_attribs(dev, msg); @@ -1196,6 +1209,9 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev, } break; case SCMI_PROTOCOL_ID_RESET_DOMAIN: + if (!CONFIG_IS_ENABLED(RESET_SCMI)) + return sandbox_proto_not_supported(msg); + switch (msg->message_id) { case SCMI_RESET_DOMAIN_ATTRIBUTES: return sandbox_scmi_rd_attribs(dev, msg); @@ -1206,6 +1222,9 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev, } break; case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN: + if (!CONFIG_IS_ENABLED(DM_REGULATOR_SCMI)) + return sandbox_proto_not_supported(msg); + switch (msg->message_id) { case SCMI_VOLTAGE_DOMAIN_ATTRIBUTES: return sandbox_scmi_voltd_attribs(dev, msg); @@ -1224,8 +1243,7 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev, case SCMI_PROTOCOL_ID_SYSTEM: case SCMI_PROTOCOL_ID_PERF: case SCMI_PROTOCOL_ID_SENSOR: - *(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED; - return 0; + return sandbox_proto_not_supported(msg); default: break; } diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c index facb5b06ffb..603e2bb40af 100644 --- a/drivers/firmware/scmi/sandbox-scmi_devices.c +++ b/drivers/firmware/scmi/sandbox-scmi_devices.c @@ -62,12 +62,13 @@ static int sandbox_scmi_devices_remove(struct udevice *dev) if (!devices) return 0; - for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) { - int ret2 = reset_free(devices->reset + n); + if (CONFIG_IS_ENABLED(RESET_SCMI)) + for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) { + int ret2 = reset_free(devices->reset + n); - if (ret2 && !ret) - ret = ret2; - } + if (ret2 && !ret) + ret = ret2; + } return ret; } @@ -89,39 +90,53 @@ static int sandbox_scmi_devices_probe(struct udevice *dev) .regul_count = SCMI_TEST_DEVICES_VOLTD_COUNT, }; - ret = power_domain_get_by_index(dev, priv->devices.pwdom, 0); - if (ret) { - dev_err(dev, "%s: Failed on power domain\n", __func__); - return ret; - } - - for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) { - ret = clk_get_by_index(dev, n, priv->devices.clk + n); + if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN)) { + ret = power_domain_get_by_index(dev, priv->devices.pwdom, 0); if (ret) { - dev_err(dev, "%s: Failed on clk %zu\n", __func__, n); + dev_err(dev, "%s: Failed on power domain\n", __func__); return ret; } } - for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) { - ret = reset_get_by_index(dev, n, priv->devices.reset + n); - if (ret) { - dev_err(dev, "%s: Failed on reset %zu\n", __func__, n); - goto err_reset; + if (CONFIG_IS_ENABLED(CLK_SCMI)) { + for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) { + ret = clk_get_by_index(dev, n, priv->devices.clk + n); + if (ret) { + dev_err(dev, "%s: Failed on clk %zu\n", + __func__, n); + return ret; + } } } - for (n = 0; n < SCMI_TEST_DEVICES_VOLTD_COUNT; n++) { - char name[32]; - - ret = snprintf(name, sizeof(name), "regul%zu-supply", n); - assert(ret >= 0 && ret < sizeof(name)); + if (CONFIG_IS_ENABLED(RESET_SCMI)) { + for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) { + ret = reset_get_by_index(dev, n, + priv->devices.reset + n); + if (ret) { + dev_err(dev, "%s: Failed on reset %zu\n", + __func__, n); + goto err_reset; + } + } + } - ret = device_get_supply_regulator(dev, name, - priv->devices.regul + n); - if (ret) { - dev_err(dev, "%s: Failed on voltd %zu\n", __func__, n); - goto err_regul; + if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI)) { + for (n = 0; n < SCMI_TEST_DEVICES_VOLTD_COUNT; n++) { + char name[32]; + + ret = snprintf(name, sizeof(name), "regul%zu-supply", + n); + assert(ret >= 0 && ret < sizeof(name)); + + ret = device_get_supply_regulator(dev, name, + priv->devices.regul + + n); + if (ret) { + dev_err(dev, "%s: Failed on voltd %zu\n", + __func__, n); + goto err_regul; + } } } @@ -130,8 +145,9 @@ static int sandbox_scmi_devices_probe(struct udevice *dev) err_regul: n = SCMI_TEST_DEVICES_RD_COUNT; err_reset: - for (; n > 0; n--) - reset_free(priv->devices.reset + n - 1); + if (CONFIG_IS_ENABLED(RESET_SCMI)) + for (; n > 0; n--) + reset_free(priv->devices.reset + n - 1); return ret; } diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index b6c71789eec..eaa1d692898 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -20,6 +20,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/printk.h> +#include <linux/time.h> /* STM32 I2C registers */ struct stm32_i2c_regs { @@ -121,8 +122,6 @@ struct stm32_i2c_regs { #define STM32_SCLH_MAX BIT(8) #define STM32_SCLL_MAX BIT(8) -#define STM32_NSEC_PER_SEC 1000000000L - /** * struct stm32_i2c_spec - private i2c specification timing * @rate: I2C bus speed (Hz) @@ -591,7 +590,7 @@ static int stm32_i2c_choose_solution(u32 i2cclk, struct stm32_i2c_timings *s) { struct stm32_i2c_timings *v; - u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, + u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, setup->speed_freq); u32 clk_error_prev = i2cbus; u32 clk_min, clk_max; @@ -607,8 +606,8 @@ static int stm32_i2c_choose_solution(u32 i2cclk, dnf_delay = setup->dnf * i2cclk; tsync = af_delay_min + dnf_delay + (2 * i2cclk); - clk_max = STM32_NSEC_PER_SEC / specs->rate_min; - clk_min = STM32_NSEC_PER_SEC / specs->rate_max; + clk_max = NSEC_PER_SEC / specs->rate_min; + clk_min = NSEC_PER_SEC / specs->rate_max; /* * Among Prescaler possibilities discovered above figures out SCL Low @@ -686,7 +685,7 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, const struct stm32_i2c_spec *specs; struct stm32_i2c_timings *v, *_v; struct list_head solutions; - u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src); + u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, setup->clock_src); int ret; specs = get_specs(setup->speed_freq); diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 996b757e6d0..9837960198d 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -49,6 +49,14 @@ config LED_CORTINA This option enables support for LEDs connected to the Cortina Access CAxxxx SOCs. +config LED_LP5562 + bool "LED Support for LP5562" + depends on LED && DM_I2C + help + This option enables support for LEDs connected to the TI LP5562 + 4 channel I2C LED controller. Driver fully supports blink on the + B/G/R LEDs. White LED can blink, but re-uses the period from blue. + config LED_PWM bool "LED PWM" depends on LED && DM_PWM diff --git a/drivers/led/Makefile b/drivers/led/Makefile index 49ae91961d5..2bcb8589087 100644 --- a/drivers/led/Makefile +++ b/drivers/led/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o obj-$(CONFIG_LED_PWM) += led_pwm.o obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o obj-$(CONFIG_LED_CORTINA) += led_cortina.o +obj-$(CONFIG_LED_LP5562) += led_lp5562.o diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 68ca3c29702..a4be56fc258 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -11,9 +11,27 @@ #include <errno.h> #include <led.h> #include <dm/device-internal.h> +#include <dm/lists.h> #include <dm/root.h> #include <dm/uclass-internal.h> +int led_bind_generic(struct udevice *parent, const char *driver_name) +{ + struct udevice *dev; + ofnode node; + int ret; + + dev_for_each_subnode(node, parent) { + ret = device_bind_driver_to_node(parent, driver_name, + ofnode_get_name(node), + node, &dev); + if (ret) + return ret; + } + + return 0; +} + int led_get_by_label(const char *label, struct udevice **devp) { struct udevice *dev; @@ -71,8 +89,10 @@ static int led_post_bind(struct udevice *dev) struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); const char *default_state; - uc_plat->label = dev_read_string(dev, "label"); if (!uc_plat->label) + uc_plat->label = dev_read_string(dev, "label"); + + if (!uc_plat->label && !dev_read_string(dev, "compatible")) uc_plat->label = ofnode_get_name(dev_ofnode(dev)); uc_plat->default_state = LEDST_COUNT; diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c index fbed151b5d9..71421de628c 100644 --- a/drivers/led/led_gpio.c +++ b/drivers/led/led_gpio.c @@ -11,7 +11,6 @@ #include <log.h> #include <malloc.h> #include <asm/gpio.h> -#include <dm/lists.h> struct led_gpio_priv { struct gpio_desc gpio; @@ -80,19 +79,7 @@ static int led_gpio_remove(struct udevice *dev) static int led_gpio_bind(struct udevice *parent) { - struct udevice *dev; - ofnode node; - int ret; - - dev_for_each_subnode(node, parent) { - ret = device_bind_driver_to_node(parent, "gpio_led", - ofnode_get_name(node), - node, &dev); - if (ret) - return ret; - } - - return 0; + return led_bind_generic(parent, "gpio_led"); } static const struct led_ops gpio_led_ops = { diff --git a/drivers/led/led_lp5562.c b/drivers/led/led_lp5562.c new file mode 100644 index 00000000000..431d7e10ab7 --- /dev/null +++ b/drivers/led/led_lp5562.c @@ -0,0 +1,577 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Doug Zobel <douglas.zobel@climate.com> + * + * Driver for TI lp5562 4 channel LED driver. There are only 3 + * engines available for the 4 LEDs, so white and blue LEDs share + * the same engine. This means that the blink period is shared + * between them. Changing the period of blue blink will affect + * the white period (and vice-versa). Blue and white On/Off + * states remain independent (as would PWM brightness if that's + * ever added to the LED core). + */ + +#include <dm.h> +#include <errno.h> +#include <led.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <linux/delay.h> + +#define DEFAULT_CURRENT 100 /* 10 mA */ +#define MIN_BLINK_PERIOD 32 /* ms */ +#define MAX_BLINK_PERIOD 2248 /* ms */ + +/* Register Map */ +#define REG_ENABLE 0x00 +#define REG_OP_MODE 0x01 +#define REG_B_PWM 0x02 +#define REG_G_PWM 0x03 +#define REG_R_PWM 0x04 +#define REG_B_CUR 0x05 +#define REG_G_CUR 0x06 +#define REG_R_CUR 0x07 +#define REG_CONFIG 0x08 +#define REG_ENG1_PC 0x09 +#define REG_ENG2_PC 0x0A +#define REG_ENG3_PC 0x0B +#define REG_STATUS 0x0C +#define REG_RESET 0x0D +#define REG_W_PWM 0x0E +#define REG_W_CUR 0x0F +#define REG_ENG1_MEM_BEGIN 0x10 +#define REG_ENG2_MEM_BEGIN 0x30 +#define REG_ENG3_MEM_BEGIN 0x50 +#define REG_LED_MAP 0x70 + +/* LED Register Values */ +/* 0x00 ENABLE */ +#define REG_ENABLE_CHIP_ENABLE (0x1 << 6) +#define REG_ENABLE_ENG_EXEC_HOLD 0x0 +#define REG_ENABLE_ENG_EXEC_RUN 0x2 +#define REG_ENABLE_ENG_EXEC_MASK 0x3 + +/* 0x01 OP MODE */ +#define REG_OP_MODE_DISABLED 0x0 +#define REG_OP_MODE_LOAD_SRAM 0x1 +#define REG_OP_MODE_RUN 0x2 +#define REG_OP_MODE_MASK 0x3 + +/* 0x02, 0x03, 0x04, 0x0E PWM */ +#define REG_PWM_MIN_VALUE 0 +#define REG_PWM_MAX_VALUE 0xFF + +/* 0x08 CONFIG */ +#define REG_CONFIG_EXT_CLK 0x0 +#define REG_CONFIG_INT_CLK 0x1 +#define REG_CONFIG_AUTO_CLK 0x2 +#define REG_CONFIG_CLK_MASK 0x3 + +/* 0x0D RESET */ +#define REG_RESET_RESET 0xFF + +/* 0x70 LED MAP */ +#define REG_LED_MAP_ENG_MASK 0x03 +#define REG_LED_MAP_W_ENG_SHIFT 6 +#define REG_LED_MAP_R_ENG_SHIFT 4 +#define REG_LED_MAP_G_ENG_SHIFT 2 +#define REG_LED_MAP_B_ENG_SHIFT 0 + +/* Engine program related */ +#define REG_ENGINE_MEM_SIZE 0x20 +#define LED_PGRM_RAMP_INCREMENT_SHIFT 0 +#define LED_PGRM_RAMP_SIGN_SHIFT 7 +#define LED_PGRM_RAMP_STEP_SHIFT 8 +#define LED_PGRM_RAMP_PRESCALE_SHIFT 14 + +struct lp5562_led_wrap_priv { + struct gpio_desc enable_gpio; +}; + +struct lp5562_led_priv { + u8 reg_pwm; + u8 reg_current; + u8 map_shift; + u8 enginenum; +}; + +/* enum values map to LED_MAP (0x70) values */ +enum lp5562_led_ctl_mode { + I2C = 0x0, +#ifdef CONFIG_LED_BLINK + ENGINE1 = 0x1, + ENGINE2 = 0x2, + ENGINE3 = 0x3 +#endif +}; + +/* + * Update a register value + * dev - I2C udevice (parent of led) + * regnum - register number to update + * value - value to write to register + * mask - mask of bits that should be changed + */ +static int lp5562_led_reg_update(struct udevice *dev, int regnum, + u8 value, u8 mask) +{ + int ret; + + if (mask == 0xFF) + ret = dm_i2c_reg_write(dev, regnum, value); + else + ret = dm_i2c_reg_clrset(dev, regnum, mask, value); + + + /* + * Data sheet says "Delay between consecutive I2C writes to + * ENABLE register (00h) need to be longer than 488 μs + * (typical)." and "Delay between consecutive I2C writes to + * OP_MODE register need to be longer than 153 μs (typ)." + * + * The linux driver does usleep_range(500, 600) and + * usleep_range(200, 300), respectively. + */ + switch (regnum) { + case REG_ENABLE: + udelay(600); + break; + case REG_OP_MODE: + udelay(300); + break; + } + + return ret; +} + +#ifdef CONFIG_LED_BLINK +/* + * Program the lp5562 engine + * dev - I2C udevice (parent of led) + * program - array of commands + * size - number of commands in program array (1-16) + * engine - engine number (1-3) + */ +static int lp5562_led_program_engine(struct udevice *dev, u16 *program, + u8 size, u8 engine) +{ + int ret, cmd; + u8 engine_reg = REG_ENG1_MEM_BEGIN + + ((engine - 1) * REG_ENGINE_MEM_SIZE); + u8 shift = (3 - engine) * 2; + __be16 prog_be[16]; + + if (size < 1 || size > 16 || engine < 1 || engine > 3) + return -EINVAL; + + for (cmd = 0; cmd < size; cmd++) + prog_be[cmd] = cpu_to_be16(program[cmd]); + + /* set engine mode to 'disabled' */ + ret = lp5562_led_reg_update(dev, REG_OP_MODE, + REG_OP_MODE_DISABLED << shift, + REG_OP_MODE_MASK << shift); + if (ret != 0) + goto done; + + /* set exec mode to 'hold' */ + ret = lp5562_led_reg_update(dev, REG_ENABLE, + REG_ENABLE_ENG_EXEC_HOLD << shift, + REG_ENABLE_ENG_EXEC_MASK << shift); + if (ret != 0) + goto done; + + /* set engine mode to 'load SRAM' */ + ret = lp5562_led_reg_update(dev, REG_OP_MODE, + REG_OP_MODE_LOAD_SRAM << shift, + REG_OP_MODE_MASK << shift); + if (ret != 0) + goto done; + + /* send the re-ordered program sequence */ + ret = dm_i2c_write(dev, engine_reg, (uchar *)prog_be, sizeof(u16) * size); + if (ret != 0) + goto done; + + /* set engine mode to 'run' */ + ret = lp5562_led_reg_update(dev, REG_OP_MODE, + REG_OP_MODE_RUN << shift, + REG_OP_MODE_MASK << shift); + if (ret != 0) + goto done; + + /* set engine exec to 'run' */ + ret = lp5562_led_reg_update(dev, REG_ENABLE, + REG_ENABLE_ENG_EXEC_RUN << shift, + REG_ENABLE_ENG_EXEC_MASK << shift); + +done: + return ret; +} + +/* + * Get the LED's current control mode (I2C or ENGINE[1-3]) + * dev - led udevice (child udevice) + */ +static enum lp5562_led_ctl_mode lp5562_led_get_control_mode(struct udevice *dev) +{ + struct lp5562_led_priv *priv = dev_get_priv(dev); + u8 data; + enum lp5562_led_ctl_mode mode = I2C; + + if (dm_i2c_read(dev_get_parent(dev), REG_LED_MAP, &data, 1) == 0) + mode = (data & (REG_LED_MAP_ENG_MASK << priv->map_shift)) + >> priv->map_shift; + + return mode; +} +#endif + +/* + * Set the LED's control mode to I2C or ENGINE[1-3] + * dev - led udevice (child udevice) + * mode - mode to change to + */ +static int lp5562_led_set_control_mode(struct udevice *dev, + enum lp5562_led_ctl_mode mode) +{ + struct lp5562_led_priv *priv = dev_get_priv(dev); + + return (lp5562_led_reg_update(dev_get_parent(dev), REG_LED_MAP, + mode << priv->map_shift, + REG_LED_MAP_ENG_MASK << priv->map_shift)); +} + +/* + * Return the LED's PWM value; If LED is in BLINK state, then it is + * under engine control mode which doesn't use this PWM value. + * dev - led udevice (child udevice) + */ +static int lp5562_led_get_pwm(struct udevice *dev) +{ + struct lp5562_led_priv *priv = dev_get_priv(dev); + u8 data; + + if (dm_i2c_read(dev_get_parent(dev), priv->reg_pwm, &data, 1) != 0) + return -EINVAL; + + return data; +} + +/* + * Set the LED's PWM value and configure it to use this (I2C mode). + * dev - led udevice (child udevice) + * value - PWM value (0 - 255) + */ +static int lp5562_led_set_pwm(struct udevice *dev, u8 value) +{ + struct lp5562_led_priv *priv = dev_get_priv(dev); + + if (lp5562_led_reg_update(dev_get_parent(dev), priv->reg_pwm, + value, 0xff) != 0) + return -EINVAL; + + /* set LED to I2C register mode */ + return lp5562_led_set_control_mode(dev, I2C); +} + +/* + * Return the led's current state + * dev - led udevice (child udevice) + * + */ +static enum led_state_t lp5562_led_get_state(struct udevice *dev) +{ + enum led_state_t state = LEDST_ON; + + if (lp5562_led_get_pwm(dev) == REG_PWM_MIN_VALUE) + state = LEDST_OFF; + +#ifdef CONFIG_LED_BLINK + if (lp5562_led_get_control_mode(dev) != I2C) + state = LEDST_BLINK; +#endif + + return state; +} + +/* + * Set the led state + * dev - led udevice (child udevice) + * state - State to set the LED to + */ +static int lp5562_led_set_state(struct udevice *dev, enum led_state_t state) +{ +#ifdef CONFIG_LED_BLINK + struct lp5562_led_priv *priv = dev_get_priv(dev); +#endif + + switch (state) { + case LEDST_OFF: + return lp5562_led_set_pwm(dev, REG_PWM_MIN_VALUE); + case LEDST_ON: + return lp5562_led_set_pwm(dev, REG_PWM_MAX_VALUE); +#ifdef CONFIG_LED_BLINK + case LEDST_BLINK: + return lp5562_led_set_control_mode(dev, priv->enginenum); +#endif + case LEDST_TOGGLE: + if (lp5562_led_get_state(dev) == LEDST_OFF) + return lp5562_led_set_state(dev, LEDST_ON); + else + return lp5562_led_set_state(dev, LEDST_OFF); + break; + default: + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_LED_BLINK +/* + * Set the blink period of an LED; note blue and white share the same + * engine so changing the period of one affects the other. + * dev - led udevice (child udevice) + * period_ms - blink period in ms + */ +static int lp5562_led_set_period(struct udevice *dev, int period_ms) +{ + struct lp5562_led_priv *priv = dev_get_priv(dev); + u8 opcode = 0; + u16 program[7]; + u16 wait_time; + + /* Blink is implemented as an engine program. Simple on/off + * for short periods, or fade in/fade out for longer periods: + * + * if (period_ms < 500): + * set PWM to 100% + * pause for period / 2 + * set PWM to 0% + * pause for period / 2 + * goto start + * + * else + * raise PWM 0% -> 50% in 62.7 ms + * raise PWM 50% -> 100% in 62.7 ms + * pause for (period - 4 * 62.7) / 2 + * lower PWM 100% -> 50% in 62.7 ms + * lower PWM 50% -> 0% in 62.7 ms + * pause for (period - 4 * 62.7) / 2 + * goto start + */ + + if (period_ms < MIN_BLINK_PERIOD) + period_ms = MIN_BLINK_PERIOD; + else if (period_ms > MAX_BLINK_PERIOD) + period_ms = MAX_BLINK_PERIOD; + + if (period_ms < 500) { + /* Simple on/off blink */ + wait_time = period_ms / 2; + + /* 1st command is full brightness */ + program[opcode++] = + (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + REG_PWM_MAX_VALUE; + + /* 2nd command is wait (period / 2) using 15.6ms steps */ + program[opcode++] = + (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) | + (0 << LED_PGRM_RAMP_INCREMENT_SHIFT); + + /* 3rd command is 0% brightness */ + program[opcode++] = + (1 << LED_PGRM_RAMP_PRESCALE_SHIFT); + + /* 4th command is wait (period / 2) using 15.6ms steps */ + program[opcode++] = + (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) | + (0 << LED_PGRM_RAMP_INCREMENT_SHIFT); + + /* 5th command: repeat */ + program[opcode++] = 0x00; + } else { + /* fade-in / fade-out blink */ + wait_time = ((period_ms - 251) / 2); + + /* ramp up time is 256 * 0.49ms (125.4ms) done in 2 steps */ + /* 1st command is ramp up 1/2 way */ + program[opcode++] = + (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + (1 << LED_PGRM_RAMP_STEP_SHIFT) | + (127 << LED_PGRM_RAMP_INCREMENT_SHIFT); + + /* 2nd command is ramp up rest of the way */ + program[opcode++] = + (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + (1 << LED_PGRM_RAMP_STEP_SHIFT) | + (127 << LED_PGRM_RAMP_INCREMENT_SHIFT); + + /* 3rd: wait ((period - 2 * ramp_time) / 2) (15.6ms steps) */ + program[opcode++] = + (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) | + (0 << LED_PGRM_RAMP_INCREMENT_SHIFT); + + /* ramp down is same as ramp up with sign bit set */ + /* 4th command is ramp down 1/2 way */ + program[opcode++] = + (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + (1 << LED_PGRM_RAMP_STEP_SHIFT) | + (1 << LED_PGRM_RAMP_SIGN_SHIFT) | + (127 << LED_PGRM_RAMP_INCREMENT_SHIFT); + + /* 5th command is ramp down rest of the way */ + program[opcode++] = + (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + (1 << LED_PGRM_RAMP_STEP_SHIFT) | + (1 << LED_PGRM_RAMP_SIGN_SHIFT) | + (127 << LED_PGRM_RAMP_INCREMENT_SHIFT); + + /* 6th: wait ((period - 2 * ramp_time) / 2) (15.6ms steps) */ + program[opcode++] = + (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) | + (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) | + (0 << LED_PGRM_RAMP_INCREMENT_SHIFT); + + /* 7th command: repeat */ + program[opcode++] = 0x00; + } + + return lp5562_led_program_engine(dev_get_parent(dev), program, + opcode, priv->enginenum); +} +#endif + +static const struct led_ops lp5562_led_ops = { + .get_state = lp5562_led_get_state, + .set_state = lp5562_led_set_state, +#ifdef CONFIG_LED_BLINK + .set_period = lp5562_led_set_period, +#endif +}; + +static int lp5562_led_probe(struct udevice *dev) +{ + struct lp5562_led_priv *priv = dev_get_priv(dev); + u8 current; + int ret = 0; + + /* Child LED nodes */ + switch (dev_read_addr(dev)) { + case 0: + priv->reg_current = REG_R_CUR; + priv->reg_pwm = REG_R_PWM; + priv->map_shift = REG_LED_MAP_R_ENG_SHIFT; + priv->enginenum = 1; + break; + case 1: + priv->reg_current = REG_G_CUR; + priv->reg_pwm = REG_G_PWM; + priv->map_shift = REG_LED_MAP_G_ENG_SHIFT; + priv->enginenum = 2; + break; + case 2: + priv->reg_current = REG_B_CUR; + priv->reg_pwm = REG_B_PWM; + priv->map_shift = REG_LED_MAP_B_ENG_SHIFT; + priv->enginenum = 3; /* shared with white */ + break; + case 3: + priv->reg_current = REG_W_CUR; + priv->map_shift = REG_LED_MAP_W_ENG_SHIFT; + priv->enginenum = 3; /* shared with blue */ + break; + default: + return -EINVAL; + } + + current = dev_read_u8_default(dev, "max-cur", DEFAULT_CURRENT); + + ret = lp5562_led_reg_update(dev_get_parent(dev), priv->reg_current, + current, 0xff); + + return ret; +} + +static int lp5562_led_bind(struct udevice *dev) +{ + struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + /* + * For the child nodes, parse a "chan-name" property, since + * the DT bindings for this device use that instead of + * "label". + */ + uc_plat->label = dev_read_string(dev, "chan-name"); + + return 0; +} + +U_BOOT_DRIVER(lp5562_led) = { + .name = "lp5562-led", + .id = UCLASS_LED, + .bind = lp5562_led_bind, + .probe = lp5562_led_probe, + .priv_auto = sizeof(struct lp5562_led_priv), + .ops = &lp5562_led_ops, +}; + + +static int lp5562_led_wrap_probe(struct udevice *dev) +{ + struct lp5562_led_wrap_priv *priv = dev_get_priv(dev); + u8 clock_mode; + int ret; + + /* Enable gpio if needed */ + if (gpio_request_by_name(dev, "enabled-gpios", 0, + &priv->enable_gpio, GPIOD_IS_OUT) == 0) { + dm_gpio_set_value(&priv->enable_gpio, 1); + udelay(1000); + } + + /* Ensure all registers have default values. */ + ret = lp5562_led_reg_update(dev, REG_RESET, REG_RESET_RESET, 0xff); + if (ret) + return ret; + udelay(10000); + + /* Enable the chip */ + ret = lp5562_led_reg_update(dev, REG_ENABLE, REG_ENABLE_CHIP_ENABLE, 0xff); + if (ret) + return ret; + + /* + * The DT bindings say 0=auto, 1=internal, 2=external, while + * the register[0:1] values are 0=external, 1=internal, + * 2=auto. + */ + clock_mode = dev_read_u8_default(dev, "clock-mode", 0); + ret = lp5562_led_reg_update(dev, REG_CONFIG, 2 - clock_mode, REG_CONFIG_CLK_MASK); + + return ret; +} + +static int lp5562_led_wrap_bind(struct udevice *dev) +{ + return led_bind_generic(dev, "lp5562-led"); +} + +static const struct udevice_id lp5562_led_ids[] = { + { .compatible = "ti,lp5562" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(lp5562_led_wrap) = { + .name = "lp5562-led-wrap", + .id = UCLASS_NOP, + .of_match = lp5562_led_ids, + .bind = lp5562_led_wrap_bind, + .probe = lp5562_led_wrap_probe, + .priv_auto = sizeof(struct lp5562_led_wrap_priv), +}; diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c index 7c8eae9337b..ae6de3087ab 100644 --- a/drivers/led/led_pwm.c +++ b/drivers/led/led_pwm.c @@ -9,7 +9,6 @@ #include <errno.h> #include <led.h> #include <malloc.h> -#include <dm/lists.h> #include <pwm.h> #define LEDS_PWM_DRIVER_NAME "led_pwm" @@ -136,18 +135,7 @@ static int led_pwm_of_to_plat(struct udevice *dev) static int led_pwm_bind(struct udevice *parent) { - struct udevice *dev; - ofnode node; - int ret; - - dev_for_each_subnode(node, parent) { - ret = device_bind_driver_to_node(parent, LEDS_PWM_DRIVER_NAME, - ofnode_get_name(node), - node, &dev); - if (ret) - return ret; - } - return 0; + return led_bind_generic(parent, LEDS_PWM_DRIVER_NAME); } static const struct led_ops led_pwm_ops = { diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c index 3e4ec47389f..eb86847bbe2 100644 --- a/drivers/mailbox/zynqmp-ipi.c +++ b/drivers/mailbox/zynqmp-ipi.c @@ -8,9 +8,13 @@ #include <common.h> #include <log.h> #include <asm/io.h> +#include <asm/system.h> #include <dm.h> #include <mailbox-uclass.h> #include <dm/device_compat.h> +#include <dm/lists.h> +#include <dm/of_access.h> +#include <linux/arm-smccc.h> #include <linux/ioport.h> #include <linux/io.h> #include <wait_bit.h> @@ -21,6 +25,43 @@ #define IPI_BIT_MASK_PMU0 0x10000 #define IPI_INT_REG_BASE_APU 0xFF300000 +/* IPI agent ID any */ +#define IPI_ID_ANY 0xFFUL + +/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */ +#define USE_SMC 0 + +/* Default IPI SMC function IDs */ +#define SMC_IPI_MAILBOX_OPEN 0x82001000U +#define SMC_IPI_MAILBOX_RELEASE 0x82001001U +#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U +#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U +#define SMC_IPI_MAILBOX_ACK 0x82001004U +#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U +#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U + +/* IPI SMC Macros */ + +/* + * Flag to indicate if notification interrupt + * to be disabled. + */ +#define IPI_SMC_ENQUIRY_DIRQ_MASK BIT(0) + +/* + * Flag to indicate if notification interrupt + * to be enabled. + */ +#define IPI_SMC_ACK_EIRQ_MASK BIT(0) + +/* IPI mailbox status */ +#define IPI_MB_STATUS_IDLE 0 +#define IPI_MB_STATUS_SEND_PENDING 1 +#define IPI_MB_STATUS_RECV_PENDING 2 + +#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */ +#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */ + struct ipi_int_regs { u32 trig; /* 0x0 */ u32 obs; /* 0x4 */ @@ -39,8 +80,24 @@ struct zynqmp_ipi { void __iomem *local_res_regs; void __iomem *remote_req_regs; void __iomem *remote_res_regs; + u32 remote_id; + u32 local_id; + bool el3_supported; }; +static int zynqmp_ipi_fw_call(struct zynqmp_ipi *ipi_mbox, + unsigned long a0, unsigned long a3) +{ + struct arm_smccc_res res = {0}; + unsigned long a1, a2; + + a1 = ipi_mbox->local_id; + a2 = ipi_mbox->remote_id; + arm_smccc_smc(a0, a1, a2, a3, 0, 0, 0, 0, &res); + + return (int)res.a0; +} + static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data) { const struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data; @@ -51,6 +108,21 @@ static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data) for (size_t i = 0; i < msg->len; i++) writel(msg->buf[i], &mbx[i]); + /* Use SMC calls for Exception Level less than 3 where TF-A is available */ + if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) { + ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_NOTIFY, 0); + + debug("%s, send %ld bytes\n", __func__, msg->len); + + return ret; + } + + /* Return if EL3 is not supported */ + if (!zynqmp->el3_supported) { + dev_err(chan->dev, "mailbox in EL3 only supported for zynqmp"); + return -EOPNOTSUPP; + } + /* Write trigger interrupt */ writel(IPI_BIT_MASK_PMU0, &ipi_int_apu->trig); @@ -67,29 +139,50 @@ static int zynqmp_ipi_recv(struct mbox_chan *chan, void *data) struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data; struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev); u32 *mbx = (u32 *)zynqmp->local_res_regs; + int ret = 0; /* * PMU Firmware does not trigger IPI interrupt for API call responses so - * there is no need to check ISR flags + * there is no need to check ISR flags for EL3. */ for (size_t i = 0; i < msg->len; i++) msg->buf[i] = readl(&mbx[i]); + /* Ack to remote if EL is not 3 */ + if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) { + ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_ACK, + IPI_SMC_ACK_EIRQ_MASK); + } + debug("%s, recv %ld bytes\n", __func__, msg->len); - return 0; + return ret; }; -static int zynqmp_ipi_probe(struct udevice *dev) +static int zynqmp_ipi_dest_probe(struct udevice *dev) { struct zynqmp_ipi *zynqmp = dev_get_priv(dev); struct resource res; ofnode node; + int ret; debug("%s(dev=%p)\n", __func__, dev); - /* Get subnode where the regs are defined */ - /* Note IPI mailbox node needs to be the first one in DT */ - node = ofnode_first_subnode(dev_ofnode(dev)); + node = dev_ofnode(dev); + + if (IS_ENABLED(CONFIG_SPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp")) + zynqmp->el3_supported = true; + + ret = dev_read_u32(dev->parent, "xlnx,ipi-id", &zynqmp->local_id); + if (ret) { + dev_err(dev, "can't get local ipi id\n"); + return ret; + } + + ret = ofnode_read_u32(node, "xlnx,ipi-id", &zynqmp->remote_id); + if (ret) { + dev_err(dev, "can't get remote ipi id\n"); + return ret; + } if (ofnode_read_resource_byname(node, "local_request_region", &res)) { dev_err(dev, "No reg property for local_request_region\n"); @@ -97,6 +190,8 @@ static int zynqmp_ipi_probe(struct udevice *dev) }; zynqmp->local_req_regs = devm_ioremap(dev, res.start, (res.start - res.end)); + if (!zynqmp->local_req_regs) + return -EINVAL; if (ofnode_read_resource_byname(node, "local_response_region", &res)) { dev_err(dev, "No reg property for local_response_region\n"); @@ -104,6 +199,8 @@ static int zynqmp_ipi_probe(struct udevice *dev) }; zynqmp->local_res_regs = devm_ioremap(dev, res.start, (res.start - res.end)); + if (!zynqmp->local_res_regs) + return -EINVAL; if (ofnode_read_resource_byname(node, "remote_request_region", &res)) { dev_err(dev, "No reg property for remote_request_region\n"); @@ -111,6 +208,8 @@ static int zynqmp_ipi_probe(struct udevice *dev) }; zynqmp->remote_req_regs = devm_ioremap(dev, res.start, (res.start - res.end)); + if (!zynqmp->remote_req_regs) + return -EINVAL; if (ofnode_read_resource_byname(node, "remote_response_region", &res)) { dev_err(dev, "No reg property for remote_response_region\n"); @@ -118,25 +217,59 @@ static int zynqmp_ipi_probe(struct udevice *dev) }; zynqmp->remote_res_regs = devm_ioremap(dev, res.start, (res.start - res.end)); + if (!zynqmp->remote_res_regs) + return -EINVAL; return 0; }; -static const struct udevice_id zynqmp_ipi_ids[] = { - { .compatible = "xlnx,zynqmp-ipi-mailbox" }, - { } +static int zynqmp_ipi_probe(struct udevice *dev) +{ + struct udevice *cdev; + ofnode cnode; + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + dev_for_each_subnode(cnode, dev) { + ret = device_bind_driver_to_node(dev, "zynqmp_ipi_dest", + ofnode_get_name(cnode), + cnode, &cdev); + if (ret) + return ret; + } + + return 0; }; -struct mbox_ops zynqmp_ipi_mbox_ops = { +struct mbox_ops zynqmp_ipi_dest_mbox_ops = { .send = zynqmp_ipi_send, .recv = zynqmp_ipi_recv, }; +static const struct udevice_id zynqmp_ipi_dest_ids[] = { + { .compatible = "xlnx,zynqmp-ipi-dest-mailbox" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_ipi_dest) = { + .name = "zynqmp_ipi_dest", + .id = UCLASS_MAILBOX, + .of_match = zynqmp_ipi_dest_ids, + .probe = zynqmp_ipi_dest_probe, + .priv_auto = sizeof(struct zynqmp_ipi), + .ops = &zynqmp_ipi_dest_mbox_ops, +}; + +static const struct udevice_id zynqmp_ipi_ids[] = { + { .compatible = "xlnx,zynqmp-ipi-mailbox" }, + { } +}; + U_BOOT_DRIVER(zynqmp_ipi) = { .name = "zynqmp_ipi", - .id = UCLASS_MAILBOX, + .id = UCLASS_NOP, .of_match = zynqmp_ipi_ids, .probe = zynqmp_ipi_probe, - .priv_auto = sizeof(struct zynqmp_ipi), - .ops = &zynqmp_ipi_mbox_ops, + .flags = DM_FLAG_PROBE_AFTER_BIND, }; diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index 212bb4f5dc0..a722a3836f7 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -14,6 +14,7 @@ #include <linux/err.h> #include <linux/iopoll.h> #include <linux/ioport.h> +#include <linux/time.h> /* FMC2 Controller Registers */ #define FMC2_BCR1 0x0 @@ -90,8 +91,6 @@ #define FMC2_BTR_DATLAT_MAX 0xf #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff -#define FMC2_NSEC_PER_SEC 1000000000L - enum stm32_fmc2_ebi_bank { FMC2_EBI1 = 0, FMC2_EBI2, @@ -279,7 +278,7 @@ static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi, int cs, u32 setup) { unsigned long hclk = clk_get_rate(&ebi->clk); - unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000); + unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); return DIV_ROUND_UP(setup * 1000, hclkp); } diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index c4bc88c1510..41325eb0f94 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <asm/arch/hardware.h> #include <asm/ti-common/ti-aemif.h> #define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 97057de8bf9..ed7ecedd3ac 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -615,7 +615,7 @@ config FS_LOADER ie. the FPGA device. config SPL_FS_LOADER - bool "Enable loader driver for file system" + bool "Enable loader driver for file system in SPL" depends on SPL help This is file system generic loader which can be used to load diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c index 65c9c2c6ce3..feb02f97065 100644 --- a/drivers/misc/gsc.c +++ b/drivers/misc/gsc.c @@ -531,10 +531,10 @@ static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[] if (!gsc_wd_disable(dev)) return CMD_RET_SUCCESS; } else if (strcasecmp(argv[1], "thermal") == 0) { - char *cmd, *val; + const char *cmd, *val; - cmd = (argc > 2) ? argv[2] : NULL; - val = (argc > 3) ? argv[3] : NULL; + cmd = cmd_arg2(argc, argv); + val = cmd_arg3(argc, argv); if (!gsc_thermal(dev, cmd, val)) return CMD_RET_SUCCESS; } diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 7c01bf23d53..e3b6b4cd741 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_QFW #include <common.h> +#include <acpi/acpi_table.h> #include <bootdev.h> #include <bootflow.h> #include <bootmeth.h> diff --git a/drivers/mmc/octeontx_hsmmc.h b/drivers/mmc/octeontx_hsmmc.h index 70844b1cbab..9849121f174 100644 --- a/drivers/mmc/octeontx_hsmmc.h +++ b/drivers/mmc/octeontx_hsmmc.h @@ -32,8 +32,6 @@ */ #define MMC_TIMEOUT_SHORT 20 -#define NSEC_PER_SEC 1000000000L - #define MAX_NO_OF_TAPS 64 #define EXT_CSD_POWER_CLASS 187 /* R/W */ diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index c638980ea2b..c2fc80b10f0 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -31,7 +31,7 @@ obj-$(CONFIG_NVMXIP) += nvmxip/ else ifneq ($(mtd-y),) -obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd.o +obj-$(CONFIG_SPL_MTD) += mtd.o endif obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += nand/ obj-$(CONFIG_SPL_ONENAND_SUPPORT) += onenand/ diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index a13e6f59cbd..bb9994b8626 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -447,6 +447,22 @@ config NAND_PXA3XX This enables the driver for the NAND flash device found on PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). +config NAND_SANDBOX + bool "Support for NAND in sandbox" + depends on SANDBOX + select SYS_NAND_SELF_INIT + select SPL_SYS_NAND_SELF_INIT + select SPL_NAND_INIT + select SYS_NAND_SOFT_ECC + select BCH + select NAND_ECC_BCH + imply CMD_NAND + help + Enable a dummy NAND driver for sandbox. It simulates any number of + arbitrary NAND chips with a RAM buffer. It will also inject errors to + test ECC. At the moment, only 8-bit busses and single-chip devices are + supported. + config NAND_SUNXI bool "Support for NAND on Allwinner SoCs" default ARCH_SUNXI @@ -659,20 +675,13 @@ config SYS_NAND_ONFI_DETECTION And fetching device parameters flashed on device, by parsing ONFI parameter page. -config SYS_NAND_PAGE_COUNT - hex "NAND chip page count" - depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \ - SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \ - NAND_OMAP_GPMC) - help - Number of pages in the NAND chip. - config SYS_NAND_PAGE_SIZE hex "NAND chip page size" depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ MVEBU_SPL_BOOT_DEVICE_NAND || \ - (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER + (NAND_ATMEL && SPL_NAND_SUPPORT) || \ + SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621 help Number of data bytes in one page for the NAND chip on the diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index add2b4cf655..ddbba899e58 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o +obj-$(CONFIG_NAND_SANDBOX) += sand_nand.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o obj-$(CONFIG_NAND_MXIC) += mxic_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index 6ab3f1f42c5..6831af98b73 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -11,6 +11,7 @@ #include <common.h> #include <nand.h> +#include <system-constants.h> #include <asm/io.h> #include <linux/delay.h> #include <linux/mtd/nand_ecc.h> @@ -32,7 +33,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + int page_addr = page + block * SYS_NAND_BLOCK_PAGES; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; @@ -217,6 +218,11 @@ void nand_init(void) nand_command(0, 0, 0, NAND_CMD_RESET); } +unsigned int nand_page_size(void) +{ + return nand_to_mtd(&nand_chip)->writesize; +} + /* Unselect after operation */ void nand_deselect(void) { diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index fa962ba591c..a2151f98491 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -64,6 +64,7 @@ #include <linux/mfd/syscon/atmel-smc.h> #include <linux/mtd/rawnand.h> #include <linux/mtd/mtd.h> +#include <linux/time.h> #include <mach/at91_sfr.h> #include <nand.h> #include <regmap.h> @@ -71,8 +72,6 @@ #include "pmecc.h" -#define NSEC_PER_SEC 1000000000L - #define ATMEL_HSMC_NFC_CFG 0x0 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24) #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24) @@ -352,40 +351,6 @@ static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll, return ret; } -static void iowrite8_rep(void *addr, const uint8_t *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - writeb(buf[i], addr); -} - -static void ioread8_rep(void *addr, uint8_t *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - buf[i] = readb(addr); -} - -static void ioread16_rep(void *addr, void *buf, int len) -{ - int i; - u16 *p = (u16 *)buf; - - for (i = 0; i < len; i++) - p[i] = readw(addr); -} - -static void iowrite16_rep(void *addr, const void *buf, int len) -{ - int i; - u16 *p = (u16 *)buf; - - for (i = 0; i < len; i++) - writew(p[i], addr); -} - static u8 atmel_nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd_to_nand(mtd); diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 6b17e744a69..6d94e7af38e 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -12,6 +12,7 @@ #include <common.h> #include <log.h> +#include <system-constants.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> #include <dm/device_compat.h> @@ -1258,7 +1259,7 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + int page_addr = page + block * SYS_NAND_BLOCK_PAGES; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; @@ -1359,7 +1360,7 @@ int spl_nand_erase_one(int block, int page) if (nand_chip.select_chip) nand_chip.select_chip(mtd, 0); - page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + page_addr = page + block * SYS_NAND_BLOCK_PAGES; hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Row address */ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE); @@ -1451,6 +1452,11 @@ void nand_init(void) nand_chip.select_chip(mtd, 0); } +unsigned int nand_page_size(void) +{ + return nand_to_mtd(&nand_chip)->writesize; +} + void nand_deselect(void) { if (nand_chip.select_chip) diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index 690279c9976..165a23312cb 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -234,4 +234,9 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) return 0; } +unsigned int nand_page_size(void) +{ + return page_size; +} + void nand_deselect(void) {} diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index c67065eaf8c..69d26f1f79a 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -106,6 +106,8 @@ static inline int bad_block(uchar *marker, int port_size) return __raw_readw((u16 *)marker) != 0xffff; } +static int saved_page_size; + int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) { struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR; @@ -150,6 +152,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) if (port_size == 8) bad_marker = 5; } + saved_page_size = page_size; ver = ifc_in32(&gregs->ifc_rev); if (ver >= FSL_IFC_V2_0_0) @@ -302,6 +305,11 @@ void nand_init(void) { } +unsigned int nand_page_size(void) +{ + return saved_page_size; +} + void nand_deselect(void) { } diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index ac2e669d46b..f8ae216d56c 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -765,4 +765,9 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) return 0; } +unsigned int nand_page_size(void) +{ + return BYTES_PER_PAGE; +} + #endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/mtd/nand/raw/mt7621_nand_spl.c b/drivers/mtd/nand/raw/mt7621_nand_spl.c index 114fc8b7cea..a2be9ba80e0 100644 --- a/drivers/mtd/nand/raw/mt7621_nand_spl.c +++ b/drivers/mtd/nand/raw/mt7621_nand_spl.c @@ -203,6 +203,11 @@ unsigned long nand_size(void) return SZ_2G; } +unsigned int nand_page_size(void) +{ + return nfc_dev.nand.mtd.writesize; +} + void nand_deselect(void) { } diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c index 309e75d01e5..a855c9987f8 100644 --- a/drivers/mtd/nand/raw/mxc_nand_spl.c +++ b/drivers/mtd/nand/raw/mxc_nand_spl.c @@ -13,6 +13,7 @@ #include <common.h> #include <hang.h> #include <nand.h> +#include <system-constants.h> #include <linux/mtd/rawnand.h> #include <asm/arch/imx-regs.h> #include <asm/io.h> @@ -304,13 +305,13 @@ int nand_spl_load_image(uint32_t from, unsigned int size, void *buf) * Check if we have crossed a block boundary, and if so * check for bad block. */ - if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) { + if (!(page % SYS_NAND_BLOCK_PAGES)) { /* * Yes, new block. See if this block is good. If not, * loop until we find a good block. */ while (is_badblock(page)) { - page = page + CONFIG_SYS_NAND_PAGE_COUNT; + page = page + SYS_NAND_BLOCK_PAGES; /* Check i we've reached the end of flash. */ if (page >= maxpages) return -1; @@ -350,3 +351,8 @@ __used void nand_boot(void) void nand_init(void) {} void nand_deselect(void) {} + +unsigned int nand_page_size(void) +{ + return CONFIG_SYS_NAND_PAGE_SIZE; +} diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 65eab4c8088..fd65772af80 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -31,6 +31,7 @@ #include <linux/errno.h> #include <linux/mtd/rawnand.h> #include <linux/sizes.h> +#include <linux/time.h> #include <linux/types.h> #include <linux/math64.h> @@ -52,8 +53,6 @@ #endif #define MXS_NAND_BCH_TIMEOUT 10000 -#define USEC_PER_SEC 1000000 -#define NSEC_PER_SEC 1000000000L #define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 300662994cf..f7d3f02f85a 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -295,6 +295,11 @@ int nand_default_bbt(struct mtd_info *mtd) return 0; } +unsigned int nand_page_size(void) +{ + return nand_to_mtd(&nand_chip)->writesize; +} + void nand_deselect(void) { } diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index eacd99c4e27..4c18861aa25 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -60,13 +60,11 @@ int nand_register(int devnum, struct mtd_info *mtd) sprintf(dev_name[devnum], "nand%d", devnum); mtd->name = dev_name[devnum]; -#ifdef CONFIG_MTD /* * Add MTD device so that we can reference it later * via the mtdcore infrastructure (e.g. ubi). */ add_mtd_device(mtd); -#endif total_nand_size += mtd->size / 1024; @@ -76,6 +74,23 @@ int nand_register(int devnum, struct mtd_info *mtd) return 0; } +void nand_unregister(struct mtd_info *mtd) +{ + int devnum = nand_mtd_to_devnum(mtd); + + if (devnum < 0) + return; + + if (nand_curr_device == devnum) + nand_curr_device = -1; + + total_nand_size -= mtd->size / 1024; + + del_mtd_device(nand_info[devnum]); + + nand_info[devnum] = NULL; +} + #if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) static void nand_init_chip(int i) { @@ -100,6 +115,8 @@ static void nand_init_chip(int i) #endif #ifdef CONFIG_MTD_CONCAT +struct mtd_info *concat_mtd; + static void create_mtd_concat(void) { struct mtd_info *nand_info_list[CONFIG_SYS_MAX_NAND_DEVICE]; @@ -114,28 +131,40 @@ static void create_mtd_concat(void) } } if (nand_devices_found > 1) { - struct mtd_info *mtd; char c_mtd_name[16]; /* * We detected multiple devices. Concatenate them together. */ sprintf(c_mtd_name, "nand%d", nand_devices_found); - mtd = mtd_concat_create(nand_info_list, nand_devices_found, - c_mtd_name); + concat_mtd = mtd_concat_create(nand_info_list, + nand_devices_found, c_mtd_name); - if (mtd == NULL) + if (!concat_mtd) return; - nand_register(nand_devices_found, mtd); + nand_register(nand_devices_found, concat_mtd); } return; } + +static void destroy_mtd_concat(void) +{ + if (!concat_mtd) + return; + + mtd_concat_destroy(concat_mtd); + concat_mtd = NULL; +} #else static void create_mtd_concat(void) { } + +static void destroy_mtd_concat(void) +{ +} #endif unsigned long nand_size(void) @@ -143,10 +172,10 @@ unsigned long nand_size(void) return total_nand_size; } +static int initialized; + void nand_init(void) { - static int initialized; - /* * Avoid initializing NAND Flash multiple times, * otherwise it will calculate a wrong total size. @@ -174,3 +203,22 @@ void nand_init(void) create_mtd_concat(); } + +void nand_reinit(void) +{ + int i; + + destroy_mtd_concat(); + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + assert(!nand_info[i]); + + initialized = 0; + nand_init(); +} + +unsigned int nand_page_size(void) +{ + struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device); + + return mtd ? mtd->writesize : 1; +} diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6b4adcf6bdc..c40a0f23d7b 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -245,39 +245,6 @@ static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) chip->write_buf(mtd, (uint8_t *)&word, 2); } -static void iowrite8_rep(void *addr, const uint8_t *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - writeb(buf[i], addr); -} -static void ioread8_rep(void *addr, uint8_t *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - buf[i] = readb(addr); -} - -static void ioread16_rep(void *addr, void *buf, int len) -{ - int i; - u16 *p = (u16 *) buf; - - for (i = 0; i < len; i++) - p[i] = readw(addr); -} - -static void iowrite16_rep(void *addr, void *buf, int len) -{ - int i; - u16 *p = (u16 *) buf; - - for (i = 0; i < len; i++) - writew(p[i], addr); -} - /** * nand_write_buf - [DEFAULT] write buffer to chip * @mtd: MTD device structure @@ -4462,17 +4429,14 @@ ident_done: else if (chip->jedec_version) pr_info("%s %s\n", manufacturer_desc->name, chip->jedec_params.model); - else + else if (manufacturer_desc) pr_info("%s %s\n", manufacturer_desc->name, type->name); #else if (chip->jedec_version) pr_info("%s %s\n", manufacturer_desc->name, chip->jedec_params.model); - else + else if (manufacturer_desc) pr_info("%s %s\n", manufacturer_desc->name, type->name); - - pr_info("%s %s\n", manufacturer_desc->name, - type->name); #endif pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c index 156b44d8358..db4213ea3dc 100644 --- a/drivers/mtd/nand/raw/nand_spl_loaders.c +++ b/drivers/mtd/nand/raw/nand_spl_loaders.c @@ -12,8 +12,11 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) while (block <= lastblock) { if (!nand_is_bad_block(block)) { /* Skip bad blocks */ - while (page < CONFIG_SYS_NAND_PAGE_COUNT) { + while (size && page < SYS_NAND_BLOCK_PAGES) { nand_read_page(block, page, dst); + + size -= min(size, CONFIG_SYS_NAND_PAGE_SIZE - + page_offset); /* * When offs is not aligned to page address the * extra offset is copied to dst as well. Copy diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c index 2f3af9edd4c..80d6e0e1e4e 100644 --- a/drivers/mtd/nand/raw/nand_spl_simple.c +++ b/drivers/mtd/nand/raw/nand_spl_simple.c @@ -6,6 +6,7 @@ #include <common.h> #include <nand.h> +#include <system-constants.h> #include <asm/io.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/rawnand.h> @@ -27,7 +28,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + int page_addr = page + block * SYS_NAND_BLOCK_PAGES; while (!this->dev_ready(mtd)) ; @@ -59,7 +60,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + int page_addr = page + block * SYS_NAND_BLOCK_PAGES; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; @@ -226,6 +227,11 @@ void nand_init(void) nand_chip.select_chip(mtd, 0); } +unsigned int nand_page_size(void) +{ + return nand_to_mtd(&nand_chip)->writesize; +} + /* Unselect after operation */ void nand_deselect(void) { diff --git a/drivers/mtd/nand/raw/octeontx_nand.c b/drivers/mtd/nand/raw/octeontx_nand.c index 65a03d22c1d..3b20685fac0 100644 --- a/drivers/mtd/nand/raw/octeontx_nand.c +++ b/drivers/mtd/nand/raw/octeontx_nand.c @@ -24,6 +24,7 @@ #include <linux/mtd/nand_bch.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/rawnand.h> +#include <linux/time.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/types.h> @@ -291,7 +292,6 @@ union ndf_cmd { #define OCTEONTX_NAND_DRIVER_NAME "octeontx_nand" #define NDF_TIMEOUT 1000 /** Timeout in ms */ -#define USEC_PER_SEC 1000000 /** Linux compatibility */ #ifndef NAND_MAX_CHIPS # define NAND_MAX_CHIPS 8 /** Linux compatibility */ #endif diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 1a5ed0de31a..0e25bd5dc28 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -6,6 +6,7 @@ #include <common.h> #include <log.h> +#include <system-constants.h> #include <asm/io.h> #include <dm/uclass.h> #include <linux/errno.h> @@ -1298,7 +1299,7 @@ static int nand_is_bad_block(int block) static int nand_read_page(int block, int page, uchar *dst) { - int page_addr = block * CONFIG_SYS_NAND_PAGE_COUNT + page; + int page_addr = block * SYS_NAND_BLOCK_PAGES + page; loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE; int ret; size_t len = CONFIG_SYS_NAND_PAGE_SIZE; diff --git a/drivers/mtd/nand/raw/sand_nand.c b/drivers/mtd/nand/raw/sand_nand.c new file mode 100644 index 00000000000..229d7b5b65a --- /dev/null +++ b/drivers/mtd/nand/raw/sand_nand.c @@ -0,0 +1,707 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) Sean Anderson <seanga2@gmail.com> + */ + +#define LOG_CATEGORY UCLASS_MTD +#include <errno.h> +#include <hexdump.h> +#include <log.h> +#include <nand.h> +#include <os.h> +#include <rand.h> +#include <spl.h> +#include <system-constants.h> +#include <dm/device_compat.h> +#include <dm/read.h> +#include <dm/uclass.h> +#include <asm/bitops.h> +#include <linux/bitmap.h> +#include <linux/mtd/rawnand.h> +#include <linux/sizes.h> + +enum sand_nand_state { + STATE_READY, + STATE_IDLE, + STATE_READ, + STATE_READ_ID, + STATE_READ_ONFI, + STATE_PARAM_ONFI, + STATE_STATUS, + STATE_PROG, + STATE_ERASE, +}; + +static const char *const state_name[] = { + [STATE_READY] = "READY", + [STATE_IDLE] = "IDLE", + [STATE_READ] = "READ", + [STATE_READ_ID] = "READ_ID", + [STATE_READ_ONFI] = "READ_ONFI", + [STATE_PARAM_ONFI] = "PARAM_ONFI", + [STATE_STATUS] = "STATUS", + [STATE_PROG] = "PROG", + [STATE_ERASE] = "ERASE", +}; + +/** + * struct sand_nand_chip - Per-device private data + * @nand: The nand chip + * @node: The next device in this controller + * @programmed: Bitmap of whether sectors are programmed + * @id: ID to report for NAND_CMD_READID + * @id_len: Length of @id + * @onfi: Three copies of ONFI parameter page + * @status: Status to report for NAND_CMD_STATUS + * @chunksize: Size of one "chunk" (page + oob) in bytes + * @pageize: Size of one page in bytes + * @pages: Total number of pages + * @pages_per_erase: Number of pages per eraseblock + * @err_count: Number of errors to inject per @err_step_bits of data + * @err_step_bits: Number of data bits per error "step" + * @err_steps: Number of err steps in a page + * @cs: Chip select for this device + * @state: Current state of the device + * @column: Column of the most-recent command + * @page_addr: Page address of the most-recent command + * @fd: File descriptor for the backing data + * @fd_page_addr: Page address that @fd is seek'd to + * @selected: Whether this device is selected + * @tmp: "Cache" buffer used to store transferred data before committing it + * @tmp_dirty: Whether @tmp is dirty (modified) or clean (all ones) + * + * Data is stored with the OOB area in-line. For example, with 512-byte pages + * and and 16-byte OOB areas, the first page would start at offset 0, the second + * at offset 528, the third at offset 1056, and so on + */ +struct sand_nand_chip { + struct nand_chip nand; + struct list_head node; + long *programmed; + const u8 *id; + u32 chunksize, pagesize, pages, pages_per_erase; + u32 err_count, err_step_bits, err_steps, ecc_bits; + unsigned int cs; + enum sand_nand_state state; + int column, page_addr, fd, fd_page_addr; + bool selected, tmp_dirty; + u8 status; + u8 id_len; + u8 tmp[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; + u8 onfi[sizeof(struct nand_onfi_params) * 3]; +}; + +#define SAND_DEBUG(chip, fmt, ...) \ + dev_dbg((chip)->nand.mtd.dev, "%u (%s): " fmt, (chip)->cs, \ + state_name[(chip)->state], ##__VA_ARGS__) + +static inline void to_state(struct sand_nand_chip *chip, + enum sand_nand_state new_state) +{ + if (new_state != chip->state) + SAND_DEBUG(chip, "to state %s\n", state_name[new_state]); + chip->state = new_state; +} + +static inline struct sand_nand_chip *to_sand_nand(struct nand_chip *nand) +{ + return container_of(nand, struct sand_nand_chip, nand); +} + +struct sand_nand_priv { + struct list_head chips; +}; + +static int sand_nand_dev_ready(struct mtd_info *mtd) +{ + return 1; +} + +static int sand_nand_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + u8 status; + + return nand_status_op(chip, &status) ?: status; +} + +static int sand_nand_seek(struct sand_nand_chip *chip) +{ + if (chip->fd_page_addr == chip->page_addr) + return 0; + + if (os_lseek(chip->fd, (off_t)chip->page_addr * chip->chunksize, + OS_SEEK_SET) < 0) { + SAND_DEBUG(chip, "could not seek: %d\n", errno); + return -EIO; + } + + chip->fd_page_addr = chip->page_addr; + return 0; +} + +static void sand_nand_inject_error(struct sand_nand_chip *chip, + unsigned int step, unsigned int pos) +{ + int byte, index; + + if (pos < chip->err_step_bits) { + __change_bit(step * chip->err_step_bits + pos, chip->tmp); + return; + } + + /* + * Only ECC bytes are covered in the OOB area, so + * pretend that those are the only bytes which can have + * errors. + */ + byte = (pos - chip->err_step_bits + step * chip->ecc_bits) / 8; + index = chip->nand.ecc.layout->eccpos[byte]; + /* Avoid endianness issues by working with bytes */ + chip->tmp[chip->pagesize + index] ^= BIT(pos & 0x7); +} + +static int sand_nand_read(struct sand_nand_chip *chip) +{ + unsigned int i, stop = 0; + + if (chip->column == chip->pagesize) + stop = chip->err_step_bits; + + if (test_bit(chip->page_addr, chip->programmed)) { + if (sand_nand_seek(chip)) + return -EIO; + + if (os_read(chip->fd, chip->tmp, chip->chunksize) != + chip->chunksize) { + SAND_DEBUG(chip, "could not read: %d\n", errno); + return -EIO; + } + chip->fd_page_addr++; + } else if (chip->tmp_dirty) { + memset(chip->tmp + chip->column, 0xff, + chip->chunksize - chip->column); + } + + /* + * Inject some errors; this is Method A from "An Efficient Algorithm for + * Sequential Random Sampling" (Vitter 87). This is still slow when + * generating a lot (dozens) of ECC errors. + * + * To avoid generating too many errors in any one ECC step, we separate + * our error generation by ECC step. + */ + chip->tmp_dirty = true; + for (i = 0; i < chip->err_steps; i++) { + u32 bit_errors = chip->err_count; + unsigned int j = chip->err_step_bits + chip->ecc_bits; + + while (bit_errors) { + unsigned int u = rand(); + float quot = 1ULL << 32; + + do { + quot *= j - bit_errors; + quot /= j; + j--; + + if (j < stop) + goto next; + } while (u < quot); + + sand_nand_inject_error(chip, i, j); + bit_errors--; + } +next: + ; + } + + return 0; +} + +static void sand_nand_command(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sand_nand_chip *chip = to_sand_nand(nand); + enum sand_nand_state new_state = chip->state; + + SAND_DEBUG(chip, "command=%02x column=%d page_addr=%d\n", command, + column, page_addr); + + if (!chip->selected) + return; + + switch (chip->state) { + case STATE_READY: + if (command == NAND_CMD_RESET) + goto reset; + break; + case STATE_PROG: + new_state = STATE_IDLE; + if (command != NAND_CMD_PAGEPROG || + test_and_set_bit(chip->page_addr, chip->programmed)) { + chip->status |= NAND_STATUS_FAIL; + break; + } + + if (sand_nand_seek(chip)) { + chip->status |= NAND_STATUS_FAIL; + break; + } + + if (os_write(chip->fd, chip->tmp, chip->chunksize) != + chip->chunksize) { + SAND_DEBUG(chip, "could not write: %d\n", errno); + chip->status |= NAND_STATUS_FAIL; + break; + } + + chip->fd_page_addr++; + break; + case STATE_ERASE: + new_state = STATE_IDLE; + if (command != NAND_CMD_ERASE2) { + chip->status |= NAND_STATUS_FAIL; + break; + } + + if (chip->page_addr < 0 || + chip->page_addr >= chip->pages || + chip->page_addr % chip->pages_per_erase) + chip->status |= NAND_STATUS_FAIL; + else + bitmap_clear(chip->programmed, chip->page_addr, + chip->pages_per_erase); + break; + default: + chip->column = column; + chip->page_addr = page_addr; + switch (command) { + case NAND_CMD_READOOB: + if (column >= 0) + chip->column += chip->pagesize; + fallthrough; + case NAND_CMD_READ0: + new_state = STATE_IDLE; + if (page_addr < 0 || page_addr >= chip->pages) + break; + + if (chip->column < 0 || chip->column >= chip->chunksize) + break; + + if (sand_nand_read(chip)) + break; + + chip->page_addr = page_addr; + new_state = STATE_READ; + break; + case NAND_CMD_ERASE1: + new_state = STATE_ERASE; + chip->status = ~NAND_STATUS_FAIL; + break; + case NAND_CMD_STATUS: + new_state = STATE_STATUS; + chip->column = 0; + break; + case NAND_CMD_SEQIN: + new_state = STATE_PROG; + chip->status = ~NAND_STATUS_FAIL; + if (page_addr < 0 || page_addr >= chip->pages || + chip->column < 0 || + chip->column >= chip->chunksize) { + chip->status |= NAND_STATUS_FAIL; + } else if (chip->tmp_dirty) { + memset(chip->tmp, 0xff, chip->chunksize); + chip->tmp_dirty = false; + } + break; + case NAND_CMD_READID: + if (chip->onfi[0] && column == 0x20) + new_state = STATE_READ_ONFI; + else + new_state = STATE_READ_ID; + chip->column = 0; + break; + case NAND_CMD_PARAM: + if (chip->onfi[0] && !column) + new_state = STATE_PARAM_ONFI; + else + new_state = STATE_IDLE; + break; + case NAND_CMD_RESET: +reset: + new_state = STATE_IDLE; + chip->column = -1; + chip->page_addr = -1; + chip->status = ~NAND_STATUS_FAIL; + break; + default: + new_state = STATE_IDLE; + SAND_DEBUG(chip, "Unsupported command %02x\n", command); + } + } + + to_state(chip, new_state); +} + +static void sand_nand_select_chip(struct mtd_info *mtd, int n) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sand_nand_chip *chip = to_sand_nand(nand); + + chip->selected = !n; +} + +static void sand_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sand_nand_chip *chip = to_sand_nand(nand); + unsigned int to_copy; + int src_len = 0; + const u8 *src = NULL; + + if (!chip->selected) + goto copy; + + switch (chip->state) { + case STATE_READ: + src = chip->tmp; + src_len = chip->chunksize; + break; + case STATE_READ_ID: + src = chip->id; + src_len = chip->id_len; + break; + case STATE_READ_ONFI: + src = "ONFI"; + src_len = 4; + break; + case STATE_PARAM_ONFI: + src = chip->onfi; + src_len = sizeof(chip->onfi); + break; + case STATE_STATUS: + src = &chip->status; + src_len = 1; + break; + default: + break; + } + +copy: + if (chip->column >= 0) + to_copy = max(min(len, src_len - chip->column), 0); + else + to_copy = 0; + memcpy(buf, src + chip->column, to_copy); + memset(buf + to_copy, 0xff, len - to_copy); + chip->column += to_copy; + + if (len == 1) { + SAND_DEBUG(chip, "read [ %02x ]\n", buf[0]); + } else if (src_len) { + SAND_DEBUG(chip, "read %d bytes\n", len); +#ifdef VERBOSE_DEBUG + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); +#endif + } + + if (src_len && chip->column == src_len) + to_state(chip, STATE_IDLE); +} + +static u8 sand_nand_read_byte(struct mtd_info *mtd) +{ + u8 ret; + + sand_nand_read_buf(mtd, &ret, 1); + return ret; +} + +static u16 sand_nand_read_word(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sand_nand_chip *chip = to_sand_nand(nand); + + SAND_DEBUG(chip, "16-bit access unsupported\n"); + return sand_nand_read_byte(mtd) | 0xff00; +} + +static void sand_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sand_nand_chip *chip = to_sand_nand(nand); + + SAND_DEBUG(chip, "write %d bytes\n", len); +#ifdef VERBOSE_DEBUG + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); +#endif + + if (chip->state != STATE_PROG || chip->status & NAND_STATUS_FAIL) + return; + + chip->tmp_dirty = true; + len = min((unsigned int)len, chip->chunksize - chip->column); + memcpy(chip->tmp + chip->column, buf, len); + chip->column += len; +} + +static struct nand_chip *nand_chip; + +int sand_nand_remove(struct udevice *dev) +{ + struct sand_nand_priv *priv = dev_get_priv(dev); + struct sand_nand_chip *chip; + + list_for_each_entry(chip, &priv->chips, node) { + struct nand_chip *nand = &chip->nand; + + if (nand_chip == nand) + nand_chip = NULL; + + nand_unregister(nand_to_mtd(nand)); + free(chip->programmed); + os_close(chip->fd); + free(chip); + } + + return 0; +} + +static int sand_nand_probe(struct udevice *dev) +{ + struct sand_nand_priv *priv = dev_get_priv(dev); + struct sand_nand_chip *chip; + int ret, devnum = 0; + ofnode np; + + INIT_LIST_HEAD(&priv->chips); + + dev_for_each_subnode(np, dev) { + struct nand_chip *nand; + struct mtd_info *mtd; + u32 erasesize, oobsize, pagesize, pages; + u32 err_count, err_step_size; + off_t expected_size; + char filename[30]; + fdt_addr_t cs; + const u8 *id, *onfi; + int id_len, onfi_len; + + cs = ofnode_get_addr_size_index_notrans(np, 0, NULL); + if (cs == FDT_ADDR_T_NONE) { + dev_dbg(dev, "Invalid cs for chip %s\n", + ofnode_get_name(np)); + ret = -ENOENT; + goto err; + } + + id = ofnode_read_prop(np, "sandbox,id", &id_len); + if (!id) { + dev_dbg(dev, "No sandbox,id property for chip %s\n", + ofnode_get_name(np)); + ret = -EINVAL; + goto err; + } + + onfi = ofnode_read_prop(np, "sandbox,onfi", &onfi_len); + if (onfi && onfi_len != sizeof(struct nand_onfi_params)) { + dev_dbg(dev, "Invalid length %d for onfi params\n", + onfi_len); + ret = -EINVAL; + goto err; + } + + ret = ofnode_read_u32(np, "sandbox,erasesize", &erasesize); + if (ret) { + dev_dbg(dev, "No sandbox,erasesize property for chip %s", + ofnode_get_name(np)); + goto err; + } + + ret = ofnode_read_u32(np, "sandbox,oobsize", &oobsize); + if (ret) { + dev_dbg(dev, "No sandbox,oobsize property for chip %s", + ofnode_get_name(np)); + goto err; + } + + ret = ofnode_read_u32(np, "sandbox,pagesize", &pagesize); + if (ret) { + dev_dbg(dev, "No sandbox,pagesize property for chip %s", + ofnode_get_name(np)); + goto err; + } + + ret = ofnode_read_u32(np, "sandbox,pages", &pages); + if (ret) { + dev_dbg(dev, "No sandbox,pages property for chip %s", + ofnode_get_name(np)); + goto err; + } + + ret = ofnode_read_u32(np, "sandbox,err-count", &err_count); + if (ret) { + dev_dbg(dev, + "No sandbox,err-count property for chip %s", + ofnode_get_name(np)); + goto err; + } + + ret = ofnode_read_u32(np, "sandbox,err-step-size", + &err_step_size); + if (ret) { + dev_dbg(dev, + "No sandbox,err-step-size property for chip %s", + ofnode_get_name(np)); + goto err; + } + + chip = calloc(sizeof(*chip), 1); + if (!chip) { + ret = -ENOMEM; + goto err; + } + + chip->cs = cs; + chip->id = id; + chip->id_len = id_len; + chip->chunksize = pagesize + oobsize; + chip->pagesize = pagesize; + chip->pages = pages; + chip->pages_per_erase = erasesize / pagesize; + memset(chip->tmp, 0xff, chip->chunksize); + + chip->err_count = err_count; + chip->err_step_bits = err_step_size * 8; + chip->err_steps = pagesize / err_step_size; + + expected_size = (off_t)pages * chip->chunksize; + snprintf(filename, sizeof(filename), + "/tmp/u-boot.nand%d.XXXXXX", devnum); + chip->fd = os_mktemp(filename, expected_size); + if (chip->fd < 0) { + dev_dbg(dev, "Could not create temp file %s\n", + filename); + ret = chip->fd; + goto err_chip; + } + + chip->programmed = calloc(sizeof(long), + BITS_TO_LONGS(pages)); + if (!chip->programmed) { + ret = -ENOMEM; + goto err_fd; + } + + if (onfi) { + memcpy(chip->onfi, onfi, onfi_len); + memcpy(chip->onfi + onfi_len, onfi, onfi_len); + memcpy(chip->onfi + 2 * onfi_len, onfi, onfi_len); + } + + nand = &chip->nand; + nand->options = spl_in_proper() ? 0 : NAND_SKIP_BBTSCAN; + nand->flash_node = np; + nand->dev_ready = sand_nand_dev_ready; + nand->cmdfunc = sand_nand_command; + nand->waitfunc = sand_nand_wait; + nand->select_chip = sand_nand_select_chip; + nand->read_byte = sand_nand_read_byte; + nand->read_word = sand_nand_read_word; + nand->read_buf = sand_nand_read_buf; + nand->write_buf = sand_nand_write_buf; + nand->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK; + + mtd = nand_to_mtd(nand); + mtd->dev = dev; + + ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS); + if (ret) { + dev_dbg(dev, "Could not scan chip %s: %d\n", + ofnode_get_name(np), ret); + goto err_prog; + } + chip->ecc_bits = nand->ecc.layout->eccbytes * 8 / + chip->err_steps; + + ret = nand_register(devnum, mtd); + if (ret) { + dev_dbg(dev, "Could not register nand %d: %d\n", devnum, + ret); + goto err_prog; + } + + if (!nand_chip) + nand_chip = nand; + + list_add_tail(&chip->node, &priv->chips); + devnum++; + continue; + +err_prog: + free(chip->programmed); +err_fd: + os_close(chip->fd); +err_chip: + free(chip); + goto err; + } + + return 0; + +err: + sand_nand_remove(dev); + return ret; +} + +static const struct udevice_id sand_nand_ids[] = { + { .compatible = "sandbox,nand" }, + { } +}; + +U_BOOT_DRIVER(sand_nand) = { + .name = "sand-nand", + .id = UCLASS_MTD, + .of_match = sand_nand_ids, + .probe = sand_nand_probe, + .remove = sand_nand_remove, + .priv_auto = sizeof(struct sand_nand_priv), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int err; + + err = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_REF(sand_nand), + &dev); + if (err && err != -ENODEV) + log_info("Failed to get sandbox NAND: %d\n", err); +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT) +void nand_deselect(void) +{ + nand_chip->select_chip(nand_to_mtd(nand_chip), -1); +} + +static int nand_is_bad_block(int block) +{ + struct mtd_info *mtd = nand_to_mtd(nand_chip); + + return mtd_block_isbad(mtd, block << mtd->erasesize_shift); +} + +static int nand_read_page(int block, int page, uchar *dst) +{ + struct mtd_info *mtd = nand_to_mtd(nand_chip); + loff_t ofs = ((loff_t)block << mtd->erasesize_shift) + + ((loff_t)page << mtd->writesize_shift); + size_t len = mtd->writesize; + + return nand_read(mtd, ofs, &len, dst); +} + +#include "nand_spl_loaders.c" +#endif /* CONFIG_SPL_NAND_INIT */ diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 64be6486b4e..3528824575b 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -22,6 +22,7 @@ #include <linux/ioport.h> #include <linux/mtd/rawnand.h> #include <linux/printk.h> +#include <linux/time.h> /* Bad block marker length */ #define FMC2_BBM_LEN 2 @@ -127,8 +128,6 @@ #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) -#define FMC2_NSEC_PER_SEC 1000000000L - #define FMC2_TIMEOUT_5S 5000000 enum stm32_fmc2_ecc { @@ -603,7 +602,7 @@ static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip, struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); struct stm32_fmc2_timings *tims = &nand->timings; unsigned long hclk = clk_get_rate(&nfc->clk); - unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000); + unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); unsigned long timing, tar, tclr, thiz, twait; unsigned long tset_mem, tset_att, thold_mem, thold_att; diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c index 6de0b0a3554..c9b8c78ed75 100644 --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c @@ -524,9 +524,10 @@ static int nand_read_buffer(struct nfc_config *conf, uint32_t offs, return 0; } +static struct nfc_config conf; + int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) { - static struct nfc_config conf = { }; int ret; ret = nand_detect_config(&conf, offs, dest); @@ -536,6 +537,11 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) return nand_read_buffer(&conf, offs, size, dest); } +unsigned int nand_page_size(void) +{ + return conf.page_size; +} + void nand_deselect(void) { struct sunxi_ccm_reg *const ccm = diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index 04791df69bb..ecacabefadc 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -44,14 +44,12 @@ void onenand_init(void) puts("Flex-"); puts("OneNAND: "); -#ifdef CONFIG_MTD /* * Add MTD device so that we can reference it later * via the mtdcore infrastructure (e.g. ubi). */ onenand_mtd.name = dev_name; add_mtd_device(&onenand_mtd); -#endif } print_size(onenand_chip.chipsize, "\n"); } diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 790d15f5bb2..d068b7860e1 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -229,6 +229,11 @@ config SPI_FLASH_XTX Add support for various XTX (XTX Technology Limited) SPI flash chips (XT25xxx). +config SPI_FLASH_ZBIT + bool "ZBIT SPI flash support" + help + Add support for Zbit Semiconductor Inc. SPI flash chips (ZB25xxx). + endif config SPI_FLASH_USE_4K_SECTORS diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index bb4a1c53a91..8db522fca06 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -595,5 +595,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif +#ifdef CONFIG_SPI_FLASH_ZBIT + /* Zbit Semiconductor Inc. */ + { INFO("zb25vq128", 0x5e4018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, +#endif { }, }; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ebab4d9f2e5..23ad2c29d0a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -471,14 +471,6 @@ config SYS_UNIFY_CACHE depends on MCFFEC bool "Invalidate icache during ethernet operations" -config FSLDMAFEC - bool "ColdFire DMA Ethernet Support" - select PHYLIB - select SYS_DISCOVER_PHY - help - This driver supports the network interface units in the - ColdFire family. - config KS8851_MLL bool "Microchip KS8851-MLL controller driver" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1ce6fea323c..f9aed1646c9 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,7 +37,6 @@ obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o obj-$(CONFIG_FEC_MXC) += fec_mxc.o obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o -obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index a4e3698c600..e40e399c802 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1711,6 +1711,10 @@ static const struct udevice_id eqos_ids[] = { .compatible = "nxp,imx8mp-dwmac-eqos", .data = (ulong)&eqos_imx_config }, + { + .compatible = "nxp,imx93-dwmac-eqos", + .data = (ulong)&eqos_imx_config + }, #endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP) { diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index 60f3f3f5a10..e3f55dd9817 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -181,6 +181,9 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev) ulong rate; int ret; + if (device_is_compatible(dev, "nxp,imx93-dwmac-eqos")) + return 0; + debug("%s(dev=%p):\n", __func__, dev); if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII) diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 7dfa8219094..a8caa0f0927 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -3,7 +3,6 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> */ -#include <common.h> #include <env.h> #include <fs_loader.h> #include <image.h> diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c deleted file mode 100644 index cc61a107403..00000000000 --- a/drivers/net/fsl_mcdmafec.c +++ /dev/null @@ -1,592 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * Conversion to DM - * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com> - */ - -#include <common.h> -#include <env.h> -#include <hang.h> -#include <malloc.h> -#include <command.h> -#include <config.h> -#include <net.h> -#include <miiphy.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/mii.h> -#include <asm/immap.h> -#include <asm/fsl_mcdmafec.h> - -#include "MCD_dma.h" - -#undef ET_DEBUG -#undef MII_DEBUG - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 -#define PKT_MAXBUF_SIZE 1518 -#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) - -/* RxBD bits definitions */ -#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ - BD_ENET_RX_OV | BD_ENET_RX_TR) - -DECLARE_GLOBAL_DATA_PTR; - -static void init_eth_info(struct fec_info_dma *info) -{ - /* setup Receive and Transmit buffer descriptor */ -#ifdef CFG_SYS_FEC_BUF_USE_SRAM - static u32 tmp; - - if (info->index == 0) - tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; - else - info->rxbd = (cbd_t *)DBUF_LENGTH; - - info->rxbd = (cbd_t *)((u32)info->rxbd + tmp); - tmp = (u32)info->rxbd; - info->txbd = - (cbd_t *)((u32)info->txbd + tmp + - (PKTBUFSRX * sizeof(cbd_t))); - tmp = (u32)info->txbd; - info->txbuf = - (char *)((u32)info->txbuf + tmp + - (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); - tmp = (u32)info->txbuf; -#else - info->rxbd = - (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, - (PKTBUFSRX * sizeof(cbd_t))); - info->txbd = - (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, - (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); - info->txbuf = - (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); -#endif - -#ifdef ET_DEBUG - printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd); -#endif - info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); -} - -static void fec_halt(struct udevice *dev) -{ - struct fec_info_dma *info = dev_get_priv(dev); - volatile fecdma_t *fecp = (fecdma_t *)info->iobase; - int counter = 0xffff; - - /* issue graceful stop command to the FEC transmitter if necessary */ - fecp->tcr |= FEC_TCR_GTS; - - /* wait for graceful stop to register */ - while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) - ; - - /* Disable DMA tasks */ - MCD_killDma(info->tx_task); - MCD_killDma(info->rx_task); - - /* Disable the Ethernet Controller */ - fecp->ecr &= ~FEC_ECR_ETHER_EN; - - /* Clear FIFO status registers */ - fecp->rfsr &= FIFO_ERRSTAT; - fecp->tfsr &= FIFO_ERRSTAT; - - fecp->frst = 0x01000000; - - /* Issue a reset command to the FEC chip */ - fecp->ecr |= FEC_ECR_RESET; - - /* wait at least 20 clock cycles */ - mdelay(10); - -#ifdef ET_DEBUG - printf("Ethernet task stopped\n"); -#endif -} - -#ifdef ET_DEBUG -static void dbg_fec_regs(struct eth_device *dev) -{ - struct fec_info_dma *info = dev->priv; - volatile fecdma_t *fecp = (fecdma_t *)info->iobase; - - printf("=====\n"); - printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); - printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); - printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); - printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); - printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); - printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); - printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); - printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); - printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); - printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); - printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); - printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); - printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); - printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); - printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); - printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); - printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); - printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); - printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); - printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); - printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); - printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); - printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); - printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); - printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); - printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); - printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); - printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); - printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); - printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); - printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); - printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); - printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); - printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); - printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); -} -#endif - -static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd) -{ - struct bd_info *bd = gd->bd; - - if ((dup_spd >> 16) == FULL) { - /* Set maximum frame length */ - fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | - FEC_RCR_PROM | 0x100; - fecp->tcr = FEC_TCR_FDEN; - } else { - /* Half duplex mode */ - fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | - FEC_RCR_MII_MODE | FEC_RCR_DRT; - fecp->tcr &= ~FEC_TCR_FDEN; - } - - if ((dup_spd & 0xFFFF) == _100BASET) { -#ifdef MII_DEBUG - printf("100Mbps\n"); -#endif - bd->bi_ethspeed = 100; - } else { -#ifdef MII_DEBUG - printf("10Mbps\n"); -#endif - bd->bi_ethspeed = 10; - } -} - -static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac) -{ - u8 curr_byte; /* byte for which to compute the CRC */ - int byte; /* loop - counter */ - int bit; /* loop - counter */ - u32 crc = 0xffffffff; /* initial value */ - - for (byte = 0; byte < 6; byte++) { - curr_byte = mac[byte]; - for (bit = 0; bit < 8; bit++) { - if ((curr_byte & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - curr_byte >>= 1; - } - } - - crc = crc >> 26; - - /* Set individual hash table register */ - if (crc >= 32) { - fecp->ialr = (1 << (crc - 32)); - fecp->iaur = 0; - } else { - fecp->ialr = 0; - fecp->iaur = (1 << crc); - } - - /* Set physical address */ - fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; - fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; - - /* Clear multicast address hash table */ - fecp->gaur = 0; - fecp->galr = 0; -} - -static int fec_init(struct udevice *dev) -{ - struct fec_info_dma *info = dev_get_priv(dev); - volatile fecdma_t *fecp = (fecdma_t *)info->iobase; - int rval, i; - uchar enetaddr[6]; - -#ifdef ET_DEBUG - printf("fec_init: iobase 0x%08x ...\n", info->iobase); -#endif - - fecpin_setclear(info, 1); - fec_halt(dev); - - mii_init(); - set_fec_duplex_speed(fecp, info->dup_spd); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set station address */ - if (info->index == 0) - rval = eth_env_get_enetaddr("ethaddr", enetaddr); - else - rval = eth_env_get_enetaddr("eth1addr", enetaddr); - - if (!rval) { - puts("Please set a valid MAC address\n"); - return -EINVAL; - } - - fec_set_hwaddr(fecp, enetaddr); - - /* Set Opcode/Pause Duration Register */ - fecp->opd = 0x00010020; - - /* Setup Buffers and Buffer Descriptors */ - info->rx_idx = 0; - info->tx_idx = 0; - - /* Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: Empty, Wrap */ - for (i = 0; i < PKTBUFSRX; i++) { - info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; - info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; - } - info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: Last, Tx CRC */ - for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) { - info->txbd[i].cbd_sc = 0; - info->txbd[i].cbd_datlen = 0; - info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); - } - info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; - - info->used_tbd_idx = 0; - info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER; - - /* Set Rx FIFO alarm and granularity value */ - fecp->rfcr = 0x0c000000; - fecp->rfar = 0x0000030c; - - /* Set Tx FIFO granularity value */ - fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; - fecp->tfar = 0x00000080; - - fecp->tfwr = 0x2; - fecp->ctcwr = 0x03000000; - - /* Enable DMA receive task */ - MCD_startDma(info->rx_task, - (s8 *)info->rxbd, - 0, - (s8 *)&fecp->rfdr, - 4, - 0, - 4, - info->rx_init, - info->rx_pri, - (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), - (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) - ); - - /* Enable DMA tx task with no ready buffer descriptors */ - MCD_startDma(info->tx_task, - (s8 *)info->txbd, - 0, - (s8 *)&fecp->tfdr, - 4, - 0, - 4, - info->tx_init, - info->tx_pri, - (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), - (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) - ); - - /* Now enable the transmit and receive processing */ - fecp->ecr |= FEC_ECR_ETHER_EN; - - return 0; -} - -static int mcdmafec_init(struct udevice *dev) -{ - return fec_init(dev); -} - -static int mcdmafec_send(struct udevice *dev, void *packet, int length) -{ - struct fec_info_dma *info = dev_get_priv(dev); - cbd_t *p_tbd, *p_used_tbd; - u16 phy_status; - - miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status); - - /* process all the consumed TBDs */ - while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) { - p_used_tbd = &info->txbd[info->used_tbd_idx]; - if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) { -#ifdef ET_DEBUG - printf("Cannot clean TBD %d, in use\n", - info->clean_tbd_num); -#endif - return 0; - } - - /* clean this buffer descriptor */ - if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1)) - p_used_tbd->cbd_sc = BD_ENET_TX_WRAP; - else - p_used_tbd->cbd_sc = 0; - - /* update some indeces for a correct handling of TBD ring */ - info->clean_tbd_num++; - info->used_tbd_idx = (info->used_tbd_idx + 1) - % CFG_SYS_TX_ETH_BUFFER; - } - - /* Check for valid length of data. */ - if (length > 1500 || length <= 0) - return -1; - - /* Check the number of vacant TxBDs. */ - if (info->clean_tbd_num < 1) { - printf("No available TxBDs ...\n"); - return -1; - } - - /* Get the first TxBD to send the mac header */ - p_tbd = &info->txbd[info->tx_idx]; - p_tbd->cbd_datlen = length; - p_tbd->cbd_bufaddr = (u32)packet; - p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; - info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER; - - /* Enable DMA transmit task */ - MCD_continDma(info->tx_task); - - info->clean_tbd_num -= 1; - - /* wait until frame is sent . */ - while (p_tbd->cbd_sc & BD_ENET_TX_READY) - udelay(10); - - return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS); -} - -static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp) -{ - struct fec_info_dma *info = dev_get_priv(dev); - volatile fecdma_t *fecp = (fecdma_t *)info->iobase; - - cbd_t *prbd = &info->rxbd[info->rx_idx]; - u32 ievent; - int frame_length, len = 0; - - /* Check if any critical events have happened */ - ievent = fecp->eir; - if (ievent != 0) { - fecp->eir = ievent; - - if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { - printf("fec_recv: error\n"); - fec_halt(dev); - fec_init(dev); - return 0; - } - - if (ievent & FEC_EIR_HBERR) { - /* Heartbeat error */ - fecp->tcr |= FEC_TCR_GTS; - } - - if (ievent & FEC_EIR_GRA) { - /* Graceful stop complete */ - if (fecp->tcr & FEC_TCR_GTS) { - printf("fec_recv: tcr_gts\n"); - fec_halt(dev); - fecp->tcr &= ~FEC_TCR_GTS; - fec_init(dev); - } - } - } - - if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) { - if ((prbd->cbd_sc & BD_ENET_RX_LAST) && - !(prbd->cbd_sc & BD_ENET_RX_ERR) && - ((prbd->cbd_datlen - 4) > 14)) { - /* Get buffer address and size */ - frame_length = prbd->cbd_datlen - 4; - - /* Fill the buffer and pass it to upper layers */ - net_process_received_packet((uchar *)prbd->cbd_bufaddr, - frame_length); - len = frame_length; - } - - /* Reset buffer descriptor as empty */ - if (info->rx_idx == (PKTBUFSRX - 1)) - prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - else - prbd->cbd_sc = BD_ENET_RX_EMPTY; - - prbd->cbd_datlen = PKTSIZE_ALIGN; - - /* Now, we have an empty RxBD, restart the DMA receive task */ - MCD_continDma(info->rx_task); - - /* Increment BD count */ - info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX; - } - - return len; -} - -static void mcdmafec_halt(struct udevice *dev) -{ - fec_halt(dev); -} - -static const struct eth_ops mcdmafec_ops = { - .start = mcdmafec_init, - .send = mcdmafec_send, - .recv = mcdmafec_recv, - .stop = mcdmafec_halt, -}; - -/* - * Boot sequence, called just after mcffec_of_to_plat, - * as DM way, it replaces old mcffec_initialize. - */ -static int mcdmafec_probe(struct udevice *dev) -{ - struct fec_info_dma *info = dev_get_priv(dev); - struct eth_pdata *pdata = dev_get_plat(dev); - int node = dev_of_offset(dev); - int retval; - const u32 *val; - - info->index = dev_seq(dev); - info->iobase = pdata->iobase; - info->miibase = pdata->iobase; - info->phy_addr = -1; - - val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL); - if (val) - info->rx_task = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL); - if (val) - info->tx_task = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL); - if (val) - info->rx_pri = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL); - if (val) - info->tx_pri = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL); - if (val) - info->rx_init = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL); - if (val) - info->tx_init = fdt32_to_cpu(*val); - -#ifdef CFG_SYS_FEC_BUF_USE_SRAM - u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; -#endif - init_eth_info(info); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - info->bus = mdio_alloc(); - if (!info->bus) - return -ENOMEM; - strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN); - info->bus->read = mcffec_miiphy_read; - info->bus->write = mcffec_miiphy_write; - - retval = mdio_register(info->bus); - if (retval < 0) - return retval; -#endif - - return 0; -} - -static int mcdmafec_remove(struct udevice *dev) -{ - struct fec_info_dma *priv = dev_get_priv(dev); - - mdio_unregister(priv->bus); - mdio_free(priv->bus); - - return 0; -} - -/* - * Boot sequence, called 1st - */ -static int mcdmafec_of_to_plat(struct udevice *dev) -{ - struct eth_pdata *pdata = dev_get_plat(dev); - const u32 *val; - - pdata->iobase = dev_read_addr(dev); - /* Default to 10Mbit/s */ - pdata->max_speed = 10; - - val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); - if (val) - pdata->max_speed = fdt32_to_cpu(*val); - - return 0; -} - -static const struct udevice_id mcdmafec_ids[] = { - { .compatible = "fsl,mcf-dma-fec" }, - { } -}; - -U_BOOT_DRIVER(mcffec) = { - .name = "mcdmafec", - .id = UCLASS_ETH, - .of_match = mcdmafec_ids, - .of_to_plat = mcdmafec_of_to_plat, - .probe = mcdmafec_probe, - .remove = mcdmafec_remove, - .ops = &mcdmafec_ops, - .priv_auto = sizeof(struct fec_info_dma), - .plat_auto = sizeof(struct eth_pdata), -}; diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 396cac76d63..7e1036b2271 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -446,6 +446,20 @@ U_BOOT_PHY_DRIVER(rtl8211f) = { .writeext = &rtl8211f_phy_extwrite, }; +/* Support for RTL8211F-VD PHY */ +U_BOOT_PHY_DRIVER(rtl8211fvd) = { + .name = "RealTek RTL8211F-VD", + .uid = 0x1cc878, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .probe = &rtl8211f_probe, + .config = &rtl8211f_config, + .startup = &rtl8211f_startup, + .shutdown = &genphy_shutdown, + .readext = &rtl8211f_phy_extread, + .writeext = &rtl8211f_phy_extwrite, +}; + /* Support for RTL8201F PHY */ U_BOOT_PHY_DRIVER(rtl8201f) = { .name = "RealTek RTL8201F 10/100Mbps Ethernet", diff --git a/drivers/net/qe/uccf.c b/drivers/net/qe/uccf.c index 306f1ea1db6..00848a1a37d 100644 --- a/drivers/net/qe/uccf.c +++ b/drivers/net/qe/uccf.c @@ -6,7 +6,6 @@ * based on source code of Shlomi Gridish */ -#include <common.h> #include <malloc.h> #include <linux/errno.h> #include <asm/io.h> diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 54f22327684..ef151ee51b4 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -903,12 +903,11 @@ static int axi_emac_of_to_plat(struct udevice *dev) ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0, &axistream_node); - if (ret) { - printf("%s: axistream is not found\n", __func__); - return -EINVAL; - } + if (!ret) + plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node); + else + plat->dmatx = (struct axidma_reg *)dev_read_addr_index(dev, 1); - plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node); if (!plat->dmatx) { printf("%s: axi_dma register space not found\n", __func__); return -EINVAL; diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index 53fd121e905..3db460b5f93 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -8,11 +8,10 @@ #include <common.h> #include <dm.h> #include <pci.h> -#include <asm/global_data.h> #include <linux/bitops.h> #include <linux/printk.h> - -#include <asm/io.h> +#include <linux/io.h> +#include <linux/err.h> /** * struct xilinx_pcie - Xilinx PCIe controller state @@ -25,6 +24,8 @@ struct xilinx_pcie { /* Register definitions */ #define XILINX_PCIE_REG_PSCR 0x144 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) +#define XILINX_PCIE_REG_RPSC 0x148 +#define XILINX_PCIE_REG_RPSC_BEN BIT(0) /** * pcie_xilinx_link_up() - Check whether the PCIe link is up @@ -140,20 +141,22 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf, static int pcie_xilinx_of_to_plat(struct udevice *dev) { struct xilinx_pcie *pcie = dev_get_priv(dev); - struct fdt_resource reg_res; - DECLARE_GLOBAL_DATA_PTR; - int err; - - err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", - 0, ®_res); - if (err < 0) { - pr_err("\"reg\" resource not found\n"); - return err; - } - - pcie->cfg_base = map_physmem(reg_res.start, - fdt_resource_size(®_res), - MAP_NOCACHE); + fdt_addr_t addr; + fdt_size_t size; + u32 rpsc; + + addr = dev_read_addr_size(dev, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + pcie->cfg_base = devm_ioremap(dev, addr, size); + if (IS_ERR(pcie->cfg_base)) + return PTR_ERR(pcie->cfg_base); + + /* Enable the Bridge enable bit */ + rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC); + rpsc |= XILINX_PCIE_REG_RPSC_BEN; + __raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC); return 0; } diff --git a/drivers/phy/meson-axg-mipi-dphy.c b/drivers/phy/meson-axg-mipi-dphy.c index cf2a1cd14c7..a69b6c97594 100644 --- a/drivers/phy/meson-axg-mipi-dphy.c +++ b/drivers/phy/meson-axg-mipi-dphy.c @@ -25,6 +25,7 @@ #include <linux/bitops.h> #include <linux/compat.h> #include <linux/bitfield.h> +#include <linux/time.h> /* [31] soft reset for the phy. * 1: reset. 0: dessert the reset. @@ -170,8 +171,6 @@ #define MIPI_DSI_TEST_CTRL0 0x3c #define MIPI_DSI_TEST_CTRL1 0x40 -#define NSEC_PER_MSEC 1000000L - struct phy_meson_axg_mipi_dphy_priv { struct regmap *regmap; #if CONFIG_IS_ENABLED(CLK) diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c index ba5f6486126..bb61816add2 100644 --- a/drivers/phy/phy-core-mipi-dphy.c +++ b/drivers/phy/phy-core-mipi-dphy.c @@ -6,11 +6,10 @@ #include <common.h> #include <div64.h> +#include <linux/time.h> #include <phy-mipi-dphy.h> -#define PSEC_PER_SEC 1000000000000LL - /* * Minimum D-PHY timings based on MIPI D-PHY specification. Derived * from the valid ranges specified in Section 6.9, Table 14, Page 41 diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c index b660eadecf1..e5e96e77a68 100644 --- a/drivers/phy/phy-imx8mq-usb.c +++ b/drivers/phy/phy-imx8mq-usb.c @@ -231,16 +231,10 @@ static int imx8mq_usb_phy_power_off(struct phy *usb_phy) return 0; } -static int imx8mq_usb_phy_exit(struct phy *usb_phy) -{ - return imx8mq_usb_phy_power_off(usb_phy); -} - struct phy_ops imx8mq_usb_phy_ops = { .init = imx8mpq_usb_phy_init, .power_on = imx8mq_usb_phy_power_on, .power_off = imx8mq_usb_phy_power_off, - .exit = imx8mq_usb_phy_exit, }; int imx8mq_usb_phy_probe(struct udevice *dev) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 9ed7af0d6ef..5be76e05339 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -15,6 +15,7 @@ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/math64.h> +#include <linux/time.h> #include <phy-mipi-dphy.h> #include <reset.h> @@ -186,8 +187,6 @@ #define DSI_PHY_STATUS 0xb0 #define PHY_LOCK BIT(0) -#define PSEC_PER_SEC 1000000000000LL - #define msleep(a) udelay(a * 1000) enum phy_max_rate { diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 8bb7588714a..7120b8edba0 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -505,6 +505,8 @@ static const struct udevice_id stm32_pinctrl_ids[] = { { .compatible = "st,stm32mp157-pinctrl" }, { .compatible = "st,stm32mp157-z-pinctrl" }, { .compatible = "st,stm32mp135-pinctrl" }, + { .compatible = "st,stm32mp257-pinctrl" }, + { .compatible = "st,stm32mp257-z-pinctrl" }, { } }; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 2395720c99c..33b8bc1214d 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -56,7 +56,6 @@ choice depends on ARCH_SUNXI default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 - default AXP305_POWER if MACH_SUN50I_H616 default AXP818_POWER if MACH_SUN8I_A83T default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S diff --git a/drivers/pwm/pwm-aspeed.c b/drivers/pwm/pwm-aspeed.c index ba98641c866..b03472d2345 100644 --- a/drivers/pwm/pwm-aspeed.c +++ b/drivers/pwm/pwm-aspeed.c @@ -49,6 +49,7 @@ #include <dm/device_compat.h> #include <linux/math64.h> #include <linux/bitfield.h> +#include <linux/time.h> #include <asm/io.h> /* The channel number of Aspeed pwm controller */ @@ -77,8 +78,6 @@ /* PWM fixed value */ #define PWM_ASPEED_FIXED_PERIOD 0xff -#define NSEC_PER_SEC 1000000000L - struct aspeed_pwm_priv { struct clk clk; struct regmap *regmap; diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c index 95597aee557..3ff1fb6d5c3 100644 --- a/drivers/pwm/pwm-at91.c +++ b/drivers/pwm/pwm-at91.c @@ -14,11 +14,11 @@ #include <dm.h> #include <linux/bitops.h> #include <linux/io.h> +#include <linux/time.h> #include <pwm.h> #define PERIOD_BITS 16 #define PWM_MAX_PRES 10 -#define NSEC_PER_SEC 1000000000L #define PWM_ENA 0x04 #define PWM_CHANNEL_OFFSET 0x20 diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c index dc3b314b0cc..d9f6736a7ae 100644 --- a/drivers/pwm/pwm-cadence-ttc.c +++ b/drivers/pwm/pwm-cadence-ttc.c @@ -17,6 +17,7 @@ #include <linux/bitfield.h> #include <linux/math64.h> #include <linux/log2.h> +#include <linux/time.h> #include <dm/device_compat.h> #define CLOCK_CONTROL 0 @@ -37,8 +38,6 @@ #define COUNTER_INTERVAL_ENABLE BIT(1) #define COUNTER_COUNTING_DISABLE BIT(0) -#define NSEC_PER_SEC 1000000000L - #define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32)) #define TTC_CLOCK_CONTROL(reg, channel) \ TTC_REG((reg) + CLOCK_CONTROL, (channel)) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 2311910a636..60959720dac 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -26,8 +26,7 @@ #include <linux/math64.h> #include <linux/bitfield.h> #include <linux/clk-provider.h> - -#define NSEC_PER_SEC 1000000000L +#include <linux/time.h> #define REG_PWM_A 0x0 #define REG_PWM_B 0x4 diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c index 11e74440197..ad845ed9662 100644 --- a/drivers/pwm/pwm-mtk.c +++ b/drivers/pwm/pwm-mtk.c @@ -12,6 +12,7 @@ #include <div64.h> #include <linux/bitops.h> #include <linux/io.h> +#include <linux/time.h> /* PWM registers and bits definitions */ #define PWMCON 0x00 @@ -27,8 +28,6 @@ #define PWM_CLK_DIV_MAX 7 #define MAX_PWM_NUM 8 -#define NSEC_PER_SEC 1000000000L - enum mtk_pwm_reg_ver { PWM_REG_V1, PWM_REG_V2, diff --git a/drivers/pwm/pwm-ti-ehrpwm.c b/drivers/pwm/pwm-ti-ehrpwm.c index f09914519bd..fefa3c65ec4 100644 --- a/drivers/pwm/pwm-ti-ehrpwm.c +++ b/drivers/pwm/pwm-ti-ehrpwm.c @@ -14,8 +14,7 @@ #include <dm/device_compat.h> #include <pwm.h> #include <asm/io.h> - -#define NSEC_PER_SEC 1000000000L +#include <linux/time.h> /* Time base module registers */ #define TI_EHRPWM_TBCTL 0x00 diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index 6195c7c4442..fa9e4065560 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <asm/global_data.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 2825dc6f9aa..9631337b8d9 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -6,7 +6,6 @@ * based on source code of Shlomi Gridish */ -#include <common.h> #include <malloc.h> #include <command.h> #include <asm/global_data.h> @@ -24,6 +23,9 @@ #include <asm/armv8/mmu.h> #include <asm/arch/cpu.h> #endif +#ifdef CONFIG_PPC +#include <asm/ppc.h> +#endif #define MPC85xx_DEVDISR_QE_DISABLE 0x1 diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index a8014129d33..7e21c4ae2bb 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -1,46 +1,9 @@ config SCSI - bool "Support SCSI controllers" + bool "Support SCSI controllers with driver model" help This enables support for SCSI (Small Computer System Interface), a parallel interface widely used with storage peripherals such as hard drives and optical drives. The SCSI standards define physical interfaces as well as protocols for controlling devices and - tranferring data. - -config DM_SCSI - bool "Support SCSI controllers with driver model" - help - This option enables the SCSI (Small Computer System Interface) uclass - which supports SCSI and SATA HDDs. For every device configuration - (IDs/LUNs) a block device is created with RAW read/write and - filesystem support. - -if SCSI && !DM_SCSI - -config SCSI_AHCI_PLAT - bool "Platform-specific init of AHCI" - help - This enables a way for boards to set up an AHCI device manually, by - called ahci_init() and providing an ahci_reset() mechanism. - - This is deprecated. An AHCI driver should be provided instead. - -config SYS_SCSI_MAX_SCSI_ID - int "Maximum supported SCSI ID" - default 1 - help - Sets the maximum number of SCSI IDs to scan when looking for devices. - IDs from 0 to (this value - 1) are scanned. - - This is deprecated and is not needed when BLK is enabled. - -config SYS_SCSI_MAX_LUN - int "Maximum support SCSI LUN" - default 1 - help - Sets the maximum number of SCSI Logical Unit Numbers (LUNs) to scan on - devices. LUNs from 0 to (this value - 1) are scanned. - - This is deprecated and is not needed when CONFIG_DM_SCSI is enabled. - -endif + tranferring data. For every device configuration (IDs/LUNs) a block + device is created with RAW read/write and filesystem support. diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index d8d6de59090..628be4c89fb 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -4,25 +4,16 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_DM_SCSI) += scsi-uclass.o -obj-$(CONFIG_SCSI) += scsi.o - +obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o ifdef CONFIG_SCSI -ifdef CONFIG_DM_SCSI obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += scsi_bootdev.o +obj-$(CONFIG_SANDBOX) += sandbox_scsi.o +obj-$(CONFIG_SANDBOX) += scsi_emul.o endif endif -endif - ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_SATA -obj-$(CONFIG_DM_SCSI) += scsi-uclass.o -obj-$(CONFIG_SCSI) += scsi.o +obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o endif endif - -ifdef CONFIG_SCSI -obj-$(CONFIG_SANDBOX) += sandbox_scsi.o -obj-$(CONFIG_SANDBOX) += scsi_emul.o -endif diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 1330482c167..79ee400d12f 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -21,38 +21,10 @@ #include <dm/device-internal.h> #include <dm/uclass-internal.h> -#if !defined(CONFIG_DM_SCSI) -# ifdef CFG_SCSI_DEV_LIST -# define SCSI_DEV_LIST CFG_SCSI_DEV_LIST -# else -# ifdef CONFIG_SATA_ULI5288 - -# define SCSI_VEND_ID 0x10b9 -# define SCSI_DEV_ID 0x5288 - -# elif !defined(CONFIG_SCSI_AHCI_PLAT) -# error no scsi device defined -# endif -# define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -# endif -#endif - -#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \ - !defined(CONFIG_DM_SCSI) -const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST }; -#endif static struct scsi_cmd tempccb; /* temporary scsi command buffer */ DEFINE_CACHE_ALIGN_BUFFER(u8, tempbuff, 512); /* temporary data buffer */ -#if !defined(CONFIG_DM_SCSI) -static int scsi_max_devs; /* number of highest available scsi device */ - -static int scsi_curr_dev; /* current device */ - -static struct blk_desc scsi_dev_desc[SCSI_MAX_DEVICE]; -#endif - /* almost the maximum amount of the scsi_ext command.. */ #define SCSI_MAX_BLK 0xFFFF #define SCSI_LBA48_READ 0xFFFFFFF @@ -107,7 +79,6 @@ static void scsi_setup_inquiry(struct scsi_cmd *pccb) pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ } -#ifdef CONFIG_BLK static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, unsigned short blocks) { @@ -286,59 +257,6 @@ static int scsi_buffer_aligned(struct udevice *dev, struct bounce_buffer *state) return 1; } #endif /* CONFIG_BOUNCE_BUFFER */ -#endif - -#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \ - !defined(CONFIG_DM_SCSI) -void scsi_init(void) -{ - int busdevfunc = -1; - int i; - /* - * Find a device from the list, this driver will support a single - * controller. - */ - for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) { - /* get PCI Device ID */ - struct udevice *dev; - int ret; - - ret = dm_pci_find_device(scsi_device_list[i].vendor, - scsi_device_list[i].device, 0, &dev); - if (!ret) { - busdevfunc = dm_pci_get_bdf(dev); - break; - } - if (busdevfunc != -1) - break; - } - - if (busdevfunc == -1) { - printf("Error: SCSI Controller(s) "); - for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) { - printf("%04X:%04X ", - scsi_device_list[i].vendor, - scsi_device_list[i].device); - } - printf("not found\n"); - return; - } -#ifdef DEBUG - else { - printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n", - scsi_device_list[i].vendor, - scsi_device_list[i].device, - (busdevfunc >> 16) & 0xFF, - (busdevfunc >> 11) & 0x1F, - (busdevfunc >> 8) & 0x7); - } -#endif - bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci"); - scsi_low_level_init(busdevfunc); - scsi_scan(true); - bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI); -} -#endif /* copy src to dest, skipping leading and trailing blanks * and null terminate the string @@ -462,25 +380,6 @@ static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc) #endif /* CONFIG_BOUNCE_BUFFER */ } -#if !defined(CONFIG_DM_SCSI) -/** - * scsi_init_dev_desc - initialize all SCSI specific blk_desc properties - * - * @dev_desc: Block device description pointer - * @devnum: Device number - */ -static void scsi_init_dev_desc(struct blk_desc *dev_desc, int devnum) -{ - dev_desc->lba = 0; - dev_desc->blksz = 0; - dev_desc->uclass_id = UCLASS_SCSI; - dev_desc->devnum = devnum; - dev_desc->part_type = PART_TYPE_UNKNOWN; - - scsi_init_dev_desc_priv(dev_desc); -} -#endif - /** * scsi_detect_dev - Detect scsi device * @@ -569,7 +468,6 @@ removable: * (re)-scan the scsi bus and reports scsi device info * to the user if mode = 1 */ -#if defined(CONFIG_DM_SCSI) static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose) { int ret; @@ -690,48 +588,7 @@ int scsi_scan(bool verbose) return 0; } -#else -int scsi_scan(bool verbose) -{ - unsigned char i, lun; - int ret; - - if (verbose) - printf("scanning bus for devices...\n"); - for (i = 0; i < SCSI_MAX_DEVICE; i++) - scsi_init_dev_desc(&scsi_dev_desc[i], i); - - scsi_max_devs = 0; - for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { - for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) { - struct blk_desc *bdesc = &scsi_dev_desc[scsi_max_devs]; - - ret = scsi_detect_dev(NULL, i, lun, bdesc); - if (ret) - continue; - part_init(bdesc); - - if (verbose) { - printf(" Device %d: ", bdesc->devnum); - dev_print(bdesc); - } - scsi_max_devs++; - } /* next LUN */ - } - if (scsi_max_devs > 0) - scsi_curr_dev = 0; - else - scsi_curr_dev = -1; - - printf("Found %d device(s).\n", scsi_max_devs); -#ifndef CONFIG_SPL_BUILD - env_set_ulong("scsidevs", scsi_max_devs); -#endif - return 0; -} -#endif -#ifdef CONFIG_BLK static const struct blk_ops scsi_blk_ops = { .read = scsi_read, .write = scsi_write, @@ -745,11 +602,3 @@ U_BOOT_DRIVER(scsi_blk) = { .id = UCLASS_BLK, .ops = &scsi_blk_ops, }; -#else -U_BOOT_LEGACY_BLK(scsi) = { - .uclass_idname = "scsi", - .uclass_id = UCLASS_SCSI, - .max_devs = SCSI_MAX_DEVICE, - .desc = scsi_dev_desc, -}; -#endif diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 78fd9389c03..b8bc61451a0 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -13,14 +13,13 @@ #include <dm.h> #include <errno.h> #include <linux/delay.h> +#include <linux/time.h> #include <misc.h> #include <serial.h> #define UART_OVERSAMPLING 32 #define STALE_TIMEOUT 160 -#define USEC_PER_SEC 1000000L - /* Registers*/ #define GENI_FORCE_DEFAULT_REG 0x20 #define GENI_SER_M_CLK_CFG 0x48 diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c index 76ac7cb80db..6bf3a943a2f 100644 --- a/drivers/serial/serial_npcm.c +++ b/drivers/serial/serial_npcm.c @@ -83,8 +83,11 @@ static int npcm_serial_setbrg(struct udevice *dev, int baudrate) struct npcm_uart *uart = plat->reg; u16 divisor; + if (IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT)) + return 0; + /* BaudOut = UART Clock / (16 * [Divisor + 2]) */ - divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2; + divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate) - 2; setbits_8(&uart->lcr, LCR_DLAB); writeb(divisor & 0xff, &uart->dll); @@ -97,29 +100,35 @@ static int npcm_serial_setbrg(struct udevice *dev, int baudrate) static int npcm_serial_probe(struct udevice *dev) { struct npcm_serial_plat *plat = dev_get_plat(dev); - struct npcm_uart *uart = plat->reg; + struct npcm_uart *uart; struct clk clk, parent; u32 freq; int ret; plat->reg = dev_read_addr_ptr(dev); - freq = dev_read_u32_default(dev, "clock-frequency", 0); + uart = plat->reg; - ret = clk_get_by_index(dev, 0, &clk); - if (ret < 0) - return ret; + if (!IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT)) { + freq = dev_read_u32_default(dev, "clock-frequency", 24000000); - ret = clk_get_by_index(dev, 1, &parent); - if (!ret) { - ret = clk_set_parent(&clk, &parent); - if (ret) + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) return ret; - } - ret = clk_set_rate(&clk, freq); - if (ret < 0) - return ret; - plat->uart_clk = ret; + ret = clk_get_by_index(dev, 1, &parent); + if (!ret) { + ret = clk_set_parent(&clk, &parent); + if (ret) + return ret; + } + + if (freq) { + ret = clk_set_rate(&clk, freq); + if (ret < 0) + return ret; + } + plat->uart_clk = clk_get_rate(&clk); + } /* Disable all interrupt */ writeb(0, &uart->ier); diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 23d476fba28..fb039546a41 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -30,7 +30,7 @@ */ #define ONE_BYTE_B115200_US 87 -static void _stm32_serial_setbrg(fdt_addr_t base, +static void _stm32_serial_setbrg(void __iomem *base, struct stm32_uart_info *uart_info, u32 clock_rate, int baudrate) @@ -75,7 +75,7 @@ static int stm32_serial_setconfig(struct udevice *dev, uint serial_config) struct stm32x7_serial_plat *plat = dev_get_plat(dev); bool stm32f4 = plat->uart_info->stm32f4; u8 uart_enable_bit = plat->uart_info->uart_enable_bit; - u32 cr1 = plat->base + CR1_OFFSET(stm32f4); + void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4); u32 config = 0; uint parity = SERIAL_GET_PARITY(serial_config); uint bits = SERIAL_GET_BITS(serial_config); @@ -122,7 +122,7 @@ static int stm32_serial_getc(struct udevice *dev) { struct stm32x7_serial_plat *plat = dev_get_plat(dev); bool stm32f4 = plat->uart_info->stm32f4; - fdt_addr_t base = plat->base; + void __iomem *base = plat->base; u32 isr = readl(base + ISR_OFFSET(stm32f4)); if ((isr & USART_ISR_RXNE) == 0) @@ -141,7 +141,7 @@ static int stm32_serial_getc(struct udevice *dev) return readl(base + RDR_OFFSET(stm32f4)); } -static int _stm32_serial_putc(fdt_addr_t base, +static int _stm32_serial_putc(void __iomem *base, struct stm32_uart_info *uart_info, const char c) { @@ -166,7 +166,7 @@ static int stm32_serial_pending(struct udevice *dev, bool input) { struct stm32x7_serial_plat *plat = dev_get_plat(dev); bool stm32f4 = plat->uart_info->stm32f4; - fdt_addr_t base = plat->base; + void __iomem *base = plat->base; if (input) return readl(base + ISR_OFFSET(stm32f4)) & @@ -176,7 +176,7 @@ static int stm32_serial_pending(struct udevice *dev, bool input) USART_ISR_TXE ? 0 : 1; } -static void _stm32_serial_init(fdt_addr_t base, +static void _stm32_serial_init(void __iomem *base, struct stm32_uart_info *uart_info) { bool stm32f4 = uart_info->stm32f4; @@ -250,11 +250,14 @@ static const struct udevice_id stm32_serial_id[] = { static int stm32_serial_of_to_plat(struct udevice *dev) { struct stm32x7_serial_plat *plat = dev_get_plat(dev); + fdt_addr_t addr; - plat->base = dev_read_addr(dev); - if (plat->base == FDT_ADDR_T_NONE) + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) return -EINVAL; + plat->base = (void __iomem *)addr; + return 0; } @@ -297,7 +300,7 @@ static inline struct stm32_uart_info *_debug_uart_info(void) static inline void _debug_uart_init(void) { - fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); struct stm32_uart_info *uart_info = _debug_uart_info(); _stm32_serial_init(base, uart_info); @@ -308,7 +311,7 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int c) { - fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); struct stm32_uart_info *uart_info = _debug_uart_info(); while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN) diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h index b7e7a90b931..d2c92ba48ea 100644 --- a/drivers/serial/serial_stm32.h +++ b/drivers/serial/serial_stm32.h @@ -49,7 +49,7 @@ struct stm32_uart_info stm32h7_info = { /* Information about a serial port */ struct stm32x7_serial_plat { - fdt_addr_t base; /* address of registers in physical memory */ + void __iomem *base; /* address of registers in physical memory */ struct stm32_uart_info *uart_info; unsigned long int clock_rate; }; diff --git a/drivers/soc/ti/keystone_serdes.c b/drivers/soc/ti/keystone_serdes.c index 2ece1a8f647..0e1bf8ff39d 100644 --- a/drivers/soc/ti/keystone_serdes.c +++ b/drivers/soc/ti/keystone_serdes.c @@ -8,6 +8,7 @@ #include <errno.h> #include <common.h> +#include <asm/io.h> #include <asm/ti-common/keystone_serdes.h> #include <linux/bitops.h> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index eb7fbf83d01..dfc74c882d2 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -7,7 +7,6 @@ #include <common.h> #include <clk.h> #include <log.h> -#include <asm-generic/io.h> #include <dm.h> #include <fdtdec.h> #include <malloc.h> @@ -17,13 +16,13 @@ #include <dm/device_compat.h> #include <linux/err.h> #include <linux/errno.h> +#include <linux/io.h> #include <linux/sizes.h> +#include <linux/time.h> #include <zynqmp_firmware.h> #include "cadence_qspi.h" #include <dt-bindings/power/xlnx-versal-power.h> -#define NSEC_PER_SEC 1000000000L - #define CQSPI_STIG_READ 0 #define CQSPI_STIG_WRITE 1 #define CQSPI_READ 2 diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index f8ec268812c..89907cbbb02 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -27,9 +27,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/printk.h> - -/* linux/include/time.h */ -#define NSEC_PER_SEC 1000000000L +#include <linux/time.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/spi/meson_spifc_a1.c b/drivers/spi/meson_spifc_a1.c index 099c4c037dd..cca4debb412 100644 --- a/drivers/spi/meson_spifc_a1.c +++ b/drivers/spi/meson_spifc_a1.c @@ -16,6 +16,7 @@ #include <spi-mem.h> #include <asm/io.h> #include <linux/log2.h> +#include <linux/time.h> #include <linux/iopoll.h> #include <linux/bitfield.h> @@ -117,7 +118,7 @@ static int amlogic_spifc_a1_request(struct amlogic_spifc_a1 *spifc, bool read) return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG, val, (val & mask) == mask, - 200 * 1000); + 200 * USEC_PER_MSEC); } static void amlogic_spifc_a1_drain_buffer(struct amlogic_spifc_a1 *spifc, @@ -129,7 +130,7 @@ static void amlogic_spifc_a1_drain_buffer(struct amlogic_spifc_a1 *spifc, writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR, spifc->base + SPIFC_A1_DBUF_CTRL_REG); - readsl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); + ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); if (pad) { data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG); @@ -146,7 +147,7 @@ static void amlogic_spifc_a1_fill_buffer(struct amlogic_spifc_a1 *spifc, writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR, spifc->base + SPIFC_A1_DBUF_CTRL_REG); - writesl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); + iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); if (pad) { memcpy(&data, buf + len - pad, pad); diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c index 6ee841358b3..6d9ab61769a 100644 --- a/drivers/spi/spi-mem-nodm.c +++ b/drivers/spi/spi-mem-nodm.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <errno.h> #include <log.h> #include <malloc.h> #include <spi.h> diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index b58a3f632a4..94ddf4967ea 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -67,7 +67,7 @@ /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ #define SPISSR_MASK(cs) (1 << (cs)) #define SPISSR_ACT(cs) ~SPISSR_MASK(cs) -#define SPISSR_OFF ~0UL +#define SPISSR_OFF (~0U) /* SPI Software Reset Register (ssr) */ #define SPISSR_RESET_VALUE 0x0a @@ -109,6 +109,27 @@ struct xilinx_spi_priv { u8 startup; }; +static int xilinx_spi_find_buffer_size(struct xilinx_spi_regs *regs) +{ + u8 sr; + int n_words = 0; + + /* + * Before the buffer_size detection reset the core + * to make sure to start with a clean state. + */ + writel(SPISSR_RESET_VALUE, ®s->srr); + + /* Fill the Tx FIFO with as many words as possible */ + do { + writel(0, ®s->spidtr); + sr = readl(®s->spisr); + n_words++; + } while (!(sr & SPISR_TX_FULL)); + + return n_words; +} + static int xilinx_spi_probe(struct udevice *bus) { struct xilinx_spi_priv *priv = dev_get_priv(bus); @@ -116,6 +137,8 @@ static int xilinx_spi_probe(struct udevice *bus) regs = priv->regs = dev_read_addr_ptr(bus); priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0); + if (!priv->fifo_depth) + priv->fifo_depth = xilinx_spi_find_buffer_size(regs); writel(SPISSR_RESET_VALUE, ®s->srr); @@ -217,9 +240,9 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes) return i; } -static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u32 len) +static int start_transfer(struct udevice *dev, const void *dout, void *din, u32 len) { - struct udevice *bus = spi->dev->parent; + struct udevice *bus = dev->parent; struct xilinx_spi_priv *priv = dev_get_priv(bus); struct xilinx_spi_regs *regs = priv->regs; u32 count, txbytes, rxbytes; @@ -259,10 +282,9 @@ static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u3 return 0; } -static void xilinx_spi_startup_block(struct spi_slave *spi) +static void xilinx_spi_startup_block(struct udevice *dev) { - struct dm_spi_slave_plat *slave_plat = - dev_get_parent_plat(spi->dev); + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); unsigned char txp; unsigned char rxp[8]; @@ -270,13 +292,25 @@ static void xilinx_spi_startup_block(struct spi_slave *spi) * Perform a dummy read as a work around for * the startup block issue. */ - spi_cs_activate(spi->dev, slave_plat->cs); + spi_cs_activate(dev, slave_plat->cs); txp = 0x9f; - start_transfer(spi, (void *)&txp, NULL, 1); + start_transfer(dev, (void *)&txp, NULL, 1); - start_transfer(spi, NULL, (void *)rxp, 6); + start_transfer(dev, NULL, (void *)rxp, 6); - spi_cs_deactivate(spi->dev); + spi_cs_deactivate(dev); +} + +static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + int ret; + + spi_cs_activate(dev, slave_plat->cs); + ret = start_transfer(dev, dout, din, bitlen / 8); + spi_cs_deactivate(dev); + return ret; } static int xilinx_spi_mem_exec_op(struct spi_slave *spi, @@ -294,14 +328,15 @@ static int xilinx_spi_mem_exec_op(struct spi_slave *spi, * as QSPI provides command. So first command fails. */ if (!startup) { - xilinx_spi_startup_block(spi); + xilinx_spi_startup_block(spi->dev); startup++; } spi_cs_activate(spi->dev, slave_plat->cs); if (op->cmd.opcode) { - ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1); + ret = start_transfer(spi->dev, (void *)&op->cmd.opcode, + NULL, 1); if (ret) goto done; } @@ -313,7 +348,7 @@ static int xilinx_spi_mem_exec_op(struct spi_slave *spi, addr_buf[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); - ret = start_transfer(spi, (void *)addr_buf, NULL, + ret = start_transfer(spi->dev, (void *)addr_buf, NULL, op->addr.nbytes); if (ret) goto done; @@ -322,16 +357,16 @@ static int xilinx_spi_mem_exec_op(struct spi_slave *spi, dummy_len = (op->dummy.nbytes * op->data.buswidth) / op->dummy.buswidth; - ret = start_transfer(spi, NULL, NULL, dummy_len); + ret = start_transfer(spi->dev, NULL, NULL, dummy_len); if (ret) goto done; } if (op->data.nbytes) { if (op->data.dir == SPI_MEM_DATA_IN) { - ret = start_transfer(spi, NULL, + ret = start_transfer(spi->dev, NULL, op->data.buf.in, op->data.nbytes); } else { - ret = start_transfer(spi, op->data.buf.out, + ret = start_transfer(spi->dev, op->data.buf.out, NULL, op->data.nbytes); } if (ret) @@ -427,6 +462,7 @@ static const struct spi_controller_mem_ops xilinx_spi_mem_ops = { static const struct dm_spi_ops xilinx_spi_ops = { .claim_bus = xilinx_spi_claim_bus, .release_bus = xilinx_spi_release_bus, + .xfer = xilinx_spi_xfer, .set_speed = xilinx_spi_set_speed, .set_mode = xilinx_spi_set_mode, .mem_ops = &xilinx_spi_mem_ops, diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig index e35f7cb1791..2030e4babc9 100644 --- a/drivers/sysinfo/Kconfig +++ b/drivers/sysinfo/Kconfig @@ -8,6 +8,13 @@ menuconfig SYSINFO if SYSINFO +config SYSINFO_EXTRA + bool "Show extra information on startup" + help + Enable this to see extra information on startup. Normally only the + model is shown, but with this option the vendor and any prior-stage + firmware's version and date are shown as well. + config SPL_SYSINFO depends on SPL_DM bool "Enable board driver support in SPL" diff --git a/drivers/sysreset/poweroff_gpio.c b/drivers/sysreset/poweroff_gpio.c index a5c24fd85bc..ad04e4b1a85 100644 --- a/drivers/sysreset/poweroff_gpio.c +++ b/drivers/sysreset/poweroff_gpio.c @@ -33,7 +33,7 @@ static int poweroff_gpio_request(struct udevice *dev, enum sysreset_t type) int r; if (type != SYSRESET_POWER_OFF) - return -ENOSYS; + return -EPROTONOSUPPORT; debug("GPIO poweroff\n"); diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c index a8a41528a84..aa09d0b8827 100644 --- a/drivers/sysreset/sysreset_psci.c +++ b/drivers/sysreset/sysreset_psci.c @@ -25,7 +25,7 @@ static int psci_sysreset_request(struct udevice *dev, enum sysreset_t type) psci_sys_poweroff(); break; default: - return -ENOSYS; + return -EPROTONOSUPPORT; } return -EINPROGRESS; diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index f485a135299..c12eda81d03 100644 --- a/drivers/sysreset/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c @@ -21,7 +21,7 @@ static int sandbox_warm_sysreset_request(struct udevice *dev, state->last_sysreset = type; break; default: - return -ENOSYS; + return -EPROTONOSUPPORT; } if (!state->sysreset_allowed[type]) return -EACCES; @@ -70,7 +70,7 @@ static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type) return -EACCES; sandbox_exit(); default: - return -ENOSYS; + return -EPROTONOSUPPORT; } if (!state->sysreset_allowed[type]) return -EACCES; diff --git a/drivers/sysreset/sysreset_watchdog.c b/drivers/sysreset/sysreset_watchdog.c index ceada2e47b5..6db5aa75b54 100644 --- a/drivers/sysreset/sysreset_watchdog.c +++ b/drivers/sysreset/sysreset_watchdog.c @@ -29,7 +29,7 @@ static int wdt_reboot_request(struct udevice *dev, enum sysreset_t type) return ret; break; default: - return -ENOSYS; + return -EPROTONOSUPPORT; } return -EINPROGRESS; diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index 4936fdb76c7..dc772b5ff9e 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -87,7 +87,7 @@ static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) return ret; return -EINPROGRESS; default: - return -ENOSYS; + return -EPROTONOSUPPORT; } outb(value, IO_PORT_RESET); diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index 0c2018bfe3b..60ff65529ab 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -66,13 +66,13 @@ static int timer_pre_probe(struct udevice *dev) err = clk_get_by_index(dev, 0, &timer_clk); if (!err) { ret = clk_get_rate(&timer_clk); - if (IS_ERR_VALUE(ret)) - return ret; - uc_priv->clock_rate = ret; - } else { - uc_priv->clock_rate = - dev_read_u32_default(dev, "clock-frequency", 0); + if (!IS_ERR_VALUE(ret)) { + uc_priv->clock_rate = ret; + return 0; + } } + + uc_priv->clock_rate = dev_read_u32_default(dev, "clock-frequency", 0); } return 0; diff --git a/drivers/tpm/tpm2_tis_core.c b/drivers/tpm/tpm2_tis_core.c index 985a8162198..81b9210056d 100644 --- a/drivers/tpm/tpm2_tis_core.c +++ b/drivers/tpm/tpm2_tis_core.c @@ -224,9 +224,6 @@ int tpm_tis_send(struct udevice *dev, const u8 *buf, size_t len) u8 status; int ret; - if (!chip) - return -ENODEV; - ret = tpm_tis_request_locality(dev, 0); if (ret < 0) return -EBUSY; diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig index 0e0cc58e3d6..7da46faed6b 100644 --- a/drivers/ufs/Kconfig +++ b/drivers/ufs/Kconfig @@ -2,7 +2,7 @@ menu "UFS Host Controller Support" config UFS bool "Support UFS controllers" - depends on DM_SCSI + depends on SCSI select CHARSET help This selects support for Universal Flash Subsystem (UFS). @@ -15,6 +15,17 @@ config CADENCE_UFS This selects the platform driver for the Cadence UFS host controller present on present TI's J721e devices. +config UFS_PCI + bool "PCI bus based UFS Controller support" + depends on PCI && UFS + help + This selects the PCI UFS Host Controller Interface. Select this if + you have UFS Host Controller with PCI Interface. + + If you have a controller with this interface, say Y here. + + If unsure, say N. + config TI_J721E_UFS bool "Glue Layer driver for UFS on TI J721E devices" help diff --git a/drivers/ufs/Makefile b/drivers/ufs/Makefile index 56a4b0776d3..67c42621aba 100644 --- a/drivers/ufs/Makefile +++ b/drivers/ufs/Makefile @@ -6,4 +6,5 @@ obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o obj-$(CONFIG_CADENCE_UFS) += cdns-platform.o obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o +obj-$(CONFIG_UFS_PCI) += ufs-pci.o obj-$(CONFIG_UFS_RENESAS) += ufs-renesas.o diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c index 9202b53989d..d1f346937c5 100644 --- a/drivers/ufs/cdns-platform.c +++ b/drivers/ufs/cdns-platform.c @@ -13,11 +13,10 @@ #include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/err.h> +#include <linux/time.h> #include "ufs.h" -#define USEC_PER_SEC 1000000L - #define CDNS_UFS_REG_HCLKDIV 0xFC #define CDNS_UFS_REG_PHY_XCFGD1 0x113C diff --git a/drivers/ufs/ufs-pci.c b/drivers/ufs/ufs-pci.c new file mode 100644 index 00000000000..ad41358727a --- /dev/null +++ b/drivers/ufs/ufs-pci.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 tinylab.org + * Author: Bin Meng <bmeng@tinylab.org> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <pci.h> +#include <ufs.h> +#include <dm/device_compat.h> +#include "ufs.h" + +static int ufs_pci_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + + return ufs_scsi_bind(dev, &scsi_dev); +} + +static int ufs_pci_probe(struct udevice *dev) +{ + int err; + + err = ufshcd_probe(dev, NULL); + if (err) + dev_err(dev, "%s failed (ret=%d)\n", __func__, err); + + return err; +} + +U_BOOT_DRIVER(ufs_pci) = { + .name = "ufs_pci", + .id = UCLASS_UFS, + .bind = ufs_pci_bind, + .probe = ufs_pci_probe, +}; + +static struct pci_device_id ufs_supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_UFS) }, + {}, +}; + +U_BOOT_PCI_DEVICE(ufs_pci, ufs_supported); diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c index e6478a9209b..92fcdf4e6cb 100644 --- a/drivers/ufs/ufs-uclass.c +++ b/drivers/ufs/ufs-uclass.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /** - * ufs-uclass.c - Universal Flash Subsystem (UFS) Uclass driver + * ufs-uclass.c - Universal Flash Storage (UFS) Uclass driver * * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index 346f0fd916f..e4400f319a7 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /** - * ufs.c - Universal Flash Subsystem (UFS) driver + * ufs.c - Universal Flash Storage (UFS) driver * * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported * to u-boot. @@ -320,7 +320,7 @@ static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 0); if (err) { - dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", + dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n", __func__, peer, i, err); break; } @@ -441,7 +441,7 @@ static int ufshcd_make_hba_operational(struct ufs_hba *hba) ufshcd_enable_run_stop_reg(hba); } else { dev_err(hba->dev, - "Host controller not ready to process requests"); + "Host controller not ready to process requests\n"); err = -EIO; goto out; } @@ -930,7 +930,7 @@ static int ufshcd_copy_query_response(struct ufs_hba *hba) memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); } else { dev_warn(hba->dev, - "%s: Response size is bigger than buffer", + "%s: Response size is bigger than buffer\n", __func__); return -EINVAL; } @@ -1179,11 +1179,11 @@ static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id, &header_len); if (ret) { - dev_err(hba->dev, "%s: Failed to get descriptor header id %d", + dev_err(hba->dev, "%s: Failed to get descriptor header id %d\n", __func__, desc_id); return ret; } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) { - dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch", + dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch\n", __func__, header[QUERY_DESC_DESC_TYPE_OFFSET], desc_id); ret = -EINVAL; @@ -1302,7 +1302,7 @@ int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, /* Sanity checks */ if (ret || !buff_len) { - dev_err(hba->dev, "%s: Failed to get full descriptor length", + dev_err(hba->dev, "%s: Failed to get full descriptor length\n", __func__); return ret; } @@ -1323,14 +1323,14 @@ int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, &buff_len); if (ret) { - dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d", + dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", __func__, desc_id, desc_index, param_offset, ret); goto out; } /* Sanity check */ if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { - dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header", + dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); ret = -EINVAL; goto out; @@ -1914,6 +1914,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev); struct scsi_plat *scsi_plat; struct udevice *scsi_dev; + void __iomem *mmio_base; int err; device_find_first_child(ufs_dev, &scsi_dev); @@ -1927,7 +1928,14 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) hba->dev = ufs_dev; hba->ops = hba_ops; - hba->mmio_base = dev_read_addr_ptr(ufs_dev); + + if (device_is_on_pci_bus(ufs_dev)) { + mmio_base = dm_pci_map_bar(ufs_dev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); + } else { + mmio_base = dev_read_addr_ptr(ufs_dev); + } + hba->mmio_base = mmio_base; /* Set descriptor lengths to specification defaults */ ufshcd_def_desc_sizes(hba); @@ -1945,7 +1953,8 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) hba->version != UFSHCI_VERSION_11 && hba->version != UFSHCI_VERSION_20 && hba->version != UFSHCI_VERSION_21 && - hba->version != UFSHCI_VERSION_30) + hba->version != UFSHCI_VERSION_30 && + hba->version != UFSHCI_VERSION_31) dev_err(hba->dev, "invalid UFS version 0x%x\n", hba->version); diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index 9daaf03d222..816a5ce0caf 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -782,6 +782,7 @@ enum { UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */ + UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */ }; /* Interrupt disable masks */ diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c index 92a7941ed15..2e44aadea47 100644 --- a/drivers/usb/cdns3/cdns3-ti.c +++ b/drivers/usb/cdns3/cdns3-ti.c @@ -6,7 +6,6 @@ */ #include <common.h> -#include <asm-generic/io.h> #include <clk.h> #include <dm.h> #include <dm/device_compat.h> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 3aec8b0d941..4b4fcd8a22e 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -31,6 +31,7 @@ #include <linux/usb/gadget.h> #include <linux/bitfield.h> #include <linux/math64.h> +#include <linux/time.h> #include "core.h" #include "gadget.h" @@ -38,8 +39,6 @@ #include "linux-compat.h" -#define NSEC_PER_SEC 1000000000L - static LIST_HEAD(dwc3_list); /* -------------------------------------------------------------------------- */ diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index e0356e653fc..196035215a6 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -8,13 +8,13 @@ #include <common.h> #include <log.h> -#include <asm-generic/io.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <dwc3-uboot.h> #include <generic-phy.h> #include <linux/delay.h> +#include <linux/io.h> #include <linux/printk.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index d56f2747b63..cbe8aaa005b 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -8,12 +8,12 @@ #define DEBUG #include <common.h> -#include <asm-generic/io.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <dwc3-uboot.h> #include <generic-phy.h> +#include <linux/io.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <malloc.h> diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 4eccc5e3370..c72a8047635 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -17,6 +17,7 @@ menuconfig USB_GADGET bool "USB Gadget Support" depends on DM select DM_USB + imply CMD_BIND help USB is a master/slave protocol, organized with one master host (such as a PC) controlling up to 127 peripheral devices. diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 1d17331cb03..c725aed3f62 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -327,6 +327,7 @@ struct fsg_common { unsigned int short_packet_received:1; unsigned int bad_lun_okay:1; unsigned int running:1; + unsigned int eject:1; int thread_wakeup_needed; struct completion thread_notifier; @@ -669,6 +670,10 @@ static int sleep_thread(struct fsg_common *common) } if (k == 10) { + /* Handle START-STOP UNIT */ + if (common->eject) + return -EPIPE; + /* Handle CTRL+C */ if (ctrlc()) return -EPIPE; @@ -1325,6 +1330,8 @@ static int do_start_stop(struct fsg_common *common) return -EINVAL; } + common->eject = 1; + return 0; } diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index ee9384fb37e..ca2760c00d0 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -744,7 +744,7 @@ static ulong sdp_load_read(struct spl_load_info *load, ulong sector, { debug("%s: sector %lx, count %lx, buf %lx\n", __func__, sector, count, (ulong)buf); - memcpy(buf, (void *)(load->dev + sector), count); + memcpy(buf, (void *)(load->priv + sector), count); return count; } @@ -844,8 +844,8 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.dev = header; - load.bl_len = 1; + load.priv = header; + spl_set_bl_len(&load, 1); load.read = sdp_load_read; spl_load_simple_fit(spl_image, &load, 0, header); @@ -857,8 +857,8 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, valid_container_hdr((void *)header)) { struct spl_load_info load; - load.dev = header; - load.bl_len = 1; + load.priv = header; + spl_set_bl_len(&load, 1); load.read = sdp_load_read; spl_load_imx_container(spl_image, &load, 0); return SDP_EXIT; diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index eb0b35969ce..ba658d92296 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -323,6 +323,7 @@ err1: int usb_gadget_probe_driver(struct usb_gadget_driver *driver) { struct usb_udc *udc = NULL; + unsigned int udc_count = 0; int ret; if (!driver || !driver->bind || !driver->setup) @@ -330,12 +331,22 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver) mutex_lock(&udc_lock); list_for_each_entry(udc, &udc_list, list) { + udc_count++; + /* For now we take the first one */ if (!udc->driver) goto found; } - printf("couldn't find an available UDC\n"); + if (!udc_count) + printf("No UDC available in the system\n"); + else + /* When this happens, users should 'unbind <class> <index>' + * using the output of 'dm tree' and looking at the line right + * after the USB peripheral/device controller. + */ + printf("All UDCs in use (%d available), use the unbind command\n", + udc_count); mutex_unlock(&udc_lock); return -ENODEV; found: diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h index 72a53656321..19b12f36a5c 100644 --- a/drivers/usb/musb-new/musb_io.h +++ b/drivers/usb/musb-new/musb_io.h @@ -14,31 +14,7 @@ #ifndef __MUSB_LINUX_PLATFORM_ARCH_H__ #define __MUSB_LINUX_PLATFORM_ARCH_H__ -#ifndef __UBOOT__ #include <linux/io.h> -#else -#include <asm/io.h> -#endif - -#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \ - && !defined(CONFIG_PPC32) \ - && !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \ - && !defined(CONFIG_M68K) -static inline void readsl(const void __iomem *addr, void *buf, int len) - { insl((unsigned long)addr, buf, len); } -static inline void readsw(const void __iomem *addr, void *buf, int len) - { insw((unsigned long)addr, buf, len); } -static inline void readsb(const void __iomem *addr, void *buf, int len) - { insb((unsigned long)addr, buf, len); } - -static inline void writesl(const void __iomem *addr, const void *buf, int len) - { outsl((unsigned long)addr, buf, len); } -static inline void writesw(const void __iomem *addr, const void *buf, int len) - { outsw((unsigned long)addr, buf, len); } -static inline void writesb(const void __iomem *addr, const void *buf, int len) - { outsb((unsigned long)addr, buf, len); } - -#endif /* NOTE: these offsets are all in bytes */ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index ab927641bb7..6f319ba0d54 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -180,7 +180,6 @@ config CONSOLE_ROTATION config CONSOLE_TRUETYPE bool "Support a console that uses TrueType fonts" - select CMD_SELECT_FONT help TrueTrype fonts can provide outline-drawing capability rather than needing to provide a bitmap for each font and size that is needed. diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c index 22fef7e8825..a7e0784596a 100644 --- a/drivers/video/dw_mipi_dsi.c +++ b/drivers/video/dw_mipi_dsi.c @@ -22,6 +22,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/iopoll.h> +#include <linux/time.h> #include <video_bridge.h> #define HWVER_131 0x31333100 /* IP version 1.31 */ @@ -214,8 +215,6 @@ #define PHY_STATUS_TIMEOUT_US 10000 #define CMD_PKT_STATUS_TIMEOUT_US 20000 -#define MSEC_PER_SEC 1000 - struct dw_mipi_dsi { struct mipi_dsi_host dsi_host; struct mipi_dsi_device *device; diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index 1a5ab781e3f..5e75b6ec68c 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -30,12 +30,11 @@ #include <asm/io.h> #include <dm/device-internal.h> #include <linux/bitops.h> +#include <linux/time.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/hardware.h> -#define USEC_PER_SEC 1000000L - /* * DSI wrapper registers & bit definitions * Note: registers are named as in the Reference Manual diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 6fd90e33919..4f60ba8ebee 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -495,6 +495,33 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr) setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN); } +#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY) +static int stm32_ltdc_alloc_fb(struct udevice *dev) +{ + u32 sdram_size = gd->ram_size; + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + phys_addr_t cpu; + dma_addr_t bus; + u64 dma_size; + int ret; + + ret = dev_get_dma_range(dev, &cpu, &bus, &dma_size); + if (ret) { + dev_err(dev, "failed to get dma address\n"); + return ret; + } + + uc_plat->base = bus + sdram_size - ALIGN(uc_plat->size, uc_plat->align); + return 0; +} +#else +static inline int stm32_ltdc_alloc_fb(struct udevice *dev) +{ + /* Delegate framebuffer allocation to video-uclass */ + return 0; +} +#endif + static int stm32_ltdc_probe(struct udevice *dev) { struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); @@ -605,6 +632,10 @@ static int stm32_ltdc_probe(struct udevice *dev) priv->crop_h = timings.vactive.typ; priv->alpha = 0xFF; + ret = stm32_ltdc_alloc_fb(dev); + if (ret) + return ret; + dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n", timings.hactive.typ, timings.vactive.typ, VNBITS(priv->l2bpp), uc_plat->base); diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index b4cf4fad5eb..a48f9c85d0f 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -14,6 +14,7 @@ #include <panel.h> #include <linux/delay.h> #include <linux/err.h> +#include <linux/time.h> #include <power/regulator.h> #include <asm/gpio.h> @@ -24,9 +25,6 @@ #include "mipi-phy.h" -#define USEC_PER_SEC 1000000L -#define NSEC_PER_SEC 1000000000L - struct tegra_dsi_priv { struct mipi_dsi_host host; struct mipi_dsi_device device; diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index 852f6735b60..1de68867d52 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -56,7 +56,7 @@ config VIRTIO_SANDBOX config VIRTIO_NET bool "virtio net driver" - depends on VIRTIO + depends on VIRTIO && NETDEVICES help This is the virtual net driver for virtio. It can be used with QEMU based targets. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 07fc4940e91..569726119ca 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -344,6 +344,13 @@ config WDT_STM32MP Enable the STM32 watchdog (IWDG) driver. Enable support to configure STM32's on-SoC watchdog. +config WDT_STARFIVE + bool "StarFive watchdog timer support" + depends on WDT + imply WATCHDOG + help + Enable support for the watchdog timer of StarFive JH7110 SoC. + config WDT_SUNXI bool "Allwinner sunxi watchdog timer support" depends on WDT && ARCH_SUNXI diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index eef786f5e74..5520d3d9ae8 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o +obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c new file mode 100644 index 00000000000..ee9ec4cdc3a --- /dev/null +++ b/drivers/watchdog/starfive_wdt.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Starfive Watchdog driver + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include <clk.h> +#include <dm.h> +#include <reset.h> +#include <wdt.h> +#include <linux/iopoll.h> + +/* JH7110 Watchdog register define */ +#define STARFIVE_WDT_JH7110_LOAD 0x000 +#define STARFIVE_WDT_JH7110_VALUE 0x004 +#define STARFIVE_WDT_JH7110_CONTROL 0x008 /* + * [0]: reset enable; + * [1]: interrupt enable && watchdog enable + * [31:2]: reserved. + */ +#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */ +#define STARFIVE_WDT_JH7110_IMS 0x014 +#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */ + +/* WDOGCONTROL */ +#define STARFIVE_WDT_ENABLE 0x1 +#define STARFIVE_WDT_EN_SHIFT 0 +#define STARFIVE_WDT_RESET_EN 0x1 +#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1 + +/* WDOGLOCK */ +#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551 + +/* WDOGINTCLR */ +#define STARFIVE_WDT_INTCLR 0x1 +#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */ + +#define STARFIVE_WDT_MAXCNT 0xffffffff +#define STARFIVE_WDT_DEFAULT_TIME (15) +#define STARFIVE_WDT_DELAY_US 0 +#define STARFIVE_WDT_TIMEOUT_US 10000 + +/* module parameter */ +#define STARFIVE_WDT_EARLY_ENA 0 + +struct starfive_wdt_variant { + unsigned int control; /* Watchdog Control Resgister for reset enable */ + unsigned int load; /* Watchdog Load register */ + unsigned int reload; /* Watchdog Reload Control register */ + unsigned int enable; /* Watchdog Enable Register */ + unsigned int value; /* Watchdog Counter Value Register */ + unsigned int int_clr; /* Watchdog Interrupt Clear Register */ + unsigned int unlock; /* Watchdog Lock Register */ + unsigned int int_status; /* Watchdog Interrupt Status Register */ + + u32 unlock_key; + char enrst_shift; + char en_shift; + bool intclr_check; /* whether need to check it before clearing interrupt */ + char intclr_ava_shift; + bool double_timeout; /* The watchdog need twice timeout to reboot */ +}; + +struct starfive_wdt_priv { + void __iomem *base; + struct clk *core_clk; + struct clk *apb_clk; + struct reset_ctl_bulk *rst; + const struct starfive_wdt_variant *variant; + unsigned long freq; + u32 count; /* count of timeout */ + u32 reload; /* restore the count */ +}; + +/* Register layout and configuration for the JH7110 */ +static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = { + .control = STARFIVE_WDT_JH7110_CONTROL, + .load = STARFIVE_WDT_JH7110_LOAD, + .enable = STARFIVE_WDT_JH7110_CONTROL, + .value = STARFIVE_WDT_JH7110_VALUE, + .int_clr = STARFIVE_WDT_JH7110_INTCLR, + .unlock = STARFIVE_WDT_JH7110_LOCK, + .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY, + .int_status = STARFIVE_WDT_JH7110_IMS, + .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT, + .en_shift = STARFIVE_WDT_EN_SHIFT, + .intclr_check = false, + .double_timeout = true, +}; + +static int starfive_wdt_enable_clock(struct starfive_wdt_priv *wdt) +{ + int ret; + + ret = clk_enable(wdt->apb_clk); + if (ret) + return ret; + + ret = clk_enable(wdt->core_clk); + if (ret) { + clk_disable(wdt->apb_clk); + return ret; + } + + return 0; +} + +static void starfive_wdt_disable_clock(struct starfive_wdt_priv *wdt) +{ + clk_disable(wdt->core_clk); + clk_disable(wdt->apb_clk); +} + +/* Write unlock-key to unlock. Write other value to lock. */ +static void starfive_wdt_unlock(struct starfive_wdt_priv *wdt) +{ + writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); +} + +static void starfive_wdt_lock(struct starfive_wdt_priv *wdt) +{ + writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); +} + +/* enable watchdog interrupt to reset/reboot */ +static void starfive_wdt_enable_reset(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->control); + val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift; + writel(val, wdt->base + wdt->variant->control); +} + +/* waiting interrupt can be free to clear */ +static int starfive_wdt_wait_int_free(struct starfive_wdt_priv *wdt) +{ + u32 value; + + return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value, + !(value & BIT(wdt->variant->intclr_ava_shift)), + STARFIVE_WDT_TIMEOUT_US); +} + +/* clear interrupt signal before initialization or reload */ +static int starfive_wdt_int_clr(struct starfive_wdt_priv *wdt) +{ + int ret; + + if (wdt->variant->intclr_check) { + ret = starfive_wdt_wait_int_free(wdt); + if (ret) + return ret; + } + writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr); + + return 0; +} + +static inline void starfive_wdt_set_count(struct starfive_wdt_priv *wdt, + u32 val) +{ + writel(val, wdt->base + wdt->variant->load); +} + +/* enable watchdog */ +static inline void starfive_wdt_enable(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->enable); + val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift; + writel(val, wdt->base + wdt->variant->enable); +} + +/* disable watchdog */ +static inline void starfive_wdt_disable(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->enable); + val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift); + writel(val, wdt->base + wdt->variant->enable); +} + +static inline void starfive_wdt_set_reload_count(struct starfive_wdt_priv *wdt, + u32 count) +{ + starfive_wdt_set_count(wdt, count); + + /* 7100 need set any value to reload register and could reload value to counter */ + if (wdt->variant->reload) + writel(0x1, wdt->base + wdt->variant->reload); +} + +static int starfive_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + int ret; + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + /* disable watchdog, to be safe */ + starfive_wdt_disable(wdt); + + starfive_wdt_enable_reset(wdt); + ret = starfive_wdt_int_clr(wdt); + if (ret) + goto exit; + + wdt->count = (timeout_ms / 1000) * wdt->freq; + if (wdt->variant->double_timeout) + wdt->count /= 2; + + starfive_wdt_set_count(wdt, wdt->count); + starfive_wdt_enable(wdt); + +exit: + starfive_wdt_lock(wdt); + return ret; +} + +static int starfive_wdt_stop(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + starfive_wdt_disable(wdt); + starfive_wdt_lock(wdt); + + return 0; +} + +static int starfive_wdt_reset(struct udevice *dev) +{ + int ret; + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + ret = starfive_wdt_int_clr(wdt); + if (ret) + goto exit; + + starfive_wdt_set_reload_count(wdt, wdt->count); + +exit: + starfive_wdt_lock(wdt); + + return ret; +} + +static const struct wdt_ops starfive_wdt_ops = { + .start = starfive_wdt_start, + .stop = starfive_wdt_stop, + .reset = starfive_wdt_reset, +}; + +static int starfive_wdt_probe(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + int ret; + + ret = starfive_wdt_enable_clock(wdt); + if (ret) + return ret; + + ret = reset_deassert_bulk(wdt->rst); + if (ret) + goto err_reset; + + wdt->variant = (const struct starfive_wdt_variant *)dev_get_driver_data(dev); + + wdt->freq = clk_get_rate(wdt->core_clk); + if (!wdt->freq) { + ret = -EINVAL; + goto err_get_freq; + } + + return 0; + +err_get_freq: + reset_assert_bulk(wdt->rst); +err_reset: + starfive_wdt_disable_clock(wdt); + + return ret; +} + +static int starfive_wdt_of_to_plat(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + wdt->base = (void *)dev_read_addr(dev); + if (!wdt->base) + return -ENODEV; + + wdt->apb_clk = devm_clk_get(dev, "apb"); + if (IS_ERR(wdt->apb_clk)) + return -ENODEV; + + wdt->core_clk = devm_clk_get(dev, "core"); + if (IS_ERR(wdt->core_clk)) + return -ENODEV; + + wdt->rst = devm_reset_bulk_get(dev); + if (IS_ERR(wdt->rst)) + return -ENODEV; + + return 0; +} + +static const struct udevice_id starfive_wdt_ids[] = { + { + .compatible = "starfive,jh7110-wdt", + .data = (ulong)&starfive_wdt_jh7110_variant + }, { + /* sentinel */ + } +}; + +U_BOOT_DRIVER(starfive_wdt) = { + .name = "starfive_wdt", + .id = UCLASS_WDT, + .of_match = starfive_wdt_ids, + .priv_auto = sizeof(struct starfive_wdt_priv), + .probe = starfive_wdt_probe, + .of_to_plat = starfive_wdt_of_to_plat, + .ops = &starfive_wdt_ops, +}; diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c index b40a1d29caa..8eeac935760 100644 --- a/drivers/watchdog/sunxi_wdt.c +++ b/drivers/watchdog/sunxi_wdt.c @@ -9,8 +9,7 @@ #include <wdt.h> #include <asm/io.h> #include <linux/delay.h> - -#define MSEC_PER_SEC 1000 +#include <linux/time.h> #define WDT_MAX_TIMEOUT 16 #define WDT_TIMEOUT_MASK 0xf diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c index 4ad548d599d..1df04e239ad 100644 --- a/drivers/xen/pvblock.c +++ b/drivers/xen/pvblock.c @@ -632,7 +632,8 @@ static ulong pvblock_iop(struct udevice *udev, lbaint_t blknr, memcpy(blk_dev->bounce_buffer, buffer, desc->blksz); aiocb.aio_nbytes = unaligned ? desc->blksz : - min((size_t)(BLKIF_MAX_SEGMENTS_PER_REQUEST * PAGE_SIZE), + min((size_t)((BLKIF_MAX_SEGMENTS_PER_REQUEST - 1) + * PAGE_SIZE), (size_t)(blocks_todo * desc->blksz)); blkfront_io(&aiocb, write); diff --git a/env/common.c b/env/common.c index eb1a9137953..656748c1f5b 100644 --- a/env/common.c +++ b/env/common.c @@ -37,11 +37,116 @@ struct hsearch_data env_htab = { }; /* - * This env_set() function is defined in cmd/nvedit.c, since it calls - * _do_env_set(), whis is a static function in that file. - * - * int env_set(const char *varname, const char *varvalue); + * This variable is incremented each time we set an environment variable so we + * can be check via env_get_id() to see if the environment has changed or not. + * This makes it possible to reread an environment variable only if the + * environment was changed, typically used by networking code. */ +static int env_id = 1; + +int env_get_id(void) +{ + return env_id; +} + +void env_inc_id(void) +{ + env_id++; +} + +int env_do_env_set(int flag, int argc, char *const argv[], int env_flag) +{ + int i, len; + char *name, *value, *s; + struct env_entry e, *ep; + + debug("Initial value for argc=%d\n", argc); + +#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_CMD_NVEDIT_EFI) + if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e') + return do_env_set_efi(NULL, flag, --argc, ++argv); +#endif + + while (argc > 1 && **(argv + 1) == '-') { + char *arg = *++argv; + + --argc; + while (*++arg) { + switch (*arg) { + case 'f': /* force */ + env_flag |= H_FORCE; + break; + default: + return CMD_RET_USAGE; + } + } + } + debug("Final value for argc=%d\n", argc); + name = argv[1]; + + if (strchr(name, '=')) { + printf("## Error: illegal character '='" + "in variable name \"%s\"\n", name); + return 1; + } + + env_inc_id(); + + /* Delete only ? */ + if (argc < 3 || argv[2] == NULL) { + int rc = hdelete_r(name, &env_htab, env_flag); + + /* If the variable didn't exist, don't report an error */ + return rc && rc != -ENOENT ? 1 : 0; + } + + /* + * Insert / replace new value + */ + for (i = 2, len = 0; i < argc; ++i) + len += strlen(argv[i]) + 1; + + value = malloc(len); + if (value == NULL) { + printf("## Can't malloc %d bytes\n", len); + return 1; + } + for (i = 2, s = value; i < argc; ++i) { + char *v = argv[i]; + + while ((*s++ = *v++) != '\0') + ; + *(s - 1) = ' '; + } + if (s != value) + *--s = '\0'; + + e.key = name; + e.data = value; + hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag); + free(value); + if (!ep) { + printf("## Error inserting \"%s\" variable, errno=%d\n", + name, errno); + return 1; + } + + return 0; +} + +int env_set(const char *varname, const char *varvalue) +{ + const char * const argv[4] = { "setenv", varname, varvalue, NULL }; + + /* before import into hashtable */ + if (!(gd->flags & GD_FLG_ENV_READY)) + return 1; + + if (varvalue == NULL || varvalue[0] == '\0') + return env_do_env_set(0, 2, (char * const *)argv, H_PROGRAMMATIC); + else + return env_do_env_set(0, 3, (char * const *)argv, H_PROGRAMMATIC); +} /** * Set an environment variable to an integer value diff --git a/env/ext4.c b/env/ext4.c index 47e05a48919..da26705b8da 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -77,7 +77,7 @@ static int env_ext4_save_buffer(env_t *env_new) dev = dev_desc->devnum; ext4fs_set_blk_dev(dev_desc, &info); - if (!ext4fs_mount(info.size)) { + if (!ext4fs_mount()) { printf("\n** Unable to use %s %s for saveenv **\n", ifname, dev_and_part); return 1; @@ -160,7 +160,7 @@ static int env_ext4_load(void) dev = dev_desc->devnum; ext4fs_set_blk_dev(dev_desc, &info); - if (!ext4fs_mount(info.size)) { + if (!ext4fs_mount()) { printf("\n** Unable to use %s %s for loading the env **\n", ifname, dev_and_part); goto err_env_relocate; diff --git a/env/mmc.c b/env/mmc.c index cb14bbb58f1..da84cddd74f 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -495,7 +495,7 @@ U_BOOT_ENV_LOCATION(mmc) = { .location = ENVL_MMC, ENV_NAME("MMC") .load = env_mmc_load, -#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_SPL_BUILD) .save = env_save_ptr(env_mmc_save), .erase = ENV_ERASE_PTR(env_mmc_erase) #endif diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c index 4cdbbbe3d06..1149a3b2007 100644 --- a/fs/btrfs/btrfs.c +++ b/fs/btrfs/btrfs.c @@ -228,7 +228,7 @@ int btrfs_read(const char *file, void *buf, loff_t offset, loff_t len, { struct btrfs_fs_info *fs_info = current_fs_info; struct btrfs_root *root; - loff_t real_size = 0; + loff_t real_size; u64 ino; u8 type; int ret; @@ -246,16 +246,13 @@ int btrfs_read(const char *file, void *buf, loff_t offset, loff_t len, return -EINVAL; } - if (!len) { - ret = btrfs_size(file, &real_size); - if (ret < 0) { - error("Failed to get inode size: %s", file); - return ret; - } - len = real_size; + ret = btrfs_size(file, &real_size); + if (ret < 0) { + error("Failed to get inode size: %s", file); + return ret; } - if (len > real_size - offset) + if (!len || len > real_size - offset) len = real_size - offset; ret = btrfs_file_read(root, ino, offset, len, buf); diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index f50de7c089e..ea9b92298ba 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -2368,7 +2368,7 @@ fail: return -1; } -int ext4fs_mount(unsigned part_length) +int ext4fs_mount(void) { struct ext2_data *data; int status; diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 4c89152ce4a..3b12ec54fa2 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -233,7 +233,7 @@ int ext4fs_probe(struct blk_desc *fs_dev_desc, { ext4fs_set_blk_dev(fs_dev_desc, fs_partition); - if (!ext4fs_mount(fs_partition->size)) { + if (!ext4fs_mount()) { ext4fs_close(); return -1; } diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 8ff1fd0ec83..14e53cf2d5a 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -18,12 +18,17 @@ #include <fs.h> #include <log.h> #include <asm/byteorder.h> +#include <asm/unaligned.h> #include <part.h> #include <malloc.h> #include <memalign.h> #include <asm/cache.h> #include <linux/compiler.h> #include <linux/ctype.h> +#include <linux/log2.h> + +/* maximum number of clusters for FAT12 */ +#define MAX_FAT12 0xFF4 /* * Convert a string to lowercase. Converts at most 'len' characters, @@ -484,6 +489,73 @@ static __u8 mkcksum(struct nameext *nameext) } /* + * Determine if the FAT type is FAT12 or FAT16 + * + * Based on fat_fill_super() from the Linux kernel's fs/fat/inode.c + */ +static int determine_legacy_fat_bits(const boot_sector *bs) +{ + u16 fat_start = bs->reserved; + u32 dir_start = fat_start + bs->fats * bs->fat_length; + u32 rootdir_sectors = get_unaligned_le16(bs->dir_entries) * + sizeof(dir_entry) / + get_unaligned_le16(bs->sector_size); + u32 data_start = dir_start + rootdir_sectors; + u16 sectors = get_unaligned_le16(bs->sectors); + u32 total_sectors = sectors ? sectors : bs->total_sect; + u32 total_clusters = (total_sectors - data_start) / + bs->cluster_size; + + return (total_clusters > MAX_FAT12) ? 16 : 12; +} + +/* + * Determines if the boot sector's media field is valid + * + * Based on fat_valid_media() from Linux kernel's include/linux/msdos_fs.h + */ +static int fat_valid_media(u8 media) +{ + return media >= 0xf8 || media == 0xf0; +} + +/* + * Determines if the given boot sector is valid + * + * Based on fat_read_bpb() from the Linux kernel's fs/fat/inode.c + */ +static int is_bootsector_valid(const boot_sector *bs) +{ + u16 sector_size = get_unaligned_le16(bs->sector_size); + u16 dir_per_block = sector_size / sizeof(dir_entry); + + if (!bs->reserved) + return 0; + + if (!bs->fats) + return 0; + + if (!fat_valid_media(bs->media)) + return 0; + + if (!is_power_of_2(sector_size) || + sector_size < 512 || + sector_size > 4096) + return 0; + + if (!is_power_of_2(bs->cluster_size)) + return 0; + + if (!bs->fat_length && !bs->fat32_length) + return 0; + + if (get_unaligned_le16(bs->dir_entries) & (dir_per_block - 1)) + return 0; + + return 1; +} + +/* * Read boot sector and volume info from a FAT filesystem */ static int @@ -506,7 +578,8 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) if (disk_read(0, 1, block) < 0) { debug("Error: reading block\n"); - goto fail; + ret = -1; + goto out_free; } memcpy(bs, block, sizeof(boot_sector)); @@ -516,8 +589,14 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) bs->heads = FAT2CPU16(bs->heads); bs->total_sect = FAT2CPU32(bs->total_sect); + if (!is_bootsector_valid(bs)) { + debug("Error: bootsector is invalid\n"); + ret = -1; + goto out_free; + } + /* FAT32 entries */ - if (bs->fat_length == 0) { + if (!bs->fat_length && bs->fat32_length) { /* Assume FAT32 */ bs->fat32_length = FAT2CPU32(bs->fat32_length); bs->flags = FAT2CPU16(bs->flags); @@ -528,28 +607,11 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) *fatsize = 32; } else { vistart = (volume_info *)&(bs->fat32_length); - *fatsize = 0; + *fatsize = determine_legacy_fat_bits(bs); } memcpy(volinfo, vistart, sizeof(volume_info)); - if (*fatsize == 32) { - if (strncmp(FAT32_SIGN, vistart->fs_type, SIGNLEN) == 0) - goto exit; - } else { - if (strncmp(FAT12_SIGN, vistart->fs_type, SIGNLEN) == 0) { - *fatsize = 12; - goto exit; - } - if (strncmp(FAT16_SIGN, vistart->fs_type, SIGNLEN) == 0) { - *fatsize = 16; - goto exit; - } - } - - debug("Error: broken fs_type sign\n"); -fail: - ret = -1; -exit: +out_free: free(block); return ret; } @@ -571,7 +633,7 @@ static int get_fs_info(fsdata *mydata) mydata->total_sect = bs.total_sect; } else { mydata->fatlength = bs.fat_length; - mydata->total_sect = (bs.sectors[1] << 8) + bs.sectors[0]; + mydata->total_sect = get_unaligned_le16(bs.sectors); if (!mydata->total_sect) mydata->total_sect = bs.total_sect; } @@ -583,7 +645,7 @@ static int get_fs_info(fsdata *mydata) mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats; - mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0]; + mydata->sect_size = get_unaligned_le16(bs.sector_size); mydata->clust_size = bs.cluster_size; if (mydata->sect_size != cur_part_info.blksz) { log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n", @@ -607,8 +669,7 @@ static int get_fs_info(fsdata *mydata) (mydata->clust_size * 2); mydata->root_cluster = bs.root_cluster; } else { - mydata->rootdir_size = ((bs.dir_entries[1] * (int)256 + - bs.dir_entries[0]) * + mydata->rootdir_size = (get_unaligned_le16(bs.dir_entries) * sizeof(dir_entry)) / mydata->sect_size; mydata->data_begin = mydata->rootdir_sect + @@ -1157,9 +1218,8 @@ int file_fat_detectfs(void) memcpy(vol_label, volinfo.volume_label, 11); vol_label[11] = '\0'; - volinfo.fs_type[5] = '\0'; - printf("Filesystem: %s \"%s\"\n", volinfo.fs_type, vol_label); + printf("Filesystem: FAT%d \"%s\"\n", fatsize, vol_label); return 0; } @@ -749,7 +749,7 @@ int do_load(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], if (argc > 7) return CMD_RET_USAGE; - if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype)) { + if (fs_set_blk_dev(argv[1], cmd_arg2(argc, argv), fstype)) { log_err("Can't set block device\n"); return 1; } @@ -818,7 +818,7 @@ int do_ls(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], if (argc > 4) return CMD_RET_USAGE; - if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype)) + if (fs_set_blk_dev(argv[1], cmd_arg2(argc, argv), fstype)) return 1; if (fs_ls(argc >= 4 ? argv[3] : "/")) diff --git a/fs/squashfs/sqfs_decompressor.c b/fs/squashfs/sqfs_decompressor.c index 6b3e01cdad7..cfd1153fd74 100644 --- a/fs/squashfs/sqfs_decompressor.c +++ b/fs/squashfs/sqfs_decompressor.c @@ -18,6 +18,10 @@ #include <u-boot/zlib.h> #endif +#if IS_ENABLED(CONFIG_LZ4) +#include <u-boot/lz4.h> +#endif + #if IS_ENABLED(CONFIG_ZSTD) #include <linux/zstd.h> #endif @@ -38,6 +42,10 @@ int sqfs_decompressor_init(struct squashfs_ctxt *ctxt) case SQFS_COMP_ZLIB: break; #endif +#if IS_ENABLED(CONFIG_LZ4) + case SQFS_COMP_LZ4: + break; +#endif #if IS_ENABLED(CONFIG_ZSTD) case SQFS_COMP_ZSTD: ctxt->zstd_workspace = malloc(zstd_dctx_workspace_bound()); @@ -66,6 +74,10 @@ void sqfs_decompressor_cleanup(struct squashfs_ctxt *ctxt) case SQFS_COMP_ZLIB: break; #endif +#if IS_ENABLED(CONFIG_LZ4) + case SQFS_COMP_LZ4: + break; +#endif #if IS_ENABLED(CONFIG_ZSTD) case SQFS_COMP_ZSTD: free(ctxt->zstd_workspace); @@ -139,6 +151,17 @@ int sqfs_decompress(struct squashfs_ctxt *ctxt, void *dest, break; #endif +#if IS_ENABLED(CONFIG_LZ4) + case SQFS_COMP_LZ4: + ret = LZ4_decompress_safe(source, dest, src_len, *dest_len); + if (ret < 0) { + printf("LZ4 decompression failed.\n"); + return -EINVAL; + } + + ret = 0; + break; +#endif #if IS_ENABLED(CONFIG_ZSTD) case SQFS_COMP_ZSTD: ret = sqfs_zstd_decompress(ctxt, dest, *dest_len, source, src_len); diff --git a/fs/squashfs/sqfs_decompressor.h b/fs/squashfs/sqfs_decompressor.h index 892cfb69744..c48b74fdf50 100644 --- a/fs/squashfs/sqfs_decompressor.h +++ b/fs/squashfs/sqfs_decompressor.h @@ -18,41 +18,6 @@ #define SQFS_COMP_LZ4 5 #define SQFS_COMP_ZSTD 6 -/* LZMA does not support any compression options */ - -struct squashfs_gzip_opts { - u32 compression_level; - u16 window_size; - u16 strategies; -}; - -struct squashfs_xz_opts { - u32 dictionary_size; - u32 executable_filters; -}; - -struct squashfs_lz4_opts { - u32 version; - u32 flags; -}; - -struct squashfs_zstd_opts { - u32 compression_level; -}; - -struct squashfs_lzo_opts { - u32 algorithm; - u32 level; -}; - -union squashfs_compression_opts { - struct squashfs_gzip_opts *gzip; - struct squashfs_xz_opts *xz; - struct squashfs_lz4_opts *lz4; - struct squashfs_zstd_opts *zstd; - struct squashfs_lzo_opts *lzo; -}; - int sqfs_decompress(struct squashfs_ctxt *ctxt, void *dest, unsigned long *dest_len, void *source, u32 src_len); int sqfs_decompressor_init(struct squashfs_ctxt *ctxt); diff --git a/fs/squashfs/sqfs_filesystem.h b/fs/squashfs/sqfs_filesystem.h index 5440b6c0e05..be56498a5e3 100644 --- a/fs/squashfs/sqfs_filesystem.h +++ b/fs/squashfs/sqfs_filesystem.h @@ -13,7 +13,6 @@ #include <part.h> #include <stdint.h> -#define SQFS_UNCOMPRESSED_DATA 0x0002 #define SQFS_MAGIC_NUMBER 0x73717368 /* The three first members of squashfs_dir_index make a total of 12 bytes */ #define SQFS_DIR_INDEX_BASE_LENGTH 12 @@ -23,7 +22,6 @@ #define SQFS_MAX_ENTRIES 512 /* Metadata blocks start by a 2-byte length header */ #define SQFS_HEADER_SIZE 2 -#define SQFS_LREG_INODE_MIN_SIZE 56 #define SQFS_DIR_HEADER_SIZE 12 #define SQFS_MISC_ENTRY_TYPE -1 #define SQFS_EMPTY_FILE_SIZE 3 diff --git a/fs/squashfs/sqfs_utils.h b/fs/squashfs/sqfs_utils.h index 1260abe22be..41f13e8a9ec 100644 --- a/fs/squashfs/sqfs_utils.h +++ b/fs/squashfs/sqfs_utils.h @@ -15,11 +15,8 @@ #define SQFS_FRAGMENT_INDEX_OFFSET(A) ((A) % SQFS_MAX_ENTRIES) #define SQFS_FRAGMENT_INDEX(A) ((A) / SQFS_MAX_ENTRIES) #define SQFS_BLOCK_SIZE(A) ((A) & GENMASK(23, 0)) -#define SQFS_CHECK_FLAG(flag, bit) (((flag) >> (bit)) & 1) /* Useful for both fragment and data blocks */ #define SQFS_COMPRESSED_BLOCK(A) (!((A) & BIT(24))) -/* SQFS_COMPRESSED_DATA strictly used with super block's 'flags' member */ -#define SQFS_COMPRESSED_DATA(A) (!((A) & 0x0002)) #define SQFS_IS_FRAGMENTED(A) ((A) != 0xFFFFFFFF) /* * These two macros work as getters for a metada block header, retrieving the @@ -28,22 +25,4 @@ #define SQFS_COMPRESSED_METADATA(A) (!((A) & BIT(15))) #define SQFS_METADATA_SIZE(A) ((A) & GENMASK(14, 0)) -struct squashfs_super_block_flags { - /* check: unused - * uncompressed_ids: not supported - */ - bool uncompressed_inodes; - bool uncompressed_data; - bool check; - bool uncompressed_frags; - bool no_frags; - bool always_frags; - bool duplicates; - bool exportable; - bool uncompressed_xattrs; - bool no_xattrs; - bool compressor_options; - bool uncompressed_ids; -}; - #endif /* SQFS_UTILS_H */ diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 67b13c83b56..b4e761c3668 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -68,7 +68,6 @@ struct page { void iput(struct inode *inode); /* linux/include/time.h */ -#define NSEC_PER_SEC 1000000000L #define get_seconds() 0 #define CURRENT_TIME_SEC ((struct timespec) { get_seconds(), 0 }) diff --git a/include/MCD_dma.h b/include/MCD_dma.h deleted file mode 100644 index 2f16c89044e..00000000000 --- a/include/MCD_dma.h +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -#ifndef _MCD_API_H -#define _MCD_API_H - -/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */ -#undef MCD_INCLUDE_EU - -/* Number of DMA channels */ -#define NCHANNELS 16 - -/* Total number of variants */ -#ifdef MCD_INCLUDE_EU -#define NUMOFVARIANTS 6 -#else -#define NUMOFVARIANTS 4 -#endif - -/* Define sizes of the various tables */ -#define TASK_TABLE_SIZE (NCHANNELS*32) -#define VAR_TAB_SIZE (128) -#define CONTEXT_SAVE_SIZE (128) -#define FUNCDESC_TAB_SIZE (256) - -#ifdef MCD_INCLUDE_EU -#define FUNCDESC_TAB_NUM 16 -#else -#define FUNCDESC_TAB_NUM 1 -#endif - -#ifndef DEFINESONLY - -/* Portability typedefs */ -#if 1 -#include "common.h" -#else -#ifndef s32 -typedef int s32; -#endif -#ifndef u32 -typedef unsigned int u32; -#endif -#ifndef s16 -typedef short s16; -#endif -#ifndef u16 -typedef unsigned short u16; -#endif -#ifndef s8 -typedef char s8; -#endif -#ifndef u8 -typedef unsigned char u8; -#endif -#endif - -/* - * These structures represent the internal registers of the - * multi-channel DMA - */ -struct dmaRegs_s { - u32 taskbar; /* task table base address */ - u32 currPtr; - u32 endPtr; - u32 varTablePtr; - u16 dma_rsvd0; - u16 ptdControl; /* ptd control */ - u32 intPending; /* interrupt pending */ - u32 intMask; /* interrupt mask */ - u16 taskControl[16]; /* task control */ - u8 priority[32]; /* priority */ - u32 initiatorMux; /* initiator mux control */ - u32 taskSize0; /* task size control 0. */ - u32 taskSize1; /* task size control 1. */ - u32 dma_rsvd1; /* reserved */ - u32 dma_rsvd2; /* reserved */ - u32 debugComp1; /* debug comparator 1 */ - u32 debugComp2; /* debug comparator 2 */ - u32 debugControl; /* debug control */ - u32 debugStatus; /* debug status */ - u32 ptdDebug; /* priority task decode debug */ - u32 dma_rsvd3[31]; /* reserved */ -}; -typedef volatile struct dmaRegs_s dmaRegs; - -#endif - -/* PTD contrl reg bits */ -#define PTD_CTL_TSK_PRI 0x8000 -#define PTD_CTL_COMM_PREFETCH 0x0001 - -/* Task Control reg bits and field masks */ -#define TASK_CTL_EN 0x8000 -#define TASK_CTL_VALID 0x4000 -#define TASK_CTL_ALWAYS 0x2000 -#define TASK_CTL_INIT_MASK 0x1f00 -#define TASK_CTL_ASTRT 0x0080 -#define TASK_CTL_HIPRITSKEN 0x0040 -#define TASK_CTL_HLDINITNUM 0x0020 -#define TASK_CTL_ASTSKNUM_MASK 0x000f - -/* Priority reg bits and field masks */ -#define PRIORITY_HLD 0x80 -#define PRIORITY_PRI_MASK 0x07 - -/* Debug Control reg bits and field masks */ -#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 -#define DBG_CTL_AUTO_ARM 0x00008000 -#define DBG_CTL_BREAK 0x00004000 -#define DBG_CTL_COMP1_TYP_MASK 0x00003800 -#define DBG_CTL_COMP2_TYP_MASK 0x00000070 -#define DBG_CTL_EXT_BREAK 0x00000004 -#define DBG_CTL_INT_BREAK 0x00000002 - -/* - * PTD Debug reg selector addresses - * This reg must be written with a value to show the contents of - * one of the desired internal register. - */ -#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ -#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and - have initiators asserted */ - -/* General return values */ -#define MCD_OK 0 -#define MCD_ERROR -1 -#define MCD_TABLE_UNALIGNED -2 -#define MCD_CHANNEL_INVALID -3 - -/* MCD_initDma input flags */ -#define MCD_RELOC_TASKS 0x00000001 -#define MCD_NO_RELOC_TASKS 0x00000000 -#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */ - -/* - * MCD_dmaStatus Status Values for each channel: - * MCD_NO_DMA - No DMA has been requested since reset - * MCD_IDLE - DMA active, but the initiator is currently inactive - * MCD_RUNNING - DMA active, and the initiator is currently active - * MCD_PAUSED - DMA active but it is currently paused - * MCD_HALTED - the most recent DMA has been killed with MCD_killTask() - * MCD_DONE - the most recent DMA has completed - */ -#define MCD_NO_DMA 1 -#define MCD_IDLE 2 -#define MCD_RUNNING 3 -#define MCD_PAUSED 4 -#define MCD_HALTED 5 -#define MCD_DONE 6 - -/* MCD_startDma parameter defines */ - -/* Constants for the funcDesc parameter */ -/* - * MCD_NO_BYTE_SWAP - to disable byte swapping - * MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data - * MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data - * value being DMAed - * MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of - * each 32-bit data value DMAed - * MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed - * MCD_BIT_REV - reverse the bits of each byte DMAed - * MCD_CRC16 - to perform CRC-16 on DMAed data - * MCD_CRCCCITT - to perform CRC-CCITT on DMAed data - * MCD_CRC32 - to perform CRC-32 on DMAed data - * MCD_CSUMINET - to perform internet checksums on DMAed data - * MCD_NO_CSUM - to perform no checksumming - */ -#define MCD_NO_BYTE_SWAP 0x00045670 -#define MCD_BYTE_REVERSE 0x00076540 -#define MCD_U16_REVERSE 0x00067450 -#define MCD_U16_BYTE_REVERSE 0x00054760 -#define MCD_NO_BIT_REV 0x00000000 -#define MCD_BIT_REV 0x00088880 -/* CRCing: */ -#define MCD_CRC16 0xc0100000 -#define MCD_CRCCCITT 0xc0200000 -#define MCD_CRC32 0xc0300000 -#define MCD_CSUMINET 0xc0400000 -#define MCD_NO_CSUM 0xa0000000 - -#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \ - MCD_NO_CSUM) -#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) - -/* Constants for the flags parameter */ -#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ -#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ -#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */ -#define MCD_TT_FLAGS_MASK 0x000000ff -#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) - -#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ -#define MCD_CHAIN_DMA /* TBD */ -#define MCD_EU_DMA /* TBD */ -#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ -#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ - -/* these flags are valid for MCD_startDma and the chained buffer descriptors */ -/* - * MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl - * MCD_WRAP - to tell the FEC Dmas to wrap to the first BD - * MCD_INTERRUPT - to generate an interrupt after completion of the DMA - * MCD_END_FRAME - tell the DMA to end the frame when transferring - * last byte of data in buffer - * MCD_CRC_RESTART - to empty out the accumulated checksum prior to - * performing the DMA - */ -#define MCD_BUF_READY 0x80000000 -#define MCD_WRAP 0x20000000 -#define MCD_INTERRUPT 0x10000000 -#define MCD_END_FRAME 0x08000000 -#define MCD_CRC_RESTART 0x40000000 - -/* Defines for the FEC buffer descriptor control/status word*/ -#define MCD_FEC_BUF_READY 0x8000 -#define MCD_FEC_WRAP 0x2000 -#define MCD_FEC_INTERRUPT 0x1000 -#define MCD_FEC_END_FRAME 0x0800 - -/* Defines for general intuitiveness */ - -#define MCD_TRUE 1 -#define MCD_FALSE 0 - -/* Three different cases for destination and source. */ -#define MINUS1 -1 -#define ZERO 0 -#define PLUS1 1 - -#ifndef DEFINESONLY - -/* Task Table Entry struct*/ -typedef struct { - u32 TDTstart; /* task descriptor table start */ - u32 TDTend; /* task descriptor table end */ - u32 varTab; /* variable table start */ - u32 FDTandFlags; /* function descriptor table start & flags */ - volatile u32 descAddrAndStatus; - volatile u32 modifiedVarTab; - u32 contextSaveSpace; /* context save space start */ - u32 literalBases; -} TaskTableEntry; - -/* Chained buffer descriptor: - * flags - flags describing the DMA - * csumResult - checksum performed since last checksum reset - * srcAddr - the address to move data from - * destAddr - the address to move data to - * lastDestAddr - the last address written to - * dmaSize - the no of bytes to xfer independent of the xfer sz - * next - next buffer descriptor in chain - * info - private info about this descriptor; DMA does not affect it - */ -typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; -struct MCD_bufDesc_struct { - u32 flags; - u32 csumResult; - s8 *srcAddr; - s8 *destAddr; - s8 *lastDestAddr; - u32 dmaSize; - MCD_bufDesc *next; - u32 info; -}; - -/* Progress Query struct: - * lastSrcAddr - the most-recent or last, post-increment source address - * lastDestAddr - the most-recent or last, post-increment destination address - * dmaSize - the amount of data transferred for the current buffer - * currBufDesc - pointer to the current buffer descriptor being DMAed - */ - -typedef volatile struct MCD_XferProg_struct { - s8 *lastSrcAddr; - s8 *lastDestAddr; - u32 dmaSize; - MCD_bufDesc *currBufDesc; -} MCD_XferProg; - -/* FEC buffer descriptor */ -typedef volatile struct MCD_bufDescFec_struct { - u16 statCtrl; - u16 length; - u32 dataPointer; -} MCD_bufDescFec; - -/*************************************************************************/ -/* API function Prototypes - see MCD_dmaApi.c for further notes */ - -/* MCD_startDma starts a particular kind of DMA: - * srcAddr - the channel on which to run the DMA - * srcIncr - the address to move data from, or buffer-descriptor address - * destAddr - the amount to increment the source address per transfer - * destIncr - the address to move data to - * dmaSize - the amount to increment the destination address per transfer - * xferSize - the number bytes in of each data movement (1, 2, or 4) - * initiator - what device initiates the DMA - * priority - priority of the DMA - * flags - flags describing the DMA - * funcDesc - description of byte swapping, bit swapping, and CRC actions - */ -int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr, - s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator, - int priority, u32 flags, u32 funcDesc); - -/* - * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task structures, and - * setting up some global settings - */ -int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags); - -/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */ -int MCD_dmaStatus(int channel); - -/* MCD_XferProgrQuery() returns progress of DMA on requested channel */ -int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep); - -/* - * MCD_killDma() halts the DMA on the requested channel, without any - * intention of resuming the DMA. - */ -int MCD_killDma(int channel); - -/* - * MCD_continDma() continues a DMA which as stopped due to encountering an - * unready buffer descriptor. - */ -int MCD_continDma(int channel); - -/* - * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is - * running on that channel). - */ -int MCD_pauseDma(int channel); - -/* - * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is - * running on that channel). - */ -int MCD_resumeDma(int channel); - -/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */ -int MCD_csumQuery(int channel, u32 * csum); - -/* - * MCD_getCodeSize provides the packed size required by the microcoded task - * and structures. - */ -int MCD_getCodeSize(void); - -/* - * MCD_getVersion provides a pointer to a version string and returns a - * version number. - */ -int MCD_getVersion(char **longVersion); - -/* macro for setting a location in the variable table */ -#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value -/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, - so I'm avoiding surrounding it with "do {} while(0)" */ - -#endif /* DEFINESONLY */ - -#endif /* _MCD_API_H */ diff --git a/include/MCD_progCheck.h b/include/MCD_progCheck.h deleted file mode 100644 index 1ec8fbfbd28..00000000000 --- a/include/MCD_progCheck.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - - /* This file is autogenerated. Do not change */ -#define CURRBD 4 -#define DCOUNT 6 -#define DESTPTR 5 -#define SRCPTR 7 diff --git a/include/MCD_tasksInit.h b/include/MCD_tasksInit.h deleted file mode 100644 index 9f582beb51a..00000000000 --- a/include/MCD_tasksInit.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -#ifndef MCD_TSK_INIT_H -#define MCD_TSK_INIT_H 1 - -/* - * Do not edit! - */ - -/* Task 0 */ -void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, - int xferSize, short xferSizeIncr, int *cSave, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 1 */ -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, - short destIncr, int dmaSize, short xferSizeIncr, - int flags, int *currBD, int *cSave, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 2 */ -void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, - int xferSize, short xferSizeIncr, int *cSave, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 3 */ -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, - short destIncr, int dmaSize, short xferSizeIncr, - int flags, int *currBD, int *cSave, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 4 */ -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 5 */ -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, - volatile TaskTableEntry * taskTable, int channel); - -#endif /* MCD_TSK_INIT_H */ diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 1f85de091d3..20ac3b51ba7 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -80,7 +80,7 @@ struct acpi_rsdt { }; /* XSDT (Extended System Description Table) */ -struct acpi_xsdt { +struct __packed acpi_xsdt { struct acpi_table_header header; u64 entry[MAX_ACPI_TABLES]; }; @@ -921,6 +921,15 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature); int acpi_fill_csrt(struct acpi_ctx *ctx); /** + * acpi_get_rsdp_addr() - get ACPI RSDP table address + * + * This routine returns the ACPI RSDP table address in the system memory. + * + * @return: ACPI RSDP table address + */ +ulong acpi_get_rsdp_addr(void); + +/** * write_acpi_tables() - Write out the ACPI tables * * This writes all ACPI tables to the given address diff --git a/include/ahci.h b/include/ahci.h index d7f951c3883..d4f0f3ce0e7 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -223,9 +223,6 @@ int sata_dm_port_status(struct udevice *dev, int port); */ int sata_scan(struct udevice *dev); -int ahci_init(void __iomem *base); -int ahci_reset(void __iomem *base); - /** * ahci_init_one_dm() - set up a single AHCI port * diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 7a2f0dba316..13d99cfb597 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -105,5 +105,353 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } #endif +/* + * __raw_{read,write}{b,w,l,q}() access memory in native endianness. + * + * On some architectures memory mapped IO needs to be accessed differently. + * On the simple architectures, we just read/write the memory location + * directly. + */ + +#ifndef __raw_readb +#define __raw_readb __raw_readb +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + return *(const volatile u8 __force *)addr; +} +#endif + +#ifndef __raw_readw +#define __raw_readw __raw_readw +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + return *(const volatile u16 __force *)addr; +} +#endif + +#ifndef __raw_readl +#define __raw_readl __raw_readl +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + return *(const volatile u32 __force *)addr; +} +#endif + +#ifdef CONFIG_64BIT +#ifndef __raw_readq +#define __raw_readq __raw_readq +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + return *(const volatile u64 __force *)addr; +} +#endif +#endif /* CONFIG_64BIT */ + +#ifndef __raw_writeb +#define __raw_writeb __raw_writeb +static inline void __raw_writeb(u8 value, volatile void __iomem *addr) +{ + *(volatile u8 __force *)addr = value; +} +#endif + +#ifndef __raw_writew +#define __raw_writew __raw_writew +static inline void __raw_writew(u16 value, volatile void __iomem *addr) +{ + *(volatile u16 __force *)addr = value; +} +#endif + +#ifndef __raw_writel +#define __raw_writel __raw_writel +static inline void __raw_writel(u32 value, volatile void __iomem *addr) +{ + *(volatile u32 __force *)addr = value; +} +#endif + +#ifdef CONFIG_64BIT +#ifndef __raw_writeq +#define __raw_writeq __raw_writeq +static inline void __raw_writeq(u64 value, volatile void __iomem *addr) +{ + *(volatile u64 __force *)addr = value; +} +#endif +#endif /* CONFIG_64BIT */ + +/* + * {read,write}s{b,w,l,q}() repeatedly access the same memory address in + * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). + */ +#ifndef readsb +#define readsb readsb +static inline void readsb(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + if (count) { + u8 *buf = buffer; + + do { + u8 x = __raw_readb(addr); + *buf++ = x; + } while (--count); + } +} +#endif + +#ifndef readsw +#define readsw readsw +static inline void readsw(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + if (count) { + u16 *buf = buffer; + + do { + u16 x = __raw_readw(addr); + *buf++ = x; + } while (--count); + } +} +#endif + +#ifndef readsl +#define readsl readsl +static inline void readsl(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + if (count) { + u32 *buf = buffer; + + do { + u32 x = __raw_readl(addr); + *buf++ = x; + } while (--count); + } +} +#endif + +#ifdef CONFIG_64BIT +#ifndef readsq +#define readsq readsq +static inline void readsq(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + if (count) { + u64 *buf = buffer; + + do { + u64 x = __raw_readq(addr); + *buf++ = x; + } while (--count); + } +} +#endif +#endif /* CONFIG_64BIT */ + +#ifndef writesb +#define writesb writesb +static inline void writesb(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u8 *buf = buffer; + + do { + __raw_writeb(*buf++, addr); + } while (--count); + } +} +#endif + +#ifndef writesw +#define writesw writesw +static inline void writesw(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u16 *buf = buffer; + + do { + __raw_writew(*buf++, addr); + } while (--count); + } +} +#endif + +#ifndef writesl +#define writesl writesl +static inline void writesl(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u32 *buf = buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} +#endif + +#ifdef CONFIG_64BIT +#ifndef writesq +#define writesq writesq +static inline void writesq(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u64 *buf = buffer; + + do { + __raw_writeq(*buf++, addr); + } while (--count); + } +} +#endif +#endif /* CONFIG_64BIT */ + +#ifndef PCI_IOBASE +#define PCI_IOBASE ((void __iomem *)0) +#endif + +/* + * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a + * single I/O port multiple times. + */ + +#ifndef insb +#define insb insb +static inline void insb(unsigned long addr, void *buffer, unsigned int count) +{ + readsb(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef insw +#define insw insw +static inline void insw(unsigned long addr, void *buffer, unsigned int count) +{ + readsw(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef insl +#define insl insl +static inline void insl(unsigned long addr, void *buffer, unsigned int count) +{ + readsl(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef outsb +#define outsb outsb +static inline void outsb(unsigned long addr, const void *buffer, + unsigned int count) +{ + writesb(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef outsw +#define outsw outsw +static inline void outsw(unsigned long addr, const void *buffer, + unsigned int count) +{ + writesw(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef outsl +#define outsl outsl +static inline void outsl(unsigned long addr, const void *buffer, + unsigned int count) +{ + writesl(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef ioread8_rep +#define ioread8_rep ioread8_rep +static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + readsb(addr, buffer, count); +} +#endif + +#ifndef ioread16_rep +#define ioread16_rep ioread16_rep +static inline void ioread16_rep(const volatile void __iomem *addr, + void *buffer, unsigned int count) +{ + readsw(addr, buffer, count); +} +#endif + +#ifndef ioread32_rep +#define ioread32_rep ioread32_rep +static inline void ioread32_rep(const volatile void __iomem *addr, + void *buffer, unsigned int count) +{ + readsl(addr, buffer, count); +} +#endif + +#ifdef CONFIG_64BIT +#ifndef ioread64_rep +#define ioread64_rep ioread64_rep +static inline void ioread64_rep(const volatile void __iomem *addr, + void *buffer, unsigned int count) +{ + readsq(addr, buffer, count); +} +#endif +#endif /* CONFIG_64BIT */ + +#ifndef iowrite8_rep +#define iowrite8_rep iowrite8_rep +static inline void iowrite8_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesb(addr, buffer, count); +} +#endif + +#ifndef iowrite16_rep +#define iowrite16_rep iowrite16_rep +static inline void iowrite16_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesw(addr, buffer, count); +} +#endif + +#ifndef iowrite32_rep +#define iowrite32_rep iowrite32_rep +static inline void iowrite32_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesl(addr, buffer, count); +} +#endif + +#ifdef CONFIG_64BIT +#ifndef iowrite64_rep +#define iowrite64_rep iowrite64_rep +static inline void iowrite64_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesq(addr, buffer, count); +} +#endif +#endif /* CONFIG_64BIT */ + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_GENERIC_IO_H__ */ diff --git a/include/bcb.h b/include/bcb.h index 5edb17aa47d..1941d8c28b4 100644 --- a/include/bcb.h +++ b/include/bcb.h @@ -8,14 +8,69 @@ #ifndef __BCB_H__ #define __BCB_H__ +#include <part.h> + +enum bcb_field { + BCB_FIELD_COMMAND, + BCB_FIELD_STATUS, + BCB_FIELD_RECOVERY, + BCB_FIELD_STAGE +}; + #if IS_ENABLED(CONFIG_CMD_BCB) -int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp); + +int bcb_find_partition_and_load(const char *iface, + int devnum, char *partp); +int bcb_load(struct blk_desc *block_description, + struct disk_partition *disk_partition); +int bcb_set(enum bcb_field field, const char *value); + +/** + * bcb_get() - get the field value. + * @field: field to get + * @value_out: buffer to copy bcb field value to + * @value_size: buffer size to avoid overflow in case + * value_out is smaller then the field value + */ +int bcb_get(enum bcb_field field, char *value_out, size_t value_size); + +int bcb_store(void); +void bcb_reset(void); + #else + #include <linux/errno.h> -static inline int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp) + +static inline int bcb_load(struct blk_desc *block_description, + struct disk_partition *disk_partition) +{ + return -EOPNOTSUPP; +} + +static inline int bcb_find_partition_and_load(const char *iface, + int devnum, char *partp) +{ + return -EOPNOTSUPP; +} + +static inline int bcb_set(enum bcb_field field, const char *value) +{ + return -EOPNOTSUPP; +} + +static inline int bcb_get(enum bcb_field field, char *value_out) { return -EOPNOTSUPP; } + +static inline int bcb_store(void) +{ + return -EOPNOTSUPP; +} + +static inline void bcb_reset(void) +{ +} #endif #endif /* __BCB_H__ */ diff --git a/include/blkmap.h b/include/blkmap.h index af54583c7dd..30dc84a7da8 100644 --- a/include/blkmap.h +++ b/include/blkmap.h @@ -7,6 +7,23 @@ #ifndef _BLKMAP_H #define _BLKMAP_H +#include <dm/lists.h> + +/** + * struct blkmap - Block map + * + * Data associated with a blkmap. + * + * @label: Human readable name of this blkmap + * @blk: Underlying block device + * @slices: List of slices associated with this blkmap + */ +struct blkmap { + char *label; + struct udevice *blk; + struct list_head slices; +}; + /** * blkmap_map_linear() - Map region of other block device * @@ -74,4 +91,16 @@ int blkmap_create(const char *label, struct udevice **devp); */ int blkmap_destroy(struct udevice *dev); +/** + * blkmap_create_ramdisk() - Create new ramdisk with blkmap + * + * @label: Label of the new blkmap + * @image_addr: Target memory start address of this mapping + * @image_size: Target memory size of this mapping + * @devp: Updated with the address of the created blkmap device + * Returns: 0 on success, negative error code on failure + */ +int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size, + struct udevice **devp); + #endif /* _BLKMAP_H */ diff --git a/include/bootcount.h b/include/bootcount.h index bfa5d464276..bc06e17c9fb 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -6,7 +6,6 @@ #ifndef _BOOTCOUNT_H__ #define _BOOTCOUNT_H__ -#include <common.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/byteorder.h> diff --git a/include/bootdev.h b/include/bootdev.h index 35fa25aff1d..2cee8832d26 100644 --- a/include/bootdev.h +++ b/include/bootdev.h @@ -7,6 +7,7 @@ #ifndef __bootdev_h #define __bootdev_h +#include <dm/uclass-id.h> #include <linux/list.h> struct bootflow; diff --git a/include/bootflow.h b/include/bootflow.h index fede8f22a2b..42112874f64 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -45,10 +45,12 @@ enum bootflow_state_t { * CONFIG_OF_HAS_PRIOR_STAGE is enabled * @BOOTFLOWF_STATIC_BUF: Indicates that @bflow->buf is statically set, rather * than being allocated by malloc(). + * @BOOTFLOWF_USE_BUILTIN_FDT : Indicates that current bootflow uses built-in FDT */ enum bootflow_flags_t { BOOTFLOWF_USE_PRIOR_FDT = 1 << 0, BOOTFLOWF_STATIC_BUF = 1 << 1, + BOOTFLOWF_USE_BUILTIN_FDT = 1 << 2, }; /** diff --git a/include/bootm.h b/include/bootm.h index 10a1bd65a75..f5229ea90b3 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -52,9 +52,29 @@ int boot_selected_os(int argc, char *const argv[], int state, ulong bootm_disable_interrupts(void); -/* This is a special function used by booti/bootz */ -int bootm_find_images(int flag, int argc, char *const argv[], ulong start, - ulong size); +/** + * bootm_find_images() - find and locate various images + * + * @img_addr: Address of image being loaded + * @conf_ramdisk: Indicates the ramdisk to use (typically second arg of bootm) + * @conf_fdt: Indicates the FDT to use (typically third arg of bootm) + * @start: OS image start address + * @size: OS image size + * + * boot_find_images() will attempt to load an available ramdisk, + * flattened device tree, as well as specifically marked + * "loadable" images (loadables are FIT only) + * + * Note: bootm_find_images will skip an image if it is not found + * + * This is a special function used by booti/bootz + * + * Return: + * 0, if all existing images were loaded correctly + * 1, if an image is found but corrupted, or invalid + */ +int bootm_find_images(ulong img_addr, const char *conf_ramdisk, + const char *conf_fdt, ulong start, ulong size); /* * Measure the boot images. Measurement is the process of hashing some binary diff --git a/include/bootstage.h b/include/bootstage.h index affb0e5c6a6..59a76d0f0c4 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -147,7 +147,6 @@ enum bootstage_id { BOOTSTAGE_ID_FIT_CONFIG = 110, BOOTSTAGE_ID_FIT_TYPE, - BOOTSTAGE_ID_FIT_KERNEL_INFO, BOOTSTAGE_ID_FIT_COMPRESSION, BOOTSTAGE_ID_FIT_OS, diff --git a/include/bootstd.h b/include/bootstd.h index 7802564bcc6..99ce7b64e7c 100644 --- a/include/bootstd.h +++ b/include/bootstd.h @@ -94,4 +94,13 @@ int bootstd_get_priv(struct bootstd_priv **stdp); */ void bootstd_clear_glob(void); +/** + * bootstd_prog_boot() - Run standard boot in a fully programmatic mode + * + * Attempts to boot without making any use of U-Boot commands + * + * Returns: -ve error value (does not return except on failure to boot) + */ +int bootstd_prog_boot(void); + #endif diff --git a/include/clk-uclass.h b/include/clk-uclass.h index a22f1a5d848..cd62848bece 100644 --- a/include/clk-uclass.h +++ b/include/clk-uclass.h @@ -25,6 +25,7 @@ struct ofnode_phandle_args; * @set_parent: Set current clock parent * @enable: Enable a clock. * @disable: Disable a clock. + * @dump: Print clock information. * * The individual methods are described more fully below. */ @@ -39,6 +40,9 @@ struct clk_ops { int (*set_parent)(struct clk *clk, struct clk *parent); int (*enable)(struct clk *clk); int (*disable)(struct clk *clk); +#if IS_ENABLED(CONFIG_CMD_CLK) + void (*dump)(struct udevice *dev); +#endif }; #if 0 /* For documentation only */ @@ -135,6 +139,15 @@ int enable(struct clk *clk); * Return: zero on success, or -ve error code. */ int disable(struct clk *clk); + +/** + * dump() - Print clock information. + * @dev: The clock device to dump. + * + * If present, this function is called by "clk dump" command for each + * bound device. + */ +void dump(struct udevice *dev); #endif #endif diff --git a/include/clk.h b/include/clk.h index 249c0e0ab42..3d6394477be 100644 --- a/include/clk.h +++ b/include/clk.h @@ -676,8 +676,6 @@ static inline bool clk_valid(struct clk *clk) return clk && !!clk->dev; } -int soc_clk_dump(void); - #endif #define clk_prepare_enable(clk) clk_enable(clk) diff --git a/include/command.h b/include/command.h index 6262365e128..4cec6345453 100644 --- a/include/command.h +++ b/include/command.h @@ -60,6 +60,39 @@ struct cmd_tbl { #endif }; +/** + * cmd_arg_get() - Get a particular argument + * + * @argc: Number of arguments + * @argv: Argument vector of length @argc + * @argnum: Argument to get (0=first) + * Return: Pointer to argument @argnum if it exists, else NULL + */ +static inline const char *cmd_arg_get(int argc, char *const argv[], int argnum) +{ + return argc > argnum ? argv[argnum] : NULL; +} + +static inline const char *cmd_arg0(int argc, char *const argv[]) +{ + return cmd_arg_get(argc, argv, 0); +} + +static inline const char *cmd_arg1(int argc, char *const argv[]) +{ + return cmd_arg_get(argc, argv, 1); +} + +static inline const char *cmd_arg2(int argc, char *const argv[]) +{ + return cmd_arg_get(argc, argv, 2); +} + +static inline const char *cmd_arg3(int argc, char *const argv[]) +{ + return cmd_arg_get(argc, argv, 3); +} + #if defined(CONFIG_CMD_RUN) int do_run(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); @@ -390,7 +423,7 @@ int cmd_source_script(ulong addr, const char *fit_uname, const char *confname); #define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \ ll_entry_declare(struct cmd_tbl, _name, cmd) = \ U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ - _usage, _help, _comp); + _usage, _help, _comp) #define U_BOOT_CMDREP_COMPLETE(_name, _maxargs, _cmd_rep, _usage, \ _help, _comp) \ diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h index 57003f120f9..496d1c2348f 100644 --- a/include/configs/am62ax_evm.h +++ b/include/configs/am62ax_evm.h @@ -12,10 +12,6 @@ #include <env/ti/mmc.h> #include <env/ti/k3_dfu.h> -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 - - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 811dc0ff1a8..64458ebb4b8 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -14,9 +14,6 @@ #include <env/ti/k3_rproc.h> #include <env/ti/k3_dfu.h> -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 03f8ed14787..7a9f4afe7d1 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -101,7 +101,6 @@ UBI_BOOTCMD #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define MODULE_EXTRA_ENV_SETTINGS \ - "variant=-emmc\0" \ EMMC_ANDROID_BOOTCMD #endif diff --git a/include/configs/etamin.h b/include/configs/draco-etamin.h index 97585a4fd12..97585a4fd12 100644 --- a/include/configs/etamin.h +++ b/include/configs/draco-etamin.h diff --git a/include/configs/rastaban.h b/include/configs/draco-rastaban.h index 0991ebfd00c..0991ebfd00c 100644 --- a/include/configs/rastaban.h +++ b/include/configs/draco-rastaban.h diff --git a/include/configs/thuban.h b/include/configs/draco-thuban.h index f4c04c55ebf..f4c04c55ebf 100644 --- a/include/configs/thuban.h +++ b/include/configs/draco-thuban.h diff --git a/include/configs/draco.h b/include/configs/draco.h deleted file mode 100644 index 8f993cee0a3..00000000000 --- a/include/configs/draco.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef __CONFIG_DRACO_H -#define __CONFIG_DRACO_H - -#include "siemens-am33x-common.h" - -#define DDR_PLL_FREQ 303 - -#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ -#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ - -#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - "button_dfu0=27\0" \ - "led0=103,1,0\0" \ - "led1=64,0,1\0" - - /* Physical Memory Map */ -#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -/* Default env settings */ -#define CFG_EXTRA_ENV_SETTINGS \ - "hostname=draco\0" \ - "ubi_off=2048\0"\ - "nand_img_size=0x400000\0" \ - "optargs=\0" \ - "preboot=draco_led 0\0" \ - CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CFG_ENV_SETTINGS_V2 \ - CFG_ENV_SETTINGS_NAND_V2 - -#endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/imx8mp_debix_model_a.h b/include/configs/imx8mp_debix_model_a.h new file mode 100644 index 00000000000..e82e8b16b1d --- /dev/null +++ b/include/configs/imx8mp_debix_model_a.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * Copyright 2023 Gilles Talis <gilles.talis@gmail.com> + */ + +#ifndef __IMX8MP_DEBIX_MODEL_A_H +#define __IMX8MP_DEBIX_MODEL_A_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#if defined(CONFIG_CMD_NET) +#define CFG_FEC_MXC_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include <config_distro_bootcmd.h> + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 + +/* 2GB DDR */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ + +#endif diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index ea39d1bf824..c26438c8684 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -11,8 +11,6 @@ #include <linux/sizes.h> -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ #define CFG_SYS_FLASH_BASE 0x000000000 diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 692c6bb5e42..846cfa7531c 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -12,9 +12,6 @@ #include <linux/sizes.h> #include <config_distro_bootcmd.h> -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 - /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) #define CFG_SYS_UBOOT_BASE 0x50280000 diff --git a/include/configs/librem5.h b/include/configs/librem5.h index ce0a340ba26..876b02f4da6 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -56,6 +56,8 @@ "scriptaddr=0x80000000\0" \ "pxefile_addr_r=0x80100000\0" \ "kernel_addr_r=0x80800000\0" \ + "kernel_comp_addr_r=0x90000000\0" \ + "kernel_comp_size=0x08000000\0" \ "fdt_addr_r=0x84800000\0" \ "ramdisk_addr_r=0x85000000\0" \ "console=" CONSOLE ",115200\0" \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 83ab94ec444..971a393817a 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -57,13 +57,6 @@ * MMC */ -/* SATA */ -#ifndef PCI_DEVICE_ID_FREESCALE_AHCI -#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 -#endif -#define CFG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ - PCI_DEVICE_ID_FREESCALE_AHCI} - /* SPI */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index ee4f885c534..0f591e3c4ab 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -49,11 +49,6 @@ CSOR_NOR_TRHZ_80) #endif -/* SATA */ -#define SCSI_VEND_ID 0x1b4b -#define SCSI_DEV_ID 0x9170 -#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} - /* Initial environment variables */ #ifndef SPL_NO_ENV #undef CFG_EXTRA_ENV_SETTINGS diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 60362b6a4d0..ef8fdc1912b 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -199,13 +199,6 @@ #endif #endif -/* SATA */ -#ifndef SPL_NO_SATA -#define SCSI_VEND_ID 0x1b4b -#define SCSI_DEV_ID 0x9170 -#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -#endif - #include <asm/fsl_secure_boot.h> #endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 096e5bbe663..e7a8cb20dff 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -13,7 +13,7 @@ #define CFG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ -#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ @@ -79,9 +79,11 @@ "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ "fastboot_partition_alias_system=rootfs\0" \ "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ + "mmcautodetect=yes\0" \ PICO_BOOT_ENV #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ diff --git a/include/configs/poplar.h b/include/configs/poplar.h index 6e8adf91877..629b335f5d1 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -37,11 +37,11 @@ "env_mmc_blknum=0xf80\0" \ "env_mmc_nblks=0x80\0" \ "kernel_addr_r=0x30000000\0" \ - "pxefile_addr_r=0x32000000\0" \ - "scriptaddr=0x32000000\0" \ - "fdt_addr_r=0x32200000\0" \ + "pxefile_addr_r=0x33000000\0" \ + "scriptaddr=0x33000000\0" \ + "fdt_addr_r=0x33200000\0" \ "fdtfile=hisilicon/hi3798cv200-poplar.dtb\0" \ - "ramdisk_addr_r=0x32400000\0" \ + "ramdisk_addr_r=0x33400000\0" \ BOOTENV #endif /* _POPLAR_H_ */ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index ff43113f243..29c74470c71 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -40,6 +40,7 @@ "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ "fdt_addr_r=0x46000000\0" \ + "fdtoverlay_addr_r=0x45800000\0" \ "scriptaddr=0x43900000\0" \ "pxefile_addr_r=0x45900000\0" \ "ramdisk_addr_r=0x46100000\0" \ diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 62a7e9af0c5..75bb9cd8d06 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -31,6 +31,8 @@ "scriptaddr=0x00418000\0" \ "pxefile_addr_r=0x00428000\0" \ "ramdisk_addr_r=0x00438000\0" \ + "splashimage=0x00448000\0" \ + "splashpos=m,m\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/stm32mp25_common.h b/include/configs/stm32mp25_common.h new file mode 100644 index 00000000000..ec980eea856 --- /dev/null +++ b/include/configs/stm32mp25_common.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STM32MP25x CPU + */ + +#ifndef __CONFIG_STM32MP25_COMMMON_H +#define __CONFIG_STM32MP25_COMMMON_H +#include <linux/sizes.h> +#include <asm/arch/stm32.h> + +/* + * Configuration of the external SRAM memory used by U-Boot + */ +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE + +/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_SYS_BOOTMAPSZ SZ_256M + +#endif /* __CONFIG_STM32MP25_COMMMON_H */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 72c04d8a994..b36207cb5d1 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -9,23 +9,10 @@ #ifndef __CONFIG_KS2_EVM_H #define __CONFIG_KS2_EVM_H -/* U-Boot Build Configuration */ - -/* SoC Configuration */ - /* Memory Configuration */ #define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#ifdef CONFIG_SYS_MALLOC_F_LEN -#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN -#else -#define SPL_MALLOC_F_SIZE 0 -#endif - -/* SPL SPI Loader Configuration */ -#define KEYSTONE_SPL_STACK_SIZE (8 * 1024) - /* SRAM scratch space entries */ #define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc @@ -53,8 +40,6 @@ #define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES -/* EEPROM definitions */ - /* NAND Configuration */ #define CFG_SYS_NAND_MASK_CLE 0x4000 #define CFG_SYS_NAND_MASK_ALE 0x2000 @@ -63,18 +48,10 @@ #define CFG_SYS_NAND_LARGEPAGE #define CFG_SYS_NAND_BASE_LIST { 0x30000000, } - - -/* U-Boot general configuration */ - -/* EDMA3 */ - - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> /* we may include files below only after all above definitions */ -#include <asm/arch/hardware.h> #include <asm/arch/clock.h> #ifndef CONFIG_SOC_K2G #define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) diff --git a/include/console.h b/include/console.h index ceb733b5cb6..e29817e57b0 100644 --- a/include/console.h +++ b/include/console.h @@ -156,6 +156,16 @@ int console_announce_r(void); */ void console_puts_select_stderr(bool serial_only, const char *s); +/** + * console_clear() - Clear the console + * + * Uses an ANSI sequence to clear the display, failing back to clearing the + * video display directly if !CONFIG_VIDEO_ANSI + * + * Return: 0 if OK, -ve on error + */ +int console_clear(void); + /* * CONSOLE multiplexing. */ diff --git a/include/dfu.h b/include/dfu.h index 07922224ef1..2f42781888a 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -10,7 +10,6 @@ #ifndef __DFU_ENTITY_H_ #define __DFU_ENTITY_H_ -#include <common.h> #include <linux/list.h> #include <mmc.h> #include <spi_flash.h> @@ -99,7 +98,12 @@ struct virt_internal_data { int dev_num; }; + +#if defined(CONFIG_DFU_NAME_MAX_SIZE) +#define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE +#else #define DFU_NAME_SIZE 32 +#endif #ifndef DFU_DEFAULT_POLL_TIMEOUT #define DFU_DEFAULT_POLL_TIMEOUT 0 #endif diff --git a/include/display_options.h b/include/display_options.h index 85dacbc7590..66e59607737 100644 --- a/include/display_options.h +++ b/include/display_options.h @@ -9,6 +9,8 @@ #ifndef __DISPLAY_OPTIONS_H #define __DISPLAY_OPTIONS_H +#include <linux/types.h> + /** * print_size() - Print a size with a suffix * @@ -19,7 +21,6 @@ * @size: Size to print * @suffix String to print after the size */ -#include <display_options.h> void print_size(uint64_t size, const char *suffix); /** diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 3f28ce685f4..7da4243984b 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -130,7 +130,7 @@ #define IMX8MP_CLK_SAI1 123 #define IMX8MP_CLK_SAI2 124 #define IMX8MP_CLK_SAI3 125 -#define IMX8MP_CLK_SAI4 126 +/* #define IMX8MP_CLK_SAI4 126 */ #define IMX8MP_CLK_SAI5 127 #define IMX8MP_CLK_SAI6 128 #define IMX8MP_CLK_ENET_QOS 129 @@ -376,7 +376,6 @@ #define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 #define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 #define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 diff --git a/include/dt-bindings/phy/nuvoton,npcm-usbphy.h b/include/dt-bindings/phy/nuvoton,npcm-usbphy.h new file mode 100644 index 00000000000..46946d377d9 --- /dev/null +++ b/include/dt-bindings/phy/nuvoton,npcm-usbphy.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2023 Nuvoton Technology corporation. + +#ifndef _DT_BINDINGS_NPCM_USBPHY_H +#define _DT_BINDINGS_NPCM_USBPHY_H + +#define NPCM_UDC0_7 0 +#define NPCM_UDC8 1 +#define NPCM_UDC9 2 +#define NPCM_USBH1 3 +#define NPCM_USBH2 4 +#define NPCM_MAX_USB_CTRL_ID 4 + +#endif diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6fb8ada3f4..28ad0235086 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -37,6 +37,9 @@ #define STM32MP_PKG_AB 0x2 #define STM32MP_PKG_AC 0x4 #define STM32MP_PKG_AD 0x8 +#define STM32MP_PKG_AI 0x100 +#define STM32MP_PKG_AK 0x400 +#define STM32MP_PKG_AL 0x800 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ diff --git a/include/efi_api.h b/include/efi_api.h index 8f5ef5f680f..0e92cb8a7f6 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -192,7 +192,7 @@ struct efi_boot_services { struct efi_event *event, void *context), void *notify_context, - efi_guid_t *event_group, + const efi_guid_t *event_group, struct efi_event **event); }; @@ -404,6 +404,9 @@ struct efi_runtime_services { #define EFI_EVENT_GROUP_RESET_SYSTEM \ EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \ 0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b) +#define EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR \ + EFI_GUID(0xb4a40fe6, 0x9149, 0x4f29, 0x94, 0x47, \ + 0x49, 0x38, 0x7a, 0x7f, 0xab, 0x87) /* EFI Configuration Table and GUID definitions */ #define NULL_GUID \ diff --git a/include/efi_loader.h b/include/efi_loader.h index e24410505f4..34e7fbbf184 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -8,7 +8,6 @@ #ifndef _EFI_LOADER_H #define _EFI_LOADER_H 1 -#include <common.h> #include <blk.h> #include <event.h> #include <log.h> @@ -91,6 +90,8 @@ efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len); * back to u-boot world */ void efi_restore_gd(void); +/* Call this to unset the current device name */ +void efi_clear_bootdev(void); /* Call this to set the current device name */ void efi_set_bootdev(const char *dev, const char *devnr, const char *path, void *buffer, size_t buffer_size); @@ -115,6 +116,7 @@ static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len) /* No loader configured, stub out EFI_ENTRY */ static inline void efi_restore_gd(void) { } +static inline void efi_clear_bootdev(void) { } static inline void efi_set_bootdev(const char *dev, const char *devnr, const char *path, void *buffer, size_t buffer_size) { } @@ -290,6 +292,8 @@ extern const efi_guid_t efi_guid_event_group_memory_map_change; extern const efi_guid_t efi_guid_event_group_ready_to_boot; /* event group ResetSystem() invoked (before ExitBootServices) */ extern const efi_guid_t efi_guid_event_group_reset_system; +/* event group return to efibootmgr */ +extern const efi_guid_t efi_guid_event_group_return_to_efibootmgr; /* GUID of the device tree table */ extern const efi_guid_t efi_guid_fdt; extern const efi_guid_t efi_guid_loaded_image; @@ -526,14 +530,21 @@ efi_status_t efi_bootmgr_get_unused_bootoption(u16 *buf, efi_status_t efi_bootmgr_update_media_device_boot_option(void); /* Delete selected boot option */ efi_status_t efi_bootmgr_delete_boot_option(u16 boot_index); +/* Invoke EFI boot manager */ +efi_status_t efi_bootmgr_run(void *fdt); /* search the boot option index in BootOrder */ bool efi_search_bootorder(u16 *bootorder, efi_uintn_t num, u32 target, u32 *index); /* Set up console modes */ void efi_setup_console_size(void); +/* Set up load options from environment variable */ +efi_status_t efi_env_set_load_options(efi_handle_t handle, const char *env_var, + u16 **load_options); /* Install device tree */ efi_status_t efi_install_fdt(void *fdt); /* Run loaded UEFI image */ efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size); +/* Run loaded UEFI image with given fdt */ +efi_status_t efi_binary_run(void *image, size_t size, void *fdt); /* Initialize variable services */ efi_status_t efi_init_variables(void); /* Notify ExitBootServices() is called */ @@ -685,7 +696,7 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( struct efi_event *event, void *context), - void *notify_context, efi_guid_t *group, + void *notify_context, const efi_guid_t *group, struct efi_event **event); /* Call this to set a timer */ efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type, @@ -878,14 +889,12 @@ efi_status_t __efi_runtime EFIAPI efi_get_time( efi_status_t __efi_runtime EFIAPI efi_set_time(struct efi_time *time); -#ifdef CONFIG_CMD_BOOTEFI_SELFTEST /* * Entry point for the tests of the EFI API. * It is called by 'bootefi selftest' */ efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle, struct efi_system_table *systab); -#endif efi_status_t EFIAPI efi_get_variable(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, diff --git a/include/efi_selftest.h b/include/efi_selftest.h index 7c69c3f3761..5bcebb36828 100644 --- a/include/efi_selftest.h +++ b/include/efi_selftest.h @@ -8,7 +8,6 @@ #ifndef _EFI_SELFTEST_H #define _EFI_SELFTEST_H -#include <common.h> #include <efi.h> #include <efi_api.h> #include <efi_loader.h> diff --git a/include/env.h b/include/env.h index 430c4fa94a4..9778e3e4f2c 100644 --- a/include/env.h +++ b/include/env.h @@ -73,6 +73,14 @@ enum env_redund_flags { int env_get_id(void); /** + * env_inc_id() - Increase the sequence number for the environment + * + * Increment the value that is used by env_get_id() to inform callers + * if the environment has changed since they last checked. + */ +void env_inc_id(void); + +/** * env_init() - Set up the pre-relocation environment * * This locates the environment or uses the default if nothing is available. diff --git a/include/env_internal.h b/include/env_internal.h index fcb464263f0..5c289d67f90 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -194,6 +194,18 @@ struct env_driver { extern struct hsearch_data env_htab; /** + * env_do_env_set() - Perform the actual setting of an environment variable + * + * Due to the number of places we may need to set an environmental variable + * from we have an exposed internal function that performs the real work and + * then call this from both the command line function as well as other + * locations. + * + * Return: 0 on success or 1 on failure + */ +int env_do_env_set(int flag, int argc, char *const argv[], int env_flag); + +/** * env_ext4_get_intf() - Provide the interface for env in EXT4 * * It is a weak function allowing board to overidde the default interface for diff --git a/include/ext4fs.h b/include/ext4fs.h index dd66d27f776..d96edfd0576 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -147,7 +147,7 @@ int ext4fs_create_link(const char *target, const char *fname); struct ext_filesystem *get_fs(void); int ext4fs_open(const char *filename, loff_t *len); int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread); -int ext4fs_mount(unsigned part_length); +int ext4fs_mount(void); void ext4fs_close(void); void ext4fs_reinit_global(void); int ext4fs_ls(const char *dirname); diff --git a/include/fat.h b/include/fat.h index a9756fb4cd1..3dce99a23cf 100644 --- a/include/fat.h +++ b/include/fat.h @@ -34,12 +34,6 @@ struct disk_partition; /* Maximum number of entry for long file name according to spec */ #define MAX_LFN_SLOT 20 -/* Filesystem identifiers */ -#define FAT12_SIGN "FAT12 " -#define FAT16_SIGN "FAT16 " -#define FAT32_SIGN "FAT32 " -#define SIGNLEN 8 - /* File attributes */ #define ATTR_RO 1 #define ATTR_HIDDEN 2 diff --git a/include/fdt_support.h b/include/fdt_support.h index 2cd83668982..25600d62f29 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -7,8 +7,7 @@ #ifndef __FDT_SUPPORT_H #define __FDT_SUPPORT_H -#if (defined(CONFIG_OF_LIBFDT) || defined(CONFIG_OF_CONTROL)) && \ - !defined(USE_HOSTCC) +#if !defined(USE_HOSTCC) #include <asm/u-boot.h> #include <linux/libfdt.h> @@ -56,7 +55,17 @@ int fdt_chosen(void *fdt); /** * Add initrd information to the FDT before booting the OS. * - * @param fdt FDT address in memory + * Adds linux,initrd-start and linux,initrd-end properties to the /chosen node, + * creating it if necessary. + * + * A memory reservation for the ramdisk is added to the FDT, or an existing one + * (with matching @initrd_start) updated. + * + * If @initrd_start == @initrd_end this function does nothing and returns 0. + * + * @fdt: Pointer to FDT in memory + * @initrd_start: Start of ramdisk + * @initrd_end: End of ramdisk * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end); @@ -233,13 +242,23 @@ int ft_system_setup(void *blob, struct bd_info *bd); void set_working_fdt_addr(ulong addr); /** - * shrink down the given blob to minimum size + some extrasize if required + * fdt_shrink_to_minimum() - shrink FDT while allowing for some margin + * + * Shrink down the given blob to 'minimum' size + some extrasize. + * + * The new size is enough to hold the existing contents plus @extrasize bytes, + * plus 5 memory reservations. Also, the end of the FDT is aligned to a 4KB + * boundary, so it might end up up to 4KB larger than needed. + * + * If there is an existing memory reservation for @blob in the FDT, it is + * updated for the new size. * * @param blob FDT blob to update * @param extrasize additional bytes needed * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_shrink_to_minimum(void *blob, uint extrasize); + int fdt_increase_size(void *fdt, int add_len); int fdt_delete_disabled_nodes(void *blob); @@ -418,7 +437,7 @@ int fdt_valid(struct fdt_header **blobp); */ int fdt_get_cells_len(const void *blob, char *nr_cells_name); -#endif /* ifdef CONFIG_OF_LIBFDT */ +#endif /* !USE_HOSTCC */ #ifdef USE_HOSTCC int fdtdec_get_int(const void *blob, int node, const char *prop_name, diff --git a/include/fm_eth.h b/include/fm_eth.h index 8b133e703b4..f30110817c7 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -7,7 +7,6 @@ #ifndef __FM_ETH_H__ #define __FM_ETH_H__ -#include <common.h> #include <phy.h> #include <asm/types.h> diff --git a/include/fs.h b/include/fs.h index e341a0ed01b..ef540e7c23d 100644 --- a/include/fs.h +++ b/include/fs.h @@ -5,7 +5,6 @@ #ifndef _FS_H #define _FS_H -#include <common.h> #include <rtc.h> struct cmd_tbl; diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 258738dfc8c..71907bc73c5 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -7,9 +7,10 @@ #ifndef __FSL_MC_H__ #define __FSL_MC_H__ -#include <common.h> #include <linux/bitops.h> +struct bd_info; + #define MC_CCSR_BASE_ADDR \ ((struct mc_ccsr_registers __iomem *)0x8340000) diff --git a/include/fsl_errata.h b/include/fsl_errata.h index 88f4268658a..44547645df8 100644 --- a/include/fsl_errata.h +++ b/include/fsl_errata.h @@ -6,7 +6,6 @@ #ifndef _FSL_ERRATA_H #define _FSL_ERRATA_H -#include <common.h> #if defined(CONFIG_PPC) #include <asm/processor.h> #elif defined(CONFIG_ARCH_LS1021A) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index de1e70a6d0b..f9a0a7017d4 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -9,7 +9,6 @@ #ifdef CONFIG_FSL_IFC #include <config.h> -#include <common.h> #include <part.h> #ifdef CONFIG_ARM #include <asm/arch/soc.h> diff --git a/include/fsl_qe.h b/include/fsl_qe.h index 48accb8d891..309ca7ea6af 100644 --- a/include/fsl_qe.h +++ b/include/fsl_qe.h @@ -9,7 +9,6 @@ #ifndef __QE_H__ #define __QE_H__ -#include "common.h" #ifdef CONFIG_U_QE #include <linux/immap_qe.h> #endif diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 9dad1d1ec47..8c5e59c5b1c 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -9,7 +9,6 @@ #ifndef __FSL_SEC_H #define __FSL_SEC_H -#include <common.h> #include <asm/io.h> #ifdef CONFIG_SYS_FSL_SEC_LE diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index 3092a0ea62a..248d5b6d421 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -8,7 +8,6 @@ #ifndef __FSL_SEC_MON_H #define __FSL_SEC_MON_H -#include <common.h> #include <asm/io.h> #ifdef CONFIG_SYS_FSL_SEC_MON_LE diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index e7674c1bff2..0dec69a7235 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -6,7 +6,6 @@ #ifndef _FSL_SFP_SNVS_ #define _FSL_SFP_SNVS_ -#include <common.h> #include <config.h> #include <asm/io.h> diff --git a/include/image.h b/include/image.h index 2e3cf839ee3..432ec927b1f 100644 --- a/include/image.h +++ b/include/image.h @@ -612,41 +612,86 @@ int boot_get_setup(struct bootm_headers *images, uint8_t arch, ulong *setup_star #define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ #define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */ -ulong genimg_get_kernel_addr_fit(char * const img_addr, - const char **fit_uname_config, - const char **fit_uname_kernel); +/** + * genimg_get_kernel_addr_fit() - Parse FIT specifier + * + * Get the real kernel start address from a string which is normally the first + * argv of bootm/bootz + * + * These cases are dealt with, based on the value of @img_addr: + * NULL: Returns image_load_addr, does not set last two args + * "<addr>": Returns address + * + * For FIT: + * "[<addr>]#<conf>": Returns address (or image_load_addr), + * sets fit_uname_config to config name + * "[<addr>]:<subimage>": Returns address (or image_load_addr) and sets + * fit_uname_kernel to the subimage name + * + * @img_addr: a string might contain real image address (or NULL) + * @fit_uname_config: Returns configuration unit name + * @fit_uname_kernel: Returns subimage name + * + * Returns: kernel start address + */ +ulong genimg_get_kernel_addr_fit(const char *const img_addr, + const char **fit_uname_config, + const char **fit_uname_kernel); + ulong genimg_get_kernel_addr(char * const img_addr); int genimg_get_format(const void *img_addr); int genimg_has_config(struct bootm_headers *images); -int boot_get_fpga(int argc, char *const argv[], struct bootm_headers *images, - uint8_t arch, const ulong *ld_start, ulong * const ld_len); -int boot_get_ramdisk(int argc, char *const argv[], struct bootm_headers *images, - uint8_t arch, ulong *rd_start, ulong *rd_end); +/** + * boot_get_fpga() - Locate the FPGA image + * + * @images: Information about images being loaded + * Return 0 if OK, non-zero on failure + */ +int boot_get_fpga(struct bootm_headers *images); + +/** + * boot_get_ramdisk() - Locate the ramdisk + * + * @select: address or name of ramdisk to use, or NULL for default + * @images: pointer to the bootm images structure + * @arch: expected ramdisk architecture + * @rd_start: pointer to a ulong variable, will hold ramdisk start address + * @rd_end: pointer to a ulong variable, will hold ramdisk end + * + * boot_get_ramdisk() is responsible for finding a valid ramdisk image. + * Currently supported are the following ramdisk sources: + * - multicomponent kernel/ramdisk image, + * - commandline provided address of decicated ramdisk image. + * + * returns: + * 0, if ramdisk image was found and valid, or skiped + * rd_start and rd_end are set to ramdisk start/end addresses if + * ramdisk image is found and valid + * + * 1, if ramdisk image is found but corrupted, or invalid + * rd_start and rd_end are set to 0 if no ramdisk exists + */ +int boot_get_ramdisk(char const *select, struct bootm_headers *images, + uint arch, ulong *rd_start, ulong *rd_end); /** - * boot_get_loadable - routine to load a list of binaries to memory - * @argc: Ignored Argument - * @argv: Ignored Argument + * boot_get_loadable() - load a list of binaries to memory + * * @images: pointer to the bootm images structure - * @arch: expected architecture for the image - * @ld_start: Ignored Argument - * @ld_len: Ignored Argument * - * boot_get_loadable() will take the given FIT configuration, and look - * for a field named "loadables". Loadables, is a list of elements in - * the FIT given as strings. exe: + * Takes the given FIT configuration, then looks for a field named + * "loadables", a list of elements in the FIT given as strings, e.g.: * loadables = "linux_kernel", "fdt-2"; - * this function will attempt to parse each string, and load the - * corresponding element from the FIT into memory. Once placed, - * no aditional actions are taken. * - * @return: + * Each string is parsed, loading the corresponding element from the FIT into + * memory. Once placed, no additional actions are taken. + * + * Return: * 0, if only valid images or no images are found * error code, if an error occurs during fit_image_load */ -int boot_get_loadable(int argc, char *const argv[], struct bootm_headers *images, - uint8_t arch, const ulong *ld_start, ulong *const ld_len); +int boot_get_loadable(struct bootm_headers *images); int boot_get_setup_fit(struct bootm_headers *images, uint8_t arch, ulong *setup_start, ulong *setup_len); @@ -705,7 +750,13 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr, * @param load_op Decribes what to do with the load address * @param datap Returns address of loaded image * @param lenp Returns length of loaded image - * Return: node offset of image, or -ve error code on error + * Return: node offset of image, or -ve error code on error: + * -ENOEXEC - unsupported architecture + * -ENOENT - could not find image / subimage + * -EACCES - hash, signature or decryptions failure + * -EBADF - invalid OS or image type, or cannot get image load-address + * -EXDEV - memory overwritten / overlap + * -NOEXEC - image decompression error, or invalid FDT */ int fit_image_load(struct bootm_headers *images, ulong addr, const char **fit_unamep, const char **fit_uname_configp, @@ -756,9 +807,33 @@ int image_locate_script(void *buf, int size, const char *fit_uname, int fit_get_node_from_config(struct bootm_headers *images, const char *prop_name, ulong addr); -int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, - struct bootm_headers *images, - char **of_flat_tree, ulong *of_size); +/** + * boot_get_fdt() - locate FDT devicetree to use for booting + * + * @buf: Pointer to image + * @select: FDT to select (this is normally argv[2] of the bootm command) + * @arch: architecture (IH_ARCH_...) + * @images: pointer to the bootm images structure + * @of_flat_tree: pointer to a char* variable, will hold fdt start address + * @of_size: pointer to a ulong variable, will hold fdt length + * + * boot_get_fdt() is responsible for finding a valid flat device tree image. + * Currently supported are the following FDT sources: + * - multicomponent kernel/ramdisk/FDT image, + * - commandline provided address of decicated FDT image. + * + * Return: + * 0, if fdt image was found and valid, or skipped + * of_flat_tree and of_size are set to fdt start address and length if + * fdt image is found and valid + * + * 1, if fdt image is found but corrupted + * of_flat_tree and of_size are set to 0 if no fdt exists + */ +int boot_get_fdt(void *buf, const char *select, uint arch, + struct bootm_headers *images, char **of_flat_tree, + ulong *of_size); + void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob); int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size); @@ -936,7 +1011,7 @@ int image_decomp_type(const unsigned char *buf, ulong len); * @load: Destination load address in U-Boot memory * @image_start Image start address (where we are decompressing from) * @type: OS type (IH_OS_...) - * @load_bug: Place to decompress to + * @load_buf: Place to decompress to * @image_buf: Address to decompress from * @image_len: Number of bytes in @image_buf to decompress * @unc_len: Available space for decompression @@ -953,12 +1028,11 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, * * @images: Images information * @blob: FDT to update - * @of_size: Size of the FDT * @lmb: Points to logical memory block structure * Return: 0 if ok, <0 on failure */ int image_setup_libfdt(struct bootm_headers *images, void *blob, - int of_size, struct lmb *lmb); + struct lmb *lmb); /** * Set up the FDT to use for booting a kernel diff --git a/include/init.h b/include/init.h index d57a24fd00d..9a1951d10a0 100644 --- a/include/init.h +++ b/include/init.h @@ -292,6 +292,17 @@ int misc_init_r(void); /* common/board_info.c */ int checkboard(void); + +/** + * show_board_info() - Show board information + * + * Check sysinfo for board information. Failing that if the root node of the DTB + * has a "model" property, show it. + * + * Then call checkboard(). + * + * Return 0 if OK, -ve on error + */ int show_board_info(void); /** diff --git a/include/iotrace.h b/include/iotrace.h index 7ff2e8332b0..d5610426cc8 100644 --- a/include/iotrace.h +++ b/include/iotrace.h @@ -6,7 +6,6 @@ #ifndef __IOTRACE_H #define __IOTRACE_H -//#include <common.h> #include <linux/types.h> /* Support up to the machine word length for now */ diff --git a/include/k210/pll.h b/include/k210/pll.h index fd16a89cb20..175c47f6f23 100644 --- a/include/k210/pll.h +++ b/include/k210/pll.h @@ -16,9 +16,6 @@ struct k210_pll_config { #ifdef CONFIG_UNIT_TEST TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, struct k210_pll_config *best); -#ifndef nop -#define nop() -#endif #endif #endif /* K210_PLL_H */ diff --git a/include/key_matrix.h b/include/key_matrix.h index e7420b9d795..17f5d12cdd9 100644 --- a/include/key_matrix.h +++ b/include/key_matrix.h @@ -8,7 +8,6 @@ #ifndef _KEY_MATRIX_H #define _KEY_MATRIX_H -#include <common.h> /* Information about a matrix keyboard */ struct key_matrix { diff --git a/include/led.h b/include/led.h index 329041008c1..a6353166289 100644 --- a/include/led.h +++ b/include/led.h @@ -110,4 +110,12 @@ enum led_state_t led_get_state(struct udevice *dev); */ int led_set_period(struct udevice *dev, int period_ms); +/** + * led_bind_generic() - bind children of parent to given driver + * + * @parent: Top-level LED device + * @driver_name: Driver for handling individual child nodes + */ +int led_bind_generic(struct udevice *parent, const char *driver_name); + #endif diff --git a/include/libata.h b/include/libata.h index b03b29960df..a55e9315a73 100644 --- a/include/libata.h +++ b/include/libata.h @@ -10,7 +10,6 @@ #ifndef __LIBATA_H__ #define __LIBATA_H__ -#include <common.h> enum { /* various global constants */ diff --git a/include/linux/mii.h b/include/linux/mii.h index 49e29ac314a..70689bc53d7 100644 --- a/include/linux/mii.h +++ b/include/linux/mii.h @@ -9,6 +9,8 @@ #ifndef __LINUX_MII_H__ #define __LINUX_MII_H__ +#include <linux/types.h> + /* Generic MII registers. */ #define MII_BMCR 0x00 /* Basic mode control register */ #define MII_BMSR 0x01 /* Basic mode status register */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 09f52698877..7a66c7af749 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -552,8 +552,20 @@ unsigned mtd_mmap_capabilities(struct mtd_info *mtd); #ifdef __UBOOT__ /* drivers/mtd/mtdcore.h */ +#if CONFIG_IS_ENABLED(MTD) int add_mtd_device(struct mtd_info *mtd); int del_mtd_device(struct mtd_info *mtd); +#else +static inline int add_mtd_device(struct mtd_info *mtd) +{ + return -ENOSYS; +} + +static inline int del_mtd_device(struct mtd_info *mtd) +{ + return -ENOSYS; +} +#endif #ifdef CONFIG_MTD_PARTITIONS int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 91e61ce8646..6f479fa5adc 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -17,7 +17,6 @@ #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #else -#include <common.h> #include <spi.h> #include <spi-mem.h> #include <linux/mtd/nand.h> diff --git a/include/linux/time.h b/include/linux/time.h index 14ff5b6f481..14a144d9c9c 100644 --- a/include/linux/time.h +++ b/include/linux/time.h @@ -11,6 +11,15 @@ #define _REENT_ONLY +#define MSEC_PER_SEC 1000L +#define USEC_PER_MSEC 1000L +#define NSEC_PER_USEC 1000L +#define NSEC_PER_MSEC 1000000L +#define USEC_PER_SEC 1000000L +#define NSEC_PER_SEC 1000000000L +#define PSEC_PER_SEC 1000000000000LL +#define FSEC_PER_SEC 1000000000000000LL + #define SECSPERMIN 60L #define MINSPERHOUR 60L #define HOURSPERDAY 24L diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h index 935e5c0cbb1..bb1eb93bd20 100644 --- a/include/linux/usb/composite.h +++ b/include/linux/usb/composite.h @@ -21,7 +21,6 @@ * the composite model the host can use both functions at the same time. */ -#include <common.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <linux/bitmap.h> diff --git a/include/miiphy.h b/include/miiphy.h index c66a1845b58..5abffd8fb6b 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -14,7 +14,6 @@ #ifndef _miiphy_h_ #define _miiphy_h_ -#include <common.h> #include <linux/mii.h> #include <linux/list.h> #include <net.h> diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 5926c8090a4..aa8803413cd 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -6,8 +6,6 @@ #ifndef __MPC83XX_H__ #define __MPC83XX_H__ -#include <config.h> -#include <asm/fsl_lbc.h> #if defined(CONFIG_E300) #include <asm/e300.h> #endif diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 52cd1c4dbc4..f4aecaac75f 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -163,7 +163,7 @@ struct cfi_pri_hdr { #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) /* map to cfi_flash_num_flash_banks only when supported */ #if IS_ENABLED(CONFIG_FLASH_CFI_DRIVER) && \ - (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD_SUPPORT)) + (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD)) #define CFI_FLASH_BANKS (cfi_flash_num_flash_banks) /* board code can update this variable before CFI detection */ extern int cfi_flash_num_flash_banks; diff --git a/include/mv88e6352.h b/include/mv88e6352.h index 2e810c8183e..152a0774fc0 100644 --- a/include/mv88e6352.h +++ b/include/mv88e6352.h @@ -7,7 +7,6 @@ #ifndef __MV886352_H #define __MV886352_H -#include <common.h> /* PHY registers */ #define PHY(itf) (itf) diff --git a/include/nand.h b/include/nand.h index 70c1286ccb4..220ffa202ef 100644 --- a/include/nand.h +++ b/include/nand.h @@ -11,7 +11,9 @@ #include <config.h> extern void nand_init(void); +void nand_reinit(void); unsigned long nand_size(void); +unsigned int nand_page_size(void); #include <linux/compat.h> #include <linux/mtd/mtd.h> @@ -21,6 +23,7 @@ int nand_mtd_to_devnum(struct mtd_info *mtd); #if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) void board_nand_init(void); int nand_register(int devnum, struct mtd_info *mtd); +void nand_unregister(struct mtd_info *mtd); #else struct nand_chip; diff --git a/include/net.h b/include/net.h index e63a946002d..ac511eab103 100644 --- a/include/net.h +++ b/include/net.h @@ -930,4 +930,21 @@ void eth_set_enable_bootdevs(bool enable); static inline void eth_set_enable_bootdevs(bool enable) {} #endif +/** + * wget_with_dns() - runs dns host IP address resulution before wget + * + * @dst_addr: destination address to download the file + * @uri: uri string of target file of wget + * Return: downloaded file size, negative if failed + */ +int wget_with_dns(ulong dst_addr, char *uri); + +/** + * wget_validate_uri() - varidate the uri + * + * @uri: uri string of target file of wget + * Return: true if uri is valid, false if uri is invalid + */ +bool wget_validate_uri(char *uri); + #endif /* __NET_H__ */ diff --git a/include/net/ncsi.h b/include/net/ncsi.h index 2800c842b72..7aec457562d 100644 --- a/include/net/ncsi.h +++ b/include/net/ncsi.h @@ -5,7 +5,6 @@ * Copyright (C) 2019, IBM Corporation. */ -#include <common.h> #include <phy.h> bool ncsi_active(void); diff --git a/include/os.h b/include/os.h index fc8a1b15cbf..877404a6c13 100644 --- a/include/os.h +++ b/include/os.h @@ -109,6 +109,19 @@ int os_unlink(const char *pathname); int os_persistent_file(char *buf, int maxsize, const char *fname); /** + * os_mktemp() - Create a temporary file + * @fname: The template to use for the file name. This must end with 6 Xs. It + * will be modified to the opened filename on success. + * @size: The size of the file + * + * Create a temporary file using @fname as a template, unlink it, and truncate + * it to @size. + * + * Return: A file descriptor, or negative errno on error + */ +int os_mktemp(char *fname, off_t size); + +/** * os_exit() - access to the OS exit() system call * * This exits with the supplied return code, which should be 0 to indicate diff --git a/include/palmas.h b/include/palmas.h index e259a4d04ba..c13b67a84d9 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -6,7 +6,6 @@ #ifndef PALMAS_H #define PALMAS_H -#include <common.h> #include <i2c.h> /* I2C chip addresses, TW6035/37 */ diff --git a/include/pci_ids.h b/include/pci_ids.h index 88b0a640458..b63bf45168d 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1363,6 +1363,13 @@ #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6 +/* Per https://www.qemu.org/docs/master/specs/pci-ids.html */ +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 +#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d +#define PCI_DEVICE_ID_REDHAT_NVME 0x0010 +#define PCI_DEVICE_ID_REDHAT_UFS 0x0013 + #define PCI_VENDOR_ID_INIT 0x1101 #define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ diff --git a/include/post.h b/include/post.h index 6e88d550722..da851e37fa2 100644 --- a/include/post.h +++ b/include/post.h @@ -11,7 +11,6 @@ #define _POST_H #ifndef __ASSEMBLY__ -#include <common.h> #include <asm/io.h> #if defined(CONFIG_POST) diff --git a/include/sata.h b/include/sata.h index 6111cf65d9d..8414e77e42b 100644 --- a/include/sata.h +++ b/include/sata.h @@ -2,22 +2,6 @@ #define __SATA_H__ #include <part.h> -#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI) -int init_sata(int dev); -int reset_sata(int dev); -int scan_sata(int dev); -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer); -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer); - -int sata_initialize(void); -int __sata_initialize(void); -int sata_stop(void); -int __sata_stop(void); -int sata_port_status(int dev, int port); - -extern struct blk_desc sata_dev_desc[]; -#endif - int sata_probe(int devnum); int sata_remove(int devnum); diff --git a/include/scsi.h b/include/scsi.h index ee9d622680d..cf756aa62e1 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -10,10 +10,6 @@ #include <bouncebuf.h> #include <linux/dma-direction.h> -/* Fix this to the maximum */ -#define SCSI_MAX_DEVICE \ - (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) - struct udevice; /** @@ -355,11 +351,6 @@ int scsi_scan(bool verbose); */ int scsi_scan_dev(struct udevice *dev, bool verbose); -#ifndef CONFIG_DM_SCSI -void scsi_low_level_init(int busdevfunc); -void scsi_init(void); -#endif - #define SCSI_IDENTIFY 0xC0 /* not used */ /* Hardware errors */ diff --git a/include/spi.h b/include/spi.h index 1bc18e65525..7e38cc2a2ad 100644 --- a/include/spi.h +++ b/include/spi.h @@ -9,7 +9,6 @@ #ifndef _SPI_H_ #define _SPI_H_ -#include <common.h> #include <linux/bitops.h> /* SPI mode flags */ diff --git a/include/spl.h b/include/spl.h index 8ff20adc28e..09521889014 100644 --- a/include/spl.h +++ b/include/spl.h @@ -285,30 +285,53 @@ static inline void *spl_image_fdt_addr(struct spl_image_info *info) /** * Information required to load data from a device * - * @dev: Pointer to the device, e.g. struct mmc * * @priv: Private data for the device * @bl_len: Block length for reading in bytes - * @filename: Name of the fit image file. * @read: Function to call to read from the device */ struct spl_load_info { - void *dev; void *priv; - int bl_len; - const char *filename; /** * read() - Read from device * * @load: Information about the load state - * @sector: Sector number to read from (each @load->bl_len bytes) - * @count: Number of sectors to read + * @offset: Offset to read from in bytes. This must be a multiple of + * @load->bl_len. + * @count: Number of bytes to read. This must be a multiple of + * @load->bl_len. * @buf: Buffer to read into - * @return number of sectors read, 0 on error + * @return number of bytes read, 0 on error */ ulong (*read)(struct spl_load_info *load, ulong sector, ulong count, void *buf); +#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) + int bl_len; +}; + +static inline int spl_get_bl_len(struct spl_load_info *info) +{ + return info->bl_len; +} + +static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len) +{ + info->bl_len = bl_len; +} +#else }; +static inline int spl_get_bl_len(struct spl_load_info *info) +{ + return 1; +} + +static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len) +{ + if (bl_len != 1) + panic("CONFIG_SPL_LOAD_BLOCK not enabled"); +} +#endif + /* * We need to know the position of U-Boot in memory so we can jump to it. We * allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin, @@ -370,7 +393,8 @@ void *spl_load_simple_fit_fix_load(const void *fit); * spl_load_simple_fit() - Loads a fit image from a device. * @spl_image: Image description to set up * @info: Structure containing the information required to load data. - * @sector: Sector number where FIT image is located in the device + * @offset: Offset where FIT image is located in the device. Must be aligned + * to the device's bl_len. * @fdt: Pointer to the copied FIT header. * * Reads the FIT image @sector in the device. Loads u-boot image to @@ -378,12 +402,25 @@ void *spl_load_simple_fit_fix_load(const void *fit); * Returns 0 on success. */ int spl_load_simple_fit(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector, void *fdt); + struct spl_load_info *info, ulong offset, void *fdt); #define SPL_COPY_PAYLOAD_ONLY 1 #define SPL_FIT_FOUND 2 /** + * spl_load_legacy_lzma() - Load an LZMA-compressed legacy image + * @spl_image: Image description (already set up) + * @load: Structure containing the information required to load data. + * @offset: Pointer to image + * + * Load/decompress an LZMA-compressed legacy image from the device. + * + * Return: 0 on success, or a negative error on failure + */ +int spl_load_legacy_lzma(struct spl_image_info *spl_image, + struct spl_load_info *load, ulong offset); + +/** * spl_load_legacy_img() - Loads a legacy image from a device. * @spl_image: Image description to set up * @load: Structure containing the information required to load data. @@ -404,13 +441,14 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, * spl_load_imx_container() - Loads a imx container image from a device. * @spl_image: Image description to set up * @info: Structure containing the information required to load data. - * @sector: Sector number where container image is located in the device + * @sector: Offset where container image is located in the device. Must be + * aligned to the device block size. * * Reads the container image @sector in the device. Loads u-boot image to * specified load address. */ int spl_load_imx_container(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector); + struct spl_load_info *info, ulong offset); /* SPL common functions */ void preloader_console_init(void); diff --git a/include/spl_load.h b/include/spl_load.h new file mode 100644 index 00000000000..1c2b296c0a2 --- /dev/null +++ b/include/spl_load.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Sean Anderson <seanga2@gmail.com> + */ +#ifndef _SPL_LOAD_H_ +#define _SPL_LOAD_H_ + +#include <image.h> +#include <imx_container.h> +#include <mapmem.h> +#include <spl.h> + +static inline int _spl_load(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, + struct spl_load_info *info, size_t size, + size_t offset) +{ + struct legacy_img_hdr *header = + spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + ulong base_offset, image_offset, overhead; + int read, ret; + + read = info->read(info, offset, ALIGN(sizeof(*header), + spl_get_bl_len(info)), header); + if (read < sizeof(*header)) + return -EIO; + + if (image_get_magic(header) == FDT_MAGIC) { + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + void *buf; + + /* + * In order to support verifying images in the FIT, we + * need to load the whole FIT into memory. Try and + * guess how much we need to load by using the total + * size. This will fail for FITs with external data, + * but there's not much we can do about that. + */ + if (!size) + size = round_up(fdt_totalsize(header), 4); + buf = map_sysmem(CONFIG_SYS_LOAD_ADDR, size); + read = info->read(info, offset, + ALIGN(size, spl_get_bl_len(info)), + buf); + if (read < size) + return -EIO; + + return spl_parse_image_header(spl_image, bootdev, buf); + } + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) + return spl_load_simple_fit(spl_image, info, offset, + header); + } + + if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && + valid_container_hdr((void *)header)) + return spl_load_imx_container(spl_image, info, offset); + + if (IS_ENABLED(CONFIG_SPL_LZMA) && + image_get_magic(header) == IH_MAGIC && + image_get_comp(header) == IH_COMP_LZMA) { + spl_image->flags |= SPL_COPY_PAYLOAD_ONLY; + ret = spl_parse_image_header(spl_image, bootdev, header); + if (ret) + return ret; + + return spl_load_legacy_lzma(spl_image, info, offset); + } + + ret = spl_parse_image_header(spl_image, bootdev, header); + if (ret) + return ret; + + base_offset = spl_image->offset; + /* Only NOR sets this flag. */ + if (IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) && + spl_image->flags & SPL_COPY_PAYLOAD_ONLY) + base_offset += sizeof(*header); + image_offset = ALIGN_DOWN(base_offset, spl_get_bl_len(info)); + overhead = base_offset - image_offset; + size = ALIGN(spl_image->size + overhead, spl_get_bl_len(info)); + + read = info->read(info, offset + image_offset, size, + map_sysmem(spl_image->load_addr - overhead, size)); + return read < spl_image->size ? -EIO : 0; +} + +/* + * Although spl_load results in size reduction for callers, this is generally + * not enough to counteract the bloat if there is only one caller. The core + * problem is that the compiler can't optimize across translation units. The + * general solution to this is CONFIG_LTO, but that is not available on all + * architectures. Perform a pseudo-LTO just for this function by declaring it + * inline if there is one caller, and extern otherwise. + */ +#define SPL_LOAD_USERS \ + IS_ENABLED(CONFIG_SPL_BLK_FS) + \ + IS_ENABLED(CONFIG_SPL_FS_EXT4) + \ + IS_ENABLED(CONFIG_SPL_FS_FAT) + \ + IS_ENABLED(CONFIG_SPL_SYS_MMCSD_RAW_MODE) + \ + (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT) && !IS_ENABLED(CONFIG_SPL_UBI)) + \ + IS_ENABLED(CONFIG_SPL_NET) + \ + IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) + \ + IS_ENABLED(CONFIG_SPL_SEMIHOSTING) + \ + IS_ENABLED(CONFIG_SPL_SPI_LOAD) + \ + 0 + +#if SPL_LOAD_USERS > 1 +/** + * spl_load() - Parse a header and load the image + * @spl_image: Image data which will be filled in by this function + * @bootdev: The device to load from + * @info: Describes how to load additional information from @bootdev. At the + * minimum, read() and bl_len must be populated. + * @size: The size of the image, in bytes, if it is known in advance. Some boot + * devices (such as filesystems) know how big an image is before parsing + * the header. If 0, then the size will be determined from the header. + * @offset: The offset from the start of @bootdev, in bytes. This should have + * the offset @header was loaded from. It will be added to any offsets + * passed to @info->read(). + * + * This function determines the image type (FIT, legacy, i.MX, raw, etc), calls + * the appropriate parsing function, determines the load address, and the loads + * the image from storage. It is designed to replace ad-hoc image loading which + * may not support all image types (especially when config options are + * involved). + * + * Return: 0 on success, or a negative error on failure + */ +int spl_load(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, struct spl_load_info *info, + size_t size, size_t offset); +#else +static inline int spl_load(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, + struct spl_load_info *info, size_t size, + size_t offset) +{ + return _spl_load(spl_image, bootdev, info, size, offset); +} +#endif + +#endif /* _SPL_LOAD_H_ */ diff --git a/include/sysinfo.h b/include/sysinfo.h index b140d742e93..f2c1aa29d18 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -46,6 +46,9 @@ enum sysinfo_id { /* For show_board_info() */ SYSINFO_ID_BOARD_MODEL, + SYSINFO_ID_BOARD_MANUFACTURER, + SYSINFO_ID_PRIOR_STAGE_VERSION, + SYSINFO_ID_PRIOR_STAGE_DATE, /* First value available for downstream/board used */ SYSINFO_ID_USER = 0x1000, diff --git a/include/system-constants.h b/include/system-constants.h index 59371568d1e..d688629f119 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -41,4 +41,8 @@ #define SPL_PAYLOAD_ARGS_ADDR 0 #endif +/* Number of pages per block */ +#define SYS_NAND_BLOCK_PAGES \ + (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE) + #endif diff --git a/include/tegra-kbc.h b/include/tegra-kbc.h index f331c79c9d5..1208b75ee78 100644 --- a/include/tegra-kbc.h +++ b/include/tegra-kbc.h @@ -7,7 +7,6 @@ #ifndef __include_tegra_kbc_h__ #define __include_tegra_kbc_h__ -#include <common.h> #define KEY_IS_MODIFIER(key) ((key) >= KEY_FIRST_MODIFIER) diff --git a/include/test/cmd.h b/include/test/cmd.h new file mode 100644 index 00000000000..c200570e423 --- /dev/null +++ b/include/test/cmd.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __TEST_CMD_H__ +#define __TEST_CMD_H__ + +#include <test/test.h> + +/* Declare a new command test */ +#define CMD_TEST(_name, _flags) UNIT_TEST(_name, _flags, cmd_test) + +#endif /* __TEST_CMD_H__ */ diff --git a/include/test/spl.h b/include/test/spl.h index c1f64658502..a2a5f33e328 100644 --- a/include/test/spl.h +++ b/include/test/spl.h @@ -81,6 +81,10 @@ size_t create_image(void *dst, enum spl_test_image type, int check_image_info(struct unit_test_state *uts, struct spl_image_info *info1, struct spl_image_info *info2); +/* Some compressed data and it size */ +extern const char lzma_compressed[]; +extern const size_t lzma_compressed_size; + /** * typedef write_image_t - Callback for writing an image * @uts: Current unit test state diff --git a/include/test/suites.h b/include/test/suites.h index ad4fc926f48..49224d8ea2e 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -34,6 +34,7 @@ int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_bloblist(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_common(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_compression(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/include/test/ut.h b/include/test/ut.h index ea6ee95d734..d3172af8083 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -98,6 +98,23 @@ int ut_check_skipline(struct unit_test_state *uts); int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...); /** + * ut_check_skip_to_linen() - skip output until a partial line is found + * + * This creates a string and then checks it against the following lines of + * console output obtained with console_record_readline() until it is found. + * Only the characters up to the length of the string are checked, so the line + * may extend further + * + * After the function returns, uts->expect_str holds the expected string and + * uts->actual_str holds the actual string read from the console. + * + * @uts: Test state + * @fmt: printf() format string to look for, followed by args + * Return: 0 if OK, -ENOENT if not found, other value on error + */ +int ut_check_skip_to_linen(struct unit_test_state *uts, const char *fmt, ...); + +/** * ut_check_console_end() - Check there is no more console output * * After the function returns, uts->actual_str holds the actual string read @@ -359,6 +376,19 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes); __ret; \ }) +/* Assert that a following console output line matches */ +#define ut_assert_skip_to_linen(fmt, args...) ({ \ + int __ret = 0; \ + \ + if (ut_check_skip_to_linen(uts, fmt, ##args)) { \ + ut_failf(uts, __FILE__, __LINE__, __func__, \ + "console", "\nExpected '%s',\n got to '%s'", \ + uts->expect_str, uts->actual_str); \ + return CMD_RET_FAILURE; \ + } \ + __ret; \ +}) + /* Assert that there is no more console output */ #define ut_assert_console_end() ({ \ int __ret = 0; \ diff --git a/include/twl4030.h b/include/twl4030.h index 0a6d85a7c1c..ee80bb1f6b9 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -11,7 +11,6 @@ #ifndef TWL4030_H #define TWL4030_H -#include <common.h> #include <i2c.h> /* I2C chip addresses */ diff --git a/include/twl6030.h b/include/twl6030.h index 05d476f8048..e3a1058091a 100644 --- a/include/twl6030.h +++ b/include/twl6030.h @@ -7,7 +7,6 @@ #ifndef TWL6030_H #define TWL6030_H -#include <common.h> #include <i2c.h> /* I2C chip addresses */ diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 6da348eb628..d7a8851094b 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -14,7 +14,6 @@ #ifndef __UBOOT_UBI_H #define __UBOOT_UBI_H -#include <common.h> #include <compiler.h> #include <linux/compat.h> #include <malloc.h> diff --git a/include/usbdevice.h b/include/usbdevice.h index 80c5af0cbcd..e59f5587eea 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -17,7 +17,6 @@ #ifndef __USBDCORE_H__ #define __USBDCORE_H__ -#include <common.h> #include "usbdescriptors.h" diff --git a/lib/Kconfig b/lib/Kconfig index 19649517a39..37ac14f7bab 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -74,6 +74,13 @@ config HAVE_PRIVATE_LIBGCC config LIB_UUID bool +config RANDOM_UUID + bool "GPT Random UUID generation" + select LIB_UUID + help + Enable the generation of partitions with random UUIDs if none + are provided. + config SPL_LIB_UUID depends on SPL bool @@ -93,7 +100,7 @@ config SEMIHOSTING config SEMIHOSTING_FALLBACK bool "Recover gracefully when semihosting fails" - depends on SEMIHOSTING && (ARM64 || RISCV) + depends on SEMIHOSTING default y help Normally, if U-Boot makes a semihosting call and no debugger is @@ -116,7 +123,7 @@ config SPL_SEMIHOSTING config SPL_SEMIHOSTING_FALLBACK bool "Recover gracefully when semihosting fails in SPL" - depends on SPL_SEMIHOSTING && (ARM64 || RISCV) + depends on SPL_SEMIHOSTING select ARMV8_SPL_EXCEPTION_VECTORS if ARM64 default y help @@ -995,7 +1002,7 @@ config GENERATE_SMBIOS_TABLE Check http://www.dmtf.org/standards/smbios for details. - See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in + See also SYSINFO_SMBIOS which allows SMBIOS values to be provided in the devicetree. endmenu diff --git a/lib/acpi/acpi.c b/lib/acpi/acpi.c index 14b15754f49..f21e5094615 100644 --- a/lib/acpi/acpi.c +++ b/lib/acpi/acpi.c @@ -16,18 +16,30 @@ struct acpi_table_header *acpi_find_table(const char *sig) { struct acpi_rsdp *rsdp; struct acpi_rsdt *rsdt; + struct acpi_xsdt *xsdt; int len, i, count; rsdp = map_sysmem(gd_acpi_start(), 0); if (!rsdp) return NULL; - rsdt = map_sysmem(rsdp->rsdt_address, 0); - len = rsdt->header.length - sizeof(rsdt->header); - count = len / sizeof(u32); + if (rsdp->xsdt_address) { + xsdt = map_sysmem(rsdp->xsdt_address, 0); + len = xsdt->header.length - sizeof(xsdt->header); + count = len / sizeof(u64); + } else { + if (!rsdp->rsdt_address) + return NULL; + rsdt = map_sysmem(rsdp->rsdt_address, 0); + len = rsdt->header.length - sizeof(rsdt->header); + count = len / sizeof(u32); + } for (i = 0; i < count; i++) { struct acpi_table_header *hdr; - hdr = map_sysmem(rsdt->entry[i], 0); + if (rsdp->xsdt_address) + hdr = map_sysmem(xsdt->entry[i], 0); + else + hdr = map_sysmem(rsdt->entry[i], 0); if (!memcmp(hdr->signature, sig, ACPI_NAME_LEN)) return hdr; if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) { diff --git a/lib/acpi/base.c b/lib/acpi/base.c index 2057bd2bef8..26bf0cb8d30 100644 --- a/lib/acpi/base.c +++ b/lib/acpi/base.c @@ -12,6 +12,7 @@ #include <dm/acpi.h> #include <mapmem.h> #include <tables_csum.h> +#include <linux/sizes.h> void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, struct acpi_xsdt *xsdt) @@ -21,10 +22,13 @@ void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, memcpy(rsdp->signature, RSDP_SIG, 8); memcpy(rsdp->oem_id, OEM_ID, 6); - rsdp->length = sizeof(struct acpi_rsdp); - rsdp->rsdt_address = map_to_sysmem(rsdt); + if (rsdt) + rsdp->rsdt_address = map_to_sysmem(rsdt); + + if (xsdt) + rsdp->xsdt_address = map_to_sysmem(xsdt); - rsdp->xsdt_address = map_to_sysmem(xsdt); + rsdp->length = sizeof(struct acpi_rsdp); rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; /* Calculate checksums */ @@ -68,11 +72,15 @@ static void acpi_write_xsdt(struct acpi_xsdt *xsdt) static int acpi_write_base(struct acpi_ctx *ctx, const struct acpi_writer *entry) { - /* We need at least an RSDP and an RSDT Table */ + /* We need at least an RSDP and an XSDT Table */ ctx->rsdp = ctx->current; acpi_inc_align(ctx, sizeof(struct acpi_rsdp)); - ctx->rsdt = ctx->current; - acpi_inc_align(ctx, sizeof(struct acpi_rsdt)); + if (map_to_sysmem(ctx->current) < SZ_4G - SZ_64K) { + ctx->rsdt = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_rsdt)); + } else { + ctx->rsdt = 0; + } ctx->xsdt = ctx->current; acpi_inc_align(ctx, sizeof(struct acpi_xsdt)); @@ -80,7 +88,8 @@ static int acpi_write_base(struct acpi_ctx *ctx, memset(ctx->base, '\0', ctx->current - ctx->base); acpi_write_rsdp(ctx->rsdp, ctx->rsdt, ctx->xsdt); - acpi_write_rsdt(ctx->rsdt); + if (ctx->rsdt) + acpi_write_rsdt(ctx->rsdt); acpi_write_xsdt(ctx->xsdt); return 0; diff --git a/lib/acpi/ssdt.c b/lib/acpi/ssdt.c index 659c1aad406..b140b4b2ff6 100644 --- a/lib/acpi/ssdt.c +++ b/lib/acpi/ssdt.c @@ -18,10 +18,9 @@ int acpi_write_ssdt(struct acpi_ctx *ctx, const struct acpi_writer *entry) int ret; ssdt = ctx->current; - memset((void *)ssdt, '\0', sizeof(struct acpi_table_header)); + memset(ssdt, '\0', sizeof(struct acpi_table_header)); acpi_fill_header(ssdt, "SSDT"); - memcpy(ssdt->oem_table_id, OEM_TABLE_ID, sizeof(ssdt->oem_table_id)); ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT); ssdt->aslc_revision = 1; ssdt->length = sizeof(struct acpi_table_header); diff --git a/lib/efi/efi_app.c b/lib/efi/efi_app.c index 2209410f35b..c5eb816655e 100644 --- a/lib/efi/efi_app.c +++ b/lib/efi/efi_app.c @@ -12,18 +12,21 @@ #include <cpu_func.h> #include <debug_uart.h> #include <dm.h> +#include <efi.h> +#include <efi_api.h> #include <errno.h> #include <init.h> #include <malloc.h> +#include <sysreset.h> +#include <uuid.h> #include <asm/global_data.h> #include <linux/err.h> #include <linux/types.h> -#include <efi.h> -#include <efi_api.h> -#include <sysreset.h> +#include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <dm/root.h> +#include <mapmem.h> DECLARE_GLOBAL_DATA_PTR; @@ -320,6 +323,19 @@ int dm_scan_other(bool pre_reloc_only) return 0; } +static void scan_tables(struct efi_system_table *sys_table) +{ + efi_guid_t acpi = EFI_ACPI_TABLE_GUID; + uint i; + + for (i = 0; i < sys_table->nr_tables; i++) { + struct efi_configuration_table *tab = &sys_table->tables[i]; + + if (!memcmp(&tab->guid, &acpi, sizeof(efi_guid_t))) + gd_set_acpi_start(map_to_sysmem(tab->table)); + } +} + /** * efi_main() - Start an EFI image * @@ -354,6 +370,8 @@ efi_status_t EFIAPI efi_main(efi_handle_t image, return ret; } + scan_tables(priv->sys_table); + /* * We could store the EFI memory map here, but it changes all the time, * so this is only useful for debugging. diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 2e3935467c1..ea807342f02 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -32,14 +32,14 @@ config EFI_LOADER if EFI_LOADER -config CMD_BOOTEFI_BOOTMGR +config BOOTEFI_BOOTMGR bool "UEFI Boot Manager" default y select BOOTMETH_GLOBAL if BOOTSTD help Select this option if you want to select the UEFI binary to be booted - via UEFI variables Boot####, BootOrder, and BootNext. This enables the - 'bootefi bootmgr' command. + via UEFI variables Boot####, BootOrder, and BootNext. You should also + normally enable CMD_BOOTEFI_BOOTMGR so that the command is available. choice prompt "Store for non-volatile UEFI variables" @@ -479,4 +479,13 @@ config EFI_RISCV_BOOT_PROTOCOL replace the transfer via the device-tree. The latter is not possible on systems using ACPI. +config EFI_HTTP_BOOT + bool "EFI HTTP Boot support" + select CMD_DNS + select CMD_WGET + select BLKMAP + help + Enabling this option adds EFI HTTP Boot support. It allows to + directly boot from network. + endif diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 8d31fc61c60..24d33d54099 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -42,7 +42,7 @@ targets += initrddump.o endif obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o -obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += efi_bootmgr.o +obj-$(CONFIG_BOOTEFI_BOOTMGR) += efi_bootmgr.o obj-y += efi_boottime.o obj-y += efi_helper.o obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o @@ -51,9 +51,7 @@ obj-y += efi_console.o obj-y += efi_device_path.o obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o obj-$(CONFIG_EFI_DEVICE_PATH_UTIL) += efi_device_path_utilities.o -ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) obj-y += efi_dt_fixup.o -endif obj-y += efi_file.o obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o obj-y += efi_image_loader.o diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index a40762c74c8..e815fa06c8b 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -3,22 +3,56 @@ * EFI boot manager * * Copyright (c) 2017 Rob Clark + * For the code moved from cmd/bootefi.c + * Copyright (c) 2016 Alexander Graf */ #define LOG_CATEGORY LOGC_EFI +#include <blk.h> +#include <blkmap.h> #include <common.h> #include <charset.h> +#include <dm.h> #include <log.h> #include <malloc.h> +#include <net.h> #include <efi_default_filename.h> #include <efi_loader.h> #include <efi_variable.h> #include <asm/unaligned.h> +/* TODO: temporarily added here; clean up later */ +#include <bootm.h> +#include <efi_selftest.h> +#include <env.h> +#include <mapmem.h> +#include <asm/global_data.h> +#include <linux/libfdt.h> +#include <linux/libfdt_env.h> + +DECLARE_GLOBAL_DATA_PTR; + static const struct efi_boot_services *bs; static const struct efi_runtime_services *rs; +/** + * struct uridp_context - uri device path resource + * + * @image_size: image size + * @image_addr: image address + * @loaded_dp: pointer to loaded device path + * @ramdisk_blk_dev: pointer to the ramdisk blk device + * @mem_handle: efi_handle to the loaded PE-COFF image + */ +struct uridp_context { + ulong image_size; + ulong image_addr; + struct efi_device_path *loaded_dp; + struct udevice *ramdisk_blk_dev; + efi_handle_t mem_handle; +}; + const efi_guid_t efi_guid_bootmenu_auto_generated = EFICONFIG_AUTO_GENERATED_ENTRY_GUID; @@ -169,6 +203,364 @@ out: } /** + * mount_image() - mount the image with blkmap + * + * @lo_label: u16 label string of load option + * @addr: image address + * @size: image size + * Return: pointer to the UCLASS_BLK udevice, NULL if failed + */ +static struct udevice *mount_image(u16 *lo_label, ulong addr, ulong size) +{ + int err; + struct blkmap *bm; + struct udevice *bm_dev; + char *label = NULL, *p; + + label = efi_alloc(utf16_utf8_strlen(lo_label) + 1); + if (!label) + return NULL; + + p = label; + utf16_utf8_strcpy(&p, lo_label); + err = blkmap_create_ramdisk(label, addr, size, &bm_dev); + if (err) { + efi_free_pool(label); + return NULL; + } + bm = dev_get_plat(bm_dev); + + efi_free_pool(label); + + return bm->blk; +} + +/** + * search_default_file() - search default file + * + * @dev: pointer to the UCLASS_BLK or UCLASS_PARTITION udevice + * @loaded_dp: pointer to default file device path + * Return: status code + */ +static efi_status_t search_default_file(struct udevice *dev, + struct efi_device_path **loaded_dp) +{ + efi_status_t ret; + efi_handle_t handle; + u16 *default_file_name = NULL; + struct efi_file_handle *root, *f; + struct efi_device_path *dp = NULL, *fp = NULL; + struct efi_simple_file_system_protocol *file_system; + struct efi_device_path *device_path, *full_path = NULL; + + if (dev_tag_get_ptr(dev, DM_TAG_EFI, (void **)&handle)) { + log_warning("DM_TAG_EFI not found\n"); + return EFI_INVALID_PARAMETER; + } + + ret = EFI_CALL(bs->open_protocol(handle, &efi_guid_device_path, + (void **)&device_path, efi_root, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL)); + if (ret != EFI_SUCCESS) + return ret; + + ret = EFI_CALL(bs->open_protocol(handle, &efi_simple_file_system_protocol_guid, + (void **)&file_system, efi_root, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL)); + if (ret != EFI_SUCCESS) + return ret; + + ret = EFI_CALL(file_system->open_volume(file_system, &root)); + if (ret != EFI_SUCCESS) + return ret; + + full_path = expand_media_path(device_path); + ret = efi_dp_split_file_path(full_path, &dp, &fp); + if (ret != EFI_SUCCESS) + goto err; + + default_file_name = efi_dp_str(fp); + efi_free_pool(dp); + efi_free_pool(fp); + if (!default_file_name) { + ret = EFI_OUT_OF_RESOURCES; + goto err; + } + + ret = EFI_CALL(root->open(root, &f, default_file_name, + EFI_FILE_MODE_READ, 0)); + efi_free_pool(default_file_name); + if (ret != EFI_SUCCESS) + goto err; + + EFI_CALL(f->close(f)); + EFI_CALL(root->close(root)); + + *loaded_dp = full_path; + + return EFI_SUCCESS; + +err: + EFI_CALL(root->close(root)); + efi_free_pool(full_path); + + return ret; +} + +/** + * check_disk_has_default_file() - load the default file + * + * @blk: pointer to the UCLASS_BLK udevice + * @dp: pointer to default file device path + * Return: status code + */ +static efi_status_t check_disk_has_default_file(struct udevice *blk, + struct efi_device_path **dp) +{ + efi_status_t ret; + struct udevice *partition; + + /* image that has no partition table but a file system */ + ret = search_default_file(blk, dp); + if (ret == EFI_SUCCESS) + return ret; + + /* try the partitions */ + device_foreach_child(partition, blk) { + enum uclass_id id; + + id = device_get_uclass_id(partition); + if (id != UCLASS_PARTITION) + continue; + + ret = search_default_file(partition, dp); + if (ret == EFI_SUCCESS) + return ret; + } + + return EFI_NOT_FOUND; +} + +/** + * prepare_loaded_image() - prepare ramdisk for downloaded image + * + * @label: label of load option + * @addr: image address + * @size: image size + * @dp: pointer to default file device path + * @blk: pointer to created blk udevice + * Return: status code + */ +static efi_status_t prepare_loaded_image(u16 *label, ulong addr, ulong size, + struct efi_device_path **dp, + struct udevice **blk) +{ + efi_status_t ret; + struct udevice *ramdisk_blk; + + ramdisk_blk = mount_image(label, addr, size); + if (!ramdisk_blk) + return EFI_LOAD_ERROR; + + ret = check_disk_has_default_file(ramdisk_blk, dp); + if (ret != EFI_SUCCESS) { + log_info("Cannot boot from downloaded image\n"); + goto err; + } + + /* + * TODO: expose the ramdisk to OS. + * Need to pass the ramdisk information by the architecture-specific + * methods such as 'pmem' device-tree node. + */ + ret = efi_add_memory_map(addr, size, EFI_RESERVED_MEMORY_TYPE); + if (ret != EFI_SUCCESS) { + log_err("Memory reservation failed\n"); + goto err; + } + + *blk = ramdisk_blk; + + return EFI_SUCCESS; + +err: + if (blkmap_destroy(ramdisk_blk->parent)) + log_err("Destroying blkmap failed\n"); + + return ret; +} + +/** + * efi_bootmgr_release_uridp_resource() - cleanup uri device path resource + * + * @ctx: event context + * Return: status code + */ +efi_status_t efi_bootmgr_release_uridp_resource(struct uridp_context *ctx) +{ + efi_status_t ret = EFI_SUCCESS; + + if (!ctx) + return ret; + + /* cleanup for iso or img image */ + if (ctx->ramdisk_blk_dev) { + ret = efi_add_memory_map(ctx->image_addr, ctx->image_size, + EFI_CONVENTIONAL_MEMORY); + if (ret != EFI_SUCCESS) + log_err("Reclaiming memory failed\n"); + + if (blkmap_destroy(ctx->ramdisk_blk_dev->parent)) { + log_err("Destroying blkmap failed\n"); + ret = EFI_DEVICE_ERROR; + } + } + + /* cleanup for PE-COFF image */ + if (ctx->mem_handle) { + ret = efi_uninstall_multiple_protocol_interfaces( + ctx->mem_handle, &efi_guid_device_path, ctx->loaded_dp, + NULL); + if (ret != EFI_SUCCESS) + log_err("Uninstall device_path protocol failed\n"); + } + + efi_free_pool(ctx->loaded_dp); + free(ctx); + + return ret; +} + +/** + * efi_bootmgr_image_return_notify() - return to efibootmgr callback + * + * @event: the event for which this notification function is registered + * @context: event context + */ +static void EFIAPI efi_bootmgr_image_return_notify(struct efi_event *event, + void *context) +{ + efi_status_t ret; + + EFI_ENTRY("%p, %p", event, context); + ret = efi_bootmgr_release_uridp_resource(context); + EFI_EXIT(ret); +} + +/** + * try_load_from_uri_path() - Handle the URI device path + * + * @uridp: uri device path + * @lo_label: label of load option + * @handle: pointer to handle for newly installed image + * Return: status code + */ +static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp, + u16 *lo_label, + efi_handle_t *handle) +{ + char *s; + int err; + int uri_len; + efi_status_t ret; + void *source_buffer; + efi_uintn_t source_size; + struct uridp_context *ctx; + struct udevice *blk = NULL; + struct efi_event *event = NULL; + efi_handle_t mem_handle = NULL; + struct efi_device_path *loaded_dp; + static ulong image_size, image_addr; + + ctx = calloc(1, sizeof(struct uridp_context)); + if (!ctx) + return EFI_OUT_OF_RESOURCES; + + s = env_get("loadaddr"); + if (!s) { + log_err("Error: loadaddr is not set\n"); + ret = EFI_INVALID_PARAMETER; + goto err; + } + + image_addr = hextoul(s, NULL); + err = wget_with_dns(image_addr, uridp->uri); + if (err < 0) { + ret = EFI_INVALID_PARAMETER; + goto err; + } + + image_size = env_get_hex("filesize", 0); + if (!image_size) { + ret = EFI_INVALID_PARAMETER; + goto err; + } + + /* + * If the file extension is ".iso" or ".img", mount it and try to load + * the default file. + * If the file is PE-COFF image, load the downloaded file. + */ + uri_len = strlen(uridp->uri); + if (!strncmp(&uridp->uri[uri_len - 4], ".iso", 4) || + !strncmp(&uridp->uri[uri_len - 4], ".img", 4)) { + ret = prepare_loaded_image(lo_label, image_addr, image_size, + &loaded_dp, &blk); + if (ret != EFI_SUCCESS) + goto err; + + source_buffer = NULL; + source_size = 0; + } else if (efi_check_pe((void *)image_addr, image_size, NULL) == EFI_SUCCESS) { + /* + * loaded_dp must exist until efi application returns, + * will be freed in return_to_efibootmgr event callback. + */ + loaded_dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, + (uintptr_t)image_addr, image_size); + ret = efi_install_multiple_protocol_interfaces( + &mem_handle, &efi_guid_device_path, loaded_dp, NULL); + if (ret != EFI_SUCCESS) + goto err; + + source_buffer = (void *)image_addr; + source_size = image_size; + } else { + log_err("Error: file type is not supported\n"); + ret = EFI_UNSUPPORTED; + goto err; + } + + ctx->image_size = image_size; + ctx->image_addr = image_addr; + ctx->loaded_dp = loaded_dp; + ctx->ramdisk_blk_dev = blk; + ctx->mem_handle = mem_handle; + + ret = EFI_CALL(efi_load_image(false, efi_root, loaded_dp, source_buffer, + source_size, handle)); + if (ret != EFI_SUCCESS) + goto err; + + /* create event for cleanup when the image returns or error occurs */ + ret = efi_create_event(EVT_NOTIFY_SIGNAL, TPL_CALLBACK, + efi_bootmgr_image_return_notify, ctx, + &efi_guid_event_group_return_to_efibootmgr, + &event); + if (ret != EFI_SUCCESS) { + log_err("Creating event failed\n"); + goto err; + } + + return ret; + +err: + efi_bootmgr_release_uridp_resource(ctx); + + return ret; +} + +/** * try_load_entry() - try to load image for boot option * * Attempt to load load-option number 'n', returning device_path and file_path @@ -211,6 +603,13 @@ static efi_status_t try_load_entry(u16 n, efi_handle_t *handle, if (EFI_DP_TYPE(lo.file_path, MEDIA_DEVICE, FILE_PATH)) { /* file_path doesn't contain a device path */ ret = try_load_from_short_path(lo.file_path, handle); + } else if (EFI_DP_TYPE(lo.file_path, MESSAGING_DEVICE, MSG_URI)) { + if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT)) + ret = try_load_from_uri_path( + (struct efi_device_path_uri *)lo.file_path, + lo.label, handle); + else + ret = EFI_LOAD_ERROR; } else { file_path = expand_media_path(lo.file_path); ret = EFI_CALL(efi_load_image(true, efi_root, file_path, @@ -729,3 +1128,515 @@ out: return EFI_SUCCESS; return ret; } + +static struct efi_device_path *bootefi_image_path; +static struct efi_device_path *bootefi_device_path; +static void *image_addr; +static size_t image_size; + +/** + * efi_get_image_parameters() - return image parameters + * + * @img_addr: address of loaded image in memory + * @img_size: size of loaded image + */ +void efi_get_image_parameters(void **img_addr, size_t *img_size) +{ + *img_addr = image_addr; + *img_size = image_size; +} + +/** + * efi_clear_bootdev() - clear boot device + */ +void efi_clear_bootdev(void) +{ + efi_free_pool(bootefi_device_path); + efi_free_pool(bootefi_image_path); + bootefi_device_path = NULL; + bootefi_image_path = NULL; + image_addr = NULL; + image_size = 0; +} + +/** + * efi_set_bootdev() - set boot device + * + * This function is called when a file is loaded, e.g. via the 'load' command. + * We use the path to this file to inform the UEFI binary about the boot device. + * + * @dev: device, e.g. "MMC" + * @devnr: number of the device, e.g. "1:2" + * @path: path to file loaded + * @buffer: buffer with file loaded + * @buffer_size: size of file loaded + */ +void efi_set_bootdev(const char *dev, const char *devnr, const char *path, + void *buffer, size_t buffer_size) +{ + struct efi_device_path *device, *image; + efi_status_t ret; + + log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev, + devnr, path, buffer, buffer_size); + + /* Forget overwritten image */ + if (buffer + buffer_size >= image_addr && + image_addr + image_size >= buffer) + efi_clear_bootdev(); + + /* Remember only PE-COFF and FIT images */ + if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) { + if (IS_ENABLED(CONFIG_FIT) && + !fit_check_format(buffer, IMAGE_SIZE_INVAL)) { + /* + * FIT images of type EFI_OS are started via command + * bootm. We should not use their boot device with the + * bootefi command. + */ + buffer = 0; + buffer_size = 0; + } else { + log_debug("- not remembering image\n"); + return; + } + } + + /* efi_set_bootdev() is typically called repeatedly, recover memory */ + efi_clear_bootdev(); + + image_addr = buffer; + image_size = buffer_size; + + ret = efi_dp_from_name(dev, devnr, path, &device, &image); + if (ret == EFI_SUCCESS) { + bootefi_device_path = device; + if (image) { + /* FIXME: image should not contain device */ + struct efi_device_path *image_tmp = image; + + efi_dp_split_file_path(image, &device, &image); + efi_free_pool(image_tmp); + } + bootefi_image_path = image; + log_debug("- boot device %pD\n", device); + if (image) + log_debug("- image %pD\n", image); + } else { + log_debug("- efi_dp_from_name() failed, err=%lx\n", ret); + efi_clear_bootdev(); + } +} + +/** + * efi_env_set_load_options() - set load options from environment variable + * + * @handle: the image handle + * @env_var: name of the environment variable + * @load_options: pointer to load options (output) + * Return: status code + */ +efi_status_t efi_env_set_load_options(efi_handle_t handle, + const char *env_var, + u16 **load_options) +{ + const char *env = env_get(env_var); + size_t size; + u16 *pos; + efi_status_t ret; + + *load_options = NULL; + if (!env) + return EFI_SUCCESS; + size = sizeof(u16) * (utf8_utf16_strlen(env) + 1); + pos = calloc(size, 1); + if (!pos) + return EFI_OUT_OF_RESOURCES; + *load_options = pos; + utf8_utf16_strcpy(&pos, env); + ret = efi_set_load_options(handle, size, *load_options); + if (ret != EFI_SUCCESS) { + free(*load_options); + *load_options = NULL; + } + return ret; +} + +/** + * copy_fdt() - Copy the device tree to a new location available to EFI + * + * The FDT is copied to a suitable location within the EFI memory map. + * Additional 12 KiB are added to the space in case the device tree needs to be + * expanded later with fdt_open_into(). + * + * @fdtp: On entry a pointer to the flattened device tree. + * On exit a pointer to the copy of the flattened device tree. + * FDT start + * Return: status code + */ +static efi_status_t copy_fdt(void **fdtp) +{ + unsigned long fdt_ram_start = -1L, fdt_pages; + efi_status_t ret = 0; + void *fdt, *new_fdt; + u64 new_fdt_addr; + uint fdt_size; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + u64 ram_start = gd->bd->bi_dram[i].start; + u64 ram_size = gd->bd->bi_dram[i].size; + + if (!ram_size) + continue; + + if (ram_start < fdt_ram_start) + fdt_ram_start = ram_start; + } + + /* + * Give us at least 12 KiB of breathing room in case the device tree + * needs to be expanded later. + */ + fdt = *fdtp; + fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000); + fdt_size = fdt_pages << EFI_PAGE_SHIFT; + + ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, + EFI_ACPI_RECLAIM_MEMORY, fdt_pages, + &new_fdt_addr); + if (ret != EFI_SUCCESS) { + log_err("ERROR: Failed to reserve space for FDT\n"); + goto done; + } + new_fdt = (void *)(uintptr_t)new_fdt_addr; + memcpy(new_fdt, fdt, fdt_totalsize(fdt)); + fdt_set_totalsize(new_fdt, fdt_size); + + *fdtp = (void *)(uintptr_t)new_fdt_addr; +done: + return ret; +} + +/** + * get_config_table() - get configuration table + * + * @guid: GUID of the configuration table + * Return: pointer to configuration table or NULL + */ +static void *get_config_table(const efi_guid_t *guid) +{ + size_t i; + + for (i = 0; i < systab.nr_tables; i++) { + if (!guidcmp(guid, &systab.tables[i].guid)) + return systab.tables[i].table; + } + return NULL; +} + +/** + * efi_install_fdt() - install device tree + * + * If fdt is not EFI_FDT_USE_INTERNAL, the device tree located at that memory + * address will be installed as configuration table, otherwise the device + * tree located at the address indicated by environment variable fdt_addr or as + * fallback fdtcontroladdr will be used. + * + * On architectures using ACPI tables device trees shall not be installed as + * configuration table. + * + * @fdt: address of device tree or EFI_FDT_USE_INTERNAL to use + * the hardware device tree as indicated by environment variable + * fdt_addr or as fallback the internal device tree as indicated by + * the environment variable fdtcontroladdr + * Return: status code + */ +efi_status_t efi_install_fdt(void *fdt) +{ + struct bootm_headers img = { 0 }; + efi_status_t ret; + + /* + * The EBBR spec requires that we have either an FDT or an ACPI table + * but not both. + */ + if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt) + log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n"); + + if (fdt == EFI_FDT_USE_INTERNAL) { + const char *fdt_opt; + uintptr_t fdt_addr; + + /* Look for device tree that is already installed */ + if (get_config_table(&efi_guid_fdt)) + return EFI_SUCCESS; + /* Check if there is a hardware device tree */ + fdt_opt = env_get("fdt_addr"); + /* Use our own device tree as fallback */ + if (!fdt_opt) { + fdt_opt = env_get("fdtcontroladdr"); + if (!fdt_opt) { + log_err("ERROR: need device tree\n"); + return EFI_NOT_FOUND; + } + } + fdt_addr = hextoul(fdt_opt, NULL); + if (!fdt_addr) { + log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n"); + return EFI_LOAD_ERROR; + } + fdt = map_sysmem(fdt_addr, 0); + } + + /* Install device tree */ + if (fdt_check_header(fdt)) { + log_err("ERROR: invalid device tree\n"); + return EFI_LOAD_ERROR; + } + + /* Create memory reservations as indicated by the device tree */ + efi_carve_out_dt_rsv(fdt); + + if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) + return EFI_SUCCESS; + + /* Prepare device tree for payload */ + ret = copy_fdt(&fdt); + if (ret) { + log_err("ERROR: out of memory\n"); + return EFI_OUT_OF_RESOURCES; + } + + if (image_setup_libfdt(&img, fdt, NULL)) { + log_err("ERROR: failed to process device tree\n"); + return EFI_LOAD_ERROR; + } + + efi_try_purge_kaslr_seed(fdt); + + if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) { + ret = efi_tcg2_measure_dtb(fdt); + if (ret == EFI_SECURITY_VIOLATION) { + log_err("ERROR: failed to measure DTB\n"); + return ret; + } + } + + /* Install device tree as UEFI table */ + ret = efi_install_configuration_table(&efi_guid_fdt, fdt); + if (ret != EFI_SUCCESS) { + log_err("ERROR: failed to install device tree\n"); + return ret; + } + + return EFI_SUCCESS; +} + +/** + * do_bootefi_exec() - execute EFI binary + * + * The image indicated by @handle is started. When it returns the allocated + * memory for the @load_options is freed. + * + * @handle: handle of loaded image + * @load_options: load options + * Return: status code + * + * Load the EFI binary into a newly assigned memory unwinding the relocation + * information, install the loaded image protocol, and call the binary. + */ +static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options) +{ + efi_status_t ret; + efi_uintn_t exit_data_size = 0; + u16 *exit_data = NULL; + struct efi_event *evt; + + /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */ + switch_to_non_secure_mode(); + + /* + * The UEFI standard requires that the watchdog timer is set to five + * minutes when invoking an EFI boot option. + * + * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A + * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer + */ + ret = efi_set_watchdog(300); + if (ret != EFI_SUCCESS) { + log_err("ERROR: Failed to set watchdog timer\n"); + goto out; + } + + /* Call our payload! */ + ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data)); + if (ret != EFI_SUCCESS) { + log_err("## Application failed, r = %lu\n", + ret & ~EFI_ERROR_MASK); + if (exit_data) { + log_err("## %ls\n", exit_data); + efi_free_pool(exit_data); + } + } + + efi_restore_gd(); + +out: + free(load_options); + + if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) { + if (efi_initrd_deregister() != EFI_SUCCESS) + log_err("Failed to remove loadfile2 for initrd\n"); + } + + /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */ + list_for_each_entry(evt, &efi_events, link) { + if (evt->group && + !guidcmp(evt->group, + &efi_guid_event_group_return_to_efibootmgr)) { + efi_signal_event(evt); + EFI_CALL(systab.boottime->close_event(evt)); + break; + } + } + + /* Control is returned to U-Boot, disable EFI watchdog */ + efi_set_watchdog(0); + + return ret; +} + +/** + * efi_bootmgr_run() - execute EFI boot manager + * @fdt: Flat device tree + * + * Invoke EFI boot manager and execute a binary depending on + * boot options. If @fdt is not NULL, it will be passed to + * the executed binary. + * + * Return: status code + */ +efi_status_t efi_bootmgr_run(void *fdt) +{ + efi_handle_t handle; + void *load_options; + efi_status_t ret; + + /* Initialize EFI drivers */ + ret = efi_init_obj_list(); + if (ret != EFI_SUCCESS) { + log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n", + ret & ~EFI_ERROR_MASK); + return CMD_RET_FAILURE; + } + + ret = efi_install_fdt(fdt); + if (ret != EFI_SUCCESS) + return ret; + + ret = efi_bootmgr_load(&handle, &load_options); + if (ret != EFI_SUCCESS) { + log_notice("EFI boot manager: Cannot load any image\n"); + return ret; + } + + return do_bootefi_exec(handle, load_options); +} + +/** + * efi_run_image() - run loaded UEFI image + * + * @source_buffer: memory address of the UEFI image + * @source_size: size of the UEFI image + * Return: status code + */ +efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) +{ + efi_handle_t mem_handle = NULL, handle; + struct efi_device_path *file_path = NULL; + struct efi_device_path *msg_path; + efi_status_t ret, ret2; + u16 *load_options; + + if (!bootefi_device_path || !bootefi_image_path) { + log_debug("Not loaded from disk\n"); + /* + * Special case for efi payload not loaded from disk, + * such as 'bootefi hello' or for example payload + * loaded directly into memory via JTAG, etc: + */ + file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, + (uintptr_t)source_buffer, + source_size); + /* + * Make sure that device for device_path exist + * in load_image(). Otherwise, shell and grub will fail. + */ + ret = efi_install_multiple_protocol_interfaces(&mem_handle, + &efi_guid_device_path, + file_path, NULL); + if (ret != EFI_SUCCESS) + goto out; + msg_path = file_path; + } else { + file_path = efi_dp_append(bootefi_device_path, + bootefi_image_path); + msg_path = bootefi_image_path; + log_debug("Loaded from disk\n"); + } + + log_info("Booting %pD\n", msg_path); + + ret = EFI_CALL(efi_load_image(false, efi_root, file_path, source_buffer, + source_size, &handle)); + if (ret != EFI_SUCCESS) { + log_err("Loading image failed\n"); + goto out; + } + + /* Transfer environment variable as load options */ + ret = efi_env_set_load_options(handle, "bootargs", &load_options); + if (ret != EFI_SUCCESS) + goto out; + + ret = do_bootefi_exec(handle, load_options); + +out: + ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle, + &efi_guid_device_path, + file_path, NULL); + efi_free_pool(file_path); + return (ret != EFI_SUCCESS) ? ret : ret2; +} + +/** + * efi_binary_run() - run loaded UEFI image + * + * @image: memory address of the UEFI image + * @size: size of the UEFI image + * @fdt: device-tree + * + * Execute an EFI binary image loaded at @image. + * @size may be zero if the binary is loaded with U-Boot load command. + * + * Return: status code + */ +efi_status_t efi_binary_run(void *image, size_t size, void *fdt) +{ + efi_status_t ret; + + /* Initialize EFI drivers */ + ret = efi_init_obj_list(); + if (ret != EFI_SUCCESS) { + log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n", + ret & ~EFI_ERROR_MASK); + return -1; + } + + ret = efi_install_fdt(fdt); + if (ret != EFI_SUCCESS) + return ret; + + return efi_run_image(image, size); +} diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 0b7579cb5af..644bebee6b7 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -90,6 +90,9 @@ const efi_guid_t efi_guid_event_group_ready_to_boot = /* event group ResetSystem() invoked (before ExitBootServices) */ const efi_guid_t efi_guid_event_group_reset_system = EFI_EVENT_GROUP_RESET_SYSTEM; +/* event group return to efibootmgr */ +const efi_guid_t efi_guid_event_group_return_to_efibootmgr = + EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR; /* GUIDs of the Load File and Load File2 protocols */ const efi_guid_t efi_guid_load_file_protocol = EFI_LOAD_FILE_PROTOCOL_GUID; const efi_guid_t efi_guid_load_file2_protocol = EFI_LOAD_FILE2_PROTOCOL_GUID; @@ -712,7 +715,7 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( struct efi_event *event, void *context), - void *notify_context, efi_guid_t *group, + void *notify_context, const efi_guid_t *group, struct efi_event **event) { struct efi_event *evt; @@ -790,7 +793,7 @@ efi_status_t EFIAPI efi_create_event_ex(uint32_t type, efi_uintn_t notify_tpl, struct efi_event *event, void *context), void *notify_context, - efi_guid_t *event_group, + const efi_guid_t *event_group, struct efi_event **event) { efi_status_t ret; @@ -1339,7 +1342,7 @@ static efi_status_t efi_disconnect_all_drivers const efi_guid_t *protocol, efi_handle_t child_handle) { - efi_uintn_t number_of_drivers, tmp; + efi_uintn_t number_of_drivers; efi_handle_t *driver_handle_buffer; efi_status_t r, ret; @@ -1350,27 +1353,13 @@ static efi_status_t efi_disconnect_all_drivers if (!number_of_drivers) return EFI_SUCCESS; - tmp = number_of_drivers; while (number_of_drivers) { - ret = EFI_CALL(efi_disconnect_controller( + r = EFI_CALL(efi_disconnect_controller( handle, driver_handle_buffer[--number_of_drivers], child_handle)); - if (ret != EFI_SUCCESS) - goto reconnect; - } - - free(driver_handle_buffer); - return ret; - -reconnect: - /* Reconnect all disconnected drivers */ - for (; number_of_drivers < tmp; number_of_drivers++) { - r = EFI_CALL(efi_connect_controller(handle, - &driver_handle_buffer[number_of_drivers], - NULL, true)); if (r != EFI_SUCCESS) - EFI_PRINT("Failed to reconnect controller\n"); + ret = r; } free(driver_handle_buffer); @@ -1409,6 +1398,13 @@ static efi_status_t efi_uninstall_protocol r = efi_disconnect_all_drivers(handle, protocol, NULL); if (r != EFI_SUCCESS) { r = EFI_ACCESS_DENIED; + /* + * This will reconnect all controllers of the handle, even ones + * that were not connected before. This can be done better + * but we are following the EDKII implementation on this for + * now + */ + EFI_CALL(efi_connect_controller(handle, NULL, NULL, true)); goto out; } /* Close protocol */ diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index f0d76113b00..b808a7fe627 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -690,6 +690,13 @@ int efi_disk_probe(void *ctx, struct event *event) return -1; } + /* only do the boot option management when UEFI sub-system is initialized */ + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) && efi_obj_list_initialized == EFI_SUCCESS) { + ret = efi_bootmgr_update_media_device_boot_option(); + if (ret != EFI_SUCCESS) + return -1; + } + return 0; } @@ -742,6 +749,17 @@ int efi_disk_remove(void *ctx, struct event *event) dev_tag_del(dev, DM_TAG_EFI); return 0; + + /* + * TODO A flag to distinguish below 2 different scenarios of this + * function call is needed: + * a) Unplugging of a removable media under U-Boot + * b) U-Boot exiting and booting an OS + * In case of scenario a), efi_bootmgr_update_media_device_boot_option() + * needs to be invoked here to update the boot options and remove the + * unnecessary ones. + */ + } /** diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c index 838023c78ff..a0c889cf986 100644 --- a/lib/efi_loader/efi_dt_fixup.c +++ b/lib/efi_loader/efi_dt_fixup.c @@ -173,7 +173,7 @@ efi_dt_fixup(struct efi_dt_fixup_protocol *this, void *dtb, } fdt_set_totalsize(dtb, *buffer_size); - if (image_setup_libfdt(&img, dtb, 0, NULL)) { + if (image_setup_libfdt(&img, dtb, NULL)) { log_err("failed to process device tree\n"); ret = EFI_INVALID_PARAMETER; goto out; diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index e6de685e879..37359a77bbc 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -245,6 +245,13 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) { + /* update boot option after variable service initialized */ + ret = efi_bootmgr_update_media_device_boot_option(); + if (ret != EFI_SUCCESS) + goto out; + } + /* Define supported languages */ ret = efi_init_platform_lang(); if (ret != EFI_SUCCESS) diff --git a/lib/slre.c b/lib/slre.c index e82a9e7635b..e1a50443e04 100644 --- a/lib/slre.c +++ b/lib/slre.c @@ -686,6 +686,7 @@ int main(int argc, char *argv[]) } if (!slre_compile(&slre, argv[1])) { + (void) fclose(fp); fprintf(stderr, "Error compiling slre: %s\n", slre.err_str); return 1; } diff --git a/net/Kconfig b/net/Kconfig index 4215889127c..8c80b3a6c67 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -5,6 +5,7 @@ menuconfig NET bool "Networking support" default y + imply NETDEVICES if NET diff --git a/net/wget.c b/net/wget.c index 8bb4d72db1a..6ae2237a0a8 100644 --- a/net/wget.c +++ b/net/wget.c @@ -4,15 +4,20 @@ * Copyright Duncan Hare <dh@synoia.com> 2017 */ +#include <asm/global_data.h> #include <command.h> #include <common.h> #include <display_options.h> #include <env.h> #include <image.h> +#include <lmb.h> #include <mapmem.h> #include <net.h> #include <net/tcp.h> #include <net/wget.h> +#include <stdlib.h> + +DECLARE_GLOBAL_DATA_PTR; static const char bootfile1[] = "GET "; static const char bootfile3[] = " HTTP/1.0\r\n\r\n"; @@ -56,6 +61,29 @@ static unsigned int retry_tcp_ack_num; /* TCP retry acknowledge number*/ static unsigned int retry_tcp_seq_num; /* TCP retry sequence number */ static int retry_len; /* TCP retry length */ +static ulong wget_load_size; + +/** + * wget_init_max_size() - initialize maximum load size + * + * Return: 0 if success, -1 if fails + */ +static int wget_init_load_size(void) +{ + struct lmb lmb; + phys_size_t max_size; + + lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); + + max_size = lmb_get_free_size(&lmb, image_load_addr); + if (!max_size) + return -1; + + wget_load_size = max_size; + + return 0; +} + /** * store_block() - store block in memory * @src: source of data @@ -64,10 +92,25 @@ static int retry_len; /* TCP retry length */ */ static inline int store_block(uchar *src, unsigned int offset, unsigned int len) { + ulong store_addr = image_load_addr + offset; ulong newsize = offset + len; uchar *ptr; - ptr = map_sysmem(image_load_addr + offset, len); + if (IS_ENABLED(CONFIG_LMB)) { + ulong end_addr = image_load_addr + wget_load_size; + + if (!end_addr) + end_addr = ULONG_MAX; + + if (store_addr < image_load_addr || + store_addr + len > end_addr) { + printf("\nwget error: "); + printf("trying to overwrite reserved memory...\n"); + return -1; + } + } + + ptr = map_sysmem(store_addr, len); memcpy(ptr, src, len); unmap_sysmem(ptr); @@ -248,25 +291,39 @@ static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, net_boot_file_size = 0; - if (len > hlen) - store_block(pkt + hlen, 0, len - hlen); + if (len > hlen) { + if (store_block(pkt + hlen, 0, len - hlen) != 0) { + wget_loop_state = NETLOOP_FAIL; + wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action); + net_set_state(NETLOOP_FAIL); + return; + } + } debug_cond(DEBUG_WGET, "wget: Connected Pkt %p hlen %x\n", pkt, hlen); for (i = 0; i < pkt_q_idx; i++) { + int err; + ptr1 = map_sysmem( (phys_addr_t)(pkt_q[i].pkt), pkt_q[i].len); - store_block(ptr1, - pkt_q[i].tcp_seq_num - - initial_data_seq_num, - pkt_q[i].len); + err = store_block(ptr1, + pkt_q[i].tcp_seq_num - + initial_data_seq_num, + pkt_q[i].len); unmap_sysmem(ptr1); debug_cond(DEBUG_WGET, "wget: Connctd pkt Q %p len %x\n", pkt_q[i].pkt, pkt_q[i].len); + if (err) { + wget_loop_state = NETLOOP_FAIL; + wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action); + net_set_state(NETLOOP_FAIL); + return; + } } } } @@ -338,6 +395,7 @@ static void wget_handler(uchar *pkt, u16 dport, len) != 0) { wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action); + net_set_state(NETLOOP_FAIL); return; } @@ -428,6 +486,15 @@ void wget_start(void) debug_cond(DEBUG_WGET, "\nwget:Load address: 0x%lx\nLoading: *\b", image_load_addr); + if (IS_ENABLED(CONFIG_LMB)) { + if (wget_init_load_size()) { + printf("\nwget error: "); + printf("trying to overwrite reserved memory...\n"); + net_set_state(NETLOOP_FAIL); + return; + } + } + net_set_timeout_handler(wget_timeout, wget_timeout_handler); tcp_set_tcp_handler(wget_handler); @@ -446,3 +513,127 @@ void wget_start(void) wget_send(TCP_SYN, 0, 0, 0); } + +#if (IS_ENABLED(CONFIG_CMD_DNS)) +int wget_with_dns(ulong dst_addr, char *uri) +{ + int ret; + char *s, *host_name, *file_name, *str_copy; + + /* + * Download file using wget. + * + * U-Boot wget takes the target uri in this format. + * "<http server ip>:<file path>" e.g.) 192.168.1.1:/sample/test.iso + * Need to resolve the http server ip address before starting wget. + */ + str_copy = strdup(uri); + if (!str_copy) + return -ENOMEM; + + s = str_copy + strlen("http://"); + host_name = strsep(&s, "/"); + if (!s) { + log_err("Error: invalied uri, no file path\n"); + ret = -EINVAL; + goto out; + } + file_name = s; + + /* TODO: If the given uri has ip address for the http server, skip dns */ + net_dns_resolve = host_name; + net_dns_env_var = "httpserverip"; + if (net_loop(DNS) < 0) { + log_err("Error: dns lookup of %s failed, check setup\n", net_dns_resolve); + ret = -EINVAL; + goto out; + } + s = env_get("httpserverip"); + if (!s) { + ret = -EINVAL; + goto out; + } + + strlcpy(net_boot_file_name, s, sizeof(net_boot_file_name)); + strlcat(net_boot_file_name, ":/", sizeof(net_boot_file_name)); /* append '/' which is removed by strsep() */ + strlcat(net_boot_file_name, file_name, sizeof(net_boot_file_name)); + image_load_addr = dst_addr; + ret = net_loop(WGET); + +out: + free(str_copy); + + return ret; +} +#endif + +/** + * wget_validate_uri() - validate the uri for wget + * + * @uri: uri string + * + * This function follows the current U-Boot wget implementation. + * scheme: only "http:" is supported + * authority: + * - user information: not supported + * - host: supported + * - port: not supported(always use the default port) + * + * Uri is expected to be correctly percent encoded. + * This is the minimum check, control codes(0x1-0x19, 0x7F, except '\0') + * and space character(0x20) are not allowed. + * + * TODO: stricter uri conformance check + * + * Return: true on success, false on failure + */ +bool wget_validate_uri(char *uri) +{ + char c; + bool ret = true; + char *str_copy, *s, *authority; + + for (c = 0x1; c < 0x21; c++) { + if (strchr(uri, c)) { + log_err("invalid character is used\n"); + return false; + } + } + if (strchr(uri, 0x7f)) { + log_err("invalid character is used\n"); + return false; + } + + if (strncmp(uri, "http://", 7)) { + log_err("only http:// is supported\n"); + return false; + } + str_copy = strdup(uri); + if (!str_copy) + return false; + + s = str_copy + strlen("http://"); + authority = strsep(&s, "/"); + if (!s) { + log_err("invalid uri, no file path\n"); + ret = false; + goto out; + } + s = strchr(authority, '@'); + if (s) { + log_err("user information is not supported\n"); + ret = false; + goto out; + } + s = strchr(authority, ':'); + if (s) { + log_err("user defined port is not supported\n"); + ret = false; + goto out; + } + +out: + free(str_copy); + + return ret; +} diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8dc6ec82cd5..16bbc277a9f 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -339,7 +339,12 @@ cmd_capsule_esl_gen = \ $(shell sed "s:ESL_BIN_FILE:$(capsule_esl_path):" $(capsule_esl_input_file) > $@) $(obj)/.capsule_esl.dtsi: FORCE +ifeq ($(CONFIG_EFI_CAPSULE_ESL_FILE),"") + $(error "CONFIG_EFI_CAPSULE_ESL_FILE is empty, EFI capsule authentication \ + public key must be specified when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled") +else $(call cmd_capsule_esl_gen) +endif capsule_esl_input_file=$(srctree)/lib/efi_loader/capsule_esl.dtsi.in capsule_esl_dtsi = .capsule_esl.dtsi diff --git a/scripts/make_pip.sh b/scripts/make_pip.sh index 4602dcf61c8..d2639ffd6e4 100755 --- a/scripts/make_pip.sh +++ b/scripts/make_pip.sh @@ -29,6 +29,9 @@ repo="--repository testpypi" # Non-empty to do the actual upload upload=1 +# Non-empty to delete files used for testing +delete_testfiles=1 + tool="$1" shift flags="$*" @@ -36,7 +39,7 @@ flags="$*" if [[ "${tool}" =~ ^(patman|buildman|dtoc|binman|u_boot_pylib)$ ]]; then echo "Building dist package for tool ${tool}" else - echo "Unknown tool ${tool}: use patman, buildman, dtoc or binman" + echo "Unknown tool ${tool}: use u_boot_pylib, patman, buildman, dtoc or binman" exit 1 fi @@ -58,6 +61,11 @@ if [ -n "${upload}" ]; then fi fi +if [[ "${tool}" =~ ^(patman|u_boot_pylib)$ ]]; then + # Leave test_util.py and patman test files alone + delete_testfiles= +fi + # Create a temp dir to work in dir=$(mktemp -d) @@ -91,7 +99,9 @@ find ${dest} -name __pycache__ -type f -exec rm {} \; find ${dest} -depth -name __pycache__ -exec rmdir 112 \; # Remove test files -rm -rf ${dest}/*test* +if [ -n "${delete_testfiles}" ]; then + rm -rfv ${dest}/*test* +fi mkdir ${dir}/tests cd ${dir} diff --git a/test/Kconfig b/test/Kconfig index ca648d23376..e842c01308f 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -2,6 +2,7 @@ menu "Testing" config UNIT_TEST bool "Unit tests" + depends on CMDLINE help Select this to compile in unit tests for various parts of U-Boot. Test suites will be subcommands of the "ut" command. @@ -31,6 +32,7 @@ if UT_LIB config UT_LIB_ASN1 bool "Unit test for asn1 compiler and decoder function" + depends on SANDBOX default y imply ASYMMETRIC_KEY_TYPE imply ASYMMETRIC_PUBLIC_KEY_SUBTYPE @@ -63,6 +65,11 @@ config UT_LIB_RSA endif +config UT_BOOTSTD + bool "Unit tests for standard boot" + depends on UNIT_TEST && SANDBOX + default y + config UT_COMPRESSION bool "Unit test for compression" depends on UNIT_TEST diff --git a/test/Makefile b/test/Makefile index 8e1fed2c28b..6b8a1506f54 100644 --- a/test/Makefile +++ b/test/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_UT_TIME) += time_ut.o obj-y += ut.o ifeq ($(CONFIG_SPL_BUILD),) -obj-$(CONFIG_UNIT_TEST) += boot/ +obj-$(CONFIG_$(SPL_)UT_BOOTSTD) += boot/ obj-$(CONFIG_UNIT_TEST) += common/ obj-y += log/ obj-$(CONFIG_$(SPL_)UT_UNICODE) += unicode_ut.o diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index b97c566f000..f3e5a839da4 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -374,7 +374,7 @@ static int bootflow_system(struct unit_test_state *uts) { struct udevice *bootstd, *dev; - if (!IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) + if (!IS_ENABLED(CONFIG_BOOTEFI_BOOTMGR)) return -EAGAIN; ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd)); ut_assertok(device_bind(bootstd, DM_DRIVER_GET(bootmeth_efi_mgr), @@ -637,6 +637,88 @@ static int bootflow_cmd_menu(struct unit_test_state *uts) } BOOTSTD_TEST(bootflow_cmd_menu, UT_TESTF_DM | UT_TESTF_SCAN_FDT); +/* Check 'bootflow scan -m' to select a bootflow using a menu */ +static int bootflow_scan_menu(struct unit_test_state *uts) +{ + struct bootstd_priv *std; + const char **old_order, **new_order; + char prev[3]; + + /* get access to the current bootflow */ + ut_assertok(bootstd_get_priv(&std)); + + ut_assertok(prep_mmc_bootdev(uts, "mmc4", false, &old_order)); + + /* Add keypresses to move to and select the second one in the list */ + prev[0] = CTL_CH('n'); + prev[1] = '\r'; + prev[2] = '\0'; + ut_asserteq(2, console_in_puts(prev)); + + ut_assertok(run_command("bootflow scan -lm", 0)); + new_order = std->bootdev_order; + std->bootdev_order = old_order; + + ut_assert_skip_to_line("No more bootdevs"); + ut_assert_nextlinen("--"); + ut_assert_nextline("(2 bootflows, 2 valid)"); + + ut_assert_nextline("Selected: Armbian"); + ut_assertnonnull(std->cur_bootflow); + ut_assert_console_end(); + + /* Check not selecting anything */ + prev[0] = '\e'; + prev[1] = '\0'; + ut_asserteq(1, console_in_puts(prev)); + + std->bootdev_order = new_order; /* Blue Monday */ + ut_assertok(run_command("bootflow scan -lm", 0)); + std->bootdev_order = old_order; + + ut_assertnull(std->cur_bootflow); + ut_assert_skip_to_line("(2 bootflows, 2 valid)"); + ut_assert_nextline("Nothing chosen"); + ut_assert_console_end(); + + return 0; +} +BOOTSTD_TEST(bootflow_scan_menu, + UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC); + +/* Check 'bootflow scan -mb' to select and boot a bootflow using a menu */ +static int bootflow_scan_menu_boot(struct unit_test_state *uts) +{ + struct bootstd_priv *std; + const char **old_order; + char prev[3]; + + /* get access to the current bootflow */ + ut_assertok(bootstd_get_priv(&std)); + + ut_assertok(prep_mmc_bootdev(uts, "mmc4", false, &old_order)); + + /* Add keypresses to move to and select the second one in the list */ + prev[0] = CTL_CH('n'); + prev[1] = '\r'; + prev[2] = '\0'; + ut_asserteq(2, console_in_puts(prev)); + + ut_assertok(run_command("bootflow scan -lmb", 0)); + std->bootdev_order = old_order; + + ut_assert_skip_to_line("(2 bootflows, 2 valid)"); + + ut_assert_nextline("Selected: Armbian"); + ut_assert_skip_to_line("Boot failed (err=-14)"); + ut_assertnonnull(std->cur_bootflow); + ut_assert_console_end(); + + return 0; +} +BOOTSTD_TEST(bootflow_scan_menu_boot, + UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC); + /* Check searching for a single bootdev using the hunters */ static int bootflow_cmd_hunt_single(struct unit_test_state *uts) { diff --git a/test/cmd/Makefile b/test/cmd/Makefile index e296ba1192b..7e40e25b9e8 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -3,6 +3,8 @@ # Copyright (c) 2013 Google, Inc # Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> +obj-y += cmd_ut_cmd.o + ifdef CONFIG_HUSH_PARSER obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o endif diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 8c09281cac0..4977d01f62d 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -114,6 +114,18 @@ static int lmb_test_dump_region(struct unit_test_state *uts, end = base + size - 1; flags = rgn->region[i].flags; + /* + * this entry includes the stack (get_sp()) on many platforms + * so will different each time lmb_init_and_reserve() is called. + * We could instead have the bdinfo command put its lmb region + * in a known location, so we can check it directly, rather than + * calling lmb_init_and_reserve() to create a new (and hopefully + * identical one). But for now this seems good enough. + */ + if (!IS_ENABLED(CONFIG_SANDBOX) && i == 3) { + ut_assert_nextlinen(" %s[%d]\t[", name, i); + continue; + } ut_assert_nextline(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x", name, i, base, end, size, flags); } @@ -124,23 +136,17 @@ static int lmb_test_dump_region(struct unit_test_state *uts, static int lmb_test_dump_all(struct unit_test_state *uts, struct lmb *lmb) { ut_assert_nextline("lmb_dump_all:"); - lmb_test_dump_region(uts, &lmb->memory, "memory"); - lmb_test_dump_region(uts, &lmb->reserved, "reserved"); + ut_assertok(lmb_test_dump_region(uts, &lmb->memory, "memory")); + ut_assertok(lmb_test_dump_region(uts, &lmb->reserved, "reserved")); return 0; } -static int bdinfo_test_move(struct unit_test_state *uts) +static int bdinfo_check_mem(struct unit_test_state *uts) { struct bd_info *bd = gd->bd; int i; - /* Test moving the working BDINFO to a new location */ - ut_assertok(console_record_reset_enable()); - ut_assertok(run_commandf("bdinfo")); - - ut_assertok(test_num_l(uts, "boot_params", 0)); - for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { if (bd->bi_dram[i].size) { ut_assertok(test_num_l(uts, "DRAM bank", i)); @@ -151,6 +157,15 @@ static int bdinfo_test_move(struct unit_test_state *uts) } } + return 0; +} + +static int bdinfo_test_all(struct unit_test_state *uts) +{ + ut_assertok(test_num_l(uts, "boot_params", 0)); + + ut_assertok(bdinfo_check_mem(uts)); + /* CONFIG_SYS_HAS_SRAM testing not supported */ ut_assertok(test_num_l(uts, "flashstart", 0)); ut_assertok(test_num_l(uts, "flashsize", 0)); @@ -176,7 +191,7 @@ static int bdinfo_test_move(struct unit_test_state *uts) ut_assertok(test_num_l(uts, "fdt_size", (ulong)gd->fdt_size)); if (IS_ENABLED(CONFIG_VIDEO)) - test_video_info(uts); + ut_assertok(test_video_info(uts)); /* The gd->multi_dtb_fit may not be available, hence, #if below. */ #if CONFIG_IS_ENABLED(MULTI_DTB_FIT) @@ -187,7 +202,7 @@ static int bdinfo_test_move(struct unit_test_state *uts) struct lmb lmb; lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - lmb_test_dump_all(uts, &lmb); + ut_assertok(lmb_test_dump_all(uts, &lmb)); if (IS_ENABLED(CONFIG_OF_REAL)) ut_assert_nextline("devicetree = %s", fdtdec_get_srcname()); } @@ -212,12 +227,80 @@ static int bdinfo_test_move(struct unit_test_state *uts) ut_assertok(test_num_l(uts, "malloc base", gd_malloc_start())); } + if (IS_ENABLED(CONFIG_X86)) + ut_check_skip_to_linen(uts, " high end ="); + + return 0; +} + +static int bdinfo_test_full(struct unit_test_state *uts) +{ + /* Test BDINFO full print */ + ut_assertok(console_record_reset_enable()); + ut_assertok(run_commandf("bdinfo")); + ut_assertok(bdinfo_test_all(uts)); + ut_assertok(run_commandf("bdinfo -a")); + ut_assertok(bdinfo_test_all(uts)); + ut_assertok(ut_check_console_end(uts)); + + return 0; +} + +BDINFO_TEST(bdinfo_test_full, UT_TESTF_CONSOLE_REC); + +static int bdinfo_test_help(struct unit_test_state *uts) +{ + /* Test BDINFO unknown option help text print */ + ut_assertok(console_record_reset_enable()); + if (!CONFIG_IS_ENABLED(GETOPT)) { + ut_asserteq(0, run_commandf("bdinfo -h")); + ut_assertok(bdinfo_test_all(uts)); + } else { + ut_asserteq(1, run_commandf("bdinfo -h")); + ut_assert_nextlinen("bdinfo: invalid option -- h"); + ut_assert_nextlinen("bdinfo - print Board Info structure"); + ut_assert_nextline_empty(); + ut_assert_nextlinen("Usage:"); + ut_assert_nextlinen("bdinfo"); + } + ut_assertok(ut_check_console_end(uts)); + + return 0; +} + +BDINFO_TEST(bdinfo_test_help, UT_TESTF_CONSOLE_REC); + +static int bdinfo_test_memory(struct unit_test_state *uts) +{ + /* Test BDINFO memory layout only print */ + ut_assertok(console_record_reset_enable()); + ut_assertok(run_commandf("bdinfo -m")); + if (!CONFIG_IS_ENABLED(GETOPT)) + ut_assertok(bdinfo_test_all(uts)); + else + ut_assertok(bdinfo_check_mem(uts)); + ut_assertok(ut_check_console_end(uts)); + + return 0; +} + +BDINFO_TEST(bdinfo_test_memory, UT_TESTF_CONSOLE_REC); + +static int bdinfo_test_eth(struct unit_test_state *uts) +{ + /* Test BDINFO ethernet settings only print */ + ut_assertok(console_record_reset_enable()); + ut_assertok(run_commandf("bdinfo -e")); + if (!CONFIG_IS_ENABLED(GETOPT)) + ut_assertok(bdinfo_test_all(uts)); + else if (IS_ENABLED(CONFIG_CMD_NET)) + ut_assertok(test_eth(uts)); ut_assertok(ut_check_console_end(uts)); return 0; } -BDINFO_TEST(bdinfo_test_move, UT_TESTF_CONSOLE_REC); +BDINFO_TEST(bdinfo_test_eth, UT_TESTF_CONSOLE_REC); int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/test/cmd/cmd_ut_cmd.c b/test/cmd/cmd_ut_cmd.c new file mode 100644 index 00000000000..e77fa1c7f01 --- /dev/null +++ b/test/cmd/cmd_ut_cmd.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + * + * Unit tests for command functions + */ + +#include <command.h> +#include <test/cmd.h> +#include <test/suites.h> +#include <test/ut.h> + +int do_ut_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct unit_test *tests = UNIT_TEST_SUITE_START(cmd_test); + const int n_ents = UNIT_TEST_SUITE_COUNT(cmd_test); + + return cmd_ut_category("cmd", "cmd_test_", tests, n_ents, argc, argv); +} diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c index 1f103a1d7eb..54708552175 100644 --- a/test/cmd/fdt.c +++ b/test/cmd/fdt.c @@ -160,7 +160,13 @@ static int fdt_test_addr(struct unit_test_state *uts) set_working_fdt_addr(0); ut_assert_nextline("Working FDT set to 0"); ut_asserteq(CMD_RET_FAILURE, run_command("fdt addr", 0)); - ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC"); + + /* + * sandbox fails the check for !blob since the 0 pointer is mapped to + * memory somewhere other than at 0x0 + */ + if (IS_ENABLED(CONFIG_SANDBOX)) + ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC"); ut_assertok(ut_check_console_end(uts)); /* Set up a working FDT and try again */ diff --git a/test/cmd/font.c b/test/cmd/font.c index 40682e5ce49..1fe05c1ead5 100644 --- a/test/cmd/font.c +++ b/test/cmd/font.c @@ -30,13 +30,17 @@ static int font_test_base(struct unit_test_state *uts) ut_assertok(console_record_reset_enable()); ut_assertok(run_command("font list", 0)); ut_assert_nextline("nimbus_sans_l_regular"); - ut_assert_nextline("cantoraone_regular"); + if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE)) + ut_assert_nextline("cantoraone_regular"); ut_assertok(ut_check_console_end(uts)); ut_assertok(vidconsole_get_font_size(dev, &name, &size)); ut_asserteq_str("nimbus_sans_l_regular", name); ut_asserteq(18, size); + if (!IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE)) + return 0; + max_metrics = 1; if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE)) max_metrics = IF_ENABLED_INT(CONFIG_CONSOLE_TRUETYPE, diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 2d5b80f992e..1b934b23295 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -45,7 +45,7 @@ int cmd_ut_category(const char *name, const char *prefix, } ret = ut_run_list(name, prefix, tests, n_ents, - argc > 1 ? argv[1] : NULL, runs_per_text, force_run, + cmd_arg1(argc, argv), runs_per_text, force_run, test_insert); return ret ? CMD_RET_FAILURE : 0; @@ -57,10 +57,13 @@ static struct cmd_tbl cmd_ut_sub[] = { #ifdef CONFIG_CMD_BDI U_BOOT_CMD_MKENT(bdinfo, CONFIG_SYS_MAXARGS, 1, do_ut_bdinfo, "", ""), #endif -#ifdef CONFIG_BOOTSTD +#ifdef CONFIG_UT_BOOTSTD U_BOOT_CMD_MKENT(bootstd, CONFIG_SYS_MAXARGS, 1, do_ut_bootstd, "", ""), #endif +#ifdef CONFIG_CMDLINE + U_BOOT_CMD_MKENT(cmd, CONFIG_SYS_MAXARGS, 1, do_ut_cmd, "", ""), +#endif U_BOOT_CMD_MKENT(common, CONFIG_SYS_MAXARGS, 1, do_ut_common, "", ""), #if defined(CONFIG_UT_DM) U_BOOT_CMD_MKENT(dm, CONFIG_SYS_MAXARGS, 1, do_ut_dm, "", ""), @@ -195,6 +198,9 @@ U_BOOT_LONGHELP(ut, #ifdef CONFIG_BOOTSTD "\nbootstd - standard boot implementation" #endif +#ifdef CONFIG_CMDLINE + "\ncmd - test various commands" +#endif #ifdef CONFIG_SANDBOX "\ncompression - compressors and bootm decompression" #endif diff --git a/test/common/event.c b/test/common/event.c index c0912a3437b..b462694fc3b 100644 --- a/test/common/event.c +++ b/test/common/event.c @@ -92,6 +92,9 @@ static int test_event_probe(struct unit_test_state *uts) struct test_state state; struct udevice *dev; + if (!IS_ENABLED(SANDBOX)) + return -EAGAIN; + state.val = 0; ut_assertok(event_register("pre", EVT_DM_PRE_PROBE, h_probe, &state)); ut_assertok(event_register("post", EVT_DM_POST_PROBE, h_probe, &state)); diff --git a/test/dm/Makefile b/test/dm/Makefile index cb82d839f8a..a3ce7b3889f 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_CMD_MUX) += mux-cmd.o obj-$(CONFIG_MULTIPLEXER) += mux-emul.o obj-$(CONFIG_MUX_MMIO) += mux-mmio.o obj-y += fdtdec.o +obj-$(CONFIG_MTD_RAW_NAND) += nand.o obj-$(CONFIG_UT_DM) += nop.o obj-y += ofnode.o obj-y += ofread.o diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 5997bda649b..fb071902b45 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -395,26 +395,26 @@ static int dm_test_acpi_cmd_list(struct unit_test_state *uts) console_record_reset(); run_command("acpi list", 0); - ut_assert_nextline("Name Base Size Detail"); - ut_assert_nextline("---- -------- ----- ------"); - ut_assert_nextline("RSDP %08lx %5zx v02 U-BOOT", addr, + ut_assert_nextline("Name Base Size Detail"); + ut_assert_nextline("---- ---------------- ----- ----------------------------"); + ut_assert_nextline("RSDP %16lx %5zx v02 U-BOOT", addr, sizeof(struct acpi_rsdp)); addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16); - ut_assert_nextline("RSDT %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", + ut_assert_nextline("RSDT %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", addr, sizeof(struct acpi_table_header) + 3 * sizeof(u32), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16); - ut_assert_nextline("XSDT %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", + ut_assert_nextline("XSDT %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", addr, sizeof(struct acpi_table_header) + 3 * sizeof(u64), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64); - ut_assert_nextline("DMAR %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", + ut_assert_nextline("DMAR %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", addr, sizeof(struct acpi_dmar), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); - ut_assert_nextline("DMAR %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", + ut_assert_nextline("DMAR %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", addr, sizeof(struct acpi_dmar), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); - ut_assert_nextline("DMAR %08lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", + ut_assert_nextline("DMAR %16lx %5zx v01 U-BOOT U-BOOTBL %x INTL 0", addr, sizeof(struct acpi_dmar), OEM_REVISION); ut_assert_console_end(); @@ -446,7 +446,7 @@ static int dm_test_acpi_cmd_dump(struct unit_test_state *uts) console_record_reset(); run_command("acpi dump dmar", 0); addr = ALIGN(map_to_sysmem(ctx.xsdt) + sizeof(struct acpi_xsdt), 64); - ut_assert_nextline("DMAR @ %08lx", addr); + ut_assert_nextline("DMAR @ %16lx", addr); ut_assert_nextlines_are_dump(0x30); ut_assert_console_end(); @@ -651,3 +651,109 @@ static int dm_test_acpi_cmd_set(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_cmd_set, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/** + * dm_test_write_test_table() - create test ACPI table + * + * Create an ACPI table TSTn, where n is given by @index. + * + * @ctx: ACPI table writing context + * @index: table index + * Return: generated table + */ +static struct acpi_table_header +*dm_test_write_test_table(struct acpi_ctx *ctx, int index) +{ + struct acpi_table_header *tbl = ctx->current; + char signature[5]; + + snprintf(signature, sizeof(signature), "TST%1d", index); + memset(tbl, 0, sizeof(*tbl)); + acpi_fill_header(tbl, signature); + acpi_inc(ctx, sizeof(struct acpi_table_header)); + tbl->length = (u8 *)ctx->current - (u8 *)tbl; + tbl->checksum = table_compute_checksum(tbl, tbl->length); + acpi_add_table(ctx, tbl); + + return tbl; +} + +/* Test acpi_find_table() */ +static int dm_test_acpi_find_table(struct unit_test_state *uts) +{ + struct acpi_ctx ctx; + ulong acpi_start, addr; + void *buf; + struct acpi_table_header *table, *table1, *table2, *table3; + struct acpi_rsdp *rsdp; + ulong rsdt; + ulong xsdt; + + /* Keep reference to original ACPI tables */ + acpi_start = gd_acpi_start(); + + /* Setup new ACPI tables */ + buf = memalign(16, BUF_SIZE); + ut_assertnonnull(buf); + addr = map_to_sysmem(buf); + ut_assertok(setup_ctx_and_base_tables(uts, &ctx, addr)); + table3 = dm_test_write_test_table(&ctx, 3); + table1 = dm_test_write_test_table(&ctx, 1); + table2 = dm_test_write_test_table(&ctx, 2); + + /* Retrieve RSDP, RSDT, XSDT */ + rsdp = map_sysmem(gd_acpi_start(), 0); + ut_assertnonnull(rsdp); + rsdt = rsdp->rsdt_address; + ut_assert(rsdt); + xsdt = rsdp->xsdt_address; + ut_assert(xsdt); + + /* Find with both RSDT and XSDT */ + table = acpi_find_table("TST1"); + ut_asserteq_ptr(table1, table); + ut_asserteq_strn("TST1", table->signature); + table = acpi_find_table("TST2"); + ut_asserteq_ptr(table2, table); + ut_asserteq_strn("TST2", table->signature); + table = acpi_find_table("TST3"); + ut_asserteq_ptr(table3, table); + ut_asserteq_strn("TST3", table->signature); + + /* Find with XSDT only */ + rsdp->rsdt_address = 0; + table = acpi_find_table("TST1"); + ut_asserteq_ptr(table1, table); + table = acpi_find_table("TST2"); + ut_asserteq_ptr(table2, table); + table = acpi_find_table("TST3"); + ut_asserteq_ptr(table3, table); + rsdp->rsdt_address = rsdt; + + /* Find with RSDT only */ + rsdp->xsdt_address = 0; + table = acpi_find_table("TST1"); + ut_asserteq_ptr(table1, table); + table = acpi_find_table("TST2"); + ut_asserteq_ptr(table2, table); + table = acpi_find_table("TST3"); + ut_asserteq_ptr(table3, table); + rsdp->xsdt_address = xsdt; + + /* Restore previous ACPI tables */ + gd_set_acpi_start(acpi_start); + free(buf); + + return 0; +} +DM_TEST(dm_test_acpi_find_table, 0); + +/* Test offsets in RSDT, XSDT */ +static int dm_test_acpi_offsets(struct unit_test_state *uts) +{ + ut_asserteq(36, offsetof(struct acpi_rsdt, entry)); + ut_asserteq(36, offsetof(struct acpi_xsdt, entry)); + + return 0; +} +DM_TEST(dm_test_acpi_offsets, 0); diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index e4ebb93cdad..61dad8d8527 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -19,16 +19,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) { struct clk *clk, *pclk; - struct udevice *dev; + struct udevice *dev, *test_dev; long long rate; int ret; #if CONFIG_IS_ENABLED(CLK_CCF) + struct clk clk_ccf; const char *clkname; int clkid, i; #endif /* Get the device using the clk device */ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &test_dev)); /* Test for clk_get_by_id() */ ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk); @@ -63,6 +65,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_parent_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_set_rate(clk, 60000000); + ut_asserteq(rate, -ENOSYS); + rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); @@ -87,6 +92,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ut_asserteq_str("pll3_80m", pclk->dev->name); ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags); + rate = clk_set_rate(clk, 80000000); + ut_asserteq(rate, -ENOSYS); + rate = clk_get_rate(clk); ut_asserteq(rate, 80000000); @@ -108,13 +116,23 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_set_rate(clk, 60000000); + ut_asserteq(rate, 60000000); + #if CONFIG_IS_ENABLED(CLK_CCF) /* Test clk tree enable/disable */ + + ret = clk_get_by_index(test_dev, SANDBOX_CLK_TEST_ID_I2C_ROOT, &clk_ccf); + ut_assertok(ret); + ut_asserteq_str("clk-ccf", clk_ccf.dev->name); + ut_asserteq(clk_ccf.id, SANDBOX_CLK_I2C_ROOT); + ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk); ut_assertok(ret); ut_asserteq_str("i2c_root", clk->dev->name); + ut_asserteq(clk->id, SANDBOX_CLK_I2C_ROOT); - ret = clk_enable(clk); + ret = clk_enable(&clk_ccf); ut_assertok(ret); ret = sandbox_clk_enable_count(clk); diff --git a/test/dm/eth.c b/test/dm/eth.c index d05d2a9abe1..bb3dcc6b954 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -263,12 +263,16 @@ static int dm_test_eth_act(struct unit_test_state *uts) /* Prepare the test scenario */ for (i = 0; i < DM_TEST_ETH_NUM; i++) { + char *addr; + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, ethname[i], &dev[i])); ut_assertok(device_remove(dev[i], DM_REMOVE_NORMAL)); /* Invalidate MAC address */ - strncpy(ethaddr[i], env_get(addrname[i]), 17); + addr = env_get(addrname[i]); + ut_assertnonnull(addr); + strncpy(ethaddr[i], addr, 17); /* Must disable access protection for ethaddr before clearing */ env_set(".flags", addrname[i]); env_set(addrname[i], NULL); @@ -312,12 +316,16 @@ static int dm_test_ethaddr(struct unit_test_state *uts) for (i = 0; i < ARRAY_SIZE(addr); i++) { char addrname[10]; + char *env_addr; if (i) snprintf(addrname, sizeof(addrname), "eth%daddr", i + 1); else strcpy(addrname, "ethaddr"); - ut_asserteq_str(addr[i], env_get(addrname)); + + env_addr = env_get(addrname); + ut_assertnonnull(env_addr); + ut_asserteq_str(addr[i], env_addr); } return 0; diff --git a/test/dm/nand.c b/test/dm/nand.c new file mode 100644 index 00000000000..0b992fdce1c --- /dev/null +++ b/test/dm/nand.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com> + */ + +#include <nand.h> +#include <part.h> +#include <rand.h> +#include <dm/test.h> +#include <test/test.h> +#include <test/ut.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/rawnand.h> + +static int dm_test_nand(struct unit_test_state *uts, int dev, bool end) +{ + nand_erase_options_t opts = { }; + struct mtd_info *mtd; + size_t length; + loff_t size; + char *buf; + int *gold; + u8 oob[NAND_MAX_OOBSIZE]; + int i; + loff_t off = 0; + mtd_oob_ops_t ops = { }; + + /* Seed RNG for bit errors */ + srand((off >> 32) ^ off ^ ~dev); + + mtd = get_nand_dev_by_index(dev); + ut_assertnonnull(mtd); + size = mtd->erasesize * 4; + length = size; + + buf = malloc(size); + ut_assertnonnull(buf); + gold = malloc(size); + ut_assertnonnull(gold); + + /* Mark a block as bad */ + ut_assertok(mtd_block_markbad(mtd, off + mtd->erasesize)); + + /* Erase some stuff */ + if (end) + off = mtd->size - size - mtd->erasesize; + opts.offset = off; + opts.length = size; + opts.spread = 1; + opts.lim = U32_MAX; + ut_assertok(nand_erase_opts(mtd, &opts)); + + /* Make sure everything is erased */ + memset(gold, 0xff, size); + ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf)); + ut_asserteq(size, length); + ut_asserteq_mem(gold, buf, size); + + /* ...but our bad block marker is still there */ + ops.oobbuf = oob; + ops.ooblen = mtd->oobsize; + ut_assertok(mtd_read_oob(mtd, mtd->erasesize, &ops)); + ut_asserteq(0, oob[mtd_to_nand(mtd)->badblockpos]); + + /* Generate some data and write it */ + for (i = 0; i < size / sizeof(int); i++) + gold[i] = rand(); + ut_assertok(nand_write_skip_bad(mtd, off, &length, NULL, U64_MAX, + (void *)gold, 0)); + ut_asserteq(size, length); + + /* Verify */ + ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf)); + ut_asserteq(size, length); + ut_asserteq_mem(gold, buf, size); + + /* Erase some blocks */ + memset(((char *)gold) + mtd->erasesize, 0xff, mtd->erasesize * 2); + opts.offset = off + mtd->erasesize; + opts.length = mtd->erasesize * 2; + ut_assertok(nand_erase_opts(mtd, &opts)); + + /* Verify */ + ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf)); + ut_asserteq(size, length); + ut_asserteq_mem(gold, buf, size); + + return 0; +} + +#define DM_NAND_TEST(dev) \ +static int dm_test_nand##dev##_start(struct unit_test_state *uts) \ +{ \ + return dm_test_nand(uts, dev, false); \ +} \ +DM_TEST(dm_test_nand##dev##_start, UT_TESTF_SCAN_FDT); \ +static int dm_test_nand##dev##_end(struct unit_test_state *uts) \ +{ \ + return dm_test_nand(uts, dev, true); \ +} \ +DM_TEST(dm_test_nand##dev##_end, UT_TESTF_SCAN_FDT) + +DM_NAND_TEST(0); +DM_NAND_TEST(1); diff --git a/test/dm/scmi.c b/test/dm/scmi.c index da45314f2e4..e80667ef72a 100644 --- a/test/dm/scmi.c +++ b/test/dm/scmi.c @@ -19,6 +19,7 @@ #include <scmi_agent.h> #include <scmi_agent-uclass.h> #include <scmi_protocols.h> +#include <vsprintf.h> #include <asm/scmi_test.h> #include <dm/device-internal.h> #include <dm/test.h> @@ -206,6 +207,86 @@ static int dm_test_scmi_base(struct unit_test_state *uts) DM_TEST(dm_test_scmi_base, UT_TESTF_SCAN_FDT); +static int dm_test_scmi_cmd(struct unit_test_state *uts) +{ + struct udevice *agent_dev; + int num_proto = 0; + char cmd_out[30]; + + if (!CONFIG_IS_ENABLED(CMD_SCMI)) + return -EAGAIN; + + /* preparation */ + ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi", + &agent_dev)); + ut_assertnonnull(agent_dev); + + /* + * Estimate the number of provided protocols. + * This estimation is correct as far as a corresponding + * protocol support is added to sandbox fake serer. + */ + if (CONFIG_IS_ENABLED(POWER_DOMAIN)) + num_proto++; + if (CONFIG_IS_ENABLED(CLK_SCMI)) + num_proto++; + if (CONFIG_IS_ENABLED(RESET_SCMI)) + num_proto++; + if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI)) + num_proto++; + + /* scmi info */ + ut_assertok(run_command("scmi info", 0)); + + ut_assert_nextline("SCMI device: scmi"); + snprintf(cmd_out, 30, " protocol version: 0x%x", + SCMI_BASE_PROTOCOL_VERSION); + ut_assert_nextline(cmd_out); + ut_assert_nextline(" # of agents: 2"); + ut_assert_nextline(" 0: platform"); + ut_assert_nextline(" > 1: OSPM"); + snprintf(cmd_out, 30, " # of protocols: %d", num_proto); + ut_assert_nextline(cmd_out); + if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN)) + ut_assert_nextline(" Power domain management"); + if (CONFIG_IS_ENABLED(CLK_SCMI)) + ut_assert_nextline(" Clock management"); + if (CONFIG_IS_ENABLED(RESET_SCMI)) + ut_assert_nextline(" Reset domain management"); + if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI)) + ut_assert_nextline(" Voltage domain management"); + ut_assert_nextline(" vendor: U-Boot"); + ut_assert_nextline(" sub vendor: Sandbox"); + ut_assert_nextline(" impl version: 0x1"); + + ut_assert_console_end(); + + /* scmi perm_dev */ + ut_assertok(run_command("scmi perm_dev 1 0 1", 0)); + ut_assert_console_end(); + + ut_assert(run_command("scmi perm_dev 1 0 0", 0)); + ut_assert_nextline("Denying access to device:0 failed (-13)"); + ut_assert_console_end(); + + /* scmi perm_proto */ + ut_assertok(run_command("scmi perm_proto 1 0 14 1", 0)); + ut_assert_console_end(); + + ut_assert(run_command("scmi perm_proto 1 0 14 0", 0)); + ut_assert_nextline("Denying access to protocol:0x14 on device:0 failed (-13)"); + ut_assert_console_end(); + + /* scmi reset */ + ut_assert(run_command("scmi reset 1 1", 0)); + ut_assert_nextline("Reset failed (-13)"); + ut_assert_console_end(); + + return 0; +} + +DM_TEST(dm_test_scmi_cmd, UT_TESTF_SCAN_FDT); + static int dm_test_scmi_power_domains(struct unit_test_state *uts) { struct sandbox_scmi_agent *agent; @@ -217,6 +298,9 @@ static int dm_test_scmi_power_domains(struct unit_test_state *uts) u8 *name; int ret; + if (!CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN)) + return -EAGAIN; + /* preparation */ ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev)); ut_assertnonnull(agent); @@ -317,6 +401,9 @@ static int dm_test_scmi_clocks(struct unit_test_state *uts) int ret_dev; int ret; + if (!CONFIG_IS_ENABLED(CLK_SCMI)) + return -EAGAIN; + ret = load_sandbox_scmi_test_devices(uts, &agent, &dev); if (ret) return ret; @@ -382,6 +469,9 @@ static int dm_test_scmi_resets(struct unit_test_state *uts) struct udevice *agent_dev, *reset_dev, *dev = NULL; int ret; + if (!CONFIG_IS_ENABLED(RESET_SCMI)) + return -EAGAIN; + ret = load_sandbox_scmi_test_devices(uts, &agent, &dev); if (ret) return ret; @@ -418,6 +508,9 @@ static int dm_test_scmi_voltage_domains(struct unit_test_state *uts) struct udevice *dev; struct udevice *regul0_dev; + if (!CONFIG_IS_ENABLED(DM_REGULATOR_SCMI)) + return -EAGAIN; + ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev)); scmi_devices = sandbox_scmi_devices_ctx(dev); diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c index 691683c5674..5aa69e04618 100644 --- a/test/dm/sysreset.c +++ b/test/dm/sysreset.c @@ -27,8 +27,8 @@ static int dm_test_sysreset_base(struct unit_test_state *uts) /* Device 1 is the warm sysreset device */ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev)); ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM)); - ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD)); - ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER)); + ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_COLD)); + ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_POWER)); state->sysreset_allowed[SYSRESET_WARM] = true; ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM)); @@ -36,7 +36,7 @@ static int dm_test_sysreset_base(struct unit_test_state *uts) /* Device 2 is the cold sysreset device */ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev)); - ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM)); + ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_WARM)); state->sysreset_allowed[SYSRESET_COLD] = false; ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD)); state->sysreset_allowed[SYSRESET_COLD] = true; diff --git a/test/image/Kconfig b/test/image/Kconfig index 8f9e6ae036b..45b6e8c52e6 100644 --- a/test/image/Kconfig +++ b/test/image/Kconfig @@ -23,6 +23,15 @@ config SPL_UT_LOAD_FS help Test filesystems and the various load methods which use them. +config SPL_UT_LOAD_NAND + bool "Test loading from NAND flash" + depends on SANDBOX && SPL_OF_REAL + depends on SPL_NAND_SUPPORT + depends on SPL_MTD + default y + help + Test the NAND flash load method. + config SPL_UT_LOAD_NET bool "Test loading over TFTP" depends on SANDBOX && SPL_OF_REAL @@ -43,6 +52,7 @@ config SPL_UT_LOAD_SPI config SPL_UT_LOAD_OS bool "Test loading from the host OS" depends on SANDBOX && SPL_LOAD_FIT + select SPL_LOAD_BLOCK default y help Smoke test to ensure that loading U-boot works in sandbox. diff --git a/test/image/Makefile b/test/image/Makefile index b30210106a4..11ed25734e8 100644 --- a/test/image/Makefile +++ b/test/image/Makefile @@ -4,6 +4,7 @@ obj-y += spl_load.o obj-$(CONFIG_SPL_UT_LOAD_FS) += spl_load_fs.o +obj-$(CONFIG_SPL_UT_LOAD_NAND) += spl_load_nand.o obj-$(CONFIG_SPL_UT_LOAD_NET) += spl_load_net.o obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_load_nor.o obj-$(CONFIG_SPL_UT_LOAD_OS) += spl_load_os.o diff --git a/test/image/spl_load.c b/test/image/spl_load.c index ab4c14d6491..e1036eff28c 100644 --- a/test/image/spl_load.c +++ b/test/image/spl_load.c @@ -342,12 +342,11 @@ static int spl_test_image(struct unit_test_state *uts, const char *test_name, if (check_image_info(uts, &info_write, &info_read)) return CMD_RET_FAILURE; } else { - struct spl_load_info load = { - .bl_len = 1, - .priv = img, - .read = spl_test_read, - }; + struct spl_load_info load; + spl_set_bl_len(&load, 1); + load.priv = img; + load.read = spl_test_read; if (type == IMX8) ut_assertok(spl_load_imx_container(&info_read, &load, 0)); @@ -375,7 +374,7 @@ SPL_IMG_TEST(spl_test_image, FIT_EXTERNAL, 0); * LZMA is too complex to generate on the fly, so let's use some data I put in * the oven^H^H^H^H compressed earlier */ -static const char lzma_compressed[] = { +const char lzma_compressed[] = { 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x02, 0x05, 0x55, 0x4e, 0x82, 0xbc, 0xc2, 0x42, 0xf6, 0x88, 0x6c, 0x99, 0xd6, 0x82, 0x48, 0xa6, 0x06, 0x67, 0xf8, 0x46, 0x7c, 0xe9, @@ -611,6 +610,8 @@ static const char lzma_compressed[] = { 0x1e, 0xff, 0xff, 0x80, 0x8e, 0x00, 0x00 }; +const size_t lzma_compressed_size = sizeof(lzma_compressed); + int do_spl_test_load(struct unit_test_state *uts, const char *test_name, enum spl_test_image type, struct spl_image_loader *loader, int (*write_image)(struct unit_test_state *, void *, size_t)) diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c index 297ab08a820..a89189e1124 100644 --- a/test/image/spl_load_fs.c +++ b/test/image/spl_load_fs.c @@ -220,7 +220,7 @@ static size_t create_fat(void *dst, size_t size, const char *filename, bs->root_cluster = cpu_to_le32(root_sector); vi->ext_boot_sign = 0x29; - memcpy(vi->fs_type, FAT32_SIGN, sizeof(vi->fs_type)); + memcpy(vi->fs_type, "FAT32 ", sizeof(vi->fs_type)); memcpy(dst + 0x1fe, "\x55\xAA", 2); @@ -320,10 +320,11 @@ static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name, const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME; struct blk_desc *dev_desc; size_t fs_size, fs_data, img_size, img_data, - data_size = SPL_TEST_DATA_SIZE; + plain_size = SPL_TEST_DATA_SIZE; struct spl_image_info info_write = { .name = test_name, - .size = data_size, + .size = type == LEGACY_LZMA ? lzma_compressed_size : + plain_size, }, info_read = { }; struct disk_partition part = { .start = 1, @@ -335,7 +336,7 @@ static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name, .boot_device = loader->boot_device, }; void *fs; - char *data; + char *data, *plain; img_size = create_image(NULL, type, &info_write, &img_data); ut_assert(img_size); @@ -345,7 +346,15 @@ static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name, ut_assertnonnull(fs); data = fs + fs_data + img_data; - generate_data(data, data_size, test_name); + if (type == LEGACY_LZMA) { + plain = malloc(plain_size); + ut_assertnonnull(plain); + generate_data(plain, plain_size, "lzma"); + memcpy(data, lzma_compressed, lzma_compressed_size); + } else { + plain = data; + generate_data(plain, plain_size, test_name); + } ut_asserteq(img_size, create_image(fs + fs_data, type, &info_write, NULL)); ut_asserteq(fs_size, create_fs(fs, img_size, filename, NULL)); @@ -366,8 +375,12 @@ static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name, ut_assertok(loader->load_image(&info_read, &bootdev)); if (check_image_info(uts, &info_write, &info_read)) return CMD_RET_FAILURE; - ut_asserteq_mem(data, phys_to_virt(info_write.load_addr), data_size); + if (type == LEGACY_LZMA) + ut_asserteq(plain_size, info_read.size); + ut_asserteq_mem(plain, phys_to_virt(info_write.load_addr), plain_size); + if (type == LEGACY_LZMA) + free(plain); free(fs); return 0; } @@ -382,6 +395,8 @@ static int spl_test_blk(struct unit_test_state *uts, const char *test_name, return spl_test_mmc_fs(uts, test_name, type, create_ext2, true); } SPL_IMG_TEST(spl_test_blk, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_blk, LEGACY_LZMA, DM_FLAGS); +SPL_IMG_TEST(spl_test_blk, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_blk, FIT_EXTERNAL, DM_FLAGS); SPL_IMG_TEST(spl_test_blk, FIT_INTERNAL, DM_FLAGS); @@ -409,12 +424,10 @@ static int spl_test_mmc(struct unit_test_state *uts, const char *test_name, spl_mmc_clear_cache(); spl_fat_force_reregister(); - if (type == LEGACY && - spl_test_mmc_fs(uts, test_name, type, create_ext2, false)) + if (spl_test_mmc_fs(uts, test_name, type, create_ext2, false)) return CMD_RET_FAILURE; - if (type != IMX8 && - spl_test_mmc_fs(uts, test_name, type, create_fat, false)) + if (spl_test_mmc_fs(uts, test_name, type, create_fat, false)) return CMD_RET_FAILURE; return do_spl_test_load(uts, test_name, type, @@ -423,6 +436,7 @@ static int spl_test_mmc(struct unit_test_state *uts, const char *test_name, spl_test_mmc_write_image); } SPL_IMG_TEST(spl_test_mmc, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_mmc, LEGACY_LZMA, DM_FLAGS); SPL_IMG_TEST(spl_test_mmc, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_mmc, FIT_EXTERNAL, DM_FLAGS); SPL_IMG_TEST(spl_test_mmc, FIT_INTERNAL, DM_FLAGS); diff --git a/test/image/spl_load_nand.c b/test/image/spl_load_nand.c new file mode 100644 index 00000000000..ec242207948 --- /dev/null +++ b/test/image/spl_load_nand.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com> + */ + +#include <nand.h> +#include <spl.h> +#include <test/spl.h> +#include <test/ut.h> + +uint32_t spl_nand_get_uboot_raw_page(void); + +static int spl_test_nand_write_image(struct unit_test_state *uts, void *img, + size_t img_size) +{ + uint32_t off = spl_nand_get_uboot_raw_page(); + struct mtd_info *mtd; + struct erase_info erase = { }; + size_t length; + + nand_reinit(); + mtd = get_nand_dev_by_index(0); + ut_assertnonnull(mtd); + + /* Mark the first block as bad to test that it gets skipped */ + ut_assertok(mtd_block_markbad(mtd, off & ~mtd->erasesize_mask)); + off += mtd->erasesize; + + erase.mtd = mtd; + erase.len = img_size + (off & mtd->erasesize_mask); + erase.len += mtd->erasesize_mask; + erase.len &= ~mtd->erasesize_mask; + erase.addr = off & ~mtd->erasesize_mask; + erase.scrub = 1; + ut_assertok(mtd_erase(mtd, &erase)); + + ut_assertok(mtd_write(mtd, off, img_size, &length, img)); + + return 0; +} + +static int spl_test_nand(struct unit_test_state *uts, const char *test_name, + enum spl_test_image type) +{ + return do_spl_test_load(uts, test_name, type, + SPL_LOAD_IMAGE_GET(1, BOOT_DEVICE_NAND, + spl_nand_load_image), + spl_test_nand_write_image); +} +SPL_IMG_TEST(spl_test_nand, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_nand, LEGACY_LZMA, DM_FLAGS); +SPL_IMG_TEST(spl_test_nand, IMX8, DM_FLAGS); +SPL_IMG_TEST(spl_test_nand, FIT_INTERNAL, DM_FLAGS); +#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) +SPL_IMG_TEST(spl_test_nand, FIT_EXTERNAL, DM_FLAGS); +#endif diff --git a/test/image/spl_load_net.c b/test/image/spl_load_net.c index f570cef163f..9d067a7a592 100644 --- a/test/image/spl_load_net.c +++ b/test/image/spl_load_net.c @@ -248,5 +248,7 @@ static int spl_test_net(struct unit_test_state *uts, const char *test_name, return ret; } SPL_IMG_TEST(spl_test_net, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_net, LEGACY_LZMA, DM_FLAGS); +SPL_IMG_TEST(spl_test_net, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_net, FIT_INTERNAL, DM_FLAGS); SPL_IMG_TEST(spl_test_net, FIT_EXTERNAL, DM_FLAGS); diff --git a/test/image/spl_load_nor.c b/test/image/spl_load_nor.c index a62bb60d253..de5686343b9 100644 --- a/test/image/spl_load_nor.c +++ b/test/image/spl_load_nor.c @@ -36,4 +36,6 @@ SPL_IMG_TEST(spl_test_nor, LEGACY, 0); SPL_IMG_TEST(spl_test_nor, LEGACY_LZMA, 0); SPL_IMG_TEST(spl_test_nor, IMX8, 0); SPL_IMG_TEST(spl_test_nor, FIT_INTERNAL, 0); +#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) SPL_IMG_TEST(spl_test_nor, FIT_EXTERNAL, 0); +#endif diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c index 49edf152d78..26228a8a4a9 100644 --- a/test/image/spl_load_os.c +++ b/test/image/spl_load_os.c @@ -16,14 +16,13 @@ struct text_ctx { int fd; }; -static ulong read_fit_image(struct spl_load_info *load, ulong sector, - ulong count, void *buf) +static ulong read_fit_image(struct spl_load_info *load, ulong offset, + ulong size, void *buf) { struct text_ctx *text_ctx = load->priv; - off_t offset, ret; + off_t ret; ssize_t res; - offset = sector * load->bl_len; ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET); if (ret != offset) { printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset, @@ -31,14 +30,14 @@ static ulong read_fit_image(struct spl_load_info *load, ulong sector, return 0; } - res = os_read(text_ctx->fd, buf, count * load->bl_len); + res = os_read(text_ctx->fd, buf, size); if (res == -1) { printf("Failed to read %lx bytes, got %ld (errno=%d)\n", - count * load->bl_len, res, errno); + size, res, errno); return 0; } - return count; + return size; } static int spl_test_load(struct unit_test_state *uts) @@ -52,13 +51,12 @@ static int spl_test_load(struct unit_test_state *uts) int fd; memset(&load, '\0', sizeof(load)); - load.bl_len = 512; + spl_set_bl_len(&load, 512); load.read = read_fit_image; ret = sandbox_find_next_phase(fname, sizeof(fname), true); if (ret) ut_assertf(0, "%s not found, error %d\n", fname, ret); - load.filename = fname; header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); diff --git a/test/image/spl_load_spi.c b/test/image/spl_load_spi.c index 8f9b6e0139b..54a95465e23 100644 --- a/test/image/spl_load_spi.c +++ b/test/image/spl_load_spi.c @@ -34,6 +34,7 @@ static int spl_test_spi(struct unit_test_state *uts, const char *test_name, spl_test_spi_write_image); } SPL_IMG_TEST(spl_test_spi, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_spi, LEGACY_LZMA, DM_FLAGS); SPL_IMG_TEST(spl_test_spi, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_spi, FIT_INTERNAL, DM_FLAGS); #if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 15c68ce3961..7e4368de22e 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -9,6 +9,7 @@ #include <log.h> #include <malloc.h> #include <dm/test.h> +#include <test/lib.h> #include <test/test.h> #include <test/ut.h> @@ -205,8 +206,7 @@ static int lib_test_lmb_simple(struct unit_test_state *uts) /* simulate 512 MiB RAM beginning at 1.5GiB */ return test_multi_alloc_512mb(uts, 0xE0000000); } - -DM_TEST(lib_test_lmb_simple, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_simple, 0); /* Create two memory regions with one reserved region and allocate */ static int lib_test_lmb_simple_x2(struct unit_test_state *uts) @@ -221,8 +221,7 @@ static int lib_test_lmb_simple_x2(struct unit_test_state *uts) /* simulate 512 MiB RAM beginning at 3.5GiB and 1 GiB */ return test_multi_alloc_512mb_x2(uts, 0xE0000000, 0x40000000); } - -DM_TEST(lib_test_lmb_simple_x2, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_simple_x2, 0); /* Simulate 512 MiB RAM, allocate some blocks that fit/don't fit */ static int test_bigblock(struct unit_test_state *uts, const phys_addr_t ram) @@ -288,8 +287,7 @@ static int lib_test_lmb_big(struct unit_test_state *uts) /* simulate 512 MiB RAM beginning at 1.5GiB */ return test_bigblock(uts, 0xE0000000); } - -DM_TEST(lib_test_lmb_big, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_big, 0); /* Simulate 512 MiB RAM, allocate a block without previous reservation */ static int test_noreserved(struct unit_test_state *uts, const phys_addr_t ram, @@ -364,7 +362,7 @@ static int lib_test_lmb_noreserved(struct unit_test_state *uts) return test_noreserved(uts, 0xE0000000, 4, 1); } -DM_TEST(lib_test_lmb_noreserved, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_noreserved, 0); static int lib_test_lmb_unaligned_size(struct unit_test_state *uts) { @@ -378,8 +376,8 @@ static int lib_test_lmb_unaligned_size(struct unit_test_state *uts) /* simulate 512 MiB RAM beginning at 1.5GiB */ return test_noreserved(uts, 0xE0000000, 5, 8); } +LIB_TEST(lib_test_lmb_unaligned_size, 0); -DM_TEST(lib_test_lmb_unaligned_size, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); /* * Simulate a RAM that starts at 0 and allocate down to address 0, which must * fail as '0' means failure for the lmb_alloc functions. @@ -421,8 +419,7 @@ static int lib_test_lmb_at_0(struct unit_test_state *uts) return 0; } - -DM_TEST(lib_test_lmb_at_0, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_at_0, 0); /* Check that calling lmb_reserve with overlapping regions fails. */ static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts) @@ -470,9 +467,7 @@ static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts) 0, 0, 0, 0); return 0; } - -DM_TEST(lib_test_lmb_overlapping_reserve, - UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_overlapping_reserve, 0); /* * Simulate 512 MiB RAM, reserve 3 blocks, allocate addresses in between. @@ -601,8 +596,7 @@ static int lib_test_lmb_alloc_addr(struct unit_test_state *uts) /* simulate 512 MiB RAM beginning at 1.5GiB */ return test_alloc_addr(uts, 0xE0000000); } - -DM_TEST(lib_test_lmb_alloc_addr, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_alloc_addr, 0); /* Simulate 512 MiB RAM, reserve 3 blocks, check addresses in between */ static int test_get_unreserved_size(struct unit_test_state *uts, @@ -672,9 +666,7 @@ static int lib_test_lmb_get_free_size(struct unit_test_state *uts) /* simulate 512 MiB RAM beginning at 1.5GiB */ return test_get_unreserved_size(uts, 0xE0000000); } - -DM_TEST(lib_test_lmb_get_free_size, - UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_get_free_size, 0); #ifdef CONFIG_LMB_USE_MAX_REGIONS static int lib_test_lmb_max_regions(struct unit_test_state *uts) @@ -743,11 +735,9 @@ static int lib_test_lmb_max_regions(struct unit_test_state *uts) return 0; } +LIB_TEST(lib_test_lmb_max_regions, 0); #endif -DM_TEST(lib_test_lmb_max_regions, - UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); - static int lib_test_lmb_flags(struct unit_test_state *uts) { const phys_addr_t ram = 0x40000000; @@ -833,6 +823,4 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) return 0; } - -DM_TEST(lib_test_lmb_flags, - UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); +LIB_TEST(lib_test_lmb_flags, 0); diff --git a/test/print_ut.c b/test/print_ut.c index b26f6281b01..bb844d2542b 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -170,6 +170,10 @@ static int print_display_buffer(struct unit_test_state *uts) u8 *buf; int i; + /* This test requires writable memory at zero */ + if (IS_ENABLED(CONFIG_X86)) + return -EAGAIN; + buf = map_sysmem(0, BUF_SIZE); memset(buf, '\0', BUF_SIZE); for (i = 0; i < 0x11; i++) @@ -275,6 +279,10 @@ static int print_do_hex_dump(struct unit_test_state *uts) u8 *buf; int i; + /* This test requires writable memory at zero */ + if (IS_ENABLED(CONFIG_X86)) + return -EAGAIN; + buf = map_sysmem(0, BUF_SIZE); memset(buf, '\0', BUF_SIZE); for (i = 0; i < 0x11; i++) diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py index 9882ddb1daa..380f4c4dca3 100644 --- a/test/py/tests/fs_helper.py +++ b/test/py/tests/fs_helper.py @@ -9,7 +9,7 @@ import re import os from subprocess import call, check_call, check_output, CalledProcessError -def mk_fs(config, fs_type, size, prefix): +def mk_fs(config, fs_type, size, prefix, size_gran = 0x100000): """Create a file system volume Args: @@ -17,6 +17,7 @@ def mk_fs(config, fs_type, size, prefix): fs_type (str): File system type, e.g. 'ext4' size (int): Size of file system in bytes prefix (str): Prefix string of volume's file name + size_gran (int): Size granularity of file system image in bytes Raises: CalledProcessError: if any error occurs when creating the filesystem @@ -24,7 +25,9 @@ def mk_fs(config, fs_type, size, prefix): fs_img = f'{prefix}.{fs_type}.img' fs_img = os.path.join(config.persistent_data_dir, fs_img) - if fs_type == 'fat16': + if fs_type == 'fat12': + mkfs_opt = '-F 12' + elif fs_type == 'fat16': mkfs_opt = '-F 16' elif fs_type == 'fat32': mkfs_opt = '-F 32' @@ -36,7 +39,7 @@ def mk_fs(config, fs_type, size, prefix): else: fs_lnxtype = fs_type - count = (size + 0x100000 - 1) // 0x100000 + count = (size + size_gran - 1) // size_gran # Some distributions do not add /sbin to the default PATH, where mkfs lives if '/sbin' not in os.environ["PATH"].split(os.pathsep): @@ -44,7 +47,7 @@ def mk_fs(config, fs_type, size, prefix): try: check_call(f'rm -f {fs_img}', shell=True) - check_call(f'dd if=/dev/zero of={fs_img} bs=1M count={count}', + check_call(f'dd if=/dev/zero of={fs_img} bs={size_gran} count={count}', shell=True) check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True) if fs_type == 'ext4': diff --git a/test/py/tests/test_efi_secboot/test_signed.py b/test/py/tests/test_efi_secboot/test_signed.py index ca52e853d8f..2f862a259ad 100644 --- a/test/py/tests/test_efi_secboot/test_signed.py +++ b/test/py/tests/test_efi_secboot/test_signed.py @@ -29,7 +29,7 @@ class TestEfiSignedImage(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'bootefi bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -37,7 +37,7 @@ class TestEfiSignedImage(object): # Test Case 1b, run unsigned image if no PK output = u_boot_console.run_command_list([ 'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""', - 'efidebug boot next 2', + 'efidebug boot order 2', 'bootefi bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -59,13 +59,13 @@ class TestEfiSignedImage(object): assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert('\'HELLO1\' failed' in ''.join(output)) assert('efi_start_image() returned: 26' in ''.join(output)) output = u_boot_console.run_command_list([ 'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""', - 'efidebug boot next 2', + 'efidebug boot order 2', 'efidebug test bootmgr']) assert '\'HELLO2\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -77,12 +77,12 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 2', + 'efidebug boot order 2', 'efidebug test bootmgr']) assert '\'HELLO2\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'bootefi bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -105,7 +105,7 @@ class TestEfiSignedImage(object): assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -117,7 +117,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -143,7 +143,7 @@ class TestEfiSignedImage(object): assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -170,7 +170,7 @@ class TestEfiSignedImage(object): assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -181,7 +181,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -193,7 +193,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -205,7 +205,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize dbx']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -230,7 +230,7 @@ class TestEfiSignedImage(object): assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -254,7 +254,7 @@ class TestEfiSignedImage(object): assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'bootefi bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -265,7 +265,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -279,7 +279,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -307,7 +307,7 @@ class TestEfiSignedImage(object): assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -330,7 +330,7 @@ class TestEfiSignedImage(object): assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -349,7 +349,7 @@ class TestEfiSignedImage(object): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld_forged.efi.signed -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert('hELLO, world!' in ''.join(output)) @@ -364,7 +364,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert(not 'hELLO, world!' in ''.join(output)) assert('\'HELLO1\' failed' in ''.join(output)) diff --git a/test/py/tests/test_efi_secboot/test_signed_intca.py b/test/py/tests/test_efi_secboot/test_signed_intca.py index d8d599d22f3..8d9a5f3e7fe 100644 --- a/test/py/tests/test_efi_secboot/test_signed_intca.py +++ b/test/py/tests/test_efi_secboot/test_signed_intca.py @@ -40,7 +40,7 @@ class TestEfiSignedImageIntca(object): output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO_a host 0:1 /helloworld.efi.signed_a -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO_a\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -49,7 +49,7 @@ class TestEfiSignedImageIntca(object): # Test Case 1b, signed and authenticated by root CA output = u_boot_console.run_command_list([ 'efidebug boot add -b 2 HELLO_ab host 0:1 /helloworld.efi.signed_ab -s ""', - 'efidebug boot next 2', + 'efidebug boot order 2', 'bootefi bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -71,7 +71,7 @@ class TestEfiSignedImageIntca(object): output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO_abc\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -81,7 +81,7 @@ class TestEfiSignedImageIntca(object): output = u_boot_console.run_command_list([ 'fatload host 0:1 4000000 db_b.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO_abc\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) @@ -91,7 +91,7 @@ class TestEfiSignedImageIntca(object): output = u_boot_console.run_command_list([ 'fatload host 0:1 4000000 db_c.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -117,7 +117,7 @@ class TestEfiSignedImageIntca(object): output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert 'Hello, world!' in ''.join(output) # Or, @@ -129,7 +129,7 @@ class TestEfiSignedImageIntca(object): output = u_boot_console.run_command_list([ 'fatload host 0:1 4000000 dbx_c.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx', - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert '\'HELLO_abc\' failed' in ''.join(output) assert 'efi_start_image() returned: 26' in ''.join(output) diff --git a/test/py/tests/test_efi_secboot/test_unsigned.py b/test/py/tests/test_efi_secboot/test_unsigned.py index df63f0df081..7c078f220d0 100644 --- a/test/py/tests/test_efi_secboot/test_unsigned.py +++ b/test/py/tests/test_efi_secboot/test_unsigned.py @@ -36,11 +36,11 @@ class TestEfiUnsignedImage(object): output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'bootefi bootmgr']) assert '\'HELLO\' failed' in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert 'efi_start_image() returned: 26' in ''.join(output) assert 'Hello, world!' not in ''.join(output) @@ -65,7 +65,7 @@ class TestEfiUnsignedImage(object): output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'bootefi bootmgr']) assert 'Hello, world!' in ''.join(output) @@ -89,11 +89,11 @@ class TestEfiUnsignedImage(object): output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'bootefi bootmgr']) assert '\'HELLO\' failed' in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert 'efi_start_image() returned: 26' in ''.join(output) assert 'Hello, world!' not in ''.join(output) @@ -107,11 +107,11 @@ class TestEfiUnsignedImage(object): output = u_boot_console.run_command_list([ 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""', - 'efidebug boot next 1', + 'efidebug boot order 1', 'bootefi bootmgr']) assert '\'HELLO\' failed' in ''.join(output) output = u_boot_console.run_command_list([ - 'efidebug boot next 1', + 'efidebug boot order 1', 'efidebug test bootmgr']) assert 'efi_start_image() returned: 26' in ''.join(output) assert 'Hello, world!' not in ''.join(output) diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py index f45848484eb..04f64fd4bc6 100755 --- a/test/py/tests/test_fit.py +++ b/test/py/tests/test_fit.py @@ -390,10 +390,10 @@ def test_fit(u_boot_console): cons = u_boot_console + # We need to use our own device tree file. Remember to restore it + # afterwards. + old_dtb = cons.config.dtb try: - # We need to use our own device tree file. Remember to restore it - # afterwards. - old_dtb = cons.config.dtb mkimage = cons.config.build_dir + '/tools/mkimage' run_fit_test(mkimage) finally: diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py index 0d87d180c7b..fca54488374 100644 --- a/test/py/tests/test_fs/conftest.py +++ b/test/py/tests/test_fs/conftest.py @@ -9,12 +9,14 @@ import re from subprocess import call, check_call, check_output, CalledProcessError from fstest_defs import * import u_boot_utils as util +# pylint: disable=E0611 from tests import fs_helper supported_fs_basic = ['fat16', 'fat32', 'ext4'] -supported_fs_ext = ['fat16', 'fat32'] -supported_fs_mkdir = ['fat16', 'fat32'] -supported_fs_unlink = ['fat16', 'fat32'] +supported_fs_ext = ['fat12', 'fat16', 'fat32'] +supported_fs_fat = ['fat12', 'fat16'] +supported_fs_mkdir = ['fat12', 'fat16', 'fat32'] +supported_fs_unlink = ['fat12', 'fat16', 'fat32'] supported_fs_symlink = ['ext4'] # @@ -49,6 +51,7 @@ def pytest_configure(config): """ global supported_fs_basic global supported_fs_ext + global supported_fs_fat global supported_fs_mkdir global supported_fs_unlink global supported_fs_symlink @@ -61,6 +64,7 @@ def pytest_configure(config): print('*** FS TYPE modified: %s' % supported_fs) supported_fs_basic = intersect(supported_fs, supported_fs_basic) supported_fs_ext = intersect(supported_fs, supported_fs_ext) + supported_fs_fat = intersect(supported_fs, supported_fs_fat) supported_fs_mkdir = intersect(supported_fs, supported_fs_mkdir) supported_fs_unlink = intersect(supported_fs, supported_fs_unlink) supported_fs_symlink = intersect(supported_fs, supported_fs_symlink) @@ -83,6 +87,9 @@ def pytest_generate_tests(metafunc): if 'fs_obj_ext' in metafunc.fixturenames: metafunc.parametrize('fs_obj_ext', supported_fs_ext, indirect=True, scope='module') + if 'fs_obj_fat' in metafunc.fixturenames: + metafunc.parametrize('fs_obj_fat', supported_fs_fat, + indirect=True, scope='module') if 'fs_obj_mkdir' in metafunc.fixturenames: metafunc.parametrize('fs_obj_mkdir', supported_fs_mkdir, indirect=True, scope='module') @@ -624,3 +631,44 @@ def fs_obj_symlink(request, u_boot_config): finally: call('rmdir %s' % mount_dir, shell=True) call('rm -f %s' % fs_img, shell=True) + +# +# Fixture for fat test +# +@pytest.fixture() +def fs_obj_fat(request, u_boot_config): + """Set up a file system to be used in fat test. + + Args: + request: Pytest request object. + u_boot_config: U-Boot configuration. + + Return: + A fixture for fat test, i.e. a duplet of file system type and + volume file name. + """ + + # the maximum size of a FAT12 filesystem resulting in 4084 clusters + MAX_FAT12_SIZE = 261695 * 1024 + + # the minimum size of a FAT16 filesystem that can be created with + # mkfs.vfat resulting in 4087 clusters + MIN_FAT16_SIZE = 8208 * 1024 + + fs_type = request.param + fs_img = '' + + fs_ubtype = fstype_to_ubname(fs_type) + check_ubconfig(u_boot_config, fs_ubtype) + + fs_size = MAX_FAT12_SIZE if fs_type == 'fat12' else MIN_FAT16_SIZE + + try: + # the volume size depends on the filesystem + fs_img = fs_helper.mk_fs(u_boot_config, fs_type, fs_size, f'{fs_size}', 1024) + except: + pytest.skip('Setup failed for filesystem: ' + fs_type) + return + else: + yield [fs_ubtype, fs_img] + call('rm -f %s' % fs_img, shell=True) diff --git a/test/py/tests/test_fs/test_erofs.py b/test/py/tests/test_fs/test_erofs.py index 458a52ba79d..87ad8f2d5fd 100644 --- a/test/py/tests/test_fs/test_erofs.py +++ b/test/py/tests/test_fs/test_erofs.py @@ -196,6 +196,15 @@ def test_erofs(u_boot_console): """ build_dir = u_boot_console.config.build_dir + # If the EFI subsystem is enabled and initialized, EFI subsystem tries to + # add EFI boot option when the new disk is detected. If there is no EFI + # System Partition exists, EFI subsystem outputs error messages and + # it ends up with test failure. + # Restart U-Boot to clear the previous state. + # TODO: Ideally EFI test cases need to be fixed, but it will + # increase the number of system reset. + u_boot_console.restart_uboot() + try: # setup test environment make_erofs_image(build_dir) diff --git a/test/py/tests/test_fs/test_fs_fat.py b/test/py/tests/test_fs/test_fs_fat.py new file mode 100644 index 00000000000..4009d0b63a3 --- /dev/null +++ b/test/py/tests/test_fs/test_fs_fat.py @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2023 Weidmüller Interface GmbH & Co. KG +# Author: Christian Taedcke <christian.taedcke@weidmueller.com> +# +# U-Boot File System: FAT Test + +""" +This test verifies fat specific file system behaviour. +""" + +import pytest +import re + +@pytest.mark.boardspec('sandbox') +@pytest.mark.slow +class TestFsFat(object): + def test_fs_fat1(self, u_boot_console, fs_obj_fat): + """Test that `fstypes` prints a result which includes `sandbox`.""" + fs_type,fs_img = fs_obj_fat + with u_boot_console.log.section('Test Case 1 - fatinfo'): + # Test Case 1 - ls + output = u_boot_console.run_command_list([ + 'host bind 0 %s' % fs_img, + 'fatinfo host 0:0']) + assert(re.search('Filesystem: %s' % fs_type.upper(), ''.join(output))) diff --git a/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py b/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py index 527a556ed80..a20a7d1a663 100644 --- a/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py +++ b/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py @@ -118,6 +118,15 @@ def test_sqfs_ls(u_boot_console): """ build_dir = u_boot_console.config.build_dir + # If the EFI subsystem is enabled and initialized, EFI subsystem tries to + # add EFI boot option when the new disk is detected. If there is no EFI + # System Partition exists, EFI subsystem outputs error messages and + # it ends up with test failure. + # Restart U-Boot to clear the previous state. + # TODO: Ideally EFI test cases need to be fixed, but it will + # increase the number of system reset. + u_boot_console.restart_uboot() + # setup test environment check_mksquashfs_version() generate_sqfs_src_dir(build_dir) diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py index b2241ae6a48..2495608786d 100644 --- a/test/py/tests/test_net.py +++ b/test/py/tests/test_net.py @@ -7,6 +7,7 @@ import pytest import u_boot_utils import uuid +import datetime """ Note: This test relies on boardenv_* containing configuration values to define @@ -51,6 +52,8 @@ env__net_tftp_readable_file = { 'addr': 0x10000000, 'size': 5058624, 'crc32': 'c2244b26', + 'timeout': 50000, + 'fnu': 'ubtest-upload.bin', } # Details regarding a file that may be read from a NFS server. This variable @@ -326,3 +329,71 @@ def test_net_pxe_get(u_boot_console): assert expected_text_default in output assert "Config file 'default.boot' found" in output + +@pytest.mark.buildconfigspec("cmd_crc32") +@pytest.mark.buildconfigspec("cmd_net") +@pytest.mark.buildconfigspec("cmd_tftpput") +def test_net_tftpput(u_boot_console): + """Test the tftpput command. + + A file is downloaded from the TFTP server and then uploaded to the TFTP + server, its size and its CRC32 are validated. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + + if not net_set_up: + pytest.skip("Network not initialized") + + f = u_boot_console.config.env.get("env__net_tftp_readable_file", None) + if not f: + pytest.skip("No TFTP readable file to read") + + addr = f.get("addr", None) + if not addr: + addr = u_boot_utils.find_ram_base(u_boot_console) + + sz = f.get("size", None) + timeout = f.get("timeout", u_boot_console.p.timeout) + fn = f["fn"] + fnu = f.get("fnu", "_".join([datetime.datetime.now().strftime("%y%m%d%H%M%S"), fn])) + expected_text = "Bytes transferred = " + if sz: + expected_text += "%d" % sz + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command("tftpboot %x %s" % (addr, fn)) + + assert "TIMEOUT" not in output + assert expected_text in output + + expected_tftpb_crc = f.get("crc32", None) + + output = u_boot_console.run_command("crc32 $fileaddr $filesize") + assert expected_tftpb_crc in output + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + "tftpput $fileaddr $filesize $serverip:%s" % (fnu) + ) + + expected_text = "Bytes transferred = " + if sz: + expected_text += "%d" % sz + addr = addr + sz + assert "TIMEOUT" not in output + assert "Access violation" not in output + assert expected_text in output + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command("tftpboot %x %s" % (addr, fnu)) + + expected_text = "Bytes transferred = " + if sz: + expected_text += "%d" % sz + assert "TIMEOUT" not in output + assert expected_text in output + + output = u_boot_console.run_command("crc32 $fileaddr $filesize") + assert expected_tftpb_crc in output diff --git a/test/py/tests/test_sandbox_opts.py b/test/py/tests/test_sandbox_opts.py new file mode 100644 index 00000000000..422b43cb3bc --- /dev/null +++ b/test/py/tests/test_sandbox_opts.py @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright 2022 Google LLC +# Written by Simon Glass <sjg@chromium.org> + +import pytest + +import u_boot_utils as util + +# This is needed for Azure, since the default '..' directory is not writeable +TMPDIR = '/tmp/test_cmdline' + +@pytest.mark.slow +@pytest.mark.boardspec('sandbox') +def test_sandbox_cmdline(u_boot_console): + """Test building sandbox without CONFIG_CMDLINE""" + cons = u_boot_console + + out = util.run_and_log( + cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox', + '-a', '~CMDLINE', '-o', TMPDIR]) + +@pytest.mark.slow +@pytest.mark.boardspec('sandbox') +def test_sandbox_lto(u_boot_console): + """Test building sandbox without CONFIG_LTO""" + cons = u_boot_console + + out = util.run_and_log( + cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox', + '-a', '~LTO', '-o', TMPDIR]) diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py index 1d9149a3f68..0e3a48e73f6 100644 --- a/test/py/tests/test_ut.py +++ b/test/py/tests/test_ut.py @@ -9,6 +9,7 @@ import os.path import pytest import u_boot_utils +# pylint: disable=E0611 from tests import fs_helper def mkdir_cond(dirname): diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index 04fa59f98b0..7e0e8e44750 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -533,10 +533,10 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required, with open(evil_kernel, 'wb') as fd: fd.write(500 * b'\x01') + # We need to use our own device tree file. Remember to restore it + # afterwards. + old_dtb = cons.config.dtb try: - # We need to use our own device tree file. Remember to restore it - # afterwards. - old_dtb = cons.config.dtb cons.config.dtb = dtb if global_sign: test_global_sign(sha_algo, padding, sign_options) diff --git a/test/ut.c b/test/ut.c index 28da417686e..628e9dc9805 100644 --- a/test/ut.c +++ b/test/ut.c @@ -121,6 +121,33 @@ int ut_check_skipline(struct unit_test_state *uts) return 0; } +int ut_check_skip_to_linen(struct unit_test_state *uts, const char *fmt, ...) +{ + va_list args; + int len; + int ret; + + va_start(args, fmt); + len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args); + va_end(args); + if (len >= sizeof(uts->expect_str)) { + ut_fail(uts, __FILE__, __LINE__, __func__, + "unit_test_state->expect_str too small"); + return -EOVERFLOW; + } + while (1) { + if (!console_record_avail()) + return -ENOENT; + ret = readline_check(uts); + if (ret < 0) + return ret; + + if (!strncmp(uts->expect_str, uts->actual_str, + strlen(uts->expect_str))) + return 0; + } +} + int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...) { va_list args; diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index 020988d955f..230e055667f 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -2060,7 +2060,7 @@ don't have access to the blobs. If the blobs are in a different directory, you can specify this with the `-I` option. -For U-Boot, you can use set the BINMAN_INDIRS environment variable to provide a +For U-Boot, you can set the BINMAN_INDIRS environment variable to provide a space-separated list of directories to search for binary blobs:: BINMAN_INDIRS="odroid-c4/fip/g12a \ diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py index e3dee79d065..b64134123c1 100644 --- a/tools/binman/elf_test.py +++ b/tools/binman/elf_test.py @@ -249,8 +249,8 @@ class TestElf(unittest.TestCase): def testEmbedFail(self): """Test calling GetSymbolFileOffset() without elftools""" + old_val = elf.ELF_TOOLS try: - old_val = elf.ELF_TOOLS elf.ELF_TOOLS = False fname = self.ElfTestFile('embed_data') with self.assertRaises(ValueError) as e: @@ -290,8 +290,8 @@ class TestElf(unittest.TestCase): def test_read_segments_fail(self): """Test for read_loadable_segments() without elftools""" + old_val = elf.ELF_TOOLS try: - old_val = elf.ELF_TOOLS elf.ELF_TOOLS = False fname = self.ElfTestFile('embed_data') with self.assertRaises(ValueError) as e: @@ -327,8 +327,8 @@ class TestElf(unittest.TestCase): def test_get_file_offset_fail(self): """Test calling GetFileOffset() without elftools""" + old_val = elf.ELF_TOOLS try: - old_val = elf.ELF_TOOLS elf.ELF_TOOLS = False fname = self.ElfTestFile('embed_data') with self.assertRaises(ValueError) as e: @@ -351,8 +351,8 @@ class TestElf(unittest.TestCase): def test_get_symbol_from_address_fail(self): """Test calling GetSymbolFromAddress() without elftools""" + old_val = elf.ELF_TOOLS try: - old_val = elf.ELF_TOOLS elf.ELF_TOOLS = False fname = self.ElfTestFile('embed_data') with self.assertRaises(ValueError) as e: diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index 61de7f1f4a8..254afe76074 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1906,6 +1906,20 @@ the included board config binaries. Example:: +.. _etype_ti_dm: + +Entry: ti-dm: TI Device Manager (DM) blob +----------------------------------------- + +Properties / Entry arguments: + - ti-dm-path: Filename of file to read into the entry, typically ti-dm.bin + +This entry holds the device manager responsible for resource and power management +in K3 devices. See https://software-dl.ti.com/tisci/esd/latest/ for more information +about TI DM. + + + .. _etype_ti_secure: Entry: ti-secure: Entry containing a TI x509 certificate binary diff --git a/tools/binman/etype/ti_dm.py b/tools/binman/etype/ti_dm.py new file mode 100644 index 00000000000..0faa0bf0ca7 --- /dev/null +++ b/tools/binman/etype/ti_dm.py @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Written by Neha Malcom Francis <n-francis@ti.com> +# +# Entry-type module for TI Device Manager (DM) +# + +from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg + +class Entry_ti_dm(Entry_blob_named_by_arg): + """TI Device Manager (DM) blob + + Properties / Entry arguments: + - ti-dm-path: Filename of file to read into the entry, typically ti-dm.bin + + This entry holds the device manager responsible for resource and power management + in K3 devices. See https://software-dl.ti.com/tisci/esd/latest/ for more information + about TI DM. + """ + def __init__(self, section, etype, node): + super().__init__(section, etype, node, 'ti-dm') + self.external = True diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 5ace2a825dc..a273120d9f9 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -88,6 +88,7 @@ FSP_S_DATA = b'fsp_s' FSP_T_DATA = b'fsp_t' ATF_BL31_DATA = b'bl31' TEE_OS_DATA = b'this is some tee OS data' +TI_DM_DATA = b'tidmtidm' ATF_BL2U_DATA = b'bl2u' OPENSBI_DATA = b'opensbi' SCP_DATA = b'scp' @@ -221,6 +222,7 @@ class TestFunctional(unittest.TestCase): TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG) TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA) TestFunctional._MakeInputFile('tee-pager.bin', TEE_OS_DATA) + TestFunctional._MakeInputFile('dm.bin', TI_DM_DATA) TestFunctional._MakeInputFile('bl2u.bin', ATF_BL2U_DATA) TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA) TestFunctional._MakeInputFile('scp.bin', SCP_DATA) @@ -5455,6 +5457,11 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = self._DoReadFile('222_tee_os.dts') self.assertEqual(TEE_OS_DATA, data[:len(TEE_OS_DATA)]) + def testPackTiDm(self): + """Test that an image with a TI DM binary can be created""" + data = self._DoReadFile('225_ti_dm.dts') + self.assertEqual(TI_DM_DATA, data[:len(TI_DM_DATA)]) + def testFitFdtOper(self): """Check handling of a specified FIT operation""" entry_args = { diff --git a/tools/binman/pyproject.toml b/tools/binman/pyproject.toml index b4b54fbaee6..ba34437fc53 100644 --- a/tools/binman/pyproject.toml +++ b/tools/binman/pyproject.toml @@ -4,11 +4,11 @@ build-backend = "setuptools.build_meta" [project] name = "binary-manager" -version = "0.0.2" +version = "0.0.6" authors = [ { name="Simon Glass", email="sjg@chromium.org" }, ] -dependencies = ["pylibfdt", "u_boot_pylib", "dtoc"] +dependencies = ["pylibfdt", "u_boot_pylib >= 0.0.6", "dtoc >= 0.0.6"] description = "Binman firmware-packaging tool" readme = "README.rst" requires-python = ">=3.7" @@ -19,7 +19,7 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://u-boot.readthedocs.io/en/latest/develop/package/index.html" +"Homepage" = "https://docs.u-boot.org/en/latest/develop/package/index.html" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [project.scripts] diff --git a/tools/binman/test/225_ti_dm.dts b/tools/binman/test/225_ti_dm.dts new file mode 100644 index 00000000000..3ab754131e9 --- /dev/null +++ b/tools/binman/test/225_ti_dm.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + binman { + ti-dm { + filename = "dm.bin"; + }; + }; +}; diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 3e42c987d1c..f35175b4598 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -480,7 +480,7 @@ class Builder: Args: commit: Commit object that is being built brd: Board object that is being built - stage: Stage that we are at (mrproper, config, build) + stage: Stage that we are at (mrproper, config, oldconfig, build) cwd: Directory where make should be run args: Arguments to pass to make kwargs: Arguments to pass to command.run_pipe() diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index 6a61f64da1d..a8599c0bb2a 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -426,6 +426,12 @@ class BuilderThread(threading.Thread): # Now do the build, if everything looks OK if result.return_code == 0: + if adjust_cfg: + oldc_args = list(args) + ['oldconfig'] + oldc_result = self.make(commit, brd, 'oldconfig', cwd, + *oldc_args, env=env) + if oldc_result.return_code: + return oldc_result result = self._build(commit, brd, cwd, args, env, cmd_list, config_only) if adjust_cfg: diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py index 55dd494fe8e..6b88ed815d6 100644 --- a/tools/buildman/func_test.py +++ b/tools/buildman/func_test.py @@ -439,6 +439,8 @@ class TestFunctional(unittest.TestCase): tools.write_file(fname, b'CONFIG_SOMETHING=1') return command.CommandResult(return_code=0, combined='Test configuration complete') + elif stage == 'oldconfig': + return command.CommandResult(return_code=0) elif stage == 'build': stderr = '' fname = os.path.join(cwd or '', out_dir, 'u-boot') @@ -461,7 +463,7 @@ Some images are invalid''' return command.CommandResult(return_code=0) # Not handled, so abort - print('make', stage) + print('_HandleMake failure: make', stage) sys.exit(1) # Example function to print output lines diff --git a/tools/buildman/pyproject.toml b/tools/buildman/pyproject.toml index 4d75e772ee1..fe0f6421b53 100644 --- a/tools/buildman/pyproject.toml +++ b/tools/buildman/pyproject.toml @@ -4,11 +4,11 @@ build-backend = "setuptools.build_meta" [project] name = "buildman" -version = "0.0.2" +version = "0.0.6" authors = [ { name="Simon Glass", email="sjg@chromium.org" }, ] -dependencies = ["u_boot_pylib", "patch-manager"] +dependencies = ["u_boot_pylib >= 0.0.6", "patch-manager >= 0.0.6"] description = "Buildman build tool for U-Boot" readme = "README.rst" requires-python = ">=3.7" @@ -19,7 +19,7 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://u-boot.readthedocs.io/en/latest/build/buildman.html" +"Homepage" = "https://docs.u-boot.org/en/latest/build/buildman.html" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [project.scripts] diff --git a/tools/dtoc/pyproject.toml b/tools/dtoc/pyproject.toml index 77fe4da2158..9f59788e616 100644 --- a/tools/dtoc/pyproject.toml +++ b/tools/dtoc/pyproject.toml @@ -4,11 +4,11 @@ build-backend = "setuptools.build_meta" [project] name = "dtoc" -version = "0.0.2" +version = "0.0.6" authors = [ { name="Simon Glass", email="sjg@chromium.org" }, ] -dependencies = ["pylibfdt", "u_boot_pylib"] +dependencies = ["pylibfdt", "u_boot_pylib >= 0.0.6"] description = "Devicetree-to-C generator" readme = "README.rst" requires-python = ">=3.7" @@ -19,7 +19,7 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://u-boot.readthedocs.io/en/latest/develop/driver-model/of-plat.html" +"Homepage" = "https://docs.u-boot.org/en/latest/develop/driver-model/of-plat.html" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [project.scripts] diff --git a/tools/logos/stm32f469-discovery.bmp b/tools/logos/stm32f469-discovery.bmp Binary files differnew file mode 100644 index 00000000000..ecc8d984218 --- /dev/null +++ b/tools/logos/stm32f469-discovery.bmp diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 04d86f87a86..8f4018aa560 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -478,7 +478,7 @@ static int mx28_create_nand_image(int infd, int outfd) goto err0; } - memset(buf, 0, size); + memset(buf, 0xff, size); fcb = mx28_nand_get_fcb(MAX_BOOTSTREAM_SIZE); if (!fcb) { diff --git a/tools/patman/pyproject.toml b/tools/patman/pyproject.toml index a54211f7069..fcefcf66960 100644 --- a/tools/patman/pyproject.toml +++ b/tools/patman/pyproject.toml @@ -4,11 +4,11 @@ build-backend = "setuptools.build_meta" [project] name = "patch-manager" -version = "0.0.2" +version = "0.0.6" authors = [ { name="Simon Glass", email="sjg@chromium.org" }, ] -dependencies = ["u_boot_pylib"] +dependencies = ["u_boot_pylib >= 0.0.6"] description = "Patman patch manager" readme = "README.rst" requires-python = ">=3.7" @@ -19,11 +19,11 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://u-boot.readthedocs.io/en/latest/develop/patman.html" +"Homepage" = "https://docs.u-boot.org/en/latest/develop/patman.html" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [project.scripts] -patman = "patman.__main__" +patman = "patman.__main__:run_patman" [tool.setuptools.package-data] patman = ["*.rst"] diff --git a/tools/u_boot_pylib/README.rst b/tools/u_boot_pylib/README.rst index 93858f5571d..36a18256d8b 100644 --- a/tools/u_boot_pylib/README.rst +++ b/tools/u_boot_pylib/README.rst @@ -1,7 +1,7 @@ .. SPDX-License-Identifier: GPL-2.0+ # U-Boot Python Library -===================== +======================= This is a Python library used by various U-Boot tools, including patman, buildman and binman. diff --git a/tools/u_boot_pylib/pyproject.toml b/tools/u_boot_pylib/pyproject.toml index 037c5d629ec..ce2355084ac 100644 --- a/tools/u_boot_pylib/pyproject.toml +++ b/tools/u_boot_pylib/pyproject.toml @@ -4,7 +4,7 @@ build-backend = "setuptools.build_meta" [project] name = "u_boot_pylib" -version = "0.0.2" +version = "0.0.6" authors = [ { name="Simon Glass", email="sjg@chromium.org" }, ] @@ -18,9 +18,8 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://u-boot.readthedocs.io" +"Homepage" = "https://docs.u-boot.org" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" -[tool.setuptools.packages.find] -where = [".."] -include = ["u_boot_pylib*"] +[tool.setuptools.package-data] +u_boot_pylib = ["*.rst"] |
