diff options
1189 files changed, 9143 insertions, 7954 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 7aefda93d01..09298e6bc86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1714,6 +1714,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git F: drivers/mtd/ubi/ UFS +M: Neil Armstrong <neil.armstrong@linaro.org> M: Bhupesh Sharma <bhupesh.linux@gmail.com> M: Neha Malcom Francis <n-francis@ti.com> S: Maintained @@ -624,7 +624,7 @@ include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd @# Otherwise, 'make silentoldconfig' would be invoked twice. $(Q)touch include/config/auto.conf -u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg: +u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg vpl/u-boot.cfg: $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf $(@) -include include/autoconf.mk @@ -835,7 +835,7 @@ UBOOTINCLUDE := \ -I$(srctree)/lib/mbedtls/port \ -I$(srctree)/lib/mbedtls/external/mbedtls \ -I$(srctree)/lib/mbedtls/external/mbedtls/include) \ - $(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \ + $(if $(CONFIG_$(XPL_)SYS_THUMB_BUILD), \ $(if $(CONFIG_HAS_THUMB2), \ $(if $(CONFIG_CPU_V7M), \ -I$(srctree)/arch/arm/thumb1/include), \ @@ -870,7 +870,7 @@ libs-y += disk/ libs-y += drivers/ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/ -libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/ +libs-$(CONFIG_$(XPL_)ALTERA_SDRAM) += drivers/ddr/altera/ libs-y += drivers/usb/cdns3/ libs-y += drivers/usb/dwc3/ libs-y += drivers/usb/common/ @@ -889,7 +889,7 @@ libs-y += drivers/usb/ulpi/ ifdef CONFIG_POST libs-y += post/ endif -libs-$(CONFIG_$(SPL_TPL_)UNIT_TEST) += test/ +libs-$(CONFIG_$(PHASE_)UNIT_TEST) += test/ libs-$(CONFIG_UT_ENV) += test/env/ libs-$(CONFIG_UT_OPTEE) += test/optee/ libs-$(CONFIG_UT_OVERLAY) += test/overlay/ @@ -2110,7 +2110,7 @@ spl/u-boot-spl-dtb.hex: spl/u-boot-spl @: spl/u-boot-spl: tools prepare $(if $(CONFIG_SPL_OF_CONTROL),dts/dt.dtb) - $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all + $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.xpl all spl/sunxi-spl.bin: spl/u-boot-spl @: @@ -2129,14 +2129,14 @@ tpl/u-boot-tpl.bin: tpl/u-boot-tpl $(TPL_SIZE_CHECK) tpl/u-boot-tpl: tools prepare $(if $(CONFIG_TPL_OF_CONTROL),dts/dt.dtb) - $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all + $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.xpl all vpl/u-boot-vpl.bin: vpl/u-boot-vpl @: $(VPL_SIZE_CHECK) vpl/u-boot-vpl: tools prepare $(if $(CONFIG_TPL_OF_CONTROL),dts/dt.dtb) - $(Q)$(MAKE) obj=vpl -f $(srctree)/scripts/Makefile.spl all + $(Q)$(MAKE) obj=vpl -f $(srctree)/scripts/Makefile.xpl all TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include) @@ -133,96 +133,6 @@ run some of U-Boot's tests. See doc/arch/sandbox/sandbox.rst for more details. - -Board Initialisation Flow: --------------------------- - -This is the intended start-up flow for boards. This should apply for both -SPL and U-Boot proper (i.e. they both follow the same rules). - -Note: "SPL" stands for "Secondary Program Loader," which is explained in -more detail later in this file. - -At present, SPL mostly uses a separate code path, but the function names -and roles of each function are the same. Some boards or architectures -may not conform to this. At least most ARM boards which use -CONFIG_SPL_FRAMEWORK conform to this. - -Execution typically starts with an architecture-specific (and possibly -CPU-specific) start.S file, such as: - - - arch/arm/cpu/armv7/start.S - - arch/powerpc/cpu/mpc83xx/start.S - - arch/mips/cpu/start.S - -and so on. From there, three functions are called; the purpose and -limitations of each of these functions are described below. - -lowlevel_init(): - - purpose: essential init to permit execution to reach board_init_f() - - no global_data or BSS - - there is no stack (ARMv7 may have one but it will soon be removed) - - must not set up SDRAM or use console - - must only do the bare minimum to allow execution to continue to - board_init_f() - - this is almost never needed - - return normally from this function - -board_init_f(): - - purpose: set up the machine ready for running board_init_r(): - i.e. SDRAM and serial UART - - global_data is available - - stack is in SRAM - - BSS is not available, so you cannot use global/static variables, - only stack variables and global_data - - Non-SPL-specific notes: - - dram_init() is called to set up DRAM. If already done in SPL this - can do nothing - - SPL-specific notes: - - you can override the entire board_init_f() function with your own - version as needed. - - preloader_console_init() can be called here in extremis - - should set up SDRAM, and anything needed to make the UART work - - there is no need to clear BSS, it will be done by crt0.S - - for specific scenarios on certain architectures an early BSS *can* - be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing - of BSS prior to entering board_init_f()) but doing so is discouraged. - Instead it is strongly recommended to architect any code changes - or additions such to not depend on the availability of BSS during - board_init_f() as indicated in other sections of this README to - maintain compatibility and consistency across the entire code base. - - must return normally from this function (don't call board_init_r() - directly) - -Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at -this point the stack and global_data are relocated to below -CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of -memory. - -board_init_r(): - - purpose: main execution, common code - - global_data is available - - SDRAM is available - - BSS is available, all static/global variables can be used - - execution eventually continues to main_loop() - - Non-SPL-specific notes: - - U-Boot is relocated to the top of memory and is now running from - there. - - SPL-specific notes: - - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and - CONFIG_SYS_FSL_HAS_CCI400 - - Defined For SoC that has cache coherent interconnect - CCN-400 - - CONFIG_SYS_FSL_HAS_CCN504 - - Defined for SoC that has cache coherent interconnect CCN-504 - The following options need to be configured: - CPU Type: Define exactly one, e.g. CONFIG_MPC85XX. @@ -1508,13 +1418,13 @@ Low Level (hardware related) configuration options: This only takes effect if the memory commands are activated globally (CONFIG_CMD_MEMORY). -- CONFIG_SPL_BUILD +- CONFIG_XPL_BUILD Set when the currently running compilation is for an artifact that will end up in one of the 'xPL' builds, i.e. SPL, TPL or VPL. Code that needs phase-specific behaviour can check this, - or (where possible) use spl_phase() instead. + or (where possible) use xpl_phase() instead. - Note that CONFIG_SPL_BUILD *is* always defined when either + Note that CONFIG_XPL_BUILD *is* always defined when either of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be counter-intuitive and should perhaps be changed. @@ -1522,13 +1432,13 @@ Low Level (hardware related) configuration options: Set when the currently running compilation is for an artifact that will end up in the TPL build (as opposed to SPL, VPL or U-Boot proper). Code that needs phase-specific behaviour can - check this, or (where possible) use spl_phase() instead. + check this, or (where possible) use xpl_phase() instead. - CONFIG_VPL_BUILD Set when the currently running compilation is for an artifact that will end up in the VPL build (as opposed to the SPL, TPL or U-Boot proper). Code that needs phase-specific behaviour can - check this, or (where possible) use spl_phase() instead. + check this, or (where possible) use xpl_phase() instead. - CONFIG_ARCH_MAP_SYSMEM Generally U-Boot (and in particular the md command) uses @@ -2516,51 +2426,6 @@ On RISC-V, the following registers are used: ==> U-Boot will use gp to hold a pointer to the global data -Memory Management: ------------------- - -U-Boot runs in system state and uses physical addresses, i.e. the -MMU is not used either for address mapping nor for memory protection. - -The available memory is mapped to fixed addresses using the memory -controller. In this process, a contiguous block is formed for each -memory type (Flash, SDRAM, SRAM), even when it consists of several -physical memory banks. - -U-Boot is installed in the first 128 kB of the first Flash bank (on -TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After -booting and sizing and initializing DRAM, the code relocates itself -to the upper end of DRAM. Immediately below the U-Boot code some -memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN -configuration setting]. Below that, a structure with global Board -Info data is placed, followed by the stack (growing downward). - -Additionally, some exception handler code is copied to the low 8 kB -of DRAM (0x00000000 ... 0x00001FFF). - -So a typical memory configuration with 16 MB of DRAM could look like -this: - - 0x0000 0000 Exception Vector code - : - 0x0000 1FFF - 0x0000 2000 Free for Application Use - : - : - - : - : - 0x00FB FF20 Monitor Stack (Growing downward) - 0x00FB FFAC Board Info Data and permanent copy of global data - 0x00FC 0000 Malloc Arena - : - 0x00FD FFFF - 0x00FE 0000 RAM Copy of Monitor Code - ... eventually: LCD or video framebuffer - ... eventually: pRAM (Protected RAM - unchanged by reset) - 0x00FF FFFF [End of RAM] - - System Initialization: ---------------------- diff --git a/arch/arm/Makefile b/arch/arm/Makefile index dbeedbe544b..cb87a684754 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) CONFIG_CPU_V7A= CONFIG_CPU_ARM720T=y endif @@ -24,7 +24,7 @@ endif # On Tegra systems we must build SPL for the armv4 core on the device # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) arch-y += -D__LINUX_ARM_ARCH__=4 else arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) @@ -106,7 +106,7 @@ libs-y += $(machdirs) head-y := arch/arm/cpu/$(CPU)/start.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs") head-y := arch/arm/cpu/arm926ejs/mxs/start.o endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 5530d02b66c..e0045e22271 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -40,7 +40,7 @@ PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm endif # Choose between ARM/Thumb instruction sets -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \ $(call cc-option, -mthumb -mthumb-interwork,\ @@ -53,7 +53,7 @@ PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \ endif # Only test once -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) archprepare: checkthumb checkgcc6 checkthumb: @@ -99,7 +99,7 @@ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI) ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) # This file is parsed many times, so the string may get added multiple # times. Also, the prefix needs to be different based on whether -# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry +# CONFIG_XPL_BUILD is defined or not. 'filter-out' the existing entry # before adding the correct one. PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \ $(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) @@ -116,7 +116,7 @@ LDFLAGS_u-boot += -pie # # http://sourceware.org/bugzilla/show_bug.cgi?id=12532 # -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) ifeq ($(GAS_BUG_12532),) export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \ then echo y; else echo n; fi) @@ -126,7 +126,7 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls endif endif -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) # Check that only R_ARM_RELATIVE relocations are generated. INPUTS-y += checkarmreloc # The movt / movw can hardcode 16 bit parts of the addresses in the @@ -160,7 +160,7 @@ endif ifdef CONFIG_MACH_IMX ifneq ($(CONFIG_IMX_CONFIG),"") ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-y += SPL endif else diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile index 5dfa01ae8d0..38a3e4d95e2 100644 --- a/arch/arm/cpu/arm11/Makefile +++ b/arch/arm/cpu/arm11/Makefile @@ -5,6 +5,6 @@ obj-y = cpu.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_EFI_LOADER) += sctlr.o endif diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 78a9cc173a3..d3ab5928eee 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -65,7 +65,7 @@ cpu_init_crit: * When booting from NAND - it has definitely been a reset, so, no need * to flush caches and disable the MMU */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * flush v4 I/D caches */ diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 5ac3740621c..06456fe5a81 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -9,6 +9,6 @@ obj-y += cpu.o # some files can only build in ARM mode -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD CFLAGS_cpu.o := -marm endif diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 8cfe3f0fbbc..750cb94dc6e 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -6,7 +6,7 @@ extra-y = start.o obj-y = cpu.o cache.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_NO_CPU_SUPPORT extra-y := endif @@ -17,7 +17,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 1638ef8fd8d..f633e54ba62 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -3,11 +3,11 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -extra-$(CONFIG_SPL_BUILD) := start.o +extra-$(CONFIG_XPL_BUILD) := start.o obj-y = clock.o mxs.o iomux.o timer.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk index 76ffec9df6a..50899d20316 100644 --- a/arch/arm/cpu/arm926ejs/sunxi/config.mk +++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk @@ -1,6 +1,6 @@ # Build a combined spl + u-boot image ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ALL-y += u-boot-sunxi-with-spl.bin endif endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 99cf9eb515f..6461f5f5bde 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,12 +12,12 @@ obj-y += syslib.o obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_EFI_LOADER) += sctlr.o obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o endif -ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y) +ifneq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index aa981faef00..8082f369ed6 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -32,7 +32,7 @@ int cleanup_before_linux_select(int flags) * * we turn off caches etc ... */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD disable_interrupts(); #endif diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 3c8c07fe016..a6c844b7e3d 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -26,7 +26,7 @@ WEAK(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr sp, =CONFIG_SPL_STACK #else ldr sp, =SYS_INIT_SP_ADDR @@ -39,7 +39,7 @@ WEAK(lowlevel_init) * Set up global data for boards that still need it. This will be * removed soon. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD ldr r9, =gdata #else sub sp, sp, #GD_SIZE diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index 0985420fe5c..4660ff0057e 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_ARCH_NEXELL obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o else obj-y += cpu_info.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += timer.o obj-y += sromc.o endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7730a16e512..b63481b43ca 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -279,7 +279,7 @@ ENTRY(cpu_init_cp15) orr r2, r4, r2 @ r2 has combined CPU variant + revision /* Early stack for ERRATA that needs into call C code */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(SYS_INIT_SP_ADDR) diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 3e975b366c4..0624e93efde 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,10 +12,10 @@ obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o obj-$(CONFIG_MACH_SUN6I) += sram.o obj-$(CONFIG_MACH_SUN8I) += sram.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index bba4f570dbb..8747d2eb186 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -6,14 +6,14 @@ extra-y := start.o obj-y += cpu.o -ifndef CONFIG_$(SPL_TPL_)TIMER +ifndef CONFIG_$(PHASE_)TIMER obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o endif -ifndef CONFIG_$(SPL_)SYS_DCACHE_OFF +ifndef CONFIG_$(XPL_)SYS_DCACHE_OFF obj-y += cache_v8.o obj-y += cache.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o else obj-y += exceptions.o @@ -27,14 +27,14 @@ endif obj-y += cpu-dt.o obj-$(CONFIG_ARM_SMCCC) += smccc-call.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o else obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o endif -obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o +obj-$(CONFIG_$(XPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o endif diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 631d9efa5e1..e6be6359c5d 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -1016,7 +1016,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) * running however really wants to have dcache and the MMU active. Check that * everything is sane and give the developer a hint if it isn't. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache. #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index eefdf12369c..e2033dc5aff 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -5,7 +5,7 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2dbfdd08a0..f9c2083677a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -122,7 +122,7 @@ static struct mm_region early_map[] = { { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -181,7 +181,7 @@ static struct mm_region early_map[] = { { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -1055,7 +1055,7 @@ int cpu_eth_init(struct bd_info *bis) { int error = 0; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) error = fsl_mc_ldpaa_init(bis); #endif return error; @@ -1285,7 +1285,7 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) { phys_size_t ram_top = ram_size; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) ram_top = mc_get_dram_block_size(); if (ram_top > ram_size) return ram_size + ram_top; @@ -1381,7 +1381,7 @@ static int tfa_dram_init_banksize(void) if (i > 0) ret = 0; -#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1467,7 +1467,7 @@ int dram_init_banksize(void) } #endif /* CFG_SYS_MEM_RESERVE_SECURE */ -#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1624,7 +1624,7 @@ __weak int dram_init(void) #ifdef CONFIG_SYS_FSL_DDR fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ - defined(CONFIG_SPL_BUILD) + defined(CONFIG_XPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9a24d4b3031..1f03f5e2ecd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -93,7 +93,7 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) rcw_tmp = in_be32(&gur->rcwsr[7]); switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { case 2: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index b768790437f..b5213c780fb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -25,7 +25,7 @@ static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) int xfi_dpmac[XFI14 + 1]; int sgmii_dpmac[SGMII18 + 1]; @@ -162,7 +162,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, debug("Unknown SerDes lane protocol %d\n", lane_prtcl); else { serdes_prtcl_map[lane_prtcl] = 1; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], @@ -553,7 +553,7 @@ int setup_serdes_volt(u32 svdd) void fsl_serdes_init(void) { -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) int i , j; #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index 04ffefafbf7..aa0af077d2f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -23,7 +23,7 @@ static void set_icid(struct icid_id_table *tbl, int size) out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); } -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) static void set_fman_icids(struct fman_icid_id_table *tbl, int size) { int i; @@ -41,12 +41,12 @@ void set_icids(void) /* setup general icid offsets */ set_icid(icid_tbl, icid_tbl_sz); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids) { int i, ret; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 4358c6ed11c..75c204e8309 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -183,7 +183,7 @@ ENTRY(lowlevel_init) #endif /* Initialize GIC Secure Bank Status */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f bl get_gic_offset @@ -306,7 +306,7 @@ ENTRY(lowlevel_init) #endif #if !defined(CONFIG_TFABOOT) && \ - (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD)) bl fsl_ocram_init #endif @@ -314,7 +314,7 @@ ENTRY(lowlevel_init) ret ENDPROC(lowlevel_init) -#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD) ENTRY(fsl_ocram_init) mov x28, lr /* Save LR */ bl fsl_clear_ocram diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index ec80e42055d..48b95627bae 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -60,7 +60,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index a73dd316f8d..ab175b60c6c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index a739ff2da58..1f1e3d4a97b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -41,7 +41,7 @@ u32 spl_boot_device(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { @@ -136,4 +136,4 @@ int spl_start_uboot(void) return 1; } #endif /* CONFIG_SPL_OS_BOOT */ -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 74612802617..4a3b9f60e46 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -58,7 +58,7 @@ reset: .globl save_boot_params_ret save_boot_params_ret: -#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD) +#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_XPL_BUILD) /* Verify that we're 4K aligned. */ adr x0, _start ands x0, x0, #0xfff @@ -104,7 +104,7 @@ pie_skip_reloc: pie_fixup_done: #endif -#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD) .macro set_vbar, regname, reg msr \regname, \reg .endm @@ -174,7 +174,7 @@ pie_fixup_done: /* Processor specific initialization */ bl lowlevel_init -#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_XPL_BUILD) branch_if_master x0, master_cpu b spin_table_secondary_jump /* never return */ @@ -354,7 +354,7 @@ ENDPROC(smp_kick_all_cpus) /*-----------------------------------------------------------------------*/ ENTRY(c_runtime_cpu_setup) -#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD) /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 65176c8fb83..123e121e7e7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -721,13 +721,6 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-pine-h64-model-b.dtb \ sun50i-h6-tanix-tx6.dtb \ sun50i-h6-tanix-tx6-mini.dtb -dtb-$(CONFIG_MACH_SUN50I_H616) += \ - sun50i-h313-tanix-tx1.dtb \ - sun50i-h616-orangepi-zero2.dtb \ - sun50i-h618-orangepi-zero2w.dtb \ - sun50i-h618-orangepi-zero3.dtb \ - sun50i-h618-transpeed-8k618-t.dtb \ - sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ sun50i-a64-bananapi-m64.dtb \ @@ -967,7 +960,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ - imx8mp-debix-model-a.dtb \ imx8mp-dhcom-drc02.dtb \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ diff --git a/arch/arm/dts/bcm6846.dtsi b/arch/arm/dts/bcm6846.dtsi deleted file mode 100644 index 8aa47a2583b..00000000000 --- a/arch/arm/dts/bcm6846.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "brcm,bcm6846", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CA7_0>, <&CA7_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x1b>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm96846.dts b/arch/arm/dts/bcm96846.dts deleted file mode 100644 index c70ebccabc1..00000000000 --- a/arch/arm/dts/bcm96846.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6846.dtsi" - -/ { - model = "Broadcom BCM96846 Reference Board"; - compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi index 33bd89a8434..d5bd9f591e5 100644 --- a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi @@ -20,6 +20,14 @@ }; }; +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + bootph-pre-ram; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-pre-ram; +}; + &crypto { bootph-pre-ram; }; @@ -88,14 +96,6 @@ bootph-pre-ram; }; -&pmic { - bootph-pre-ram; - - regulators { - bootph-pre-ram; - }; -}; - ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts deleted file mode 100644 index 58dae612b4b..00000000000 --- a/arch/arm/dts/imx8mp-debix-model-a.dts +++ /dev/null @@ -1,507 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - * Copyright 2022 Ideas on Board Oy - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/usb/pd.h> - -#include "imx8mp.dtsi" - -/ { - model = "Polyhex Debix Model A i.MX8MPlus board"; - compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-connection-type = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { /* RTL8211E */ - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - reset-assert-us = <20>; - reset-deassert-us = <200000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4{ - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - }; -}; - -&i2c6 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { - /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* SD Card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f - MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f - MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c6: i2c6grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 - MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 - >; - }; -}; - diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi index d316e869516..af229501a4d 100644 --- a/arch/arm/dts/imx8qm-u-boot.dtsi +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -10,7 +10,7 @@ }; &binman { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u-boot-spl-ddr { align = <4>; align-size = <4>; diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi index 7622c40906f..62791c34c77 100644 --- a/arch/arm/dts/imx8qxp-u-boot.dtsi +++ b/arch/arm/dts/imx8qxp-u-boot.dtsi @@ -10,7 +10,7 @@ }; &binman { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u-boot-spl-ddr { align = <4>; align-size = <4>; diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi index 8070b62af5b..6629f3256a8 100644 --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi @@ -17,10 +17,6 @@ }; }; -&canvas { - status = "disabled"; -}; - &vpu { reg = <0x0 0xff900000 0x0 0x100000>, <0x0 0xff63c000 0x0 0x1000>, diff --git a/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi b/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi new file mode 100644 index 00000000000..cbada739042 --- /dev/null +++ b/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> + */ + +#include "meson-g12-common-u-boot.dtsi" + +&sd_emmc_c { + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>; + bus-width = <4>; +}; + +&spifc { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi b/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi new file mode 100644 index 00000000000..1c4f019120f --- /dev/null +++ b/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> + */ + +#include "meson-g12-common-u-boot.dtsi" + +&sd_emmc_c { + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>; + bus-width = <4>; +}; + +&spifc { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h313-tanix-tx1.dts b/arch/arm/dts/sun50i-h313-tanix-tx1.dts deleted file mode 100644 index bb2cde59bd0..00000000000 --- a/arch/arm/dts/sun50i-h313-tanix-tx1.dts +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2024 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Tanix TX1"; - compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - ethernet0 = &sdio_wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key { - label = "hidden"; - linux,code = <BTN_0>; - gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_BLUE>; - gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - default-state = "on"; - }; - }; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - max-frequency = <100000000>; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL, so needs to be always on. */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1120000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts b/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts deleted file mode 100644 index 4bfb52609c9..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. - */ - -/dts-v1/; - -#include "sun50i-h616-bigtreetech-cb1.dtsi" - -/ { - model = "BigTreeTech CB1"; - compatible = "bigtreetech,cb1-manta", "bigtreetech,cb1", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi deleted file mode 100644 index d12b01c5f41..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - aliases { - ethernet0 = &rtl8189ftv; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - }; - }; - - reg_vcc5v: regulator-vcc5v { - /* board wide 5V supply from carrier boards */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc33_wifi: vcc33-wifi { - compatible = "regulator-fixed"; - regulator-name = "vcc33-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; - - reg_vcc_wifi_io: vcc-wifi-io { - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <®_vcc33_wifi>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - post-power-on-delay-ms = <200>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&mmc0 { - vmmc-supply = <®_dldo1>; - /* Card detection pin is not connected */ - broken-cd; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc33_wifi>; - vqmmc-supply = <®_vcc_wifi_io>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - mmc-ddr-1_8v; - status = "okay"; - - rtl8189ftv: wifi@1 { - reg = <1>; - }; -}; - -&r_i2c { - status = "okay"; - - axp313a: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - reg_dcdc1: dcdc1 { - regulator-name = "vdd-gpu-sys"; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-always-on; - }; - - reg_dcdc2: dcdc2 { - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-ramp-delay = <200>; - regulator-always-on; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_aldo1: aldo1 { - regulator-name = "vcc-1v8-pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_dldo1: dldo1 { - regulator-name = "vcc-3v3-io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts b/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts deleted file mode 100644 index ff84a379447..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin@biqu3d.com>. - */ - -/dts-v1/; - -#include "sun50i-h616-bigtreetech-cb1.dtsi" - -/ { - model = "BigTreeTech Pi"; - compatible = "bigtreetech,pi", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi b/arch/arm/dts/sun50i-h616-cpu-opp.dtsi deleted file mode 100644 index aca22a7f019..00000000000 --- a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2023 Martin Botka <martin@somainline.org> - -/ { - cpu_opp_table: opp-table-cpu { - compatible = "allwinner,sun50i-h616-operating-points"; - nvmem-cells = <&cpu_speed_grade>; - opp-shared; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x12>; - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-microvolt-speed1 = <900000>; - opp-microvolt-speed4 = <940000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x12>; - }; - - opp-936000000 { - opp-hz = /bits/ 64 <936000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt-speed0 = <950000>; - opp-microvolt-speed1 = <940000>; - opp-microvolt-speed2 = <950000>; - opp-microvolt-speed3 = <950000>; - opp-microvolt-speed4 = <1020000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt-speed0 = <1000000>; - opp-microvolt-speed2 = <1000000>; - opp-microvolt-speed3 = <1000000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt-speed0 = <1050000>; - opp-microvolt-speed1 = <1020000>; - opp-microvolt-speed2 = <1050000>; - opp-microvolt-speed3 = <1050000>; - opp-microvolt-speed4 = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1d>; - }; - - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt-speed1 = <1100000>; - opp-microvolt-speed3 = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0a>; - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu1 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu2 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu3 { - operating-points-v2 = <&cpu_opp_table>; -}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi deleted file mode 100644 index fc7315b9440..00000000000 --- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Arm Ltd. - * - * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3. - * Excludes PMIC nodes and properties, since they are different between the two. - */ - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_RED>; - gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - default-state = "on"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; - enable-active-high; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - }; -}; - -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on headers only. */ - -&emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-handle = <&ext_rgmii_phy>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts deleted file mode 100644 index a360d8567f9..00000000000 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616-orangepi-zero.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -/ { - model = "OrangePi Zero2"; - compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&emac0 { - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - phy-mode = "rgmii"; - phy-supply = <®_dcdce>; -}; - -&mmc0 { - vmmc-supply = <®_dcdce>; -}; - -&r_rsb { - status = "okay"; - - axp305: pmic@745 { - compatible = "x-powers,axp305", "x-powers,axp805", - "x-powers,axp806"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x745>; - - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-sys"; - }; - - reg_aldo2: aldo2 { /* 3.3V on headers */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext"; - }; - - reg_aldo3: aldo3 { /* 3.3V on headers */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext2"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - bldo2 { - /* unused */ - }; - - bldo3 { - /* unused */ - }; - - bldo4 { - /* unused */ - }; - - cldo1 { - /* reserved */ - }; - - cldo2 { - /* unused */ - }; - - cldo3 { - /* unused */ - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-dram"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-eth-mmc"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pf-supply = <®_aldo1>; - vcc-pg-supply = <®_bldo1>; - vcc-ph-supply = <®_aldo1>; - vcc-pi-supply = <®_aldo1>; -}; diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts deleted file mode 100644 index 26d25b5b59e..00000000000 --- a/arch/arm/dts/sun50i-h616-x96-mate.dts +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "X96 Mate"; - compatible = "hechuang,x96-mate", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdce>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_dcdce>; - vqmmc-supply = <®_bldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp305: pmic@745 { - compatible = "x-powers,axp305", "x-powers,axp805", - "x-powers,axp806"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x745>; - - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-sys"; - }; - - /* Enabled by the Android BSP */ - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext"; - status = "disabled"; - }; - - /* Enabled by the Android BSP */ - reg_aldo3: aldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext2"; - status = "disabled"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Enabled by the Android BSP */ - reg_bldo2: bldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8-2"; - status = "disabled"; - }; - - bldo3 { - /* unused */ - }; - - bldo4 { - /* unused */ - }; - - cldo1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc2v5"; - }; - - cldo2 { - /* unused */ - }; - - cldo3 { - /* unused */ - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vdd-dram"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-eth-mmc"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi deleted file mode 100644 index 921d5f61d8d..00000000000 --- a/arch/arm/dts/sun50i-h616.dtsi +++ /dev/null @@ -1,930 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Arm Ltd. -// based on the H6 dtsi, which is: -// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/sun50i-h616-ccu.h> -#include <dt-bindings/clock/sun50i-h6-r-ccu.h> -#include <dt-bindings/clock/sun6i-rtc.h> -#include <dt-bindings/reset/sun50i-h616-ccu.h> -#include <dt-bindings/reset/sun50i-h6-r-ccu.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * 256 KiB reserved for Trusted Firmware-A (BL31). - * This is added by BL31 itself, but some bootloaders fail - * to propagate this into the DTB handed to kernels. - */ - secmon@40000000 { - reg = <0x0 0x40000000 0x0 0x40000>; - no-map; - }; - }; - - osc24M: osc24M-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - arm,no-tick-in-suspend; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; - - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h616-system-control"; - reg = <0x03000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@28000 { - compatible = "mmio-sram"; - reg = <0x00028000 0x30000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00028000 0x30000>; - }; - }; - - ccu: clock@3001000 { - compatible = "allwinner,sun50i-h616-ccu"; - reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - dma: dma-controller@3002000 { - compatible = "allwinner,sun50i-h616-dma", - "allwinner,sun50i-a100-dma"; - reg = <0x03002000 0x1000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; - clock-names = "bus", "mbus"; - dma-channels = <16>; - dma-requests = <49>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - sid: efuse@3006000 { - compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; - reg = <0x03006000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@14 { - reg = <0x14 0x8>; - }; - - cpu_speed_grade: cpu-speed-grade@0 { - reg = <0x0 2>; - }; - }; - - watchdog: watchdog@30090a0 { - compatible = "allwinner,sun50i-h616-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x030090a0 0x20>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-h616-pinctrl"; - reg = <0x0300b000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - ext_rgmii_pins: rgmii-pins { - pins = "PI0", "PI1", "PI2", "PI3", "PI4", - "PI5", "PI7", "PI8", "PI9", "PI10", - "PI11", "PI12", "PI13", "PI14", "PI15", - "PI16"; - function = "emac0"; - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PI5", "PI6"; - function = "i2c0"; - }; - - i2c3_ph_pins: i2c3-ph-pins { - pins = "PH4", "PH5"; - function = "i2c3"; - }; - - ir_rx_pin: ir-rx-pin { - pins = "PH10"; - function = "ir_rx"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC0", "PC1", "PC5", "PC6", - "PC8", "PC9", "PC10", "PC11", - "PC13", "PC14", "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - spi0_pins: spi0-pins { - pins = "PC0", "PC2", "PC4"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs0_pin: spi0-cs0-pin { - pins = "PC3"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi1_pins: spi1-pins { - pins = "PH6", "PH7", "PH8"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs0_pin: spi1-cs0-pin { - pins = "PH5"; - function = "spi1"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH4"; - function = "spdif"; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH0", "PH1"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - /omit-if-no-ref/ - x32clk_fanout_pin: x32clk-fanout-pin { - pins = "PG10"; - function = "clock"; - }; - }; - - gic: interrupt-controller@3021000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - mmc0: mmc@4020000 { - compatible = "allwinner,sun50i-h616-mmc", - "allwinner,sun50i-a100-mmc"; - reg = <0x04020000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@4021000 { - compatible = "allwinner,sun50i-h616-mmc", - "allwinner,sun50i-a100-mmc"; - reg = <0x04021000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@4022000 { - compatible = "allwinner,sun50i-h616-emmc", - "allwinner,sun50i-a100-emmc"; - reg = <0x04022000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@5000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000000 0x400>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - dmas = <&dma 14>, <&dma 14>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@5000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000400 0x400>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@5000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000800 0x400>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - dmas = <&dma 16>, <&dma 16>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@5000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000c00 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - dmas = <&dma 17>, <&dma 17>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@5001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05001000 0x400>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - dmas = <&dma 18>, <&dma 18>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - uart5: serial@5001400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05001400 0x400>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART5>; - dmas = <&dma 19>, <&dma 19>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART5>; - status = "disabled"; - }; - - i2c0: i2c@5002000 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002000 0x400>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C0>; - dmas = <&dma 43>, <&dma 43>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@5002400 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002400 0x400>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C1>; - dmas = <&dma 44>, <&dma 44>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@5002800 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002800 0x400>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C2>; - dmas = <&dma 45>, <&dma 45>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@5002c00 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002c00 0x400>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C3>; - dmas = <&dma 46>, <&dma 46>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@5003000 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05003000 0x400>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C4>; - dmas = <&dma 47>, <&dma 47>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@5010000 { - compatible = "allwinner,sun50i-h616-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x05010000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@5011000 { - compatible = "allwinner,sun50i-h616-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x05011000 0x1000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac0: ethernet@5020000 { - compatible = "allwinner,sun50i-h616-emac0", - "allwinner,sun50i-a64-emac"; - reg = <0x05020000 0x10000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_EMAC0>; - clock-names = "stmmaceth"; - resets = <&ccu RST_BUS_EMAC0>; - reset-names = "stmmaceth"; - syscon = <&syscon>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - spdif: spdif@5093000 { - compatible = "allwinner,sun50i-h616-spdif"; - reg = <0x05093000 0x400>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - resets = <&ccu RST_BUS_SPDIF>; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - ths: thermal-sensor@5070400 { - compatible = "allwinner,sun50i-h616-ths"; - reg = <0x05070400 0x400>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_THS>; - clock-names = "bus"; - resets = <&ccu RST_BUS_THS>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - allwinner,sram = <&syscon>; - #thermal-sensor-cells = <1>; - }; - - usbotg: usb@5100000 { - compatible = "allwinner,sun50i-h616-musb", - "allwinner,sun8i-h3-musb"; - reg = <0x05100000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@5100400 { - compatible = "allwinner,sun50i-h616-usb-phy"; - reg = <0x05100400 0x24>, - <0x05101800 0x14>, - <0x05200800 0x14>, - <0x05310800 0x14>, - <0x05311800 0x14>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>, - <&ccu CLK_BUS_EHCI2>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy", - "pmu2_clk"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@5101000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05101000 0x100>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@5101400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05101400 0x100>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@5200000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05200000 0x100>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_BUS_EHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>, - <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@5200400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05200400 0x100>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@5310000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05310000 0x100>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_BUS_EHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>, - <&ccu RST_BUS_EHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@5310400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05310400 0x100>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@5311000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05311000 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_BUS_EHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>, - <&ccu RST_BUS_EHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@5311400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05311400 0x100>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h616-rtc"; - reg = <0x07000000 0x400>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, - <&ccu CLK_PLL_SYSTEM_32K>; - clock-names = "bus", "hosc", - "pll-32k"; - #clock-cells = <1>; - }; - - r_ccu: clock@7010000 { - compatible = "allwinner,sun50i-h616-r-ccu"; - reg = <0x07010000 0x210>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - nmi_intc: interrupt-controller@7010320 { - compatible = "allwinner,sun50i-h616-nmi", - "allwinner,sun9i-a80-nmi"; - reg = <0x07010320 0xc>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - }; - - r_pio: pinctrl@7022000 { - compatible = "allwinner,sun50i-h616-r-pinctrl"; - reg = <0x07022000 0x400>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - - /omit-if-no-ref/ - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - }; - }; - - ir: ir@7040000 { - compatible = "allwinner,sun50i-h616-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x07040000 0x400>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1_IR>, - <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_R_APB1_IR>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_rx_pin>; - status = "disabled"; - }; - - r_i2c: i2c@7081400 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x07081400 0x400>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB2_I2C>; - dmas = <&dma 48>, <&dma 48>; - dma-names = "rx", "tx"; - resets = <&r_ccu RST_R_APB2_I2C>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_rsb: rsb@7083000 { - compatible = "allwinner,sun50i-h616-rsb", - "allwinner,sun8i-a23-rsb"; - reg = <0x07083000 0x400>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB2_RSB>; - clock-frequency = <3000000>; - resets = <&r_ccu RST_R_APB2_RSB>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <500>; - polling-delay = <1000>; - thermal-sensors = <&ths 2>; - sustainable-power = <1000>; - - trips { - cpu_threshold: cpu-trip-0 { - temperature = <60000>; - type = "passive"; - hysteresis = <0>; - }; - cpu_target: cpu-trip-1 { - temperature = <70000>; - type = "passive"; - hysteresis = <0>; - }; - cpu_critical: cpu-trip-2 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <500>; - polling-delay = <1000>; - thermal-sensors = <&ths 0>; - sustainable-power = <1100>; - - trips { - gpu_temp_critical: gpu-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - ve-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - - trips { - ve_temp_critical: ve-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 3>; - - trips { - ddr_temp_critical: ddr-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi b/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi deleted file mode 100644 index e92d150aaf1..00000000000 --- a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) Jisheng Zhang <jszhang@kernel.org> - */ - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8-pll"; - }; - - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-io"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; diff --git a/arch/arm/dts/sun50i-h618-longanpi-3h.dts b/arch/arm/dts/sun50i-h618-longanpi-3h.dts deleted file mode 100644 index 18b29c6b867..00000000000 --- a/arch/arm/dts/sun50i-h618-longanpi-3h.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) Jisheng Zhang <jszhang@kernel.org> - */ - -/dts-v1/; - -#include "sun50i-h618-longan-module-3h.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Sipeed Longan Pi 3H"; - compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618"; - - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - color = <LED_COLOR_ID_ORANGE>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <0>; - gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ - }; - - led-1 { - color = <LED_COLOR_ID_ORANGE>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */ - }; - }; - - reg_vcc5v: regulator-vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; -}; - -&axp313 { - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -/* WiFi & BT combo module is connected to this Host */ -&ehci3 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - phy-supply = <®_vcc3v3>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v>; - usb2_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts b/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts deleted file mode 100644 index 6a4f0da9723..00000000000 --- a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "OrangePi Zero 2W"; - compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: vcc3v3 { - /* SY8089 DC/DC converter */ - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_vcc5v>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on the FPC connector (or the exansion board) */ - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; /* internally via VCC-IO */ - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; /* internally via VCC-IO */ - vcc-pi-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL and DRAM */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts deleted file mode 100644 index e1cd7572a14..00000000000 --- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616-orangepi-zero.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -/ { - model = "OrangePi Zero3"; - compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&emac0 { - allwinner,tx-delay-ps = <700>; - phy-mode = "rgmii-rxid"; - phy-supply = <®_dldo1>; -}; - -&ext_rgmii_phy { - motorcomm,clk-out-frequency-hz = <125000000>; -}; - -&mmc0 { - /* - * The schematic shows the card detect pin wired up to PF6, via an - * inverter, but it just doesn't work. - */ - broken-cd; - vmmc-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL, so needs to be always on. */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; diff --git a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts b/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts deleted file mode 100644 index d6631bfe629..00000000000 --- a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Transpeed 8K618-T"; - compatible = "transpeed,8k618-t", "allwinner,sun50i-h618"; - - aliases { - ethernet1 = &sdio_wifi; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: vcc3v3 { - /* discrete 3.3V regulator */ - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dldo1>; - cd-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>; /* PI16 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8-pll"; - }; - - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-io-mmc"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pg-supply = <®_dldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts deleted file mode 100644 index ee30584b6ad..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Anbernic RG35XX 2024"; - chassis-type = "handset"; - compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys_gamepad: gpio-keys-gamepad { - compatible = "gpio-keys"; - - button-a { - label = "Action-Pad A"; - gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_EAST>; - }; - - button-b { - label = "Action-Pad B"; - gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_SOUTH>; - }; - - button-down { - label = "D-Pad Down"; - gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_DOWN>; - }; - - button-l1 { - label = "Key L1"; - gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TL>; - }; - - button-l2 { - label = "Key L2"; - gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TL2>; - }; - - button-left { - label = "D-Pad left"; - gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_LEFT>; - }; - - button-menu { - label = "Key Menu"; - gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_MODE>; - }; - - button-r1 { - label = "Key R1"; - gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TR>; - }; - - button-r2 { - label = "Key R2"; - gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TR2>; - }; - - button-right { - label = "D-Pad Right"; - gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_RIGHT>; - }; - - button-select { - label = "Key Select"; - gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_SELECT>; - }; - button-start { - label = "Key Start"; - gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_START>; - }; - - button-up { - label = "D-Pad Up"; - gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_UP>; - }; - - button-x { - label = "Action-Pad X"; - gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_NORTH>; - }; - - button-y { - label = "Action Pad Y"; - gpios = <&pio 0 2 GPIO_ACTIVE_LOW>; /* PA2 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_WEST>; - }; - }; - - gpio-keys-volume { - compatible = "gpio-keys"; - autorepeat; - - button-vol-up { - label = "Key Volume Up"; - gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; /* PE1 */ - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; - }; - - button-vol-down { - label = "Key Volume Down"; - gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PE2 */ - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ - default-state = "on"; - }; - }; - - reg_vcc5v: regulator-vcc5v { /* USB-C power input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc1>; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_cldo3>; - disable-wp; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_cldo3>; - vcc-pc-supply = <®_cldo3>; - vcc-pe-supply = <®_cldo3>; - vcc-pf-supply = <®_cldo3>; - vcc-pg-supply = <®_aldo4>; - vcc-ph-supply = <®_cldo3>; - vcc-pi-supply = <®_cldo3>; -}; - -&r_rsb { - status = "okay"; - - axp717: pmic@3a3 { - compatible = "x-powers,axp717"; - reg = <0x3a3>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - vin4-supply = <®_vcc5v>; - - regulators { - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <940000>; - regulator-max-microvolt = <940000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - - reg_aldo1: aldo1 { - /* 1.8v - unused */ - }; - - reg_aldo2: aldo2 { - /* 1.8v - unused */ - }; - - reg_aldo3: aldo3 { - /* 1.8v - unused */ - }; - - reg_aldo4: aldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pg"; - }; - - reg_bldo1: bldo1 { - /* 1.8v - unused */ - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pll"; - }; - - reg_bldo3: bldo3 { - /* 2.8v - unused */ - }; - - reg_bldo4: bldo4 { - /* 1.2v - unused */ - }; - - reg_cldo1: cldo1 { - /* 3.3v - audio codec - not yet implemented */ - }; - - reg_cldo2: cldo2 { - /* 3.3v - unused */ - }; - - reg_cldo3: cldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-io"; - }; - - reg_cldo4: cldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_boost: boost { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5200000>; - regulator-name = "boost"; - }; - - reg_cpusldo: cpusldo { - /* unused */ - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */ -&usbotg { - dr_mode = "peripheral"; /* USB type-C receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts deleted file mode 100644 index 63036256917..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - * Copyright (C) 2024 Chris Morgan <macroalpha82@gmail.com>. - */ - -#include "sun50i-h700-anbernic-rg35xx-plus.dts" - -/ { - model = "Anbernic RG35XX H"; - compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; -}; - -&gpio_keys_gamepad { - button-thumbl { - label = "GPIO Thumb Left"; - gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_THUMBL>; - }; - - button-thumbr { - label = "GPIO Thumb Right"; - gpios = <&pio 4 9 GPIO_ACTIVE_LOW>; /* PE9 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_THUMBR>; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts deleted file mode 100644 index 60a8e492210..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - */ - -#include "sun50i-h700-anbernic-rg35xx-2024.dts" - -/ { - model = "Anbernic RG35XX Plus"; - compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700"; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - post-power-on-delay-ms = <200>; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; -}; - -/* SDIO WiFi RTL8821CS */ -&mmc1 { - vmmc-supply = <®_cldo4>; - vqmmc-supply = <®_aldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - interrupt-parent = <&pio>; - interrupts = <6 15 IRQ_TYPE_LEVEL_LOW>; /* PG15 */ - interrupt-names = "host-wake"; - }; -}; - -/* Bluetooth RTL8821CS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; - device-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */ - enable-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>; /* PG19 */ - host-wake-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16 */ - }; -}; diff --git a/arch/arm/dts/tegra-u-boot.dtsi b/arch/arm/dts/tegra-u-boot.dtsi index b3d0dec7757..c200f2d3a0b 100644 --- a/arch/arm/dts/tegra-u-boot.dtsi +++ b/arch/arm/dts/tegra-u-boot.dtsi @@ -19,6 +19,27 @@ }; }; +#ifdef CONFIG_MULTI_DTB_FIT + image2 { + filename = "u-boot-dtb-tegra.bin"; + pad-byte = <0xff>; + u-boot-spl { + }; + u-boot-nodtb { + offset = <(U_BOOT_OFFSET)>; + }; + fit-dtb { +#ifdef CONFIG_MULTI_DTB_FIT_LZO + filename = "fit-dtb.blob.lzo"; +#elif CONFIG_MULTI_DTB_FIT_GZIP + filename = "fit-dtb.blob.gz"; +#else + filename = "fit-dtb.blob"; +#endif + type = "blob"; + }; + }; +#else /* Same as image1 - some tools still expect the -dtb suffix */ image2 { filename = "u-boot-dtb-tegra.bin"; @@ -29,6 +50,7 @@ offset = <(U_BOOT_OFFSET)>; }; }; +#endif image3 { filename = "u-boot-nodtb-tegra.bin"; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index d5f63f4a7ed..22671d4bbfd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -12,13 +12,13 @@ #include <asm/armv8/sec_firmware.h> struct icid_id_table { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD const char *compat; phys_addr_t compat_addr; #endif phys_addr_t reg_addr; u32 reg; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD u32 id; #endif bool le; @@ -35,7 +35,7 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void); void fdt_fixup_icid(void *blob); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ { .reg = regA, \ .reg_addr = addr, \ diff --git a/arch/arm/include/asm/arch-imx8/boot0.h b/arch/arm/include/asm/arch-imx8/boot0.h index 5ce781adb75..fc580b20a46 100644 --- a/arch/arm/include/asm/arch-imx8/boot0.h +++ b/arch/arm/include/asm/arch-imx8/boot0.h @@ -3,7 +3,7 @@ * Copyright 2019 NXP */ -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* * We use absolute address not PC relative address to jump. * When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000, diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 4675dc3c533..b499d975526 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -16,7 +16,7 @@ void lpc32xx_slc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); void lpc32xx_ssp_init(void); void lpc32xx_usb_init(void); -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) void ddr_init(const struct emc_dram_settings *dram); #endif #endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-mx6/litesom.h b/arch/arm/include/asm/arch-mx6/litesom.h index 37a16d2c309..642ed22bffc 100644 --- a/arch/arm/include/asm/arch-mx6/litesom.h +++ b/arch/arm/include/asm/arch-mx6/litesom.h @@ -8,7 +8,7 @@ int litesom_mmc_init(struct bd_info *bis); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void litesom_init_f(void); #endif diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index dbc97b25df8..ad9c1ac906a 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -5,7 +5,7 @@ #ifndef __ASM_ARCH_MX6_DDR_H__ #define __ASM_ARCH_MX6_DDR_H__ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifdef CONFIG_MX6Q #include "mx6q-ddr.h" #else @@ -488,7 +488,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, const struct mx6_mmdc_calibration *, const void *); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define MX6_MMDC_P0_MDCTL 0x021b0000 #define MX6_MMDC_P0_MDPDC 0x021b0004 diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 17afd1b29e4..f8a56495acd 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -14,7 +14,7 @@ int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int), int (*cd)(int)); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if defined(CONFIG_MX23) #include <asm/arch/iomux-mx23.h> diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h index 6bf3828c84e..eaf81554f5b 100644 --- a/arch/arm/include/asm/arch-rk3066/boot0.h +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -10,7 +10,7 @@ * (containing the magic 'RK30'). This magic constant will be written into * the final image by the rkimage tool, but we need to reserve space for it here. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD b 1f /* if overwritten, entry-address is at the next word */ 1: #endif @@ -68,7 +68,7 @@ back_to_bootrom: pop {r1-r12, pc} #endif -#if (defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_XPL_BUILD)) /* U-Boot proper of armv7 does not need this */ b reset #endif diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 0c375e543a5..edb2a31c348 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -12,7 +12,7 @@ * To make life easier for everyone, we build the SPL binary with * space for this 4-byte header already included in the binary. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * We need to add 4 bytes of space for the 'RK33' at the * beginning of the executable. However, as we want to keep @@ -39,7 +39,7 @@ entry_counter: .word 0 #endif -#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64)) +#if (defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARM64)) /* U-Boot proper of armv7 do not need this */ b reset #endif @@ -54,7 +54,7 @@ _start: ARM_VECTORS #endif -#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \ +#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_XPL_BUILD) && \ (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h index 49a1f763795..ae273de3144 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h @@ -11,7 +11,7 @@ #define KHz 1000 #define OSC_HZ (24 * MHz) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define APLL_HZ (1008 * MHz) #else #define APLL_HZ (816 * MHz) @@ -20,7 +20,7 @@ #define CPLL_HZ (500 * MHz) #define HPLL_HZ (1400 * MHz) #define PCLK_PDPMU_HZ (100 * MHz) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define ACLK_PDBUS_HZ (396 * MHz) #else #define ACLK_PDBUS_HZ (500 * MHz) @@ -32,7 +32,7 @@ #define HCLK_PDCORE_HZ (200 * MHz) #define HCLK_PDAUDIO_HZ (150 * MHz) #define CLK_OSC0_DIV_HZ (32768) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define ACLK_PDVI_HZ (297 * MHz) #define CLK_ISP_HZ (297 * MHz) #define ACLK_PDISPP_HZ (297 * MHz) @@ -324,7 +324,7 @@ enum { DCLK_VOP_DIV_SHIFT = 0, DCLK_VOP_DIV_MASK = 0xff, -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) /* CRU_CLK_SEL49_CON */ ACLK_PDVI_SEL_SHIFT = 6, ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT, @@ -397,7 +397,7 @@ enum { CLK_GMAC_SRC_DIV_SHIFT = 0, CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT, -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) /* CRU_CLK_SEL68_CON */ ACLK_PDISPP_SEL_SHIFT = 6, ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT, diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index cad25c50bc6..6b2bb5a4586 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -5,7 +5,7 @@ #include <asm/arch/cpu.h> -#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_XPL_BUILD) /* reserve space for BOOT0 header information */ b reset .space 1532 @@ -49,7 +49,7 @@ .word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr .word SUNXI_SRAMC_BASE .word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_TEXT_BASE diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h index 064602292b6..92c7721a530 100644 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -23,7 +23,7 @@ void sdelay(unsigned long); void return_to_fel(uint32_t lr, uint32_t sp); /* Board / SoC level designware gmac init */ -#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC +#if !defined CONFIG_XPL_BUILD && defined CONFIG_SUN7I_GMAC void eth_init_board(void); #else static inline void eth_init_board(void) {} diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 7a4e0972fb7..a399c94213b 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -68,8 +68,9 @@ struct timerus { /* These are the available SKUs (product types) for Tegra */ enum { - SKU_ID_T20_7 = 0x7, + SKU_ID_AP20 = 0x7, SKU_ID_T20 = 0x8, + SKU_ID_AP20H = 0xf, SKU_ID_T25SE = 0x14, SKU_ID_AP25 = 0x17, SKU_ID_T25 = 0x18, diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index 6e6ea1443cb..2ae109ab6c1 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -336,10 +336,13 @@ struct usb_ctlr { #define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 #define UTMIP_XCVR_HSSLEW_MSB_MASK \ (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 -#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_SHIFT 0 -#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) + +#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) +#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) +#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) +#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) +#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) +#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) /* USBx_UTMIP_XCVR_CFG1_0 */ #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h index 2e8b3359161..05414061a23 100644 --- a/arch/arm/include/asm/arch-tegra30/funcmux.h +++ b/arch/arm/include/asm/arch-tegra30/funcmux.h @@ -16,5 +16,6 @@ enum { /* UART configs */ FUNCMUX_UART1_ULPI = 0, + FUNCMUX_UART5_SDMMC1 = 1, }; #endif /* _TEGRA30_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 15627c96e90..382a6d420a2 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,8 +8,8 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_CHAIN_OF_TRUST -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif /* #ifndef CONFIG_XPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index d4ac567e7ed..19d12696a1e 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -47,6 +47,8 @@ #define ELE_ATTEST_REQ (0xDB) #define ELE_RELEASE_PATCH_REQ (0xDC) #define ELE_OTP_SEQ_SWITH_REQ (0xDD) +#define ELE_WRITE_SHADOW_REQ (0xF2) +#define ELE_READ_SHADOW_REQ (0xF3) /* ELE failure indications */ #define ELE_ROM_PING_FAILURE_IND (0x0A) @@ -154,4 +156,6 @@ int ele_release_m33_trout(void); int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response); int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); int ele_start_rng(void); +int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response); +int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); #endif diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h index a96a8382fb6..514086a1bc4 100644 --- a/arch/arm/include/asm/ti-common/sys_proto.h +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -57,7 +57,7 @@ static inline u8 uboot_loaded_by_spl(void) */ static inline u32 omap_hw_init_context(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD return OMAP_INIT_CONTEXT_SPL; #else if (uboot_loaded_by_spl()) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 67275fba616..f254186c525 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -21,7 +21,7 @@ else obj-y += setjmp.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifdef CONFIG_ARM64 obj-y += relocate_64.o else @@ -34,7 +34,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o else -obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o +obj-$(CONFIG_$(PHASE_)FRAMEWORK) += spl.o ifdef CONFIG_SPL_FRAMEWORK obj-$(CONFIG_CMD_BOOTI) += image.o obj-$(CONFIG_CMD_BOOTZ) += zimage.o @@ -42,14 +42,14 @@ endif obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o endif ifdef CONFIG_ARM64 -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset-arm64.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy-arm64.o else -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy.o endif -obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o -obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o +obj-$(CONFIG_$(PHASE_)SYS_L2_PL310) += cache-pl310.o +obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),) obj-y += save_prev_bl_data.o @@ -73,7 +73,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_$(SPL_TPL_)SYSRESET +ifndef CONFIG_$(PHASE_)SYSRESET obj-y += reset.o endif @@ -94,7 +94,7 @@ endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL ifndef CONFIG_HAS_THUMB2 @@ -129,11 +129,3 @@ CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI) CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI) CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI) - -extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC) -# TODO: As of v2019.01 the relocation code for the EFI application cannot -# be built on ARMv7-M. -ifndef CONFIG_CPU_V7M -#extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC) -endif -extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 648edf308f6..516754caeaf 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -60,7 +60,7 @@ int check_cache_range(unsigned long start, unsigned long stop) ok = 0; if (!ok) { - warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + warn_non_xpl("CACHE: Misaligned operation at range [%08lx, %08lx]\n", start, stop); } diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a0311438b45..3e4906e273d 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -102,7 +102,7 @@ ENTRY(_main) #if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) ldr r0, =(CONFIG_TPL_STACK) -#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(SYS_INIT_SP_ADDR) @@ -119,14 +119,14 @@ ENTRY(_main) bl debug_uart_init #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS) CLEAR_BSS #endif mov r0, #0 bl board_init_f -#if ! defined(CONFIG_SPL_BUILD) +#if ! defined(CONFIG_XPL_BUILD) /* * Set up intermediate environment (new sp and gd) and call @@ -171,13 +171,13 @@ here: bl c_runtime_cpu_setup /* we still call old routine here */ #endif -#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) +#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) -#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS) +#if !defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS) CLEAR_BSS #endif -# ifdef CONFIG_SPL_BUILD +# ifdef CONFIG_XPL_BUILD /* Use a DRAM stack for the rest of SPL, if requested */ bl spl_relocate_stack_gd cmp r0, #0 @@ -185,7 +185,7 @@ here: movne r9, r0 # endif -#if ! defined(CONFIG_SPL_BUILD) +#if ! defined(CONFIG_XPL_BUILD) bl coloured_LED_init bl red_led_on #endif diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index dcc924dd2f4..32401f544a7 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -71,7 +71,7 @@ ENTRY(_main) */ #if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) ldr x0, =(CONFIG_TPL_STACK) -#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) #elif defined(CONFIG_INIT_SP_RELATIVE) #if CONFIG_POSITION_INDEPENDENT @@ -99,7 +99,7 @@ ENTRY(_main) mov x0, #0 bl board_init_f -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /* * Set up intermediate environment (new sp and gd) and call * relocate_code(addr_moni). Trick here is that we'll return @@ -139,9 +139,9 @@ relocation_return: * Set up final (full) environment */ bl c_runtime_cpu_setup /* still call old routine */ -#endif /* !CONFIG_SPL_BUILD */ -#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) -#if defined(CONFIG_SPL_BUILD) +#endif /* !CONFIG_XPL_BUILD */ +#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) +#if defined(CONFIG_XPL_BUILD) bl spl_relocate_stack_gd /* may return NULL */ /* set up gd here, outside any C code, if new stack is returned */ cmp x0, #0 diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index 0a96ba1355f..602efe04c04 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -12,7 +12,7 @@ int raise (int signum) { /* Even if printf() is available, it's large. Punt it for SPL builds */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) printf("raise: Signal # %d caught\n", signum); #endif return 0; diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index 2b21ec0734e..78507b76894 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; int arch_reserve_stacks(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ gd->irq_sp = gd->start_addr_sp; #else diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index b6b879339df..cf3f6c3e65c 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -133,7 +133,7 @@ _fiq: .word fiq /* SPL interrupt handling: just hang */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) .align 5 @@ -166,7 +166,7 @@ fiq: b 1b /* hang and never return */ #endif -#else /* !CONFIG_SPL_BUILD */ +#else /* !CONFIG_XPL_BUILD */ /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN @@ -332,4 +332,4 @@ fiq: bad_save_user_regs bl do_fiq -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c index 51287251b3f..7e1cd4dd8bc 100644 --- a/arch/arm/lib/zimage.c +++ b/arch/arm/lib/zimage.c @@ -24,14 +24,14 @@ int bootz_setup(ulong image, ulong *start, ulong *end) if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC && zi->zi_magic != BAREBOX_IMAGE_MAGIC) { - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) puts("zimage: Bad magic!\n"); return 1; } *start = zi->zi_start; *end = zi->zi_end; - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start, *end); diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile index 448d3201aff..18f9f75e8ef 100644 --- a/arch/arm/mach-aspeed/ast2600/Makefile +++ b/arch/arm/mach-aspeed/ast2600/Makefile @@ -1,2 +1,2 @@ obj-y += lowlevel_init.o board_common.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/arch/arm/mach-aspeed/ast2600/lowlevel_init.S b/arch/arm/mach-aspeed/ast2600/lowlevel_init.S index 594963d039d..d1c31068685 100644 --- a/arch/arm/mach-aspeed/ast2600/lowlevel_init.S +++ b/arch/arm/mach-aspeed/ast2600/lowlevel_init.S @@ -97,7 +97,7 @@ .globl lowlevel_init lowlevel_init: -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) mov pc, lr #else /* setup ARM arch timer frequency */ diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index cbd0ed68c27..447cd80642c 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o -ifneq ($(CONFIG_SPL_BUILD),) +ifneq ($(CONFIG_XPL_BUILD),) obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index a8916862b3f..8f0bc5d997e 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o obj-$(CONFIG_SAM9X60) += sam9x60_devices.o obj-y += clock.o obj-y += cpu.o -ifndef CONFIG_$(SPL_TPL_)SYSRESET +ifndef CONFIG_$(PHASE_)SYSRESET obj-y += reset.o endif ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) @@ -32,7 +32,7 @@ obj-y += lowlevel_init.o endif endif -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cache.o := -marm diff --git a/arch/arm/mach-at91/config.mk b/arch/arm/mach-at91/config.mk index 5426394651e..a31612b8179 100644 --- a/arch/arm/mach-at91/config.mk +++ b/arch/arm/mach-at91/config.mk @@ -3,7 +3,7 @@ PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) endif ifeq ($(CONFIG_CPU_V7A),y) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-y += u-boot.img endif endif diff --git a/arch/arm/mach-bcmbca/bcm6846/Kconfig b/arch/arm/mach-bcmbca/bcm6846/Kconfig index 229ab88dbb0..1f5639f46df 100644 --- a/arch/arm/mach-bcmbca/bcm6846/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6846/Kconfig @@ -8,6 +8,10 @@ if BCM6846 config TARGET_BCM96846 bool "Broadcom 6846 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM + imply MTD_RAW_NAND + imply NAND_BRCMNAND + imply NAND_BRCMNAND_BCMBCA config SYS_SOC default "bcm6846" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index ae171e3ee22..c994f97bab8 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -9,7 +9,7 @@ obj-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o obj-$(CONFIG_SOC_DA850) += da850_pinmux.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o endif diff --git a/arch/arm/mach-davinci/config.mk b/arch/arm/mach-davinci/config.mk index edbac8e8e21..3b972a26c0c 100644 --- a/arch/arm/mach-davinci/config.mk +++ b/arch/arm/mach-davinci/config.mk @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2012, Texas Instruments, Incorporated - https://www.ti.com/ -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais endif diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 6c97e5810cd..07125eac7cd 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index dd097cf5418..ebdc3b89d05 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o obj-$(CONFIG_EXYNOS5420) += sec_boot.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 0967ab995a9..0c50b2e2b99 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -221,8 +221,8 @@ int do_lowlevel_init(void) if (actions & DO_CLOCKS) { system_clock_init(); #ifdef CONFIG_DEBUG_UART -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ - !defined(CONFIG_SPL_BUILD) +#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ + !defined(CONFIG_XPL_BUILD) exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); debug_uart_init(); #endif diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 07d19fd17ba..48c325190d5 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -171,7 +171,7 @@ static int exynos5420_mmc_config(int peripheral, int flags) * this same assumption. */ if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD gpio_request(i, "sdmmc0_vdden"); #endif gpio_set_value(i, 1); diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index f8903afc92e..21d955b4aef 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -10,7 +10,7 @@ obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),imx8m)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o @@ -22,7 +22,7 @@ obj-y += cpu.o endif ifeq ($(SOC),$(filter $(SOC),imx8m imx9)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-y += fdt.o endif endif @@ -38,7 +38,7 @@ endif ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imx9 imxrt)) obj-y += misc.o obj-$(CONFIG_CMD_PRIBLOB) += priblob.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o @@ -46,7 +46,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o endif ifeq ($(SOC),$(filter $(SOC),mx7 imx8m)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o endif endif @@ -57,10 +57,10 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o init.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif -obj-$(CONFIG_$(SPL_)SATA) += sata.o +obj-$(CONFIG_$(XPL_)SATA) += sata.o obj-$(CONFIG_IMX_HAB) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif @@ -73,18 +73,18 @@ obj-y += ddrmc-vf610.o obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o endif ifeq ($(SOC),$(filter $(SOC),imx8)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif endif -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o endif -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o endif @@ -128,7 +128,7 @@ container.cfg: $(IMX_CONTAINER_CFG) FORCE ifeq ($(CONFIG_ARCH_IMX8), y) CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh IMAGE_TYPE := imx8image -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi) endif DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index ceee31eecd7..17de9ff98ec 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -39,7 +39,7 @@ u32 get_imx_reset_cause(void) if (reset_cause == -1) { reset_cause = readl(&src_regs->srsr); /* preserve the value for U-Boot proper */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) writel(reset_cause, &src_regs->srsr); #endif } @@ -47,7 +47,7 @@ u32 get_imx_reset_cause(void) return reset_cause; } -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) static char *get_reset_cause(void) { switch (get_imx_reset_cause()) { @@ -92,7 +92,7 @@ static char *get_reset_cause(void) } #endif -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) const char *get_imx_type(u32 imxtype) { diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 85d90686f68..a8107f46ae5 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -245,7 +245,7 @@ void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset, return ret; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */ @@ -727,7 +727,7 @@ U_BOOT_CMD( "" ); -#endif /* !defined(CONFIG_SPL_BUILD) */ +#endif /* !defined(CONFIG_XPL_BUILD) */ /* Get CSF Header length */ static int get_hab_hdr_len(struct hab_hdr *hdr) @@ -939,7 +939,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, puts("Dumping CSF Header\n"); print_buffer(ivt->csf, (void *)(uintptr_t)(ivt->csf), 4, 0x10, 0); -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) get_hab_status(); #endif @@ -989,7 +989,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, } hab_exit_failure_print_status: -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) get_hab_status(); #endif diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index ed44df394b1..324e010bb2c 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -345,9 +345,9 @@ int ahab_close(void) u16 lc; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in get lifecycle\n"); - return -EIO; + return err; } if (lc != 0x20) { @@ -357,9 +357,9 @@ int ahab_close(void) } err = sc_seco_forward_lifecycle(-1, 16); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in forward lifecycle to OEM closed\n"); - return -EIO; + return err; } return 0; diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 834aca82bcf..37a5473ac7c 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -48,7 +48,7 @@ static char *get_reset_cause(void) { sc_pm_reset_reason_t reason; - if (sc_pm_reset_reason(-1, &reason) != SC_ERR_NONE) + if (sc_pm_reset_reason(-1, &reason)) return "Unknown reset"; switch (reason) { @@ -89,11 +89,11 @@ __weak void reset_cpu(void) int arch_cpu_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) spl_save_restore_data(); #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct pass_over_info_t *pass_over; if (is_soc_rev(CHIP_REV_A)) { @@ -160,6 +160,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) sc_faddr_t tcml_addr; u32 tcml_size = SZ_128K; ulong addr; + int ret; switch (core_id) { case 0: @@ -187,10 +188,12 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Power on M4 and MU\n"); - if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON); + if (ret) + return ret; - if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON); + if (ret) return -EIO; printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr); @@ -199,7 +202,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) memcpy((void *)tcml_addr, (void *)addr, tcml_size); printf("Start M4 %u\n", core_id); - if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE) + ret = sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr); + if (ret) return -EIO; printf("bootaux complete\n"); @@ -214,6 +218,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) sc_faddr_t aux_core_ram; u32 size; ulong addr; + int ret; switch (core_id) { case 0: @@ -242,20 +247,23 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Power on aux core %d\n", core_id); - if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON); + if (ret) + return ret; if (mu_rsrc != SC_R_NONE) { - if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON); + if (ret) return -EIO; } if (core_id == 1) { struct power_domain pd; - if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) { + ret = sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false); + if (ret) { printf("Error enable clock\n"); - return -EIO; + return ret; } if (!imx8_power_domain_lookup_name("audio_sai0", &pd)) { @@ -286,8 +294,9 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); - if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram); + if (ret) + return ret; printf("bootaux complete\n"); return 0; @@ -313,7 +322,7 @@ int arch_auxiliary_core_check_up(u32 core_id) return 0; } - if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE) + if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode)) return 0; if (power_mode != SC_PM_PW_MODE_OFF) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index d1fdaec7043..9d1fabe91c0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -197,6 +197,7 @@ config TARGET_IMX8MP_DEBIX_MODEL_A select IMX8MP select IMX8M_LPDDR4 select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d7fd102c955..d5745f67262 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -51,7 +51,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 43e677deae2..2f53430b4d0 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -611,7 +611,7 @@ void dram_disable_bypass(void) CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void dram_pll_init(ulong pll_val) { u32 val; @@ -791,7 +791,7 @@ int clock_init(void) /* * Dump some clockes. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5293cb85e56..a72329ea919 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -45,7 +45,7 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = { int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); @@ -255,7 +255,7 @@ int dram_init(void) return ret; /* rom_pointer[1] contains the size of TEE occupies */ - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) gd->ram_size = sdram_size - rom_pointer[1]; else gd->ram_size = sdram_size; @@ -284,7 +284,7 @@ int dram_init_banksize(void) } gd->bd->bi_dram[bank].start = PHYS_SDRAM; - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; @@ -329,7 +329,7 @@ phys_size_t get_effective_memsize(void) sdram_b1_size = sdram_size; } - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { /* We will relocate u-boot to Top of dram1. Tee position has two cases: * 1. At the top of dram1, Then return the size removed optee size. @@ -612,7 +612,7 @@ static void early_enable_caches(void) phys_size_t sdram_size; int entry, ret; - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return; if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) @@ -646,7 +646,7 @@ int arch_cpu_init(void) * ROM might disable clock for SCTR, * enable the clock before timer_init. */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) clock_enable(CCGR_SCTR, 1); /* * Init timer at very early state, because sscg pll setting @@ -654,7 +654,7 @@ int arch_cpu_init(void) */ timer_init(); - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { clock_init(); imx_set_wdog_powerdown(false); @@ -1477,7 +1477,7 @@ int arch_misc_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) bool serror_need_skip = true; diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 2c9938fcdf0..b478dab59d0 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -6,6 +6,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += upower/ endif diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index fadf165ece2..c390f20d769 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -519,7 +519,7 @@ u32 get_lpuart_clk(void) return pcc_clock_get_rate(lpuart_pcc[index], lpuart_pcc_slots[index]); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S index 791c26407c9..9ede695dbba 100644 --- a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S +++ b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S @@ -16,7 +16,7 @@ rom_pointer: .global save_boot_params save_boot_params: -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* The firmware provided ATAG/FDT address can be found in r2/x0 */ adr x0, rom_pointer stp x1, x2, [x0], #16 diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index c3722c60836..b5dc45296d1 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -104,7 +104,7 @@ enum bt_mode get_boot_mode(void) bool m33_image_booted(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { u32 gp6 = 0; /* DGO_GP6 */ @@ -124,7 +124,7 @@ bool m33_image_booted(void) bool rdc_enabled_in_boot(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { u32 val = 0; int ret; bool rdc_en = true; /* Default assume DBD_EN is set */ @@ -146,7 +146,7 @@ bool rdc_enabled_in_boot(void) static void spl_pass_boot_info(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { bool m33_booted = m33_image_booted(); bool rdc_en = rdc_enabled_in_boot(); u32 val = 0; @@ -164,7 +164,7 @@ static void spl_pass_boot_info(void) bool is_m33_handshake_necessary(void) { /* Only need handshake in u-boot */ - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) return (m33_image_booted() || rdc_enabled_in_boot()); else return false; @@ -716,7 +716,7 @@ void set_lpav_qos(void) int arch_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* Enable System Reset Interrupt using WDOG_AD */ setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13)); /* Clear AD_PERIPH Power switch domain out of reset interrupt flag */ @@ -805,7 +805,7 @@ int imx8ulp_dm_post_init(void) } EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init); -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index e1b09ab5341..45a9105a75a 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -5,6 +5,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o clock_root.o trdc.o -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD obj-y += imx_bootaux.o #endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 12685f970de..dda57ed7f55 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -640,7 +640,7 @@ void enable_usboh3_clk(unsigned char enable) } } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void dram_pll_init(ulong pll_val) { configure_fracpll(DRAM_PLL_CLK, pll_val); @@ -950,7 +950,7 @@ int set_clk_enet(enum enet_freq type) /* * Dump some clockes. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { u32 freq; diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S index 1dc1dbfcddc..97d85911041 100644 --- a/arch/arm/mach-imx/imx9/lowlevel_init.S +++ b/arch/arm/mach-imx/imx9/lowlevel_init.S @@ -16,7 +16,7 @@ rom_pointer: .global save_boot_params save_boot_params: -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* The firmware provided ATAG/FDT address can be found in r2/x0 */ adr x0, rom_pointer stp x1, x2, [x0], #16 diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 04b21207a28..7c28fa39e14 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -383,7 +383,7 @@ int dram_init(void) return ret; /* rom_pointer[1] contains the size of TEE occupies */ - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) gd->ram_size = sdram_size - rom_pointer[1]; else gd->ram_size = sdram_size; @@ -412,7 +412,7 @@ int dram_init_banksize(void) } gd->bd->bi_dram[bank].start = PHYS_SDRAM; - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; @@ -457,7 +457,7 @@ phys_size_t get_effective_memsize(void) else sdram_b1_size = sdram_size; - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { /* We will relocate u-boot to top of dram1. TEE position has two cases: * 1. At the top of dram1, Then return the size removed optee size. * 2. In the middle of dram1, return the size of dram1. @@ -629,7 +629,7 @@ static int low_drive_freq_update(void *blob) } #ifdef CONFIG_OF_BOARD_FIXUP -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int board_fix_fdt(void *fdt) { /* Update dtb clocks for low drive mode */ @@ -701,7 +701,7 @@ static void save_reset_cause(void) int arch_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* Disable wdog */ init_wdog(); @@ -745,7 +745,7 @@ EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu); int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 0b8a10fd729..41116e2c6a2 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -940,7 +940,7 @@ void mxc_set_sata_internal_clock(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx6/Makefile b/arch/arm/mach-imx/mx6/Makefile index 7ea8f91e4f0..da461b0be9b 100644 --- a/arch/arm/mach-imx/mx6/Makefile +++ b/arch/arm/mach-imx/mx6/Makefile @@ -7,7 +7,7 @@ obj-y := soc.o clock.o obj-$(CONFIG_IMX_MODULE_FUSE) += module_fuse.o -obj-$(CONFIG_SPL_BUILD) += ddr.o +obj-$(CONFIG_XPL_BUILD) += ddr.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_MX6UL_LITESOM) += litesom.o obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index fb9f56d2e63..b5aa606b8d0 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1367,7 +1367,7 @@ void disable_ipu_clock(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 03e1214c060..c6bf933df94 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -78,7 +78,7 @@ int litesom_mmc_init(struct bd_info *bis) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/mx6-ddr.h> diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index 340e6147b63..6a79dcb5bd1 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -79,7 +79,7 @@ int dram_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <asm/arch/mx6-ddr.h> #include <linux/libfdt.h> #include <spl.h> @@ -210,4 +210,4 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 2c0c77e1a56..9b40fe9235a 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -37,7 +37,7 @@ struct scu_regs { u32 fpga_rev; }; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx6_thermal_plat = { .regs = (void *)ANATOP_BASE_ADDR, .fuse_bank = 1, @@ -565,7 +565,7 @@ int board_postclk_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * cfg_val will be used for * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] @@ -600,7 +600,7 @@ const struct boot_mode soc_boot_modes[] = { void reset_misc(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO) lcdif_power_down(); #endif diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index a8606fa9b24..a8328a0b224 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -1100,7 +1100,7 @@ void epdc_clock_disable(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 16c77cbf7be..1b891a2db3d 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -432,7 +432,7 @@ void s_init(void) return; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD const struct boot_mode soc_boot_modes[] = { {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, {"primary", MAKE_CFGVAL_PRIMARY_BOOT}, @@ -450,7 +450,7 @@ int boot_mode_getprisec(void) void reset_misc(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO) lcdif_power_down(); #endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index fb19c62a520..eca92955a17 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -327,7 +327,7 @@ void hab_caam_clock_enable(unsigned char enable) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 198ae2d919c..980e0226156 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -171,7 +171,7 @@ static bool ldo_mode_is_enabled(void) return false; } -#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) +#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_XPL_BUILD)) #if defined(CONFIG_LDO_ENABLED_MODE) static void init_ldo_mode(void) { diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 922f851c56b..96fe2c7c17b 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec) return usec; } -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_SPL_BUILD) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_XPL_BUILD) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile index 1717ca343d6..e2ef88196f8 100644 --- a/arch/arm/mach-k3/am62ax/Makefile +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o -obj-$(CONFIG_SPL_BUILD) += am62a7_init.o +obj-$(CONFIG_XPL_BUILD) += am62a7_init.o diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile index eed91a033eb..3165435f265 100644 --- a/arch/arm/mach-k3/am62px/Makefile +++ b/arch/arm/mach-k3/am62px/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o -obj-$(CONFIG_SPL_BUILD) += am62p5_init.o +obj-$(CONFIG_XPL_BUILD) += am62p5_init.o diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile index 8494cdda482..ca10b6a8d3d 100644 --- a/arch/arm/mach-k3/am62x/Makefile +++ b/arch/arm/mach-k3/am62x/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o -obj-$(CONFIG_SPL_BUILD) += am625_init.o +obj-$(CONFIG_XPL_BUILD) += am625_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile index d0b286276c8..053a8239999 100644 --- a/arch/arm/mach-k3/am64x/Makefile +++ b/arch/arm/mach-k3/am64x/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += am642_init.o +obj-$(CONFIG_XPL_BUILD) += am642_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am65x/Makefile b/arch/arm/mach-k3/am65x/Makefile index 20d5f1d3bf1..34734f24ff7 100644 --- a/arch/arm/mach-k3/am65x/Makefile +++ b/arch/arm/mach-k3/am65x/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o -obj-$(CONFIG_SPL_BUILD) += am654_init.o +obj-$(CONFIG_XPL_BUILD) += am654_init.o diff --git a/arch/arm/mach-k3/arm64/cache.S b/arch/arm/mach-k3/arm64/cache.S index 17cfb12f108..6a507ae3af5 100644 --- a/arch/arm/mach-k3/arm64/cache.S +++ b/arch/arm/mach-k3/arm64/cache.S @@ -7,7 +7,7 @@ #include <config.h> #include <linux/linkage.h> -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) ENTRY(__asm_invalidate_l3_dcache) /* Invalidate SPL address range */ mov x0, #CONFIG_SPL_TEXT_BASE diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile index 982b88db57d..e4b0e5a8193 100644 --- a/arch/arm/mach-k3/j721e/Makefile +++ b/arch/arm/mach-k3/j721e/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o -obj-$(CONFIG_SPL_BUILD) += j721e_init.o +obj-$(CONFIG_XPL_BUILD) += j721e_init.o diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile index ceef68297c9..051ef1b11d8 100644 --- a/arch/arm/mach-k3/j721s2/Makefile +++ b/arch/arm/mach-k3/j721s2/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o -obj-$(CONFIG_SPL_BUILD) += j721s2_init.o +obj-$(CONFIG_XPL_BUILD) += j721s2_init.o diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index 05453fcad41..64c34d3dbd6 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -312,7 +312,7 @@ void do_dt_magic(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { k3_spl_init(); diff --git a/arch/arm/mach-k3/j722s/Makefile b/arch/arm/mach-k3/j722s/Makefile index 2b1fec131ed..9b0dd8afd8b 100644 --- a/arch/arm/mach-k3/j722s/Makefile +++ b/arch/arm/mach-k3/j722s/Makefile @@ -4,4 +4,4 @@ # Jayesh Choudhary <j-choudhary@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j722s_fdt.o -obj-$(CONFIG_SPL_BUILD) += j722s_init.o +obj-$(CONFIG_XPL_BUILD) += j722s_init.o diff --git a/arch/arm/mach-k3/j784s4/Makefile b/arch/arm/mach-k3/j784s4/Makefile index 6d1841e3f9e..1d51bcf6e8c 100644 --- a/arch/arm/mach-k3/j784s4/Makefile +++ b/arch/arm/mach-k3/j784s4/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o -obj-$(CONFIG_SPL_BUILD) += j784s4_init.o +obj-$(CONFIG_XPL_BUILD) += j784s4_init.o diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile index d3886caa064..f533c5e7743 100644 --- a/arch/arm/mach-k3/r5/Makefile +++ b/arch/arm/mach-k3/r5/Makefile @@ -16,6 +16,6 @@ obj-y += common.o obj-y += lowlevel_init.o obj-y += r5_mpu.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 7c46914d9dd..3468a370a45 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -126,7 +126,7 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index 6c7c25090a2..c864317baea 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -10,7 +10,7 @@ obj-y += psc.o obj-y += clock.o obj-y += mon.o CFLAGS_REMOVE_mon.o := $(LTO_CFLAGS) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cmd_clock.o obj-y += cmd_mon.o obj-y += cmd_poweroff.o diff --git a/arch/arm/mach-keystone/config.mk b/arch/arm/mach-keystone/config.mk index 8eccbdb3018..925a2deee23 100644 --- a/arch/arm/mach-keystone/config.mk +++ b/arch/arm/mach-keystone/config.mk @@ -7,7 +7,7 @@ include $(srctree)/arch/arm/mach-omap2/config_secure.mk -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifeq ($(CONFIG_TI_SECURE_DEVICE),y) INPUTS-y += u-boot_HS_MLO else @@ -25,7 +25,7 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE $(call if_changed,pad_cat) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) -n U-Boot MLO: u-boot.bin FORCE diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index b945e19ec77..f99b9fbca2e 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -134,7 +134,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile index 6303570beea..f551abb4772 100644 --- a/arch/arm/mach-lpc32xx/Makefile +++ b/arch/arm/mach-lpc32xx/Makefile @@ -5,4 +5,4 @@ obj-y = cpu.o clk.o devices.o timer.o -obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o +obj-$(CONFIG_XPL_BUILD) += dram.o lowlevel_init.o diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 46bdab88206..3d9e4684fb4 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += cpu.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT7622) += mt7622/ diff --git a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S index 0a0672cbea7..9f19003e43b 100644 --- a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S +++ b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S @@ -16,7 +16,7 @@ ENTRY(lowlevel_init) -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Return to U-Boot via saved link register */ mov pc, lr #else diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 329c2e49153..35fd2d0a1d2 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -22,7 +22,7 @@ else # CONFIG_ARCH_KIRKWOOD obj-y = cpu.o obj-y += dram.o obj-y += lowlevel.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o @@ -110,11 +110,11 @@ $(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ include/config/auto.conf $(call cmd,kwbcfg) -endif # CONFIG_SPL_BUILD +endif # CONFIG_XPL_BUILD obj-y += gpio.o obj-y += mbus.o -obj-$(CONFIG_SPL_BUILD) += spl.o -obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += lowlevel_spl.o obj-$(CONFIG_ARMADA_38X) += serdes/a38x/ obj-$(CONFIG_ARMADA_XP) += serdes/axp/ diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 8a145a5f742..da44727cf4f 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -52,7 +52,7 @@ void lowlevel_init(void) */ } -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) void reset_cpu(void) { struct mvebu_system_registers *reg = @@ -549,7 +549,7 @@ static void ahci_mvebu_mbus_config(void __iomem *base) int i; /* mbus is not initialized in SPL; keep the ROM settings */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return; dram = mvebu_mbus_dram_info(); diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index af6ce2920e6..37a00501214 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -66,7 +66,7 @@ enum cpu_attrib { /* * Default Device Address MAP BAR values */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_ARMADA_38X #define MBUS_PCI_MEM_BASE 0x88000000 #define MBUS_PCI_MEM_SIZE ((3 * 128) << 20) @@ -81,19 +81,19 @@ enum cpu_attrib { #define MBUS_PCI_IO_BASE 0xF1100000 #define MBUS_PCI_IO_SIZE ((MBUS_PCI_MAX_PORTS * 64) << 10) #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define MBUS_SPI_BASE 0xD4000000 #define MBUS_SPI_SIZE (64 << 20) #else #define MBUS_SPI_BASE 0xF4000000 #define MBUS_SPI_SIZE (8 << 20) #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define MBUS_DFX_BASE 0xF6000000 #define MBUS_DFX_SIZE (1 << 20) #endif #define MBUS_BOOTROM_BASE 0xF8000000 -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define MBUS_BOOTROM_SIZE (128 << 20) #else #define MBUS_BOOTROM_SIZE (8 << 20) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index dc68d406f99..495530d8452 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -36,7 +36,7 @@ /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700) +#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARMADA_3700) /* * The SPL U-Boot version still runs with the default * address for the internal registers, configured by diff --git a/arch/arm/mach-mvebu/serdes/a38x/Makefile b/arch/arm/mach-mvebu/serdes/a38x/Makefile index 5a70b375966..c33e272217d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/Makefile +++ b/arch/arm/mach-mvebu/serdes/a38x/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec-38x.o -obj-$(CONFIG_SPL_BUILD) += seq_exec.o -obj-$(CONFIG_SPL_BUILD) += sys_env_lib.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec-38x.o +obj-$(CONFIG_XPL_BUILD) += seq_exec.o +obj-$(CONFIG_XPL_BUILD) += sys_env_lib.o diff --git a/arch/arm/mach-mvebu/serdes/axp/Makefile b/arch/arm/mach-mvebu/serdes/axp/Makefile index 897afb703ad..7d48f8da9ed 100644 --- a/arch/arm/mach-mvebu/serdes/axp/Makefile +++ b/arch/arm/mach-mvebu/serdes/axp/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o +obj-$(CONFIG_XPL_BUILD) = high_speed_env_lib.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec.o diff --git a/arch/arm/mach-nexell/include/mach/display.h b/arch/arm/mach-nexell/include/mach/display.h index b0ee9126057..3a4e2c47f5e 100644 --- a/arch/arm/mach-nexell/include/mach/display.h +++ b/arch/arm/mach-nexell/include/mach/display.h @@ -265,7 +265,7 @@ int dp_plane_set_enable(int module, int layer, int on); int dp_plane_set_address(int module, int layer, unsigned int address); int dp_plane_wait_vsync(int module, int layer, int fps); -#if defined CONFIG_SPL_BUILD || \ +#if defined CONFIG_XPL_BUILD || \ (!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)) int nx_display_probe(struct nx_display_plat *plat); #endif diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d683c64566a..fb5ea97e56e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -11,7 +11,7 @@ obj-y += reset.o ifeq ($(CONFIG_TIMER),) obj-y += timer.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += timer.o endif endif @@ -26,7 +26,7 @@ obj-y += vc.o obj-y += abb.o endif -ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),) +ifeq ($(CONFIG_$(PHASE_)SYS_DCACHE_OFF),) obj-y += omap-cache.o endif diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 3f1af7f1633..6f3587f01d0 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -11,7 +11,7 @@ endif obj-y += sys_info.o obj-y += ddr.o -ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) obj-y += emif4.o endif obj-y += board.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index abdc1e40335..4e9ad8935e3 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -209,7 +209,7 @@ int cpu_mmc_init(struct bd_info *bis) /* AM33XX has two MUSB controllers which can be host or gadget */ #if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ - defined(CONFIG_SPL_BUILD) + defined(CONFIG_XPL_BUILD) static struct musb_hdrc_config musb_config = { .multipoint = 1, @@ -282,7 +282,7 @@ int arch_misc_init(void) #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) + (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) static void rtc32k_unlock(struct davinci_rtc *rtc) { /* @@ -295,7 +295,7 @@ static void rtc32k_unlock(struct davinci_rtc *rtc) } #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) /* * Write contents of the RTC_SCRATCH1 register based on board type * Two things are passed @@ -331,7 +331,7 @@ int board_early_init_f(void) { set_mux_conf_regs(); prcm_init(); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) update_rtc_magic(); #endif return 0; @@ -379,7 +379,7 @@ static void watchdog_disable(void) ; } -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) /* * Check if we are executing rtc-only + DDR mode, and resume from it if needed */ @@ -455,7 +455,7 @@ am43xx_wait: void s_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) rtc_only(); #endif } @@ -474,7 +474,7 @@ void early_system_init(void) set_uart_mux_conf(); setup_early_clocks(); uart_soft_reset(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, @@ -483,7 +483,7 @@ void early_system_init(void) save_omap_boot_params(); #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD spl_early_init(); #endif @@ -497,7 +497,7 @@ void early_system_init(void) #endif } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { hw_data_init(); @@ -526,7 +526,7 @@ EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init); #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { - if (u_boot_first_phase()) { + if (xpl_is_first_phase()) { hw_data_init(); set_uart_mux_conf(); setup_early_clocks(); diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 649bc07047a..ddd7eeaf052 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -173,7 +173,7 @@ void save_omap_boot_params(void) #endif } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 spl_boot_device(void) { return gd->arch.omap_boot_device; @@ -208,7 +208,7 @@ void spl_boot_ipu(void) int ret, size; u32 loadaddr = IPU1_LOAD_ADDR; - if (!IS_ENABLED(CONFIG_SPL_BUILD) || + if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) return; @@ -286,7 +286,7 @@ void spl_soc_init(void) #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) hw_watchdog_init(); #endif - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) spl_boot_ipu(); } diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 18d099145c5..f05b16797ec 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -24,7 +24,7 @@ #include <asm/omap_gpio.h> #include <asm/emif.h> -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * printing to console doesn't work unless * this code is executed from SPL diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk index 30d8fb1b1d9..02b26733ee6 100644 --- a/arch/arm/mach-omap2/config.mk +++ b/arch/arm/mach-omap2/config.mk @@ -5,7 +5,7 @@ include $(srctree)/arch/arm/mach-omap2/config_secure.mk -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifeq ($(CONFIG_TI_SECURE_DEVICE),y) # Refer to README.ti-secure for more info # On DRA7xx/AM57xx: # diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index 40db1aec142..62ac27dfa90 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -4,7 +4,7 @@ quiet_cmd_mkomapsecimg = SECURE $@ ifneq ($(TI_SECURE_DEV_PKG),) ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),) -ifneq ($(CONFIG_SPL_BUILD),) +ifneq ($(CONFIG_XPL_BUILD),) cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_SPL_TEXT_BASE) \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index bb67e50fd56..b1e486a99d9 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -113,7 +113,7 @@ static void omap_rev_string(void) puts("\n"); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_display_print(void) { omap_rev_string(); @@ -175,7 +175,7 @@ void __weak init_package_revision(void) */ int early_system_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) int ret; int rescan; #endif @@ -183,19 +183,19 @@ int early_system_init(void) hw_data_init(); init_package_revision(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD if (warm_reset()) force_emif_self_refresh(); #endif watchdog_init(); set_mux_conf_regs(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD srcomp_enable(); do_io_settings(); #endif setup_early_clocks(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, @@ -206,7 +206,7 @@ int early_system_init(void) #endif do_board_detect(); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) /* * Board detection has been done. * Let us see if another dtb wouldn't be a better match @@ -228,7 +228,7 @@ int early_system_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { early_system_init(); diff --git a/arch/arm/mach-omap2/omap3/Makefile b/arch/arm/mach-omap2/omap3/Makefile index 151bdf6ebc9..159633e7f6d 100644 --- a/arch/arm/mach-omap2/omap3/Makefile +++ b/arch/arm/mach-omap2/omap3/Makefile @@ -15,7 +15,7 @@ obj-y += clock.o obj-y += sys_info.o obj-y += prcm-regs.o obj-y += hw_data.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o endif diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 1de343ff48e..4b6ce6940a9 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -211,7 +211,7 @@ void s_init(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { early_system_init(); @@ -280,7 +280,7 @@ void abort(void) { } -#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_XPL_BUILD) /****************************************************************************** * OMAP3 specific command to switch between NAND HW and SW ecc *****************************************************************************/ @@ -331,7 +331,7 @@ U_BOOT_CMD( "nandecc sw - Switch to NAND software ecc algorithm." ); -#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ +#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_XPL_BUILD */ #ifdef CONFIG_DISPLAY_BOARDINFO /** diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 404333689f6..24fae484369 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -146,7 +146,7 @@ static void do_sdrc_init(u32 cs, u32 early) * then set cs_cfg to the appropriate value then try and * setup CS1. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* set/modify board-specific timings */ get_board_mem_timings(&timings); #endif @@ -166,7 +166,7 @@ static void do_sdrc_init(u32 cs, u32 early) writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD write_sdrc_timings(CS0, sdrc_actim_base0, &timings); make_cs1_contiguous(); write_sdrc_timings(CS1, sdrc_actim_base1, &timings); diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 7f41e85c4a6..42f9c63fe12 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -50,7 +50,7 @@ void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) writel(pad->val, base + pad->offset); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* LPDDR2 specific IO settings */ static void io_settings_lpddr2(void) { diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 16bbc93f4a3..b1d11a4d1a4 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -178,7 +178,7 @@ auth_exit: * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index a8b87f6d710..3c381dedaf8 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -11,13 +11,13 @@ obj-y = cpu.o obj-y += dram.o obj-y += timer.o -ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT +ifndef CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index 58ee67eca50..4eba69a6909 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -235,7 +235,7 @@ int arch_cpu_init(void) /* Enable and invalidate L2 cache in write through mode */ invalidate_l2_cache(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD orion5x_config_adr_windows(); #endif diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index aa3fcf7c301..358d2a49fbb 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -69,7 +69,7 @@ lowlevel_init: -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Use 'r2 as the base for internal register accesses */ ldr r2, =ORION5X_REGS_PHY_BASE @@ -280,7 +280,7 @@ lowlevel_init: ldr r0, =0x7fff0001 str r0, [r3, #0x504] -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* Return to U-Boot via saved link register */ mov pc, lr diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index 1d8c3eea99c..fe88a2e0373 100644 --- a/arch/arm/mach-renesas/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h @@ -9,7 +9,7 @@ _start: ARM_VECTORS -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .word 0x0badc0d3; .word 0x0badc0d3; .word 0x0badc0d3; diff --git a/arch/arm/mach-renesas/lowlevel_init_ca15.S b/arch/arm/mach-renesas/lowlevel_init_ca15.S index 059cd738785..ecefa3d5c43 100644 --- a/arch/arm/mach-renesas/lowlevel_init_ca15.S +++ b/arch/arm/mach-renesas/lowlevel_init_ca15.S @@ -11,7 +11,7 @@ #include <system-constants.h> ENTRY(lowlevel_init) -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD mrc p15, 0, r4, c0, c0, 5 /* mpidr */ orr r4, r4, r4, lsr #6 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 3b13891ec24..5e7edc99cdc 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -15,7 +15,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) # Always include boot_mode.o, as we bypass it (i.e. turn it off) # inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way, @@ -29,7 +29,7 @@ ifeq ($(CONFIG_TPL_BUILD),) obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o endif -obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o +obj-$(CONFIG_$(PHASE_)RAM) += sdram.o obj-$(CONFIG_ROCKCHIP_PX30) += px30/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ @@ -51,5 +51,5 @@ obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/ obj-spl-$(CONFIG_TPL_BUILD) = # Now add SPL/TPL objects back into the main build -obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y) +obj-$(CONFIG_XPL_BUILD) += $(obj-spl-y) obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y) diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8b1509e55f2..8ce9ac561f0 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -244,7 +244,7 @@ int arch_cpu_init(void) static struct px30_cru * const cru = (void *)CRU_BASE; u32 __maybe_unused val; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* We do some SoC one time setting here. */ /* Disable the ddr secure region setting to make it non-secure */ writel(0x0, DDR_FW_BASE + FW_DDR_CON); diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 299fc50635d..038180c275c 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -6,7 +6,7 @@ obj-y += clk_rk3036.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += syscon_rk3036.o endif diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 70b55ca8abf..b8c177a4d0d 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -27,7 +27,7 @@ void board_debug_uart_init(void) void spl_board_init(void) { - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) return; if (IS_ENABLED(CONFIG_SPL_DM_MMC)) { diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 53b2eaa2d53..7cce1112fbd 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -51,7 +51,7 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int arch_cpu_init(void) { struct rk3188_grf *grf; @@ -106,7 +106,7 @@ int rk_board_late_init(void) return rk3188_board_late_init(); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static int setup_led(void) { #ifdef CONFIG_SPL_LED diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index 712c0524266..e35ca7778e7 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -51,7 +51,7 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SGRF_BASE 0x10150000 static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE; diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index d1170f7e23d..62dd9da6578 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -31,7 +31,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void configure_l2ctlr(void) { u32 l2ctlr; @@ -72,7 +72,7 @@ int rk3288_qos_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD configure_l2ctlr(); #else /* We do some SoC one time setting here. */ diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 6f88638d156..c6b1a35f47e 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -185,7 +185,7 @@ __weak void board_debug_uart_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) int arch_cpu_init(void) { static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE; diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index c86d11943d6..12ad17d9e8b 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -62,7 +62,7 @@ struct mm_region *mem_map = rk3328_mem_map; int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 reg; /* We do some SoC one time setting here. */ diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index f589bf67328..97b9500da25 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -93,7 +93,7 @@ int arch_early_init_r(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * The SPL (and also the full U-Boot stage on the RK3368) will run in * secure mode (i.e. EL3) and an ATF will eventually be booted before diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 2d7d0f82a2f..edccb2a3980 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -51,7 +51,7 @@ static struct mm_region rk3399_mem_map[] = { struct mm_region *mem_map = rk3399_mem_map; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define TIMER_END_COUNT_L 0x00 #define TIMER_END_COUNT_H 0x04 @@ -83,7 +83,7 @@ void rockchip_stimer_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct rk3399_pmusgrf_regs *sgrf; struct rk3399_grf_regs *grf; @@ -136,7 +136,7 @@ void board_debug_uart_init(void) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { rk_setreg(&grf->io_vsel, 1 << 0); @@ -169,7 +169,7 @@ void board_debug_uart_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) static void rk3399_force_power_on_reset(void) { ofnode node; diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 1b3e40074e3..768a3739329 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -105,7 +105,7 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * When perform idle operation, corresponding clock can * be opened or gated automatically. diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index d3162d3447e..e2dac2a5b80 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -111,7 +111,7 @@ void board_debug_uart_init(void) GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void rockchip_stimer_init(void) { /* If Timer already enabled, don't re-init it */ @@ -130,7 +130,7 @@ void rockchip_stimer_init(void) #ifndef CONFIG_TPL_BUILD int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE; #endif diff --git a/arch/arm/mach-rockchip/rv1108/Makefile b/arch/arm/mach-rockchip/rv1108/Makefile index 9035a1a8923..283fc966e7b 100644 --- a/arch/arm/mach-rockchip/rv1108/Makefile +++ b/arch/arm/mach-rockchip/rv1108/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += syscon_rv1108.o endif obj-y += rv1108.o diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index 1c10e9b9f23..27ed5dc19e1 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -66,7 +66,7 @@ int arch_cpu_init(void) * since they are unsecure. * (Note: only secure-world can access this register) */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG); return 0; diff --git a/arch/arm/mach-sc5xx/Makefile b/arch/arm/mach-sc5xx/Makefile index cac768ba565..47b28200a03 100644 --- a/arch/arm/mach-sc5xx/Makefile +++ b/arch/arm/mach-sc5xx/Makefile @@ -19,5 +19,5 @@ obj-$(CONFIG_SC59X) += sc59x-spl.o obj-$(CONFIG_SC59X_64) += sc59x_64.o obj-$(CONFIG_SC59X_64) += sc59x_64-spl.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_SYSCON) += rcu.o diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk index 580964e559c..e7e4c9a1181 100644 --- a/arch/arm/mach-sc5xx/config.mk +++ b/arch/arm/mach-sc5xx/config.mk @@ -8,7 +8,7 @@ # Contact: Greg Malysa <greg.malysa@timesys.com> # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD INPUTS-y += $(obj)/u-boot-spl.ldr endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec5..5fc61b4a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -80,7 +80,7 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o obj-y += freeze_controller.o diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index feaf5ce4596..24a15f7903f 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -102,7 +102,7 @@ u8 socfpga_get_board_id(void) u32 jtag_usercode; int err; -#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) +#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) err = smc_get_usercode(&jtag_usercode); #else u32 resp_len = 1; @@ -130,7 +130,7 @@ u8 socfpga_get_board_id(void) return board_id; } -#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) int board_fit_config_name_match(const char *name) { char board_name[10]; @@ -154,7 +154,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, } #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT) +#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_FIT) void board_prep_linux(struct bootm_headers *images) { bool use_fit = false; diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 160f6e73ca9..134eaf08e0a 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -99,7 +99,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 58b9321131a..5674194f4d1 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -12,7 +12,7 @@ #include <asm/arch/clock_manager.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void sdelay(unsigned long loops); u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h index c78def5066e..2676d6c8283 100644 --- a/arch/arm/mach-socfpga/include/mach/boot0.h +++ b/arch/arm/mach-socfpga/include/mach/boot0.h @@ -9,7 +9,7 @@ _start: ARM_VECTORS -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .balignl 64,0xf33db33f; .word 0x1337c0d3; /* SoCFPGA preloader validation word */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h index 553ebe660de..80d5047b469 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -62,7 +62,7 @@ #define CLKMGR_INTER CLKMGR_A10_INTER #define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int cm_basic_init(const void *blob); #endif diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 875927cc4d9..8926c2d1d9c 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -13,7 +13,7 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 4c86f1e9917..2b4f26040fe 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -400,7 +400,7 @@ error: int mbox_reset_cold(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) psci_system_reset(); #else int ret; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 495ba2a0d41..46f9c82bbb2 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -180,7 +180,7 @@ int arch_cpu_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 34c21317894..c442af02888 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -58,7 +58,7 @@ static Altera_desc altera_fpga[] = { }, }; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) static struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index b898b6f8f22..b136691c685 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -213,7 +213,7 @@ int arch_early_init_r(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index dd0383c7c76..a634c11a028 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -58,7 +58,7 @@ void socfpga_per_reset_all(void) void socfpga_bridges_reset(int enable) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) u64 arg = enable; int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index 4347bf6e792..e931f1043b3 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -120,7 +120,7 @@ int socfpga_vendor_authentication(void **p_image, size_t *p_size) debug("mbox_relocate_data_addr = 0x%p\n", mbox_relocate_data_addr); do { - if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { /* Invoke SMC call to ATF to send the VAB certificate to SDM */ ret = smc_send_mailbox(MBOX_VAB_SRC_CERT, mbox_data_sz, (u32 *)mbox_relocate_data_addr, 0, &resp_len, diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 80933586319..1a4e7c0e7e2 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -14,7 +14,7 @@ */ int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int enable = 0x3; /* timer enable + output signal masked */ int loadval = ~0; @@ -56,4 +56,4 @@ __always_inline void __udelay(unsigned long usec) while (__get_time_stamp() < tmp + 1) /* loop till event */ ; -}
\ No newline at end of file +} diff --git a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c index f13581033e6..60ba557d390 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c @@ -11,7 +11,7 @@ const struct cm_config * const cm_get_default_config(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct cm_config *cm_handoff_cfg = (struct cm_config *) (SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA); u32 *conversion = (u32 *)cm_handoff_cfg; @@ -32,7 +32,7 @@ const struct cm_config * const cm_get_default_config(void) const unsigned int cm_get_osc_clk_hz(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC); @@ -50,7 +50,7 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA); writel(clock, diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index ee8a5428feb..db7ed19bd91 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_STM32MP13X) += stm32mp1/ obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cmd_stm32prog/ obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o obj-$(CONFIG_TFABOOT) += boot_params.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 9ba7a6c9a89..9cbe6a52623 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -409,7 +409,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) u32 tmp_data = 0; int ret; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_OTP, otp, 0, val); @@ -440,7 +440,7 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_SHADOW, otp, 0, val); @@ -469,7 +469,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_PROG_OTP, otp, val); @@ -484,7 +484,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRITE_SHADOW, otp, val); @@ -504,7 +504,7 @@ static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) return 0; /* nothing to do */ } - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRLOCK_OTP, otp, 0); @@ -762,7 +762,7 @@ static int stm32mp_bsec_probe(struct udevice *dev) * update unlocked shadow for OTP cleared by the rom code * only executed in SPL, it is done in TF-A for TFABOOT */ - if (IS_ENABLED(CONFIG_SPL_BUILD) && !data->ta) { + if (IS_ENABLED(CONFIG_XPL_BUILD) && !data->ta) { plat = dev_get_plat(dev); /* here 57 is the value for STM32MP15x ROM code, only MPU with SPL support*/ diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index ebae50f66c9..db160c24cbc 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -8,12 +8,12 @@ obj-y += cpu.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += tzc400.o else obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_$(XPL_)STM32MP15_PWR) += pwr_regulator.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 64480da9f8d..26c073f06a0 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -57,7 +57,7 @@ void dram_bank_mmu_setup(int bank) bool use_lmb = false; enum dcache_option option; - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* STM32_SYSRAM_BASE exist only when SPL is supported */ #ifdef CONFIG_SPL start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); @@ -133,7 +133,7 @@ int mach_cpu_init(void) if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; - else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) + else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD)) debug_uart_init(); return 0; @@ -339,7 +339,7 @@ uintptr_t get_stm32mp_bl2_dtb(void) return nt_fw_dtb; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index ca202bec8ee..4f1d783649b 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -214,13 +214,13 @@ static void update_bootmode(void) /* weak function: STM32MP15x mach init for boot without TFA */ void stm32mp_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { security_init(); update_bootmode(); } /* reset copro state in SPL, when used, or in U-Boot */ - if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_XPL_BUILD)) { /* Reset Coprocessor state unless it wakes up from Standby power mode */ if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 17666814c52..8065161e61e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -108,6 +108,23 @@ config DRAM_SUN50I_H616_TPR12 default 0x0 help TPR12 value from vendor DRAM settings. + +choice + prompt "H616 PHY pin mapping selection" + default DRAM_SUN50I_H616_PHY_ADDR_MAP_0 + +config DRAM_SUN50I_H616_PHY_ADDR_MAP_0 + bool "H313/H616/H618" + help + The pin mapping selection used by the H313, H616, H618, and + possibly other dies which use the H616 DRAM controller. + +config DRAM_SUN50I_H616_PHY_ADDR_MAP_1 + bool "H700" + help + The pin mapping selection used by the H700 and possibly other + dies which use the H616 DRAM controller. +endchoice endif config SUN6I_PRCM @@ -437,6 +454,7 @@ config MACH_SUN50I_H616 select ARM64 select DRAM_SUN50I_H616 select SUN50I_GEN_H6 + imply OF_UPSTREAM endchoice diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 3f83c0280ef..eb6a49119a1 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -29,7 +29,7 @@ ifndef CONFIG_ARM64 obj-y += timer.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += clock.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 2b64ddc0dc7..701899ee4b2 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -74,7 +74,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) } #endif /* CONFIG_ARM64 */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static int gpio_init(void) { __maybe_unused uint val; @@ -209,7 +209,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image, return 0; } SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define SUNXI_INVALID_BOOT_SOURCE -1 @@ -258,7 +258,7 @@ static int sunxi_get_boot_source(void) * proper, just return MMC0 as a placeholder, for now. */ if (IS_ENABLED(CONFIG_MACH_SUNIV) && - !IS_ENABLED(CONFIG_SPL_BUILD)) + !IS_ENABLED(CONFIG_XPL_BUILD)) return SUNXI_BOOTED_FROM_MMC0; if (IS_ENABLED(CONFIG_MACH_SUNIV)) @@ -314,7 +314,7 @@ uint32_t sunxi_get_boot_device(void) return -1; /* Never reached */ } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD uint32_t sunxi_get_spl_size(void) { struct boot_file_head *egon_head = (void *)SPL_ADDR; @@ -478,7 +478,7 @@ void board_init_f(ulong dummy) #endif sunxi_board_init(); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 6458d066f7e..1367b439b83 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -13,7 +13,7 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -175,7 +175,7 @@ void clock_set_pll1(unsigned int hz) &ccm->cpu_ahb_apb0_cfg); sdelay(20); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index cc2ee336416..b424a7893ea 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -3,7 +3,7 @@ #include <asm/arch/clock.h> #include <asm/arch/prcm.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = @@ -131,7 +131,7 @@ int clock_twi_onoff(int port, int state) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* PLL_PERIPH0 clock, used by the MMC driver */ unsigned int clock_get_pll6(void) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 59f7e15ffe8..657736c7ac2 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -16,7 +16,7 @@ #include <linux/bitops.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -169,7 +169,7 @@ void clock_set_pll1(unsigned int clk) &ccm->cpu_axi_cfg); } } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index c00d16a918d..f593749028c 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -15,7 +15,7 @@ #include <asm/arch/sys_proto.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -100,7 +100,7 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ void clock_set_pll5(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index abdab405445..5f99071f21b 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -14,7 +14,7 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void clock_set_pll2(unsigned int clk) { @@ -188,7 +188,7 @@ int clock_twi_onoff(int port, int state) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* PLL_PERIPH0 clock (used by the MMC driver) */ unsigned int clock_get_pll4_periph0(void) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 37c139e0eea..863c4f1d7a8 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -55,8 +55,8 @@ static void mbus_configure_port(u8 port, writel_relaxed(cfg1, &mctl_com->master[port].cfg1); } -#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \ - mbus_configure_port(port, bwlimit, false, \ +#define MBUS_CONF(port, priority, qos, acs, bwl0, bwl1, bwl2) \ + mbus_configure_port(port, true, priority, \ MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2) static void mctl_set_master_priority(void) @@ -68,24 +68,25 @@ static void mctl_set_master_priority(void) writel(399, &mctl_com->tmr); writel(BIT(16), &mctl_com->bwcr); - MBUS_CONF( 0, true, HIGHEST, 0, 256, 128, 100); - MBUS_CONF( 1, true, HIGH, 0, 1536, 1400, 256); - MBUS_CONF( 2, true, HIGHEST, 0, 512, 256, 96); - MBUS_CONF( 3, true, HIGH, 0, 256, 100, 80); - MBUS_CONF( 4, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF( 5, true, HIGH, 2, 100, 64, 32); - MBUS_CONF( 6, true, HIGH, 2, 100, 64, 32); - MBUS_CONF( 8, true, HIGH, 0, 256, 128, 64); - MBUS_CONF(11, true, HIGH, 0, 256, 128, 100); - MBUS_CONF(14, true, HIGH, 0, 1024, 256, 64); - MBUS_CONF(16, true, HIGHEST, 6, 8192, 2800, 2400); - MBUS_CONF(21, true, HIGHEST, 6, 2048, 768, 512); - MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32); - MBUS_CONF(26, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF(37, true, HIGH, 0, 256, 128, 64); - MBUS_CONF(38, true, HIGH, 2, 100, 64, 32); - MBUS_CONF(39, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF(40, true, HIGH, 2, 100, 64, 32); + MBUS_CONF(0, false, HIGHEST, 0, 256, 128, 100); + MBUS_CONF(1, false, HIGH, 0, 1536, 1400, 256); + MBUS_CONF(2, false, HIGHEST, 0, 512, 256, 96); + MBUS_CONF(3, false, HIGH, 0, 256, 100, 80); + MBUS_CONF(4, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(5, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(6, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(8, false, HIGH, 0, 256, 128, 64); + MBUS_CONF(11, false, HIGH, 0, 256, 128, 100); + MBUS_CONF(14, false, HIGH, 0, 1024, 256, 64); + MBUS_CONF(16, false, HIGHEST, 6, 8192, 2800, 2400); + MBUS_CONF(21, false, HIGHEST, 6, 2048, 768, 512); + MBUS_CONF(22, false, HIGH, 0, 256, 128, 100); + MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32); + MBUS_CONF(26, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(37, false, HIGH, 0, 256, 128, 64); + MBUS_CONF(38, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(39, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(40, false, HIGH, 2, 100, 64, 32); dmb(); } @@ -225,6 +226,26 @@ static void mctl_set_addrmap(const struct dram_config *config) mctl_ctl->addrmap[8] = 0x3F3F; } +#ifdef CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1 +static const u8 phy_init[] = { +#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 + 0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b, + 0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a, + 0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19, + 0x06, 0x09, 0x0f +#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3) + 0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19, + 0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07, + 0x08, 0x01, 0x1a +#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4) + 0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01, + 0x18, 0x04, 0x1a +#endif +}; +#else /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */ static const u8 phy_init[] = { #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19, @@ -243,7 +264,7 @@ static const u8 phy_init[] = { 0x18, 0x03, 0x1a #endif }; - +#endif /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */ #define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f) static void mctl_phy_configure_odt(const struct dram_para *para) { @@ -293,14 +314,22 @@ static void mctl_phy_configure_odt(const struct dram_para *para) dmb(); } -static bool mctl_phy_write_leveling(const struct dram_config *config) +static bool mctl_phy_write_leveling(const struct dram_para *para, + const struct dram_config *config) { bool result = true; u32 val; clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0, 0x80); - writel(4, SUNXI_DRAM_PHY0_BASE + 0xc); - writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + /* MR2 value */ + writel(0x1b, SUNXI_DRAM_PHY0_BASE + 0xc); + writel(0, SUNXI_DRAM_PHY0_BASE + 0x10); + } else { + writel(4, SUNXI_DRAM_PHY0_BASE + 0xc); + writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10); + } setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4); @@ -859,9 +888,9 @@ static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para, } break; case SUNXI_DRAM_TYPE_LPDDR4: - if (para->tpr2 & 1) { - writel(val, SUNXI_DRAM_PHY0_BASE + 0x788); - } else { + writel(val, SUNXI_DRAM_PHY0_BASE + 0x788); + if (config->ranks == 2) { + val = (para->tpr10 >> 11) & 0x1e; writel(val, SUNXI_DRAM_PHY0_BASE + 0x794); }; break; @@ -986,12 +1015,16 @@ static bool mctl_phy_init(const struct dram_para *para, clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0, 0x20); } + clrbits_le32(&mctl_com->unk_0x500, 0x200); + udelay(1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8); mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4); + udelay(1000); + writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58); - clrbits_le32(&mctl_com->unk_0x500, 0x200); writel(0, &mctl_ctl->swctl); setbits_le32(&mctl_ctl->dfimisc, 1); @@ -1010,6 +1043,8 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->swstat, 1, 1); mctl_await_completion(&mctl_ctl->statr, 3, 1); + udelay(200); + writel(0, &mctl_ctl->swctl); clrbits_le32(&mctl_ctl->dfimisc, 1); @@ -1080,19 +1115,27 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xb04, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xc72, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xe09, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0x1624, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); break; case SUNXI_DRAM_TYPE_DDR4: @@ -1108,7 +1151,7 @@ static bool mctl_phy_init(const struct dram_para *para, if (para->tpr10 & TPR10_WRITE_LEVELING) { for (i = 0; i < 5; i++) - if (mctl_phy_write_leveling(config)) + if (mctl_phy_write_leveling(para, config)) break; if (i == 5) { debug("write leveling failed!\n"); @@ -1234,9 +1277,6 @@ static bool mctl_ctrl_init(const struct dram_para *para, setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30)); setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30)); - if (para->type == SUNXI_DRAM_TYPE_LPDDR4) - setbits_le32(&mctl_ctl->dbictl, 0x1); - setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); @@ -1248,8 +1288,10 @@ static bool mctl_ctrl_init(const struct dram_para *para, setbits_le32(&mctl_ctl->clken, BIT(8)); clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x300); + udelay(1); /* this write seems to enable PHY MMIO region */ setbits_le32(&mctl_com->unk_0x500, BIT(24)); + udelay(1); if (!mctl_phy_init(para, config)) return false; @@ -1321,28 +1363,33 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para, static void mctl_auto_detect_dram_size(const struct dram_para *para, struct dram_config *config) { - /* detect row address bits */ - config->cols = 8; - config->rows = 18; + unsigned int shift; + + /* max. config for columns, but not rows */ + config->cols = 11; + config->rows = 13; mctl_core_init(para, config); - for (config->rows = 13; config->rows < 18; config->rows++) { - /* 8 banks, 8 bit per byte and 16/32 bit width */ - if (mctl_mem_matches((1 << (config->rows + config->cols + - 4 + config->bus_full_width)))) + shift = config->bus_full_width + 1; + + /* detect column address bits */ + for (config->cols = 8; config->cols < 11; config->cols++) { + if (mctl_mem_matches(1ULL << (config->cols + shift))) break; } + debug("detected %u columns\n", config->cols); - /* detect column address bits */ - config->cols = 11; + /* reconfigure to make sure that all active rows are accessible */ + config->rows = 18; mctl_core_init(para, config); - for (config->cols = 8; config->cols < 11; config->cols++) { - /* 8 bits per byte and 16/32 bit width */ - if (mctl_mem_matches(1 << (config->cols + 1 + - config->bus_full_width))) + /* detect row address bits */ + shift = config->bus_full_width + 4 + config->cols; + for (config->rows = 13; config->rows < 18; config->rows++) { + if (mctl_mem_matches(1ULL << (config->rows + shift))) break; } + debug("detected %u rows\n", config->rows); } static unsigned long mctl_calc_size(const struct dram_config *config) diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c index e6446b9180d..6f5c4acbd62 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c @@ -23,7 +23,7 @@ void mctl_set_timing_params(const struct dram_para *para) u8 trcd = max(ns_to_t(18), 2); u8 trc = ns_to_t(65); u8 txp = max(ns_to_t(8), 2); - u8 trtp = max(ns_to_t(8), 4); + u8 trtp = 4; u8 trp = ns_to_t(21); u8 tras = ns_to_t(42); u16 trefi = ns_to_t(3904) / 32; diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c index a058fea6bef..aa93defb25e 100644 --- a/arch/arm/mach-sunxi/gtbus_sun9i.c +++ b/arch/arm/mach-sunxi/gtbus_sun9i.c @@ -11,7 +11,7 @@ #include <asm/arch/gtbus_sun9i.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void gtbus_init(void) { diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 1d22dc3942f..ebac3473a1f 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -5,7 +5,7 @@ # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += cpu.o else @@ -16,7 +16,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o -obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o +obj-$(CONFIG_$(XPL_)TEGRA_CRYPTO) += crypto.o obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o @@ -25,7 +25,7 @@ obj-y += dt-setup.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_IVC) += ivc.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 1ea620e4ab5..f35bdba4d48 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -32,7 +32,7 @@ int tegra_get_chip(void) * Tegra30, 0x35 for T114, and 0x40 for Tegra124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - debug("%s: CHIPID is 0x%02X\n", __func__, rev); + debug("%s: CHIPID is 0x%02x\n", __func__, rev); return rev; } @@ -43,7 +43,7 @@ int tegra_get_sku_info(void) struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; sku_id = readl(&fuse->sku_info) & 0xff; - debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); + debug("%s: SKU info byte is 0x%02x\n", __func__, sku_id); return sku_id; } @@ -58,8 +58,9 @@ int tegra_get_chip_sku(void) switch (chip_id) { case CHIPID_TEGRA20: switch (sku_id) { - case SKU_ID_T20_7: + case SKU_ID_AP20: case SKU_ID_T20: + case SKU_ID_AP20H: return TEGRA_SOC_T20; case SKU_ID_T25SE: case SKU_ID_AP25: @@ -103,8 +104,8 @@ int tegra_get_chip_sku(void) } /* unknown chip/sku id */ - printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", - __func__, chip_id, sku_id); + printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02x/0x%02x)\n", + __func__, chip_id, sku_id); return TEGRA_SOC_UNKNOWN; } diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index c382e042860..7ca56a3b081 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -47,7 +47,7 @@ enum { static bool from_spl __section(".data"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, unsigned long r3) { @@ -181,7 +181,7 @@ static int uart_configs[] = { -1, -1, -1, - -1, + FUNCMUX_UART5_SDMMC1, /* UARTE */ #elif defined(CONFIG_TEGRA114) -1, -1, diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 5c5838629b2..6e9ef68caf9 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -6,6 +6,7 @@ #include <config.h> #include <dm.h> +#include <dm/root.h> #include <env.h> #include <errno.h> #include <init.h> @@ -46,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ U_BOOT_DRVINFO(tegra_gpios) = { "gpio_tegra" @@ -457,3 +458,18 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } + +#if IS_ENABLED(CONFIG_DTB_RESELECT) +int embedded_dtb_select(void) +{ + int ret, rescan; + + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(true); + } + + return 0; +} +#endif diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index 346d6cb5696..f1c1042b4e2 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -2,6 +2,6 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -obj-$(CONFIG_SPL_BUILD) += cpu.o +obj-$(CONFIG_XPL_BUILD) += cpu.o obj-y += clock.o diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index fb016aa46c9..84c8f86bad0 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -21,8 +21,8 @@ config TARGET_CEI_TK1_SOM bool "Colorado Engineering Inc Tegra124 TK1-som board" select ARCH_SUPPORT_PSCI select BOARD_LATE_INIT - select CPU_V7_HAS_NONSEC if !SPL_BUILD - select CPU_V7_HAS_VIRT if !SPL_BUILD + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT help The Colorado Engineering Tegra TK1-SOM is a very compact (51mmx58mm) board that is functionally almost the same as diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index 6ea511e7b25..dee790015a3 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -5,13 +5,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SPL_BUILD) += cpu.o +obj-$(CONFIG_XPL_BUILD) += cpu.o obj-y += clock.o obj-y += pmc.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_NONSEC) += psci.o endif diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index c2ae98eb376..32c1866b099 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -2,8 +2,8 @@ # # (C) Copyright 2010,2011 Nvidia Corporation. -obj-$(CONFIG_SPL_BUILD) += cpu.o -obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o +obj-$(CONFIG_XPL_BUILD) += cpu.o +obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index ee0e6f5b948..b36657a432f 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -2,7 +2,7 @@ # # Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -obj-$(CONFIG_SPL_BUILD) += cpu.o -obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o +obj-$(CONFIG_XPL_BUILD) += cpu.o +obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o obj-y += clock.o diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5172efac0c4..d1ec8195dcb 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += boards.o obj-y += spl_board_init.o diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile index b41aba7e29a..c8ce67ac05a 100644 --- a/arch/arm/mach-uniphier/arm32/Makefile +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += lowlevel_init.o obj-$(CONFIG_DEBUG_LL) += debug_ll.o else diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 1e6bc8433f7..9d0fe5c8583 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -214,7 +214,7 @@ int uniphier_boot_from_backend(void) return !!(readl(sg_base + SG_PINMON0) & BIT(27)); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_pinmon(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -267,4 +267,4 @@ U_BOOT_CMD( "" ); -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index c49e44754c0..0e47beb5f22 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile b/arch/arm/mach-uniphier/debug-uart/Makefile index 81e9314a50d..4202cb3503b 100644 --- a/arch/arm/mach-uniphier/debug-uart/Makefile +++ b/arch/arm/mach-uniphier/debug-uart/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index 1ba012ca45d..6836eb63bfa 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -26,7 +26,7 @@ static void _debug_uart_putc(int c) writel(c, base + UNIPHIER_UART_TX); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void sg_set_pinsel(unsigned int pin, unsigned int muxval, unsigned int mux_bits, unsigned int reg_stride) { @@ -56,7 +56,7 @@ void sg_set_iectrl(unsigned int pin) void _debug_uart_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); unsigned int divisor; diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 7d11315d07f..36188c38cf9 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \ ddrphy-training.o ddrphy-ld4.o diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index d9b2b999e10..8545331c54a 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -12,4 +12,4 @@ obj-y += slcr.o obj-y += clk.o obj-y += lowlevel_init.o AFLAGS_lowlevel_init.o := -mfpu=neon -obj-$(CONFIG_SPL_BUILD) += spl.o ps7_spl_init.o +obj-$(CONFIG_XPL_BUILD) += spl.o ps7_spl_init.o diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 5b6d765099d..74dddc25988 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -52,7 +52,7 @@ static const struct { int arch_cpu_init(void) { zynq_slcr_unlock(); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 38be1627eeb..ff426044797 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -5,10 +5,10 @@ obj-y += aes.o clk.o cpu.o obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o +obj-$(CONFIG_XPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o -obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o +obj-$(CONFIG_$(XPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o -endif # !CONFIG_SPL_BUILD +endif # !CONFIG_XPL_BUILD diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 07668c94689..24fd5751216 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -187,7 +187,7 @@ int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) { - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) return zynqmp_mmio_rawwrite(address, mask, value); #if defined(CONFIG_ZYNQMP_FIRMWARE) else @@ -205,7 +205,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value) if (!value) return ret; - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { ret = zynqmp_mmio_rawread(address, value); } #if defined(CONFIG_ZYNQMP_FIRMWARE) diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 64c3f313195..53244046f19 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -11,7 +11,7 @@ PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections LDFLAGS_FINAL += --gc-sections -ifeq ($(CONFIG_SPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC LDFLAGS_u-boot += -pic endif diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index b8c1dcbe14f..4d4919c3e3f 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -7,4 +7,4 @@ extra-y = start.o obj-y = irq.o obj-y += interrupts.o cache.o exception.o cpuinfo.o relocate.o obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index c1e0fcda0a4..69c4efdad7f 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -26,7 +26,7 @@ _start: mts rslr, r0 mts rshr, r20 -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) addi r1, r0, CONFIG_SPL_STACK #else add r1, r0, r20 @@ -83,7 +83,7 @@ uboot_sym_start: brlid r15, board_init_f_init_reserve nop -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /* Setup vectors with pre-relocation symbols */ or r5, r0, r0 brlid r15, __setup_exceptions @@ -122,7 +122,7 @@ clear_bss: brlid r15, debug_uart_init nop #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD or r5, r0, r0 /* flags - empty */ bri board_init_f #else @@ -130,7 +130,7 @@ clear_bss: #endif 1: bri 1b -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD .text .ent __setup_exceptions .align 2 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a007914590f..453c7885075 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -2,7 +2,7 @@ head-y := arch/mips/cpu/start.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) head-$(CONFIG_ARCH_JZ47XX) := arch/mips/mach-jz47xx/start.o head-$(CONFIG_SOC_MT7621) := arch/mips/mach-mtmips/mt7621/spl/start.o endif diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 745f03190e9..ad2ea11f72c 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -53,7 +53,7 @@ PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS) # LDFLAGS_vmlinux += -G 0 -static -n -nostdlib # MODFLAGS += -mlong-calls # -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD OBJCOPYFLAGS += -j .data.reloc -j .dtb.init.rodata LDFLAGS_FINAL += --emit-relocs endif diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 1621cc9a1ff..79841dbe5ed 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -12,6 +12,6 @@ obj-y += traps.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o diff --git a/arch/mips/mach-jz47xx/Makefile b/arch/mips/mach-jz47xx/Makefile index dbb8229f785..5621a09b6dd 100644 --- a/arch/mips/mach-jz47xx/Makefile +++ b/arch/mips/mach-jz47xx/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -extra-$(CONFIG_SPL_BUILD) := start.o +extra-$(CONFIG_XPL_BUILD) := start.o obj-$(CONFIG_SOC_JZ4780) += jz4780/ diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780.h b/arch/mips/mach-jz47xx/include/mach/jz4780.h index 880445dac39..9f9a8cf9438 100644 --- a/arch/mips/mach-jz47xx/include/mach/jz4780.h +++ b/arch/mips/mach-jz47xx/include/mach/jz4780.h @@ -94,7 +94,7 @@ void jz4780_efuse_init(u32 ahb2_rate); void jz4780_tcu_wdt_start(void); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int jz_mmc_init(void __iomem *base); #endif diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index 1d6fb6a4e27..504fd27d285 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -19,7 +19,7 @@ #include <mmc.h> #include <spl.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Pointer to the global data structure for SPL */ DECLARE_GLOBAL_DATA_PTR; gd_t gdata __section(".bss"); @@ -73,7 +73,7 @@ void board_init_f(ulong dummy) hang(); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { diff --git a/arch/mips/mach-jz47xx/start.S b/arch/mips/mach-jz47xx/start.S index 760d0215493..0d40e637a68 100644 --- a/arch/mips/mach-jz47xx/start.S +++ b/arch/mips/mach-jz47xx/start.S @@ -18,7 +18,7 @@ .globl _start .text _start: -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* magic value ("MSPL") */ .word 0x4d53504c @@ -95,4 +95,4 @@ enable_caches: .end enable_caches #endif /* CONFIG_SOC_JZ4780 */ -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/mips/mach-mtmips/Makefile b/arch/mips/mach-mtmips/Makefile index 19f1e07033e..2f35b1a925c 100644 --- a/arch/mips/mach-mtmips/Makefile +++ b/arch/mips/mach-mtmips/Makefile @@ -5,7 +5,7 @@ obj-y += cpu.o ifneq ($(CONFIG_SOC_MT7621),y) obj-y += ddr_init.o obj-y += ddr_cal.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o endif obj-$(CONFIG_SOC_MT7620) += mt7620/ diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c index 243938a0ebb..982a5889df8 100644 --- a/arch/mips/mach-mtmips/cpu.c +++ b/arch/mips/mach-mtmips/cpu.c @@ -21,7 +21,7 @@ int dram_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int last_stage_init(void) { void *src, *dst; diff --git a/arch/mips/mach-mtmips/mt7620/Makefile b/arch/mips/mach-mtmips/mt7620/Makefile index 649f6c3798f..d2d79e3424b 100644 --- a/arch/mips/mach-mtmips/mt7620/Makefile +++ b/arch/mips/mach-mtmips/mt7620/Makefile @@ -5,6 +5,6 @@ obj-y += init.o obj-y += dram.o obj-y += serial.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += sysc.o endif diff --git a/arch/mips/mach-mtmips/mt7621/Makefile b/arch/mips/mach-mtmips/mt7621/Makefile index bf1b0bb688b..f48083e3559 100644 --- a/arch/mips/mach-mtmips/mt7621/Makefile +++ b/arch/mips/mach-mtmips/mt7621/Makefile @@ -3,7 +3,7 @@ obj-y += init.o obj-y += serial.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) ifeq ($(CONFIG_TPL_BUILD),y) obj-y += tpl/ else diff --git a/arch/mips/mach-mtmips/mt7628/Makefile b/arch/mips/mach-mtmips/mt7628/Makefile index 7e139d5adfd..63acf54536b 100644 --- a/arch/mips/mach-mtmips/mt7628/Makefile +++ b/arch/mips/mach-mtmips/mt7628/Makefile @@ -3,4 +3,4 @@ obj-y += lowlevel_init.o obj-y += init.o obj-y += ddr.o -obj-$(CONFIG_SPL_BUILD) += serial.o +obj-$(CONFIG_XPL_BUILD) += serial.o diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 725a4f48aad..dd0124cace1 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -27,7 +27,7 @@ PLATFORM_CPPFLAGS+= -D__PPC__ endif # Only test once -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) archprepare: checkgcc4 # GCC 3.x is reported to have problems generating the type of relocation diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 1255f533e34..9974239f881 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -7,7 +7,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index ceb54867894..78762f000df 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -41,11 +41,11 @@ #endif #if defined(CONFIG_NAND_SPL) || \ - (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) + (defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) #define MINIMAL_SPL #endif -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ +#if !defined(CONFIG_XPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ !defined(CONFIG_SYS_RAMBOOT) #define CFG_SYS_FLASHBOOT #endif @@ -168,7 +168,7 @@ _start: /* time t 0 */ /* Initialise the E300 processor core */ /*------------------------------------------*/ -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ +#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ defined(CONFIG_NAND_SPL) /* The FCM begins execution after only the first page * is loaded. Wait for the rest before branching diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f3ee7d34949..bf74228efde 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -8,7 +8,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y @@ -26,7 +26,7 @@ else obj-$(CONFIG_MP) += release.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 574510fa088..75bfc07fe97 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -179,7 +179,7 @@ void cpu_init_early_f(void *fdt) invalidate_tlb(1); #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \ - !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \ + !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_XPL_BUILD)) && \ !defined(CONFIG_NAND_SPL) disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); #endif diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 3e24a90233c..89bce5bed69 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -28,7 +28,7 @@ #define LAW_EN 0x80000000 #if defined(CONFIG_NAND_SPL) || \ - (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) + (defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) #define MINIMAL_SPL #endif @@ -58,16 +58,16 @@ END_GOT #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) /* Maximal size of the image */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define MAX_IMAGE_SIZE (CONFIG_SPL_MAX_SIZE - (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512)) #else #define MAX_IMAGE_SIZE CONFIG_SYS_L2_SIZE #endif -#if defined(CONFIG_SPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 +#if defined(CONFIG_XPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 #error "CONFIG_SPL_MAX_SIZE is too small for CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA" #endif @@ -1138,10 +1138,10 @@ create_init_ram_area: /* * For Targets without CONFIG_SPL like P3, P5 * and for targets with CONFIG_SPL like T1, T2, T4, only for - * u-boot-spl i.e. CONFIG_SPL_BUILD + * u-boot-spl i.e. CONFIG_XPL_BUILD */ #elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \ - (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) /* create a temp mapping in AS = 1 for mapping CONFIG_VAL(SYS_MONITOR_BASE) * to L3 Address configured by PBL for ISBC code */ @@ -1617,7 +1617,7 @@ relocate_code: mr r10,r5 /* Save copy of Destination Address */ GET_GOT -#if !defined(CONFIG_SPL_SKIP_RELOCATE) || !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_SKIP_RELOCATE) || !defined(CONFIG_XPL_BUILD) mr r3,r5 /* Destination Address */ lis r4,CONFIG_VAL(SYS_MONITOR_BASE)@h /* Source Address */ ori r4,r4,CONFIG_VAL(SYS_MONITOR_BASE)@l diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 32b68a169a4..415ab1096c6 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -45,7 +45,7 @@ __weak void init_tlbs(void) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) + (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { @@ -313,7 +313,7 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, print_size(memsize > CFG_MAX_MEM_MAPPED ? memsize - CFG_MAX_MEM_MAPPED + size : size, " of DDR memory left unmapped in U-Boot\n"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD puts(" "); #endif } diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index e3a536d4f8c..a44b5165d74 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -4,7 +4,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 3a82e60a247..638c3a6fee5 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -241,7 +241,7 @@ int pamu_init(void) spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; /* Allocate space for Primary PAACT Table */ -#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR)) +#if (defined(CONFIG_XPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR)) ppaact = (void *)CFG_SPL_PPAACT_ADDR; #else ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); @@ -251,7 +251,7 @@ int pamu_init(void) memset(ppaact, 0, ppaact_size); /* Allocate space for Secondary PAACT Table */ -#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR)) +#if (defined(CONFIG_XPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR)) sec = (void *)CFG_SPL_SPAACT_ADDR; #else sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index b4695cc99cb..3fd80eb29c0 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -78,7 +78,7 @@ void disable_law(u8 idx) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) + (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) static int get_law_entry(u8 i, struct law_entry *e) { u32 lawar; @@ -109,7 +109,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) + (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 831a11736cc..bd3f69b469e 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -28,7 +28,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) i++; #endif -#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) +#if (defined(CONFIG_XPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) tbl->start_addr[i] = (uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR); tbl->size[i] = 256 * 1024; /* 256K CPC flash */ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 221f9d842a8..f12830984c6 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -36,7 +36,7 @@ #endif /* #ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_CHAIN_OF_TRUST -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init * due to space crunch on CPC and thus malloc will not work. @@ -45,10 +45,10 @@ #define CFG_SPL_SPAACT_ADDR 0x2f000000 #define CFG_SPL_JR0_LIODN_S 454 #define CFG_SPL_JR0_LIODN_NS 458 -#endif /* ifdef CONFIG_SPL_BUILD */ +#endif /* ifdef CONFIG_XPL_BUILD */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #include <config_fsl_chain_trust.h> -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif /* #ifndef CONFIG_XPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index ecc2aba8f3c..c0caa703caa 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -9,7 +9,7 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y @@ -45,6 +45,6 @@ obj-y += time.o obj-y += traps.o endif # not minimal -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_$(SPL_TPL)_FRAMEWORK) += spl.o +ifdef CONFIG_XPL_BUILD +obj-$(CONFIG_$(PHASE_)FRAMEWORK) += spl.o endif diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index c36a8533e0f..4e6f347038d 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -48,7 +48,7 @@ endif ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) -ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y) +ifeq ($(CONFIG_$(XPL_)FRAMEPOINTER),y) ARCH_FLAGS += -fno-omit-frame-pointer endif diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 043fb961a51..69759c55658 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2020 SiFive, Inc # Pragnesh Patel <pragnesh.patel@sifive.com> -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += spl.o else obj-y += dram.o diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile index 1d1ad98ba7c..9071c831992 100644 --- a/arch/riscv/cpu/fu740/Makefile +++ b/arch/riscv/cpu/fu740/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2020-2021 SiFive, Inc # Pragnesh Patel <pragnesh.patel@sifive.com> -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += spl.o else obj-y += dram.o diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile index 951c95631e9..0939c1061d0 100644 --- a/arch/riscv/cpu/jh7110/Makefile +++ b/arch/riscv/cpu/jh7110/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2022 StarFive Technology Co., Ltd. -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += spl.o else obj-y += cpu.o diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8e58f641f1b..3f78932aa9d 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -90,7 +90,7 @@ _start: * Set stackpointer in internal/ex RAM to call board_init_f */ call_board_init_f: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) li t0, CONFIG_SPL_STACK #else li t0, SYS_INIT_SP_ADDR @@ -218,7 +218,7 @@ wait_for_gd_init: la t5, board_init_f jalr t5 /* jump to board_init_f() */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD spl_clear_bss: la t0, __bss_start la t1, __bss_end @@ -271,7 +271,7 @@ spl_call_board_init_r: j board_init_r #endif -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /* * void relocate_code(addr_sp, gd, addr_moni) * @@ -420,7 +420,7 @@ call_board_init_r: * jump to it ... */ jr t4 /* jump to board_init_r() */ -#endif /* !defined(CONFIG_SPL_BUILD) */ +#endif /* !defined(CONFIG_XPL_BUILD) */ #if CONFIG_IS_ENABLED(SMP) hart_out_of_bounds_loop: diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 65dc49f6fa5..268116f3757 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -11,20 +11,20 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o -ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) -obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += aclint_ipi.o +ifeq ($(CONFIG_$(XPL_)RISCV_MMODE),y) +obj-$(CONFIG_$(XPL_)RISCV_ACLINT) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o -ifeq ($(CONFIG_$(SPL_)SYSRESET),) +ifeq ($(CONFIG_$(XPL_)SYSRESET),) obj-y += reset.o endif obj-y += setjmp.o -obj-$(CONFIG_$(SPL_)SMP) += smp.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_$(XPL_)SMP) += smp.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-y += fdt_fixup.o obj-$(CONFIG_$(SPL)CMD_BDI) += bdinfo.o @@ -36,15 +36,11 @@ CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI) CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI) CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI) -extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC) -extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC) -extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMMOVE) += memmove.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_STRLEN) += strlen_zbb.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_STRCMP) += strcmp_zbb.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_STRNCMP) += strncmp_zbb.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRLEN) += strlen_zbb.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRCMP) += strcmp_zbb.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRNCMP) += strncmp_zbb.o - -obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o +obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index d8fe1dfa958..d74544b93d8 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -10,7 +10,7 @@ #include <dm/device-internal.h> #include <dm/uclass-internal.h> -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD void enable_caches(void) { struct udevice *dev; @@ -45,4 +45,4 @@ void enable_caches(void) probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev); } -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 7c5c52652f5..bfcdc335d32 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -8,7 +8,7 @@ obj-y := cache.o cpu.o state.o extra-y := start.o os.o extra-$(CONFIG_SANDBOX_SDL) += sdl.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_ETH_SANDBOX_RAW) += eth-raw-os.o # os.c is build in the system environment, so needs standard includes diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 51ce40e7f08..06f8c13fab9 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -165,7 +165,7 @@ phys_addr_t virt_to_phys(void *ptr) void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { -#if defined(CONFIG_PCI) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_PCI) && !defined(CONFIG_XPL_BUILD) unsigned long plen = len; void *ptr; diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 1c33a520c64..c50df5f9179 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -27,8 +27,8 @@ int sandbox_find_next_phase(char *fname, int maxlen, bool use_img) const char *cur_prefix, *next_prefix; int ret; - cur_prefix = spl_phase_prefix(spl_phase()); - next_prefix = spl_phase_prefix(spl_next_phase()); + cur_prefix = xpl_prefix(xpl_phase()); + next_prefix = xpl_prefix(xpl_next_phase()); ret = os_find_u_boot(fname, maxlen, use_img, cur_prefix, next_prefix); if (ret) return log_msg_ret("find", ret); @@ -91,7 +91,7 @@ static int load_from_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { struct sandbox_state *state = state_get_current(); - enum u_boot_phase next_phase; + enum xpl_phase_t next_phase; const char *fname; ulong pos, size; int full_size; @@ -101,7 +101,7 @@ static int load_from_image(struct spl_image_info *spl_image, if (!IS_ENABLED(CONFIG_SANDBOX_VPL)) return -ENOENT; - next_phase = spl_next_phase(); + next_phase = xpl_next_phase(); pos = spl_get_image_pos(); size = spl_get_image_size(); if (pos == BINMAN_SYM_MISSING || size == BINMAN_SYM_MISSING) { diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 9ad5d46271a..81752edc9f8 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -129,7 +129,7 @@ static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg) } SANDBOX_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int sandbox_main_loop_init(void) { struct sandbox_state *state = state_get_current(); @@ -206,7 +206,7 @@ static int sandbox_cmdline_cb_test_fdt(struct sandbox_state *state, char *relname; int len; - if (spl_phase() <= PHASE_SPL) + if (xpl_phase() <= PHASE_SPL) relname = "../arch/sandbox/dts/test.dtb"; else relname = "arch/sandbox/dts/test.dtb"; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 8412506c17a..9bf44ae3b0b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -101,6 +101,11 @@ bootscr-ram-offset = /bits/ 64 <0x12345678>; bootscr-flash-offset = /bits/ 64 <0>; bootscr-flash-size = /bits/ 64 <0x2000>; + boot-led = "sandbox:green"; + activity-led = "sandbox:red"; + testing-bool; + testing-int = <123>; + testing-str = "testing"; }; }; diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index d3c480e79ed..99acc599965 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -33,8 +33,9 @@ static inline void cache_wback_all(void) } } -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 +#define CACHE_ENABLE 0 +#define CACHE_DISABLE 1 +#define CACHE_INVALIDATE 2 static int cache_control(unsigned int cmd) { @@ -46,7 +47,9 @@ static int cache_control(unsigned int cmd) if (ccr & CCR_CACHE_ENABLE) cache_wback_all(); - if (cmd == CACHE_DISABLE) + if (cmd == CACHE_INVALIDATE) + outl(CCR_CACHE_ICI | ccr, CCR); + else if (cmd == CACHE_DISABLE) outl(CCR_CACHE_STOP, CCR); else outl(CCR_CACHE_INIT, CCR); @@ -103,7 +106,7 @@ void icache_disable(void) void invalidate_icache_all(void) { - puts("No arch specific invalidate_icache_all available!\n"); + cache_control(CACHE_INVALIDATE); } int icache_status(void) diff --git a/arch/x86/Makefile b/arch/x86/Makefile index f1afc74fff8..fd409b9f720 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0+ ifeq ($(CONFIG_EFI_APP),) -ifdef CONFIG_$(SPL_)X86_64 +ifdef CONFIG_$(XPL_)X86_64 head-y := arch/x86/cpu/start64.o else -ifeq ($(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),y) +ifeq ($(CONFIG_$(PHASE_)X86_16BIT_INIT),y) head-y := arch/x86/cpu/start.o else ifndef CONFIG_SPL head-y := arch/x86/cpu/start.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD head-y = arch/x86/cpu/start_from_tpl.o else head-y = arch/x86/cpu/start_from_spl.o @@ -20,8 +20,8 @@ endif endif endif # EFI -head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o -head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o +head-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += arch/x86/cpu/start16.o +head-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o libs-y += arch/x86/cpu/ libs-y += arch/x86/lib/ diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 2e3a7119e79..6d4839dfb38 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -10,7 +10,7 @@ PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD IS_32BIT := y else ifndef CONFIG_X86_64 @@ -26,7 +26,7 @@ endif ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 else -PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -march=core2 -m64 +PLATFORM_CPPFLAGS += $(if $(CONFIG_XPL_BUILD),,-fpic) -fno-common -march=core2 -m64 ifndef CONFIG_X86_HARDFP PLATFORM_CPPFLAGS += -mno-mmx -mno-sse @@ -86,12 +86,12 @@ ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -mregparm=3 endif KBUILD_LDFLAGS += --emit-relocs -LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie) +LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_XPL_BUILD),,-pie) endif ifdef CONFIG_X86_64 -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD PLATFORM_CPPFLAGS += -D__x86_64__ else PLATFORM_CPPFLAGS += -D__I386__ diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 16e67e3da24..39c8b0835cc 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -6,16 +6,16 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -ifeq ($(CONFIG_$(SPL_)X86_64),y) +ifeq ($(CONFIG_$(XPL_)X86_64),y) extra-y = start64.o else -ifeq ($(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),y) +ifeq ($(CONFIG_$(PHASE_)X86_16BIT_INIT),y) extra-y = start.o else ifndef CONFIG_SPL extra-y = start.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD extra-y = start_from_tpl.o else extra-y = start_from_spl.o @@ -24,14 +24,14 @@ endif endif endif -extra-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += resetvec.o start16.o +extra-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += resetvec.o start16.o obj-y += cpu.o ifndef CONFIG_TPL_BUILD obj-y += cpu_x86.o endif -ifndef CONFIG_$(SPL_)X86_64 +ifndef CONFIG_$(XPL_)X86_64 AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) AFLAGS_call32.o := -fpic -fshort-wchar \ @@ -54,23 +54,23 @@ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o -obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o +obj-$(CONFIG_$(PHASE_)ACPI_GPE) += acpi_gpe.o obj-$(CONFIG_QFW) += qfw_cpu.o ifndef CONFIG_SYS_COREBOOT -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += irq.o endif -ifndef CONFIG_$(SPL_)X86_64 -obj-$(CONFIG_$(SPL_)SMP) += mp_init.o +ifndef CONFIG_$(XPL_)X86_64 +obj-$(CONFIG_$(XPL_)SMP) += mp_init.o endif obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o -ifndef CONFIG_$(SPL_)X86_64 +ifndef CONFIG_$(XPL_)X86_64 obj-$(CONFIG_SMP) += sipi_vector.o endif obj-y += turbo.o obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.o -ifeq ($(CONFIG_$(SPL_)X86_64),y) +ifeq ($(CONFIG_$(XPL_)X86_64),y) obj-y += x86_64/ else obj-y += i386/ diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 2ddf4af62c5..f481f40d9bb 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -2,20 +2,20 @@ # # Copyright 2019 Google LLC -obj-$(CONFIG_SPL_BUILD) += cpu_spl.o -obj-$(CONFIG_SPL_BUILD) += spl.o -obj-$(CONFIG_SPL_BUILD) += systemagent.o +obj-$(CONFIG_XPL_BUILD) += cpu_spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += systemagent.o obj-y += cpu_common.o ifndef CONFIG_TPL_BUILD obj-y += cpu.o obj-y += punit.o obj-y += fsp_bindings.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += fsp_m.o endif endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += acpi.o obj-y += fsp_s.o endif diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8798fa79d4c..8198667fa50 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -184,9 +184,9 @@ int arch_cpu_init(void) { int ret = 0; - if (spl_phase() == PHASE_TPL) + if (xpl_phase() == PHASE_TPL) ret = arch_cpu_init_tpl(); - else if (spl_phase() == PHASE_SPL) + else if (xpl_phase() == PHASE_SPL) ret = arch_cpu_init_spl(); if (ret) printf("%s: Error %d\n", __func__, ret); diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index f6fbddce922..b4bb677f5cd 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -247,7 +247,7 @@ static int fsp_update_config_from_dtb(ofnode node, u8 *cfg, return 0; } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) const struct fsp_binding fsp_m_bindings[] = { { .type = FSP_UINT32, @@ -653,7 +653,7 @@ int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg) } #endif -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) const struct fsp_binding fsp_s_bindings[] = { { .type = FSP_UINT8, diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 9ee362239ef..039236df02d 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -255,7 +255,7 @@ static int apl_hostbridge_of_to_plat(struct udevice *dev) static int apl_hostbridge_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) + if (xpl_phase() == PHASE_TPL) return apl_hostbridge_early_init(dev); return 0; diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index 531ff1cd91f..f34c199bf73 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -80,7 +80,7 @@ int lpc_open_pmio_window(uint base, uint size) lgir_reg_num = find_unused_pmio_window(); if (lgir_reg_num < 0) { - if (spl_phase() > PHASE_TPL) { + if (xpl_phase() > PHASE_TPL) { log_err("LPC: Cannot open IO window: %lx size %lx\n", bridge_base, size - bridged_size); log_err("No more IO windows\n"); diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c index 32190312ff8..07ef26f6bde 100644 --- a/arch/x86/cpu/apollolake/pch.c +++ b/arch/x86/cpu/apollolake/pch.c @@ -12,7 +12,7 @@ static int apl_set_spi_protect(struct udevice *dev, bool protect) { - if (spl_phase() == PHASE_SPL) + if (xpl_phase() == PHASE_SPL) return lpc_set_spi_protect(dev, BIOS_CTRL, protect); return 0; diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index 32fd0344861..bfb8a07d47a 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -115,7 +115,7 @@ int apl_pmc_ofdata_to_uc_plat(struct udevice *dev) ARRAY_SIZE(base)); if (ret) return log_msg_ret("Missing/short early-regs", ret); - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { upriv->pmc_bar0 = (void *)base[0]; upriv->pmc_bar2 = (void *)base[2]; @@ -186,7 +186,7 @@ static int enable_pmcbar(struct udevice *dev) static int apl_pmc_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { return enable_pmcbar(dev); } else { struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c index b1503c25140..9c708e9df55 100644 --- a/arch/x86/cpu/apollolake/punit.c +++ b/arch/x86/cpu/apollolake/punit.c @@ -77,7 +77,7 @@ static int punit_init(struct udevice *dev) static int apl_punit_probe(struct udevice *dev) { - if (spl_phase() == PHASE_SPL) + if (xpl_phase() == PHASE_SPL) return punit_init(dev); return 0; diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c index b351d73e7d8..510f8c4350f 100644 --- a/arch/x86/cpu/apollolake/spl.c +++ b/arch/x86/cpu/apollolake/spl.c @@ -116,7 +116,7 @@ static int spl_fast_spi_load_image(struct spl_image_info *spl_image, return ret; spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ - spl_image->entry_point = spl_phase() == PHASE_TPL ? + spl_image->entry_point = xpl_phase() == PHASE_TPL ? CONFIG_SPL_TEXT_BASE : CONFIG_TEXT_BASE; spl_image->load_addr = spl_image->entry_point; spl_image->os = IH_OS_U_BOOT; diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index 3e1f76d6118..dfe013e3833 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -2,23 +2,23 @@ # # Copyright (c) 2016 Google, Inc -obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += cpu.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += cpu_full.o +obj-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += cpu.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += cpu_full.o ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cpu_from_spl.o obj-y += cpu_full.o obj-y += refcode.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD # obj-y += cpu_from_spl.o obj-y += adsp.o obj-y += sata.o endif endif -ifeq ($(CONFIG_$(SPL_TPL_)X86_32BIT_INIT),) +ifeq ($(CONFIG_$(PHASE_)X86_32BIT_INIT),) #obj-y += cpu_from_spl.o endif @@ -29,5 +29,5 @@ obj-y += northbridge.o obj-y += pch.o obj-y += pinctrl_broadwell.o obj-y += power_state.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += refcode.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += sdram.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += refcode.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += sdram.o diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index dc6717eca40..87463748c4d 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -68,7 +68,7 @@ int arch_cpu_init(void) post_code(POST_CPU_INIT); /* Do a mini-init if TPL has already done the full init */ - if (IS_ENABLED(CONFIG_TPL) && spl_phase() != PHASE_TPL) + if (IS_ENABLED(CONFIG_TPL) && xpl_phase() != PHASE_TPL) return x86_cpu_reinit_f(); else return x86_cpu_init_f(); diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index c43fb7a608b..529dab18d5d 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -84,7 +84,7 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) int arch_cpu_init(void) { return 0; diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index 2c8b7380d96..5b6147432a7 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -606,7 +606,7 @@ static int broadwell_pch_probe(struct udevice *dev) return broadwell_pch_early_init(dev); else return broadwell_pch_init(dev); - } else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_SPL_BUILD)) { + } else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_XPL_BUILD)) { return broadwell_pch_init(dev); } else { return 0; diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 87e242a2065..6acdf9b3b23 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -9,7 +9,7 @@ LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC) LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) ifdef CONFIG_X86_64 -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_EFI_APP),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_EFI_APP),) LDSCRIPT = $(srctree)/arch/x86/cpu/u-boot-64.lds endif endif diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index a6cdb9a1485..a6c7d0e56d5 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -14,7 +14,7 @@ ifndef CONFIG_SPL obj-y += car.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += coreboot_spl.o else obj-y += sdram.o diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d474c79e25e..c3d7442b4a8 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -82,7 +82,7 @@ static void board_final_init(void) static int last_stage_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return 0; board_final_init(); diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index ad21fdb457a..ea11b09eacc 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -185,7 +185,7 @@ void show_boot_progress(int val) #endif #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) && \ - !defined(CONFIG_SPL_BUILD) + !defined(CONFIG_XPL_BUILD) /* * Implement a weak default function for boards that need to do some final init * before the system is ready. @@ -247,7 +247,7 @@ static int last_stage_init(void) } EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); -#endif /* !SYS_COREBOOT && !EFI_STUB && !SPL_BUILD */ +#endif /* !SYS_COREBOOT && !EFI_STUB && !XPL_BUILD */ static int x86_init_cpus(void) { diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 934e98ac582..d837fb97982 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -271,7 +271,7 @@ static void identify_cpu(struct cpu_device_id *cpu) * Do a quick and dirty check to save space - Intel and AMD only and * just the vendor. This is enough for most TPL code. */ - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { struct cpuid_result result; result = cpuid(0x00000000); diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 1dc17b45879..a28e6c77c9c 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -5,19 +5,19 @@ obj-$(CONFIG_INTEL_ACPIGEN) += acpi.o ifdef CONFIG_HAVE_MRC -obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o +obj-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += car.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += me_status.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += report_platform.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += mrc.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o endif ifdef CONFIG_INTEL_CAR_CQOS obj-$(CONFIG_TPL_BUILD) += car2.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += car2_uninit.o endif endif @@ -26,10 +26,10 @@ obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o obj-y += lpss.o -obj-$(CONFIG_$(SPL_)INTEL_GENERIC_WIFI) += generic_wifi.o +obj-$(CONFIG_$(XPL_)INTEL_GENERIC_WIFI) += generic_wifi.o ifndef CONFIG_EFI_APP -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o -ifndef CONFIG_$(SPL_)X86_64 +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += microcode.o +ifndef CONFIG_$(XPL_)X86_64 obj-y += microcode.o endif endif @@ -38,7 +38,7 @@ obj-$(CONFIG_HAVE_ITSS) += itss.o obj-$(CONFIG_HAVE_P2SB) += p2sb.o ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifndef CONFIG_SYS_COREBOOT obj-y += cpu_from_spl.o endif diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index c834c05d130..baa1f0e32d6 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -259,7 +259,7 @@ int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage) return ret; delay = dev_read_u32_default(dev, "fspm,training-delay", 0); - if (spl_phase() == PHASE_SPL) { + if (xpl_phase() == PHASE_SPL) { if (delay) printf("SDRAM training (%d seconds)...", delay); else diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index 7aad8f8ca56..406c41013fc 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -96,7 +96,7 @@ int p2sb_of_to_plat(struct udevice *dev) return log_msg_ret("Missing/short early-regs", ret); plat->mmio_base = base[0]; /* TPL sets up the initial BAR */ - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { plat->bdf = pci_get_devfn(dev); if (plat->bdf < 0) return log_msg_ret("Cannot get p2sb PCI address", @@ -114,9 +114,9 @@ int p2sb_of_to_plat(struct udevice *dev) static int p2sb_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) + if (xpl_phase() == PHASE_TPL) return p2sb_early_init(dev); - else if (spl_phase() == PHASE_SPL) + else if (xpl_phase() == PHASE_SPL) return p2sb_spl_init(dev); return 0; diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 716134e9ff3..471ad8d7ebc 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -5,15 +5,15 @@ ifdef CONFIG_HAVE_FSP obj-y += fsp_configs.o ivybridge.o else -obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o +obj-$(CONFIG_$(XPL_)X86_32BIT_INIT) += cpu.o obj-y += early_me.o obj-y += lpc.o obj-y += northbridge.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += sata.o endif -obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o -ifndef CONFIG_$(SPL_)X86_32BIT_INIT +obj-$(CONFIG_$(XPL_)X86_32BIT_INIT) += sdram.o +ifndef CONFIG_$(XPL_)X86_32BIT_INIT obj-y += sdram_nop.o endif endif diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index b7dd5bd46c7..1439916ac2d 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> -ifndef CONFIG_$(SPL_)X86_64 +ifndef CONFIG_$(XPL_)X86_64 obj-y += car.o endif obj-y += dram.o diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index 5c49b0f009b..f6836b74488 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -18,7 +18,7 @@ extern char *strchr(const char *s, int c); * Our assembly routines do not work on in 64-bit mode and we don't do a lot of * copying in SPL, so code size is more important there. */ -#if defined(CONFIG_SPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT) +#if defined(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT) #undef __HAVE_ARCH_MEMCPY extern void *memcpy(void *, const void *, __kernel_size_t); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 8fc35e1b51e..7677c0c352f 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -5,21 +5,21 @@ obj-y += bdinfo.o -ifndef CONFIG_$(SPL_TPL_)X86_64 +ifndef CONFIG_$(PHASE_)X86_64 obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_X86_32BIT_INIT) += string.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_BOOTM) += bootm.o endif obj-y += cmd_boot.o -obj-$(CONFIG_$(SPL_)COREBOOT_SYSINFO) += coreboot/ +obj-$(CONFIG_$(XPL_)COREBOOT_SYSINFO) += coreboot/ obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-y += early_cmos.o obj-y += e820.o @@ -27,7 +27,7 @@ obj-y += init_helpers.o obj-y += interrupts.o obj-y += lpc-uclass.o obj-y += mpspec.o -obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi_nhlt.o +obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_nhlt.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o @@ -44,10 +44,10 @@ obj-y += acpi.o obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o ifndef CONFIG_QEMU obj-y += acpigen.o -obj-$(CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE) += acpi_table.o +obj-$(CONFIG_$(PHASE_)GENERATE_ACPI_TABLE) += acpi_table.o endif obj-y += tables.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ZBOOT) += zimage.o endif obj-$(CONFIG_USE_HOB) += hob.o @@ -58,7 +58,7 @@ obj-$(CONFIG_FSP_VERSION1) += fsp1/ obj-$(CONFIG_FSP_VERSION2) += fsp2/ endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_TPL_BUILD obj-y += tpl.o else @@ -90,13 +90,13 @@ endif ifdef CONFIG_EFI_STUB -ifeq ($(CONFIG_$(SPL_)X86_64),) +ifeq ($(CONFIG_$(XPL_)X86_64),) extra-y += $(EFI_CRT0) $(EFI_RELOC) endif else -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),) extra-y += $(EFI_CRT0) $(EFI_RELOC) endif diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index da6c0a886ae..0039dd1bf5c 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -4,7 +4,7 @@ obj-y += fsp_common.o obj-y += fsp_dram.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o endif obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index a50dc985a3c..4c4c8334bdb 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -28,7 +28,7 @@ int dram_init(void) return 0; } - if (spl_phase() == PHASE_SPL) { + if (xpl_phase() == PHASE_SPL) { bool s3wake = false; s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index ecbadaae75c..1a2bf46c5c5 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -25,7 +25,7 @@ int fsp_setup_pinctrl(void) int ret; /* Make sure pads are set up early in U-Boot */ - if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F) + if (!ll_boot_init() || xpl_phase() != PHASE_BOARD_F) return 0; /* Probe all pinctrl devices to set up the pads */ @@ -134,7 +134,7 @@ int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry, return log_msg_ret("Could not get flash mmap", ret); } - if (spl_phase() >= PHASE_BOARD_F) { + if (xpl_phase() >= PHASE_BOARD_F) { if (type != FSP_S) return -EPROTONOSUPPORT; ret = binman_entry_find("intel-fsp-s", entry); diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 7c03dea0711..f7df7e03621 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -103,7 +103,7 @@ int spl_spi_load_image(void) void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { - debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()), + debug("Jumping to %s at %lx\n", xpl_name(xpl_next_phase()), (ulong)spl_image->entry_point); #ifdef DEBUG print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1, diff --git a/board/BuR/brppt1/Makefile b/board/BuR/brppt1/Makefile index 3dec0e6522a..417afacad15 100644 --- a/board/BuR/brppt1/Makefile +++ b/board/BuR/brppt1/Makefile @@ -5,7 +5,7 @@ # Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> # Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y := mux.o endif obj-y += ../common/common.o diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index 80e0ca805b5..8b7def06cc4 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; /* -- defines for GPIO -- */ #define REPSWITCH (0+20) /* GPIO0_20 */ -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* TODO: check ram-timing ! */ static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, @@ -142,7 +142,7 @@ void sdram_init(void) &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* Basic board specific setup. Pinmux has been handled already. */ int board_init(void) diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c index 105fac8912d..c0a163251b4 100644 --- a/board/BuR/brppt2/board.c +++ b/board/BuR/brppt2/board.c @@ -16,7 +16,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD # include <asm/arch/mx6-ddr.h> #endif #include <asm/arch/clock.h> @@ -82,7 +82,7 @@ #define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl)) -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) static iomux_v3_cfg_t const eth_pads[] = { /* * Gigabit Ethernet @@ -542,4 +542,4 @@ void board_init_f(ulong dummy) void reset_cpu(void) { } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/BuR/brppt2/config.mk b/board/BuR/brppt2/config.mk index 0d1638a97ac..f2362d16dc4 100644 --- a/board/BuR/brppt2/config.mk +++ b/board/BuR/brppt2/config.mk @@ -23,7 +23,7 @@ cmd_prodzip = \ zip -9 -r $@ misc/* >/dev/null $< ifeq ($(hw-platform-y),brppt2) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) INPUTS-y += $(hw-platform-y)_prog.bin INPUTS-y += $(hw-platform-y)_prod.zip endif diff --git a/board/BuR/brsmarc1/Makefile b/board/BuR/brsmarc1/Makefile index 1c3f64dea4d..42b647af58d 100644 --- a/board/BuR/brsmarc1/Makefile +++ b/board/BuR/brsmarc1/Makefile @@ -4,7 +4,7 @@ # B&R Industrial Automation GmbH - http://www.br-automation.com/ # -obj-$(CONFIG_SPL_BUILD) += mux.o +obj-$(CONFIG_XPL_BUILD) += mux.o obj-y += ../common/br_resetc.o obj-y += ../common/common.o obj-y += board.o diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c index bfb6adf6d5c..c05eec6b35e 100644 --- a/board/BuR/brsmarc1/board.c +++ b/board/BuR/brsmarc1/board.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, .datawdsratio0 = MT41K256M16HA125E_WR_DQS, @@ -124,8 +124,8 @@ void sdram_init(void) &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } -#endif /* CONFIG_SPL_BUILD */ -#if !defined(CONFIG_SPL_BUILD) +#endif /* CONFIG_XPL_BUILD */ +#if !defined(CONFIG_XPL_BUILD) /* decision if backlight is switched on or not on powerup */ int board_backlightstate(void) @@ -166,4 +166,4 @@ int board_late_init(void) } #endif /* CONFIG_BOARD_LATE_INIT */ -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/board/BuR/brxre1/Makefile b/board/BuR/brxre1/Makefile index 1d224e9e719..c4b1a67be3e 100644 --- a/board/BuR/brxre1/Makefile +++ b/board/BuR/brxre1/Makefile @@ -5,7 +5,7 @@ # Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> - # Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ -obj-$(CONFIG_SPL_BUILD) += mux.o +obj-$(CONFIG_XPL_BUILD) += mux.o obj-y += ../common/br_resetc.o obj-y += ../common/common.o obj-y += board.o diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c index 510d2af3147..c25af42e70a 100644 --- a/board/BuR/brxre1/board.c +++ b/board/BuR/brxre1/board.c @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, .datawdsratio0 = MT41K256M16HA125E_WR_DQS, @@ -134,7 +134,7 @@ void sdram_init(void) &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* * Basic board specific setup. Pinmux has been handled already. */ diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 8aff821cfe8..7fb61736710 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -83,7 +83,7 @@ int overwrite_console(void) return 1; } -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_AM33XX) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_AM33XX) #include <asm/arch/hardware.h> #include <asm/arch/omap.h> #include <asm/arch/clock.h> @@ -175,4 +175,4 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } -#endif /* CONFIG_SPL_BUILD && CONFIG_AM33XX */ +#endif /* CONFIG_XPL_BUILD && CONFIG_AM33XX */ diff --git a/board/CZ.NIC/turris_1x/Makefile b/board/CZ.NIC/turris_1x/Makefile index a24aee9161b..1bf370122d9 100644 --- a/board/CZ.NIC/turris_1x/Makefile +++ b/board/CZ.NIC/turris_1x/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) 2022 Pali Rohár <pali@kernel.org> -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += ../../freescale/p1_p2_rdb_pc/spl.o endif diff --git a/board/CZ.NIC/turris_1x/tlb.c b/board/CZ.NIC/turris_1x/tlb.c index f35a5558385..5e5892ee1e5 100644 --- a/board/CZ.NIC/turris_1x/tlb.c +++ b/board/CZ.NIC/turris_1x/tlb.c @@ -111,7 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 9, BOOKE_PAGESZ_256K, 1), #endif -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) /* **M** - SDRAM 2G */ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile index d1ef5cb8600..acaa3b8ef31 100644 --- a/board/CZ.NIC/turris_omnia/Makefile +++ b/board/CZ.NIC/turris_omnia/Makefile @@ -4,4 +4,4 @@ obj-y := turris_omnia.o ../turris_atsha_otp.o ../turris_common.o obj-$(CONFIG_CMD_EEPROM_LAYOUT) += eeprom.o -obj-$(CONFIG_SPL_BUILD) += old_ddr3_training.o +obj-$(CONFIG_XPL_BUILD) += old_ddr3_training.o diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index eb88ee7f1ed..b7588fa4eec 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -494,7 +494,7 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep) if (!eeprom) return false; - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) ret = dm_i2c_read(eeprom, 0, (void *)oep, sizeof(*oep)); else ret = i2c_eeprom_read(eeprom, 0, (void *)oep, sizeof(*oep)); diff --git a/board/Synology/ds414/Makefile b/board/Synology/ds414/Makefile index b1d018effaa..1a10e9d8d54 100644 --- a/board/Synology/ds414/Makefile +++ b/board/Synology/ds414/Makefile @@ -3,6 +3,6 @@ # Copyright (C) 2015 Phil Sutter <phil@nwl.cc> obj-y += ds414.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cmd_syno.o endif diff --git a/board/advantech/imx8mp_rsb3720a1/Makefile b/board/advantech/imx8mp_rsb3720a1/Makefile index eb6b18b04a2..39fb0d4fb62 100644 --- a/board/advantech/imx8mp_rsb3720a1/Makefile +++ b/board/advantech/imx8mp_rsb3720a1/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_6G obj-y += imx8mp_rsb3720a1.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_6G.o endif @@ -17,7 +17,7 @@ endif ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_4G obj-y += imx8mp_rsb3720a1.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_4G.o endif diff --git a/board/advantech/imx8qm_dmsse20_a1/Makefile b/board/advantech/imx8qm_dmsse20_a1/Makefile index 262ffcd6834..c82fcc85636 100644 --- a/board/advantech/imx8qm_dmsse20_a1/Makefile +++ b/board/advantech/imx8qm_dmsse20_a1/Makefile @@ -5,4 +5,4 @@ # obj-y += imx8qm_dmsse20_a1.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/advantech/imx8qm_rom7720_a1/Makefile b/board/advantech/imx8qm_rom7720_a1/Makefile index 51c5de251c4..d8792c6c687 100644 --- a/board/advantech/imx8qm_rom7720_a1/Makefile +++ b/board/advantech/imx8qm_rom7720_a1/Makefile @@ -6,6 +6,6 @@ obj-y += imx8qm_rom7720_a1.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o endif diff --git a/board/alliedtelesis/x530/Makefile b/board/alliedtelesis/x530/Makefile index 97de1d463fe..467c55d7e66 100644 --- a/board/alliedtelesis/x530/Makefile +++ b/board/alliedtelesis/x530/Makefile @@ -4,6 +4,6 @@ # obj-y := $(BOARD).o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += ../common/gpio_hog.o endif diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS index b2e3205fdf0..e73a4e52c1f 100644 --- a/board/amlogic/p212/MAINTAINERS +++ b/board/amlogic/p212/MAINTAINERS @@ -5,11 +5,9 @@ L: u-boot-amlogic@groups.io F: board/amlogic/p212/ F: include/configs/p212.h F: configs/khadas-vim_defconfig -F: configs/libretech-ac_defconfig F: configs/libretech-cc_defconfig F: configs/libretech-cc_v2_defconfig F: configs/p212_defconfig F: doc/board/amlogic/p212.rst -F: doc/board/amlogic/libretech-ac.rst F: doc/board/amlogic/libretech-cc.rst F: doc/board/amlogic/khadas-vim.rst diff --git a/board/asus/grouper/MAINTAINERS b/board/asus/grouper/MAINTAINERS index f4068d85623..3c59632451f 100644 --- a/board/asus/grouper/MAINTAINERS +++ b/board/asus/grouper/MAINTAINERS @@ -2,6 +2,6 @@ GROUPER BOARD M: Svyatoslav Ryhel <clamor95@gmail.com> S: Maintained F: board/asus/grouper/ -F: configs/grouper_common_defconfig -F: doc/board/asus/grouper_common.rst +F: configs/grouper_defconfig +F: doc/board/asus/grouper.rst F: include/configs/grouper.h diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile index d041cf80870..8a8e6530c86 100644 --- a/board/asus/grouper/Makefile +++ b/board/asus/grouper/Makefile @@ -6,9 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel <clamor95@gmail.com> -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_DM_PMIC_MAX77663) += grouper-spl-max.o -obj-$(CONFIG_DM_PMIC_TPS65910) += grouper-spl-ti.o -endif +obj-$(CONFIG_SPL_BUILD) += grouper-spl.o +obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += grouper.o diff --git a/board/asus/grouper/board-info.c b/board/asus/grouper/board-info.c new file mode 100644 index 00000000000..4892accc523 --- /dev/null +++ b/board/asus/grouper/board-info.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <env.h> +#include <spl_gpio.h> + +#include <asm/gpio.h> +#include <asm/arch/pinmux.h> + +/* + * PMIC_ID is GMI_CS2_N_PK3 + * MODEM_ID is GMI_CS4_N_PK2 + * + * Extended Project ID + * ==================================== + * MODEM_ID PMIC_ID project name + * 0 0 grouper-E1565 + * 0 1 grouper-PM269 + * 1 0 tilapia + */ +enum project_rev { + E1565, PM269, TILAPIA, COUNT, +}; + +static const char * const project_id_to_fdt[] = { + [E1565] = "tegra30-asus-nexus7-grouper-E1565", + [PM269] = "tegra30-asus-nexus7-grouper-PM269", + [TILAPIA] = "tegra30-asus-nexus7-tilapia-E1565", +}; + +static int id_gpio_get_value(u32 pingrp, u32 pin) +{ + /* Configure pinmux */ + pinmux_set_func(pingrp, PMUX_FUNC_GMI); + pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); + pinmux_tristate_enable(pingrp); + pinmux_set_io(pingrp, PMUX_PIN_INPUT); + + /* + * Since this function may be called + * during DM reload we should use SPL + * GPIO functions which do not depend + * on DM. + */ + spl_gpio_input(NULL, pin); + return spl_gpio_get_value(NULL, pin); +} + +static int get_project_id(void) +{ + u32 pmic_id, modem_id, proj_id; + + modem_id = id_gpio_get_value(PMUX_PINGRP_GMI_CS4_N_PK2, + TEGRA_GPIO(K, 2)); + pmic_id = id_gpio_get_value(PMUX_PINGRP_GMI_CS2_N_PK3, + TEGRA_GPIO(K, 3)); + + proj_id = (modem_id << 1 | pmic_id) & COUNT; + + log_debug("[GROUPER]: project id %d (%s)\n", proj_id, + project_id_to_fdt[proj_id]); + + return proj_id; +} + +int board_fit_config_name_match(const char *name) +{ + if (!strcmp(name, project_id_to_fdt[get_project_id()])) + return 0; + + return -1; +} + +void nvidia_board_late_init(void) +{ + char dt_path[64] = { 0 }; + + snprintf(dt_path, sizeof(dt_path), "%s.dtb", + project_id_to_fdt[get_project_id()]); + env_set("fdtfile", dt_path); +} diff --git a/board/asus/grouper/configs/grouper_E1565.config b/board/asus/grouper/configs/grouper_E1565.config deleted file mode 100644 index 265295c8b3e..00000000000 --- a/board/asus/grouper/configs/grouper_E1565.config +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565" -CONFIG_CMD_POWEROFF=y -# CONFIG_MAX77663_GPIO is not set -CONFIG_DM_PMIC_MAX77663=y -CONFIG_DM_REGULATOR_MAX77663=y -CONFIG_SYSRESET_MAX77663=y diff --git a/board/asus/grouper/configs/grouper_PM269.config b/board/asus/grouper/configs/grouper_PM269.config deleted file mode 100644 index a7ee3587edd..00000000000 --- a/board/asus/grouper/configs/grouper_PM269.config +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-PM269" -CONFIG_CMD_POWEROFF=y -CONFIG_DM_PMIC_TPS65910=y -# CONFIG_DM_REGULATOR_TPS65910 is not set -CONFIG_DM_REGULATOR_TPS65911=y -CONFIG_SYSRESET_TPS65910=y diff --git a/board/asus/grouper/configs/tilapia.config b/board/asus/grouper/configs/tilapia.config deleted file mode 100644 index d461b4752a9..00000000000 --- a/board/asus/grouper/configs/tilapia.config +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-tilapia-E1565" -CONFIG_SYS_PROMPT="Tegra30 (Tilapia) # " -CONFIG_CMD_POWEROFF=y -# CONFIG_MAX77663_GPIO is not set -CONFIG_DM_PMIC_MAX77663=y -CONFIG_DM_REGULATOR_MAX77663=y -CONFIG_SYSRESET_MAX77663=y diff --git a/board/asus/grouper/grouper-spl-max.c b/board/asus/grouper/grouper-spl-max.c deleted file mode 100644 index 3e58bf97cc4..00000000000 --- a/board/asus/grouper/grouper-spl-max.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * T30 Grouper MAX SPL stage configuration - * - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2022 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#include <asm/arch/tegra.h> -#include <asm/arch-tegra/tegra_i2c.h> -#include <linux/delay.h> - -#define MAX77663_I2C_ADDR (0x3C << 1) - -#define MAX77663_REG_SD0 0x16 -#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) -#define MAX77663_REG_SD1 0x17 -#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) -#define MAX77663_REG_LDO4 0x2B -#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) - -#define MAX77663_REG_GPIO4 0x3A -#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4) - -void pmic_enable_cpu_vdd(void) -{ - /* Set VDD_CORE to 1.200V. */ - tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA); - - udelay(1000); - - /* Bring up VDD_CPU to 1.0125V. */ - tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA); - udelay(1000); - - /* Bring up VDD_RTC to 1.200V. */ - tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA); - udelay(10 * 1000); - - /* Set 32k-out gpio state */ - tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA); -} diff --git a/board/asus/grouper/grouper-spl-ti.c b/board/asus/grouper/grouper-spl-ti.c deleted file mode 100644 index 1dcce80b48c..00000000000 --- a/board/asus/grouper/grouper-spl-ti.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * T30 Grouper TI SPL stage configuration - * - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2022 - * Svyatoslav Ryhel <clamor95@gmail.com> - */ - -#include <asm/arch/tegra.h> -#include <asm/arch-tegra/tegra_i2c.h> -#include <linux/delay.h> - -#define TPS65911_I2C_ADDR (0x2D << 1) -#define TPS65911_VDDCTRL_OP_REG 0x28 -#define TPS65911_VDDCTRL_SR_REG 0x27 -#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) -#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) - -#define TPS62361B_I2C_ADDR (0x60 << 1) -#define TPS62361B_SET3_REG 0x03 -#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) - -void pmic_enable_cpu_vdd(void) -{ - /* Set VDD_CORE to 1.200V. */ - tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); - - udelay(1000); - - /* - * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. - * First set VDD to 1.0125V, then enable the VDD regulator. - */ - tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); - udelay(1000); - tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); - udelay(10 * 1000); -} diff --git a/board/asus/grouper/grouper-spl.c b/board/asus/grouper/grouper-spl.c new file mode 100644 index 00000000000..a8d4e540ab2 --- /dev/null +++ b/board/asus/grouper/grouper-spl.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 Grouper SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2022 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/gpio.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <spl_gpio.h> +#include <linux/delay.h> + +#define MAX77663_I2C_ADDR (0x3C << 1) + +#define MAX77663_REG_SD0 0x16 +#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) +#define MAX77663_REG_SD1 0x17 +#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) +#define MAX77663_REG_LDO4 0x2B +#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) + +#define MAX77663_REG_GPIO4 0x3A +#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4) + +#define TPS65911_I2C_ADDR (0x2D << 1) + +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) + +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +/* + * PCB_ID[8] is GMI_CS2_N_PK3 + * + * PMIC module detection + * ============================== + * PCB_ID[8] 0 1 + * PMIC Maxim TI + */ +static bool ti_pmic_detected(void) +{ + /* Configure pinmux */ + pinmux_set_func(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_FUNC_GMI); + pinmux_set_pullupdown(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PULL_DOWN); + pinmux_tristate_enable(PMUX_PINGRP_GMI_CS2_N_PK3); + pinmux_set_io(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PIN_INPUT); + + spl_gpio_input(NULL, TEGRA_GPIO(K, 3)); + return spl_gpio_get_value(NULL, TEGRA_GPIO(K, 3)); +} + +static void max_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA); + + udelay(1000); + + /* Bring up VDD_CPU to 1.0125V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA); + udelay(1000); + + /* Bring up VDD_RTC to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA); + udelay(10 * 1000); + + /* Set 32k-out gpio state */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA); +} + +static void ti_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} + +void pmic_enable_cpu_vdd(void) +{ + if (ti_pmic_detected()) + ti_enable_cpu_vdd(); + else + max_enable_cpu_vdd(); +} diff --git a/board/asus/grouper/grouper.env b/board/asus/grouper/grouper.env new file mode 100644 index 00000000000..b1f4aeb5552 --- /dev/null +++ b/board/asus/grouper/grouper.env @@ -0,0 +1,15 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +button_cmd_1_name=Lid +button_cmd_1=poweroff +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_2=update bootloader=run flash_uboot +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/board/asus/transformer-t20/transformer-t20.env b/board/asus/transformer-t20/transformer-t20.env new file mode 100644 index 00000000000..2f7e8206c24 --- /dev/null +++ b/board/asus/transformer-t20/transformer-t20.env @@ -0,0 +1,17 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +button_cmd_1_name=Lid sensor +button_cmd_1=poweroff +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/asus/transformer-t30/MAINTAINERS b/board/asus/transformer-t30/MAINTAINERS index 071a9c04b86..869cc5aeb91 100644 --- a/board/asus/transformer-t30/MAINTAINERS +++ b/board/asus/transformer-t30/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/asus/transformer-t30/ F: configs/transformer_t30_defconfig F: doc/board/asus/transformer_t30.rst -F: include/configs/transformer-common.h F: include/configs/transformer-t30.h diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile index c083f2289ba..22b6160f757 100644 --- a/board/asus/transformer-t30/Makefile +++ b/board/asus/transformer-t30/Makefile @@ -7,5 +7,6 @@ # Svyatoslav Ryhel <clamor95@gmail.com> obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o +obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += transformer-t30.o diff --git a/board/asus/transformer-t30/board-info.c b/board/asus/transformer-t30/board-info.c new file mode 100644 index 00000000000..a2b540c90b6 --- /dev/null +++ b/board/asus/transformer-t30/board-info.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <env.h> +#include <spl_gpio.h> + +#include <asm/gpio.h> +#include <asm/arch/pinmux.h> + +/* + * PCB_ID[1] is kb_row5_pr5 + * PCB_ID[3] is kb_col7_pq7 + * PCB_ID[4] is kb_row2_pr2 + * PCB_ID[5] is kb_col5_pq5 + * + * Project ID + * ===================================================== + * PCB_ID[1] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project + * 0 0 0 0 TF201 + * 0 0 0 1 P1801 + * 0 0 1 0 TF300T + * 0 0 1 1 TF300TG + * 0 1 0 0 TF700T + * 0 1 0 1 TF300TL + * 0 1 1 0 Extension + * 0 1 1 1 TF500T + * 1 0 0 0 TF502T/TF600T + * ===================================================== + */ +enum project_rev { + TF201, P1801, TF300T, TF300TG, TF700T, + TF300TL, EXT, TF500T, TF600T +}; + +static const char * const project_id_to_fdt[] = { + [TF201] = "tegra30-asus-tf201", + [P1801] = "tegra30-asus-p1801-t", + [TF300T] = "tegra30-asus-tf300t", + [TF300TG] = "tegra30-asus-tf300tg", + [TF700T] = "tegra30-asus-tf700t", + [TF300TL] = "tegra30-asus-tf300tl", + [TF600T] = "tegra30-asus-tf600t", +}; + +static int id_gpio_get_value(u32 pingrp, u32 pin) +{ + /* Configure pinmux */ + pinmux_set_func(pingrp, PMUX_FUNC_KBC); + pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); + pinmux_tristate_enable(pingrp); + pinmux_set_io(pingrp, PMUX_PIN_INPUT); + + /* + * Since this function may be called + * during DM reload we should use SPL + * GPIO functions which do not depend + * on DM. + */ + spl_gpio_input(NULL, pin); + return spl_gpio_get_value(NULL, pin); +} + +static int get_project_id(void) +{ + u32 pcb_id1, pcb_id3, pcb_id4, pcb_id5; + + pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_ROW5_PR5, + TEGRA_GPIO(R, 5)); + pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL7_PQ7, + TEGRA_GPIO(Q, 7)); + pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_ROW2_PR2, + TEGRA_GPIO(R, 2)); + pcb_id5 = id_gpio_get_value(PMUX_PINGRP_KB_COL5_PQ5, + TEGRA_GPIO(Q, 5)); + + /* Construct board ID */ + int proj_id = pcb_id1 << 3 | pcb_id5 << 2 | + pcb_id4 << 1 | pcb_id3; + + log_debug("[TRANSFORMER]: project id %d (%s)\n", proj_id, + project_id_to_fdt[proj_id]); + + /* Mark tablet with SPI flash */ + if (proj_id == TF600T) + env_set_hex("spiflash", true); + else + env_set_hex("spiflash", false); + + return proj_id & 0xf; +} + +int board_fit_config_name_match(const char *name) +{ + if (!strcmp(name, project_id_to_fdt[get_project_id()])) + return 0; + + return -1; +} + +void nvidia_board_late_init(void) +{ + char dt_path[64] = { 0 }; + + snprintf(dt_path, sizeof(dt_path), "%s.dtb", + project_id_to_fdt[get_project_id()]); + env_set("fdtfile", dt_path); +} diff --git a/board/asus/transformer-t30/configs/p1801-t.config b/board/asus/transformer-t30/configs/p1801-t.config deleted file mode 100644 index f378f54570d..00000000000 --- a/board/asus/transformer-t30/configs/p1801-t.config +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-p1801-t" -# CONFIG_I2C_MUX is not set -CONFIG_USB_GADGET_PRODUCT_NUM=0x4cb0 diff --git a/board/asus/transformer-t30/configs/tf201.config b/board/asus/transformer-t30/configs/tf201.config deleted file mode 100644 index e4fd30378a1..00000000000 --- a/board/asus/transformer-t30/configs/tf201.config +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201" -# CONFIG_I2C_MUX is not set -CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/configs/tf300t.config b/board/asus/transformer-t30/configs/tf300t.config deleted file mode 100644 index 9ad2ebd98e8..00000000000 --- a/board/asus/transformer-t30/configs/tf300t.config +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300t" -# CONFIG_I2C_MUX is not set -CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/configs/tf300tg.config b/board/asus/transformer-t30/configs/tf300tg.config deleted file mode 100644 index 7b44a91acc4..00000000000 --- a/board/asus/transformer-t30/configs/tf300tg.config +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tg" -# CONFIG_I2C_MUX is not set -CONFIG_USB_GADGET_PRODUCT_NUM=0x4c80 diff --git a/board/asus/transformer-t30/configs/tf300tl.config b/board/asus/transformer-t30/configs/tf300tl.config deleted file mode 100644 index 81e96d5df6f..00000000000 --- a/board/asus/transformer-t30/configs/tf300tl.config +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf300tl" -# CONFIG_I2C_MUX is not set -CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/configs/tf600t.config b/board/asus/transformer-t30/configs/tf600t.config deleted file mode 100644 index b3734869f59..00000000000 --- a/board/asus/transformer-t30/configs/tf600t.config +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t" -CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" -# CONFIG_I2C_MUX is not set -CONFIG_TEGRA20_SLINK=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/board/asus/transformer-t30/configs/tf700t.config b/board/asus/transformer-t30/configs/tf700t.config deleted file mode 100644 index 887c25fbf22..00000000000 --- a/board/asus/transformer-t30/configs/tf700t.config +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf700t" -CONFIG_CLK_GPIO=y -CONFIG_USB_GADGET_PRODUCT_NUM=0x4c90 -CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y diff --git a/board/asus/transformer-t30/transformer-t30.env b/board/asus/transformer-t30/transformer-t30.env new file mode 100644 index 00000000000..9b6f4079f84 --- /dev/null +++ b/board/asus/transformer-t30/transformer-t30.env @@ -0,0 +1,17 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=if spiflash; then run update_spi; else bootmenu; fi +button_cmd_1_name=Lid sensor +button_cmd_1=poweroff +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index af486e977e5..d94904366ed 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -70,7 +70,7 @@ void at91sam9m10g45ek_nand_hw_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <spl.h> #include <nand.h> diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 6f9abcbb127..2cddc2175ac 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -119,7 +119,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <spl.h> #include <nand.h> diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index f52b9a97731..3f41fb1c983 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -134,7 +134,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <spl.h> #include <nand.h> diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index cb3cd7ac9ae..bf54fc33df4 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -105,7 +105,7 @@ int misc_init_r(void) #endif /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { } diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 15cbd0daa6f..04de1257eca 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -90,7 +90,7 @@ int dram_init(void) } /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void board_leds_init(void) { diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 6f0d578abf7..113bd2feb62 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -79,7 +79,7 @@ int misc_init_r(void) } /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* must set PB25 low to enable the CAN transceivers */ static void board_can_stdby_dis(void) diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index d104736fa7c..eca5b2bf107 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -105,7 +105,7 @@ int misc_init_r(void) #endif /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { } diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index f98322fb540..7a813c19ff2 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -117,7 +117,7 @@ int dram_init(void) } /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { #ifdef CONFIG_SD_BOOT diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 28079a81517..555a8c0970b 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -194,7 +194,7 @@ int board_late_init(void) #endif /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { #if CONFIG_NAND_BOOT diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index f9112fc5321..e296b0466aa 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -141,7 +141,7 @@ int dram_init(void) } /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { #if CONFIG_NAND_BOOT diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 0bdc6adbdc8..e820605d3b9 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -127,7 +127,7 @@ int dram_init(void) } /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { #if CONFIG_NAND_BOOT diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile index d6890e5797f..ec1710e137e 100644 --- a/board/avionic-design/tec-ng/Makefile +++ b/board/avionic-design/tec-ng/Makefile @@ -3,6 +3,6 @@ # (C) Copyright 2013 # Avionic Design GmbH <www.avionic-design.de> -obj-$(CONFIG_SPL_BUILD) += tec-ng-spl.o +obj-$(CONFIG_XPL_BUILD) += tec-ng-spl.o obj-y += ../common/tamonten-ng.o diff --git a/board/beacon/imx8mm/Makefile b/board/beacon/imx8mm/Makefile index 7d3bd3112cb..b33dc8b05b9 100644 --- a/board/beacon/imx8mm/Makefile +++ b/board/beacon/imx8mm/Makefile @@ -7,7 +7,7 @@ obj-y += imx8mm_beacon.o obj-y += ../../freescale/common/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += lpddr4_timing.o endif diff --git a/board/beacon/imx8mn/Makefile b/board/beacon/imx8mn/Makefile index d620ccb7723..48b7b0952cc 100644 --- a/board/beacon/imx8mn/Makefile +++ b/board/beacon/imx8mn/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mn_beacon.o obj-y += ../../freescale/common/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o ifdef CONFIG_IMX8MN_BEACON_2GB_LPDDR obj-y += lpddr4_2g_timing.o diff --git a/board/beacon/imx8mp/Makefile b/board/beacon/imx8mp/Makefile index 264720f6d49..7b994d2c8a1 100644 --- a/board/beacon/imx8mp/Makefile +++ b/board/beacon/imx8mp/Makefile @@ -7,7 +7,7 @@ obj-y += imx8mp_beacon.o obj-y += ../../freescale/common/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/bitmain/antminer_s9/Makefile b/board/bitmain/antminer_s9/Makefile index 1af01d6d808..57580f3730b 100644 --- a/board/bitmain/antminer_s9/Makefile +++ b/board/bitmain/antminer_s9/Makefile @@ -6,4 +6,4 @@ obj-y += ../../xilinx/common/board.o # Remove quotes hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) -obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o +obj-$(CONFIG_XPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c index a1a00e7ffc4..4c7c9d38a44 100644 --- a/board/bosch/acc/acc.c +++ b/board/bosch/acc/acc.c @@ -269,7 +269,7 @@ int dram_init(void) return 0; } -#if IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> diff --git a/board/bosch/guardian/Makefile b/board/bosch/guardian/Makefile index 20cecbfb64e..8e38881ec2c 100644 --- a/board/bosch/guardian/Makefile +++ b/board/bosch/guardian/Makefile @@ -5,7 +5,7 @@ # Copyright (C) 2018 Robert Bosch Power Tools GmbH # -ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index 1f9dc2d8df1..02f51ca2ca8 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -259,7 +259,7 @@ static void check_button_status(void) } } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { @@ -473,7 +473,7 @@ int board_late_init(void) #endif #if defined(CONFIG_USB_ETHER) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) + (!defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) int board_eth_init(struct bd_info *bis) { return usb_eth_initialize(bis); diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile index b761bbb2f90..59870419bdd 100644 --- a/board/bsh/imx6ulz_smm_m2/Makefile +++ b/board/bsh/imx6ulz_smm_m2/Makefile @@ -2,5 +2,5 @@ # (C) Copyright 2021 Amarula Solutions B.V. obj-y := imx6ulz_smm_m2.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/bsh/imx8mn_smm_s2/Makefile b/board/bsh/imx8mn_smm_s2/Makefile index 19d37a723ea..3050194ff89 100644 --- a/board/bsh/imx8mn_smm_s2/Makefile +++ b/board/bsh/imx8mn_smm_s2/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mn_smm_s2.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_BSH_SMM_S2_DDR3L_256) += ddr3l_timing_256m.o obj-$(CONFIG_BSH_SMM_S2_DDR3L_512) += ddr3l_timing_512m.o diff --git a/board/bticino/mamoj/Makefile b/board/bticino/mamoj/Makefile index f1ddda48918..b83e667e828 100644 --- a/board/bticino/mamoj/Makefile +++ b/board/bticino/mamoj/Makefile @@ -5,4 +5,4 @@ # obj-y := mamoj.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/cloos/imx8mm_phg/Makefile b/board/cloos/imx8mm_phg/Makefile index 2b36931fcf7..c3e54bfc2e0 100644 --- a/board/cloos/imx8mm_phg/Makefile +++ b/board/cloos/imx8mm_phg/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mm_phg.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/compulab/cl-som-imx7/Makefile b/board/compulab/cl-som-imx7/Makefile index 8f0e068b7e9..35cf2c13562 100644 --- a/board/compulab/cl-som-imx7/Makefile +++ b/board/compulab/cl-som-imx7/Makefile @@ -10,7 +10,7 @@ obj-y := mux.o common.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += cl-som-imx7.o diff --git a/board/compulab/cl-som-imx7/common.h b/board/compulab/cl-som-imx7/common.h index bc19867f876..5b29763b340 100644 --- a/board/compulab/cl-som-imx7/common.h +++ b/board/compulab/cl-som-imx7/common.h @@ -18,7 +18,7 @@ PADS_SET_PROT(uart1_pads); PADS_SET_PROT(espi1_pads); #endif /* CONFIG_SPI */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifdef CONFIG_FSL_ESDHC_IMX PADS_SET_PROT(usdhc3_emmc_pads); #endif /* CONFIG_FSL_ESDHC_IMX */ @@ -28,4 +28,4 @@ PADS_SET_PROT(fec1_pads); #endif /* CONFIG_FEC_MXC */ PADS_SET_PROT(usb_otg1_pads); PADS_SET_PROT(wdog_pads); -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c index 25123ee145a..da8848b9f57 100644 --- a/board/compulab/cl-som-imx7/mux.c +++ b/board/compulab/cl-som-imx7/mux.c @@ -67,7 +67,7 @@ PADS_SET(espi1_pads) #endif /* CONFIG_SPI */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifdef CONFIG_FSL_ESDHC_IMX @@ -138,4 +138,4 @@ static iomux_v3_cfg_t const wdog_pads[] = { PADS_SET(wdog_pads) -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/board/compulab/cm_fx6/Makefile b/board/compulab/cm_fx6/Makefile index e648db26a1d..e9f86cb8410 100644 --- a/board/compulab/cm_fx6/Makefile +++ b/board/compulab/cm_fx6/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> # # Authors: Nikita Kiryanov <nikita@compulab.co.il> -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y = common.o spl.o else obj-y = common.o cm_fx6.o diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile index 6fa231a045e..221d1b432fd 100644 --- a/board/compulab/cm_t43/Makefile +++ b/board/compulab/cm_t43/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2015 Compulab, Ltd. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o mux.o else obj-y += cm_t43.o mux.o diff --git a/board/compulab/imx8mm-cl-iot-gate/Makefile b/board/compulab/imx8mm-cl-iot-gate/Makefile index 3800b21a6fd..7c2d6e508b3 100644 --- a/board/compulab/imx8mm-cl-iot-gate/Makefile +++ b/board/compulab/imx8mm-cl-iot-gate/Makefile @@ -7,7 +7,7 @@ obj-y += imx8mm-cl-iot-gate.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o eeprom_spl.o obj-y += ddr/ endif diff --git a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c index 1256848f9a9..a22e6ef1d96 100644 --- a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c @@ -10,7 +10,7 @@ #include <asm/setup.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_SYS_I2C_EEPROM_ADDR_P1 0x51 diff --git a/board/comvetia/lxr2/lxr2.c b/board/comvetia/lxr2/lxr2.c index 173263522bd..dc7fc202049 100644 --- a/board/comvetia/lxr2/lxr2.c +++ b/board/comvetia/lxr2/lxr2.c @@ -138,7 +138,7 @@ int board_late_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11) diff --git a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c index 37750137ad9..15dba146eb8 100644 --- a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c +++ b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c @@ -141,7 +141,7 @@ int dram_init(void) } /* SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { } diff --git a/board/congatec/cgtqmx8/Makefile b/board/congatec/cgtqmx8/Makefile index 4b59dbb6bc7..2a02cec4f15 100644 --- a/board/congatec/cgtqmx8/Makefile +++ b/board/congatec/cgtqmx8/Makefile @@ -6,6 +6,6 @@ obj-y += cgtqmx8.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o endif diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile index 2db0fc1ae5c..f8170d9c653 100644 --- a/board/congatec/common/Makefile +++ b/board/congatec/common/Makefile @@ -7,7 +7,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index 75bfbd18943..0abdb7df534 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -11,4 +11,4 @@ # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. obj-y += coreboot.o -obj-$(CONFIG_$(SPL_TPL_)SMBIOS_PARSER) += sysinfo.o +obj-$(CONFIG_$(PHASE_)SMBIOS_PARSER) += sysinfo.o diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index b4d74a8fd8b..b5f83908771 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -72,7 +72,7 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void data_modul_imx_edm_sbc_early_init_f(const iomux_v3_cfg_t wdog_pad) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; diff --git a/board/data_modul/imx8mm_edm_sbc/Makefile b/board/data_modul/imx8mm_edm_sbc/Makefile index 6d72e930fca..3d8fedf74d4 100644 --- a/board/data_modul/imx8mm_edm_sbc/Makefile +++ b/board/data_modul/imx8mm_edm_sbc/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o else obj-y += imx8mm_data_modul_edm_sbc.o diff --git a/board/data_modul/imx8mp_edm_sbc/Makefile b/board/data_modul/imx8mp_edm_sbc/Makefile index 28c1d62f2bb..7e1fe855799 100644 --- a/board/data_modul/imx8mp_edm_sbc/Makefile +++ b/board/data_modul/imx8mp_edm_sbc/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o lpddr4_timing_4G_32.o else obj-y += imx8mp_data_modul_edm_sbc.o diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index 03c34455c50..dc42a4a7b53 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -311,7 +311,7 @@ int board_mmc_init(struct bd_info *bis) #endif #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static const struct ns16550_plat serial_pdata = { .base = DAVINCI_UART2_BASE, .reg_shift = 2, diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS b/board/dhelectronics/dh_imx6/MAINTAINERS index 8f9b5ff2dca..472e908e278 100644 --- a/board/dhelectronics/dh_imx6/MAINTAINERS +++ b/board/dhelectronics/dh_imx6/MAINTAINERS @@ -3,6 +3,5 @@ M: Andreas Geisreiter <ageisreiter@dh-electronics.de> M: Christoph Niedermaier <cniedermaier@dh-electronics.com> L: u-boot@dh-electronics.com S: Maintained -F: board/dhelectronics/dh_imx6/ -F: include/configs/dh_imx6.h -F: configs/dh_imx6_defconfig +N: imx6.*dh[cs]o +N: dh_imx6 diff --git a/board/dhelectronics/dh_imx6/Makefile b/board/dhelectronics/dh_imx6/Makefile index 70ca30d3971..7102a47450e 100644 --- a/board/dhelectronics/dh_imx6/Makefile +++ b/board/dhelectronics/dh_imx6/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2017 Marek Vasut <marex@denx.de> -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := dh_imx6_spl.o else obj-y := dh_imx6.o diff --git a/board/dhelectronics/dh_imx8mp/MAINTAINERS b/board/dhelectronics/dh_imx8mp/MAINTAINERS index db69781a852..cf9f77252c9 100644 --- a/board/dhelectronics/dh_imx8mp/MAINTAINERS +++ b/board/dhelectronics/dh_imx8mp/MAINTAINERS @@ -2,7 +2,5 @@ DH electronics DHCOM i.MX8M Plus and matching carrier boards M: Marek Vasut <marex@denx.de> L: u-boot@dh-electronics.com S: Maintained -F: arch/arm/dts/imx8mp-dhcom* -F: board/dhelectronics/dh_imx8mp/ -F: configs/imx8mp_dhcom*defconfig -F: include/configs/imx8mp_dhcom* +N: imx8mp.*dh[cs]o +N: dh_imx8mp diff --git a/board/dhelectronics/dh_imx8mp/Makefile b/board/dhelectronics/dh_imx8mp/Makefile index e5a29fdd122..7bc8dc21e64 100644 --- a/board/dhelectronics/dh_imx8mp/Makefile +++ b/board/dhelectronics/dh_imx8mp/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o else obj-y += imx8mp_dhcom_pdk2.o diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 24c5f37c12f..a975fd2978c 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -260,13 +260,13 @@ int board_stm32mp1_ddr_config_name_match(struct udevice *dev, void board_vddcore_init(u32 voltage_mv) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) opp_voltage_mv = voltage_mv; } int board_early_init_f(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) stpmic1_init(opp_voltage_mv); board_get_coding_straps(); @@ -765,7 +765,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image)); diff --git a/board/ea/mx7ulp_com/mx7ulp_com.c b/board/ea/mx7ulp_com/mx7ulp_com.c index 8f78937e097..d3a65fd820b 100644 --- a/board/ea/mx7ulp_com/mx7ulp_com.c +++ b/board/ea/mx7ulp_com/mx7ulp_com.c @@ -52,7 +52,7 @@ int board_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> #ifdef CONFIG_SPL_LOAD_FIT diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index 00f9a5ef341..16af687d9cc 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CFG_SYS_RTC_SCRATCH0 0x60 #define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CFG_SYS_RTC_SCRATCH0) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void save_boot_device(void) { *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device(); diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index cf3368c253b..5ed41d01d9b 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -394,7 +394,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> void board_init_f(ulong dummy) diff --git a/board/engicam/common/Makefile b/board/engicam/common/Makefile index 15f0eaa1ec4..dc8be383c23 100644 --- a/board/engicam/common/Makefile +++ b/board/engicam/common/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2016 Amarula Solutions B.V. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_IMX6_ENGICAM_COMMON) += spl.o else obj-$(CONFIG_IMX6_ENGICAM_COMMON) += board.o diff --git a/board/engicam/imx8mm/Makefile b/board/engicam/imx8mm/Makefile index 3392d61920a..d6ad299f830 100644 --- a/board/engicam/imx8mm/Makefile +++ b/board/engicam/imx8mm/Makefile @@ -6,7 +6,7 @@ obj-y += icore_mx8mm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += lpddr4_timing.o endif diff --git a/board/engicam/imx8mp/Makefile b/board/engicam/imx8mp/Makefile index c3ec09d6e38..f21a31b8078 100644 --- a/board/engicam/imx8mp/Makefile +++ b/board/engicam/imx8mp/Makefile @@ -6,7 +6,7 @@ obj-y += icore_mx8mp.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/engicam/stm32mp1/Makefile b/board/engicam/stm32mp1/Makefile index 155d33f9eec..9ac78e4d1aa 100644 --- a/board/engicam/stm32mp1/Makefile +++ b/board/engicam/stm32mp1/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += stm32mp1.o diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c index 8e67ab4b132..c65ce5890e5 100644 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ b/board/firefly/firefly-rk3288/firefly-rk3288.c @@ -9,7 +9,7 @@ #include <asm/global_data.h> #include <dm/ofnode.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static int setup_led(void) { #ifdef CONFIG_SPL_LED diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index a149e4fe822..6937a27176f 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -13,7 +13,7 @@ #include <asm/arch-rockchip/gpio.h> #include <asm/arch-rockchip/grf_rk3399.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define PMUGRF_BASE 0xff320000 #define GPIO0_BASE 0xff720000 diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index b4faf6f9e0a..c2c86c0dd08 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -5,7 +5,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y @@ -29,14 +29,14 @@ endif obj-$(CONFIG_FSL_CADMUS) += cadmus.o obj-$(CONFIG_FSL_VIA) += cds_via.o obj-$(CONFIG_FMAN_ENET) += fman.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o endif obj-$(I2C_COMMON) += i2c_common.o obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o -obj-$(CONFIG_$(SPL_)VID) += vid.o +obj-$(CONFIG_$(XPL_)VID) += vid.o obj-$(CONFIG_FSL_QIXIS) += qixis.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o endif ifndef CONFIG_RAMBOOT_PBL @@ -54,7 +54,7 @@ obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o -ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) +ifeq ($(CONFIG_$(XPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o endif obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index 3344653ba2d..7629d7091e9 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -23,7 +23,7 @@ loop: return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_esbc_validate(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 27a33924c84..194a0907e72 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -15,7 +15,7 @@ #include <dm/root.h> #include <asm/fsl_secure_boot.h> -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) #include <spl.h> #endif @@ -67,7 +67,7 @@ int fsl_check_boot_mode_secure(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int fsl_setenv_chain_of_trust(void) { /* Check Boot Mode @@ -92,7 +92,7 @@ int fsl_setenv_chain_of_trust(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) { int res; @@ -157,4 +157,4 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry(); } #endif /* ifdef CONFIG_SPL_FRAMEWORK */ -#endif /* ifdef CONFIG_SPL_BUILD */ +#endif /* ifdef CONFIG_XPL_BUILD */ diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 657f4533bcd..df0c1a1f406 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -396,7 +396,7 @@ static void fsl_secboot_bootscript_parse_failure(void) */ void fsl_secboot_handle_error(int error) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD const struct fsl_secboot_errcode *e; for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; @@ -807,7 +807,7 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) prop.num_bits = key_len * 8; prop.exp_len = key_len; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", NULL); if (ret) { printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret); diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 6400ac05245..7815ba2dbce 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -161,7 +161,7 @@ void board_deassert_mem_reset(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static void qixis_reset(void) { QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile index 1db7b62cafc..9fecd8dd8cb 100644 --- a/board/freescale/imx8mm_evk/Makefile +++ b/board/freescale/imx8mm_evk/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mm_evk.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile index 42d1179724d..5ef666a36dd 100644 --- a/board/freescale/imx8mn_evk/Makefile +++ b/board/freescale/imx8mn_evk/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mn_evk.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o diff --git a/board/freescale/imx8mp_evk/Makefile b/board/freescale/imx8mp_evk/Makefile index 106bf9a1edf..3c154d7f7f5 100644 --- a/board/freescale/imx8mp_evk/Makefile +++ b/board/freescale/imx8mp_evk/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mp_evk.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/freescale/imx8mq_evk/Makefile b/board/freescale/imx8mq_evk/Makefile index cf046963d25..ca449e6f369 100644 --- a/board/freescale/imx8mq_evk/Makefile +++ b/board/freescale/imx8mq_evk/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mq_evk.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o endif diff --git a/board/freescale/imx8qm_mek/Makefile b/board/freescale/imx8qm_mek/Makefile index bc9a1260bde..53b33a0dfb1 100644 --- a/board/freescale/imx8qm_mek/Makefile +++ b/board/freescale/imx8qm_mek/Makefile @@ -5,4 +5,4 @@ # obj-y += imx8qm_mek.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/freescale/imx8qxp_mek/Makefile b/board/freescale/imx8qxp_mek/Makefile index acaadcd84a4..459ec771eea 100644 --- a/board/freescale/imx8qxp_mek/Makefile +++ b/board/freescale/imx8qxp_mek/Makefile @@ -5,4 +5,4 @@ # obj-y += imx8qxp_mek.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/freescale/imx8ulp_evk/Makefile b/board/freescale/imx8ulp_evk/Makefile index 1cf148ab910..7819b2675b3 100644 --- a/board/freescale/imx8ulp_evk/Makefile +++ b/board/freescale/imx8ulp_evk/Makefile @@ -2,7 +2,7 @@ obj-y += imx8ulp_evk.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o ifdef CONFIG_IMX8ULP_ND_MODE obj-y += lpddr4_timing_264.o diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile index ede8d20ff5c..b077acc70a5 100644 --- a/board/freescale/imx93_evk/Makefile +++ b/board/freescale/imx93_evk/Makefile @@ -6,7 +6,7 @@ obj-y += imx93_evk.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o lpddr4x_timing_1866mts.o endif diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/board/freescale/imxrt1020-evk/imxrt1020-evk.c index 42a0a67ae93..11dbef84688 100644 --- a/board/freescale/imxrt1020-evk/imxrt1020-evk.c +++ b/board/freescale/imxrt1020-evk/imxrt1020-evk.c @@ -37,7 +37,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c index 46a644908e9..056489932ac 100644 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c @@ -37,7 +37,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { diff --git a/board/freescale/imxrt1170-evk/imxrt1170-evk.c b/board/freescale/imxrt1170-evk/imxrt1170-evk.c index e10b8830ec6..047aea8181a 100644 --- a/board/freescale/imxrt1170-evk/imxrt1170-evk.c +++ b/board/freescale/imxrt1170-evk/imxrt1170-evk.c @@ -37,7 +37,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index dae2cf097bc..f157e75e385 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -140,7 +140,7 @@ int dram_init(void) #endif mmdc_init(&mparam); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 7d56eb0117d..b21c4d917d0 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -88,7 +88,7 @@ int dram_init(void) mmdc_init(&mparam); gd->ram_size = CFG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 5f0564f1b23..ab69eab8408 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -138,7 +138,7 @@ int dram_init(void) #endif gd->ram_size = CFG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 2fdac87bc29..4eff0a3fee0 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -99,7 +99,7 @@ void ddrmc_init(void) int dram_init(void) { -#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) ddrmc_init(); #endif @@ -125,7 +125,7 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { /* Clear the BSS */ diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 5b0f23688f0..fd897e832c8 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -172,14 +172,14 @@ int fsl_initdram(void) { phys_size_t dram_size; -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) fsl_dp_resume(); #endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 930ef6be385..0bdd468d9a7 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -181,7 +181,7 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { #ifdef CONFIG_NAND_BOOT diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index b7e043b2e62..d1acccec110 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; static void ddrmc_init(void) { -#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; u32 temp_sdram_cfg, tmp; @@ -105,7 +105,7 @@ static void ddrmc_init(void) out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); } #endif -#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ +#endif /* !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) */ } int dram_init(void) @@ -116,7 +116,7 @@ int dram_init(void) gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) fsl_dp_resume(); #endif @@ -156,7 +156,7 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { void (*second_uboot)(void); @@ -214,7 +214,7 @@ int board_init(void) return 0; } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) void spl_board_init(void) { ls102xa_smmu_stream_id_init(); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 78006afce86..cc9665c0410 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -224,7 +224,7 @@ void ddrmc_init(void) int dram_init(void) { -#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) ddrmc_init(); #endif @@ -232,7 +232,7 @@ int dram_init(void) gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) fsl_dp_resume(); #endif @@ -407,7 +407,7 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { void (*second_uboot)(void); @@ -527,7 +527,7 @@ int board_init(void) return 0; } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) void spl_board_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { @@ -607,7 +607,7 @@ u16 flash_read16(void *addr) } #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \ - && !defined(CONFIG_SPL_BUILD) + && !defined(CONFIG_XPL_BUILD) static void convert_flash_bank(char bank) { struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index e01b5a8c2eb..db94d9c1fa8 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -123,7 +123,7 @@ int board_early_init_f(void) u8 uart; #endif -#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_XPL_BUILD) i2c_early_init_f(); #endif diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile index 49d8d7d9b96..ff830788fd7 100644 --- a/board/freescale/ls1043aqds/Makefile +++ b/board/freescale/ls1043aqds/Makefile @@ -5,7 +5,7 @@ # obj-y += ddr.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += eth.o endif obj-y += ls1043aqds.o diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 2a9717df616..137ad7395ad 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -123,7 +123,7 @@ int fsl_initdram(void) { phys_size_t dram_size; -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); return 0; diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 2ecf5a74a03..f043599fbb8 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -288,7 +288,7 @@ int dram_init(void) select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ - defined(CONFIG_SPL_BUILD) + defined(CONFIG_XPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile index 5309576c688..95745bf3a9c 100644 --- a/board/freescale/ls1043ardb/Makefile +++ b/board/freescale/ls1043ardb/Makefile @@ -4,7 +4,7 @@ obj-y += ddr.o obj-y += ls1043ardb.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_NET) += eth.o obj-y += cpld.o endif diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 187925e981a..231b60d1b3d 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -225,14 +225,14 @@ int fsl_initdram(void) phys_size_t dram_size; #ifdef CONFIG_SYS_DDR_RAW_TIMING -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif #else -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) puts("Initialzing DDR using fixed setting\n"); dram_size = fixed_sdram(); #else diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index cf84ff9e638..bba041065b5 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -132,7 +132,7 @@ int board_early_init_f(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int checkboard(void) { diff --git a/board/freescale/ls1046aqds/Makefile b/board/freescale/ls1046aqds/Makefile index 6267522cc26..365247d92bc 100644 --- a/board/freescale/ls1046aqds/Makefile +++ b/board/freescale/ls1046aqds/Makefile @@ -5,7 +5,7 @@ # obj-y += ddr.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += eth.o endif obj-y += ls1046aqds.o diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index ac1b6049721..57790335f0a 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -107,7 +107,7 @@ int fsl_initdram(void) { phys_size_t dram_size; -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); return 0; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index a83b2170651..7df12550868 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -284,7 +284,7 @@ int dram_init(void) select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ - defined(CONFIG_SPL_BUILD) + defined(CONFIG_XPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile index 1c13ed6b6f0..9e5d24f53c8 100644 --- a/board/freescale/ls1046ardb/Makefile +++ b/board/freescale/ls1046ardb/Makefile @@ -4,7 +4,7 @@ obj-y += ddr.o obj-y += ls1046ardb.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_NET) += eth.o obj-y += cpld.o endif diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index 68353022e7d..4170666c420 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -113,7 +113,7 @@ int fsl_initdram(void) { phys_size_t dram_size; -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); return 0; diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 0492f0a8c0a..83b280f7646 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -44,7 +44,7 @@ int board_early_init_f(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int checkboard(void) { static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index c2b0e7dc0f4..e54d6cad9e1 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -4,7 +4,7 @@ obj-y += ls1088a.o obj-y += ddr.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o endif diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c index 54b432ad794..cd590af9534 100644 --- a/board/freescale/ls1088a/ddr.c +++ b/board/freescale/ls1088a/ddr.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) { int vdd; @@ -101,7 +101,7 @@ found: popts->addr_hash = 1; popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); -#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) fsl_ddr_setup_0v9_volt(popts); #endif @@ -124,7 +124,7 @@ int fsl_initdram(void) { puts("Initializing DDR....using SPD\n"); -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); #else gd->ram_size = fsl_ddr_sdram(); diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 58951f2bb2a..9f4eb4811d9 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -248,7 +248,7 @@ int fixup_ls1088ardb_pb_banner(void *fdt) return 0; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) int checkboard(void) { #ifdef CONFIG_TFABOOT @@ -421,7 +421,7 @@ unsigned long get_board_ddr_clk(void) } #endif -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) void board_retimer_init(void) { u8 reg; @@ -804,7 +804,7 @@ exit: return ret; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) int board_init(void) { init_final_memctl_regs(); @@ -995,7 +995,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif -#endif /* defined(CONFIG_SPL_BUILD) */ +#endif /* defined(CONFIG_XPL_BUILD) */ #ifdef CONFIG_TFABOOT #ifdef CONFIG_MTD_NOR_FLASH diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index d19c061e122..31ed72c949b 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -168,7 +168,7 @@ int fsl_initdram(void) #else int fsl_initdram(void) { -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 4c8d0706688..aba0560181a 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -264,7 +264,7 @@ void detail_board_ddr_info(void) #endif } -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) void fdt_fixup_board_enet(void *fdt) { int offset; @@ -323,7 +323,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fsl_fdt_fixup_dr_usb(blob, bd); -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) fdt_fixup_board_enet(blob); fdt_reserve_mc_mem(blob, 0x300); #endif diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index a1a97f9f8c2..e56667c846f 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -173,7 +173,7 @@ int fsl_initdram(void) #else int fsl_initdram(void) { -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 7fc4fecf774..7d5beb32417 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_eth_init(struct bd_info *bis) { -#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD) /* * Export functions to be used by AQ firmware * upload application diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 3aa984dab8e..341f82ce724 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -58,7 +58,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { -#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_XPL_BUILD) i2c_early_init_f(); #endif diff --git a/board/freescale/mx23evk/Makefile b/board/freescale/mx23evk/Makefile index 6fe6992a5fc..5cc99ab1836 100644 --- a/board/freescale/mx23evk/Makefile +++ b/board/freescale/mx23evk/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y := mx23evk.o else obj-y := spl_boot.o diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile index 057760433da..1fd2a439f7a 100644 --- a/board/freescale/mx28evk/Makefile +++ b/board/freescale/mx28evk/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y := mx28evk.o else obj-y := iomux.o diff --git a/board/freescale/mx6memcal/Makefile b/board/freescale/mx6memcal/Makefile index fc2d3eb9e10..b4088b9f2ec 100644 --- a/board/freescale/mx6memcal/Makefile +++ b/board/freescale/mx6memcal/Makefile @@ -4,7 +4,7 @@ # # (C) Copyright 2011 Freescale Semiconductor, Inc. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := spl.o else obj-y := mx6memcal.o diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index bab62fd4421..8ca57e0b2ac 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -545,7 +545,7 @@ int board_ehci_hcd_init(int port) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <asm/arch/mx6-ddr.h> #include <spl.h> #include <linux/libfdt.h> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index bb066a5d36c..dff3a9c33bf 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -507,7 +507,7 @@ int board_late_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <asm/arch/mx6-ddr.h> #include <spl.h> #include <linux/libfdt.h> diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index d37d8a4136f..fb145fa6aac 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -61,7 +61,7 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static iomux_v3_cfg_t const usdhc1_pads[] = { /* 8 bit SD */ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -195,7 +195,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> #include <linux/libfdt.h> diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index e5a0197e2fd..c4ab59da78c 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -123,7 +123,7 @@ static int board_qspi_init(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ @@ -346,7 +346,7 @@ void board_preboot_os(void) gpio_set_value(IMX_GPIO_NR(5, 9), 0); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/mx6-ddr.h> diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile index a00806e6aae..df4e8001d38 100644 --- a/board/freescale/p1010rdb/Makefile +++ b/board/freescale/p1010rdb/Makefile @@ -4,7 +4,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y @@ -15,7 +15,7 @@ endif ifdef MINIMAL obj-y += spl_minimal.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o endif obj-y += p1010rdb.o diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index e386840d9ef..9b4b6f34f46 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -656,7 +656,7 @@ int misc_init_r(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 44acebaa2bb..aa130ccf78b 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index cbdb2507e83..8c13813e3b0 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -4,7 +4,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y @@ -15,7 +15,7 @@ endif ifdef MINIMAL obj-y += spl_minimal.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o endif obj-y += p1_p2_rdb_pc.o diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index ae0b7adbe54..f27821418eb 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -37,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile index e597486c940..b0f27c47191 100644 --- a/board/freescale/t102xrdb/Makefile +++ b/board/freescale/t102xrdb/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += t102xrdb.o diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index f8d504fb3c7..1a8a131cdcc 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -236,7 +236,7 @@ int dram_init(void) { phys_size_t dram_size; -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) #ifndef CONFIG_SYS_DDR_RAW_TIMING puts("Initializing....using SPD\n"); #endif @@ -248,7 +248,7 @@ int dram_init(void) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) fsl_dp_resume(); #endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 008bd6e72b7..8e99c2c7022 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -100,7 +100,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 11, BOOKE_PAGESZ_256K, 1), #endif -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index a9495019430..9bca1a1fbcc 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -2,7 +2,7 @@ # # Copyright 2013 Freescale Semiconductor, Inc. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += t104xrdb.o diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index bab684860da..6c066480b46 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -129,7 +129,7 @@ int dram_init(void) { phys_size_t dram_size; -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); #else @@ -138,7 +138,7 @@ int dram_init(void) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) fsl_dp_resume(); #endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 24bc83f756b..7b2183da8b0 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -38,7 +38,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), -#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_XPL_BUILD) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot * the physical address of the SRAM is at 0xbffc0000, @@ -66,7 +66,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -118,7 +118,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 11, BOOKE_PAGESZ_256K, 1), #endif -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index de8613058de..eb99d921b4a 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index 9076fbba10a..77c8ce0c870 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -109,7 +109,7 @@ int dram_init(void) { phys_size_t dram_size; -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); #else diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index a4cc532acda..08c140afc68 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -65,7 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -142,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile index 7af3cd0ac4c..e5ef250c8b2 100644 --- a/board/freescale/t208xrdb/Makefile +++ b/board/freescale/t208xrdb/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index fe98f62668a..cc9586eaa14 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -102,7 +102,7 @@ int dram_init(void) { phys_size_t dram_size; -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); #else diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index a9a03908dfb..a3f283548f3 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -65,7 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -141,7 +141,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index 3106848639c..8d94faaba1c 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index cd14d5895f5..f076350c1c5 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -94,7 +94,7 @@ static void cpld_dump_regs(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int rc = 0; diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index bbe31d4a54e..1ce70962264 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -111,7 +111,7 @@ int dram_init(void) puts("Initializing....using SPD\n"); -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); #else /* DDR has been initialised by first stage boot loader */ diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 1fb9d41d52b..7c58c14f3b6 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -51,7 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -114,7 +114,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 18, BOOKE_PAGESZ_2G, 1) diff --git a/board/gardena/smart-gateway-at91sam/Makefile b/board/gardena/smart-gateway-at91sam/Makefile index a2ed79fd06c..ac9e57938b3 100644 --- a/board/gardena/smart-gateway-at91sam/Makefile +++ b/board/gardena/smart-gateway-at91sam/Makefile @@ -2,6 +2,6 @@ obj-y += board.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o endif diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c index eb7fcd630a1..b6c0fe960ea 100644 --- a/board/gardena/smart-gateway-mt7688/board.c +++ b/board/gardena/smart-gateway-mt7688/board.c @@ -295,7 +295,7 @@ err_free: return ret; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD U_BOOT_CMD( fd_write, 1, 0, do_fd_write, "Write test factory-data values to SPI NOR", diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index c407f8e6c54..08859a963d0 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -7,4 +7,4 @@ # obj-y := gw_ventana.o eeprom.o common.o -obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o +obj-$(CONFIG_XPL_BUILD) += gw_ventana_spl.o diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index b37f1972249..447862dfee1 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -327,7 +327,7 @@ struct ventana_eeprom_config econfig[] = { { /* Sentinel */ } }; -#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_XPL_BUILD) static struct ventana_eeprom_config *get_config(const char *name) { struct ventana_eeprom_config *cfg = econfig; diff --git a/board/gateworks/venice/Makefile b/board/gateworks/venice/Makefile index faf1348cfa9..ab69e07ba7b 100644 --- a/board/gateworks/venice/Makefile +++ b/board/gateworks/venice/Makefile @@ -6,7 +6,7 @@ obj-y += venice.o eeprom.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o ifdef CONFIG_IMX8MM obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_imx8mm.o diff --git a/board/gdsys/a38x/Makefile b/board/gdsys/a38x/Makefile index 4b13859fed1..2713633730f 100644 --- a/board/gdsys/a38x/Makefile +++ b/board/gdsys/a38x/Makefile @@ -6,6 +6,6 @@ obj-$(CONFIG_TARGET_CONTROLCENTERDC) += controlcenterdc.o hre.o keyprogram.o dt_helpers.o -ifeq ($(CONFIG_SPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD),) obj-$(CONFIG_TARGET_CONTROLCENTERDC) += hydra.o ihs_phys.o endif diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index 4abb3e45128..659dfddecea 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -84,7 +84,7 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) void spl_board_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD uint k; struct gpio_desc gpio = {}; @@ -139,7 +139,7 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) int board_early_init_f(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Configure MPP */ writel(0x00111111, MVEBU_MPP_BASE + 0x00); writel(0x40040000, MVEBU_MPP_BASE + 0x04); @@ -174,7 +174,7 @@ int board_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD void init_host_phys(struct mii_dev *bus) { uint k; @@ -241,7 +241,7 @@ int ccdc_eth_init(void) int board_late_init(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD hydra_initialize(); #endif return 0; @@ -272,13 +272,13 @@ int board_fix_fdt(void *rw_fdt_blob) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int last_stage_init(void) { struct udevice *tpm; int ret; - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return 0; ccdc_eth_init(); diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index 031773bc5ef..c1aacd1458b 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define B1X5V2_GE_VPD_OFFSET 0x0100000 #define B1X5V2_GE_VPD_SIZE 1022 @@ -695,4 +695,4 @@ U_BOOT_CMD( "" ); -#endif // CONFIG_SPL_BUILD +#endif // CONFIG_XPL_BUILD diff --git a/board/ge/b1x5v2/spl.c b/board/ge/b1x5v2/spl.c index 460d3be1d83..b6f23345acd 100644 --- a/board/ge/b1x5v2/spl.c +++ b/board/ge/b1x5v2/spl.c @@ -20,7 +20,7 @@ #include <spi_flash.h> #include <spl.h> -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <asm/arch/mx6-ddr.h> diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index 7b2724c01d0..3443dc91885 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -147,7 +147,7 @@ static int coral_get_str(struct udevice *dev, int id, size_t size, char *val) { int ret; - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return -ENOSYS; switch (id) { diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c index e08cb42c27e..f3a1a19f2b6 100644 --- a/board/google/gru/gru.c +++ b/board/google/gru/gru.c @@ -7,7 +7,7 @@ #include <init.h> #include <asm/arch-rockchip/clock.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* provided to defeat compiler optimisation in board_init_f() */ void gru_dummy_function(int i) { @@ -33,7 +33,7 @@ int board_early_init_f(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int board_early_init_r(void) { struct udevice *clk; diff --git a/board/google/imx8mq_phanbell/Makefile b/board/google/imx8mq_phanbell/Makefile index d6427cf8e90..ac6418e49a7 100644 --- a/board/google/imx8mq_phanbell/Makefile +++ b/board/google/imx8mq_phanbell/Makefile @@ -5,7 +5,7 @@ obj-y += imx8mq_phanbell.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1g.o endif diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 674f19ba03c..a38f7125648 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -19,7 +19,7 @@ * There is a U-Boot driver for this but it may need to add support for the * 'voltage-table' property. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) static int veyron_init(void) { diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index e0eb8aa9f2b..d5491d5076f 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -104,7 +104,7 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index 07bb5b7d797..c2a44b4aa2d 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -229,7 +229,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_boot_order(u32 *spl_boot_list) { struct src *psrc = (struct src *)SRC_BASE_ADDR; diff --git a/board/htc/endeavoru/Makefile b/board/htc/endeavoru/Makefile index 0c6ba4af3b1..57f84d6ea98 100644 --- a/board/htc/endeavoru/Makefile +++ b/board/htc/endeavoru/Makefile @@ -6,6 +6,6 @@ # (C) Copyright 2021 # Svyatoslav Ryhel <clamor95@gmail.com> -obj-$(CONFIG_SPL_BUILD) += endeavoru-spl.o +obj-$(CONFIG_XPL_BUILD) += endeavoru-spl.o obj-y += endeavoru.o diff --git a/board/htc/endeavoru/endeavoru-spl.c b/board/htc/endeavoru/endeavoru-spl.c index 3c4caff8069..33ff72be273 100644 --- a/board/htc/endeavoru/endeavoru-spl.c +++ b/board/htc/endeavoru/endeavoru-spl.c @@ -9,13 +9,12 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/board.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/tegra_i2c.h> +#include <spl_gpio.h> #include <linux/delay.h> /* @@ -35,24 +34,6 @@ #define TPS80032_SMPS1_CFG_STATE_DATA (0x0100 | TPS80032_SMPS1_CFG_STATE_REG) #define TPS80032_SMPS2_CFG_STATE_DATA (0x0100 | TPS80032_SMPS2_CFG_STATE_REG) -#define TEGRA_GPIO_PS0 144 - -void pmic_enable_cpu_vdd(void) -{ - /* Set VDD_CORE to 1.200V. */ - tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS2_CFG_VOLTAGE_DATA); - udelay(1000); - tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS2_CFG_STATE_DATA); - - udelay(1000); - - /* Bring up VDD_CPU to 1.0125V. */ - tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS1_CFG_VOLTAGE_DATA); - udelay(1000); - tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA); - udelay(10 * 1000); -} - /* * Unlike all other supported Tegra devices and most known Tegra devices, the * HTC One X has no hardware way to enter APX/RCM mode, which may lead to a @@ -65,15 +46,13 @@ void pmic_enable_cpu_vdd(void) * proposed to add the RCM rebooting hook as early into SPL as possible since * SPL is much more robust and has minimal changes that can break bootflow. * - * gpio_early_init_uart() function was chosen as it is the earliest function + * pmic_enable_cpu_vdd() function was chosen as it is the earliest function * exposed for setup by the device. Hook performs a check for volume up * button state and triggers RCM if it is pressed. */ -void gpio_early_init_uart(void) +void apx_hook(void) { - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(TEGRA_GPIO_PS0)]; - u32 value; + int value; /* Configure pinmux */ pinmux_set_func(PMUX_PINGRP_KB_ROW8_PS0, PMUX_FUNC_KBC); @@ -81,19 +60,8 @@ void gpio_early_init_uart(void) pinmux_tristate_disable(PMUX_PINGRP_KB_ROW8_PS0); pinmux_set_io(PMUX_PINGRP_KB_ROW8_PS0, PMUX_PIN_INPUT); - /* Configure GPIO direction as input. */ - value = readl(&bank->gpio_dir_out[GPIO_PORT(TEGRA_GPIO_PS0)]); - value &= ~(1 << GPIO_BIT(TEGRA_GPIO_PS0)); - writel(value, &bank->gpio_dir_out[GPIO_PORT(TEGRA_GPIO_PS0)]); - - /* Enable the pin as a GPIO */ - value = readl(&bank->gpio_config[GPIO_PORT(TEGRA_GPIO_PS0)]); - value |= 1 << GPIO_BIT(TEGRA_GPIO_PS0); - writel(value, &bank->gpio_config[GPIO_PORT(TEGRA_GPIO_PS0)]); - - /* Get GPIO value */ - value = readl(&bank->gpio_in[GPIO_PORT(TEGRA_GPIO_PS0)]); - value = (value >> GPIO_BIT(TEGRA_GPIO_PS0)) & 1; + spl_gpio_input(NULL, TEGRA_GPIO(S, 0)); + value = spl_gpio_get_value(NULL, TEGRA_GPIO(S, 0)); /* Enter RCM if button is pressed */ if (!value) { @@ -101,3 +69,22 @@ void gpio_early_init_uart(void) tegra_pmc_writel(PMC_CNTRL_MAIN_RST, PMC_CNTRL); } } + +void pmic_enable_cpu_vdd(void) +{ + /* Check if RCM request is active */ + apx_hook(); + + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS2_CFG_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS2_CFG_STATE_DATA); + + udelay(1000); + + /* Bring up VDD_CPU to 1.0125V. */ + tegra_i2c_ll_write(TPS80032_DVS_I2C_ADDR, TPS80032_SMPS1_CFG_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS80032_CTL1_I2C_ADDR, TPS80032_SMPS1_CFG_STATE_DATA); + udelay(10 * 1000); +} diff --git a/board/htc/endeavoru/endeavoru.env b/board/htc/endeavoru/endeavoru.env new file mode 100644 index 00000000000..53e9b568454 --- /dev/null +++ b/board/htc/endeavoru/endeavoru.env @@ -0,0 +1,13 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_2=update bootloader=run flash_uboot +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c index 4e268381d3c..3e9833d684f 100644 --- a/board/imgtec/ci20/ci20.c +++ b/board/imgtec/ci20/ci20.c @@ -39,7 +39,7 @@ static void ci20_mux_mmc(void) jz4780_clk_ungate_mmc(); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static void ci20_mux_eth(void) { @@ -251,7 +251,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if defined(CONFIG_SPL_MMC) int board_mmc_init(struct bd_info *bd) diff --git a/board/isee/igep003x/Makefile b/board/isee/igep003x/Makefile index c3e39745252..02ec0ccbdb2 100644 --- a/board/isee/igep003x/Makefile +++ b/board/isee/igep003x/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += mux.o endif diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 7cd26ce3c34..162467c803a 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -68,7 +68,7 @@ static int get_board_revision(void) return revision; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/ static const struct ddr_data ddr3_igep0034_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile index e095bcada29..527748cdadd 100644 --- a/board/isee/igep00x0/Makefile +++ b/board/isee/igep00x0/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := spl.o common.o else obj-y := igep00x0.o common.o diff --git a/board/k+p/kp_imx6q_tpc/Makefile b/board/k+p/kp_imx6q_tpc/Makefile index 6551b2bfa2d..6444628c649 100644 --- a/board/k+p/kp_imx6q_tpc/Makefile +++ b/board/k+p/kp_imx6q_tpc/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := kp_imx6q_tpc_spl.o else obj-y := kp_imx6q_tpc.o diff --git a/board/kontron/pitx_imx8m/Makefile b/board/kontron/pitx_imx8m/Makefile index 6ebe5d07709..50ca56f4efd 100644 --- a/board/kontron/pitx_imx8m/Makefile +++ b/board/kontron/pitx_imx8m/Makefile @@ -2,7 +2,7 @@ obj-y += pitx_imx8m.o pitx_misc.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o pitx_misc.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_2gb.o lpddr4_timing_4gb.o endif diff --git a/board/kontron/sl-mx6ul/Makefile b/board/kontron/sl-mx6ul/Makefile index 6af5f65450a..dfed1991ee7 100644 --- a/board/kontron/sl-mx6ul/Makefile +++ b/board/kontron/sl-mx6ul/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2018 Kontron Electronics GmbH -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := spl.o else obj-y := sl-mx6ul.o diff --git a/board/kontron/sl-mx8mm/Makefile b/board/kontron/sl-mx8mm/Makefile index fceed684ede..b47fafc5733 100644 --- a/board/kontron/sl-mx8mm/Makefile +++ b/board/kontron/sl-mx8mm/Makefile @@ -3,7 +3,7 @@ obj-y := sl-mx8mm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile index 084c11da376..2cb41251708 100644 --- a/board/kontron/sl28/Makefile +++ b/board/kontron/sl28/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += sl28.o cmds.o endif @@ -8,7 +8,7 @@ obj-y += common.o ddr.o obj-$(CONFIG_ARMV8_PSCI) += psci.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_SPL_ATF) += spl_atf.o endif diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index 9b881fdc265..1f1a6aa1b16 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -98,7 +98,7 @@ int fsl_initdram(void) break; } - if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_XPL_BUILD)) fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); gd->ram_size = dram_size; diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile index 64d32f5a963..fdcd8b5f422 100644 --- a/board/kosagi/novena/Makefile +++ b/board/kosagi/novena/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2014 Marek Vasut <marex@denx.de> -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := novena_spl.o else obj-y := novena.o diff --git a/board/lenovo/ideapad-yoga-11/Makefile b/board/lenovo/ideapad-yoga-11/Makefile index 186f1cb4ee5..fd9736d1bf1 100644 --- a/board/lenovo/ideapad-yoga-11/Makefile +++ b/board/lenovo/ideapad-yoga-11/Makefile @@ -3,4 +3,4 @@ # (C) Copyright 2022 # Open Surface RT -obj-$(CONFIG_SPL_BUILD) += ideapad-yoga-11-spl.o +obj-$(CONFIG_XPL_BUILD) += ideapad-yoga-11-spl.o diff --git a/board/lenovo/ideapad-yoga-11/ideapad-yoga-11.env b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11.env new file mode 100644 index 00000000000..7bc2b80c480 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11.env @@ -0,0 +1,16 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +button_cmd_1_name=Lid sensor +button_cmd_1=poweroff +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run update_spi +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c index 9d0959f294e..d4db32ee69b 100644 --- a/board/lg/sniper/sniper.c +++ b/board/lg/sniper/sniper.c @@ -54,7 +54,7 @@ void set_muxconf_regs(void) MUX_SNIPER(); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void get_board_mem_timings(struct board_sdrc_timings *timings) { timings->mcfg = HYNIX_V_MCFG_200(256 << 20); diff --git a/board/lg/x3-t30/Makefile b/board/lg/x3-t30/Makefile index 3eeb132f3c6..fb2527f9ee8 100644 --- a/board/lg/x3-t30/Makefile +++ b/board/lg/x3-t30/Makefile @@ -6,6 +6,6 @@ # (C) Copyright 2021 # Svyatoslav Ryhel <clamor95@gmail.com> -obj-$(CONFIG_SPL_BUILD) += x3-t30-spl.o +obj-$(CONFIG_XPL_BUILD) += x3-t30-spl.o obj-y += x3-t30.o diff --git a/board/lg/x3-t30/configs/p880.config b/board/lg/x3-t30/configs/p880.config index 57c2885779b..44e0fa7ef77 100644 --- a/board/lg/x3-t30/configs/p880.config +++ b/board/lg/x3-t30/configs/p880.config @@ -1,3 +1,4 @@ +CONFIG_ENV_SOURCE_FILE="p880" CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880" CONFIG_SYS_PROMPT="Tegra30 (P880) # " CONFIG_VIDEO_LCD_RENESAS_R69328=y diff --git a/board/lg/x3-t30/configs/p895.config b/board/lg/x3-t30/configs/p895.config index 2eba92594b5..267ae3a80d0 100644 --- a/board/lg/x3-t30/configs/p895.config +++ b/board/lg/x3-t30/configs/p895.config @@ -1,3 +1,4 @@ +CONFIG_ENV_SOURCE_FILE="p895" CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p895" CONFIG_SYS_PROMPT="Tegra30 (P895) # " CONFIG_VIDEO_LCD_RENESAS_R61307=y diff --git a/board/lg/x3-t30/p880.env b/board/lg/x3-t30/p880.env new file mode 100644 index 00000000000..f2bf298a997 --- /dev/null +++ b/board/lg/x3-t30/p880.env @@ -0,0 +1,15 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/lg/x3-t30/p895.env b/board/lg/x3-t30/p895.env new file mode 100644 index 00000000000..53e9b568454 --- /dev/null +++ b/board/lg/x3-t30/p895.env @@ -0,0 +1,13 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_2=update bootloader=run flash_uboot +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/board/libre-computer/aml-a311d-cc/MAINTAINERS b/board/libre-computer/aml-a311d-cc/MAINTAINERS new file mode 100644 index 00000000000..b4b77acd23b --- /dev/null +++ b/board/libre-computer/aml-a311d-cc/MAINTAINERS @@ -0,0 +1,7 @@ +LIBRE-COMPUTER AML-A311D-CC +M: Neil Armstrong <neil.armstrong@linaro.org> +S: Maintained +L: u-boot-amlogic@groups.io +F: board/amlogic/aml-a311d-cc/ +F: configs/aml-a311d-cc_defconfig +F: doc/board/amlogic/aml-a311d-cc.rst diff --git a/board/libre-computer/aml-a311d-cc/Makefile b/board/libre-computer/aml-a311d-cc/Makefile new file mode 100644 index 00000000000..461955def3a --- /dev/null +++ b/board/libre-computer/aml-a311d-cc/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> + +obj-y := aml-a311d-cc.o diff --git a/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c b/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c new file mode 100644 index 00000000000..e45cfd5d8a3 --- /dev/null +++ b/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <dm.h> +#include <env.h> +#include <init.h> +#include <net.h> +#include <efi_loader.h> +#include <asm/io.h> +#include <asm/arch/eth.h> + +struct efi_fw_image fw_images[] = { + { + .fw_name = u"AML_A311D_CC_BOOT", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "sf 0:0=u-boot-bin raw 0 0x10000", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (strcmp(interface, "ram") == 0) + env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000"); + else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + +int misc_init_r(void) +{ + meson_generate_serial_ethaddr(); + + return 0; +} diff --git a/board/libre-computer/aml-s805x-ac/MAINTAINERS b/board/libre-computer/aml-s805x-ac/MAINTAINERS new file mode 100644 index 00000000000..7cbc08aeb6c --- /dev/null +++ b/board/libre-computer/aml-s805x-ac/MAINTAINERS @@ -0,0 +1,8 @@ +LIBRE-COMPUTER AML-S805X-AC +M: Neil Armstrong <neil.armstrong@linaro.org> +S: Maintained +L: u-boot-amlogic@groups.io +F: board/amlogic/aml-s805x-ac/ +F: include/configs/libretech-ac.h +F: configs/libretech-ac_defconfig +F: doc/board/amlogic/libretech-ac.rst diff --git a/board/libre-computer/aml-s805x-ac/Makefile b/board/libre-computer/aml-s805x-ac/Makefile new file mode 100644 index 00000000000..b4367ea522b --- /dev/null +++ b/board/libre-computer/aml-s805x-ac/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> + +obj-y := aml-s805x-ac.o diff --git a/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c b/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c new file mode 100644 index 00000000000..94cf5b4361f --- /dev/null +++ b/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <dm.h> +#include <env.h> +#include <init.h> +#include <net.h> +#include <efi_loader.h> +#include <asm/io.h> +#include <asm/arch/gx.h> +#include <asm/arch/sm.h> +#include <asm/arch/eth.h> +#include <asm/arch/mem.h> + +#define EFUSE_SN_OFFSET 20 +#define EFUSE_SN_SIZE 16 +#define EFUSE_MAC_OFFSET 52 +#define EFUSE_MAC_SIZE 6 + +struct efi_fw_image fw_images[] = { + { + .fw_name = u"AML_S805X_AC_BOOT", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "sf 0:0=u-boot-bin raw 0 0x10000", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (strcmp(interface, "ram") == 0) + env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000"); + else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + +int misc_init_r(void) +{ + u8 mac_addr[EFUSE_MAC_SIZE + 1]; + char serial[EFUSE_SN_SIZE + 1]; + ssize_t len; + + if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { + len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, + mac_addr, EFUSE_MAC_SIZE); + mac_addr[len] = '\0'; + if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); + else + meson_generate_serial_ethaddr(); + } + + if (!env_get("serial#")) { + len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, + EFUSE_SN_SIZE); + serial[len] = '\0'; + if (len == EFUSE_SN_SIZE) + env_set("serial#", serial); + } + + return 0; +} diff --git a/board/libre-computer/aml-s905d3-cc/MAINTAINERS b/board/libre-computer/aml-s905d3-cc/MAINTAINERS new file mode 100644 index 00000000000..4b75c815c07 --- /dev/null +++ b/board/libre-computer/aml-s905d3-cc/MAINTAINERS @@ -0,0 +1,7 @@ +LIBRE-COMPUTER AML-S905D3-CC +M: Neil Armstrong <neil.armstrong@linaro.org> +S: Maintained +L: u-boot-amlogic@groups.io +F: board/amlogic/aml-s905d3-cc/ +F: configs/aml-s905d3-cc_defconfig +F: doc/board/amlogic/aml-s905d3-cc.rst diff --git a/board/libre-computer/aml-s905d3-cc/Makefile b/board/libre-computer/aml-s905d3-cc/Makefile new file mode 100644 index 00000000000..7d2c41e6436 --- /dev/null +++ b/board/libre-computer/aml-s905d3-cc/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> + +obj-y := aml-s905d3-cc.o diff --git a/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c b/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c new file mode 100644 index 00000000000..f641db5a494 --- /dev/null +++ b/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <dm.h> +#include <env.h> +#include <init.h> +#include <net.h> +#include <efi_loader.h> +#include <asm/io.h> +#include <asm/arch/eth.h> + +struct efi_fw_image fw_images[] = { + { + .fw_name = u"AML_S905D3_CC_BOOT", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "sf 0:0=u-boot-bin raw 0 0x10000", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + + +#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO) +void set_dfu_alt_info(char *interface, char *devstr) +{ + if (strcmp(interface, "ram") == 0) + env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000"); + else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + env_set("dfu_alt_info", update_info.dfu_string); +} +#endif + +int misc_init_r(void) +{ + meson_generate_serial_ethaddr(); + + return 0; +} diff --git a/board/liebherr/display5/Makefile b/board/liebherr/display5/Makefile index ee503add75d..c62583a9806 100644 --- a/board/liebherr/display5/Makefile +++ b/board/liebherr/display5/Makefile @@ -4,7 +4,7 @@ # # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y = spl.o else obj-y := display5.o diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile index 3c9786c6b7d..d5fdc2011b0 100644 --- a/board/liebherr/mccmon6/Makefile +++ b/board/liebherr/mccmon6/Makefile @@ -2,7 +2,7 @@ # # (C) Copyright 2016-2017 # Lukasz Majewski, DENX Software Engineering, lukma@denx.de -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := spl.o else obj-y := mccmon6.o diff --git a/board/liebherr/xea/Makefile b/board/liebherr/xea/Makefile index abf500857f6..6efa07ca004 100644 --- a/board/liebherr/xea/Makefile +++ b/board/liebherr/xea/Makefile @@ -7,6 +7,6 @@ obj-y := xea.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl_xea.o endif diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 9ade3563b25..1d4f165fd13 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -37,7 +37,7 @@ #include <spi.h> #include <spi_flash.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> #endif @@ -62,7 +62,7 @@ static void init_clocks(void) mxs_set_sspclk(MXC_SSPCLK3, 96000, 0); } -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) void board_init_f(ulong arg) { init_clocks(); @@ -355,4 +355,4 @@ U_BOOT_DRIVER(fsl_imx28_clkctrl) = { .id = UCLASS_CLK, .of_match = imx28_clk_ids, }; -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index e6ca31016b7..e4f619d0942 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGMACSS_SW_RST (1 << 1) #define PHY_GPIO 30 -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #if defined(CONFIG_SPL_OS_BOOT) int spl_start_uboot(void) { diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 589136fd64a..652994df616 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -135,7 +135,7 @@ int board_late_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6q-ddr.h> #include <spl.h> diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index a9fe61918b6..352b519b451 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -68,7 +68,7 @@ int spl_start_uboot(void) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index 79351f47273..fc76d5765fa 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -524,7 +524,7 @@ int checkboard(void) /* * NAND SPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { setup_iomux_nand(); diff --git a/board/menlo/mx8menlo/Makefile b/board/menlo/mx8menlo/Makefile index fd5ec826336..62939395ba1 100644 --- a/board/menlo/mx8menlo/Makefile +++ b/board/menlo/mx8menlo/Makefile @@ -9,13 +9,13 @@ obj-y := mx8menlo.o obj-y += ../../toradex/verdin-imx8mm/verdin-imx8mm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += ../../toradex/verdin-imx8mm/spl.o obj-$(CONFIG_IMX8M_LPDDR4) += ../../toradex/verdin-imx8mm/lpddr4_timing.o endif # Common for all Toradex modules -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) # Necessary to create built-in.o obj- := __dummy__.o else diff --git a/board/microsoft/surface-rt/Makefile b/board/microsoft/surface-rt/Makefile index da4094a7df3..feda1dba3bd 100644 --- a/board/microsoft/surface-rt/Makefile +++ b/board/microsoft/surface-rt/Makefile @@ -3,4 +3,4 @@ # (C) Copyright 2021 # Open Surface RT -obj-$(CONFIG_SPL_BUILD) += surface-rt-spl.o +obj-$(CONFIG_XPL_BUILD) += surface-rt-spl.o diff --git a/board/microsoft/surface-rt/surface-rt.env b/board/microsoft/surface-rt/surface-rt.env new file mode 100644 index 00000000000..682929096ae --- /dev/null +++ b/board/microsoft/surface-rt/surface-rt.env @@ -0,0 +1,14 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +button_cmd_1_name=Hall Sensor +button_cmd_1=poweroff +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=boot from USB=usb reset; usb start; bootflow scan +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile index 2efd56bb4ad..2772c8dc717 100644 --- a/board/mntre/imx8mq_reform2/Makefile +++ b/board/mntre/imx8mq_reform2/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mq_reform2.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/msc/sm2s_imx8mp/Makefile b/board/msc/sm2s_imx8mp/Makefile index 7908a0ceb04..48dc885b8f6 100644 --- a/board/msc/sm2s_imx8mp/Makefile +++ b/board/msc/sm2s_imx8mp/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0 # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o lpddr4_timing.o else obj-y += sm2s_imx8mp.o diff --git a/board/myir/mys_6ulx/Makefile b/board/myir/mys_6ulx/Makefile index 3c63e439aba..9b76595701e 100644 --- a/board/myir/mys_6ulx/Makefile +++ b/board/myir/mys_6ulx/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := mys_6ulx.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile index 5e9e70825c7..d56c7151af6 100644 --- a/board/nvidia/beaver/Makefile +++ b/board/nvidia/beaver/Makefile @@ -2,6 +2,6 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -obj-$(CONFIG_SPL_BUILD) += beaver-spl.o +obj-$(CONFIG_XPL_BUILD) += beaver-spl.o obj-y = ../cardhu/cardhu.o diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile index 6f480cdfd3b..85d88295c08 100644 --- a/board/nvidia/cardhu/Makefile +++ b/board/nvidia/cardhu/Makefile @@ -3,6 +3,6 @@ # (C) Copyright 2010-2012 # NVIDIA Corporation <www.nvidia.com> -obj-$(CONFIG_SPL_BUILD) += cardhu-spl.o +obj-$(CONFIG_XPL_BUILD) += cardhu-spl.o obj-y += cardhu.o diff --git a/board/nvidia/cardhu/cardhu.env b/board/nvidia/cardhu/cardhu.env new file mode 100644 index 00000000000..9d1e3e1da2d --- /dev/null +++ b/board/nvidia/cardhu/cardhu.env @@ -0,0 +1,2 @@ +board_name=cardhu-a04 +fdtfile=tegra30-cardhu-a04.dtb diff --git a/board/nvidia/p2771-0000/p2771-0000.env b/board/nvidia/p2771-0000/p2771-0000.env new file mode 100644 index 00000000000..6789cc1cc63 --- /dev/null +++ b/board/nvidia/p2771-0000/p2771-0000.env @@ -0,0 +1,22 @@ +calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r ramdisk_addr_r + +kernel_addr_r_align=00200000 +kernel_addr_r_offset=00080000 +kernel_addr_r_size=02000000 +kernel_addr_r_aliases=loadaddr + +fdt_addr_r_align=00200000 +fdt_addr_r_offset=00000000 +fdt_addr_r_size=00200000 + +scriptaddr_align=00200000 +scriptaddr_offset=00000000 +scriptaddr_size=00200000 + +pxefile_addr_r_align=00200000 +pxefile_addr_r_offset=00000000 +pxefile_addr_r_size=00200000 + +ramdisk_addr_r_align=00200000 +ramdisk_addr_r_offset=00000000 +ramdisk_addr_r_size=02000000 diff --git a/board/nvidia/p3450-0000/p3450-0000.env b/board/nvidia/p3450-0000/p3450-0000.env new file mode 100644 index 00000000000..f21d2fc463e --- /dev/null +++ b/board/nvidia/p3450-0000/p3450-0000.env @@ -0,0 +1,7 @@ +/* Only MMC/PXE/DHCP for now, add USB back in later when supported */ +boot_targets=mmc1 mmc0 pxe dhcp + +preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then + load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; + source ${scriptaddr}; + fi diff --git a/board/olimex/mx23_olinuxino/Makefile b/board/olimex/mx23_olinuxino/Makefile index b2ea8974344..0a6beb10ded 100644 --- a/board/olimex/mx23_olinuxino/Makefile +++ b/board/olimex/mx23_olinuxino/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y := mx23_olinuxino.o else obj-y := spl_boot.o diff --git a/board/opalkelly/zynq/Makefile b/board/opalkelly/zynq/Makefile index 19e893e43d7..8a2375a1068 100644 --- a/board/opalkelly/zynq/Makefile +++ b/board/opalkelly/zynq/Makefile @@ -4,4 +4,4 @@ obj-y := board.o hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) -obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o +obj-$(CONFIG_XPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 04469d0a924..cd78f7686fe 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -2,7 +2,7 @@ # Copyright (C) 2023 PHYTEC Messtechnik GmbH # Author: Teresa Remmet <t.remmet@phytec.de> -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD # necessary to create built-in.o obj- := __dummy__.o endif diff --git a/board/phytec/pcl063/Makefile b/board/phytec/pcl063/Makefile index 53c73c9b082..0f17eb466c5 100644 --- a/board/phytec/pcl063/Makefile +++ b/board/phytec/pcl063/Makefile @@ -4,4 +4,4 @@ # obj-y := pcl063.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index ecc5b75d8d4..4a95376b359 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -108,7 +108,7 @@ int board_late_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> #include <linux/libfdt.h> diff --git a/board/phytec/phycore_am335x_r2/Makefile b/board/phytec/phycore_am335x_r2/Makefile index 16ac38fd8be..4f865ab9e10 100644 --- a/board/phytec/phycore_am335x_r2/Makefile +++ b/board/phytec/phycore_am335x_r2/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += mux.o endif diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index 2022525651d..a2a488a0e30 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 9f6bc736cbb..a0e098e010e 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -182,7 +182,7 @@ int do_board_detect(void) } #endif -#if IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { u64 start[CONFIG_NR_DRAM_BANKS]; diff --git a/board/phytec/phycore_imx8mm/Makefile b/board/phytec/phycore_imx8mm/Makefile index 27f6c027b6c..2fb59761fc9 100644 --- a/board/phytec/phycore_imx8mm/Makefile +++ b/board/phytec/phycore_imx8mm/Makefile @@ -5,7 +5,7 @@ obj-y += phycore-imx8mm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/phytec/phycore_imx8mp/Makefile b/board/phytec/phycore_imx8mp/Makefile index c4c434c9475..8cf1f4dcea3 100644 --- a/board/phytec/phycore_imx8mp/Makefile +++ b/board/phytec/phycore_imx8mp/Makefile @@ -5,7 +5,7 @@ obj-y += phycore-imx8mp.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/phytec/phycore_imx93/Makefile b/board/phytec/phycore_imx93/Makefile index ce35326a156..dd5085e160f 100644 --- a/board/phytec/phycore_imx93/Makefile +++ b/board/phytec/phycore_imx93/Makefile @@ -9,6 +9,6 @@ obj-y += phycore-imx93.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o lpddr4_timing.o endif diff --git a/board/polyhex/imx8mp_debix_model_a/Makefile b/board/polyhex/imx8mp_debix_model_a/Makefile index e5cdc850878..3d50c7af4af 100644 --- a/board/polyhex/imx8mp_debix_model_a/Makefile +++ b/board/polyhex/imx8mp_debix_model_a/Makefile @@ -7,7 +7,7 @@ obj-y += imx8mp_debix_model_a.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/purism/librem5/Makefile b/board/purism/librem5/Makefile index 47f25f047b7..4514add3a5b 100644 --- a/board/purism/librem5/Makefile +++ b/board/purism/librem5/Makefile @@ -7,7 +7,7 @@ obj-y += librem5.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o endif diff --git a/board/purism/librem5/librem5.h b/board/purism/librem5/librem5.h index 0d24edea9b1..69475a5b063 100644 --- a/board/purism/librem5/librem5.h +++ b/board/purism/librem5/librem5.h @@ -57,7 +57,7 @@ /* Could be ASPEN, BIRCH or CHESTNUT. assume CHESTNUT */ #define BOARD_REV_UNKNOWN BOARD_REV_CHESTNUT -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static const iomux_v3_cfg_t configure_pads[] = { IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(PAD_CTL_DSE6), IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, @@ -151,7 +151,7 @@ static inline void init_pinmux(void) gpio_direction_output(AUDIO_EN, 1); gpio_direction_output(DSI_EN, 1); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define USB1_BASE_ADDR 0x38100000 #define USB2_BASE_ADDR 0x38200000 diff --git a/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c index a533128b92f..fd827467b30 100644 --- a/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c +++ b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c @@ -18,7 +18,7 @@ struct efi_capsule_update_info update_info = { #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) static bool board_is_rockpi_4b(void) { @@ -55,4 +55,4 @@ void rockchip_capsule_update_board_setup(void) } } #endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */ -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile index 53418699b27..f9c131fc6cd 100644 --- a/board/renesas/alt/Makefile +++ b/board/renesas/alt/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0 # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := alt_spl.o else obj-y := alt.o qos.o diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile index 19e6038430b..cb965cde35f 100644 --- a/board/renesas/condor/Makefile +++ b/board/renesas/condor/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := ../rcar-common/common.o diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile index 1fc90d1dab4..8859cf902ca 100644 --- a/board/renesas/draak/Makefile +++ b/board/renesas/draak/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := draak.o ../rcar-common/common.o diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile index 9fb6a7c0f0a..98164b5ea29 100644 --- a/board/renesas/eagle/Makefile +++ b/board/renesas/eagle/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile index 956ce8a90fa..283d3a4ae36 100644 --- a/board/renesas/ebisu/Makefile +++ b/board/renesas/ebisu/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := ../rcar-common/common.o diff --git a/board/renesas/falcon/Makefile b/board/renesas/falcon/Makefile index 3b202c24fb1..2e240d3bad6 100644 --- a/board/renesas/falcon/Makefile +++ b/board/renesas/falcon/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := falcon.o ../rcar-common/common.o diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile index c6a1dc21cda..2c45bd74014 100644 --- a/board/renesas/gose/Makefile +++ b/board/renesas/gose/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0 # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := gose_spl.o else obj-y := gose.o qos.o diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile index 77cf067406c..1b0818fa7ec 100644 --- a/board/renesas/koelsch/Makefile +++ b/board/renesas/koelsch/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0 # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := koelsch_spl.o else obj-y := koelsch.o qos.o diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile index 379368fdfce..77e380f9335 100644 --- a/board/renesas/lager/Makefile +++ b/board/renesas/lager/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0 # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := lager_spl.o else obj-y := lager.o qos.o diff --git a/board/renesas/porter/Makefile b/board/renesas/porter/Makefile index c237ee5ec77..9f22044bc79 100644 --- a/board/renesas/porter/Makefile +++ b/board/renesas/porter/Makefile @@ -7,7 +7,7 @@ # SPDX-License-Identifier: GPL-2.0 # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := porter_spl.o else obj-y := porter.o qos.o diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile index 95258079e40..0fc69ba9de6 100644 --- a/board/renesas/salvator-x/Makefile +++ b/board/renesas/salvator-x/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := salvator-x.o ../rcar-common/common.o diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile index b5c3ad8d934..48dd7dbb8be 100644 --- a/board/renesas/silk/Makefile +++ b/board/renesas/silk/Makefile @@ -7,7 +7,7 @@ # SPDX-License-Identifier: GPL-2.0 # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := silk_spl.o else obj-y := silk.o qos.o diff --git a/board/renesas/stout/Makefile b/board/renesas/stout/Makefile index b8875bb7b98..e1bca5339b9 100644 --- a/board/renesas/stout/Makefile +++ b/board/renesas/stout/Makefile @@ -8,7 +8,7 @@ # SPDX-License-Identifier: GPL-2.0 # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := stout_spl.o else obj-y := stout.o cpld.o qos.o diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile index f4d24c68a67..ec2f161feae 100644 --- a/board/renesas/ulcb/Makefile +++ b/board/renesas/ulcb/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := ulcb.o cpld.o ../rcar-common/common.o diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile index a9d597edd58..b29114c7239 100644 --- a/board/renesas/v3hsk/Makefile +++ b/board/renesas/v3hsk/Makefile @@ -7,7 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile index ec493e572f1..f8c4bcdcf9f 100644 --- a/board/renesas/v3msk/Makefile +++ b/board/renesas/v3msk/Makefile @@ -7,7 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../rcar-common/gen3-spl.o else obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o diff --git a/board/ronetix/imx7-cm/Makefile b/board/ronetix/imx7-cm/Makefile index 7e08f238a0d..1ca6332852f 100644 --- a/board/ronetix/imx7-cm/Makefile +++ b/board/ronetix/imx7-cm/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2017 NXP Semiconductors -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += imx7-cm.o diff --git a/board/ronetix/imx8mq-cm/Makefile b/board/ronetix/imx8mq-cm/Makefile index 0d9d8e646db..4ca2a96d81e 100644 --- a/board/ronetix/imx8mq-cm/Makefile +++ b/board/ronetix/imx8mq-cm/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mq_cm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index d31b81abf1e..abecef8be11 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_USB_GADGET_DOWNLOAD) += gadget.o obj-$(CONFIG_MISC_COMMON) += misc.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_BOARD_COMMON) += board.o sromc.o ifdef CONFIG_EXYNOS5_DT obj-y += exynos5-dt.o diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index 44691af09f4..940f689a601 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2011 Samsung Electronics -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD # necessary to create built-in.o obj- := __dummy__.o diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile index fccd8ffd2c1..b7f9d5a254c 100644 --- a/board/samsung/smdkv310/Makefile +++ b/board/samsung/smdkv310/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2011 Samsung Electronics -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD # necessary to create built-in.o obj- := __dummy__.o diff --git a/board/seeed/npi_imx6ull/Makefile b/board/seeed/npi_imx6ull/Makefile index 93ea413517d..bd8f83148bb 100644 --- a/board/seeed/npi_imx6ull/Makefile +++ b/board/seeed/npi_imx6ull/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := npi_imx6ull.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/sielaff/imx6dl-sielaff/Makefile b/board/sielaff/imx6dl-sielaff/Makefile index 65cecfe6f6c..9c8bab662e4 100644 --- a/board/sielaff/imx6dl-sielaff/Makefile +++ b/board/sielaff/imx6dl-sielaff/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2022 Kontron Electronics GmbH -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := spl.o else obj-y := imx6dl-sielaff.o diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile index 4dafac10829..e8a24c448b9 100644 --- a/board/siemens/capricorn/Makefile +++ b/board/siemens/capricorn/Makefile @@ -6,7 +6,7 @@ obj-y += board.o obj-y += ../common/eeprom.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += ../common/factoryset.o diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 53dac8bfe1b..ad474d9baa0 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -235,7 +235,7 @@ void reset_cpu(void) { } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* LED's */ static int board_led_init(void) { @@ -265,7 +265,7 @@ static int board_led_init(void) mdelay(1); return ret; } -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ int checkboard(void) { @@ -335,7 +335,7 @@ void board_late_mmc_env_init(void) run_command(cmd, 0); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int load_parameters_from_factoryset(void) { int ret; @@ -443,4 +443,4 @@ U_BOOT_CMD( "Reset eth phy", "[print]" ); -#endif /* ! CONFIG_SPL_BUILD */ +#endif /* ! CONFIG_XPL_BUILD */ diff --git a/board/siemens/common/board_am335x.c b/board/siemens/common/board_am335x.c index e6537b0675a..daf0bb930ec 100644 --- a/board/siemens/common/board_am335x.c +++ b/board/siemens/common/board_am335x.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -52,9 +52,9 @@ void sdram_init(void) return; } -#endif /* #ifdef CONFIG_SPL_BUILD */ +#endif /* #ifdef CONFIG_XPL_BUILD */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Basic board specific setup. Pinmux has been handled already. */ @@ -78,7 +78,7 @@ int board_init(void) return 0; } -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif /* #ifndef CONFIG_XPL_BUILD */ #define OSC (V_OSCK/1000000) const struct dpll_params dpll_ddr = { @@ -89,7 +89,7 @@ const struct dpll_params *get_dpll_ddr_params(void) return &dpll_ddr; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define MAX_NR_LEDS 10 #define MAX_PIN_NUMBER 128 @@ -247,4 +247,4 @@ U_BOOT_CMD( "Set LEDs defined in environment", "<0|1>" ); -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/board/siemens/common/board_am335x.h b/board/siemens/common/board_am335x.h index 3a20352d457..4c9d5b04f12 100644 --- a/board/siemens/common/board_am335x.h +++ b/board/siemens/common/board_am335x.h @@ -22,7 +22,7 @@ void spl_draco_board_init(void); void draco_init_ddr(void); int draco_read_eeprom(void); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Mux for init: uart?, i2c0 to read the main EEPROM */ void enable_uart0_pin_mux(void); void enable_uart1_pin_mux(void); @@ -34,6 +34,6 @@ void enable_i2c0_pin_mux(void); /* Main mux function to enable other pinmux required on the board */ void enable_board_pin_mux(void); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #endif /* _BOARD_AM335X_H_ */ diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c index a250ccfe252..8261b3d37cc 100644 --- a/board/siemens/common/factoryset.c +++ b/board/siemens/common/factoryset.c @@ -5,7 +5,7 @@ * (C) Copyright 2013 Siemens Schweiz AG */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #include <env.h> #include <g_dnl.h> @@ -350,4 +350,4 @@ int g_dnl_get_board_bcd_device_number(int gcnum) { return factory_dat.version; } -#endif /* defined(CONFIG_SPL_BUILD) */ +#endif /* defined(CONFIG_XPL_BUILD) */ diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index cd27fc1cc37..a8714e055d7 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -114,7 +114,7 @@ static void corvus_nand_hw_init(void) at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <spl.h> #include <nand.h> diff --git a/board/siemens/draco/Makefile b/board/siemens/draco/Makefile index aae536472c5..ac59c5bd985 100644 --- a/board/siemens/draco/Makefile +++ b/board/siemens/draco/Makefile @@ -9,13 +9,13 @@ # u-boot:/board/ti/am335x/Makefile # Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := mux.o endif obj-y += board.o obj-y += ../common/board_am335x.o obj-y += ../common/eeprom.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += ../common/factoryset.o endif diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index fc3eb06ccf2..147f827673b 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -28,7 +28,7 @@ #include "../common/eeprom.h" #include "../common/factoryset.h" -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static struct draco_baseboard_id __section(".data") settings; #if DDR_PLL_FREQ == 303 @@ -106,7 +106,7 @@ static void print_chip_data(void) printf("hw version: \t'%s'\n", settings.chip.shwver); printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define AM335X_NAND_ECC_MASK 0x0f #define AM335X_NAND_ECC_TYPE_16 0x02 @@ -142,7 +142,7 @@ static int draco_read_nand_geometry(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * Read header information from EEPROM into global structure. */ @@ -233,7 +233,7 @@ void spl_draco_board_init(void) { return; } -#endif /* if def CONFIG_SPL_BUILD */ +#endif /* if def CONFIG_XPL_BUILD */ #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) @@ -266,8 +266,8 @@ int board_late_init(void) } #endif -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)) static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -343,4 +343,4 @@ U_BOOT_CMD( "" ); #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ -#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) */ diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile index aae536472c5..ac59c5bd985 100644 --- a/board/siemens/pxm2/Makefile +++ b/board/siemens/pxm2/Makefile @@ -9,13 +9,13 @@ # u-boot:/board/ti/am335x/Makefile # Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := mux.o endif obj-y += board.o obj-y += ../common/board_am335x.o obj-y += ../common/eeprom.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += ../common/factoryset.o endif diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 888c7c09baf..4f9611372cd 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -28,7 +28,7 @@ #include "../common/eeprom.h" #include "../common/factoryset.h" -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void draco_init_ddr(void) { struct emif_regs pxm2_ddr3_emif_reg_data = { @@ -154,10 +154,10 @@ int draco_read_eeprom(void) return 0; } -#endif /* if def CONFIG_SPL_BUILD */ +#endif /* if def CONFIG_XPL_BUILD */ -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)) static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -198,15 +198,15 @@ static struct cpsw_platform_data cpsw_data = { .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, }; -#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) */ #if defined(CONFIG_DRIVER_TI_CPSW) || \ (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) int board_eth_init(struct bd_info *bis) { int n = 0; -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)) struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifdef CONFIG_FACTORYSET int rv; diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile index aae536472c5..ac59c5bd985 100644 --- a/board/siemens/rut/Makefile +++ b/board/siemens/rut/Makefile @@ -9,13 +9,13 @@ # u-boot:/board/ti/am335x/Makefile # Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := mux.o endif obj-y += board.o obj-y += ../common/board_am335x.o obj-y += ../common/eeprom.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += ../common/factoryset.o endif diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 8d316918e7a..828ae5c27a0 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -24,7 +24,7 @@ #include "../common/eeprom.h" #include "../common/factoryset.h" -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * Read header information from EEPROM into global structure. */ @@ -116,7 +116,7 @@ void spl_draco_board_init(void) REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO); REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO); } -#endif /* if def CONFIG_SPL_BUILD */ +#endif /* if def CONFIG_XPL_BUILD */ #if defined(CONFIG_DRIVER_TI_CPSW) static void cpsw_control(int enabled) @@ -168,7 +168,7 @@ int board_eth_init(struct bd_info *bis) int n = 0; int rv; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD factoryset_env_set(); #endif @@ -183,7 +183,7 @@ int board_eth_init(struct bd_info *bis) return n; } #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ -#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) */ #if defined(CONFIG_HW_WATCHDOG) static bool hw_watchdog_init_done; diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index e9e4bc348cb..6fa3ca573ae 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -191,7 +191,7 @@ int board_eth_init(struct bd_info *bis) #endif /* CONFIG_MACB */ #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <spl.h> #include <nand.h> #include <spi_flash.h> diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 3764ab48ab3..252b0787124 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -79,7 +79,7 @@ static void taurus_nand_hw_init(void) at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <spl.h> #include <nand.h> #include <spi_flash.h> @@ -331,7 +331,7 @@ int dram_init(void) return 0; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_BOARD_AXM) /* * Booting the Fallback Image. diff --git a/board/sifive/unleashed/Makefile b/board/sifive/unleashed/Makefile index 98e9111cbcc..d0a156d2cab 100644 --- a/board/sifive/unleashed/Makefile +++ b/board/sifive/unleashed/Makefile @@ -2,7 +2,7 @@ # # Copyright (c) 2019 Western Digital Corporation or its affiliates. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += unleashed.o diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile index 13453300896..ce9deed9cdc 100644 --- a/board/sifive/unmatched/Makefile +++ b/board/sifive/unmatched/Makefile @@ -4,7 +4,7 @@ obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += unmatched.o diff --git a/board/silinux/ek874/Makefile b/board/silinux/ek874/Makefile index 4c8f0925f1e..6917a2418ca 100644 --- a/board/silinux/ek874/Makefile +++ b/board/silinux/ek874/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y := ../../renesas/rcar-common/gen3-spl.o else obj-y := ek874.o ../../renesas/rcar-common/common.o diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index bd430cfaa7f..769f3e2ff2a 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -402,7 +402,7 @@ void board_preboot_os(void) setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/mx6-ddr.h> diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index 2483fbcf263..ec2c7ea3631 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -43,7 +43,7 @@ int board_late_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int misc_init_r(void) { uchar data[128]; diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 3406ba8616e..e9269ef5353 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -570,7 +570,7 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[1] = BOOT_DEVICE_BOARD; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <asm/arch/mx6-ddr.h> static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { .dram_sdclk_0 = 0x00020030, diff --git a/board/st/common/Makefile b/board/st/common/Makefile index b01245e4b48..fda48d2ff99 100644 --- a/board/st/common/Makefile +++ b/board/st/common/Makefile @@ -8,7 +8,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o ifeq ($(CONFIG_ARCH_STM32MP),y) obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o -obj-$(CONFIG_$(SPL_)DFU_VIRT) += stm32mp_dfu_virt.o +obj-$(CONFIG_$(XPL_)DFU_VIRT) += stm32mp_dfu_virt.o endif obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c index 50da063051b..b9d0abdba7d 100644 --- a/board/st/common/cmd_stboard.c +++ b/board/st/common/cmd_stboard.c @@ -29,7 +29,7 @@ * Board: MB<Board> Var<VarCPN>.<VarFG> Rev.<Revision>-<BOM> */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #include <command.h> #include <console.h> #include <misc.h> diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 6d86e4fe7aa..8966a09501e 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int rv; struct udevice *dev; rv = uclass_get_device(UCLASS_RAM, 0, &dev); @@ -45,7 +45,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile index f2d720b67b3..5e39b7b189f 100644 --- a/board/st/stm32mp1/Makefile +++ b/board/st/stm32mp1/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o else obj-y += stm32mp1.o diff --git a/board/starfive/visionfive2/Makefile b/board/starfive/visionfive2/Makefile index c7ba4f7ed67..97c25a2fd13 100644 --- a/board/starfive/visionfive2/Makefile +++ b/board/starfive/visionfive2/Makefile @@ -4,5 +4,5 @@ # obj-y := starfive_visionfive2.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 4ad77c75f5e..84799879e85 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -132,6 +132,11 @@ M: Paul Kocialkowski <contact@paulk.fr> S: Maintained F: configs/Ampe_A76_defconfig +ANBERNIC RG35XX-2024 +M: Chris Morgan <macromorgan@hotmail.com> +S: Maintained +F: configs/anbernic_rg35xx_h700_defconfig + BANANAPI M1 PLUS M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 961cdcde74d..824c322a0dc 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -281,7 +281,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_XPL_BUILD) static void nand_pinmux_setup(void) { unsigned int pin; @@ -530,7 +530,7 @@ int mmc_get_env_dev(void) #endif #endif /* CONFIG_MMC */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void sunxi_spl_store_dram_size(phys_addr_t dram_size) { @@ -641,7 +641,7 @@ void sunxi_board_init(void) else printf("Failed to set core voltage! Can't set CPU frequency\n"); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #ifdef CONFIG_USB_GADGET int g_dnl_board_usb_cable_connected(void) diff --git a/board/tcl/sl50/Makefile b/board/tcl/sl50/Makefile index 0ac0ba36cdb..1502990174b 100644 --- a/board/tcl/sl50/Makefile +++ b/board/tcl/sl50/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ -ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index 6c60c70b7b4..20fa61131cb 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -249,8 +249,8 @@ int board_late_init(void) } #endif -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)) static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -303,10 +303,10 @@ static struct cpsw_platform_data cpsw_data = { * when we build an SPL that has neither option but full U-Boot will. */ #if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \ - && defined(CONFIG_SPL_BUILD)) || \ + && defined(CONFIG_XPL_BUILD)) || \ ((defined(CONFIG_DRIVER_TI_CPSW) || \ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) + !defined(CONFIG_XPL_BUILD)) int board_eth_init(struct bd_info *bis) { int rv, n = 0; @@ -323,8 +323,8 @@ int board_eth_init(struct bd_info *bis) mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)) if (!env_get("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); @@ -373,7 +373,7 @@ int board_eth_init(struct bd_info *bis) #endif #if defined(CONFIG_USB_ETHER) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) + (!defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) if (is_valid_ether_addr(mac_addr)) eth_env_set_enetaddr("usbnet_devaddr", mac_addr); diff --git a/board/technexion/pico-imx6/spl.c b/board/technexion/pico-imx6/spl.c index 50f51774264..700abb73289 100644 --- a/board/technexion/pico-imx6/spl.c +++ b/board/technexion/pico-imx6/spl.c @@ -24,7 +24,7 @@ #include <asm/arch/sys_proto.h> #include <spl.h> -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <asm/arch/mx6-ddr.h> #define IMX6DQ_DRIVE_STRENGTH 0x30 diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c index 67484e62dad..5b91868ba9c 100644 --- a/board/technexion/pico-imx6ul/spl.c +++ b/board/technexion/pico-imx6ul/spl.c @@ -18,7 +18,7 @@ #include <linux/libfdt.h> #include <spl.h> -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index 8f219f76c60..cb60d3be420 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -21,7 +21,7 @@ #include <fsl_esdhc_imx.h> #include <spl.h> -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) diff --git a/board/technexion/pico-imx8mq/Makefile b/board/technexion/pico-imx8mq/Makefile index 7cfe1e02ef9..da3073cdf79 100644 --- a/board/technexion/pico-imx8mq/Makefile +++ b/board/technexion/pico-imx8mq/Makefile @@ -6,7 +6,7 @@ obj-y += pico-imx8mq.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1gb.o lpddr4_timing_2gb.o lpddr4_timing_3gb.o lpddr4_timing_4gb.o endif diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index d7234532fe6..2f5ad769b9b 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -10,7 +10,7 @@ #include <init.h> #include <net.h> #include <pci.h> -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #include <bootcount.h> #endif #include <asm/global_data.h> @@ -252,7 +252,7 @@ int board_eth_init(struct bd_info *bis) } #endif -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT) int board_late_init(void) { pci_dev_t bdf; @@ -343,7 +343,7 @@ int board_late_init(void) } #endif -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_PCI) static int pcie_get_link_speed_width(pci_dev_t bdf, int *speed, int *width) { struct udevice *dev; diff --git a/board/theobroma-systems/jaguar_rk3588/Makefile b/board/theobroma-systems/jaguar_rk3588/Makefile index 532aab01532..d43bf194b68 100644 --- a/board/theobroma-systems/jaguar_rk3588/Makefile +++ b/board/theobroma-systems/jaguar_rk3588/Makefile @@ -5,6 +5,6 @@ # obj-y += jaguar_rk3588.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-y += ../common/common.o endif diff --git a/board/theobroma-systems/puma_rk3399/Makefile b/board/theobroma-systems/puma_rk3399/Makefile index edd61a35c1e..2256e72cda1 100644 --- a/board/theobroma-systems/puma_rk3399/Makefile +++ b/board/theobroma-systems/puma_rk3399/Makefile @@ -5,6 +5,6 @@ # obj-y += puma-rk3399.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-y += ../common/common.o endif diff --git a/board/theobroma-systems/ringneck_px30/Makefile b/board/theobroma-systems/ringneck_px30/Makefile index 45cc65baf9a..4d108f2d011 100644 --- a/board/theobroma-systems/ringneck_px30/Makefile +++ b/board/theobroma-systems/ringneck_px30/Makefile @@ -5,6 +5,6 @@ # obj-y += ringneck-px30.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-y += ../common/common.o endif diff --git a/board/theobroma-systems/tiger_rk3588/Makefile b/board/theobroma-systems/tiger_rk3588/Makefile index 5c4c484657a..94b0859eb35 100644 --- a/board/theobroma-systems/tiger_rk3588/Makefile +++ b/board/theobroma-systems/tiger_rk3588/Makefile @@ -5,6 +5,6 @@ # obj-y += tiger_rk3588.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-y += ../common/common.o endif diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index 2b1e21a1788..6ef87c22eaa 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ -ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 681002ba1da..720bf2cb3e1 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -569,8 +569,8 @@ void sdram_init(void) } #endif -#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))) +#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_XPL_BUILD) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))) static void request_and_set_gpio(int gpio, char *name, int val) { int ret; @@ -707,8 +707,8 @@ int board_init(void) gpmc_init(); #endif -#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))) +#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_XPL_BUILD) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))) if (board_is_icev2()) { int rv; u32 reg; @@ -798,7 +798,7 @@ int board_init(void) int board_late_init(void) { struct udevice *dev; -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; #endif @@ -847,7 +847,7 @@ int board_late_init(void) env_set("boot_fit", "1"); #endif -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile index b618f632eff..5b7b5b371a4 100644 --- a/board/ti/am43xx/Makefile +++ b/board/ti/am43xx/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ -ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index cc5e64c9879..fc0d87daae4 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -515,7 +515,7 @@ int get_voltrail_opp(int rail_offset) return opp; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* No env to setup for SPL */ static inline void setup_board_eeprom_env(void) { } @@ -538,7 +538,7 @@ void do_board_detect(void) #endif } -#else /* CONFIG_SPL_BUILD */ +#else /* CONFIG_XPL_BUILD */ /* Override function to read eeprom information: actual i2c read done by SPL*/ void do_board_detect(void) @@ -616,7 +616,7 @@ invalid_eeprom: set_board_info_env(name); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ void vcores_init(void) { @@ -783,7 +783,7 @@ int board_late_init(void) if (board_is_bbai()) env_set("console", "ttyS0,115200n8"); -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) board_ti_set_ethaddr(2); #endif @@ -935,7 +935,7 @@ const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) } #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) int spl_start_uboot(void) { /* break into full u-boot on 'c' */ diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 9bdd0223cdb..1166c9b8e09 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -103,7 +103,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) void spl_board_init(void) { diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 609e5cf6d51..00b8317d6bf 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -105,7 +105,7 @@ int board_fit_config_name_match(const char *name) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #if CONFIG_IS_ENABLED(USB_STORAGE) static int fixup_usb_boot(const void *fdt_blob) { diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index ea21d48bbc0..a43cc075b92 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -304,7 +304,7 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr) struct ti_common_eeprom *ep; ep = TI_EEPROM_DATA; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD if (ep->header == TI_EEPROM_HEADER_MAGIC) return 0; /* EEPROM has already been read */ #endif @@ -350,7 +350,7 @@ int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr) struct ti_common_eeprom *ep; ep = TI_EEPROM_DATA; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD if (ep->header == DRA7_EEPROM_HEADER_MAGIC) return 0; /* EEPROM has already been read */ #endif @@ -563,7 +563,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get_base(int bus_addr, int dev_addr) * Always execute EEPROM read by not allowing to bypass it during the * first invocation of SPL which happens on the R5 core. */ -#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_CPU_V7R)) +#if !(defined(CONFIG_XPL_BUILD) && defined(CONFIG_CPU_V7R)) if (ep->header == TI_EEPROM_HEADER_MAGIC) { debug("%s: EEPROM has already been read\n", __func__); return 0; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 2b1db2541b0..98d63e14e29 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -713,7 +713,7 @@ int board_late_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void do_board_detect(void) { int rc; @@ -756,7 +756,7 @@ void do_board_detect(void) snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, "Board: %s REV %s\n", bname, board_ti_get_rev()); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ void vcores_init(void) { @@ -972,7 +972,7 @@ const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) } #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) int spl_start_uboot(void) { /* break into full u-boot on 'c' */ diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index f3452ff0a8f..6221be9dcff 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -164,7 +164,7 @@ static void __maybe_unused detect_enable_hyperflash(void *blob) } #endif -#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \ +#if defined(CONFIG_XPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \ defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM)) void spl_perform_fixups(struct spl_image_info *spl_image) { @@ -340,7 +340,7 @@ static int probe_daughtercards(void) printf("Detected: %s rev %s\n", ep.name, ep.version); daughter_card_detect_flags[i] = true; - if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { int j; /* * Populate any MAC addresses from daughtercard into the U-Boot @@ -359,7 +359,7 @@ static int probe_daughtercards(void) } } - if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { char name_overlays[1024] = { 0 }; for (i = 0; i < ARRAY_SIZE(ext_cards); i++) { diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 5a0281d6b48..2cfeb3bec6c 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -239,7 +239,7 @@ static int probe_daughtercards(void) printf("Detected: %s rev %s\n", ep.name, ep.version); daughter_card_detect_flags[i] = true; - if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { int j; /* * Populate any MAC addresses from daughtercard into the U-Boot @@ -257,7 +257,7 @@ static int probe_daughtercards(void) } } - if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { char name_overlays[1024] = { 0 }; for (i = 0; i < ARRAY_SIZE(ext_cards); i++) { diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index c6735d37dda..48547719012 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -75,7 +75,7 @@ int board_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { spl_init_keystone_plls(); diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 4385be4221b..3ccf70c5ac7 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -109,7 +109,7 @@ int board_early_init_f(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_init_keystone_plls(void) { init_plls(); diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index d07b77d23e2..b1142ed5e96 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -346,7 +346,7 @@ int embedded_dtb_select(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT) int rc; rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, @@ -382,7 +382,7 @@ int board_early_init_f(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_init_keystone_plls(void) { init_plls(); diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 2b5d2d75664..93249fa5f49 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -116,7 +116,7 @@ int board_fit_config_name_match(const char *name) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_init_keystone_plls(void) { init_plls(); diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 1971bc94f7d..b813f21b682 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -104,7 +104,7 @@ int board_fit_config_name_match(const char *name) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_init_keystone_plls(void) { init_plls(); diff --git a/board/ti/omap3evm/evm.c b/board/ti/omap3evm/evm.c index 4eb08add256..8803643b032 100644 --- a/board/ti/omap3evm/evm.c +++ b/board/ti/omap3evm/evm.c @@ -117,7 +117,7 @@ int spl_start_uboot(void) } #endif /* CONFIG_SPL_OS_BOOT */ -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header @@ -150,7 +150,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->mr = MICRON_V_MR_165; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* * Routine: misc_init_r diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index ad404f7e9c4..a2a3a9489aa 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -147,7 +147,7 @@ void board_mmc_power_init(void) } #endif -#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_XPL_BUILD) /* * Routine: board_eth_init * Description: Setting up the Ethernet hardware. diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile index cc100b0f422..23a6dd86441 100644 --- a/board/topic/zynq/Makefile +++ b/board/topic/zynq/Makefile @@ -6,4 +6,4 @@ obj-y += ../../xilinx/common/board.o # Remove quotes hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) -obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o +obj-$(CONFIG_XPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o diff --git a/board/toradex/apalis-tk1/apalis-tk1.env b/board/toradex/apalis-tk1/apalis-tk1.env new file mode 100644 index 00000000000..9c2d9a92f0b --- /dev/null +++ b/board/toradex/apalis-tk1/apalis-tk1.env @@ -0,0 +1,45 @@ +/* + * Custom Boot configuration: + * 1. 8bit SD port (MMC1) + * 2. 4bit SD port (MMC2) + * 3. eMMC (MMC0) + */ +boot_targets=mmc1 mmc2 mmc0 usb pxe dhcp + +boot_file=zImage +boot_script_dhcp=boot.scr +console=ttyS0 +defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 + usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 + user_debug=30 pcie_aspm=off +dfu_alt_info=apalis-tk1.img raw 0x0 0x500 mmcpart 1; + boot part 0 1 mmcpart 0; + rootfs part 0 2 mmcpart 0; + zImage fat 0 1 mmcpart 0; + tegra124-apalis-eval.dtb fat 0 1 mmcpart 0 +fdt_board=eval +fdt_fixup=; +fdt_module=apalis-v1.2 +uboot_hwpart=1 +uboot_blk=0 +set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && + setexpr blkcnt ${blkcnt} / 0x200 +update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && + mmc write ${loadaddr} ${uboot_blk} ${blkcnt} +setethupdate=if env exists ethaddr; then; else setenv ethaddr + 00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} + flash_eth.img && source ${loadaddr} +setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; + load ${interface} ${drive}:1 ${loadaddr} flash_blk.img + || setenv drive 2; mmc rescan; load ${interface} ${drive}:1 + ${loadaddr} flash_blk.img && + source ${loadaddr} +setup=setenv setupargs igb_mac=${ethaddr} + consoleblank=0 no_console_suspend=1 console=tty1 + console=${console},${baudrate}n8 debug_uartport=lsport,0 + ${memargs} +setupdate=run setsdupdate || run setusbupdate || run setethupdate +setusbupdate=usb start && setenv interface usb; setenv drive 0; + load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && + source ${loadaddr} +vidargs=fbcon=map:1 diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 4a1cfb89345..ec0f223c4aa 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -96,7 +96,7 @@ iomux_v3_cfg_t const uart1_pads_dte[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD) /* Apalis MMC1 */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -139,7 +139,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION, }; -#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */ +#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */ int mx6_rgmii_rework(struct phy_device *phydev) { @@ -321,7 +321,7 @@ int board_ehci_hcd_init(int port) } #endif -#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD) /* use the following sequence: eMMC, MMC1, SD1 */ struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, @@ -391,7 +391,7 @@ int board_mmc_init(struct bd_info *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } -#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */ +#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */ int board_phy_config(struct phy_device *phydev) { @@ -748,7 +748,7 @@ void ldo_mode_set(int ldo_bypass) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> #include <linux/libfdt.h> #include "asm/arch/mx6q-ddr.h" @@ -1042,7 +1042,7 @@ void reset_cpu(void) { } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ static struct mxc_serial_plat mxc_serial_plat = { .reg = (struct mxc_uart *)UART1_BASE, diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c index b404b01e032..698b05bc5ad 100644 --- a/board/toradex/apalis_imx6/do_fuse.c +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -7,7 +7,7 @@ * Helpers for i.MX OTP fusing during module production */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #include <command.h> #include <console.h> #include <fuse.h> @@ -94,4 +94,4 @@ U_BOOT_CMD( "OTP fusing during module update", "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing" ); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c index 157aaec6fe0..7ea9bbb07ed 100644 --- a/board/toradex/apalis_imx6/pf0100.c +++ b/board/toradex/apalis_imx6/pf0100.c @@ -212,7 +212,7 @@ unsigned pmic_init(void) return programmed; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int pf0100_prog(void) { int rc; @@ -280,4 +280,4 @@ U_BOOT_CMD( "Program the OTP fuses on the PMIC PF0100", "" ); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile index eed607043fc..2d079004c4b 100644 --- a/board/toradex/apalis_t30/Makefile +++ b/board/toradex/apalis_t30/Makefile @@ -1,6 +1,6 @@ # Copyright (c) 2014 Marcel Ziswiler # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += apalis_t30-spl.o +obj-$(CONFIG_XPL_BUILD) += apalis_t30-spl.o obj-y += apalis_t30.o diff --git a/board/toradex/apalis_t30/apalis_t30.env b/board/toradex/apalis_t30/apalis_t30.env new file mode 100644 index 00000000000..a8f2904bcd7 --- /dev/null +++ b/board/toradex/apalis_t30/apalis_t30.env @@ -0,0 +1,9 @@ +uboot_hwpart=1 +uboot_blk=0 + +set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && + setexpr blkcnt ${blkcnt} / 0x200 +update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && + mmc write ${loadaddr} ${uboot_blk} ${blkcnt} + +boot_script_dhcp=boot.scr diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 251970b99cc..64cf99e9cfc 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -86,7 +86,7 @@ iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD) /* Colibri MMC */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -113,7 +113,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */ +#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */ /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */ iomux_v3_cfg_t const gpio_pads[] = { @@ -289,7 +289,7 @@ int board_ehci_hcd_init(int port) } #endif -#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD) /* use the following sequence: eMMC, MMC */ struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, @@ -346,7 +346,7 @@ int board_mmc_init(struct bd_info *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } -#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */ +#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */ int board_phy_config(struct phy_device *phydev) { @@ -677,7 +677,7 @@ void ldo_mode_set(int ldo_bypass) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> #include <linux/libfdt.h> #include "asm/arch/mx6dl-ddr.h" @@ -1101,7 +1101,7 @@ void reset_cpu(void) { } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ static struct mxc_serial_plat mxc_serial_plat = { .reg = (struct mxc_uart *)UART1_BASE, diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c index b404b01e032..698b05bc5ad 100644 --- a/board/toradex/colibri_imx6/do_fuse.c +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -7,7 +7,7 @@ * Helpers for i.MX OTP fusing during module production */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #include <command.h> #include <console.h> #include <fuse.h> @@ -94,4 +94,4 @@ U_BOOT_CMD( "OTP fusing during module update", "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing" ); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c index 58b7bc3bb9a..b5dffc87b35 100644 --- a/board/toradex/colibri_imx6/pf0100.c +++ b/board/toradex/colibri_imx6/pf0100.c @@ -197,7 +197,7 @@ unsigned pmic_init(void) return programmed; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int pf0100_prog(void) { int rc; @@ -265,4 +265,4 @@ U_BOOT_CMD( "Program the OTP fuses on the PMIC PF0100", "" ); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/toradex/colibri_t20/colibri_t20.env b/board/toradex/colibri_t20/colibri_t20.env new file mode 100644 index 00000000000..5e9f0630b27 --- /dev/null +++ b/board/toradex/colibri_t20/colibri_t20.env @@ -0,0 +1,3 @@ +/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ +boot_script_dhcp=boot.scr +update_uboot=nand erase.part u-boot && nand write ${loadaddr} u-boot ${filesize} diff --git a/board/toradex/colibri_t30/Makefile b/board/toradex/colibri_t30/Makefile index 8f333235b17..1cc801c8cfd 100644 --- a/board/toradex/colibri_t30/Makefile +++ b/board/toradex/colibri_t30/Makefile @@ -1,6 +1,6 @@ # Copyright (c) 2013-2014 Stefan Agner # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += colibri_t30-spl.o +obj-$(CONFIG_XPL_BUILD) += colibri_t30-spl.o obj-y += colibri_t30.o diff --git a/board/toradex/colibri_t30/colibri_t30.env b/board/toradex/colibri_t30/colibri_t30.env new file mode 100644 index 00000000000..a8f2904bcd7 --- /dev/null +++ b/board/toradex/colibri_t30/colibri_t30.env @@ -0,0 +1,9 @@ +uboot_hwpart=1 +uboot_blk=0 + +set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && + setexpr blkcnt ${blkcnt} / 0x200 +update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && + mmc write ${loadaddr} ${uboot_blk} ${blkcnt} + +boot_script_dhcp=boot.scr diff --git a/board/toradex/common/Makefile b/board/toradex/common/Makefile index 7b19b6e4c87..7e3905445a5 100644 --- a/board/toradex/common/Makefile +++ b/board/toradex/common/Makefile @@ -2,7 +2,7 @@ # Copyright (c) 2016 Toradex, Inc. # Common for all Toradex modules -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) # Necessary to create built-in.o obj- := __dummy__.o else diff --git a/board/toradex/verdin-imx8mm/Makefile b/board/toradex/verdin-imx8mm/Makefile index b38054254da..eee58aa2f83 100644 --- a/board/toradex/verdin-imx8mm/Makefile +++ b/board/toradex/verdin-imx8mm/Makefile @@ -5,7 +5,7 @@ obj-y += verdin-imx8mm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/toradex/verdin-imx8mp/Makefile b/board/toradex/verdin-imx8mp/Makefile index 98fa14e4e2a..5edd1778816 100644 --- a/board/toradex/verdin-imx8mp/Makefile +++ b/board/toradex/verdin-imx8mp/Makefile @@ -5,7 +5,7 @@ obj-y += verdin-imx8mp.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o endif diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index 4cf214bf17c..bc30bdac462 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -209,7 +209,7 @@ int board_late_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <linux/libfdt.h> #include <asm/arch/mx6-ddr.h> diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c index 6c477530055..b845284d688 100644 --- a/board/udoo/udoo_spl.c +++ b/board/udoo/udoo_spl.c @@ -23,7 +23,7 @@ #include <asm/arch/sys_proto.h> #include <spl.h> -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #include <asm/arch/mx6-ddr.h> /* diff --git a/board/variscite/common/imx9_eeprom.c b/board/variscite/common/imx9_eeprom.c index 32551af5b40..bfa30adc256 100644 --- a/board/variscite/common/imx9_eeprom.c +++ b/board/variscite/common/imx9_eeprom.c @@ -83,7 +83,7 @@ int var_eeprom_get_dram_size(struct var_eeprom *ep, phys_size_t *size) void var_eeprom_print_prod_info(struct var_eeprom *ep) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return; flush_dcache_all(); diff --git a/board/variscite/dart_6ul/Makefile b/board/variscite/dart_6ul/Makefile index 48aa361bf2d..39c3f53e736 100644 --- a/board/variscite/dart_6ul/Makefile +++ b/board/variscite/dart_6ul/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := dart_6ul.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/variscite/imx8mn_var_som/Makefile b/board/variscite/imx8mn_var_som/Makefile index a8b6a343ffc..36d9c36dd2d 100644 --- a/board/variscite/imx8mn_var_som/Makefile +++ b/board/variscite/imx8mn_var_som/Makefile @@ -6,7 +6,7 @@ obj-y += imx8mn_var_som.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += ddr4_timing.o endif diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 532d8d60a76..80c84e64241 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -54,7 +54,7 @@ int board_mmc_get_env_dev(int devno) return devno; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_DISPLAY_BOARDINFO) @@ -227,4 +227,4 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #endif /* CONFIG_OF_BOARD_SETUP */ -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/variscite/imx93_var_som/Makefile b/board/variscite/imx93_var_som/Makefile index b63883901bd..8b160f189c1 100644 --- a/board/variscite/imx93_var_som/Makefile +++ b/board/variscite/imx93_var_som/Makefile @@ -8,7 +8,7 @@ obj-y += imx93_var_som.o obj-$(CONFIG_TARGET_IMX93_VAR_SOM) += ../common/imx9_eeprom.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-$(CONFIG_TARGET_IMX93_VAR_SOM) += lpddr4x_timing.o else diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile index 2b1e21a1788..6ef87c22eaa 100644 --- a/board/vscom/baltos/Makefile +++ b/board/vscom/baltos/Makefile @@ -4,7 +4,7 @@ # # Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ -ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index f54f183038b..de9f8367d59 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -131,7 +131,7 @@ static int read_eeprom(BSP_VS_HWPARAM *header) return 0; } -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) +#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_NOR_BOOT) static const struct ddr_data ddr3_baltos_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, @@ -371,8 +371,8 @@ int board_late_init(void) } #endif -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)) static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -415,10 +415,10 @@ static struct cpsw_platform_data cpsw_data = { #endif #if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \ - && defined(CONFIG_SPL_BUILD)) || \ + && defined(CONFIG_XPL_BUILD)) || \ ((defined(CONFIG_DRIVER_TI_CPSW) || \ defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) + !defined(CONFIG_XPL_BUILD)) int board_eth_init(struct bd_info *bis) { int rv, n = 0; @@ -442,8 +442,8 @@ int board_eth_init(struct bd_info *bis) mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)) if (!env_get("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile index c3d80536b3a..6e5bcc11630 100644 --- a/board/wandboard/Makefile +++ b/board/wandboard/Makefile @@ -3,4 +3,4 @@ # (C) Copyright 2013 Freescale Semiconductor, Inc. obj-y := wandboard.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/wexler/qc750/Makefile b/board/wexler/qc750/Makefile index 4daefc4159a..5f9ebafd89c 100644 --- a/board/wexler/qc750/Makefile +++ b/board/wexler/qc750/Makefile @@ -6,6 +6,6 @@ # (C) Copyright 2023 # Svyatoslav Ryhel <clamor95@gmail.com> -obj-$(CONFIG_SPL_BUILD) += qc750-spl.o +obj-$(CONFIG_XPL_BUILD) += qc750-spl.o obj-y += qc750.o diff --git a/board/wexler/qc750/qc750.env b/board/wexler/qc750/qc750.env new file mode 100644 index 00000000000..f2bf298a997 --- /dev/null +++ b/board/wexler/qc750/qc750.env @@ -0,0 +1,15 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile index b837e7b0dd8..a96098d0f2a 100644 --- a/board/work-microwave/work_92105/Makefile +++ b/board/work-microwave/work_92105/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2014 DENX Software Engineering GmbH # Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += work_92105_spl.o else obj-y += work_92105.o diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile index d563290ab90..4b8fdec5830 100644 --- a/board/xilinx/common/Makefile +++ b/board/xilinx/common/Makefile @@ -8,6 +8,6 @@ obj-y += board.o ifndef CONFIG_ARCH_ZYNQ obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_FRU) += fru.o fru_ops.o endif diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 5e5eb49ddf3..68f401e4b34 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -370,7 +370,7 @@ void *board_fdt_blob_setup(int *err) return fdt_blob; } - if (!IS_ENABLED(CONFIG_SPL_BUILD) && + if (!IS_ENABLED(CONFIG_XPL_BUILD) && !IS_ENABLED(CONFIG_VERSAL_NO_DDR) && !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) { fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; @@ -381,7 +381,7 @@ void *board_fdt_blob_setup(int *err) debug("DTB is not passed via %p\n", fdt_blob); } - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* * FDT is at end of BSS unless it is in a different memory * region @@ -515,7 +515,7 @@ int __maybe_unused board_fit_config_name_match(const char *name) { debug("%s: Check %s, default %s\n", __func__, name, board_name); -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) if (IS_ENABLED(CONFIG_REGEX)) { struct slre slre; int ret; diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 2b035d53589..dc4523824b4 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -40,7 +40,7 @@ int board_late_init(void) ulong max_size; u32 status = 0; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE) int ret; ret = device_bind_driver(gd->dm_root, "mb_soft_reset", diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 85661715891..f40fe382f57 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -26,17 +26,17 @@ endif ifeq ($(init-objs),) ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),) init-objs := ps7_init_gpl.o -$(if $(CONFIG_SPL_BUILD),\ +$(if $(CONFIG_XPL_BUILD),\ $(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/)) endif endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_ZYNQ) += cmds.o obj-$(CONFIG_CMD_ZYNQ_RSA) += bootimg.o endif -obj-$(CONFIG_SPL_BUILD) += $(init-objs) +obj-$(CONFIG_XPL_BUILD) += $(init-objs) # Suppress "warning: function declaration isn't a prototype" CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index b9a91110ff7..a852d5b8ed5 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT) void board_debug_uart_init(void) { /* Add initialization sequence if UART is not configured */ @@ -36,7 +36,7 @@ void board_debug_uart_init(void) int board_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) printf("Silicon version:\t%d\n", zynq_get_silicon_version()); if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 9ab50eca400..6476f20eb83 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -26,16 +26,16 @@ endif ifeq ($(init-objs),) ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),) init-objs := psu_init_gpl.o -$(if $(CONFIG_SPL_BUILD),\ +$(if $(CONFIG_XPL_BUILD),\ $(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/)) endif endif -obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += $(init-objs) +obj-$(CONFIG_$(XPL_)ZYNQMP_PSU_INIT_ENABLED) += $(init-objs) -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"") -obj-$(CONFIG_SPL_BUILD) += pm_cfg_obj.o +obj-$(CONFIG_XPL_BUILD) += pm_cfg_obj.o $(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE)) FORCE endif endif diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 20a675c010d..8cdd9d86009 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -86,7 +86,7 @@ int __maybe_unused psu_uboot_init(void) return 0; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) # if defined(CONFIG_DEBUG_UART_BOARD_INIT) void board_debug_uart_init(void) { @@ -120,7 +120,7 @@ static int multi_boot(void) return multiboot; } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) static void restore_jtag(void) { if (current_el() != 3) @@ -155,7 +155,7 @@ int board_init(void) int ret; #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* Check *at build time* if the filename is an non-empty string */ if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, diff --git a/boot/Makefile b/boot/Makefile index f4675d6ffd5..b24f806d5bf 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_BOOT_RETRY) += bootretry.o obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o @@ -19,56 +19,54 @@ obj-y += image.o image-board.o obj-$(CONFIG_ANDROID_AB) += android_ab.o obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootdev-uclass.o -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow.o -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootmeth-uclass.o -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootstd-uclass.o - -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD_PROG) += prog_boot.o - -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX) += bootmeth_extlinux.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX_PXE) += bootmeth_pxe.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFILOADER) += bootmeth_efi.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_QFW) += bootmeth_qfw.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o -obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFI_BOOTMGR) += bootmeth_efi_mgr.o -ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL -obj-$(CONFIG_$(SPL_TPL_)EXPO) += bootflow_menu.o -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow_menu.o +obj-$(CONFIG_$(PHASE_)BOOTSTD) += bootdev-uclass.o +obj-$(CONFIG_$(PHASE_)BOOTSTD) += bootflow.o +obj-$(CONFIG_$(PHASE_)BOOTSTD) += bootmeth-uclass.o +obj-$(CONFIG_$(PHASE_)BOOTSTD) += bootstd-uclass.o + +obj-$(CONFIG_$(PHASE_)BOOTSTD_PROG) += prog_boot.o + +obj-$(CONFIG_$(PHASE_)BOOTMETH_EXTLINUX) += bootmeth_extlinux.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_EXTLINUX_PXE) += bootmeth_pxe.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_EFILOADER) += bootmeth_efi.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_QFW) += bootmeth_qfw.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_SCRIPT) += bootmeth_script.o +obj-$(CONFIG_$(PHASE_)CEDIT) += cedit.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_EFI_BOOTMGR) += bootmeth_efi_mgr.o +ifdef CONFIG_$(PHASE_)BOOTSTD_FULL +obj-$(CONFIG_$(PHASE_)EXPO) += bootflow_menu.o +obj-$(CONFIG_$(PHASE_)BOOTSTD) += bootflow_menu.o endif -obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o -obj-$(CONFIG_$(SPL_TPL_)FDT_SIMPLEFB) += fdt_simplefb.o +obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += fdt_support.o +obj-$(CONFIG_$(PHASE_)FDT_SIMPLEFB) += fdt_simplefb.o -obj-$(CONFIG_$(SPL_TPL_)UPL) += upl_common.o -obj-$(CONFIG_$(SPL_TPL_)UPL_READ) += upl_read.o -obj-$(CONFIG_$(SPL_TPL_)UPL_WRITE) += upl_write.o +obj-$(CONFIG_$(PHASE_)UPL) += upl_common.o +obj-$(CONFIG_$(PHASE_)UPL_READ) += upl_read.o +obj-$(CONFIG_$(PHASE_)UPL_WRITE) += upl_write.o -obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o -obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += fdt_region.o -obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o -obj-$(CONFIG_$(SPL_)MULTI_DTB_FIT) += boot_fit.o common_fit.o -obj-$(CONFIG_$(SPL_TPL_)IMAGE_PRE_LOAD) += image-pre-load.o -obj-$(CONFIG_$(SPL_TPL_)IMAGE_SIGN_INFO) += image-sig.o -obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += image-fit-sig.o -obj-$(CONFIG_$(SPL_TPL_)FIT_CIPHER) += image-cipher.o +obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += image-fdt.o +obj-$(CONFIG_$(PHASE_)FIT_SIGNATURE) += fdt_region.o +obj-$(CONFIG_$(PHASE_)FIT) += image-fit.o +obj-$(CONFIG_$(XPL_)MULTI_DTB_FIT) += boot_fit.o common_fit.o +obj-$(CONFIG_$(PHASE_)IMAGE_PRE_LOAD) += image-pre-load.o +obj-$(CONFIG_$(PHASE_)IMAGE_SIGN_INFO) += image-sig.o +obj-$(CONFIG_$(PHASE_)FIT_SIGNATURE) += image-fit-sig.o +obj-$(CONFIG_$(PHASE_)FIT_CIPHER) += image-cipher.o obj-$(CONFIG_CMD_ADTIMG) += image-android-dt.o -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o -endif +obj-$(CONFIG_$(PHASE_)LOAD_FIT) += common_fit.o -obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo.o scene.o expo_build.o -obj-$(CONFIG_$(SPL_TPL_)EXPO) += scene_menu.o scene_textline.o +obj-$(CONFIG_$(PHASE_)EXPO) += expo.o scene.o expo_build.o +obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE) += vbe.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE_REQUEST) += vbe_request.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE_SIMPLE) += vbe_simple.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE_SIMPLE_FW) += vbe_simple_fw.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE_SIMPLE_OS) += vbe_simple_os.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE) += vbe.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_REQUEST) += vbe_request.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_SIMPLE) += vbe_simple.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_SIMPLE_FW) += vbe_simple_fw.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_SIMPLE_OS) += vbe_simple_os.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_ANDROID) += bootmeth_android.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_ANDROID) += bootmeth_android.o diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index 6b41c0999f1..2ad6d3b4ace 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -162,8 +162,10 @@ static int distro_efi_try_bootflow_files(struct udevice *dev, int ret, seq; /* We require a partition table */ - if (!bflow->part) + if (!bflow->part) { + log_debug("no partitions\n"); return -ENOENT; + } strcpy(fname, EFI_DIRNAME); strcat(fname, BOOTEFI_NAME); @@ -171,8 +173,10 @@ static int distro_efi_try_bootflow_files(struct udevice *dev, if (bflow->blk) desc = dev_get_uclass_plat(bflow->blk); ret = bootmeth_try_file(bflow, desc, NULL, fname); - if (ret) + if (ret) { + log_debug("File '%s' not found\n", fname); return log_msg_ret("try", ret); + } /* Since we can access the file, let's call it ready */ bflow->state = BOOTFLOWST_READY; @@ -307,6 +311,8 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow) { int ret; + log_debug("dev='%s', part=%d\n", bflow->dev->name, bflow->part); + /* * bootmeth_efi doesn't allocate any buffer neither for blk nor net device * set flag to avoid freeing static buffer. @@ -332,6 +338,7 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) ulong kernel, fdt; int ret; + log_debug("distro EFI boot\n"); kernel = env_get_hex("kernel_addr_r", 0); if (!bootmeth_uses_network(bflow)) { ret = efiload_read_file(bflow, kernel); diff --git a/boot/bootstd-uclass.c b/boot/bootstd-uclass.c index 5de8efce19a..fdb8d69e320 100644 --- a/boot/bootstd-uclass.c +++ b/boot/bootstd-uclass.c @@ -122,7 +122,7 @@ static int bootstd_probe(struct udevice *dev) return 0; } -/* For now, bind the boormethod device if none are found in the devicetree */ +/* For now, bind the bootmethod device if none are found in the devicetree */ int dm_scan_other(bool pre_reloc_only) { struct driver *drv = ll_entry_start(struct driver, driver); diff --git a/boot/fdt_simplefb.c b/boot/fdt_simplefb.c index 53415548459..71b833eb9bd 100644 --- a/boot/fdt_simplefb.c +++ b/boot/fdt_simplefb.c @@ -27,7 +27,7 @@ static int fdt_simplefb_configure_node(void *blob, int off) struct udevice *dev; int ret; - if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) { + if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() > PHASE_SPL) { struct video_handoff *ho; ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho)); diff --git a/boot/image-android-dt.c b/boot/image-android-dt.c index 3b25018c2e7..653835cea76 100644 --- a/boot/image-android-dt.c +++ b/boot/image-android-dt.c @@ -72,7 +72,7 @@ bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr, return true; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) static void android_dt_print_fdt_info(const struct fdt_header *fdt) { u32 fdt_size; diff --git a/boot/image-android.c b/boot/image-android.c index 8934491c35f..e74dd498a30 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -656,7 +656,7 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img, return false; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /** * android_print_contents - prints out the contents of the Android format image * @hdr: pointer to the Android format image header diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c index fe328df4a85..35873b1fb0e 100644 --- a/boot/image-fit-sig.c +++ b/boot/image-fit-sig.c @@ -48,7 +48,7 @@ struct image_region *fit_region_make_list(const void *fit, * Use malloc() except in SPL (to save code size). In SPL the caller * must allocate the array. */ - if (!IS_ENABLED(CONFIG_SPL_BUILD) && !region) + if (!IS_ENABLED(CONFIG_XPL_BUILD) && !region) region = calloc(sizeof(*region), count); if (!region) return NULL; diff --git a/boot/vbe_simple_fw.c b/boot/vbe_simple_fw.c index 4d6da9490a7..da9701f9eb9 100644 --- a/boot/vbe_simple_fw.c +++ b/boot/vbe_simple_fw.c @@ -157,7 +157,7 @@ static int simple_load_from_image(struct spl_image_info *spl_image, struct vbe_handoff *handoff; int ret; - if (spl_phase() != PHASE_VPL && spl_phase() != PHASE_SPL) + if (xpl_phase() != PHASE_VPL && xpl_phase() != PHASE_SPL) return -ENOENT; ret = bloblist_ensure_size(BLOBLISTT_VBE, sizeof(struct vbe_handoff), @@ -197,7 +197,7 @@ static int simple_load_from_image(struct spl_image_info *spl_image, bootflow_free(&bflow); /* Record that VBE was used in this phase */ - handoff->phases |= 1 << spl_phase(); + handoff->phases |= 1 << xpl_phase(); return 0; } diff --git a/cmd/Kconfig b/cmd/Kconfig index dd33266cec7..37894eb80d6 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -438,21 +438,9 @@ config CMD_BOOTEFI_BOOTMGR This subcommand will allow you to select the UEFI binary to be booted via UEFI variables Boot####, BootOrder, and BootNext. -config CMD_BOOTEFI_HELLO_COMPILE - bool "Compile a standard EFI hello world binary for testing" - default y - help - This compiles a standard EFI hello world application with U-Boot so - that it can be used with the test/py testing framework. This is useful - for testing that EFI is working at a basic level, and for bringing - up EFI support on a new architecture. - - No additional space will be required in the resulting U-Boot binary - when this option is enabled. - config CMD_BOOTEFI_HELLO bool "Allow booting a standard EFI hello world for testing" - depends on CMD_BOOTEFI_BINARY && CMD_BOOTEFI_HELLO_COMPILE + depends on CMD_BOOTEFI_BINARY && BOOTEFI_HELLO_COMPILE default y if CMD_BOOTEFI_SELFTEST help This adds a standard EFI hello world application to U-Boot so that @@ -1091,13 +1079,10 @@ config CMD_BIND gadget driver from the command line. config CMD_CLK - bool "clk - Show clock frequencies" + bool "clk - Show and set clock frequencies" + depends on CLK help - (deprecated) - Shows clock frequences by calling a sock_clk_dump() hook function. - This is depreated in favour of using the CLK uclass and accessing - clock values from associated drivers. However currently no command - exists for this. + Show and set clock frequencies managed by CLK uclass drivers. config CMD_DEMO bool "demo - Demonstration commands for driver model" diff --git a/cmd/Makefile b/cmd/Makefile index 91227f1249c..21d376309b9 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD # core command obj-y += boot.o obj-$(CONFIG_CMD_BOOTM) += bootm.o @@ -247,9 +247,9 @@ obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_ARCH_KEYSTONE) += ti/ obj-$(CONFIG_ARCH_K3) += ti/ obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/ -endif # !CONFIG_SPL_BUILD +endif # !CONFIG_XPL_BUILD -obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o +obj-$(CONFIG_$(XPL_)CMD_TLV_EEPROM) += tlv_eeprom.o obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/ diff --git a/cmd/clk.c b/cmd/clk.c index 6fda6efb1ce..2fc834e5549 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -4,15 +4,12 @@ */ #include <command.h> #include <clk.h> -#if defined(CONFIG_DM) && defined(CONFIG_CLK) #include <dm.h> #include <dm/device.h> #include <dm/root.h> #include <dm/device-internal.h> #include <linux/clk-provider.h> -#endif -#if defined(CONFIG_DM) && defined(CONFIG_CLK) static void show_clks(struct udevice *dev, int depth, int last_flag) { int i, is_last; @@ -79,13 +76,6 @@ static int soc_clk_dump(void) return 0; } -#else -static int soc_clk_dump(void) -{ - puts("Not implemented\n"); - return 1; -} -#endif static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -101,7 +91,6 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc, return ret; } -#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK) static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -131,13 +120,10 @@ static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc, printf("set_rate returns %u\n", freq); return 0; } -#endif static struct cmd_tbl cmd_clk_sub[] = { U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), -#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK) U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""), -#endif }; static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/mtd.c b/cmd/mtd.c index 795aaa2b37d..f178d7bea61 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -10,6 +10,7 @@ #include <command.h> #include <console.h> +#include <led.h> #if CONFIG_IS_ENABLED(CMD_MTD_OTP) #include <hexdump.h> #endif @@ -558,6 +559,8 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc, while (mtd_block_isbad(mtd, off)) off += mtd->erasesize; + led_activity_blink(); + /* Loop over the pages to do the actual read/write */ while (remaining) { /* Skip the block if it is bad */ @@ -585,6 +588,8 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc, io_op.oobbuf += io_op.oobretlen; } + led_activity_off(); + if (!ret && dump) mtd_dump_device_buf(mtd, start_off, buf, len, woob); @@ -652,6 +657,8 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag, int argc, erase_op.addr = off; erase_op.len = mtd->erasesize; + led_activity_blink(); + while (len) { if (!scrub) { ret = mtd_block_isbad(mtd, erase_op.addr); @@ -680,6 +687,8 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag, int argc, erase_op.addr += mtd->erasesize; } + led_activity_off(); + if (ret && ret != -EIO) ret = CMD_RET_FAILURE; else diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 98a687bcabb..74ff5c6fc11 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define MAX_ENV_SIZE (1 << 20) /* 1 MiB */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Command interface: print one or all environment variables * @@ -182,9 +182,9 @@ DONE: return 0; } #endif -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_env_set(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -503,9 +503,9 @@ static int do_env_select(struct cmd_tbl *cmdtp, int flag, int argc, } #endif -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_env_default(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -1289,4 +1289,4 @@ U_BOOT_CMD_COMPLETE( var_complete ); #endif -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/cmd/ubi.c b/cmd/ubi.c index 0e62e449327..56d7da82629 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -14,6 +14,7 @@ #include <command.h> #include <env.h> #include <exports.h> +#include <led.h> #include <malloc.h> #include <memalign.h> #include <mtd.h> @@ -488,10 +489,18 @@ exit: int ubi_volume_write(char *volume, void *buf, loff_t offset, size_t size) { + int ret; + + led_activity_blink(); + if (!offset) - return ubi_volume_begin_write(volume, buf, size, size); + ret = ubi_volume_begin_write(volume, buf, size, size); + else + ret = ubi_volume_offset_write(volume, buf, offset, size); - return ubi_volume_offset_write(volume, buf, offset, size); + led_activity_off(); + + return ret; } int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size) diff --git a/cmd/vbe.c b/cmd/vbe.c index 423d9e5f8f0..186f6e6860d 100644 --- a/cmd/vbe.c +++ b/cmd/vbe.c @@ -93,7 +93,7 @@ static int do_vbe_state(struct cmd_tbl *cmdtp, int flag, int argc, printf("Phases:"); for (i = PHASE_NONE; i < PHASE_COUNT; i++) { if (handoff->phases & (1 << i)) - printf(" %s", spl_phase_name(i)); + printf(" %s", xpl_name(i)); } if (!handoff->phases) diff --git a/common/Makefile b/common/Makefile index d871113cbb9..2ee5ef9cc6e 100644 --- a/common/Makefile +++ b/common/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # core -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += init/ obj-y += main.o obj-y += exports.o @@ -42,12 +42,12 @@ obj-$(CONFIG_MENU) += menu.o obj-$(CONFIG_UPDATE_COMMON) += update.o obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o -endif # !CONFIG_SPL_BUILD +endif # !CONFIG_XPL_BUILD -obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o -obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o +obj-$(CONFIG_$(PHASE_)BOOTSTAGE) += bootstage.o +obj-$(CONFIG_$(PHASE_)BLOBLIST) += bloblist.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_DFU obj-$(CONFIG_DFU_OVER_USB) += dfu.o endif @@ -58,31 +58,23 @@ obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o obj-$(CONFIG_SPL_MUSB_NEW) += usb.o obj-$(CONFIG_SPL_SPLASH_SCREEN) += splash.o obj-$(CONFIG_SPL_SPLASH_SOURCE) += splash_source.o -endif # CONFIG_SPL_BUILD +endif # CONFIG_XPL_BUILD #others obj-$(CONFIG_DDR_SPD) += ddr_spd.o obj-$(CONFIG_SPD_EEPROM) += ddr_spd.o obj-$(CONFIG_HWCONFIG) += hwconfig.o obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_TPL_BUILD -obj-$(CONFIG_TPL_SERIAL) += console.o -else -obj-$(CONFIG_SPL_SERIAL) += console.o -endif -else -obj-y += console.o -endif # CONFIG_SPL_BUILD +obj-$(CONFIG_$(PHASE_)SERIAL) += console.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-y += dlmalloc.o -obj-$(CONFIG_$(SPL_TPL_)SYS_MALLOC_F) += malloc_simple.o +obj-$(CONFIG_$(PHASE_)SYS_MALLOC_F) += malloc_simple.o -obj-$(CONFIG_$(SPL_TPL_)CYCLIC) += cyclic.o -obj-$(CONFIG_$(SPL_TPL_)EVENT) += event.o +obj-$(CONFIG_$(PHASE_)CYCLIC) += cyclic.o +obj-$(CONFIG_$(PHASE_)EVENT) += event.o -obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o +obj-$(CONFIG_$(PHASE_)HASH) += hash.o obj-$(CONFIG_IO_TRACE) += iotrace.o obj-y += memsize.o obj-y += stdio.o @@ -96,15 +88,15 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_getch.o cli_simple.o cli_readline.o obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += cli_getch.o cli_simple.o cli_readline.o obj-$(CONFIG_DFU_OVER_USB) += dfu.o obj-y += command.o -obj-$(CONFIG_$(SPL_TPL_)LOG) += log.o -obj-$(CONFIG_$(SPL_TPL_)LOG_CONSOLE) += log_console.o -obj-$(CONFIG_$(SPL_TPL_)LOG_SYSLOG) += log_syslog.o +obj-$(CONFIG_$(PHASE_)LOG) += log.o +obj-$(CONFIG_$(PHASE_)LOG_CONSOLE) += log_console.o +obj-$(CONFIG_$(PHASE_)LOG_SYSLOG) += log_syslog.o obj-y += s_record.o obj-$(CONFIG_CMD_LOADB) += xyzModem.o -obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o +obj-$(CONFIG_$(PHASE_)YMODEM_SUPPORT) += xyzModem.o -obj-$(CONFIG_$(SPL_TPL_)AVB_VERIFY) += avb_verify.o -obj-$(CONFIG_$(SPL_TPL_)STACKPROTECTOR) += stackprot.o +obj-$(CONFIG_$(PHASE_)AVB_VERIFY) += avb_verify.o +obj-$(CONFIG_$(PHASE_)STACKPROTECTOR) += stackprot.o obj-$(CONFIG_SCP03) += scp03.o obj-$(CONFIG_QFW) += qfw.o diff --git a/common/bloblist.c b/common/bloblist.c index 2008ab4d25c..6640ad1fd69 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -504,15 +504,15 @@ int bloblist_init(void) * If U-Boot is not in the first phase, an existing bloblist must be * at a fixed address. */ - bool from_addr = fixed && !u_boot_first_phase(); + bool from_addr = fixed && !xpl_is_first_phase(); /* * If U-Boot is in the first phase that an arch custom routine should * install the bloblist passed from previous loader to this fixed * address. */ - bool from_boot_arg = fixed && u_boot_first_phase(); + bool from_boot_arg = fixed && xpl_is_first_phase(); - if (spl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST)) + if (xpl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST)) from_addr = false; if (fixed) addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED, diff --git a/common/board_f.c b/common/board_f.c index 154675d0e40..f1bd70fdd6c 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -397,7 +397,7 @@ __weak int arch_reserve_mmu(void) static int reserve_video_from_videoblob(void) { - if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) { + if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() > PHASE_SPL) { struct video_handoff *ho; int ret = 0; diff --git a/common/board_r.c b/common/board_r.c index 4faaa202421..1acad069d92 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -40,6 +40,7 @@ #include <initcall.h> #include <kgdb.h> #include <irq_func.h> +#include <led.h> #include <malloc.h> #include <mapmem.h> #include <miiphy.h> @@ -460,17 +461,28 @@ static int initr_malloc_bootparams(void) } #endif -#if defined(CONFIG_LED_STATUS) static int initr_status_led(void) { -#if defined(CONFIG_LED_STATUS_BOOT) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_BLINKING); -#else status_led_init(); -#endif + + return 0; +} + +static int initr_boot_led_blink(void) +{ + status_led_boot_blink(); + + led_boot_blink(); + + return 0; +} + +static int initr_boot_led_on(void) +{ + led_boot_on(); + return 0; } -#endif #ifdef CONFIG_CMD_NET static int initr_net(void) @@ -725,9 +737,8 @@ static init_fnc_t init_sequence_r[] = { #if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K) timer_init, /* initialize timer */ #endif -#if defined(CONFIG_LED_STATUS) initr_status_led, -#endif + initr_boot_led_blink, /* PPC has a udelay(20) here dating from 2002. Why? */ #ifdef CONFIG_BOARD_LATE_INIT board_late_init, @@ -750,6 +761,7 @@ static init_fnc_t init_sequence_r[] = { #if defined(CFG_PRAM) initr_mem, #endif + initr_boot_led_on, run_main_loop, }; diff --git a/common/bootstage.c b/common/bootstage.c index 49acc9078a6..dd6aed7c2fd 100644 --- a/common/bootstage.c +++ b/common/bootstage.c @@ -351,7 +351,7 @@ void bootstage_report(void) } if (data->rec_count > RECORD_COUNT) printf("Overflowed internal boot id table by %d entries\n" - "Please increase CONFIG_(SPL_TPL_)BOOTSTAGE_RECORD_COUNT\n", + "Please increase CONFIG_(PHASE_)BOOTSTAGE_RECORD_COUNT\n", data->rec_count - RECORD_COUNT); puts("\nAccumulated time:\n"); @@ -473,7 +473,7 @@ int bootstage_unstash(const void *base, int size) if (data->rec_count + hdr->count > RECORD_COUNT) { debug("%s: Bootstage has %d records, we have space for %d\n" - "Please increase CONFIG_(SPL_)BOOTSTAGE_RECORD_COUNT\n", + "Please increase CONFIG_(PHASE_)BOOTSTAGE_RECORD_COUNT\n", __func__, hdr->count, RECORD_COUNT - data->rec_count); return -ENOSPC; } @@ -489,7 +489,7 @@ int bootstage_unstash(const void *base, int size) for (rec = data->record + data->next_id, i = 0; i < hdr->count; i++, rec++) { rec->name = ptr; - if (spl_phase() == PHASE_SPL) + if (xpl_phase() == PHASE_SPL) rec->name = strdup(ptr); /* Assume no data corruption here */ diff --git a/common/cli_readline.c b/common/cli_readline.c index 4cb82b40149..4e6797a1944 100644 --- a/common/cli_readline.c +++ b/common/cli_readline.c @@ -73,7 +73,7 @@ static char *delete_char (char *buffer, char *p, int *colp, int *np, int plen) #define getcmd_getch() getchar() #define getcmd_cbeep() getcmd_putch('\a') -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define HIST_MAX 3 #define HIST_SIZE 32 #else diff --git a/common/console.c b/common/console.c index c9e206aec41..22224701e45 100644 --- a/common/console.c +++ b/common/console.c @@ -191,7 +191,7 @@ static int console_setfile(int file, struct stdio_dev * dev) /* Assign the new device (leaving the existing one started) */ stdio_devices[file] = dev; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Update monitor functions * (to use the console stuff by other applications) diff --git a/common/hash.c b/common/hash.c index ac63803fed9..db6925d6782 100644 --- a/common/hash.c +++ b/common/hash.c @@ -403,7 +403,7 @@ int hash_block(const char *algo_name, const void *data, unsigned int len, return 0; } -#if !defined(CONFIG_SPL_BUILD) && (defined(CONFIG_CMD_HASH) || \ +#if !defined(CONFIG_XPL_BUILD) && (defined(CONFIG_CMD_HASH) || \ defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)) || \ defined(CONFIG_CMD_MD5SUM) /** diff --git a/common/init/Makefile b/common/init/Makefile index 853b56d1e57..224e092f88c 100644 --- a/common/init/Makefile +++ b/common/init/Makefile @@ -5,4 +5,4 @@ # obj-y += board_init.o -obj-$(CONFIG_$(SPL_TPL_)HANDOFF) += handoff.o +obj-$(CONFIG_$(PHASE_)HANDOFF) += handoff.o diff --git a/common/spl/Makefile b/common/spl/Makefile index 137b18428bd..75123eb666b 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -6,36 +6,36 @@ # Based on common/Makefile. # -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o -obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o -obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o -obj-$(CONFIG_$(SPL_TPL_)BLK_FS) += spl_blk_fs.o -obj-$(CONFIG_$(SPL_TPL_)LEGACY_IMAGE_FORMAT) += spl_legacy.o -obj-$(CONFIG_$(SPL_TPL_)NOR_SUPPORT) += spl_nor.o -obj-$(CONFIG_$(SPL_TPL_)XIP_SUPPORT) += spl_xip.o -obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += spl_ymodem.o +ifdef CONFIG_XPL_BUILD +obj-$(CONFIG_$(PHASE_)FRAMEWORK) += spl.o +obj-$(CONFIG_$(PHASE_)BOOTROM_SUPPORT) += spl_bootrom.o +obj-$(CONFIG_$(PHASE_)LOAD_FIT) += spl_fit.o +obj-$(CONFIG_$(PHASE_)BLK_FS) += spl_blk_fs.o +obj-$(CONFIG_$(PHASE_)LEGACY_IMAGE_FORMAT) += spl_legacy.o +obj-$(CONFIG_$(PHASE_)NOR_SUPPORT) += spl_nor.o +obj-$(CONFIG_$(PHASE_)XIP_SUPPORT) += spl_xip.o +obj-$(CONFIG_$(PHASE_)YMODEM_SUPPORT) += spl_ymodem.o ifndef CONFIG_SPL_UBI -obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += spl_nand.o -obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o +obj-$(CONFIG_$(PHASE_)NAND_SUPPORT) += spl_nand.o +obj-$(CONFIG_$(PHASE_)ONENAND_SUPPORT) += spl_onenand.o endif -obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o -obj-$(CONFIG_$(SPL_TPL_)NET) += spl_net.o -obj-$(CONFIG_$(SPL_TPL_)MMC) += spl_mmc.o -obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o -obj-$(CONFIG_$(SPL_TPL_)OPTEE_IMAGE) += spl_optee.o -obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o -obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o -obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o -obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o -obj-$(CONFIG_$(SPL_TPL_)LOAD_IMX_CONTAINER) += spl_imx_container.o -obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o -obj-$(CONFIG_$(SPL_TPL_)NVME) += spl_nvme.o -obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += spl_semihosting.o -obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o -obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o -obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o -obj-$(CONFIG_$(SPL_TPL_)USB_SDP_SUPPORT) += spl_sdp.o +obj-$(CONFIG_$(PHASE_)UBI) += spl_ubi.o +obj-$(CONFIG_$(PHASE_)NET) += spl_net.o +obj-$(CONFIG_$(PHASE_)MMC) += spl_mmc.o +obj-$(CONFIG_$(PHASE_)ATF) += spl_atf.o +obj-$(CONFIG_$(PHASE_)OPTEE_IMAGE) += spl_optee.o +obj-$(CONFIG_$(PHASE_)OPENSBI) += spl_opensbi.o +obj-$(CONFIG_$(PHASE_)USB_STORAGE) += spl_usb.o +obj-$(CONFIG_$(PHASE_)FS_FAT) += spl_fat.o +obj-$(CONFIG_$(PHASE_)FS_EXT4) += spl_ext.o +obj-$(CONFIG_$(PHASE_)LOAD_IMX_CONTAINER) += spl_imx_container.o +obj-$(CONFIG_$(PHASE_)SATA) += spl_sata.o +obj-$(CONFIG_$(PHASE_)NVME) += spl_nvme.o +obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += spl_semihosting.o +obj-$(CONFIG_$(PHASE_)DFU) += spl_dfu.o +obj-$(CONFIG_$(PHASE_)SPI_LOAD) += spl_spi.o +obj-$(CONFIG_$(PHASE_)RAM_SUPPORT) += spl_ram.o +obj-$(CONFIG_$(PHASE_)USB_SDP_SUPPORT) += spl_sdp.o endif -obj-$(CONFIG_$(SPL_TPL_)UPL) += spl_upl.o +obj-$(CONFIG_$(PHASE_)UPL) += spl_upl.o diff --git a/common/spl/spl.c b/common/spl/spl.c index c13b2b8f714..94657d00591 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -97,9 +97,9 @@ __weak int dram_init_banksize(void) #if CONFIG_IS_ENABLED(OS_BOOT) __weak int spl_start_uboot(void) { - puts(SPL_TPL_PROMPT + puts(PHASE_PROMPT "Please implement spl_start_uboot() for your board\n"); - puts(SPL_TPL_PROMPT "Direct Linux boot not active!\n"); + puts(PHASE_PROMPT "Direct Linux boot not active!\n"); return 1; } @@ -140,13 +140,13 @@ void spl_fixup_fdt(void *fdt_blob) /* fixup the memory dt node */ err = fdt_shrink_to_minimum(fdt_blob, 0); if (err == 0) { - printf(SPL_TPL_PROMPT "fdt_shrink_to_minimum err - %d\n", err); + printf(PHASE_PROMPT "fdt_shrink_to_minimum err - %d\n", err); return; } err = arch_fixup_fdt(fdt_blob); if (err) { - printf(SPL_TPL_PROMPT "arch_fixup_fdt err - %d\n", err); + printf(PHASE_PROMPT "arch_fixup_fdt err - %d\n", err); return; } #endif @@ -176,10 +176,10 @@ ulong spl_get_image_pos(void) return BINMAN_SYM_MISSING; #ifdef CONFIG_VPL - if (spl_next_phase() == PHASE_VPL) + if (xpl_next_phase() == PHASE_VPL) return binman_sym(ulong, u_boot_vpl_any, image_pos); #endif - return spl_next_phase() == PHASE_SPL ? + return xpl_next_phase() == PHASE_SPL ? binman_sym(ulong, u_boot_spl_any, image_pos) : binman_sym(ulong, u_boot_any, image_pos); } @@ -190,10 +190,10 @@ ulong spl_get_image_size(void) return BINMAN_SYM_MISSING; #ifdef CONFIG_VPL - if (spl_next_phase() == PHASE_VPL) + if (xpl_next_phase() == PHASE_VPL) return binman_sym(ulong, u_boot_vpl_any, size); #endif - return spl_next_phase() == PHASE_SPL ? + return xpl_next_phase() == PHASE_SPL ? binman_sym(ulong, u_boot_spl_any, size) : binman_sym(ulong, u_boot_any, size); } @@ -201,10 +201,10 @@ ulong spl_get_image_size(void) ulong spl_get_image_text_base(void) { #ifdef CONFIG_VPL - if (spl_next_phase() == PHASE_VPL) + if (xpl_next_phase() == PHASE_VPL) return CONFIG_VPL_TEXT_BASE; #endif - return spl_next_phase() == PHASE_SPL ? CONFIG_SPL_TEXT_BASE : + return xpl_next_phase() == PHASE_SPL ? CONFIG_SPL_TEXT_BASE : CONFIG_TEXT_BASE; } @@ -330,7 +330,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image, spl_image->load_addr = start; spl_image->entry_point = start; spl_image->size = size; - debug(SPL_TPL_PROMPT + debug(PHASE_PROMPT "payload Image, load addr: 0x%lx size: %d\n", spl_image->load_addr, spl_image->size); return 0; @@ -344,7 +344,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image, spl_image->load_addr = CONFIG_SYS_LOAD_ADDR; spl_image->entry_point = CONFIG_SYS_LOAD_ADDR; spl_image->size = end - start; - debug(SPL_TPL_PROMPT + debug(PHASE_PROMPT "payload zImage, load addr: 0x%lx size: %d\n", spl_image->load_addr, spl_image->size); return 0; @@ -423,7 +423,7 @@ static int write_spl_handoff(void) ret = handoff_arch_save(ho); if (ret) return ret; - debug(SPL_TPL_PROMPT "Wrote SPL handoff\n"); + debug(PHASE_PROMPT "Wrote SPL handoff\n"); return 0; } @@ -441,7 +441,7 @@ static inline int write_spl_handoff(void) { return 0; } */ static enum bootstage_id get_bootstage_id(bool start) { - enum u_boot_phase phase = spl_phase(); + enum xpl_phase_t phase = xpl_phase(); if (IS_ENABLED(CONFIG_TPL_BUILD) && phase == PHASE_TPL) return start ? BOOTSTAGE_ID_START_TPL : BOOTSTAGE_ID_END_TPL; @@ -464,19 +464,18 @@ static int spl_common_init(bool setup_malloc) gd->malloc_ptr = 0; } #endif - ret = bootstage_init(u_boot_first_phase()); + ret = bootstage_init(xpl_is_first_phase()); if (ret) { debug("%s: Failed to set up bootstage: ret=%d\n", __func__, ret); return ret; } - if (!u_boot_first_phase()) { + if (!xpl_is_first_phase()) { ret = bootstage_unstash_default(); if (ret) log_debug("Failed to unstash bootstage: ret=%d\n", ret); } - bootstage_mark_name(get_bootstage_id(true), - spl_phase_name(spl_phase())); + bootstage_mark_name(get_bootstage_id(true), xpl_name(xpl_phase())); #if CONFIG_IS_ENABLED(LOG) ret = log_init(); if (ret) { @@ -493,7 +492,7 @@ static int spl_common_init(bool setup_malloc) } if (CONFIG_IS_ENABLED(DM)) { bootstage_start(BOOTSTAGE_ID_ACCUM_DM_SPL, - spl_phase() == PHASE_TPL ? "dm tpl" : "dm_spl"); + xpl_phase() == PHASE_TPL ? "dm tpl" : "dm_spl"); /* With CONFIG_SPL_OF_PLATDATA, bring in all devices */ ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA)); bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_SPL); @@ -624,11 +623,11 @@ static int boot_from_devices(struct spl_image_info *spl_image, printf("Trying to boot from %s\n", spl_loader_name(loader)); else if (CONFIG_IS_ENABLED(SHOW_ERRORS)) { - printf(SPL_TPL_PROMPT + printf(PHASE_PROMPT "Unsupported Boot Device %d\n", bootdev); } else { - puts(SPL_TPL_PROMPT + puts(PHASE_PROMPT "Unsupported Boot Device!\n"); } } @@ -674,7 +673,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) struct spl_image_info spl_image; int ret, os; - debug(">>" SPL_TPL_PROMPT "board_init_r()\n"); + debug(">>" PHASE_PROMPT "board_init_r()\n"); spl_set_bd(); @@ -694,7 +693,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (ret) { debug("%s: Failed to set up bloblist: ret=%d\n", __func__, ret); - puts(SPL_TPL_PROMPT "Cannot set up bloblist\n"); + puts(PHASE_PROMPT "Cannot set up bloblist\n"); hang(); } } @@ -703,7 +702,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) ret = setup_spl_handoff(); if (ret) { - puts(SPL_TPL_PROMPT "Cannot set up SPL handoff\n"); + puts(PHASE_PROMPT "Cannot set up SPL handoff\n"); hang(); } } @@ -724,7 +723,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (CONFIG_IS_ENABLED(PCI) && !(gd->flags & GD_FLG_DM_DEAD)) { ret = pci_init(); if (ret) - puts(SPL_TPL_PROMPT "Cannot initialize PCI\n"); + puts(PHASE_PROMPT "Cannot initialize PCI\n"); /* Don't fail. We still can try other boot methods. */ } @@ -751,10 +750,10 @@ void board_init_r(gd_t *dummy1, ulong dummy2) ARRAY_SIZE(spl_boot_list)); if (ret) { if (CONFIG_IS_ENABLED(SHOW_ERRORS)) - printf(SPL_TPL_PROMPT "failed to boot from all boot devices (err=%d)\n", + printf(PHASE_PROMPT "failed to boot from all boot devices (err=%d)\n", ret); else - puts(SPL_TPL_PROMPT "failed to boot from all boot devices\n"); + puts(PHASE_PROMPT "failed to boot from all boot devices\n"); hang(); } @@ -762,7 +761,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) os = spl_image.os; if (os == IH_OS_U_BOOT) { - debug("Jumping to %s...\n", spl_phase_name(spl_next_phase())); + debug("Jumping to %s...\n", xpl_name(xpl_next_phase())); } else if (CONFIG_IS_ENABLED(ATF) && os == IH_OS_ARM_TRUSTED_FIRMWARE) { debug("Jumping to U-Boot via ARM Trusted Firmware\n"); spl_fixup_fdt(spl_image_fdt_addr(&spl_image)); @@ -808,13 +807,13 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (CONFIG_IS_ENABLED(HANDOFF)) { ret = write_spl_handoff(); if (ret) - printf(SPL_TPL_PROMPT + printf(PHASE_PROMPT "SPL hand-off write failed (err=%d)\n", ret); } if (CONFIG_IS_ENABLED(UPL_OUT) && (gd->flags & GD_FLG_UPL)) { ret = spl_write_upl_handoff(&spl_image); if (ret) { - printf(SPL_TPL_PROMPT + printf(PHASE_PROMPT "UPL hand-off write failed (err=%d)\n", ret); hang(); } @@ -844,7 +843,7 @@ void preloader_console_init(void) gd->flags |= GD_FLG_HAVE_CONSOLE; #if CONFIG_IS_ENABLED(BANNER_PRINT) - puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - " + puts("\nU-Boot " PHASE_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - " U_BOOT_TIME " " U_BOOT_TZ ")\n"); #endif #ifdef CONFIG_SPL_DISPLAY_PRINT diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 1ad5a69d807..3160f573bfb 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -904,7 +904,7 @@ int spl_load_fit_image(struct spl_image_info *spl_image, spl_image->os = IH_OS_INVALID; spl_image->name = genimg_get_os_name(spl_image->os); - debug(SPL_TPL_PROMPT "payload image: %32s load addr: 0x%lx size: %d\n", + debug(PHASE_PROMPT "payload image: %32s load addr: 0x%lx size: %d\n", spl_image->name, spl_image->load_addr, spl_image->size); #ifdef CONFIG_SPL_FIT_SIGNATURE diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index a77893455f2..9252b3a3de0 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -71,7 +71,7 @@ int spl_parse_legacy_header(struct spl_image_info *spl_image, spl_image->os = image_get_os(header); spl_image->name = image_get_name(header); - debug(SPL_TPL_PROMPT + debug(PHASE_PROMPT "payload image: %32s load addr: 0x%lx size: %d\n", spl_image->name, spl_image->load_addr, spl_image->size); diff --git a/common/splash_source.c b/common/splash_source.c index 5b271160449..f43e7cc1be7 100644 --- a/common/splash_source.c +++ b/common/splash_source.c @@ -215,7 +215,7 @@ static int splash_init_virtio(void) } } -#if defined(CONFIG_CMD_UBIFS) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_UBIFS) && !defined(CONFIG_XPL_BUILD) static int splash_mount_ubifs(struct splash_location *location) { int res; diff --git a/config.mk b/config.mk index b915c29b3f3..e294be2a4c4 100644 --- a/config.mk +++ b/config.mk @@ -21,7 +21,7 @@ VENDOR := ARCH := $(CONFIG_SYS_ARCH:"%"=%) CPU := $(CONFIG_SYS_CPU:"%"=%) -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_ARCH_TEGRA CPU := arm720t endif diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 00518dda63d..8c308f308ab 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -146,7 +146,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_UFS=y -CONFIG_CADENCE_UFS=y +CONFIG_UFS_AMD_VERSAL2=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y diff --git a/configs/aml-a311d-cc_defconfig b/configs/aml-a311d-cc_defconfig new file mode 100644 index 00000000000..c8e22200419 --- /dev/null +++ b/configs/aml-a311d-cc_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="libre-computer" +CONFIG_SYS_BOARD="aml-a311d-cc" +CONFIG_ARCH_MESON=y +CONFIG_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFF0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-libretech-cc" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_MESON_G12A=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING="aml-a311d-cc" +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_DEBUG_UART=y +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_EFIDEBUG=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SET_DFU_ALT_INFO=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_MDIO_MUX_MESON_G12A=y +CONFIG_MESON_G12A_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_EE_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_G12A=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/aml-s905d3-cc_defconfig b/configs/aml-s905d3-cc_defconfig new file mode 100644 index 00000000000..a6e5d584c0a --- /dev/null +++ b/configs/aml-s905d3-cc_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="libre-computer" +CONFIG_SYS_BOARD="aml-s905d3-cc" +CONFIG_ARCH_MESON=y +CONFIG_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFF0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-s905d3-libretech-cc" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_MESON_G12A=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING="aml-s905d3-cc" +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_DEBUG_UART=y +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_EFIDEBUG=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SET_DFU_ALT_INFO=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_MDIO_MUX_MESON_G12A=y +CONFIG_MESON_G12A_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_EE_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_G12A=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/anbernic_rg35xx_h700_defconfig b/configs/anbernic_rg35xx_h700_defconfig new file mode 100644 index 00000000000..cd3d6bfba06 --- /dev/null +++ b/configs/anbernic_rg35xx_h700_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h700-anbernic-rg35xx-2024" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e +CONFIG_DRAM_SUN50I_H616_ODT_EN=0x7887bbbb +CONFIG_DRAM_SUN50I_H616_TPR2=0x1 +CONFIG_DRAM_SUN50I_H616_TPR6=0x40808080 +CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6633 +CONFIG_DRAM_SUN50I_H616_TPR11=0x1b1f1e1c +CONFIG_DRAM_SUN50I_H616_TPR12=0x06060606 +CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1=y +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_CLK=672 +CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_REGULATOR_AXP=y +CONFIG_AXP717_POWER=y +CONFIG_AXP_DCDC2_VOLT=940 +CONFIG_AXP_DCDC3_VOLT=1100 diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 7fa6161f22a..baab3bf8040 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_TEGRA=y CONFIG_TEXT_BASE=0x80110000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="apalis-tk1" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis" @@ -19,7 +20,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt_module}-${fdt_board}.dtb && run distro_bootcmd" +CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt_module}-${fdt_board}.dtb && bootflow scan" CONFIG_SYS_CBSIZE=1024 CONFIG_SYS_PBSIZE=1054 CONFIG_CONSOLE_MUX=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index d7da23ed752..963b280a675 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_TEGRA=y CONFIG_TEXT_BASE=0x80110000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="apalis_t30" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis" diff --git a/configs/bcm96846_defconfig b/configs/bcm96846_defconfig index ea643eddcc6..877a606a965 100644 --- a/configs/bcm96846_defconfig +++ b/configs/bcm96846_defconfig @@ -9,14 +9,27 @@ CONFIG_TARGET_BCM96846=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96846" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96846" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6846" CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MTDPARTS=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_MTDIDS_DEFAULT="nand0=nand0" +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_SYS_NAND_ONFI_DETECTION=n diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index 7d88a25eb71..3fca1ae345e 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="cardhu" CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 67456c89e77..a1a12e2b512 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_TEGRA=y CONFIG_TEXT_BASE=0x00110000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="colibri_t20" CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x200000 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri" diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 5044febb20f..3be175b46bf 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_TEGRA=y CONFIG_TEXT_BASE=0x80110000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="colibri_t30" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri" diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig index fddc3d87ed3..f0c8ce16142 100644 --- a/configs/endeavoru_defconfig +++ b/configs/endeavoru_defconfig @@ -5,6 +5,7 @@ CONFIG_CMDLINE_TAG=y CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="endeavoru" CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xFFFFD000 CONFIG_DEFAULT_DEVICE_TREE="tegra30-htc-endeavoru" diff --git a/configs/grouper_common_defconfig b/configs/grouper_defconfig index 7d8cb6110f3..d07d74025d0 100644 --- a/configs/grouper_common_defconfig +++ b/configs/grouper_defconfig @@ -5,6 +5,7 @@ CONFIG_CMDLINE_TAG=y CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="grouper" CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xFFFFD000 CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565" @@ -38,6 +39,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_UMS_ABORT_KEYED=y @@ -47,6 +49,9 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_LIST="tegra30-asus-nexus7-grouper-E1565 tegra30-asus-nexus7-grouper-PM269 tegra30-asus-nexus7-tilapia-E1565" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 @@ -61,10 +66,16 @@ CONFIG_GPIO_HOG=y CONFIG_SYS_I2C_TEGRA=y CONFIG_BUTTON_KEYBOARD=y CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_MAX77663=y +CONFIG_DM_PMIC_TPS65910=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_MAX77663=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_TPS65911=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_MAX77663=y +CONFIG_SYSRESET_TPS65910=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_TEGRA=y diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig index 4618c5253b6..a9dd5216ccf 100644 --- a/configs/ideapad-yoga-11_defconfig +++ b/configs/ideapad-yoga-11_defconfig @@ -5,6 +5,7 @@ CONFIG_CMDLINE_TAG=y CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="ideapad-yoga-11" CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xFFFFD000 CONFIG_DEFAULT_DEVICE_TREE="tegra30-lenovo-ideapad-yoga-11" diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig index dcc529f9fc2..9f75ab1477f 100644 --- a/configs/imx8mp_debix_model_a_defconfig +++ b/configs/imx8mp_debix_model_a_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-debix-model-a" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-debix-model-a" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index f6ee4c50e5f..a20ddbc688e 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="libretech-ac" +CONFIG_SYS_VENDOR="libre-computer" +CONFIG_SYS_BOARD="aml-s805x-ac" CONFIG_ARCH_MESON=y CONFIG_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 @@ -33,6 +35,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y CONFIG_CMD_DFU=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -40,6 +43,7 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_EFIDEBUG=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y @@ -47,6 +51,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SET_DFU_ALT_INFO=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y @@ -96,3 +102,5 @@ CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 80f7cd60b5b..2a83b8cd067 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -86,6 +86,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +# CONFIG_SPI_FLASH_LOCK is not set CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index b9d36d612d2..7909a33919e 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -38,7 +38,7 @@ CONFIG_SYS_PBSIZE=1050 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +# CONFIG_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MX_CYCLIC=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index 89e01539399..cac337cb84b 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -38,7 +38,7 @@ CONFIG_SYS_PBSIZE=1050 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +# CONFIG_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MX_CYCLIC=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index 2fd30050b26..c935c4ee1c6 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -39,7 +39,7 @@ CONFIG_SYS_PBSIZE=1050 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +# CONFIG_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MX_CYCLIC=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index 6ab8ebc41b3..b2143394eae 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -37,7 +37,7 @@ CONFIG_SYS_PBSIZE=1050 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +# CONFIG_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MX_CYCLIC=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index c4e4f8bda53..f60ee7375da 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h616-orangepi-zero2" CONFIG_SPL=y CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808 CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e diff --git a/configs/orangepi_zero2w_defconfig b/configs/orangepi_zero2w_defconfig index 5734d9d839c..cbb702d85b3 100644 --- a/configs/orangepi_zero2w_defconfig +++ b/configs/orangepi_zero2w_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero2w" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-orangepi-zero2w" CONFIG_SPL=y CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig index 44b7ec7887d..4e9b0ec4d33 100644 --- a/configs/orangepi_zero3_defconfig +++ b/configs/orangepi_zero3_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-orangepi-zero3" CONFIG_SPL=y CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index 3554ba6a720..a12586523e9 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=1026 +CONFIG_ENV_SOURCE_FILE="p2771-0000" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000" diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index ac7ed8e10fc..a002178b7fb 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -6,6 +6,7 @@ CONFIG_ARCH_TEGRA=y CONFIG_TEXT_BASE=0x80080000 CONFIG_SYS_MALLOC_LEN=0x2500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="p3450-0000" CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig index d0b07ee07c4..58a3c83ade0 100644 --- a/configs/qc750_defconfig +++ b/configs/qc750_defconfig @@ -5,6 +5,7 @@ CONFIG_CMDLINE_TAG=y CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="qc750" CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xFFFFD000 CONFIG_DEFAULT_DEVICE_TREE="tegra30-wexler-qc750" diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index e2f57c11f0e..1b3b8c6e788 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -46,6 +46,7 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 4e33222df60..f596f1cc55a 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -75,6 +75,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEM_SEARCH=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPIO_READ=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index dd62adbebd5..0313fa09532 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index 41fa96ace32..a48ef1fcf6f 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -81,6 +81,7 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 0b820ce62f5..f4469626090 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -60,6 +60,7 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index beb740d1b34..cda25263ac4 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -71,6 +71,7 @@ CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig index dbb08abbb1a..c1fd4a56a8f 100644 --- a/configs/surface-rt_defconfig +++ b/configs/surface-rt_defconfig @@ -5,6 +5,7 @@ CONFIG_CMDLINE_TAG=y CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="surface-rt" CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xFFFFD000 CONFIG_DEFAULT_DEVICE_TREE="tegra30-microsoft-surface-rt" diff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig index 9915fff4a00..706306b1444 100644 --- a/configs/tanix_tx1_defconfig +++ b/configs/tanix_tx1_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun50i-h313-tanix-tx1" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h313-tanix-tx1" CONFIG_SPL=y CONFIG_DRAM_SUN50I_H616_DX_ODT=0x06060606 CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0d0d0d0d diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig index f424ce8c273..df993c31c72 100644 --- a/configs/transformer_t20_defconfig +++ b/configs/transformer_t20_defconfig @@ -5,6 +5,7 @@ CONFIG_CMDLINE_TAG=y CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x00110000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="transformer-t20" CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xFFFFD000 CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101" diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig index 10784033e7e..9102dcc88b2 100644 --- a/configs/transformer_t30_defconfig +++ b/configs/transformer_t30_defconfig @@ -5,6 +5,7 @@ CONFIG_CMDLINE_TAG=y CONFIG_INITRD_TAG=y CONFIG_TEXT_BASE=0x80110000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="transformer-t30" CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xFFFFD000 CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201" @@ -49,10 +50,14 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_LIST="tegra30-asus-p1801-t tegra30-asus-tf201 tegra30-asus-tf300t tegra30-asus-tf300tg tegra30-asus-tf300tl tegra30-asus-tf600t tegra30-asus-tf700t" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_BUTTON=y +CONFIG_CLK_GPIO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 @@ -64,6 +69,7 @@ CONFIG_SYS_I2C_TEGRA=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_GPIO=y CONFIG_BUTTON_KEYBOARD=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_TPS65910=y CONFIG_DM_REGULATOR=y @@ -71,6 +77,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_TPS65911=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y CONFIG_SYSRESET_TPS65910=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -79,7 +86,9 @@ CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="ASUS" CONFIG_USB_GADGET_VENDOR_NUM=0x0b05 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf CONFIG_CI_UDC=y CONFIG_VIDEO=y # CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y CONFIG_VIDEO_TEGRA20=y diff --git a/configs/transpeed-8k618-t_defconfig b/configs/transpeed-8k618-t_defconfig index 020d3974afe..1d5a0c264b3 100644 --- a/configs/transpeed-8k618-t_defconfig +++ b/configs/transpeed-8k618-t_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-transpeed-8k618-t" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-transpeed-8k618-t" CONFIG_SPL=y CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303 CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index 42a3b8c1310..f876cc91f6e 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-x96-mate" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h616-x96-mate" CONFIG_SPL=y CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303 CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 54979eccb5b..899776e9c7f 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -128,6 +128,7 @@ CONFIG_XILINX_UARTLITE=y CONFIG_SOC_DEVICE=y CONFIG_SOC_XILINX_VERSAL_NET=y CONFIG_SPI=y +CONFIG_SPI_ADVANCE=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_CADENCE_OSPI_VERSAL=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index f3ab43e19e5..32c6bcd2078 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -129,6 +129,7 @@ CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y CONFIG_SOC_XILINX_VERSAL=y CONFIG_SPI=y +CONFIG_SPI_ADVANCE=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_HAS_CQSPI_REF_CLK=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 2437f7c8b75..eaaf105dd69 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -144,6 +144,7 @@ CONFIG_ZYNQ_GEM=y CONFIG_POWER_DOMAIN=y CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI_ADVANCE=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 2f1f46cad65..ff8ab344595 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -208,6 +208,7 @@ CONFIG_XILINX_UARTLITE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y +CONFIG_SPI_ADVANCE=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_SYSRESET=y diff --git a/disk/Kconfig b/disk/Kconfig index ffa835eb354..b0bd02539ee 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -49,6 +49,16 @@ config SPL_MAC_PARTITION default y if MAC_PARTITION select SPL_PARTITIONS +config TEGRA_PARTITION + bool "Enable Nvidia Tegra partition table" + select PARTITIONS + select EFI_PARTITION + help + Say Y here if you would like to use U-Boot on a device that + is using the Nvidia Tegra partition table and cannot alter it. + + If unsure, say N. + config DOS_PARTITION bool "Enable MS Dos partition table" default y if BOOT_DEFAULTS diff --git a/disk/Makefile b/disk/Makefile index 45588cf66e4..2248a659f8b 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -5,16 +5,16 @@ #ccflags-y += -DET_DEBUG -DDEBUG -obj-$(CONFIG_$(SPL_TPL_)PARTITIONS) += part.o -ifdef CONFIG_$(SPL_TPL_)BLK -obj-$(CONFIG_$(SPL_TPL_)PARTITIONS) += disk-uclass.o +obj-$(CONFIG_$(PHASE_)PARTITIONS) += part.o +ifdef CONFIG_$(PHASE_)BLK +obj-$(CONFIG_$(PHASE_)PARTITIONS) += disk-uclass.o endif # Must have BLK or SPL_LEGACY_BLOCK to support partitions -ifneq ($(CONFIG_$(SPL_TPL_)BLK),$(CONFIG_SPL_LEGACY_BLOCK),) -obj-$(CONFIG_$(SPL_TPL_)MAC_PARTITION) += part_mac.o -obj-$(CONFIG_$(SPL_TPL_)DOS_PARTITION) += part_dos.o -obj-$(CONFIG_$(SPL_TPL_)ISO_PARTITION) += part_iso.o -obj-$(CONFIG_$(SPL_TPL_)AMIGA_PARTITION) += part_amiga.o -obj-$(CONFIG_$(SPL_TPL_)EFI_PARTITION) += part_efi.o +ifneq ($(CONFIG_$(PHASE_)BLK),$(CONFIG_SPL_LEGACY_BLOCK),) +obj-$(CONFIG_$(PHASE_)MAC_PARTITION) += part_mac.o +obj-$(CONFIG_$(PHASE_)DOS_PARTITION) += part_dos.o +obj-$(CONFIG_$(PHASE_)ISO_PARTITION) += part_iso.o +obj-$(CONFIG_$(PHASE_)AMIGA_PARTITION) += part_amiga.o +obj-$(CONFIG_$(PHASE_)EFI_PARTITION) += part_efi.o endif diff --git a/disk/part.c b/disk/part.c index 706d77b3194..303178161c0 100644 --- a/disk/part.c +++ b/disk/part.c @@ -482,7 +482,7 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str, } #endif -#if IS_ENABLED(CONFIG_CMD_UBIFS) && !IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_CMD_UBIFS) && !IS_ENABLED(CONFIG_XPL_BUILD) /* * Special-case ubi, ubi goes through a mtd, rather than through * a regular block device. diff --git a/disk/part_dos.c b/disk/part_dos.c index 09af2aeeb99..96f748702fd 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -100,7 +100,7 @@ static int test_block_type(unsigned char *buffer) static int part_test_dos(struct blk_desc *desc) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr, DIV_ROUND_UP(desc->blksz, sizeof(legacy_mbr))); diff --git a/disk/part_efi.c b/disk/part_efi.c index 580821a6ee9..7f04c6ecd69 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -318,6 +318,17 @@ static int part_test_efi(struct blk_desc *desc) /* Read legacy MBR from block 0 and validate it */ if ((blk_dread(desc, 0, 1, (ulong *)legacymbr) != 1) || (is_pmbr_valid(legacymbr) != 1)) { + /* + * TegraPT is compatible with EFI part, but it + * cannot pass the Protective MBR check. Skip it + * if CONFIG_TEGRA_PARTITION is enabled and the + * device in question is eMMC. + */ + if (IS_ENABLED(CONFIG_TEGRA_PARTITION)) + if (!is_pmbr_valid(legacymbr) && + desc->uclass_id == UCLASS_MMC && + !desc->devnum) + return 0; return -1; } return 0; diff --git a/doc/api/index.rst b/doc/api/index.rst index ec0b8adb2cf..9f7f23f868f 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -14,6 +14,7 @@ U-Boot API documentation event getopt interrupt + led linker_lists lmb logging diff --git a/doc/api/led.rst b/doc/api/led.rst new file mode 100644 index 00000000000..e52e350d1bb --- /dev/null +++ b/doc/api/led.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +LED +=== + +.. kernel-doc:: include/led.h + :doc: Overview + +.. kernel-doc:: include/led.h + :internal:
\ No newline at end of file diff --git a/doc/board/amlogic/aml-a311d-cc.rst b/doc/board/amlogic/aml-a311d-cc.rst new file mode 100644 index 00000000000..25c1e01906a --- /dev/null +++ b/doc/board/amlogic/aml-a311d-cc.rst @@ -0,0 +1,46 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Libre Computer AML-A311D-CC 'Alta' (A311D) +===================================================== + +AML-A311D-CC is a Single Board Computer manufactured by Libre Computer Technology with +the following specifications: + + - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC + - 2 or 4GB LPDDR4 SDRAM + - Gigabit Ethernet + - HDMI 2.1 display + - 40-pin GPIO header + - 4 x USB 3.0 Host, 1 x USB 2.0 Type-C + - eMMC 5.x SM Interface for Libre Computer Modules + - microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +U-Boot Compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make aml-a311d-cc_defconfig + $ make + +U-Boot Signing with Pre-Built FIP repo +-------------------------------------- + +.. code-block:: bash + + $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 + $ cd amlogic-boot-fip + $ mkdir my-output-dir + $ ./build-fip.sh aml-a311d-cc /path/to/u-boot/u-boot.bin my-output-dir + +Then write U-Boot to SD or eMMC with: + +.. code-block:: bash + + $ DEV=/dev/boot_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440 diff --git a/doc/board/amlogic/aml-s905d3-cc.rst b/doc/board/amlogic/aml-s905d3-cc.rst new file mode 100644 index 00000000000..083a591fc52 --- /dev/null +++ b/doc/board/amlogic/aml-s905d3-cc.rst @@ -0,0 +1,46 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Libre Computer AML-S905D3-CC 'Solitude' (S905D3) +=========================================================== + +AML-S905D3-CC is a Single Board Computer manufactured by Libre Computer Technology with +the following specifications: + + - Amlogic S905D3 Cortex-A55 quad-core SoC + - 2 or 4GB LPDDR4 SDRAM + - Gigabit Ethernet + - HDMI 2.1 display + - 40-pin GPIO header + - 4 x USB 3.0 Host, 1 x USB 2.0 Type-C + - eMMC 5.x SM Interface for Libre Computer Modules + - microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +U-Boot Compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make aml-s905d3-cc_defconfig + $ make + +U-Boot Signing with Pre-Built FIP repo +-------------------------------------- + +.. code-block:: bash + + $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 + $ cd amlogic-boot-fip + $ mkdir my-output-dir + $ ./build-fip.sh aml-s905d3-cc /path/to/u-boot/u-boot.bin my-output-dir + +Then write U-Boot to SD or eMMC with: + +.. code-block:: bash + + $ DEV=/dev/boot_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440 diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 46f44bf34ec..dcd935224ac 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -85,6 +85,8 @@ Board Documentation .. toctree:: :maxdepth: 1 + aml-a311d-cc + aml-s905d3-cc bananapi-cm4io bananapi-m2pro bananapi-m2s diff --git a/doc/board/asus/grouper_common.rst b/doc/board/asus/grouper.rst index 47a854e9163..d56a9ca3921 100644 --- a/doc/board/asus/grouper_common.rst +++ b/doc/board/asus/grouper.rst @@ -19,14 +19,14 @@ Quick Start Build U-Boot ------------ -Device support is implemented by applying config fragment to a generic board -defconfig. Valid fragments are ``tilapia.config``, ``grouper_E1565.config`` -and ``grouper_PM269.config``. +U-Boot features ability to detect grouper board revision on which it is +loaded. Currently are supported both TI and MAXIM based WiFi-only models +along with cellular one. .. code-block:: bash $ export CROSS_COMPILE=arm-linux-gnueabi- - $ make grouper_common_defconfig grouper_E1565.config # For maxim based grouper + $ make grouper_defconfig # For all grouper versions and tilapia $ make After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` diff --git a/doc/board/asus/index.rst b/doc/board/asus/index.rst index 2b103287905..2cac04ce04a 100644 --- a/doc/board/asus/index.rst +++ b/doc/board/asus/index.rst @@ -6,6 +6,6 @@ ASUS .. toctree:: :maxdepth: 2 - grouper_common + grouper transformer_t20 transformer_t30 diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst index ff9792dc0fc..bebc4b9fad3 100644 --- a/doc/board/asus/transformer_t30.rst +++ b/doc/board/asus/transformer_t30.rst @@ -20,15 +20,18 @@ Quick Start Build U-Boot ------------ -Device support is implemented by applying a config fragment to a generic board -defconfig. Valid fragments are ``tf201.config``, ``tf300t.config``, -``tf300tg.config``, ``tf300tl.config``, ``tf700t.config``, ``tf600t.config`` and -``p1801-t.config``. +U-Boot features ability to detect transformer device model on which it is +loaded. The list of supported devices include: +- ASUS Transformer Prime TF201 +- ASUS Transformer Pad (3G/LTE) TF300T/TG/TL +- ASUS Transformer Infinity TF700T +- ASUS Portable AiO P1801-T +- ASUS VivoTab RT TF600T .. code-block:: bash $ export CROSS_COMPILE=arm-linux-gnueabi- - $ make transformer_t30_defconfig tf201.config # For TF201 + $ make transformer_t30_defconfig $ make After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` diff --git a/doc/develop/distro.rst b/doc/develop/distro.rst index 9e715b23ebb..637bc27fc2d 100644 --- a/doc/develop/distro.rst +++ b/doc/develop/distro.rst @@ -189,7 +189,7 @@ TO BE UPDATED: In your board configuration file, include the following:: - #ifndef CONFIG_SPL_BUILD + #ifndef CONFIG_XPL_BUILD #include <config_distro_bootcmd.h> #endif @@ -316,7 +316,7 @@ that it supports the correct set of possible boot device types. To provide this configuration, simply define macro BOOT_TARGET_DEVICES prior to including <config_distro_bootcmd.h>. For example:: - #ifndef CONFIG_SPL_BUILD + #ifndef CONFIG_XPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 0d0e60ab56c..c23192c2770 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -13,6 +13,7 @@ General codingstyle designprinciples docstyle + memory patman process release_cycle @@ -38,6 +39,7 @@ Implementation distro driver-model/index environment + init expo cedit event diff --git a/doc/develop/init.rst b/doc/develop/init.rst new file mode 100644 index 00000000000..ce985781bb4 --- /dev/null +++ b/doc/develop/init.rst @@ -0,0 +1,93 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Board Initialisation Flow +------------------------- + +This is the intended start-up flow for boards. This should apply for both +xPL and U-Boot proper (i.e. they both follow the same rules). + +Note: "xPL" stands for "any Program Loader", including SPL (Secondary +Program Loader), TPL (Tertiary Program Loader) and VPL (Verifying Program +Loader). The boot sequence is TPL->VPL->SPL->U-Boot proper + +At present, xPL mostly uses a separate code path, but the function names +and roles of each function are the same. Some boards or architectures +may not conform to this. At least most ARM boards which use +CONFIG_xPL_FRAMEWORK conform to this. + +Execution typically starts with an architecture-specific (and possibly +CPU-specific) start.S file, such as: + +- arch/arm/cpu/armv7/start.S +- arch/powerpc/cpu/mpc83xx/start.S +- arch/mips/cpu/start.S + +and so on. From there, three functions are called; the purpose and +limitations of each of these functions are described below. + +lowlevel_init() +~~~~~~~~~~~~~~~ + +- purpose: essential init to permit execution to reach board_init_f() +- no global_data or BSS +- there is no stack (ARMv7 may have one but it will soon be removed) +- must not set up SDRAM or use console +- must only do the bare minimum to allow execution to continue to + board_init_f() +- this is almost never needed +- return normally from this function + +board_init_f() +~~~~~~~~~~~~~~ + +- purpose: set up the machine ready for running board_init_r(): + i.e. SDRAM and serial UART +- global_data is available +- stack is in SRAM +- BSS is not available, so you cannot use global/static variables, + only stack variables and global_data + +Non-xPL-specific notes: + + - dram_init() is called to set up DRAM. If already done in xPL this + can do nothing + +xPL-specific notes: + + - you can override the entire board_init_f() function with your own + version as needed. + - preloader_console_init() can be called here in extremis + - should set up SDRAM, and anything needed to make the UART work + - there is no need to clear BSS, it will be done by crt0.S + - for specific scenarios on certain architectures an early BSS *can* + be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing + of BSS prior to entering board_init_f()) but doing so is discouraged. + Instead it is strongly recommended to architect any code changes + or additions such to not depend on the availability of BSS during + board_init_f() as indicated in other sections of this README to + maintain compatibility and consistency across the entire code base. + - must return normally from this function (don't call board_init_r() + directly) + +Here the BSS is cleared. For xPL, if CONFIG_xPL_STACK_R is defined, then at +this point the stack and global_data are relocated to below +CONFIG_xPL_STACK_R_ADDR. For non-xPL, U-Boot is relocated to run at the top of +memory. + +board_init_r() +~~~~~~~~~~~~~~ + + - purpose: main execution, common code + - global_data is available + - SDRAM is available + - BSS is available, all static/global variables can be used + - execution eventually continues to main_loop() + +Non-xPL-specific notes: + + - U-Boot is relocated to the top of memory and is now running from + there. + +xPL-specific notes: + + - stack is optionally in SDRAM, if CONFIG_xPL_STACK_R is defined diff --git a/doc/develop/logging.rst b/doc/develop/logging.rst index 704a6bf1d84..d7a40c94bf0 100644 --- a/doc/develop/logging.rst +++ b/doc/develop/logging.rst @@ -292,7 +292,7 @@ Convert debug() statements in the code to log() statements Convert error() statements in the code to log() statements -Figure out what to do with BUG(), BUG_ON() and warn_non_spl() +Figure out what to do with BUG(), BUG_ON() and warn_non_xpl() Add a way to browse log records diff --git a/doc/develop/memory.rst b/doc/develop/memory.rst new file mode 100644 index 00000000000..e9e65ba4c6c --- /dev/null +++ b/doc/develop/memory.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Memory Management +----------------- + +.. note:: + + This information is outdated and needs to be updated. + +U-Boot runs in system state and uses physical addresses, i.e. the +MMU is not used either for address mapping nor for memory protection. + +The available memory is mapped to fixed addresses using the +memory-controller. In this process, a contiguous block is formed for each +memory type (Flash, SDRAM, SRAM), even when it consists of several +physical-memory banks. + +U-Boot is installed in XIP flash memory, or may be loaded into a lower region of +RAM by a secondary program loader (SPL). After +booting and sizing and initialising DRAM, the code relocates itself +to the upper end of DRAM. Immediately below the U-Boot code some +memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN +configuration setting]. Below that, a structure with global Board-Info +data is placed, followed by the stack (growing downward). + +Additionally, some exception handler code may be copied to the low 8 kB +of DRAM (0x00000000 ... 0x00001fff). + +So a typical memory configuration with 16 MB of DRAM could look like +this:: + + 0x0000 0000 Exception Vector code + : + 0x0000 1fff + 0x0000 2000 Free for Application Use + : + : + + : + : + 0x00fb ff20 Monitor Stack (Growing downward) + 0x00fb ffac Board Info Data and permanent copy of global data + 0x00fc 0000 Malloc Arena + : + 0x00fd ffff + 0x00fe 0000 RAM Copy of Monitor Code + ... eventually: LCD or video framebuffer + ... eventually: pRAM (Protected RAM - unchanged by reset) + 0x00ff ffff [End of RAM] diff --git a/doc/develop/qconfig.rst b/doc/develop/qconfig.rst index 123779eab17..a18f32470ca 100644 --- a/doc/develop/qconfig.rst +++ b/doc/develop/qconfig.rst @@ -226,7 +226,7 @@ Available options Look for moved config options in spl/include/autoconf.mk instead of include/autoconf.mk. This is useful for moving options for SPL build because SPL related options (mostly prefixed with CONFIG_SPL\_) are - sometimes blocked by CONFIG_SPL_BUILD ifdef conditionals. + sometimes blocked by CONFIG_XPL_BUILD ifdef conditionals. -j, --jobs Specify the number of threads to run simultaneously. If not specified, diff --git a/doc/develop/spl.rst b/doc/develop/spl.rst index 4bb48e6b7b3..aa6d28fa333 100644 --- a/doc/develop/spl.rst +++ b/doc/develop/spl.rst @@ -1,11 +1,12 @@ -Generic SPL framework +Generic xPL framework ===================== Overview -------- -To unify all existing implementations for a secondary program loader (SPL) -and to allow simply adding of new implementations this generic SPL framework +To unify all existing implementations for secondary/tertiary program loaders +(generically called xPL) +and to allow simply adding of new implementations this generic xPL framework has been created. With this framework almost all source files for a board can be reused. No code duplication or symlinking is necessary anymore. @@ -13,36 +14,39 @@ can be reused. No code duplication or symlinking is necessary anymore. How it works ------------ -The object files for SPL are built separately and placed in the "spl" directory. -The final binaries which are generated are u-boot-spl, u-boot-spl.bin and -u-boot-spl.map. +The object files for xPL are built separately and placed in a subdirectory +("spl", "tpl" or "vpl"). +The final binaries which are generated for SPL are u-boot-spl, u-boot-spl.bin +and u-boot-spl.map -A config option named CONFIG_SPL_BUILD is enabled by Kconfig for SPL. -Source files can therefore be compiled for SPL with different settings. +A config option named CONFIG_XPL_BUILD is enabled by Kconfig for xPL builds. +Source files can therefore be compiled for xPL with different settings. For example:: - ifeq ($(CONFIG_SPL_BUILD),y) + ifeq ($(CONFIG_XPL_BUILD),y) obj-y += board_spl.o else obj-y += board.o endif - obj-$(CONFIG_SPL_BUILD) += foo.o + obj-$(CONFIG_XPL_BUILD) += foo.o - #ifdef CONFIG_SPL_BUILD + if (IS_ENABLED(CONFIG_XPL_BUILD)) foo(); - #endif + if (xpl_phase() == PHASE_TPL) + bar(); -The building of SPL images can be enabled by CONFIG_SPL option in Kconfig. +The building of xPL images can be enabled by CONFIG_SPL (etc.) options in +Kconfig. -Because SPL images normally have a different text base, one has to be -configured by defining CONFIG_SPL_TEXT_BASE. The linker script has to be -defined with CONFIG_SPL_LDSCRIPT. +Because xPL images normally have a different text base, one has to be +configured by defining CONFIG_xPL_TEXT_BASE. The linker script has to be +defined with CONFIG_xPL_LDSCRIPT. -To support generic U-Boot libraries and drivers in the SPL binary one can -optionally define CONFIG_SPL_XXX_SUPPORT. Currently following options +To support generic U-Boot libraries and drivers in the xPL binary one can +optionally define CONFIG_xPL_XXX_SUPPORT. Currently following options are supported: CONFIG_SPL_LIBCOMMON_SUPPORT (common/libcommon.o) @@ -75,7 +79,7 @@ CONFIG_SPL_DM_GPIO (drivers/gpio/gpio-uclass.o) CONFIG_SPL_BMP (drivers/video/bmp.o) CONFIG_SPL_BLOBLIST (common/bloblist.o) -Adding SPL-specific code +Adding xPL-specific code ------------------------ To check whether a feature is enabled, use CONFIG_IS_ENABLED():: @@ -90,7 +94,7 @@ U-Boot Boot Phases ------------------ U-Boot goes through the following boot phases where TPL, VPL, SPL are optional. -While many boards use SPL, less use TPL. +While many boards use SPL, fewer use TPL. TPL Very early init, as tiny as possible. This loads SPL (or VPL if enabled). @@ -117,7 +121,7 @@ Further usages of U-Boot SPL comprise: Checking the boot phase ----------------------- -Use `spl_phase()` to find the current U-Boot phase, e.g. `PHASE_SPL`. You can +Use `xpl_phase()` to find the current U-Boot phase, e.g. `PHASE_SPL`. You can also find the previous and next phase and get the phase name. @@ -177,29 +181,30 @@ files instead introduces another set of headaches. These warnings are not usually important to understanding the flow, however. -Reserving memory in SPL +Reserving memory in xPL ----------------------- -If memory needs to be reserved in RAM during SPL stage with the requirement that -the SPL reserved memory remains preserved across further boot stages too +If memory needs to be reserved in RAM during an xPL phase with the requirement +that the xPL reserved memory remains preserved across further boot phases too then it needs to be reserved mandatorily starting from end of RAM. This is to -ensure that further stages can simply skip this region before carrying out +ensure that further phases can simply skip this region before carrying out further reservations or updating the relocation address. -Also out of these regions which are to be preserved across further stages of +Also out of these regions which are to be preserved across further phases of boot, video framebuffer memory region must be reserved first starting from -end of RAM for which helper function spl_reserve_video_from_ram_top is provided -which makes sure that video memory is placed at top of reservation area with +end of RAM for which the helper function spl_reserve_video_from_ram_top() is +provided +which makes sure that video memory is placed at the top of reservation area with further reservations below it. -The corresponding information of reservation for those regions can be passed to -further boot stages using a bloblist. For e.g. the information for -framebuffer area reserved by SPL can be passed onto U-boot using -BLOBLISTT_U_BOOT_VIDEO. - -The further boot stages need to parse each of the bloblist passed from SPL stage -starting from video bloblist and skip this whole SPL reserved memory area from -end of RAM as per the bloblists received, before carrying out further -reservations or updating the relocation address. For e.g, U-boot proper uses -function "setup_relocaddr_from_bloblist" to parse the bloblists passed from -previous stage and skip the memory reserved from previous stage accordingly. +The reservation information for these regions can be passed to the +further boot phases using a bloblist. For e.g. the information for the +framebuffer area reserved by xPL can be passed onto U-Boot using +BLOBLISTT_U_BOOT_VIDEO + +The further boot phases need to parse each of the blobs passed from xPL phase +starting from video bloblist and skip this whole xPL reserved-memory area from +end of RAM as per the blobs received, before carrying out further +reservations or updating the relocation address. For e.g, U-Boot proper uses +function setup_relocaddr_from_bloblist() to parse the bloblist passed from +previous phase and skip the memory reserved from previous phase accordingly. diff --git a/doc/develop/tests_sandbox.rst b/doc/develop/tests_sandbox.rst index 72923070150..0630180bc55 100644 --- a/doc/develop/tests_sandbox.rst +++ b/doc/develop/tests_sandbox.rst @@ -278,7 +278,7 @@ Whatever sandbox build is used, which tests are present is determined by which source files are built. For sandbox_spl, the of_platdata tests are built because of the build rule in test/dm/Makefile:: - ifeq ($(CONFIG_SPL_BUILD),y) + ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_SPL_OF_PLATDATA) += of_platdata.o else ...other tests for non-spl diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst index a328ebfef33..54efb7e1b04 100644 --- a/doc/develop/tests_writing.rst +++ b/doc/develop/tests_writing.rst @@ -321,15 +321,15 @@ to control that. Finally, add the test to the build by adding to the Makefile in the same directory:: - obj-$(CONFIG_$(SPL_)CMDLINE) += wibble.o + obj-$(CONFIG_$(XPL_)CMDLINE) += wibble.o Note that CMDLINE is never enabled in SPL, so this test will only be present in U-Boot proper. See below for how to do SPL tests. As before, you can add an extra Kconfig check if needed:: - ifneq ($(CONFIG_$(SPL_)WIBBLE),) - obj-$(CONFIG_$(SPL_)CMDLINE) += wibble.o + ifneq ($(CONFIG_$(XPL_)WIBBLE),) + obj-$(CONFIG_$(XPL_)CMDLINE) += wibble.o endif diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index 94482758573..0760ca91d4f 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -720,7 +720,7 @@ Executing the built in hello world application A hello world UEFI application can be built with:: - CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y + CONFIG_BOOTEFI_HELLO_COMPILE=y It can be embedded into the U-Boot binary with:: diff --git a/doc/device-tree-bindings/bootph.yaml b/doc/device-tree-bindings/bootph.yaml index a3ccf06efa7..a364b3fe37f 100644 --- a/doc/device-tree-bindings/bootph.yaml +++ b/doc/device-tree-bindings/bootph.yaml @@ -83,6 +83,6 @@ properties: bootph-all: type: boolean description: - Include this node in all phases (for U-Boot see enum u_boot_phase). + Include this node in all phases (for U-Boot see enum xpl_phase_t). additionalProperties: true diff --git a/drivers/Makefile b/drivers/Makefile index 1acd94f3c17..9440af1b09b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,60 +1,60 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_$(SPL_TPL_)ADC) += adc/ -obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/ -obj-$(CONFIG_$(SPL_TPL_)BLK) += block/ -obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ -obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ -obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/ -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ -obj-$(CONFIG_$(SPL_TPL_)DM) += core/ -obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/ -obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/ -obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ -obj-$(CONFIG_$(SPL_TPL_)EXTCON) += extcon/ -obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/ -obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/ -obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/ -obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) +=firmware/ -obj-$(CONFIG_$(SPL_TPL_)I2C) += i2c/ -obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ -obj-$(CONFIG_$(SPL_TPL_)LED) += led/ -obj-$(CONFIG_$(SPL_TPL_)MMC) += mmc/ +obj-$(CONFIG_$(PHASE_)ADC) += adc/ +obj-$(CONFIG_$(PHASE_)BIOSEMU) += bios_emulator/ +obj-$(CONFIG_$(PHASE_)BLK) += block/ +obj-$(CONFIG_$(PHASE_)BOOTCOUNT_LIMIT) += bootcount/ +obj-$(CONFIG_$(PHASE_)BUTTON) += button/ +obj-$(CONFIG_$(PHASE_)CACHE) += cache/ +obj-$(CONFIG_$(PHASE_)CLK) += clk/ +obj-$(CONFIG_$(PHASE_)DM) += core/ +obj-$(CONFIG_$(PHASE_)DMA) += dma/ +obj-$(CONFIG_$(PHASE_)DMA_LEGACY) += dma/ +obj-$(CONFIG_$(PHASE_)DFU) += dfu/ +obj-$(CONFIG_$(PHASE_)EXTCON) += extcon/ +obj-$(CONFIG_$(PHASE_)GPIO) += gpio/ +obj-$(CONFIG_$(PHASE_)DRIVERS_MISC) += misc/ +obj-$(CONFIG_$(PHASE_)SYSRESET) += sysreset/ +obj-$(CONFIG_$(PHASE_)FIRMWARE) +=firmware/ +obj-$(CONFIG_$(PHASE_)I2C) += i2c/ +obj-$(CONFIG_$(PHASE_)INPUT) += input/ +obj-$(CONFIG_$(PHASE_)LED) += led/ +obj-$(CONFIG_$(PHASE_)MMC) += mmc/ obj-y += mtd/ -obj-$(CONFIG_$(SPL_TPL_)ETH) += net/ -obj-$(CONFIG_$(SPL_TPL_)PCH) += pch/ -obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/ -obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/ -obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/ -obj-$(CONFIG_$(SPL_TPL_)POWER) += power/ -obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/ -obj-$(CONFIG_$(SPL_TPL_)RTC) += rtc/ -obj-$(CONFIG_$(SPL_TPL_)SERIAL) += serial/ -obj-$(CONFIG_$(SPL_TPL_)SPI) += spi/ -obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/ -obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ -obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ -obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ -obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ -obj-$(CONFIG_$(SPL_TPL_)SM) += sm/ -obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ -obj-$(CONFIG_$(SPL_)NVME) += nvme/ +obj-$(CONFIG_$(PHASE_)ETH) += net/ +obj-$(CONFIG_$(PHASE_)PCH) += pch/ +obj-$(CONFIG_$(PHASE_)PCI) += pci/ +obj-$(CONFIG_$(PHASE_)PHY) += phy/ +obj-$(CONFIG_$(PHASE_)PINCTRL) += pinctrl/ +obj-$(CONFIG_$(PHASE_)POWER) += power/ +obj-$(CONFIG_$(PHASE_)RAM) += ram/ +obj-$(CONFIG_$(PHASE_)RTC) += rtc/ +obj-$(CONFIG_$(PHASE_)SERIAL) += serial/ +obj-$(CONFIG_$(PHASE_)SPI) += spi/ +obj-$(CONFIG_$(PHASE_)TIMER) += timer/ +obj-$(CONFIG_$(PHASE_)VIRTIO) += virtio/ +obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox/ +obj-$(CONFIG_$(XPL_)REMOTEPROC) += remoteproc/ +obj-$(CONFIG_$(XPL_)SYSINFO) += sysinfo/ +obj-$(CONFIG_$(PHASE_)SM) += sm/ +obj-$(CONFIG_$(PHASE_)TPM) += tpm/ +obj-$(CONFIG_$(XPL_)NVME) += nvme/ obj-$(CONFIG_XEN) += xen/ -obj-$(CONFIG_$(SPL_)FPGA) += fpga/ -obj-$(CONFIG_$(SPL_)VIDEO) += video/ +obj-$(CONFIG_$(XPL_)FPGA) += fpga/ +obj-$(CONFIG_$(XPL_)VIDEO) += video/ obj-y += bus/ ifndef CONFIG_TPL_BUILD ifndef CONFIG_VPL_BUILD -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_CPU) += cpu/ obj-$(CONFIG_SPL_CRYPTO) += crypto/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ -obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ +obj-$(CONFIG_$(XPL_)ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/ obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/ @@ -80,7 +80,7 @@ obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/ endif -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) obj-y += ata/ obj-$(CONFIG_DM_DEMO) += demo/ @@ -126,7 +126,7 @@ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/ obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ obj-$(CONFIG_FUZZ) += fuzz/ obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/ -obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng/ +obj-$(CONFIG_$(PHASE_)DM_RNG) += rng/ endif obj-y += soc/ diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index dca0b39c2e2..665a7965412 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile @@ -4,7 +4,7 @@ # Przemyslaw Marczak <p.marczak@samsung.com> # -obj-$(CONFIG_$(SPL_TPL_)ADC) += adc-uclass.o +obj-$(CONFIG_$(PHASE_)ADC) += adc-uclass.o obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o obj-$(CONFIG_ADC_SANDBOX) += sandbox.o obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index af6f0bf2780..ee10c4445b0 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o obj-$(CONFIG_AHCI) += ahci-uclass.o -obj-$(CONFIG_$(SPL_)AHCI_PCI) += ahci-pci.o +obj-$(CONFIG_$(XPL_)AHCI_PCI) += ahci-pci.o obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o diff --git a/drivers/block/Makefile b/drivers/block/Makefile index fe6a1fcf486..ee290620545 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -3,20 +3,20 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_$(SPL_TPL_)BLK) += blk-uclass.o +obj-$(CONFIG_$(PHASE_)BLK) += blk-uclass.o -ifndef CONFIG_$(SPL_)BLK +ifndef CONFIG_$(XPL_)BLK obj-$(CONFIG_SPL_LEGACY_BLOCK) += blk_legacy.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_IDE) += ide.o obj-$(CONFIG_RKMTD) += rkmtd.o endif obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o -obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o -obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap.o -obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap_helper.o +obj-$(CONFIG_$(PHASE_)BLOCK_CACHE) += blkcache.o +obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap.o +obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap_helper.o obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 0802b9666bf..7daf8247247 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -3,9 +3,9 @@ # Makefile for the bus drivers. # -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) obj-$(CONFIG_TI_PWMSS) += ti-pwmss.o obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o endif -obj-$(CONFIG_$(SPL_)TI_SYSC) += ti-sysc.o +obj-$(CONFIG_$(XPL_)TI_SYSC) += ti-sysc.o diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index e1b71e0ed51..2f683866b87 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -1,5 +1,5 @@ -obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o +obj-$(CONFIG_$(PHASE_)CACHE) += cache-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_cache.o obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f9b90a38b00..7f84f22d4b1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -4,13 +4,13 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o -obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o -obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o +obj-$(CONFIG_$(PHASE_)CLK) += clk-uclass.o +obj-$(CONFIG_$(PHASE_)CLK) += clk_fixed_rate.o +obj-$(CONFIG_$(PHASE_)CLK) += clk_fixed_factor.o +obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o +obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-fixed-factor.o +obj-$(CONFIG_$(PHASE_)CLK_COMPOSITE_CCF) += clk-composite.o +obj-$(CONFIG_$(PHASE_)CLK_GPIO) += clk-gpio.o obj-y += adi/ obj-y += analogbits/ @@ -18,7 +18,7 @@ obj-y += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ -obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ +obj-$(CONFIG_$(PHASE_)CLK_INTEL) += intel/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_MESON) += meson/ @@ -42,7 +42,7 @@ obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_QCOM) += qcom/ obj-$(CONFIG_CLK_RENESAS) += renesas/ -obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o +obj-$(CONFIG_$(PHASE_)CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_CLK_SOPHGO) += sophgo/ obj-$(CONFIG_CLK_SUNXI) += sunxi/ diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index bdc7be0fb5d..e1ddd02f356 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -242,7 +242,7 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Always force clock manager into boot mode before any configuration */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index 72b923465df..716c71598bc 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -263,7 +263,7 @@ static void clk_basic_init(struct udevice *dev, clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); } else { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Always force clock manager into boot mode before any configuration */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 3e256101a94..09db250ab6d 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -52,7 +52,7 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return; -#if IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) /* Always force clock manager into boot mode before any configuration */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 16169dac234..a9937c22dcb 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -378,7 +378,7 @@ int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage) * However, still set them for SPL. And still set them if explicitly * asked. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC))) + if (!(IS_ENABLED(CONFIG_XPL_BUILD) || (gd->flags & GD_FLG_RELOC))) if (stage != CLK_DEFAULTS_POST_FORCE) return 0; diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c index 2e0e7bbe68f..85ac92c908a 100644 --- a/drivers/clk/clk_vexpress_osc.c +++ b/drivers/clk/clk_vexpress_osc.c @@ -37,7 +37,7 @@ static ulong vexpress_osc_clk_get_rate(struct clk *clk) return data; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate) { int err; @@ -64,7 +64,7 @@ static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate) static struct clk_ops vexpress_osc_clk_ops = { .get_rate = vexpress_osc_clk_get_rate, -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD .set_rate = vexpress_osc_clk_set_rate, #endif }; diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index b62b4646f4e..a8505f62bba 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -43,13 +43,13 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD enum zynq_clk_rclk {mio_clk, emio_clk}; #endif struct zynq_clk_priv { ulong ps_clk_freq; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD struct clk gem_emio_clk[2]; #endif }; @@ -75,7 +75,7 @@ static void *zynq_clk_get_register(enum zynq_clk id) return &slcr_base->uart_clk_ctrl; case spi0_clk ... spi1_clk: return &slcr_base->spi_clk_ctrl; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case dci_clk: return &slcr_base->dci_clk_ctrl; case gem0_clk: @@ -150,7 +150,7 @@ static ulong zynq_clk_get_pll_rate(struct zynq_clk_priv *priv, enum zynq_clk id) return priv->ps_clk_freq * mul; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum zynq_clk id) { u32 clk_ctrl, srcsel; @@ -199,7 +199,7 @@ static ulong zynq_clk_get_cpu_rate(struct zynq_clk_priv *priv, enum zynq_clk id) return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, pll), div); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong zynq_clk_get_ddr2x_rate(struct zynq_clk_priv *priv) { u32 clk_ctrl, div; @@ -223,7 +223,7 @@ static ulong zynq_clk_get_ddr3x_rate(struct zynq_clk_priv *priv) return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong zynq_clk_get_dci_rate(struct zynq_clk_priv *priv) { u32 clk_ctrl, div0, div1; @@ -251,7 +251,7 @@ static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv, if (!div0) div0 = 1; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD if (two_divs) { div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; if (!div1) @@ -268,7 +268,7 @@ static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv, div1); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id) { struct clk *parent; @@ -366,7 +366,7 @@ static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id, } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong zynq_clk_get_rate(struct clk *clk) { struct zynq_clk_priv *priv = dev_get_priv(clk->dev); @@ -502,7 +502,7 @@ static void zynq_clk_dump(struct udevice *dev) static struct clk_ops zynq_clk_ops = { .get_rate = zynq_clk_get_rate, -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD .set_rate = zynq_clk_set_rate, #endif .enable = dummy_enable, @@ -514,7 +514,7 @@ static struct clk_ops zynq_clk_ops = { static int zynq_clk_probe(struct udevice *dev) { struct zynq_clk_priv *priv = dev_get_priv(dev); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD unsigned int i; char name[16]; int ret; diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile index 734100e2bff..77385864fef 100644 --- a/drivers/clk/exynos/Makefile +++ b/drivers/clk/exynos/Makefile @@ -7,6 +7,6 @@ # Thomas Abraham <thomas.ab@samsung.com> # Sam Protsenko <semen.protsenko@linaro.org> -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o +obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk.o clk-pll.o obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o obj-$(CONFIG_CLK_EXYNOS850) += clk-exynos850.o diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 6d4bcd35714..a89ee7acb12 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -2,25 +2,25 @@ # # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX6Q) += clk-imx6q.o +obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o +obj-$(CONFIG_$(PHASE_)CLK_IMX6Q) += clk-imx6q.o obj-$(CONFIG_CLK_IMX8) += clk-imx8.o ifdef CONFIG_CLK_IMX8 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o obj-$(CONFIG_IMX8QM) += clk-imx8qm.o endif -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \ clk-gate-93.o clk-composite-93.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o +obj-$(CONFIG_$(PHASE_)CLK_IMXRT1020) += clk-imxrt1020.o +obj-$(CONFIG_$(PHASE_)CLK_IMXRT1050) += clk-imxrt1050.o +obj-$(CONFIG_$(PHASE_)CLK_IMXRT1170) += clk-imxrt1170.o diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index a91c6767fac..bb6958f0ec2 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -31,7 +31,7 @@ static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; @@ -95,7 +95,7 @@ static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_ "sys_pll1_160m", "sys_pll1_200m", }; #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; @@ -357,7 +357,7 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD clk_dm(IMX8MM_CLK_ENET_AXI, imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880)); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 125215e84f4..be15ebd0e25 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -37,7 +37,7 @@ static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_2 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", }; @@ -97,7 +97,7 @@ static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m" "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; @@ -359,7 +359,7 @@ static int imx8mn_clk_probe(struct udevice *dev) imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD clk_dm(IMX8MN_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980)); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 34d91cd6880..1d04090ca00 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -197,6 +197,8 @@ static int imx8mp_clk_probe(struct udevice *dev) base = (void *)ANATOP_BASE_ADDR; + clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0)); + clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index c80b02975aa..752434cb0ad 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -124,7 +124,7 @@ static int imxrt1020_clk_probe(struct udevice *dev) clk_dm(IMXRT1020_CLK_SEMC, imx_clk_gate2("semc", "semc_podf", base + 0x74, 4)); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct clk *clk, *clk1; clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1); diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 754f3948427..788e0650a92 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -180,7 +180,7 @@ static int imxrt1050_clk_probe(struct udevice *dev) struct clk *clk, *clk1; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* bypass pll1 before setting its rate */ clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk); clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1); diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 72ad4fd0e85..51f124869c9 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -66,6 +66,8 @@ #define CLKID_VDEC_HEVC_SEL 154 #define CLKID_VDEC_HEVC_DIV 155 +#define CLKID_XTAL 0x10000000 + #define XTAL_RATE 24000000 struct meson_clk { @@ -192,6 +194,7 @@ static struct meson_gate gates[] = { MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8), MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24), MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30), + MESON_GATE(CLKID_HDMI, HHI_HDMI_CLK_CNTL, 8), }; static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on) @@ -267,6 +270,12 @@ static struct parm meson_vapb_1_div_parm = { int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL; +static struct parm meson_hdmi_div_parm = { + HHI_HDMI_CLK_CNTL, 0, 7, +}; + +int meson_hdmi_div_parent = CLKID_HDMI_SEL; + static ulong meson_div_get_rate(struct clk *clk, unsigned long id) { struct meson_clk *priv = dev_get_priv(clk->dev); @@ -292,6 +301,10 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id) parm = &meson_vapb_1_div_parm; parent = meson_vapb_1_div_parent; break; + case CLKID_HDMI_DIV: + parm = &meson_hdmi_div_parm; + parent = meson_hdmi_div_parent; + break; default: return -ENOENT; } @@ -347,6 +360,10 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, parm = &meson_vapb_1_div_parm; parent = meson_vapb_1_div_parent; break; + case CLKID_HDMI_DIV: + parm = &meson_hdmi_div_parm; + parent = meson_hdmi_div_parent; + break; default: return -ENOENT; } @@ -443,6 +460,17 @@ static int meson_vapb_0_1_mux_parents[] = { CLKID_FCLK_DIV7, }; +static struct parm meson_hdmi_mux_parm = { + HHI_HDMI_CLK_CNTL, 9, 2, +}; + +static int meson_hdmi_mux_parents[] = { + CLKID_XTAL, + CLKID_FCLK_DIV4, + CLKID_FCLK_DIV3, + CLKID_FCLK_DIV5, +}; + static ulong meson_mux_get_parent(struct clk *clk, unsigned long id) { struct meson_clk *priv = dev_get_priv(clk->dev); @@ -475,6 +503,10 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id) parm = &meson_vapb_1_mux_parm; parents = meson_vapb_0_1_mux_parents; break; + case CLKID_HDMI_SEL: + parm = &meson_hdmi_mux_parm; + parents = meson_hdmi_mux_parents; + break; default: return -ENOENT; } @@ -532,6 +564,10 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id, parm = &meson_vapb_1_mux_parm; parents = meson_vapb_0_1_mux_parents; break; + case CLKID_HDMI_SEL: + parm = &meson_hdmi_mux_parm; + parents = meson_hdmi_mux_parents; + break; default: /* Not a mux */ return -ENOENT; @@ -572,7 +608,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) unsigned long parent_rate; uint reg; int parents[] = { - -1, + CLKID_XTAL, -1, CLKID_FCLK_DIV7, CLKID_MPLL1, @@ -727,6 +763,9 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) ulong rate; switch (id) { + case CLKID_XTAL: + rate = XTAL_RATE; + break; case CLKID_FIXED_PLL: case CLKID_SYS_PLL: rate = meson_pll_get_rate(clk, id); @@ -769,10 +808,14 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) case CLKID_VAPB_1: rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV); break; + case CLKID_HDMI: + rate = meson_div_get_rate(clk, CLKID_HDMI_DIV); + break; case CLKID_VPU_0_DIV: case CLKID_VPU_1_DIV: case CLKID_VAPB_0_DIV: case CLKID_VAPB_1_DIV: + case CLKID_HDMI_DIV: rate = meson_div_get_rate(clk, id); break; case CLKID_VPU: @@ -781,6 +824,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) case CLKID_VAPB_SEL: case CLKID_VAPB_0_SEL: case CLKID_VAPB_1_SEL: + case CLKID_HDMI_SEL: rate = meson_mux_get_rate(clk, id); break; default: @@ -851,7 +895,11 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id, case CLKID_VPU_1_DIV: case CLKID_VAPB_0_DIV: case CLKID_VAPB_1_DIV: + case CLKID_HDMI_DIV: return meson_div_set_rate(clk, id, rate, current_rate); + case CLKID_HDMI: + return meson_clk_set_rate_by_id(clk, CLKID_HDMI_DIV, + rate, current_rate); default: return -ENOENT; } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index b44d5603edd..7875a990c2f 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -55,6 +55,17 @@ enum clk_ids { DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \ .offset = _offset) +#define CPG_PLL20CR 0x0834 /* PLL20 Control Register */ +#define CPG_PLL21CR 0x0838 /* PLL21 Control Register */ +#define CPG_PLL30CR 0x083c /* PLL30 Control Register */ +#define CPG_PLL31CR 0x0840 /* PLL31 Control Register */ + +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ + static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -64,10 +75,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), - DEF_PLL(".pll20", CLK_PLL20, 0x0834), - DEF_PLL(".pll21", CLK_PLL21, 0x0838), - DEF_PLL(".pll30", CLK_PLL30, 0x083c), - DEF_PLL(".pll31", CLK_PLL31, 0x0840), + DEF_PLL(".pll20", CLK_PLL20, CPG_PLL20CR), + DEF_PLL(".pll21", CLK_PLL21, CPG_PLL21CR), + DEF_PLL(".pll30", CLK_PLL30, CPG_PLL30CR), + DEF_PLL(".pll31", CLK_PLL31, CPG_PLL31CR), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), @@ -110,17 +121,17 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), - DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), - DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), + DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR), + DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, CPG_SD0CKCR), DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779A0_CLK_RPC), - DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), - DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), - DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), - DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884), + DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR), + DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR), + DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, CPG_CSICKCR), + DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, CPG_DSIEXTCKCR), DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index ea98bc6e50c..fdca63a3e8e 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -15,6 +15,12 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A779F0_CLK_R, @@ -110,13 +116,13 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1), DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1), - DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870), - DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870), + DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR), + DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, CPG_SD0CKCR), DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), - DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR), DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 4df0a69cfe1..9fb672a5369 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -15,6 +15,12 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A779G0_CLK_CP, @@ -141,14 +147,14 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1), DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), - DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), - DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880), + DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR), + DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, CPG_CSICKCR), DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), - DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), + DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, CPG_DSIEXTCKCR), - DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870), - DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870), - DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR), + DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, CPG_SD0CKCR), + DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR), DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC), diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index b20d559bee2..2e98e262fb0 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -15,6 +15,12 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A779H0_CLK_R, @@ -155,14 +161,14 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1), DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1), DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1), - DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), - DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, 0x880), + DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR), + DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, CPG_CSICKCR), DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), - DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), - DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, CPG_DSIEXTCKCR), + DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR), - DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, 0x870), - DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, 0x870), + DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR), + DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, CPG_SD0CKCR), DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC), @@ -175,6 +181,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), + DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), @@ -183,14 +192,57 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER), DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER), DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER), + DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M), + DEF_MOD("ispcs0", 612, R8A779H0_CLK_S0D2_VIO), + DEF_MOD("ispcs1", 613, R8A779H0_CLK_S0D2_VIO), + DEF_MOD("msi0", 618, R8A779H0_CLK_MSO), + DEF_MOD("msi1", 619, R8A779H0_CLK_MSO), + DEF_MOD("msi2", 620, R8A779H0_CLK_MSO), + DEF_MOD("msi3", 621, R8A779H0_CLK_MSO), + DEF_MOD("msi4", 622, R8A779H0_CLK_MSO), + DEF_MOD("msi5", 623, R8A779H0_CLK_MSO), + DEF_MOD("pcie0", 624, R8A779H0_CLK_S0D2_HSC), + DEF_MOD("pwm", 628, R8A779H0_CLK_SASYNCPERD4), DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), + DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4), + DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4), + DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4), + DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4), DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0), DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER), DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER), + DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT), + DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("vin00", 730, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin01", 731, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin02", 800, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin03", 801, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin04", 802, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin05", 803, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin06", 804, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin07", 805, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin10", 806, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin11", 807, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin12", 808, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin13", 809, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin14", 810, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), + DEF_MOD("cmt0", 910, R8A779H0_CLK_R), + DEF_MOD("cmt1", 911, R8A779H0_CLK_R), + DEF_MOD("cmt2", 912, R8A779H0_CLK_R), + DEF_MOD("cmt3", 913, R8A779H0_CLK_R), DEF_MOD("pfc0", 915, R8A779H0_CLK_CP), DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), + DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), + DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), + DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), }; /* diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index d7825c66493..22ede1c38a8 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -989,7 +989,7 @@ static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, return px30_peri_get_clk(priv, clk_id); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id) { struct px30_cru *cru = priv->cru; @@ -1261,7 +1261,7 @@ static ulong px30_clk_get_rate(struct clk *clk) case HCLK_PERI_PRE: rate = px30_peri_get_clk(priv, clk->id); break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case SCLK_CRYPTO: case SCLK_CRYPTO_APK: rate = px30_crypto_get_clk(priv, clk->id); @@ -1345,7 +1345,7 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate) case HCLK_PERI_PRE: ret = px30_peri_set_clk(priv, clk->id, rate); break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case SCLK_CRYPTO: case SCLK_CRYPTO_APK: ret = px30_crypto_set_clk(priv, clk->id, rate); diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index f569a100f22..d8b03e1d7ab 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -80,7 +80,7 @@ enum { "divisors on line " __stringify(__LINE__)); /* Keep divisors as low as possible to reduce jitter and power usage */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); #endif @@ -371,7 +371,7 @@ static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate, return rockchip_spi_get_clk(cru, gclk_rate, periph); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf, bool has_bwadj) { @@ -557,7 +557,7 @@ static int rk3188_clk_probe(struct udevice *dev) return PTR_ERR(priv->grf); priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3188_clk_plat *plat = dev_get_plat(dev); diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 432a79291c8..43c44fadbe7 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -223,7 +223,7 @@ static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf, return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define VCO_MAX_KHZ 2200000 #define VCO_MIN_KHZ 440000 #define FREF_MAX_KHZ 2200000 @@ -421,7 +421,7 @@ static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate, return rockchip_i2s_get_clk(cru, gclk_rate); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf) { @@ -819,7 +819,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI2: new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case SCLK_I2S0: new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate); break; @@ -973,7 +973,7 @@ static int rk3288_clk_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(priv->grf)) return PTR_ERR(priv->grf); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3288_clk_plat *plat = dev_get_plat(dev); diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 9137dbe69ce..7701a9734ee 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -582,7 +582,7 @@ static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) return rk3328_spi_get_clk(cru); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id) { struct rk3328_cru *cru = priv->cru; @@ -746,7 +746,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI: ret = rk3328_spi_set_clk(priv->cru, rate); break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case DCLK_LCDC: case ACLK_VOP_PRE: case ACLK_VIO_PRE: diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index d8943980521..630253fbb1d 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -50,7 +50,7 @@ struct pll_div { (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \ "divisors on line " __stringify(__LINE__)); -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); #if !defined(CONFIG_TPL_BUILD) @@ -88,7 +88,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, } } -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, const struct pll_div *div) { @@ -130,7 +130,7 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, } #endif -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static void rkclk_init(struct rk3368_cru *cru) { u32 apllb, aplll, dpll, cpll, gpll; @@ -157,7 +157,7 @@ static void rkclk_init(struct rk3368_cru *cru) } #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) +#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC) static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) { u32 div, con, con_id, rate; @@ -469,7 +469,7 @@ static ulong rk3368_clk_get_rate(struct clk *clk) case SCLK_SPI0 ... SCLK_SPI2: rate = rk3368_spi_get_clk(priv->cru, clk->id); break; -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) +#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: rate = rk3368_mmc_get_clk(priv->cru, clk->id); @@ -500,7 +500,7 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret = rk3368_ddr_set_clk(priv->cru, rate); break; #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) +#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: ret = rk3368_mmc_set_clk(clk, rate); @@ -586,7 +586,7 @@ static int rk3368_clk_probe(struct udevice *dev) priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) rkclk_init(priv->cru); #endif diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 89924041299..155ea8d6353 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -56,7 +56,7 @@ struct pll_div { static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); #endif @@ -1464,7 +1464,7 @@ static int rk3399_clk_probe(struct udevice *dev) priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) init_clocks = true; #elif CONFIG_IS_ENABLED(HANDOFF) if (!(gd->flags & GD_FLG_RELOC)) { @@ -1658,7 +1658,7 @@ static struct clk_ops rk3399_pmuclk_ops = { .set_rate = rk3399_pmuclk_set_rate, }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static void pmuclk_init(struct rk3399_pmucru *pmucru) { u32 pclk_div; @@ -1676,7 +1676,7 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru) static int rk3399_pmuclk_probe(struct udevice *dev) { -#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) +#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_XPL_BUILD) struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); #endif @@ -1686,7 +1686,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev) priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD pmuclk_init(priv->pmucru); #endif return 0; diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 35563509d61..977699d509d 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -91,7 +91,7 @@ static struct rockchip_pll_clock rk3568_pll_clks[] = { RK3568_PMU_MODE, 2, 10, 0, rk3568_pll_rates), }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3568_pmu_pll_set_rate(struct rk3568_clk_priv *priv, ulong pll_id, ulong rate) @@ -1707,7 +1707,7 @@ static ulong rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate) return rk3568_emmc_get_bclk(priv); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3568_aclk_vop_get_clk(struct rk3568_clk_priv *priv) { struct rk3568_cru *cru = priv->cru; @@ -2413,7 +2413,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case TCLK_EMMC: rate = OSC_HZ; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case ACLK_VOP: rate = rk3568_aclk_vop_get_clk(priv); break; @@ -2594,7 +2594,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case TCLK_EMMC: ret = OSC_HZ; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case ACLK_VOP: ret = rk3568_aclk_vop_set_clk(priv, rate); break; @@ -2894,7 +2894,7 @@ static void rk3568_clk_init(struct rk3568_clk_priv *priv) priv->gpll_hz = GPLL_HZ; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD ret = rk3568_bus_set_clk(priv, ACLK_BUS, 150000000); if (ret < 0) printf("Fail to set the ACLK_BUS clock.\n"); diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index db1384dacd2..6042fc10cdb 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -65,7 +65,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = { RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128), RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * The SPLL is part of the SBUSCRU, not the main CRU and as * such only directly accessible during the SPL stage. @@ -76,7 +76,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = { }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * * rational_best_approximation(31415, 10000, @@ -875,7 +875,7 @@ static ulong rk3588_mmc_set_clk(struct rk3588_clk_priv *priv, return rk3588_mmc_get_clk(priv, clk_id); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3588_aux16m_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) { struct rk3588_cru *cru = priv->cru; @@ -1600,7 +1600,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk) case CLK_GPU: rate = 200000000; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: rate = rk3588_aux16m_get_clk(priv, clk->id); @@ -1760,7 +1760,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) case CLK_150M_SRC: ret = 0; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: ret = rk3588_aux16m_set_clk(priv, clk->id, rate); @@ -1965,7 +1965,7 @@ static int rk3588_clk_probe(struct udevice *dev) priv->sync_kernel = false; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD rockchip_pll_set_rate(&rk3588_pll_clks[B0PLL], priv->cru, B0PLL, LPLL_HZ); rockchip_pll_set_rate(&rk3588_pll_clks[B1PLL], priv->cru, @@ -2051,7 +2051,7 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = { .probe = rk3588_clk_probe, }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SCRU_BASE 0xfd7d0000 #define SBUSCRU_BASE 0xfd7d8000 diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index aa26d3a109b..de55504b5c9 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -670,7 +670,7 @@ static int sifive_prci_probe(struct udevice *dev) __prci_wrpll_read_cfg0(pd, pc->pwd); } - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { if (device_is_compatible(dev, "sifive,fu740-c000-prci")) { u32 prci_pll_reg; unsigned long parent_rate; diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 581035842fc..6d2bfb3ecb7 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -348,10 +348,10 @@ struct clk *starfive_jh7110_pll(const char *name, const char *parent_name, return ERR_PTR(ret); } - if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL0) + if (IS_ENABLED(CONFIG_XPL_BUILD) && pll->type == PLL0) jh7110_pllx_set_rate(clk, 1000000000); - if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL2) + if (IS_ENABLED(CONFIG_XPL_BUILD) && pll->type == PLL2) jh7110_pllx_set_rate(clk, 1188000000); return clk; diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 204ac170531..4044edfb768 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* activate clock tree initialization in the driver */ #define STM32MP1_CLOCK_TREE_INIT #endif @@ -2279,7 +2279,7 @@ static int stm32mp1_clk_probe(struct udevice *dev) dev_err(dev, "clock tree initialization failed (%d)\n", result); #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(VERBOSE_DEBUG) /* display debug information for probe after relocation */ if (gd->flags & GD_FLG_RELOC) @@ -2314,7 +2314,7 @@ static const struct clk_ops stm32mp1_clk_ops = { .disable = stm32mp1_clk_disable, .get_rate = stm32mp1_clk_get_rate, .set_rate = stm32mp1_clk_set_rate, -#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_XPL_BUILD) .dump = stm32mp1_clk_dump, #endif }; diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 6751af8a803..091aaeee987 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -75,10 +75,10 @@ static const struct ccu_clk_gate a80_mmc_gates[] = { }; static const struct ccu_reset a80_mmc_resets[] = { - [0] = GATE(0x0, BIT(18)), - [1] = GATE(0x4, BIT(18)), - [2] = GATE(0x8, BIT(18)), - [3] = GATE(0xc, BIT(18)), + [0] = RESET(0x0, BIT(18)), + [1] = RESET(0x4, BIT(18)), + [2] = RESET(0x8, BIT(18)), + [3] = RESET(0xc, BIT(18)), }; const struct ccu_desc a80_ccu_desc = { diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 07aa9a53e08..a58f19f46d9 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -11,5 +11,5 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o -obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o -obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o +obj-$(CONFIG_$(PHASE_)CLK_K3_PLL) += clk-k3-pll.o +obj-$(CONFIG_$(PHASE_)CLK_K3) += clk-k3.o diff --git a/drivers/core/Makefile b/drivers/core/Makefile index acbd2bf2cef..9ea57911f89 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -3,19 +3,19 @@ # Copyright (c) 2013 Google, Inc obj-y += device.o fdtaddr.o lists.o root.o uclass.o util.o tag.o -obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi.o -obj-$(CONFIG_$(SPL_TPL_)DEVRES) += devres.o -obj-$(CONFIG_$(SPL_TPL_)DM_DEVICE_REMOVE) += device-remove.o -obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o +obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi.o +obj-$(CONFIG_$(PHASE_)DEVRES) += devres.o +obj-$(CONFIG_$(PHASE_)DM_DEVICE_REMOVE) += device-remove.o +obj-$(CONFIG_$(XPL_)SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_DM) += dump.o -obj-$(CONFIG_$(SPL_TPL_)REGMAP) += regmap.o -obj-$(CONFIG_$(SPL_TPL_)SYSCON) += syscon-uclass.o -obj-$(CONFIG_$(SPL_)OF_LIVE) += of_access.o of_addr.o +obj-$(CONFIG_$(PHASE_)REGMAP) += regmap.o +obj-$(CONFIG_$(PHASE_)SYSCON) += syscon-uclass.o +obj-$(CONFIG_$(XPL_)OF_LIVE) += of_access.o of_addr.o ifndef CONFIG_DM_DEV_READ_INLINE obj-$(CONFIG_OF_CONTROL) += read.o endif -obj-$(CONFIG_$(SPL_)OF_PLATDATA) += read.o +obj-$(CONFIG_$(XPL_)OF_PLATDATA) += read.o obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o ccflags-$(CONFIG_DM_DEBUG) += -DDEBUG diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 7e3b3719d18..48ae8ce830e 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -611,7 +611,7 @@ int ofnode_read_u32_array(ofnode node, const char *propname, out_values, sz); /* get the error right, but space is more important in SPL */ - if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { if (ret == -FDT_ERR_NOTFOUND) return -EINVAL; else if (ret == -FDT_ERR_BADLAYOUT) @@ -1468,7 +1468,7 @@ int ofnode_read_simple_size_cells(ofnode node) bool ofnode_pre_reloc(ofnode node) { -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_TPL_BUILD) +#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_TPL_BUILD) /* for SPL and TPL the remaining nodes after the fdtgrep 1st pass * had property bootph-all or bootph-pre-sram/bootph-pre-ram. * They are removed in final dtb (fdtgrep 2nd pass) @@ -1735,6 +1735,39 @@ const char *ofnode_conf_read_str(const char *prop_name) return ofnode_read_string(node, prop_name); } +bool ofnode_options_read_bool(const char *prop_name) +{ + ofnode uboot; + + uboot = ofnode_path("/options/u-boot"); + if (!ofnode_valid(uboot)) + return false; + + return ofnode_read_bool(uboot, prop_name); +} + +int ofnode_options_read_int(const char *prop_name, int default_val) +{ + ofnode uboot; + + uboot = ofnode_path("/options/u-boot"); + if (!ofnode_valid(uboot)) + return default_val; + + return ofnode_read_u32_default(uboot, prop_name, default_val); +} + +const char *ofnode_options_read_str(const char *prop_name) +{ + ofnode uboot; + + uboot = ofnode_path("/options/u-boot"); + if (!ofnode_valid(uboot)) + return NULL; + + return ofnode_read_string(uboot, prop_name); +} + int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset) { int ret; diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index 4fbce519a0b..965c4938c8c 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -6,6 +6,6 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o -obj-$(CONFIG_$(SPL_TPL_)FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_$(PHASE_)FSL_CAAM_RNG) += rng.o obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 55191736931..9c4ff4960fc 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -207,7 +207,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, append_store(desc, dma_addr_out, storelen, LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob, uint32_t in_sz) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 27e24808946..c45481bef0b 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -713,7 +713,7 @@ int sec_init_idx(uint8_t sec_idx) ccsr_sec_t *sec = caam->sec; uint32_t mcr = sec_in32(&sec->mcfgr); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX8M) uint32_t jrdid_ms = 0; #endif #ifdef CONFIG_FSL_CORENET @@ -745,14 +745,14 @@ int sec_init_idx(uint8_t sec_idx) mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX8M) jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID; sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); #endif jr_reset(); #ifdef CONFIG_FSL_CORENET -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * For SPL Build, Set the Liodns in SEC JR0 for * creating PAMU entries corresponding to these. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 9fa5d85a27e..c1d6a6b6c59 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> # Copyright (C) 2014-2021 Altera Corporation <www.altera.com> -ifdef CONFIG_$(SPL_)ALTERA_SDRAM +ifdef CONFIG_$(XPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 46c53e7c7a3..3c79bb11802 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -20,7 +20,7 @@ #include "sequencer.h" -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct altera_gen5_sdram_priv { struct ram_info info; @@ -651,4 +651,4 @@ U_BOOT_DRIVER(altera_gen5_sdram) = { .priv_auto = sizeof(struct altera_gen5_sdram_priv), }; -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index cc128112e4f..9c5b108267a 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -409,18 +409,18 @@ compute_lowest_common_dimm_parameters(const unsigned int ctrl_num, if (dimm_params[i].n_ranks) { if (dimm_params[i].registered_dimm) { temp1 = 1; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD printf("Detected RDIMM %s\n", dimm_params[i].mpart); #endif } else { temp2 = 1; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD printf("Detected UDIMM %s\n", dimm_params[i].mpart); #endif } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD puts(" "); #endif } diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 888dfb7ff33..d59e94779ff 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -863,16 +863,16 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) if ((first_ctrl == 0) && (total_memory - 1 > (phys_size_t)~0ULL)) { puts("Detected "); print_size(total_memory, " of memory\n"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD puts(" "); /* re-align to match init_dram print */ #endif puts("This U-Boot only supports <= "); print_size((unsigned long long)((phys_size_t)~0ULL)+1, " of DDR\n"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD puts(" "); /* re-align to match init_dram print */ #endif puts("You could rebuild it with CONFIG_PHYS_64BIT\n"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD puts(" "); /* re-align to match init_dram print */ #endif } diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile index aed91dc23f4..883e6e1b0d7 100644 --- a/drivers/ddr/imx/imx8m/Makefile +++ b/drivers/ddr/imx/imx8m/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_IMX8M_DRAM) += ddr_init.o obj-y += ../phy/ endif diff --git a/drivers/ddr/imx/imx8ulp/Makefile b/drivers/ddr/imx/imx8ulp/Makefile index 7f44a92180f..4f2ad32351c 100644 --- a/drivers/ddr/imx/imx8ulp/Makefile +++ b/drivers/ddr/imx/imx8ulp/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_IMX8ULP_DRAM) += ddr_init.o endif diff --git a/drivers/ddr/imx/imx9/Makefile b/drivers/ddr/imx/imx9/Makefile index 9403f988b32..6c9506055b8 100644 --- a/drivers/ddr/imx/imx9/Makefile +++ b/drivers/ddr/imx/imx9/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_IMX9_DRAM) += ddr_init.o obj-y += ../phy/ endif diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile index bb3d4ee5b74..592d0c6ebad 100644 --- a/drivers/ddr/imx/phy/Makefile +++ b/drivers/ddr/imx/phy/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o endif diff --git a/drivers/ddr/marvell/a38x/Makefile b/drivers/ddr/marvell/a38x/Makefile index 4e8a9d190d7..f49d009920e 100644 --- a/drivers/ddr/marvell/a38x/Makefile +++ b/drivers/ddr/marvell/a38x/Makefile @@ -1,29 +1,29 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += mv_ddr_plat.o -obj-$(CONFIG_SPL_BUILD) += mv_ddr_sys_env_lib.o -obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o -obj-$(CONFIG_SPL_BUILD) += ddr3_init.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o -obj-$(CONFIG_SPL_BUILD) += mv_ddr_build_message.o -obj-$(CONFIG_SPL_BUILD) += mv_ddr_common.o -obj-$(CONFIG_SPL_BUILD) += mv_ddr_spd.o -obj-$(CONFIG_SPL_BUILD) += mv_ddr_topology.o -obj-$(CONFIG_SPL_BUILD) += xor.o +obj-$(CONFIG_XPL_BUILD) += mv_ddr_plat.o +obj-$(CONFIG_XPL_BUILD) += mv_ddr_sys_env_lib.o +obj-$(CONFIG_XPL_BUILD) += ddr3_debug.o +obj-$(CONFIG_XPL_BUILD) += ddr3_init.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_bist.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_centralization.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_db.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_hw_algo.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_ip_engine.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_leveling.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_pbs.o +obj-$(CONFIG_XPL_BUILD) += mv_ddr_build_message.o +obj-$(CONFIG_XPL_BUILD) += mv_ddr_common.o +obj-$(CONFIG_XPL_BUILD) += mv_ddr_spd.o +obj-$(CONFIG_XPL_BUILD) += mv_ddr_topology.o +obj-$(CONFIG_XPL_BUILD) += xor.o obj-$(CONFIG_ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING) += old/ ifdef CONFIG_DDR4 - obj-$(CONFIG_SPL_BUILD) += mv_ddr4_mpr_pda_if.o - obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training.o - obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_calibration.o - obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_db.o - obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_leveling.o + obj-$(CONFIG_XPL_BUILD) += mv_ddr4_mpr_pda_if.o + obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training.o + obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_calibration.o + obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_db.o + obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_leveling.o endif diff --git a/drivers/ddr/marvell/a38x/old/Makefile b/drivers/ddr/marvell/a38x/old/Makefile index 1645a79b405..c9bc746cc2b 100644 --- a/drivers/ddr/marvell/a38x/old/Makefile +++ b/drivers/ddr/marvell/a38x/old/Makefile @@ -2,20 +2,20 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SPL_BUILD) += ddr3_a38x.o -obj-$(CONFIG_SPL_BUILD) += ddr3_a38x_training.o -obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o -obj-$(CONFIG_SPL_BUILD) += ddr3_hws_hw_training.o -obj-$(CONFIG_SPL_BUILD) += ddr3_init.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o -obj-$(CONFIG_SPL_BUILD) += ddr3_training_static.o +obj-$(CONFIG_XPL_BUILD) += ddr3_a38x.o +obj-$(CONFIG_XPL_BUILD) += ddr3_a38x_training.o +obj-$(CONFIG_XPL_BUILD) += ddr3_debug.o +obj-$(CONFIG_XPL_BUILD) += ddr3_hws_hw_training.o +obj-$(CONFIG_XPL_BUILD) += ddr3_init.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_bist.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_centralization.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_db.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_hw_algo.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_ip_engine.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_leveling.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_pbs.o +obj-$(CONFIG_XPL_BUILD) += ddr3_training_static.o define IncludeSymbolRename CFLAGS_$(1) = -include $(srctree)/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h diff --git a/drivers/ddr/marvell/axp/Makefile b/drivers/ddr/marvell/axp/Makefile index d04d9a21db2..01e427296e6 100644 --- a/drivers/ddr/marvell/axp/Makefile +++ b/drivers/ddr/marvell/axp/Makefile @@ -1,12 +1,12 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += ddr3_dfs.o -obj-$(CONFIG_SPL_BUILD) += ddr3_dqs.o -obj-$(CONFIG_SPL_BUILD) += ddr3_hw_training.o -obj-$(CONFIG_SPL_BUILD) += ddr3_init.o -obj-$(CONFIG_SPL_BUILD) += ddr3_pbs.o -obj-$(CONFIG_SPL_BUILD) += ddr3_read_leveling.o -obj-$(CONFIG_SPL_BUILD) += ddr3_sdram.o -obj-$(CONFIG_SPL_BUILD) += ddr3_spd.o -obj-$(CONFIG_SPL_BUILD) += ddr3_write_leveling.o -obj-$(CONFIG_SPL_BUILD) += xor.o +obj-$(CONFIG_XPL_BUILD) += ddr3_dfs.o +obj-$(CONFIG_XPL_BUILD) += ddr3_dqs.o +obj-$(CONFIG_XPL_BUILD) += ddr3_hw_training.o +obj-$(CONFIG_XPL_BUILD) += ddr3_init.o +obj-$(CONFIG_XPL_BUILD) += ddr3_pbs.o +obj-$(CONFIG_XPL_BUILD) += ddr3_read_leveling.o +obj-$(CONFIG_XPL_BUILD) += ddr3_sdram.o +obj-$(CONFIG_XPL_BUILD) += ddr3_spd.o +obj-$(CONFIG_XPL_BUILD) += ddr3_write_leveling.o +obj-$(CONFIG_XPL_BUILD) += xor.o diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile index dfbf64da667..05d7cc61caa 100644 --- a/drivers/dfu/Makefile +++ b/drivers/dfu/Makefile @@ -3,11 +3,11 @@ # Copyright (C) 2012 Samsung Electronics # Lukasz Majewski <l.majewski@samsung.com> -obj-$(CONFIG_$(SPL_)DFU) += dfu.o -obj-$(CONFIG_$(SPL_)DFU_MMC) += dfu_mmc.o -obj-$(CONFIG_$(SPL_)DFU_MTD) += dfu_mtd.o -obj-$(CONFIG_$(SPL_)DFU_NAND) += dfu_nand.o -obj-$(CONFIG_$(SPL_)DFU_RAM) += dfu_ram.o -obj-$(CONFIG_$(SPL_)DFU_SF) += dfu_sf.o -obj-$(CONFIG_$(SPL_)DFU_WRITE_ALT) += dfu_alt.o -obj-$(CONFIG_$(SPL_)DFU_VIRT) += dfu_virt.o +obj-$(CONFIG_$(XPL_)DFU) += dfu.o +obj-$(CONFIG_$(XPL_)DFU_MMC) += dfu_mmc.o +obj-$(CONFIG_$(XPL_)DFU_MTD) += dfu_mtd.o +obj-$(CONFIG_$(XPL_)DFU_NAND) += dfu_nand.o +obj-$(CONFIG_$(XPL_)DFU_RAM) += dfu_ram.o +obj-$(CONFIG_$(XPL_)DFU_SF) += dfu_sf.o +obj-$(CONFIG_$(XPL_)DFU_WRITE_ALT) += dfu_alt.o +obj-$(CONFIG_$(XPL_)DFU_VIRT) += dfu_virt.o diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 7ce83d72bd3..8b979f69ed9 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -1,5 +1,5 @@ obj-$(CONFIG_FIRMWARE) += firmware-uclass.o -obj-$(CONFIG_$(SPL_)ARM_PSCI_FW) += psci.o +obj-$(CONFIG_$(XPL_)ARM_PSCI_FW) += psci.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_SANDBOX) += firmware-sandbox.o obj-$(CONFIG_ZYNQMP_FIRMWARE) += firmware-zynqmp.o diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index f99507d86c6..4b1b80d7abe 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -260,7 +260,7 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) int err; u32 ret_payload[PAYLOAD_ARG_CNT]; - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) printf("Loading new PMUFW cfg obj (%ld bytes)\n", size); flush_dcache_range((ulong)cfg_obj, (ulong)(cfg_obj + size)); @@ -282,7 +282,7 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) if (ret_payload[0]) printf("PMUFW returned 0x%08x status!\n", ret_payload[0]); - if ((err || ret_payload[0]) && IS_ENABLED(CONFIG_SPL_BUILD)) + if ((err || ret_payload[0]) && IS_ENABLED(CONFIG_XPL_BUILD)) panic("PMUFW config object loading failed in EL3\n"); return 0; @@ -354,7 +354,7 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, debug("%s at EL%d, API ID: 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x\n", __func__, current_el(), api_id, arg0, arg1, arg2, arg3); - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { #if defined(CONFIG_ZYNQMP_IPI) /* * Use fixed payload and arg size as the EL2 call. The firmware @@ -416,10 +416,10 @@ static int zynqmp_firmware_bind(struct udevice *dev) int ret; struct udevice *child; - if ((IS_ENABLED(CONFIG_SPL_BUILD) && + if ((IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) && IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) || - (!IS_ENABLED(CONFIG_SPL_BUILD) && + (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN))) { ret = device_bind_driver_to_node(dev, "zynqmp_power_domain", "zynqmp_power_domain", diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 45caef4f5c1..5a65bd98779 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -17,7 +17,7 @@ #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) #define BITSTREAM_CHUNK_SIZE 0xFFFF0 #define RECONFIG_STATUS_POLL_RETRY_MAX 100 diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 57467b4d975..3e86d854a01 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -414,13 +414,13 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, if (bstype != BIT_PARTIAL) zynq_slcr_devcfg_enable(); - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) puts("INFO:post config was not run, please run manually if needed\n"); return FPGA_SUCCESS; } -#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD) static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, fpga_fs_info *fsinfo) { @@ -504,7 +504,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, struct xilinx_fpga_op zynq_op = { .load = zynq_load, -#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD) .loadfs = zynq_loadfs, #endif }; diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 56c20e4c635..fe81b6ba88b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -3,14 +3,14 @@ # Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o obj-$(CONFIG_AXP_GPIO) += axp_gpio.o obj-$(CONFIG_DM_74X164) += 74x164_gpio.o endif -obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o +obj-$(CONFIG_$(PHASE_)DM_GPIO) += gpio-uclass.o -obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o +obj-$(CONFIG_$(XPL_)DM_PCA953X) += pca953x_gpio.o obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o obj-$(CONFIG_ASPEED_G7_GPIO) += gpio-aspeed-g7.o @@ -24,7 +24,7 @@ obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -obj-$(CONFIG_$(SPL_TPL_)MCP230XX_GPIO) += mcp230xx_gpio.o +obj-$(CONFIG_$(PHASE_)MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o @@ -57,13 +57,13 @@ obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o -obj-$(CONFIG_$(SPL_)PALMAS_GPIO) += palmas_gpio.o +obj-$(CONFIG_$(XPL_)PALMAS_GPIO) += palmas_gpio.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o -obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o -obj-$(CONFIG_$(SPL_TPL_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o +obj-$(CONFIG_$(XPL_)PCF8575_GPIO) += pcf8575_gpio.o +obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o @@ -71,7 +71,7 @@ obj-$(CONFIG_NX_GPIO) += nx_gpio.o obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o -obj-$(CONFIG_$(SPL_)MAX77663_GPIO) += max77663_gpio.o +obj-$(CONFIG_$(XPL_)MAX77663_GPIO) += max77663_gpio.o obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 92ce68dd4a1..0213271e3a6 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -412,7 +412,7 @@ int dm_gpio_request(struct gpio_desc *desc, const char *label) static int dm_gpio_requestf(struct gpio_desc *desc, const char *fmt, ...) { -#if !defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF) +#if !defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF) va_list args; char buf[40]; @@ -461,7 +461,7 @@ int gpio_request(unsigned gpio, const char *label) */ int gpio_requestf(unsigned gpio, const char *fmt, ...) { -#if !defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF) +#if !defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF) va_list args; char buf[40]; diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index fc4dcf9f986..2fb14590c0f 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -143,7 +143,7 @@ int pca953x_get_val(uint8_t chip) return (int)val; } -#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_XPL_BUILD) /* * Display pca953x information */ diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 24ba12dd820..57c49c75939 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -126,7 +126,7 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) } /* Simple SPL interface to GPIOs */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD enum { PULL_NONE_1V8 = 0, @@ -169,7 +169,7 @@ int spl_gpio_output(void *vregs, uint gpio, int value) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ static int rockchip_gpio_probe(struct udevice *dev) { diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 83e65aa4aec..53dbbe97b5a 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -92,7 +92,7 @@ static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) writel(value, &bank->dat); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Common GPIO API - SPL does not support driver model yet */ int gpio_set_value(unsigned gpio, int value) { @@ -118,7 +118,7 @@ static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) value = readl(&bank->dat); return !!(value & DAT_MASK(gpio)); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) { @@ -185,7 +185,7 @@ int s5p_gpio_get_pin(unsigned gpio) } /* Driver model interface */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* set GPIO pin 'gpio' as an input */ static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset) { @@ -230,7 +230,7 @@ static int exynos_gpio_set_value(struct udevice *dev, unsigned offset, return 0; } -#endif /* nCONFIG_SPL_BUILD */ +#endif /* nCONFIG_XPL_BUILD */ /* * There is no common GPIO API for pull, drv, pin, rate (yet). These @@ -260,7 +260,7 @@ void gpio_set_rate(int gpio, int mode) s5p_gpio_get_pin(gpio), mode); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int exynos_gpio_get_function(struct udevice *dev, unsigned offset) { struct exynos_bank_info *state = dev_get_priv(dev); diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 218ca2af397..2ca4960f17a 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -245,7 +245,7 @@ int sunxi_name_to_gpio(const char *name) { unsigned int gpio; int ret; -#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO +#if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO char lookup[8]; if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) { diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index 1d45b500746..8307a07e14e 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -164,7 +164,7 @@ int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]) return ret; } -#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_XPL_BUILD) /* * Display tca642x information */ diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 0c40d36c41e..b83df351e74 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -257,6 +257,56 @@ static const struct dm_gpio_ops gpio_tegra_ops = { .xlate = tegra_gpio_xlate, }; +/* + * SPL GPIO functions. + */ +int spl_gpio_output(void *regs, uint gpio, int value) +{ + /* Configure GPIO output value. */ + set_level(gpio, value); + + /* Configure GPIO direction as output. */ + set_direction(gpio, DIRECTION_OUTPUT); + + /* Enable the pin as a GPIO */ + set_config(gpio, 1); + + return 0; +} + +int spl_gpio_input(void *regs, uint gpio) +{ + /* Configure GPIO direction as input. */ + set_direction(gpio, DIRECTION_INPUT); + + /* Enable the pin as a GPIO */ + set_config(gpio, 1); + + return 0; +} + +int spl_gpio_get_value(void *regs, uint gpio) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + int val; + + if (get_direction(gpio) == DIRECTION_INPUT) + val = readl(&bank->gpio_in[GPIO_PORT(gpio)]); + else + val = readl(&bank->gpio_out[GPIO_PORT(gpio)]); + + return (val >> GPIO_BIT(gpio)) & 1; +} + +int spl_gpio_set_value(void *regs, uint gpio, int value) +{ + /* Configure GPIO output value. */ + set_level(gpio, value); + + return 0; +} + /** * Returns the name of a GPIO port * @@ -323,7 +373,7 @@ static int gpio_tegra_bind(struct udevice *parent) return 0; /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; bank_count = TEGRA_GPIO_BANKS; #else diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 00b90523c62..bebd728e7da 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -2,15 +2,15 @@ # # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_$(SPL_)DM_I2C) += i2c-uclass.o -ifdef CONFIG_$(SPL_)ACPIGEN -obj-$(CONFIG_$(SPL_)DM_I2C) += acpi_i2c.o +obj-$(CONFIG_$(XPL_)DM_I2C) += i2c-uclass.o +ifdef CONFIG_$(XPL_)ACPIGEN +obj-$(CONFIG_$(XPL_)DM_I2C) += acpi_i2c.o endif -obj-$(CONFIG_$(SPL_)DM_I2C_GPIO) += i2c-gpio.o -obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o -obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o +obj-$(CONFIG_$(XPL_)DM_I2C_GPIO) += i2c-gpio.o +obj-$(CONFIG_$(XPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o +obj-$(CONFIG_$(XPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o -obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o +obj-$(CONFIG_$(XPL_)SYS_I2C_LEGACY) += i2c_core.o obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o obj-$(CONFIG_SYS_I2C_AST2600) += ast2600_i2c.o obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o @@ -57,4 +57,4 @@ obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o -obj-$(CONFIG_$(SPL_)I2C_MUX) += muxes/ +obj-$(CONFIG_$(XPL_)I2C_MUX) += muxes/ diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 11c98672265..c21c412231c 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -37,7 +37,7 @@ static int designware_i2c_pci_of_to_plat(struct udevice *dev) { struct dw_i2c *priv = dev_get_priv(dev); - if (spl_phase() < PHASE_SPL) { + if (xpl_phase() < PHASE_SPL) { u32 base; int ret; @@ -53,7 +53,7 @@ static int designware_i2c_pci_of_to_plat(struct udevice *dev) PCI_COMMAND_MASTER); } - if (spl_phase() < PHASE_BOARD_F) { + if (xpl_phase() < PHASE_BOARD_F) { /* Handle early, fixed mapping into a different address space */ priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0); } else { diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 71f315adf6f..8d4107b8848 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -3,12 +3,12 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_$(SPL_TPL_)CROS_EC_KEYB) += cros_ec_keyb.o -obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += key_matrix.o -obj-$(CONFIG_$(SPL_TPL_)DM_KEYBOARD) += input.o keyboard-uclass.o +obj-$(CONFIG_$(PHASE_)CROS_EC_KEYB) += cros_ec_keyb.o +obj-$(CONFIG_$(PHASE_)OF_CONTROL) += key_matrix.o +obj-$(CONFIG_$(PHASE_)DM_KEYBOARD) += input.o keyboard-uclass.o obj-$(CONFIG_BUTTON_KEYBOARD) += button_kbd.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_APPLE_SPI_KEYB) += apple_spi_kbd.o obj-$(CONFIG_I8042_KEYB) += i8042.o diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index bee74b25751..c98cbf92fab 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -9,6 +9,30 @@ config LED can provide access to board-specific LEDs. Use of the device tree for configuration is encouraged. +config LED_BOOT + bool "Enable LED boot support" + help + Enable LED boot support. + + LED boot is a specific LED assigned to signal boot operation status. + Defined in Device Tree /options/u-boot node. Refer here for the supported + options [1]. + + [1] dtschema/schemas/options/u-boot.yaml + +config LED_ACTIVITY + bool "Enable LED activity support" + help + Enable LED activity support. + + LED activity is a specific LED assigned to signal activity operation + like file trasnfer, flash write/erase... + + Defined in Device Tree /options/u-boot node. Refer here for the supported + options [1]. + + [1] dtschema/schemas/options/u-boot.yaml + config LED_BCM6328 bool "LED Support for BCM6328" depends on LED && ARCH_BMIPS diff --git a/drivers/led/Makefile b/drivers/led/Makefile index e27aa488482..aa64a38b4e1 100644 --- a/drivers/led/Makefile +++ b/drivers/led/Makefile @@ -10,6 +10,6 @@ obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o obj-$(CONFIG_LED_BCM6753) += led_bcm6753.o obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o obj-$(CONFIG_LED_PWM) += led_pwm.o -obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o +obj-$(CONFIG_$(XPL_)LED_GPIO) += led_gpio.o obj-$(CONFIG_LED_CORTINA) += led_cortina.o obj-$(CONFIG_LED_LP5562) += led_lp5562.o diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 199d68bc25a..05e09909b7d 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -94,6 +94,144 @@ int led_set_period(struct udevice *dev, int period_ms) return -ENOSYS; } +#ifdef CONFIG_LED_BOOT +static int led_boot_get(struct udevice **devp, int *period_ms) +{ + struct led_uc_priv *priv; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_LED, &uc); + if (ret) + return ret; + + priv = uclass_get_priv(uc); + if (!priv->boot_led_label) + return -ENOENT; + + if (period_ms) + *period_ms = priv->boot_led_period; + + return led_get_by_label(priv->boot_led_label, devp); +} + +int led_boot_on(void) +{ + struct udevice *dev; + int ret; + + ret = led_boot_get(&dev, NULL); + if (ret) + return ret; + + return led_set_state(dev, LEDST_ON); +} + +int led_boot_off(void) +{ + struct udevice *dev; + int ret; + + ret = led_boot_get(&dev, NULL); + if (ret) + return ret; + + return led_set_state(dev, LEDST_OFF); +} + +#if defined(CONFIG_LED_BLINK) || defined(CONFIG_LED_SW_BLINK) +int led_boot_blink(void) +{ + struct udevice *dev; + int period_ms, ret; + + ret = led_boot_get(&dev, &period_ms); + if (ret) + return ret; + + ret = led_set_period(dev, period_ms); + if (ret) { + if (ret != -ENOSYS) + return ret; + + /* fallback to ON with no set_period and no SW_BLINK */ + return led_set_state(dev, LEDST_ON); + } + + return led_set_state(dev, LEDST_BLINK); +} +#endif +#endif + +#ifdef CONFIG_LED_ACTIVITY +static int led_activity_get(struct udevice **devp, int *period_ms) +{ + struct led_uc_priv *priv; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_LED, &uc); + if (ret) + return ret; + + priv = uclass_get_priv(uc); + if (!priv->activity_led_label) + return -ENOENT; + + if (period_ms) + *period_ms = priv->activity_led_period; + + return led_get_by_label(priv->activity_led_label, devp); +} + +int led_activity_on(void) +{ + struct udevice *dev; + int ret; + + ret = led_activity_get(&dev, NULL); + if (ret) + return ret; + + return led_set_state(dev, LEDST_ON); +} + +int led_activity_off(void) +{ + struct udevice *dev; + int ret; + + ret = led_activity_get(&dev, NULL); + if (ret) + return ret; + + return led_set_state(dev, LEDST_OFF); +} + +#if defined(CONFIG_LED_BLINK) || defined(CONFIG_LED_SW_BLINK) +int led_activity_blink(void) +{ + struct udevice *dev; + int period_ms, ret; + + ret = led_activity_get(&dev, &period_ms); + if (ret) + return ret; + + ret = led_set_period(dev, period_ms); + if (ret) { + if (ret != -ENOSYS) + return ret; + + /* fallback to ON with no set_period and no SW_BLINK */ + return led_set_state(dev, LEDST_ON); + } + + return led_set_state(dev, LEDST_BLINK); +} +#endif +#endif + static int led_post_bind(struct udevice *dev) { struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); @@ -158,10 +296,34 @@ static int led_post_probe(struct udevice *dev) return ret; } +#if defined(CONFIG_LED_BOOT) || defined(CONFIG_LED_ACTIVITY) +static int led_init(struct uclass *uc) +{ + struct led_uc_priv *priv = uclass_get_priv(uc); + +#ifdef CONFIG_LED_BOOT + priv->boot_led_label = ofnode_options_read_str("boot-led"); + priv->boot_led_period = ofnode_options_read_int("boot-led-period", 250); +#endif + +#ifdef CONFIG_LED_ACTIVITY + priv->activity_led_label = ofnode_options_read_str("activity-led"); + priv->activity_led_period = ofnode_options_read_int("activity-led-period", + 250); +#endif + + return 0; +} +#endif + UCLASS_DRIVER(led) = { .id = UCLASS_LED, .name = "led", .per_device_plat_auto = sizeof(struct led_uc_plat), .post_bind = led_post_bind, .post_probe = led_post_probe, +#if defined(CONFIG_LED_BOOT) || defined(CONFIG_LED_ACTIVITY) + .init = led_init, + .priv_auto = sizeof(struct led_uc_priv), +#endif }; diff --git a/drivers/led/led_sw_blink.c b/drivers/led/led_sw_blink.c index 9e36edbee47..06a43db340c 100644 --- a/drivers/led/led_sw_blink.c +++ b/drivers/led/led_sw_blink.c @@ -103,8 +103,21 @@ bool led_sw_on_state_change(struct udevice *dev, enum led_state_t state) return false; if (state == LEDST_BLINK) { - /* start blinking on next led_sw_blink() call */ - sw_blink->state = LED_SW_BLINK_ST_OFF; + struct led_ops *ops = led_get_ops(dev); + + /* + * toggle LED initially and start blinking on next + * led_sw_blink() call. + */ + switch (ops->get_state(dev)) { + case LEDST_ON: + ops->set_state(dev, LEDST_OFF); + sw_blink->state = LED_SW_BLINK_ST_OFF; + default: + ops->set_state(dev, LEDST_ON); + sw_blink->state = LED_SW_BLINK_ST_ON; + } + return true; } diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 59e8d0de93c..6072fa1956b 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2016, NVIDIA CORPORATION. # -obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o +obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c index 4df69734ed9..713d93a200c 100644 --- a/drivers/mailbox/zynqmp-ipi.c +++ b/drivers/mailbox/zynqmp-ipi.c @@ -108,7 +108,7 @@ static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data) writel(msg->buf[i], &mbx[i]); /* Use SMC calls for Exception Level less than 3 where TF-A is available */ - if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && current_el() < 3) { ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_NOTIFY, 0); debug("%s, send %ld bytes\n", __func__, msg->len); @@ -148,7 +148,7 @@ static int zynqmp_ipi_recv(struct mbox_chan *chan, void *data) msg->buf[i] = readl(&mbx[i]); /* Ack to remote if EL is not 3 */ - if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && current_el() < 3) { ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_ACK, IPI_SMC_ACK_EIRQ_MASK); } @@ -168,7 +168,7 @@ static int zynqmp_ipi_dest_probe(struct udevice *dev) node = dev_ofnode(dev); - if (IS_ENABLED(CONFIG_SPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp")) + if (IS_ENABLED(CONFIG_XPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp")) zynqmp->el3_supported = true; ret = dev_read_u32(dev->parent, "xlnx,ipi-id", &zynqmp->local_id); diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index f7fd1d5caee..dac805e4cdd 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -3,14 +3,14 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_$(SPL_TPL_)MISC) += misc-uclass.o -obj-$(CONFIG_$(SPL_TPL_)NVMEM) += nvmem.o +obj-$(CONFIG_$(PHASE_)MISC) += misc-uclass.o +obj-$(CONFIG_$(PHASE_)NVMEM) += nvmem.o -obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o -obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o -obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o +obj-$(CONFIG_$(PHASE_)CROS_EC) += cros_ec.o +obj-$(CONFIG_$(PHASE_)CROS_EC_SANDBOX) += cros_ec_sandbox.o +obj-$(CONFIG_$(PHASE_)CROS_EC_LPC) += cros_ec_lpc.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_SANDBOX) += sandbox_adder.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o @@ -18,14 +18,14 @@ obj-$(CONFIG_SANDBOX) += p2sb_sandbox.o p2sb_emul.o obj-$(CONFIG_SANDBOX) += swap_case.o endif -ifdef CONFIG_$(SPL_)DM_I2C -ifndef CONFIG_SPL_BUILD +ifdef CONFIG_$(XPL_)DM_I2C +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o obj-$(CONFIG_USB_HUB_USB251XB) += usb251xb.o endif endif ifdef CONFIG_SPL_OF_PLATDATA -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SANDBOX) += spltest_sandbox.o endif endif @@ -37,29 +37,29 @@ obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_IIM) += fsl_iim.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o -obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o +obj-$(CONFIG_$(XPL_)FS_LOADER) += fs_loader.o obj-$(CONFIG_GATEWORKS_SC) += gsc.o obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o obj-$(CONFIG_IRQ) += irq-uclass.o obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o -obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o +obj-$(CONFIG_$(XPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ obj-$(CONFIG_IMX_ELE) += imx_ele/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o -obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o -obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o +obj-$(CONFIG_$(PHASE_)LS2_SFP) += ls2_sfp.o +obj-$(CONFIG_$(XPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NPCM_OTP) += npcm_otp.o obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o -obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o +obj-$(CONFIG_$(XPL_)PWRSEQ) += pwrseq-uclass.o ifdef CONFIG_QFW obj-y += qfw.o obj-$(CONFIG_QFW_ACPI) += qfw_acpi.o @@ -68,9 +68,9 @@ obj-$(CONFIG_QFW_MMIO) += qfw_mmio.o obj-$(CONFIG_QFW_SMBIOS) += qfw_smbios.o obj-$(CONFIG_SANDBOX) += qfw_sandbox.o endif -obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_EFUSE) += rockchip-efuse.o -obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_OTP) += rockchip-otp.o -obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o +obj-$(CONFIG_$(PHASE_)ROCKCHIP_EFUSE) += rockchip-efuse.o +obj-$(CONFIG_$(PHASE_)ROCKCHIP_OTP) += rockchip-otp.o +obj-$(CONFIG_$(PHASE_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o @@ -81,7 +81,7 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o obj-$(CONFIG_TEGRA_CAR) += tegra_car.o obj-$(CONFIG_TEST_DRV) += test_drv.o -obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o +obj-$(CONFIG_$(PHASE_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c index feb02f97065..dee0bdd9663 100644 --- a/drivers/misc/gsc.c +++ b/drivers/misc/gsc.c @@ -389,7 +389,7 @@ static int gsc_probe(struct udevice *dev) if (priv->rtc) dev_set_priv(priv->rtc, priv); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD gsc_banner(dev); #endif diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index bbd7e24200b..5d3db0bc4df 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -191,7 +191,7 @@ static int imx8_scu_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL; #else plat->base = (struct mu_type *)addr; diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index b753419f01b..661f70cf870 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -5,12 +5,12 @@ * */ -#include <hang.h> -#include <malloc.h> -#include <memalign.h> #include <asm/io.h> -#include <dm.h> +#include <asm/mach-imx/sys_proto.h> #include <asm/mach-imx/ele_api.h> +#include <dm.h> +#include <malloc.h> +#include <memalign.h> #include <misc.h> DECLARE_GLOBAL_DATA_PTR; @@ -205,8 +205,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon return -EINVAL; } - if ((fuse_id != 1 && fuse_num != 1) || - (fuse_id == 1 && fuse_num != 4)) { + if (is_imx8ulp() && ((fuse_id != 1 && fuse_num != 1) || (fuse_id == 1 && fuse_num != 4))) { printf("Invalid fuse number parameter\n"); return -EINVAL; } @@ -226,7 +225,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon *response = msg.data[0]; fuse_words[0] = msg.data[1]; - if (fuse_id == 1) { + if (fuse_id == 1 && is_imx8ulp()) { /* OTP_UNIQ_ID */ fuse_words[1] = msg.data[2]; fuse_words[2] = msg.data[3]; @@ -269,6 +268,72 @@ int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) return ret; } +int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 3; + msg.command = ELE_WRITE_SHADOW_REQ; + msg.data[0] = fuse_id; + msg.data[1] = fuse_val; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", + __func__, ret, fuse_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg = {}; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + if (!fuse_val) { + printf("Invalid parameters for shadow read\n"); + return -EINVAL; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 2; + msg.command = ELE_READ_SHADOW_REQ; + msg.data[0] = fuse_id; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", + __func__, ret, fuse_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + *fuse_val = msg.data[1]; + + return ret; +} + int ele_release_caam(u32 core_did, u32 *response) { struct udevice *dev = gd->arch.ele_dev; diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index 0cf81f33ba5..cdb85b999db 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -21,25 +21,35 @@ struct imx8ulp_mu { #define MU_SR_TE0_MASK BIT(0) #define MU_SR_RF0_MASK BIT(0) -#define MU_TR_COUNT 8 -#define MU_RR_COUNT 4 void mu_hal_init(ulong base) { struct mu_type *mu_base = (struct mu_type *)base; + u32 rr_num = (readl(&mu_base->par) & 0xFF00) >> 8; + int i; writel(0, &mu_base->tcr); writel(0, &mu_base->rcr); + + while (true) { + /* If there is pending RX data, clear them by read them out */ + if (!(readl(&mu_base->sr) & BIT(6))) + return; + + for (i = 0; i < rr_num; i++) + readl(&mu_base->rr[i]); + } } int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg) { struct mu_type *mu_base = (struct mu_type *)base; u32 mask = MU_SR_TE0_MASK << reg_index; - u32 val; + u32 val, tr_num; int ret; - assert(reg_index < MU_TR_COUNT); + tr_num = readl(&mu_base->par) & 0xFF; + assert(reg_index < tr_num); debug("sendmsg tsr 0x%x\n", readl(&mu_base->tsr)); @@ -61,11 +71,12 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) { struct mu_type *mu_base = (struct mu_type *)base; u32 mask = MU_SR_RF0_MASK << reg_index; - u32 val; + u32 val, rr_num; int ret; u32 count = 10; - assert(reg_index < MU_RR_COUNT); + rr_num = (readl(&mu_base->par) & 0xFF00) >> 8; + assert(reg_index < rr_num); debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr)); @@ -96,7 +107,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data) { struct ele_msg *msg = (struct ele_msg *)data; int ret; - u8 count = 0; + u8 count = 0, rr_num; if (!msg) return -EINVAL; @@ -113,9 +124,11 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data) return -EINVAL; } + rr_num = (readl(&base->par) & 0xFF00) >> 8; + /* Read remaining words */ while (count < msg->size) { - ret = mu_hal_receivemsg((ulong)base, count % MU_RR_COUNT, + ret = mu_hal_receivemsg((ulong)base, count % rr_num, &msg->data[count - 1]); if (ret) return ret; @@ -129,7 +142,7 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data) { struct ele_msg *msg = (struct ele_msg *)data; int ret; - u8 count = 0; + u8 count = 0, tr_num; if (!msg) return -EINVAL; @@ -144,9 +157,11 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data) return ret; count++; + tr_num = readl(&base->par) & 0xFF; + /* Write remaining words */ while (count < msg->size) { - ret = mu_hal_sendmsg((ulong)base, count % MU_TR_COUNT, + ret = mu_hal_sendmsg((ulong)base, count % tr_num, msg->data[count - 1]); if (ret) return ret; @@ -229,6 +244,7 @@ static struct misc_ops imx8ulp_mu_ops = { static const struct udevice_id imx8ulp_mu_ids[] = { { .compatible = "fsl,imx8ulp-mu" }, { .compatible = "fsl,imx93-mu-s4" }, + { .compatible = "fsl,imx95-mu-ele" }, { } }; diff --git a/drivers/misc/imx_ele/fuse.c b/drivers/misc/imx_ele/fuse.c index d12539c8aac..c1e7434dbf3 100644 --- a/drivers/misc/imx_ele/fuse.c +++ b/drivers/misc/imx_ele/fuse.c @@ -11,10 +11,10 @@ #include <env.h> #include <asm/mach-imx/ele_api.h> #include <asm/global_data.h> +#include <env.h> DECLARE_GLOBAL_DATA_PTR; -#define FUSE_BANKS 64 #define WORDS_PER_BANKS 8 struct fsb_map_entry { @@ -32,6 +32,7 @@ struct ele_map_entry { #if defined(CONFIG_IMX8ULP) #define FSB_OTP_SHADOW 0x800 +#define IS_FSB_ALLOWED (true) struct fsb_map_entry fsb_mapping_table[] = { { 3, 8 }, @@ -84,6 +85,8 @@ struct ele_map_entry ele_api_mapping_table[] = { }; #elif defined(CONFIG_ARCH_IMX9) #define FSB_OTP_SHADOW 0x8000 +#define IS_FSB_ALLOWED (!IS_ENABLED(CONFIG_SCMI_FIRMWARE) && \ + !(readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28) & BIT(0))) struct fsb_map_entry fsb_mapping_table[] = { { 0, 8 }, @@ -138,8 +141,7 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy) /* map the fuse from ocotp fuse map to FSB*/ for (i = 0; i < size; i++) { if (fsb_mapping_table[i].fuse_bank != -1 && - fsb_mapping_table[i].fuse_bank == bank && - fsb_mapping_table[i].fuse_words > word) { + fsb_mapping_table[i].fuse_bank == bank) { break; } @@ -150,8 +152,13 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy) return -1; /* Failed to find */ if (fsb_mapping_table[i].redundancy) { + if ((fsb_mapping_table[i].fuse_words << 1) <= word) + return -2; /* Not valid word */ + *redundancy = true; return (word >> 1) + word_pos; + } else if (fsb_mapping_table[i].fuse_words <= word) { + return -2; /* Not valid word */ } *redundancy = false; @@ -187,24 +194,14 @@ static s32 map_ele_fuse_index(u32 bank, u32 word) int fuse_sense(u32 bank, u32 word, u32 *val) { s32 word_index; - bool redundancy; - if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val) + if (word >= WORDS_PER_BANKS || !val) return -EINVAL; - word_index = map_fsb_fuse_index(bank, word, &redundancy); - if (word_index >= 0) { - *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2)); - if (redundancy) - *val = (*val >> ((word % 2) * 16)) & 0xFFFF; - - return 0; - } - word_index = map_ele_fuse_index(bank, word); if (word_index >= 0) { u32 data[4]; - u32 res, size = 4; + u32 res = 0, size = 4; int ret; /* Only UID return 4 words */ @@ -236,28 +233,29 @@ int fuse_sense(u32 bank, u32 word, u32 *val) return -ENOENT; } + #elif defined(CONFIG_ARCH_IMX9) int fuse_sense(u32 bank, u32 word, u32 *val) { s32 word_index; bool redundancy; - if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val) + if (word >= WORDS_PER_BANKS || !val) return -EINVAL; - word_index = map_fsb_fuse_index(bank, word, &redundancy); - if (word_index >= 0) { - *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2)); - if (redundancy) - *val = (*val >> ((word % 2) * 16)) & 0xFFFF; + if (!IS_ENABLED(CONFIG_SCMI_FIRMWARE)) { + word_index = map_fsb_fuse_index(bank, word, &redundancy); - return 0; + /* ELE read common fuse API supports all FSB fuse. */ + if (word_index < 0) + word_index = map_ele_fuse_index(bank, word); + } else { + word_index = bank * 8 + word; } - word_index = map_ele_fuse_index(bank, word); if (word_index >= 0) { u32 data; - u32 res, size = 1; + u32 res = 0, size = 1; int ret; ret = ele_read_common_fuse(word_index, &data, size, &res); @@ -275,18 +273,62 @@ int fuse_sense(u32 bank, u32 word, u32 *val) } #endif -int fuse_read(u32 bank, u32 word, u32 *val) +static int fuse_read_default(u32 bank, u32 word, u32 *val) { + s32 word_index; + bool redundancy; + + if (IS_FSB_ALLOWED) { + word_index = map_fsb_fuse_index(bank, word, &redundancy); + if (word_index >= 0) { + *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2)); + if (redundancy) + *val = (*val >> ((word % 2) * 16)) & 0xFFFF; + + return 0; + } + } + return fuse_sense(bank, word, val); } +static int fuse_read_ele_shd(u32 bank, u32 word, u32 *val) +{ + u32 res = 0; + int ret; + struct udevice *dev = gd->arch.ele_dev; + + if (!dev) + return -ENODEV; + + ret = ele_read_shadow_fuse((bank * 8 + word), val, &res); + if (ret) { + printf("ele read shadow fuse failed %d, 0x%x\n", ret, res); + return ret; + } + + return 0; +} + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + if (word >= WORDS_PER_BANKS || !val) + return -EINVAL; + + if (!IS_ENABLED(CONFIG_SPL_BUILD) && + env_get_yesno("enable_ele_shd") == 1) + return fuse_read_ele_shd(bank, word, val); + else + return fuse_read_default(bank, word, val); +} + int fuse_prog(u32 bank, u32 word, u32 val) { - u32 res; + u32 res = 0; int ret; bool lock = false; - if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val) + if (word >= WORDS_PER_BANKS || !val) return -EINVAL; /* Lock 8ULP ECC fuse word, so second programming will return failure. @@ -314,6 +356,17 @@ int fuse_prog(u32 bank, u32 word, u32 val) int fuse_override(u32 bank, u32 word, u32 val) { - printf("Override fuse to i.MX8ULP in u-boot is forbidden\n"); - return -EPERM; + u32 res = 0; + int ret; + + if (word >= WORDS_PER_BANKS || !val) + return -EINVAL; + + ret = ele_write_shadow_fuse((bank * 8 + word), val, &res); + if (ret) { + printf("ahab write shadow fuse failed %d, 0x%x\n", ret, res); + return ret; + } + + return 0; } diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c index 016c8073378..d7ce0383ac9 100644 --- a/drivers/misc/p2sb-uclass.c +++ b/drivers/misc/p2sb-uclass.c @@ -198,7 +198,7 @@ static int p2sb_child_post_bind(struct udevice *dev) static int p2sb_post_bind(struct udevice *dev) { - if (spl_phase() > PHASE_TPL && !CONFIG_IS_ENABLED(OF_PLATDATA)) + if (xpl_phase() > PHASE_TPL && !CONFIG_IS_ENABLED(OF_PLATDATA)) return dm_scan_fdt_dev(dev); return 0; diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 235c477c2e0..868f3090ff2 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -4,23 +4,23 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += mmc.o -obj-$(CONFIG_$(SPL_)DM_MMC) += mmc-uclass.o +obj-$(CONFIG_$(XPL_)DM_MMC) += mmc-uclass.o -ifdef CONFIG_$(SPL_TPL_)DM_MMC -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += mmc_bootdev.o +ifdef CONFIG_$(PHASE_)DM_MMC +obj-$(CONFIG_$(PHASE_)BOOTSTD) += mmc_bootdev.o endif -obj-$(CONFIG_$(SPL_TPL_)MMC_WRITE) += mmc_write.o -obj-$(CONFIG_$(SPL_)MMC_PWRSEQ) += mmc-pwrseq.o +obj-$(CONFIG_$(PHASE_)MMC_WRITE) += mmc_write.o +obj-$(CONFIG_$(XPL_)MMC_PWRSEQ) += mmc-pwrseq.o obj-$(CONFIG_MMC_SDHCI_ADMA_HELPERS) += sdhci-adma.o -ifndef CONFIG_$(SPL_)BLK +ifndef CONFIG_$(XPL_)BLK obj-y += mmc_legacy.o endif obj-$(CONFIG_SUPPORT_EMMC_BOOT) += mmc_boot.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o endif diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 83cdc9fd66d..c8db4f811c2 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -301,7 +301,7 @@ struct mmc *find_mmc_device(int dev_num) ret = blk_find_device(UCLASS_MMC, dev_num, &dev); if (ret) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC Device %d not found\n", dev_num); #endif return NULL; @@ -373,7 +373,7 @@ void mmc_do_preinit(void) } } -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) void print_mmc_devices(char separator) { struct udevice *dev; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d4f2fd5bf89..efe98354a0f 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -328,7 +328,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) break; if (status & MMC_STATUS_MASK) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) log_err("Status Error: %#08x\n", status); #endif return -ECOMM; @@ -341,7 +341,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) } if (timeout_ms <= 0) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) log_err("Timeout waiting card ready\n"); #endif return -ETIMEDOUT; @@ -483,7 +483,7 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, if (blkcnt > 1) { if (mmc_send_stop_transmission(mmc, false)) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) log_err("mmc fail to send stop cmd\n"); #endif return 0; @@ -534,7 +534,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, return 0; if ((start + blkcnt) > block_dev->lba) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) log_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", start + blkcnt, block_dev->lba); #endif @@ -2424,7 +2424,7 @@ static int mmc_startup_v4(struct mmc *mmc) mmc->capacity_gp[i] <<= 19; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD if (part_completed) { mmc->enh_user_size = (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) + @@ -2723,7 +2723,7 @@ static int mmc_startup(struct mmc *mmc) bdesc->blksz = mmc->read_bl_len; bdesc->log2blksz = LOG2(bdesc->blksz); bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); -#if !defined(CONFIG_SPL_BUILD) || \ +#if !defined(CONFIG_XPL_BUILD) || \ (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ !CONFIG_IS_ENABLED(USE_TINY_PRINTF)) sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", @@ -2741,7 +2741,7 @@ static int mmc_startup(struct mmc *mmc) bdesc->revision[0] = 0; #endif -#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)) +#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)) part_init(bdesc); #endif @@ -2953,7 +2953,7 @@ retry: err = mmc_send_op_cond(mmc); if (err) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) if (!quiet) log_err("Card did not respond to voltage select! : %d\n", err); @@ -3008,7 +3008,7 @@ int mmc_start_init(struct mmc *mmc) #endif if (no_card) { mmc->has_init = 0; -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) log_err("MMC: no card present\n"); #endif return -ENOMEDIUM; @@ -3195,7 +3195,7 @@ int mmc_initialize(struct bd_info *bis) if (ret) return ret; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD print_mmc_devices(','); #endif diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c index a87d2276c1b..8f8ba34be71 100644 --- a/drivers/mmc/mmc_legacy.c +++ b/drivers/mmc/mmc_legacy.c @@ -44,7 +44,7 @@ struct mmc *find_mmc_device(int dev_num) return m; } -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC Device %d not found\n", dev_num); #endif @@ -93,7 +93,7 @@ void mmc_list_add(struct mmc *mmc) list_add_tail(&mmc->link, &mmc_devices); } -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) void print_mmc_devices(char separator) { struct mmc *m; diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index b32123758ea..fc45f017e5d 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -67,7 +67,7 @@ static inline ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, } #endif -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #ifdef CONFIG_MMC_TRACE void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 8e51453d2ae..e66ab25d02a 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -59,8 +59,8 @@ DECLARE_GLOBAL_DATA_PTR; /* simplify defines to OMAP_HSMMC_USE_GPIO */ -#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO)) +#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_XPL_BUILD)) || \ + (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO)) #define OMAP_HSMMC_USE_GPIO #else #undef OMAP_HSMMC_USE_GPIO diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 5ba99d68b7d..422b8f7e4c8 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -83,7 +83,7 @@ static int rockchip_dwmmc_of_to_plat(struct udevice *dev) return log_msg_ret("rkp", -EINVAL); priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD if (!priv->fifo_mode) priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode"); #endif diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 4ea3307ed9c..da630b9d97a 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -608,7 +608,7 @@ static int rockchip_sdhci_probe(struct udevice *dev) * Disable use of DMA and force use of PIO mode in SPL to fix an issue * where loading part of TF-A into SRAM using DMA silently fails. */ - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && dev_read_bool(dev, "u-boot,spl-fifo-mode")) host->flags &= ~USE_DMA; diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 3147d3019c0..9dc1ceaa09b 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -61,7 +61,7 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) int ret; ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC, diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 0b396122b46..9fff1bc1a10 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -385,7 +385,7 @@ static bool tmio_sd_addr_is_dmaable(struct mmc_data *data) return false; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD if (IS_ENABLED(CONFIG_ARCH_UNIPHIER) && !IS_ENABLED(CONFIG_ARM64)) { /* * For UniPhier ARMv7 SoCs, the stack is allocated in locked diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 5b3650d52ee..cc89ff767ab 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -36,7 +36,7 @@ static ulong uniphier_sd_clk_get_rate(struct tmio_sd_priv *priv) { #if CONFIG_IS_ENABLED(CLK) return clk_get_rate(&priv->clk); -#elif CONFIG_SPL_BUILD +#elif CONFIG_XPL_BUILD return 100000000; #else return 0; @@ -50,7 +50,7 @@ static int uniphier_sd_probe(struct udevice *dev) priv->clk_get_rate = uniphier_sd_clk_get_rate; priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int ret; ret = clk_get_by_index(dev, 0, &priv->clk); diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 24d0556cd37..0e2bdab4e7e 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -289,7 +289,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay) { int ret; - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { if (node_id == NODE_SD_0) { ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, SD0_ITAPCHGWIN); @@ -339,7 +339,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay) static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay) { - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { if (node_id == NODE_SD_0) return zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, @@ -356,7 +356,7 @@ static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay) static inline int zynqmp_dll_reset(u32 node_id, u32 type) { - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { if (node_id == NODE_SD_0) return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST, type == PM_DLL_RESET_ASSERT ? diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 10d575e9f93..ce05e206073 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -16,7 +16,7 @@ mtd-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o # U-Boot build -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) ifneq ($(mtd-y),) obj-y += mtd.o @@ -34,9 +34,9 @@ else ifneq ($(mtd-y),) obj-$(CONFIG_SPL_MTD) += mtd.o endif -obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += nand/ +obj-$(CONFIG_$(PHASE_)NAND_SUPPORT) += nand/ obj-$(CONFIG_SPL_ONENAND_SUPPORT) += onenand/ -obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += spi/ +obj-$(CONFIG_$(PHASE_)SPI_FLASH_SUPPORT) += spi/ obj-$(CONFIG_SPL_UBI) += ubispl/ endif diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 96e186600a1..c8169cf7390 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0+ -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) nandcore-objs := core.o bbt.o obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o obj-$(CONFIG_MTD_RAW_NAND) += raw/ obj-$(CONFIG_MTD_SPI_NAND) += spi/ else -obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += raw/ +obj-$(CONFIG_$(PHASE_)NAND_SUPPORT) += raw/ endif diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 9f3f1267cbd..c345fc1f1fb 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -120,6 +120,13 @@ config NAND_BRCMNAND Enable the driver for NAND flash on platforms using a Broadcom NAND controller. +config NAND_BRCMNAND_BCMBCA + bool "Support Broadcom NAND controller on BCMBCA platforms" + depends on NAND_BRCMNAND && ARCH_BCMBCA + help + Enable support for broadcom nand driver on BCA (broadband + access) platforms such as BCM6846. + config NAND_BRCMNAND_6368 bool "Support Broadcom NAND controller on bcm6368" depends on NAND_BRCMNAND && ARCH_BMIPS diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 46fead6fa48..b47a3d787ce 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_NAND_DRIVERS NORMAL_DRIVERS=y @@ -18,7 +18,7 @@ obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \ nand_macronix.o nand_micron.o \ nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o -obj-$(CONFIG_$(SPL_TPL_)NAND_INIT) += nand.o +obj-$(CONFIG_$(PHASE_)NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o endif diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index ee4ec6da587..817fab4ca36 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1029,11 +1029,15 @@ static int atmel_nand_pmecc_init(struct nand_chip *chip) req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; else if (chip->ecc.strength) req.ecc.strength = chip->ecc.strength; + else if (chip->ecc_strength_ds) + req.ecc.strength = chip->ecc_strength_ds; else req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; if (chip->ecc.size) req.ecc.sectorsize = chip->ecc.size; + else if (chip->ecc_step_ds) + req.ecc.sectorsize = chip->ecc_step_ds; else req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO; diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 4dbf7b47135..605298628d6 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -1251,7 +1251,7 @@ static int at91_nand_ready(struct mtd_info *mtd) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* The following code is for SPL */ static struct mtd_info *mtd; static struct nand_chip nand_chip; @@ -1526,4 +1526,4 @@ void board_nand_init(void) if (atmel_nand_chip_init(i, base_addr[i])) log_err("atmel_nand: Fail to initialize #%d chip", i); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index 0c6325aaa61..24d0d568449 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o +obj-$(CONFIG_NAND_BRCMNAND_BCMBCA) += bcmbca_nand.o obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o diff --git a/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c new file mode 100644 index 00000000000..2753783ae70 --- /dev/null +++ b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <asm/io.h> +#include <memalign.h> +#include <nand.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <dm.h> +#include <linux/printk.h> + +#include "brcmnand.h" + +struct bcmbca_nand_soc { + struct brcmnand_soc soc; + void __iomem *base; +}; + +#define BCMBCA_NAND_INT 0x00 +#define BCMBCA_NAND_STATUS_SHIFT 0 +#define BCMBCA_NAND_STATUS_MASK (0xfff << BCMBCA_NAND_STATUS_SHIFT) + +#define BCMBCA_NAND_INT_EN 0x04 +#define BCMBCA_NAND_ENABLE_SHIFT 0 +#define BCMBCA_NAND_ENABLE_MASK (0xffff << BCMBCA_NAND_ENABLE_SHIFT) + +enum { + BCMBCA_NP_READ = BIT(0), + BCMBCA_BLOCK_ERASE = BIT(1), + BCMBCA_COPY_BACK = BIT(2), + BCMBCA_PAGE_PGM = BIT(3), + BCMBCA_CTRL_READY = BIT(4), + BCMBCA_DEV_RBPIN = BIT(5), + BCMBCA_ECC_ERR_UNC = BIT(6), + BCMBCA_ECC_ERR_CORR = BIT(7), +}; + +#if defined(CONFIG_ARM64) +#define ALIGN_REQ 8 +#else +#define ALIGN_REQ 4 +#endif + +static inline bool bcmbca_nand_is_buf_aligned(void *flash_cache, void *buffer) +{ + return IS_ALIGNED((uintptr_t)buffer, ALIGN_REQ) && + IS_ALIGNED((uintptr_t)flash_cache, ALIGN_REQ); +} + +static bool bcmbca_nand_intc_ack(struct brcmnand_soc *soc) +{ + struct bcmbca_nand_soc *priv = + container_of(soc, struct bcmbca_nand_soc, soc); + void __iomem *mmio = priv->base + BCMBCA_NAND_INT; + u32 val = brcmnand_readl(mmio); + + if (val & (BCMBCA_CTRL_READY << BCMBCA_NAND_STATUS_SHIFT)) { + /* Ack interrupt */ + val &= ~BCMBCA_NAND_STATUS_MASK; + val |= BCMBCA_CTRL_READY << BCMBCA_NAND_STATUS_SHIFT; + brcmnand_writel(val, mmio); + return true; + } + + return false; +} + +static void bcmbca_nand_intc_set(struct brcmnand_soc *soc, bool en) +{ + struct bcmbca_nand_soc *priv = + container_of(soc, struct bcmbca_nand_soc, soc); + void __iomem *mmio = priv->base + BCMBCA_NAND_INT_EN; + u32 val = brcmnand_readl(mmio); + + /* Don't ack any interrupts */ + val &= ~BCMBCA_NAND_STATUS_MASK; + + if (en) + val |= BCMBCA_CTRL_READY << BCMBCA_NAND_ENABLE_SHIFT; + else + val &= ~(BCMBCA_CTRL_READY << BCMBCA_NAND_ENABLE_SHIFT); + + brcmnand_writel(val, mmio); +} + +static void bcmbca_read_data_bus(struct brcmnand_soc *soc, + void __iomem *flash_cache, u32 *buffer, int fc_words) +{ + /* + * memcpy can do unaligned aligned access depending on source + * and dest address, which is incompatible with nand cache. Fallback + * to the memcpy_fromio in such case + */ + if (bcmbca_nand_is_buf_aligned((void __force *)flash_cache, buffer)) + memcpy((void *)buffer, (void __force *)flash_cache, fc_words * 4); + else + memcpy_fromio((void *)buffer, flash_cache, fc_words * 4); +} + +static int bcmbca_nand_probe(struct udevice *dev) +{ + struct udevice *pdev = dev; + struct bcmbca_nand_soc *priv = dev_get_priv(dev); + struct brcmnand_soc *soc; + struct resource res; + + soc = &priv->soc; + + dev_read_resource_byname(pdev, "nand-int-base", &res); + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + soc->ctlrdy_ack = bcmbca_nand_intc_ack; + soc->ctlrdy_set_enabled = bcmbca_nand_intc_set; + soc->read_data_bus = bcmbca_read_data_bus; + + /* Disable and ack all interrupts */ + brcmnand_writel(0, priv->base + BCMBCA_NAND_INT_EN); + brcmnand_writel(0, priv->base + BCMBCA_NAND_INT); + + return brcmnand_probe(pdev, soc); +} + +static const struct udevice_id bcmbca_nand_dt_ids[] = { + { + .compatible = "brcm,nand-bcm63138", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcmbca_nand) = { + .name = "bcmbca-nand", + .id = UCLASS_MTD, + .of_match = bcmbca_nand_dt_ids, + .probe = bcmbca_nand_probe, + .priv_auto = sizeof(struct bcmbca_nand_soc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(bcmbca_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); +} diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index c89661badbf..4430c4e93ee 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -152,7 +152,7 @@ static void lpc32xx_nand_init(void) &lpc32xx_nand_mlc_registers->time_reg); } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /** * lpc32xx_cmd_ctrl - write command to either cmd or data register @@ -606,7 +606,7 @@ void board_nand_init(void) pr_err("nand_register returned %i", ret); } -#else /* defined(CONFIG_SPL_BUILD) */ +#else /* defined(CONFIG_XPL_BUILD) */ void nand_init(void) { @@ -770,4 +770,4 @@ unsigned int nand_page_size(void) return BYTES_PER_PAGE; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 4d643bc64bc..109c31fb4d1 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = { } }; -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE) /* @@ -162,7 +162,7 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd) return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY; } -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) /* * Prepares DMA descriptors for NAND RD/WR operations * If the size is < 256 Bytes then it is assumed to be @@ -510,7 +510,7 @@ static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) */ int board_nand_init(struct nand_chip *lpc32xx_chip) { -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) int ret; /* Acquire a channel for our use */ @@ -533,7 +533,7 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) lpc32xx_chip->read_byte = lpc32xx_read_byte; lpc32xx_chip->write_byte = lpc32xx_write_byte; -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) /* Hardware ECC calculation is supported when DMA driver is selected */ lpc32xx_chip->ecc.mode = NAND_ECC_HW; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 0545c23e268..1b65c6f6443 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -414,7 +414,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd_to_nand(mtd); int ret = 0; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int res; #endif @@ -434,7 +434,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) nand_release_device(mtd); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Mark block bad in BBT */ if (chip->bbt) { res = nand_markbad_bbt(mtd, ofs); @@ -488,7 +488,7 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) if (!chip->bbt) return 0; /* Return info from the table */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD return nand_isreserved_bbt(mtd, ofs); #else return 0; @@ -518,7 +518,7 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) return chip->block_bad(mtd, ofs); /* Return info from the table */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD return nand_isbad_bbt(mtd, ofs, allowbbt); #else return 0; @@ -3729,7 +3729,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) if (!chip->read_buf || chip->read_buf == nand_read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; #endif diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index a36e2a148cc..9c704c60e8e 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -1011,7 +1011,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * omap_nand_switch_ecc - switch the ECC operation between different engines * (h/w and s/w) and different algorithms (hamming and BCHx) @@ -1072,7 +1072,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) err = nand_scan_tail(mtd); return err; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* * Board-specific NAND initialization. The following members of the diff --git a/drivers/mtd/nand/raw/sand_nand.c b/drivers/mtd/nand/raw/sand_nand.c index 229d7b5b65a..3678bb8a41b 100644 --- a/drivers/mtd/nand/raw/sand_nand.c +++ b/drivers/mtd/nand/raw/sand_nand.c @@ -601,7 +601,7 @@ static int sand_nand_probe(struct udevice *dev) } nand = &chip->nand; - nand->options = spl_in_proper() ? 0 : NAND_SKIP_BBTSCAN; + nand->options = not_xpl() ? 0 : NAND_SKIP_BBTSCAN; nand->flash_node = np; nand->dev_ready = sand_nand_dev_ready; nand->cmdfunc = sand_nand_command; @@ -680,7 +680,7 @@ void board_nand_init(void) log_info("Failed to get sandbox NAND: %d\n", err); } -#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT) +#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT) void nand_deselect(void) { nand_chip->select_chip(nand_to_mtd(nand_chip), -1); diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile index 4dc417a5794..7f4a8514c17 100644 --- a/drivers/mtd/onenand/Makefile +++ b/drivers/mtd/onenand/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2005-2007 Samsung Electronics. # Kyungmin Park <kyungmin.park@samsung.com> -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o obj-$(CONFIG_SAMSUNG_ONENAND) += samsung.o else diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index bedc4e970e4..63b0fd899fd 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -2,7 +2,7 @@ menu "SPI Flash Support" config DM_SPI_FLASH bool "Enable Driver Model for SPI flash" - depends on DM && DM_SPI + depends on DM_SPI imply SPI_FLASH help Enable driver model for SPI flash. This SPI flash interface diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 409395382f5..44e67cd913a 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -3,12 +3,12 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_$(SPL_TPL_)DM_SPI_FLASH) += sf-uclass.o +obj-$(CONFIG_$(PHASE_)DM_SPI_FLASH) += sf-uclass.o spi-nor-y := sf_probe.o spi-nor-ids.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o -ifeq ($(CONFIG_$(SPL_TPL_)SPI_FLASH_TINY),y) +ifeq ($(CONFIG_$(PHASE_)SPI_FLASH_TINY),y) spi-nor-y += spi-nor-tiny.o else spi-nor-y += spi-nor-core.o @@ -19,6 +19,6 @@ endif obj-$(CONFIG_SPI_FLASH) += spi-nor.o obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o -obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_MTD) += sf_mtd.o +obj-$(CONFIG_$(PHASE_)SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o -obj-$(CONFIG_$(SPL_TPL_)BOOTDEV_SPI_FLASH) += sf_bootdev.o +obj-$(CONFIG_$(PHASE_)BOOTDEV_SPI_FLASH) += sf_bootdev.o diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index 2d5a16bf6a2..e5ebc3479fb 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -138,7 +138,7 @@ static int sandbox_sf_probe(struct udevice *dev) return ret; } slave_plat = dev_get_parent_plat(dev); - cs = slave_plat->cs; + cs = slave_plat->cs[0]; debug("found at cs %d\n", cs); if (!pdata->filename) { diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index a4d15bd64aa..102a9236826 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -54,7 +54,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs, struct udevice *bus; char *str; -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(USE_TINY_PRINTF) +#if defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(USE_TINY_PRINTF) str = "spi_flash"; #else char name[30]; diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c index 6db24189c8e..438eb3698d5 100644 --- a/drivers/mtd/spi/sf_dataflash.c +++ b/drivers/mtd/spi/sf_dataflash.c @@ -438,7 +438,7 @@ static int add_dataflash(struct udevice *dev, char *name, int nr_pages, spi_flash->size = nr_pages * pagesize; spi_flash->erase_size = pagesize; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD printf("SPI DataFlash: Detected %s with page size ", spi_flash->name); print_size(spi_flash->page_size, ", erase size "); print_size(spi_flash->erase_size, ", total "); diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 8f7a77e7169..6f5395c7b9b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -467,8 +467,9 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, } /* - * Read the status register, returning its value in the location - * Return the status register value. + * Return the status register value. If the chip is parallel, then the + * read will be striped, so we should read 2 bytes to get the sr + * register value from both of the parallel chips. * Returns negative if error occurred. */ static int read_sr(struct spi_nor *nor) @@ -500,18 +501,29 @@ static int read_sr(struct spi_nor *nor) if (spi_nor_protocol_is_dtr(nor->reg_proto)) op.data.nbytes = 2; - ret = spi_nor_read_write_reg(nor, &op, val); - if (ret < 0) { - pr_debug("error %d reading SR\n", (int)ret); - return ret; + if (nor->flags & SNOR_F_HAS_PARALLEL) { + op.data.nbytes = 2; + ret = spi_nor_read_write_reg(nor, &op, &val[0]); + if (ret < 0) { + pr_debug("error %d reading SR\n", (int)ret); + return ret; + } + val[0] |= val[1]; + } else { + ret = spi_nor_read_write_reg(nor, &op, &val[0]); + if (ret < 0) { + pr_debug("error %d reading SR\n", (int)ret); + return ret; + } } - return *val; + return val[0]; } /* - * Read the flag status register, returning its value in the location - * Return the status register value. + * Return the flag status register value. If the chip is parallel, then + * the read will be striped, so we should read 2 bytes to get the fsr + * register value from both of the parallel chips. * Returns negative if error occurred. */ static int read_fsr(struct spi_nor *nor) @@ -543,13 +555,23 @@ static int read_fsr(struct spi_nor *nor) if (spi_nor_protocol_is_dtr(nor->reg_proto)) op.data.nbytes = 2; - ret = spi_nor_read_write_reg(nor, &op, val); - if (ret < 0) { - pr_debug("error %d reading FSR\n", ret); - return ret; + if (nor->flags & SNOR_F_HAS_PARALLEL) { + op.data.nbytes = 2; + ret = spi_nor_read_write_reg(nor, &op, &val[0]); + if (ret < 0) { + pr_debug("error %d reading SR\n", (int)ret); + return ret; + } + val[0] &= val[1]; + } else { + ret = spi_nor_read_write_reg(nor, &op, &val[0]); + if (ret < 0) { + pr_debug("error %d reading FSR\n", ret); + return ret; + } } - return *val; + return val[0]; } /* @@ -573,6 +595,24 @@ static int read_cr(struct spi_nor *nor) } #endif +/** + * read_sr3() - Read status register 3 unique to newer Winbond flashes + * @nor: pointer to a 'struct spi_nor' + */ +static int read_sr3(struct spi_nor *nor) +{ + int ret; + u8 val; + + ret = nor->read_reg(nor, SPINOR_OP_RDSR3, &val, 1); + if (ret < 0) { + dev_dbg(nor->dev, "error %d reading SR3\n", ret); + return ret; + } + + return val; +} + /* * Write status register 1 byte * Returns negative if error occurred. @@ -583,6 +623,17 @@ static int write_sr(struct spi_nor *nor, u8 val) return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); } +/** + * write_sr3() - Write status register 3 unique to newer Winbond flashes + * @nor: pointer to a 'struct spi_nor' + * @val: value to be written into SR3 + */ +static int write_sr3(struct spi_nor *nor, u8 val) +{ + nor->cmd_buf[0] = val; + return nor->write_reg(nor, SPINOR_OP_WRSR3, nor->cmd_buf, 1); +} + /* * Set write enable latch with Write Enable command. * Returns negative if error occurred. @@ -668,12 +719,17 @@ static u8 spi_nor_convert_3to4_erase(u8 opcode) static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, const struct flash_info *info) { + bool shift = 0; + + if (nor->flags & SNOR_F_HAS_PARALLEL) + shift = 1; + /* Do some manufacturer fixups first */ switch (JEDEC_MFR(info)) { case SNOR_MFR_SPANSION: /* No small sector erase for 4-byte command set */ nor->erase_opcode = SPINOR_OP_SE; - nor->mtd.erasesize = info->sector_size; + nor->mtd.erasesize = info->sector_size << shift; break; default: @@ -901,12 +957,32 @@ static int clean_bar(struct spi_nor *nor) static int write_bar(struct spi_nor *nor, u32 offset) { - u8 cmd, bank_sel; + u8 cmd, bank_sel, upage_curr; int ret; + struct mtd_info *mtd = &nor->mtd; + + /* Wait until previous write command is finished */ + if (spi_nor_wait_till_ready(nor)) + return 1; + + if (nor->flags & (SNOR_F_HAS_PARALLEL | SNOR_F_HAS_STACKED) && + mtd->size <= SZ_32M) + return 0; + + if (mtd->size <= SZ_16M) + return 0; - bank_sel = offset / SZ_16M; - if (bank_sel == nor->bank_curr) - goto bar_end; + offset = offset % (u32)mtd->size; + bank_sel = offset >> 24; + + upage_curr = nor->spi->flags & SPI_XFER_U_PAGE; + + if (!(nor->flags & SNOR_F_HAS_STACKED) && bank_sel == nor->bank_curr) + return 0; + else if (upage_curr == nor->upage_prev && bank_sel == nor->bank_curr) + return 0; + + nor->upage_prev = upage_curr; cmd = nor->bank_write_cmd; write_enable(nor); @@ -916,15 +992,19 @@ static int write_bar(struct spi_nor *nor, u32 offset) return ret; } -bar_end: nor->bank_curr = bank_sel; - return nor->bank_curr; + + return write_disable(nor); } static int read_bar(struct spi_nor *nor, const struct flash_info *info) { u8 curr_bank = 0; int ret; + struct mtd_info *mtd = &nor->mtd; + + if (mtd->size <= SZ_16M) + return 0; switch (JEDEC_MFR(info)) { case SNOR_MFR_SPANSION: @@ -936,15 +1016,30 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info) nor->bank_write_cmd = SPINOR_OP_WREAR; } + if (nor->flags & SNOR_F_HAS_PARALLEL) + nor->spi->flags |= SPI_XFER_LOWER; + ret = nor->read_reg(nor, nor->bank_read_cmd, - &curr_bank, 1); + &curr_bank, 1); if (ret) { debug("SF: fail to read bank addr register\n"); return ret; } nor->bank_curr = curr_bank; - return 0; + // Make sure both chips use the same BAR + if (nor->flags & SNOR_F_HAS_PARALLEL) { + write_enable(nor); + ret = nor->write_reg(nor, nor->bank_write_cmd, &curr_bank, 1); + if (ret) + return ret; + + ret = write_disable(nor); + if (ret) + return ret; + } + + return ret; } #endif @@ -1008,8 +1103,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); + u32 addr, len, rem, offset, max_size; bool addr_known = false; - u32 addr, len, rem, max_size; int ret, err; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -1030,11 +1125,23 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) while (len) { schedule(); - if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && ctrlc()) { addr_known = false; ret = -EINTR; goto erase_err; } + offset = addr; + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + + if (nor->flags & SNOR_F_HAS_STACKED) { + if (offset >= (mtd->size / 2)) { + offset = offset - (mtd->size / 2); + nor->spi->flags |= SPI_XFER_U_PAGE; + } else { + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } + } #ifdef CONFIG_SPI_FLASH_BAR ret = write_bar(nor, addr); if (ret < 0) @@ -1446,6 +1553,9 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) u8 id[SPI_NOR_MAX_ID_LEN]; const struct flash_info *info; + if (nor->flags & SNOR_F_HAS_PARALLEL) + nor->spi->flags |= SPI_XFER_LOWER; + tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); if (tmp < 0) { dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); @@ -1470,28 +1580,67 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; + loff_t offset = from; + u32 read_len = 0; + u32 rem_bank_len = 0; + u8 bank; + bool is_ofst_odd = false; dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); + if ((nor->flags & SNOR_F_HAS_PARALLEL) && (offset & 1)) { + /* We can hit this case when we use file system like ubifs */ + from--; + len++; + is_ofst_odd = true; + } + while (len) { - loff_t addr = from; - size_t read_len = len; + if (nor->addr_width == 3) { + if (nor->flags & SNOR_F_HAS_PARALLEL) { + bank = (u32)from / (SZ_16M << 0x01); + rem_bank_len = ((SZ_16M << 0x01) * + (bank + 1)) - from; + } else { + bank = (u32)from / SZ_16M; + rem_bank_len = (SZ_16M * (bank + 1)) - from; + } + } + offset = from; -#ifdef CONFIG_SPI_FLASH_BAR - u32 remain_len; + if (nor->flags & SNOR_F_HAS_STACKED) { + if (offset >= (mtd->size / 2)) { + offset = offset - (mtd->size / 2); + nor->spi->flags |= SPI_XFER_U_PAGE; + } else { + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } + } - ret = write_bar(nor, addr); - if (ret < 0) - return log_ret(ret); - remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr; + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + + if (nor->addr_width == 3) { +#ifdef CONFIG_SPI_FLASH_BAR + ret = write_bar(nor, offset); + if (ret < 0) + return log_ret(ret); +#endif + } - if (len < remain_len) + if (len < rem_bank_len) read_len = len; else - read_len = remain_len; -#endif + read_len = rem_bank_len; + + if (read_len == 0) + return -EIO; - ret = nor->read(nor, addr, read_len, buf); + ret = spi_nor_wait_till_ready(nor); + if (ret) + goto read_err; + + ret = nor->read(nor, offset, read_len, buf); if (ret == 0) { /* We shouldn't see 0-length reads */ ret = -EIO; @@ -1500,8 +1649,15 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, if (ret < 0) goto read_err; - *retlen += ret; - buf += ret; + if (is_ofst_odd == true) { + memmove(buf, (buf + 1), (len - 1)); + *retlen += (ret - 1); + buf += ret - 1; + is_ofst_odd = false; + } else { + *retlen += ret; + buf += ret; + } from += ret; len -= ret; } @@ -1796,6 +1952,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, struct spi_nor *nor = mtd_to_spi_nor(mtd); size_t page_offset, page_remain, i; ssize_t ret; + u32 offset; #ifdef CONFIG_SPI_FLASH_SST /* sst nor chips use AAI word program */ @@ -1805,6 +1962,27 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); + if (!len) + return 0; + + /* + * Cannot write to odd offset in parallel mode, + * so write 2 bytes first + */ + if ((nor->flags & SNOR_F_HAS_PARALLEL) && (to & 1)) { + u8 two[2] = {0xff, buf[0]}; + size_t local_retlen; + + ret = spi_nor_write(mtd, to & ~1, 2, &local_retlen, two); + if (ret < 0) + return ret; + + *retlen += 1; /* We've written only one actual byte */ + ++buf; + --len; + ++to; + } + for (i = 0; i < len; ) { ssize_t written; loff_t addr = to + i; @@ -1822,18 +2000,35 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, page_offset = do_div(aux, nor->page_size); } + offset = (to + i); + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + + if (nor->flags & SNOR_F_HAS_STACKED) { + if (offset >= (mtd->size / 2)) { + offset = offset - (mtd->size / 2); + nor->spi->flags |= SPI_XFER_U_PAGE; + } else { + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } + } + + if (nor->addr_width == 3) { +#ifdef CONFIG_SPI_FLASH_BAR + ret = write_bar(nor, offset); + if (ret < 0) + return ret; +#endif + } /* the size of data remaining on the first page */ page_remain = min_t(size_t, nor->page_size - page_offset, len - i); -#ifdef CONFIG_SPI_FLASH_BAR - ret = write_bar(nor, addr); - if (ret < 0) - return ret; -#endif + ret = spi_nor_wait_till_ready(nor); + if (ret) + goto write_err; write_enable(nor); - /* * On DTR capable flashes like Micron Xcella the writes cannot * start or end at an odd address in DTR mode. So we need to @@ -1841,7 +2036,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, * address and end address are even. */ if (spi_nor_protocol_is_dtr(nor->write_proto) && - ((addr | page_remain) & 1)) { + ((offset | page_remain) & 1)) { u_char *tmp; size_t extra_bytes = 0; @@ -1852,10 +2047,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, } /* Prepend a 0xff byte if the start address is odd. */ - if (addr & 1) { + if (offset & 1) { tmp[0] = 0xff; memcpy(tmp + 1, buf + i, page_remain); - addr--; + offset--; page_remain++; extra_bytes++; } else { @@ -1863,13 +2058,13 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, } /* Append a 0xff byte if the end address is odd. */ - if ((addr + page_remain) & 1) { + if ((offset + page_remain) & 1) { tmp[page_remain + extra_bytes] = 0xff; extra_bytes++; page_remain++; } - ret = nor->write(nor, addr, page_remain, tmp); + ret = nor->write(nor, offset, page_remain, tmp); kfree(tmp); @@ -1882,7 +2077,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, */ written = ret - extra_bytes; } else { - ret = nor->write(nor, addr, page_remain, buf + i); + ret = nor->write(nor, offset, page_remain, buf + i); if (ret < 0) goto write_err; written = ret; @@ -1891,6 +2086,11 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, ret = spi_nor_wait_till_ready(nor); if (ret) goto write_err; + + ret = write_disable(nor); + if (ret) + goto write_err; + *retlen += written; i += written; } @@ -1931,6 +2131,10 @@ static int macronix_quad_enable(struct spi_nor *nor) if (ret) return ret; + ret = write_disable(nor); + if (ret) + return ret; + ret = read_sr(nor); if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { dev_err(nor->dev, "Macronix Quad bit not set\n"); @@ -1992,7 +2196,7 @@ static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base, return -EINVAL; } - return 0; + return write_disable(nor); } #endif @@ -2168,6 +2372,10 @@ static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, nor->read_dummy = 8; while (len) { + /* Both chips are identical, so should be the SFDP data */ + if (nor->flags & SNOR_F_HAS_PARALLEL) + nor->spi->flags |= SPI_XFER_LOWER; + ret = nor->read(nor, addr, len, (u8 *)buf); if (!ret || ret > len) { ret = -EIO; @@ -2862,6 +3070,13 @@ static int spi_nor_init_params(struct spi_nor *nor, const struct flash_info *info, struct spi_nor_flash_parameter *params) { +#if CONFIG_IS_ENABLED(DM_SPI) && CONFIG_IS_ENABLED(SPI_ADVANCE) + struct udevice *dev = nor->spi->dev; + u64 flash_size[SNOR_FLASH_CNT_MAX] = {0}; + u32 idx = 0, i = 0; + int rc; +#endif + /* Set legacy flash parameters as default. */ memset(params, 0, sizeof(*params)); @@ -2979,7 +3194,62 @@ static int spi_nor_init_params(struct spi_nor *nor, memcpy(params, &sfdp_params, sizeof(*params)); } } +#if CONFIG_IS_ENABLED(DM_SPI) && CONFIG_IS_ENABLED(SPI_ADVANCE) + /* + * The flashes that are connected in stacked mode should be of same make. + * Except the flash size all other properties are identical for all the + * flashes connected in stacked mode. + * The flashes that are connected in parallel mode should be identical. + */ + while (i < SNOR_FLASH_CNT_MAX) { + rc = ofnode_read_u64_index(dev_ofnode(dev), "stacked-memories", + idx, &flash_size[i]); + if (rc == -EINVAL) { + break; + } else if (rc == -EOVERFLOW) { + idx++; + } else { + idx++; + i++; + if (!(nor->flags & SNOR_F_HAS_STACKED)) + nor->flags |= SNOR_F_HAS_STACKED; + if (!(nor->spi->flags & SPI_XFER_STACKED)) + nor->spi->flags |= SPI_XFER_STACKED; + } + } + + i = 0; + idx = 0; + while (i < SNOR_FLASH_CNT_MAX) { + rc = ofnode_read_u64_index(dev_ofnode(dev), "parallel-memories", + idx, &flash_size[i]); + if (rc == -EINVAL) { + break; + } else if (rc == -EOVERFLOW) { + idx++; + } else { + idx++; + i++; + if (!(nor->flags & SNOR_F_HAS_PARALLEL)) + nor->flags |= SNOR_F_HAS_PARALLEL; + } + } + if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) { + params->size = 0; + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) + params->size += flash_size[idx]; + } + /* + * In parallel-memories the erase operation is + * performed on both the flashes simultaneously + * so, double the erasesize. + */ + if (nor->flags & SNOR_F_HAS_PARALLEL) { + nor->mtd.erasesize <<= 1; + params->page_size <<= 1; + } +#endif spi_nor_post_sfdp_fixups(nor, params); return 0; @@ -3294,16 +3564,54 @@ static int spi_nor_select_erase(struct spi_nor *nor, /* prefer "small sector" erase if possible */ if (info->flags & SECT_4K) { nor->erase_opcode = SPINOR_OP_BE_4K; - mtd->erasesize = 4096; + /* + * In parallel-memories the erase operation is + * performed on both the flashes simultaneously + * so, double the erasesize. + */ + if (nor->flags & SNOR_F_HAS_PARALLEL) + mtd->erasesize = 4096 * 2; + else + mtd->erasesize = 4096; } else if (info->flags & SECT_4K_PMC) { nor->erase_opcode = SPINOR_OP_BE_4K_PMC; - mtd->erasesize = 4096; + /* + * In parallel-memories the erase operation is + * performed on both the flashes simultaneously + * so, double the erasesize. + */ + if (nor->flags & SNOR_F_HAS_PARALLEL) + mtd->erasesize = 4096 * 2; + else + mtd->erasesize = 4096; } else #endif { nor->erase_opcode = SPINOR_OP_SE; - mtd->erasesize = info->sector_size; + /* + * In parallel-memories the erase operation is + * performed on both the flashes simultaneously + * so, double the erasesize. + */ + if (nor->flags & SNOR_F_HAS_PARALLEL) + mtd->erasesize = info->sector_size * 2; + else + mtd->erasesize = info->sector_size; + } + + if ((JEDEC_MFR(info) == SNOR_MFR_SST) && info->flags & SECT_4K) { + nor->erase_opcode = SPINOR_OP_BE_4K; + /* + * In parallel-memories the erase operation is + * performed on both the flashes simultaneously + * so, double the erasesize. + */ + if (nor->flags & SNOR_F_HAS_PARALLEL) + mtd->erasesize = 4096 * 2; + else + mtd->erasesize = 4096; } + return 0; } @@ -3376,8 +3684,10 @@ static int s25fs_s_quad_enable(struct spi_nor *nor) static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) { + u8 opcode = nor->addr_width == 4 ? SPINOR_OP_BE_4K_4B : SPINOR_OP_BE_4K; + /* Support 8 x 4KB sectors at bottom */ - return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K); + return spansion_erase_non_uniform(nor, addr, opcode, 0, SZ_32K); } static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, @@ -3431,12 +3741,24 @@ static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, struct spi_nor_flash_parameter *params) { - /* READ_1_1_2 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; - /* READ_1_1_4 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; - /* PP_1_1_4 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* + * The S25FS064S(8MB) supports 1-1-2 and 1-1-4 commands, but params for + * read ops in SFDP are wrong. The other density parts do not support + * 1-1-2 and 1-1-4 commands. + */ + if (params->size == SZ_8M) { + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], + 0, 8, SPINOR_OP_READ_1_1_2, + SNOR_PROTO_1_1_2); + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], + 0, 8, SPINOR_OP_READ_1_1_4, + SNOR_PROTO_1_1_4); + } else { + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + } + /* Use volatile register to enable quad */ params->quad_enable = s25fs_s_quad_enable; } @@ -3925,6 +4247,9 @@ static int spi_nor_init(struct spi_nor *nor) { int err; + if (nor->flags & SNOR_F_HAS_PARALLEL) + nor->spi->flags |= SPI_NOR_ENABLE_MULTI_CS; + err = spi_nor_octal_dtr_enable(nor); if (err) { dev_dbg(nor->dev, "Octal DTR mode not supported\n"); @@ -3943,6 +4268,24 @@ static int spi_nor_init(struct spi_nor *nor) write_enable(nor); write_sr(nor, 0); spi_nor_wait_till_ready(nor); + + /* + * Some Winbond SPI NORs have special SR3 register which is + * used among other things to control whether non-standard + * "Individual Block/Sector Write Protection" (WPS bit) + * locking scheme is activated. This non-standard locking + * scheme is not supported by either U-Boot or Linux SPI + * NOR stack so make sure it is disabled, otherwise the + * SPI NOR may appear locked for no obvious reason. + */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND) { + err = read_sr3(nor); + if (err > 0 && err & SR3_WPS) { + write_enable(nor); + write_sr3(nor, err & ~SR3_WPS); + write_disable(nor); + } + } } if (nor->quad_enable) { @@ -4091,6 +4434,7 @@ int spi_nor_scan(struct spi_nor *nor) struct spi_slave *spi = nor->spi; int ret; int cfi_mtd_nb = 0; + bool shift = 0; #ifdef CONFIG_FLASH_CFI_MTD cfi_mtd_nb = CFI_FLASH_BANKS; @@ -4228,7 +4572,9 @@ int spi_nor_scan(struct spi_nor *nor) nor->addr_width = 3; } - if (nor->addr_width == 3 && mtd->size > SZ_16M) { + if (nor->flags & (SNOR_F_HAS_PARALLEL | SNOR_F_HAS_STACKED)) + shift = 1; + if (nor->addr_width == 3 && (mtd->size >> shift) > SZ_16M) { #ifndef CONFIG_SPI_FLASH_BAR /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; @@ -4238,6 +4584,7 @@ int spi_nor_scan(struct spi_nor *nor) #else /* Configure the BAR - discover bank cmds and read current bank */ nor->addr_width = 3; + set_4byte(nor, info, 0); ret = read_bar(nor, info); if (ret < 0) return ret; @@ -4255,6 +4602,14 @@ int spi_nor_scan(struct spi_nor *nor) if (ret) return ret; + if (nor->flags & SNOR_F_HAS_STACKED) { + nor->spi->flags |= SPI_XFER_U_PAGE; + ret = spi_nor_init(nor); + if (ret) + return ret; + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } + nor->rdsr_dummy = params.rdsr_dummy; nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes; nor->name = info->name; @@ -4262,7 +4617,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->erase_size = mtd->erasesize; nor->sector_size = mtd->erasesize; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD printf("SF: Detected %s with page size ", nor->name); print_size(nor->page_size, ", erase size "); print_size(nor->erase_size, ", total "); diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 88709a52b3a..dfe92c3986e 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -258,7 +258,6 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) }, { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) }, - { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K) }, { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, @@ -339,9 +338,12 @@ const struct flash_info spi_nor_ids[] = { */ { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, - { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fl256s0", 0x010219, 0x4d0080, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fl256s1", 0x010219, 0x4d0180, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs064s", 0x010217, 0x4d0181, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs128s", 0x012018, 0x4d0181, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs256s", 0x010219, 0x4d0181, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, @@ -369,7 +371,7 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, { INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024, - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) }, { INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, @@ -377,15 +379,16 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, { INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024, - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) }, { INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_S28HX_T { INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, { INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) }, + { INFO("s28hs256t", 0x345b19, 0, 256 * 1024, 128, SPI_NOR_OCTAL_DTR_READ) }, { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, { INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) }, - { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ) }, + { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | NO_CHIP_ERASE) }, #endif #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ @@ -430,11 +433,6 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) }, { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) }, { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) }, - { - INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) }, { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, @@ -442,7 +440,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, @@ -541,7 +540,11 @@ const struct flash_info spi_nor_ids[] = { }, { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { + INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, diff --git a/drivers/mux/Makefile b/drivers/mux/Makefile index d4e24789d33..63770e12bd1 100644 --- a/drivers/mux/Makefile +++ b/drivers/mux/Makefile @@ -4,4 +4,4 @@ # Jean-Jacques Hiblot <jjhiblot@ti.com> obj-$(CONFIG_MULTIPLEXER) += mux-uclass.o -obj-$(CONFIG_$(SPL_)MUX_MMIO) += mmio.o +obj-$(CONFIG_$(XPL_)MUX_MMIO) += mmio.o diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index e7d0ddfe25a..403d7e1c679 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -891,7 +891,7 @@ config FEC2_PHY_NORXERR config SYS_DPAA_QBMAN bool "Device tree fixup for QBMan on freescale SOCs" - depends on (ARM || PPC) && !SPL_BUILD + depends on ARM || PPC default y if ARCH_B4860 || \ ARCH_B4420 || \ ARCH_P1023 || \ diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c b/drivers/net/dwc_eth_xgmac_socfpga.c index 270c1b0ca6c..87fb7e887e7 100644 --- a/drivers/net/dwc_eth_xgmac_socfpga.c +++ b/drivers/net/dwc_eth_xgmac_socfpga.c @@ -37,7 +37,7 @@ static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << xgmac->syscon_phy_regshift; - if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { + if (!(IS_ENABLED(CONFIG_XPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { u32 index = ((u64)xgmac->syscon_phy - socfpga_get_sysmgr_addr() - SYSMGR_SOC64_EMAC0) >> 2; diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index bba3fc4d34b..a9e2d8c0972 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -68,7 +68,7 @@ static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) struct dwmac_socfpga_plat *pdata = dev_get_plat(dev); u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() - SYSMGR_SOC64_EMAC0) >> 2; diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile index fd3e68a91dc..8c32cfbfc0f 100644 --- a/drivers/nvme/Makefile +++ b/drivers/nvme/Makefile @@ -4,4 +4,4 @@ obj-y += nvme-uclass.o nvme.o nvme_show.o obj-$(CONFIG_NVME_APPLE) += nvme_apple.o -obj-$(CONFIG_$(SPL_)NVME_PCI) += nvme_pci.o +obj-$(CONFIG_$(XPL_)NVME_PCI) += nvme_pci.o diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 6571e653049..59894d2430b 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -722,7 +722,7 @@ static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor, u32 vendev; int index; - if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP)) + if (xpl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP)) return true; for (index = 0; @@ -798,7 +798,7 @@ static int pci_find_and_bind_driver(struct udevice *parent, if (!(gd->flags & GD_FLG_RELOC) && !(drv->flags & DM_FLAG_PRE_RELOC) && (!CONFIG_IS_ENABLED(PCI_PNP) || - spl_phase() != PHASE_SPL)) + xpl_phase() != PHASE_SPL)) return log_msg_ret("pre", -EPERM); /* diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 78e5de937cd..2753df275ca 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -379,7 +379,7 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void)) } /* In U-Boot proper, collect the information added by SPL (see below) */ - if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL && + if (IS_ENABLED(CONFIG_SPL_VIDEO) && xpl_phase() > PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { struct video_handoff *ho; @@ -425,7 +425,7 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void)) mode_info.vesa.bits_per_pixel); /* In SPL, store the information for use by U-Boot proper */ - if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { + if (xpl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { struct video_handoff *ho; ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0); diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 7a2b764492b..c35f9294dd9 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -8,8 +8,8 @@ obj-y += marvell/ obj-y += rockchip/ obj-y += socionext/ -obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o -obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o +obj-$(CONFIG_$(XPL_)PHY) += phy-uclass.o +obj-$(CONFIG_$(XPL_)NOP_PHY) += nop-phy.o obj-$(CONFIG_MIPI_DPHY_HELPERS) += phy-core-mipi-dphy.o obj-$(CONFIG_AB8500_USB_PHY) += phy-ab8500-usb.o obj-$(CONFIG_APPLE_ATCPHY) += phy-apple-atc.o @@ -19,7 +19,7 @@ obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o obj-$(CONFIG_BCM_SR_PCIE_PHY) += phy-bcm-sr-pcie.o obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o -obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o +obj-$(CONFIG_$(XPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile index af63b32d9f5..e0da41cd7eb 100644 --- a/drivers/phy/cadence/Makefile +++ b/drivers/phy/cadence/Makefile @@ -1,2 +1,2 @@ -obj-$(CONFIG_$(SPL_)PHY_CADENCE_SIERRA) += phy-cadence-sierra.o -obj-$(CONFIG_$(SPL_)PHY_CADENCE_TORRENT) += phy-cadence-torrent.o +obj-$(CONFIG_$(XPL_)PHY_CADENCE_SIERRA) += phy-cadence-sierra.o +obj-$(CONFIG_$(XPL_)PHY_CADENCE_TORRENT) += phy-cadence-torrent.o diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile index 873ddbf0363..699901fd15e 100644 --- a/drivers/phy/ti/Makefile +++ b/drivers/phy/ti/Makefile @@ -1 +1 @@ -obj-$(CONFIG_$(SPL_)PHY_J721E_WIZ) += phy-j721e-wiz.o +obj-$(CONFIG_$(XPL_)PHY_J721E_WIZ) += phy-j721e-wiz.o diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 6d7b7cd9051..634047a91f4 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += pinctrl-uclass.o -obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o +obj-$(CONFIG_$(XPL_)PINCTRL_GENERIC) += pinctrl-generic.o obj-$(CONFIG_PINCTRL_APPLE) += pinctrl-apple.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-y += nxp/ -obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/ +obj-$(CONFIG_$(XPL_)PINCTRL_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ obj-$(CONFIG_PINCTRL_INTEL) += intel/ @@ -18,7 +18,7 @@ obj-$(CONFIG_ARCH_RENESAS) += renesas/ obj-$(CONFIG_ARCH_RZN1) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ -obj-$(CONFIG_$(SPL_)PINCTRL_TEGRA) += tegra/ +obj-$(CONFIG_$(XPL_)PINCTRL_TEGRA) += tegra/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ @@ -32,7 +32,7 @@ obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o -obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o +obj-$(CONFIG_$(XPL_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-y += broadcom/ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c index 6cfe83a593a..19525f82a22 100644 --- a/drivers/pinctrl/intel/pinctrl.c +++ b/drivers/pinctrl/intel/pinctrl.c @@ -273,7 +273,7 @@ static int pinctrl_configure_itss(struct udevice *dev, irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset)); irq &= PAD_CFG1_IRQ_MASK; if (!irq) { - if (spl_phase() > PHASE_TPL) + if (xpl_phase() > PHASE_TPL) log_err("GPIO %u doesn't support APIC routing\n", cfg->pad); @@ -315,7 +315,7 @@ static int pinctrl_pad_reset_config_override(const struct pad_community *comm, return config_value; } } - if (spl_phase() > PHASE_TPL) + if (xpl_phase() > PHASE_TPL) log_err("Logical-to-Chipset mapping not found\n"); return -ENOENT; @@ -622,7 +622,7 @@ int intel_pinctrl_of_to_plat(struct udevice *dev, struct intel_pinctrl_priv *priv = dev_get_priv(dev); if (!comm) { - if (spl_phase() > PHASE_TPL) + if (xpl_phase() > PHASE_TPL) log_err("Cannot find community for pid %d\n", pplat->pid); return -EDOM; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index a3662d46bde..3760c4611ce 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -671,7 +671,7 @@ const struct pinctrl_ops mtk_pinctrl_ops = { }; #if CONFIG_IS_ENABLED(DM_GPIO) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO)) + (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO)) static int mtk_gpio_get(struct udevice *dev, unsigned int off) { int val, err; @@ -794,7 +794,7 @@ bind: int mtk_pinctrl_common_bind(struct udevice *dev) { #if CONFIG_IS_ENABLED(DM_GPIO) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO)) + (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO)) return mtk_gpiochip_register(dev); #else return 0; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index eada1001240..fbf0271f08a 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -39,7 +39,7 @@ struct stm32_gpio_bank { struct list_head list; }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static char pin_name[PINNAME_SIZE]; static const char * const pinmux_mode[GPIOF_COUNT] = { @@ -488,7 +488,7 @@ static struct pinctrl_ops stm32_pinctrl_ops = { #else /* PINCTRL_FULL */ .set_state_simple = stm32_pinctrl_set_state_simple, #endif /* PINCTRL_FULL */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD .get_pin_name = stm32_pinctrl_get_pin_name, .get_pins_count = stm32_pinctrl_get_pins_count, .get_pin_muxing = stm32_pinctrl_get_pin_muxing, diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index aa58b79c24e..2a39d1c8884 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -70,20 +70,20 @@ #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4) #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0) #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28) -#define GPSR0_6 F_(IRQ0, IP0SR0_27_24) -#define GPSR0_5 F_(IRQ1, IP0SR0_23_20) -#define GPSR0_4 F_(IRQ2, IP0SR0_19_16) -#define GPSR0_3 F_(IRQ3, IP0SR0_15_12) +#define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24) +#define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20) +#define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16) +#define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12) #define GPSR0_2 F_(GP0_02, IP0SR0_11_8) #define GPSR0_1 F_(GP0_01, IP0SR0_7_4) #define GPSR0_0 F_(GP0_00, IP0SR0_3_0) /* GPSR1 */ -#define GPSR1_28 F_(HTX3, IP3SR1_19_16) -#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12) -#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8) -#define GPSR1_25 F_(HSCK3, IP3SR1_7_4) -#define GPSR1_24 F_(HRX3, IP3SR1_3_0) +#define GPSR1_28 F_(HTX3_A, IP3SR1_19_16) +#define GPSR1_27 F_(HCTS3_N_A, IP3SR1_15_12) +#define GPSR1_26 F_(HRTS3_N_A, IP3SR1_11_8) +#define GPSR1_25 F_(HSCK3_A, IP3SR1_7_4) +#define GPSR1_24 F_(HRX3_A, IP3SR1_3_0) #define GPSR1_23 F_(GP1_23, IP2SR1_31_28) #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24) #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20) @@ -121,14 +121,14 @@ #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12) #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8) #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4) -#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0) -#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28) +#define GPSR2_8 F_(TPU0TO0_A, IP1SR2_3_0) +#define GPSR2_7 F_(TPU0TO1_A, IP0SR2_31_28) #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24) -#define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20) +#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20) #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16) #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12) #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8) -#define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4) +#define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4) #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0) /* GPSR3 */ @@ -277,13 +277,13 @@ /* SR0 */ /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ @@ -292,72 +292,72 @@ #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR1 */ /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR2 */ /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX_A) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX_A) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_31_28 FM(TPU0TO1_A) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ @@ -383,8 +383,8 @@ #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ @@ -720,22 +720,22 @@ static const u16 pinmux_data[] = { /* IP0SR0 */ PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B), - PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A), + PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B), PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1), PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2), - PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3), + PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A), PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK), - PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2), + PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A), PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD), - PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1), + PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A), PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD), - PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0), + PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A), PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC), PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2), @@ -752,75 +752,75 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD), PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2), - PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1), - PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A), + PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A), + PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B), PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1), - PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1), - PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1), + PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A), + PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A), PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC), - PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1), - PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1), + PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A), + PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A), /* IP2SR0 */ PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD), - PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N), - PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N), + PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A), + PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A), PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK), - PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N), - PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N), + PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A), + PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A), PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD), - PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1), - PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1), + PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A), + PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A), /* IP0SR1 */ PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2), - PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A), - PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3), + PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B), + PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B), PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1), - PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A), - PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3), + PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B), + PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B), PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC), - PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A), - PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N), + PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B), + PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B), PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK), - PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A), - PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N), + PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B), + PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B), PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD), - PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A), - PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3), + PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B), + PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B), PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD), PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2), - PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X), - PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_X), + PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B), + PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B), PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1), - PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X), - PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_X), + PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B), + PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B), /* IP1SR1 */ PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC), - PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_X), - PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_X), + PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B), + PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B), PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B), PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD), - PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_X), - PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_X), + PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B), + PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B), PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B), PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK), - PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X), - PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_X), + PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B), + PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B), PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD), @@ -829,15 +829,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N), PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N), - PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A), + PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8), PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N), PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N), - PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A), + PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9), PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0), PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0), - PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A), + PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0), /* IP2SR1 */ PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0), @@ -847,99 +847,99 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A), PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK), - PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3), + PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B), PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS), - PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4), + PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B), PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD), - PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_A), + PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B), PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT), - PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A), + PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B), PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN), PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A), - PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2), + PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A), PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1), PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B), /* IP3SR1 */ - PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3), + PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A), PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A), PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2), - PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3), + PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A), PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A), PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK), - PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A), + PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B), - PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N), + PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A), PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A), PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD), - PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A), + PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B), - PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N), + PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A), PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A), PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD), - PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3), + PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A), PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A), PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC), /* IP0SR2 */ PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA), PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX), - PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A), + PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B), - PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N), + PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A), PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX), - PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A), + PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B), PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR), - PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX), + PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX_A), PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5), PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR), - PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX), + PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX_A), PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B), PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR), - PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N), + PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A), PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB), - PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1), + PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A), PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX), - PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_B), + PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C), /* IP1SR2 */ - PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0), + PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A), PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX), - PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A), + PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B), PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK), - PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_X), + PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B), PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX), - PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_X), + PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B), PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR), PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), - PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2), - PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_A), + PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A), + PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C), PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX), - PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3), + PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A), PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B), - PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A), + PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C), PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX), - PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B), + PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2), PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX), PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B), @@ -981,12 +981,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN), PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN), PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A), - PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X), + PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_A), PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT), PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT), PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A), - PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X), + PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_A), PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL), @@ -1533,15 +1533,14 @@ static const unsigned int canfd4_data_mux[] = { }; /* - CANFD5 ----------------------------------------------------------------- */ -static const unsigned int canfd5_data_pins[] = { - /* CANFD5_TX, CANFD5_RX */ +static const unsigned int canfd5_data_a_pins[] = { + /* CANFD5_TX_A, CANFD5_RX_A */ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), }; -static const unsigned int canfd5_data_mux[] = { - CANFD5_TX_MARK, CANFD5_RX_MARK, +static const unsigned int canfd5_data_a_mux[] = { + CANFD5_TX_A_MARK, CANFD5_RX_A_MARK, }; -/* - CANFD5_B ----------------------------------------------------------------- */ static const unsigned int canfd5_data_b_pins[] = { /* CANFD5_TX_B, CANFD5_RX_B */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), @@ -1601,49 +1600,48 @@ static const unsigned int hscif0_ctrl_mux[] = { }; /* - HSCIF1 ----------------------------------------------------------------- */ -static const unsigned int hscif1_data_pins[] = { - /* HRX1, HTX1 */ +static const unsigned int hscif1_data_a_pins[] = { + /* HRX1_A, HTX1_A */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), }; -static const unsigned int hscif1_data_mux[] = { - HRX1_MARK, HTX1_MARK, +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, }; -static const unsigned int hscif1_clk_pins[] = { - /* HSCK1 */ +static const unsigned int hscif1_clk_a_pins[] = { + /* HSCK1_A */ RCAR_GP_PIN(0, 18), }; -static const unsigned int hscif1_clk_mux[] = { - HSCK1_MARK, +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, }; -static const unsigned int hscif1_ctrl_pins[] = { - /* HRTS1_N, HCTS1_N */ +static const unsigned int hscif1_ctrl_a_pins[] = { + /* HRTS1_N_A, HCTS1_N_A */ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), }; -static const unsigned int hscif1_ctrl_mux[] = { - HRTS1_N_MARK, HCTS1_N_MARK, +static const unsigned int hscif1_ctrl_a_mux[] = { + HRTS1_N_A_MARK, HCTS1_N_A_MARK, }; -/* - HSCIF1_X---------------------------------------------------------------- */ -static const unsigned int hscif1_data_x_pins[] = { - /* HRX1_X, HTX1_X */ +static const unsigned int hscif1_data_b_pins[] = { + /* HRX1_B, HTX1_B */ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), }; -static const unsigned int hscif1_data_x_mux[] = { - HRX1_X_MARK, HTX1_X_MARK, +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, }; -static const unsigned int hscif1_clk_x_pins[] = { - /* HSCK1_X */ +static const unsigned int hscif1_clk_b_pins[] = { + /* HSCK1_B */ RCAR_GP_PIN(1, 10), }; -static const unsigned int hscif1_clk_x_mux[] = { - HSCK1_X_MARK, +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, }; -static const unsigned int hscif1_ctrl_x_pins[] = { - /* HRTS1_N_X, HCTS1_N_X */ +static const unsigned int hscif1_ctrl_b_pins[] = { + /* HRTS1_N_B, HCTS1_N_B */ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), }; -static const unsigned int hscif1_ctrl_x_mux[] = { - HRTS1_N_X_MARK, HCTS1_N_X_MARK, +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, }; /* - HSCIF2 ----------------------------------------------------------------- */ @@ -1670,49 +1668,48 @@ static const unsigned int hscif2_ctrl_mux[] = { }; /* - HSCIF3 ----------------------------------------------------------------- */ -static const unsigned int hscif3_data_pins[] = { - /* HRX3, HTX3 */ +static const unsigned int hscif3_data_a_pins[] = { + /* HRX3_A, HTX3_A */ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28), }; -static const unsigned int hscif3_data_mux[] = { - HRX3_MARK, HTX3_MARK, +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, }; -static const unsigned int hscif3_clk_pins[] = { - /* HSCK3 */ +static const unsigned int hscif3_clk_a_pins[] = { + /* HSCK3_A */ RCAR_GP_PIN(1, 25), }; -static const unsigned int hscif3_clk_mux[] = { - HSCK3_MARK, +static const unsigned int hscif3_clk_a_mux[] = { + HSCK3_A_MARK, }; -static const unsigned int hscif3_ctrl_pins[] = { - /* HRTS3_N, HCTS3_N */ +static const unsigned int hscif3_ctrl_a_pins[] = { + /* HRTS3_N_A, HCTS3_N_A */ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), }; -static const unsigned int hscif3_ctrl_mux[] = { - HRTS3_N_MARK, HCTS3_N_MARK, +static const unsigned int hscif3_ctrl_a_mux[] = { + HRTS3_N_A_MARK, HCTS3_N_A_MARK, }; -/* - HSCIF3_A ----------------------------------------------------------------- */ -static const unsigned int hscif3_data_a_pins[] = { - /* HRX3_A, HTX3_A */ +static const unsigned int hscif3_data_b_pins[] = { + /* HRX3_B, HTX3_B */ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), }; -static const unsigned int hscif3_data_a_mux[] = { - HRX3_A_MARK, HTX3_A_MARK, +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, }; -static const unsigned int hscif3_clk_a_pins[] = { - /* HSCK3_A */ +static const unsigned int hscif3_clk_b_pins[] = { + /* HSCK3_B */ RCAR_GP_PIN(1, 3), }; -static const unsigned int hscif3_clk_a_mux[] = { - HSCK3_A_MARK, +static const unsigned int hscif3_clk_b_mux[] = { + HSCK3_B_MARK, }; -static const unsigned int hscif3_ctrl_a_pins[] = { - /* HRTS3_N_A, HCTS3_N_A */ +static const unsigned int hscif3_ctrl_b_pins[] = { + /* HRTS3_N_B, HCTS3_N_B */ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), }; -static const unsigned int hscif3_ctrl_a_mux[] = { - HRTS3_N_A_MARK, HCTS3_N_A_MARK, +static const unsigned int hscif3_ctrl_b_mux[] = { + HRTS3_N_B_MARK, HCTS3_N_B_MARK, }; /* - I2C0 ------------------------------------------------------------------- */ @@ -1769,6 +1766,90 @@ static const unsigned int i2c5_mux[] = { SDA5_MARK, SCL5_MARK, }; +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_a_pins[] = { + /* IRQ0_A */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int intc_ex_irq0_a_mux[] = { + IRQ0_A_MARK, +}; +static const unsigned int intc_ex_irq0_b_pins[] = { + /* IRQ0_B */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int intc_ex_irq0_b_mux[] = { + IRQ0_B_MARK, +}; + +static const unsigned int intc_ex_irq1_a_pins[] = { + /* IRQ1_A */ + RCAR_GP_PIN(0, 5), +}; +static const unsigned int intc_ex_irq1_a_mux[] = { + IRQ1_A_MARK, +}; +static const unsigned int intc_ex_irq1_b_pins[] = { + /* IRQ1_B */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int intc_ex_irq1_b_mux[] = { + IRQ1_B_MARK, +}; + +static const unsigned int intc_ex_irq2_a_pins[] = { + /* IRQ2_A */ + RCAR_GP_PIN(0, 4), +}; +static const unsigned int intc_ex_irq2_a_mux[] = { + IRQ2_A_MARK, +}; +static const unsigned int intc_ex_irq2_b_pins[] = { + /* IRQ2_B */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int intc_ex_irq2_b_mux[] = { + IRQ2_B_MARK, +}; + +static const unsigned int intc_ex_irq3_a_pins[] = { + /* IRQ3_A */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int intc_ex_irq3_a_mux[] = { + IRQ3_A_MARK, +}; +static const unsigned int intc_ex_irq3_b_pins[] = { + /* IRQ3_B */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int intc_ex_irq3_b_mux[] = { + IRQ3_B_MARK, +}; + +static const unsigned int intc_ex_irq4_a_pins[] = { + /* IRQ4_A */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int intc_ex_irq4_a_mux[] = { + IRQ4_A_MARK, +}; +static const unsigned int intc_ex_irq4_b_pins[] = { + /* IRQ4_B */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int intc_ex_irq4_b_mux[] = { + IRQ4_B_MARK, +}; + +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { /* MMC_SD_D[0:3], MMC_D[4:7] */ @@ -2095,16 +2176,16 @@ static const unsigned int pcie1_clkreq_n_mux[] = { PCIE1_CLKREQ_N_MARK, }; -/* - PWM0_A ------------------------------------------------------------------- */ -static const unsigned int pwm0_a_pins[] = { - /* PWM0_A */ +/* - PWM0 ------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + /* PWM0 */ RCAR_GP_PIN(1, 15), }; -static const unsigned int pwm0_a_mux[] = { - PWM0_A_MARK, +static const unsigned int pwm0_mux[] = { + PWM0_MARK, }; -/* - PWM1_A ------------------------------------------------------------------- */ +/* - PWM1 ------------------------------------------------------------------- */ static const unsigned int pwm1_a_pins[] = { /* PWM1_A */ RCAR_GP_PIN(3, 13), @@ -2113,7 +2194,6 @@ static const unsigned int pwm1_a_mux[] = { PWM1_A_MARK, }; -/* - PWM1_B ------------------------------------------------------------------- */ static const unsigned int pwm1_b_pins[] = { /* PWM1_B */ RCAR_GP_PIN(2, 13), @@ -2122,16 +2202,16 @@ static const unsigned int pwm1_b_mux[] = { PWM1_B_MARK, }; -/* - PWM2_B ------------------------------------------------------------------- */ -static const unsigned int pwm2_b_pins[] = { - /* PWM2_B */ +/* - PWM2 ------------------------------------------------------------------- */ +static const unsigned int pwm2_pins[] = { + /* PWM2 */ RCAR_GP_PIN(2, 14), }; -static const unsigned int pwm2_b_mux[] = { - PWM2_B_MARK, +static const unsigned int pwm2_mux[] = { + PWM2_MARK, }; -/* - PWM3_A ------------------------------------------------------------------- */ +/* - PWM3 ------------------------------------------------------------------- */ static const unsigned int pwm3_a_pins[] = { /* PWM3_A */ RCAR_GP_PIN(1, 22), @@ -2140,7 +2220,6 @@ static const unsigned int pwm3_a_mux[] = { PWM3_A_MARK, }; -/* - PWM3_B ------------------------------------------------------------------- */ static const unsigned int pwm3_b_pins[] = { /* PWM3_B */ RCAR_GP_PIN(2, 15), @@ -2185,22 +2264,22 @@ static const unsigned int pwm7_mux[] = { PWM7_MARK, }; -/* - PWM8_A ------------------------------------------------------------------- */ -static const unsigned int pwm8_a_pins[] = { - /* PWM8_A */ +/* - PWM8 ------------------------------------------------------------------- */ +static const unsigned int pwm8_pins[] = { + /* PWM8 */ RCAR_GP_PIN(1, 13), }; -static const unsigned int pwm8_a_mux[] = { - PWM8_A_MARK, +static const unsigned int pwm8_mux[] = { + PWM8_MARK, }; -/* - PWM9_A ------------------------------------------------------------------- */ -static const unsigned int pwm9_a_pins[] = { - /* PWM9_A */ +/* - PWM9 ------------------------------------------------------------------- */ +static const unsigned int pwm9_pins[] = { + /* PWM9 */ RCAR_GP_PIN(1, 14), }; -static const unsigned int pwm9_a_mux[] = { - PWM9_A_MARK, +static const unsigned int pwm9_mux[] = { + PWM9_MARK, }; /* - QSPI0 ------------------------------------------------------------------ */ @@ -2263,75 +2342,51 @@ static const unsigned int scif0_ctrl_mux[] = { }; /* - SCIF1 ------------------------------------------------------------------ */ -static const unsigned int scif1_data_pins[] = { - /* RX1, TX1 */ +static const unsigned int scif1_data_a_pins[] = { + /* RX1_A, TX1_A */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), }; -static const unsigned int scif1_data_mux[] = { - RX1_MARK, TX1_MARK, +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, }; -static const unsigned int scif1_clk_pins[] = { - /* SCK1 */ +static const unsigned int scif1_clk_a_pins[] = { + /* SCK1_A */ RCAR_GP_PIN(0, 18), }; -static const unsigned int scif1_clk_mux[] = { - SCK1_MARK, +static const unsigned int scif1_clk_a_mux[] = { + SCK1_A_MARK, }; -static const unsigned int scif1_ctrl_pins[] = { - /* RTS1_N, CTS1_N */ +static const unsigned int scif1_ctrl_a_pins[] = { + /* RTS1_N_A, CTS1_N_A */ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), }; -static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_MARK, CTS1_N_MARK, +static const unsigned int scif1_ctrl_a_mux[] = { + RTS1_N_A_MARK, CTS1_N_A_MARK, }; -/* - SCIF1_X ------------------------------------------------------------------ */ -static const unsigned int scif1_data_x_pins[] = { - /* RX1_X, TX1_X */ +static const unsigned int scif1_data_b_pins[] = { + /* RX1_B, TX1_B */ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), }; -static const unsigned int scif1_data_x_mux[] = { - RX1_X_MARK, TX1_X_MARK, +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, }; -static const unsigned int scif1_clk_x_pins[] = { - /* SCK1_X */ +static const unsigned int scif1_clk_b_pins[] = { + /* SCK1_B */ RCAR_GP_PIN(1, 10), }; -static const unsigned int scif1_clk_x_mux[] = { - SCK1_X_MARK, +static const unsigned int scif1_clk_b_mux[] = { + SCK1_B_MARK, }; -static const unsigned int scif1_ctrl_x_pins[] = { - /* RTS1_N_X, CTS1_N_X */ +static const unsigned int scif1_ctrl_b_pins[] = { + /* RTS1_N_B, CTS1_N_B */ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), }; -static const unsigned int scif1_ctrl_x_mux[] = { - RTS1_N_X_MARK, CTS1_N_X_MARK, +static const unsigned int scif1_ctrl_b_mux[] = { + RTS1_N_B_MARK, CTS1_N_B_MARK, }; /* - SCIF3 ------------------------------------------------------------------ */ -static const unsigned int scif3_data_pins[] = { - /* RX3, TX3 */ - RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), -}; -static const unsigned int scif3_data_mux[] = { - RX3_MARK, TX3_MARK, -}; -static const unsigned int scif3_clk_pins[] = { - /* SCK3 */ - RCAR_GP_PIN(1, 4), -}; -static const unsigned int scif3_clk_mux[] = { - SCK3_MARK, -}; -static const unsigned int scif3_ctrl_pins[] = { - /* RTS3_N, CTS3_N */ - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), -}; -static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_MARK, CTS3_N_MARK, -}; - -/* - SCIF3_A ------------------------------------------------------------------ */ static const unsigned int scif3_data_a_pins[] = { /* RX3_A, TX3_A */ RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28), @@ -2354,6 +2409,28 @@ static const unsigned int scif3_ctrl_a_mux[] = { RTS3_N_A_MARK, CTS3_N_A_MARK, }; +static const unsigned int scif3_data_b_pins[] = { + /* RX3_B, TX3_B */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_MARK, TX3_B_MARK, +}; +static const unsigned int scif3_clk_b_pins[] = { + /* SCK3_B */ + RCAR_GP_PIN(1, 4), +}; +static const unsigned int scif3_clk_b_mux[] = { + SCK3_B_MARK, +}; +static const unsigned int scif3_ctrl_b_pins[] = { + /* RTS3_N_B, CTS3_N_B */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int scif3_ctrl_b_mux[] = { + RTS3_N_B_MARK, CTS3_N_B_MARK, +}; + /* - SCIF4 ------------------------------------------------------------------ */ static const unsigned int scif4_data_pins[] = { /* RX4, TX4 */ @@ -2410,64 +2487,63 @@ static const unsigned int ssi_ctrl_mux[] = { SSI_SCK_MARK, SSI_WS_MARK, }; -/* - TPU ------------------------------------------------------------------- */ -static const unsigned int tpu_to0_pins[] = { - /* TPU0TO0 */ +/* - TPU -------------------------------------------------------------------- */ +static const unsigned int tpu_to0_a_pins[] = { + /* TPU0TO0_A */ RCAR_GP_PIN(2, 8), }; -static const unsigned int tpu_to0_mux[] = { - TPU0TO0_MARK, +static const unsigned int tpu_to0_a_mux[] = { + TPU0TO0_A_MARK, }; -static const unsigned int tpu_to1_pins[] = { - /* TPU0TO1 */ +static const unsigned int tpu_to1_a_pins[] = { + /* TPU0TO1_A */ RCAR_GP_PIN(2, 7), }; -static const unsigned int tpu_to1_mux[] = { - TPU0TO1_MARK, +static const unsigned int tpu_to1_a_mux[] = { + TPU0TO1_A_MARK, }; -static const unsigned int tpu_to2_pins[] = { - /* TPU0TO2 */ +static const unsigned int tpu_to2_a_pins[] = { + /* TPU0TO2_A */ RCAR_GP_PIN(2, 12), }; -static const unsigned int tpu_to2_mux[] = { - TPU0TO2_MARK, +static const unsigned int tpu_to2_a_mux[] = { + TPU0TO2_A_MARK, }; -static const unsigned int tpu_to3_pins[] = { - /* TPU0TO3 */ +static const unsigned int tpu_to3_a_pins[] = { + /* TPU0TO3_A */ RCAR_GP_PIN(2, 13), }; -static const unsigned int tpu_to3_mux[] = { - TPU0TO3_MARK, +static const unsigned int tpu_to3_a_mux[] = { + TPU0TO3_A_MARK, }; -/* - TPU_A ------------------------------------------------------------------- */ -static const unsigned int tpu_to0_a_pins[] = { - /* TPU0TO0_A */ +static const unsigned int tpu_to0_b_pins[] = { + /* TPU0TO0_B */ RCAR_GP_PIN(1, 25), }; -static const unsigned int tpu_to0_a_mux[] = { - TPU0TO0_A_MARK, +static const unsigned int tpu_to0_b_mux[] = { + TPU0TO0_B_MARK, }; -static const unsigned int tpu_to1_a_pins[] = { - /* TPU0TO1_A */ +static const unsigned int tpu_to1_b_pins[] = { + /* TPU0TO1_B */ RCAR_GP_PIN(1, 26), }; -static const unsigned int tpu_to1_a_mux[] = { - TPU0TO1_A_MARK, +static const unsigned int tpu_to1_b_mux[] = { + TPU0TO1_B_MARK, }; -static const unsigned int tpu_to2_a_pins[] = { - /* TPU0TO2_A */ +static const unsigned int tpu_to2_b_pins[] = { + /* TPU0TO2_B */ RCAR_GP_PIN(2, 0), }; -static const unsigned int tpu_to2_a_mux[] = { - TPU0TO2_A_MARK, +static const unsigned int tpu_to2_b_mux[] = { + TPU0TO2_B_MARK, }; -static const unsigned int tpu_to3_a_pins[] = { - /* TPU0TO3_A */ +static const unsigned int tpu_to3_b_pins[] = { + /* TPU0TO3_B */ RCAR_GP_PIN(2, 1), }; -static const unsigned int tpu_to3_a_mux[] = { - TPU0TO3_A_MARK, +static const unsigned int tpu_to3_b_mux[] = { + TPU0TO3_B_MARK, }; /* - TSN0 ------------------------------------------------ */ @@ -2580,8 +2656,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(canfd2_data), SH_PFC_PIN_GROUP(canfd3_data), SH_PFC_PIN_GROUP(canfd4_data), - SH_PFC_PIN_GROUP(canfd5_data), /* suffix might be updated */ - SH_PFC_PIN_GROUP(canfd5_data_b), /* suffix might be updated */ + SH_PFC_PIN_GROUP(canfd5_data_a), + SH_PFC_PIN_GROUP(canfd5_data_b), SH_PFC_PIN_GROUP(canfd6_data), SH_PFC_PIN_GROUP(canfd7_data), SH_PFC_PIN_GROUP(can_clk), @@ -2589,21 +2665,21 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif1_data), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif1_clk), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif1_ctrl), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif1_data_x), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif1_clk_x), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif1_ctrl_x), /* suffix might be updated */ + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), SH_PFC_PIN_GROUP(hscif2_data), SH_PFC_PIN_GROUP(hscif2_clk), SH_PFC_PIN_GROUP(hscif2_ctrl), - SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */ - SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */ + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk_a), + SH_PFC_PIN_GROUP(hscif3_ctrl_a), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_clk_b), + SH_PFC_PIN_GROUP(hscif3_ctrl_b), SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1), @@ -2612,6 +2688,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(intc_ex_irq0_a), + SH_PFC_PIN_GROUP(intc_ex_irq0_b), + SH_PFC_PIN_GROUP(intc_ex_irq1_a), + SH_PFC_PIN_GROUP(intc_ex_irq1_b), + SH_PFC_PIN_GROUP(intc_ex_irq2_a), + SH_PFC_PIN_GROUP(intc_ex_irq2_b), + SH_PFC_PIN_GROUP(intc_ex_irq3_a), + SH_PFC_PIN_GROUP(intc_ex_irq3_b), + SH_PFC_PIN_GROUP(intc_ex_irq4_a), + SH_PFC_PIN_GROUP(intc_ex_irq4_b), + SH_PFC_PIN_GROUP(intc_ex_irq5), + BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), @@ -2665,18 +2753,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pcie0_clkreq_n), SH_PFC_PIN_GROUP(pcie1_clkreq_n), - SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */ + SH_PFC_PIN_GROUP(pwm0), SH_PFC_PIN_GROUP(pwm1_a), SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */ + SH_PFC_PIN_GROUP(pwm2), SH_PFC_PIN_GROUP(pwm3_a), SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4), SH_PFC_PIN_GROUP(pwm5), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(pwm7), - SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */ - SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */ + SH_PFC_PIN_GROUP(pwm8), + SH_PFC_PIN_GROUP(pwm9), SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), @@ -2688,18 +2776,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif1_data), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif1_clk), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif1_ctrl), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif1_data_x), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif1_clk_x), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif1_ctrl_x), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif3_data_a), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif3_clk_a), /* suffix might be updated */ - SH_PFC_PIN_GROUP(scif3_ctrl_a), /* suffix might be updated */ + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk_a), + SH_PFC_PIN_GROUP(scif1_ctrl_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_ctrl_b), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk_a), + SH_PFC_PIN_GROUP(scif3_ctrl_a), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_clk_b), + SH_PFC_PIN_GROUP(scif3_ctrl_b), SH_PFC_PIN_GROUP(scif4_data), SH_PFC_PIN_GROUP(scif4_clk), SH_PFC_PIN_GROUP(scif4_ctrl), @@ -2709,14 +2797,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi_data), SH_PFC_PIN_GROUP(ssi_ctrl), - SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */ - SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */ - SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */ - SH_PFC_PIN_GROUP(tpu_to1_a), /* suffix might be updated */ - SH_PFC_PIN_GROUP(tpu_to2), /* suffix might be updated */ - SH_PFC_PIN_GROUP(tpu_to2_a), /* suffix might be updated */ - SH_PFC_PIN_GROUP(tpu_to3), /* suffix might be updated */ - SH_PFC_PIN_GROUP(tpu_to3_a), /* suffix might be updated */ + SH_PFC_PIN_GROUP(tpu_to0_a), + SH_PFC_PIN_GROUP(tpu_to0_b), + SH_PFC_PIN_GROUP(tpu_to1_a), + SH_PFC_PIN_GROUP(tpu_to1_b), + SH_PFC_PIN_GROUP(tpu_to2_a), + SH_PFC_PIN_GROUP(tpu_to2_b), + SH_PFC_PIN_GROUP(tpu_to3_a), + SH_PFC_PIN_GROUP(tpu_to3_b), SH_PFC_PIN_GROUP(tsn0_link), SH_PFC_PIN_GROUP(tsn0_phy_int), @@ -2790,8 +2878,7 @@ static const char * const canfd4_groups[] = { }; static const char * const canfd5_groups[] = { - /* suffix might be updated */ - "canfd5_data", + "canfd5_data_a", "canfd5_data_b", }; @@ -2814,13 +2901,12 @@ static const char * const hscif0_groups[] = { }; static const char * const hscif1_groups[] = { - /* suffix might be updated */ - "hscif1_data", - "hscif1_clk", - "hscif1_ctrl", - "hscif1_data_x", - "hscif1_clk_x", - "hscif1_ctrl_x", + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_ctrl_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", }; static const char * const hscif2_groups[] = { @@ -2830,13 +2916,12 @@ static const char * const hscif2_groups[] = { }; static const char * const hscif3_groups[] = { - /* suffix might be updated */ - "hscif3_data", - "hscif3_clk", - "hscif3_ctrl", "hscif3_data_a", "hscif3_clk_a", "hscif3_ctrl_a", + "hscif3_data_b", + "hscif3_clk_b", + "hscif3_ctrl_b", }; static const char * const i2c0_groups[] = { @@ -2863,6 +2948,20 @@ static const char * const i2c5_groups[] = { "i2c5", }; +static const char * const intc_ex_groups[] = { + "intc_ex_irq0_a", + "intc_ex_irq0_b", + "intc_ex_irq1_a", + "intc_ex_irq1_b", + "intc_ex_irq2_a", + "intc_ex_irq2_b", + "intc_ex_irq3_a", + "intc_ex_irq3_b", + "intc_ex_irq4_a", + "intc_ex_irq4_b", + "intc_ex_irq5", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -2933,8 +3032,7 @@ static const char * const pcie_groups[] = { }; static const char * const pwm0_groups[] = { - /* suffix might be updated */ - "pwm0_a", + "pwm0", }; static const char * const pwm1_groups[] = { @@ -2943,8 +3041,7 @@ static const char * const pwm1_groups[] = { }; static const char * const pwm2_groups[] = { - /* suffix might be updated */ - "pwm2_b", + "pwm2", }; static const char * const pwm3_groups[] = { @@ -2969,13 +3066,11 @@ static const char * const pwm7_groups[] = { }; static const char * const pwm8_groups[] = { - /* suffix might be updated */ - "pwm8_a", + "pwm8", }; static const char * const pwm9_groups[] = { - /* suffix might be updated */ - "pwm9_a", + "pwm9", }; static const char * const qspi0_groups[] = { @@ -2997,23 +3092,21 @@ static const char * const scif0_groups[] = { }; static const char * const scif1_groups[] = { - /* suffix might be updated */ - "scif1_data", - "scif1_clk", - "scif1_ctrl", - "scif1_data_x", - "scif1_clk_x", - "scif1_ctrl_x", + "scif1_data_a", + "scif1_clk_a", + "scif1_ctrl_a", + "scif1_data_b", + "scif1_clk_b", + "scif1_ctrl_b", }; static const char * const scif3_groups[] = { - /* suffix might be updated */ - "scif3_data", - "scif3_clk", - "scif3_ctrl", "scif3_data_a", "scif3_clk_a", "scif3_ctrl_a", + "scif3_data_b", + "scif3_clk_b", + "scif3_ctrl_b", }; static const char * const scif4_groups[] = { @@ -3036,15 +3129,14 @@ static const char * const ssi_groups[] = { }; static const char * const tpu_groups[] = { - /* suffix might be updated */ - "tpu_to0", "tpu_to0_a", - "tpu_to1", + "tpu_to0_b", "tpu_to1_a", - "tpu_to2", + "tpu_to1_b", "tpu_to2_a", - "tpu_to3", + "tpu_to2_b", "tpu_to3_a", + "tpu_to3_b", }; static const char * const tsn0_groups[] = { @@ -3087,6 +3179,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c index 2f09e767288..bfabf0c379a 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779h0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c @@ -77,10 +77,10 @@ #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4) #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0) #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28) -#define GPSR0_6 F_(IRQ0, IP0SR0_27_24) -#define GPSR0_5 F_(IRQ1, IP0SR0_23_20) -#define GPSR0_4 F_(IRQ2, IP0SR0_19_16) -#define GPSR0_3 F_(IRQ3, IP0SR0_15_12) +#define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24) +#define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20) +#define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16) +#define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12) #define GPSR0_2 F_(GP0_02, IP0SR0_11_8) #define GPSR0_1 F_(GP0_01, IP0SR0_7_4) #define GPSR0_0 F_(GP0_00, IP0SR0_3_0) @@ -261,15 +261,16 @@ #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) + /* SR0 */ /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ @@ -673,16 +674,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2), - PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3), + PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A), PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK), - PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2), + PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A), PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD), - PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1), + PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A), PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD), - PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0), + PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A), PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC), PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2), @@ -1237,6 +1238,30 @@ static const unsigned int avb0_mdio_pins[] = { static const unsigned int avb0_mdio_mux[] = { AVB0_MDC_MARK, AVB0_MDIO_MARK, }; +static const unsigned int avb0_mii_pins[] = { + /* + * AVB0_MII_TD0, AVB0_MII_TD1, AVB0_MII_TD2, + * AVB0_MII_TD3, AVB0_MII_RD0, AVB0_MII_RD1, + * AVB0_MII_RD2, AVB0_MII_RD3, AVB0_MII_TXC, + * AVB0_MII_TX_EN, AVB0_MII_TX_ER, AVB0_MII_RXC, + * AVB0_MII_RX_DV, AVB0_MII_RX_ER, AVB0_MII_CRS, + * AVB0_MII_COL + */ + RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 6), + RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), + RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 15), + RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 19), + RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 1), + RCAR_GP_PIN(7, 0), +}; +static const unsigned int avb0_mii_mux[] = { + AVB0_MII_TD0_MARK, AVB0_MII_TD1_MARK, AVB0_MII_TD2_MARK, + AVB0_MII_TD3_MARK, AVB0_MII_RD0_MARK, AVB0_MII_RD1_MARK, + AVB0_MII_RD2_MARK, AVB0_MII_RD3_MARK, AVB0_MII_TXC_MARK, + AVB0_MII_TX_EN_MARK, AVB0_MII_TX_ER_MARK, AVB0_MII_RXC_MARK, + AVB0_MII_RX_DV_MARK, AVB0_MII_RX_ER_MARK, AVB0_MII_CRS_MARK, + AVB0_MII_COL_MARK, +}; static const unsigned int avb0_rgmii_pins[] = { /* * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, @@ -1315,6 +1340,30 @@ static const unsigned int avb1_mdio_pins[] = { static const unsigned int avb1_mdio_mux[] = { AVB1_MDC_MARK, AVB1_MDIO_MARK, }; +static const unsigned int avb1_mii_pins[] = { + /* + * AVB1_MII_TD0, AVB1_MII_TD1, AVB1_MII_TD2, + * AVB1_MII_TD3, AVB1_MII_RD0, AVB1_MII_RD1, + * AVB1_MII_RD2, AVB1_MII_RD3, AVB1_MII_TXC, + * AVB1_MII_TX_EN, AVB1_MII_TX_ER, AVB1_MII_RXC, + * AVB1_MII_RX_DV, AVB1_MII_RX_ER, AVB1_MII_CRS, + * AVB1_MII_COL + */ + RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 16), + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14), + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 6), + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 8), + RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 10), +}; +static const unsigned int avb1_mii_mux[] = { + AVB1_MII_TD0_MARK, AVB1_MII_TD1_MARK, AVB1_MII_TD2_MARK, + AVB1_MII_TD3_MARK, AVB1_MII_RD0_MARK, AVB1_MII_RD1_MARK, + AVB1_MII_RD2_MARK, AVB1_MII_RD3_MARK, AVB1_MII_TXC_MARK, + AVB1_MII_TX_EN_MARK, AVB1_MII_TX_ER_MARK, AVB1_MII_RXC_MARK, + AVB1_MII_RX_DV_MARK, AVB1_MII_RX_ER_MARK, AVB1_MII_CRS_MARK, + AVB1_MII_COL_MARK, +}; static const unsigned int avb1_rgmii_pins[] = { /* * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, @@ -1510,7 +1559,7 @@ static const unsigned int hscif0_ctrl_mux[] = { HRTS0_N_MARK, HCTS0_N_MARK, }; -/* - HSCIF1_A ----------------------------------------------------------------- */ +/* - HSCIF1 ------------------------------------------------------------------- */ static const unsigned int hscif1_data_a_pins[] = { /* HRX1_A, HTX1_A */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), @@ -1533,7 +1582,6 @@ static const unsigned int hscif1_ctrl_a_mux[] = { HRTS1_N_A_MARK, HCTS1_N_A_MARK, }; -/* - HSCIF1_B ---------------------------------------------------------------- */ static const unsigned int hscif1_data_b_pins[] = { /* HRX1_B, HTX1_B */ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), @@ -1579,7 +1627,7 @@ static const unsigned int hscif2_ctrl_mux[] = { HRTS2_N_MARK, HCTS2_N_MARK, }; -/* - HSCIF3_A ----------------------------------------------------------------- */ +/* - HSCIF3 ------------------------------------------------------------------- */ static const unsigned int hscif3_data_a_pins[] = { /* HRX3_A, HTX3_A */ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28), @@ -1602,7 +1650,6 @@ static const unsigned int hscif3_ctrl_a_mux[] = { HRTS3_N_A_MARK, HCTS3_N_A_MARK, }; -/* - HSCIF3_B ----------------------------------------------------------------- */ static const unsigned int hscif3_data_b_pins[] = { /* HRX3_B, HTX3_B */ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), @@ -1661,6 +1708,90 @@ static const unsigned int i2c3_mux[] = { SDA3_MARK, SCL3_MARK, }; +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_a_pins[] = { + /* IRQ0_A */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int intc_ex_irq0_a_mux[] = { + IRQ0_A_MARK, +}; +static const unsigned int intc_ex_irq0_b_pins[] = { + /* IRQ0_B */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int intc_ex_irq0_b_mux[] = { + IRQ0_B_MARK, +}; + +static const unsigned int intc_ex_irq1_a_pins[] = { + /* IRQ1_A */ + RCAR_GP_PIN(0, 5), +}; +static const unsigned int intc_ex_irq1_a_mux[] = { + IRQ1_A_MARK, +}; +static const unsigned int intc_ex_irq1_b_pins[] = { + /* IRQ1_B */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int intc_ex_irq1_b_mux[] = { + IRQ1_B_MARK, +}; + +static const unsigned int intc_ex_irq2_a_pins[] = { + /* IRQ2_A */ + RCAR_GP_PIN(0, 4), +}; +static const unsigned int intc_ex_irq2_a_mux[] = { + IRQ2_A_MARK, +}; +static const unsigned int intc_ex_irq2_b_pins[] = { + /* IRQ2_B */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int intc_ex_irq2_b_mux[] = { + IRQ2_B_MARK, +}; + +static const unsigned int intc_ex_irq3_a_pins[] = { + /* IRQ3_A */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int intc_ex_irq3_a_mux[] = { + IRQ3_A_MARK, +}; +static const unsigned int intc_ex_irq3_b_pins[] = { + /* IRQ3_B */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int intc_ex_irq3_b_mux[] = { + IRQ3_B_MARK, +}; + +static const unsigned int intc_ex_irq4_a_pins[] = { + /* IRQ4_A */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int intc_ex_irq4_a_mux[] = { + IRQ4_A_MARK, +}; +static const unsigned int intc_ex_irq4_b_pins[] = { + /* IRQ4_B */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int intc_ex_irq4_b_mux[] = { + IRQ4_B_MARK, +}; + +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { /* MMC_SD_D[0:3], MMC_D[4:7] */ @@ -1978,7 +2109,7 @@ static const unsigned int pcie0_clkreq_n_mux[] = { PCIE0_CLKREQ_N_MARK, }; -/* - PWM0_A ------------------------------------------------------------------- */ +/* - PWM0 --------------------------------------------------------------------- */ static const unsigned int pwm0_a_pins[] = { /* PWM0_A */ RCAR_GP_PIN(1, 15), @@ -1987,7 +2118,6 @@ static const unsigned int pwm0_a_mux[] = { PWM0_A_MARK, }; -/* - PWM0_B ------------------------------------------------------------------- */ static const unsigned int pwm0_b_pins[] = { /* PWM0_B */ RCAR_GP_PIN(1, 14), @@ -1996,7 +2126,7 @@ static const unsigned int pwm0_b_mux[] = { PWM0_B_MARK, }; -/* - PWM1_A ------------------------------------------------------------------- */ +/* - PWM1 --------------------------------------------------------------------- */ static const unsigned int pwm1_a_pins[] = { /* PWM1_A */ RCAR_GP_PIN(3, 13), @@ -2005,7 +2135,6 @@ static const unsigned int pwm1_a_mux[] = { PWM1_A_MARK, }; -/* - PWM1_B ------------------------------------------------------------------- */ static const unsigned int pwm1_b_pins[] = { /* PWM1_B */ RCAR_GP_PIN(2, 13), @@ -2014,7 +2143,6 @@ static const unsigned int pwm1_b_mux[] = { PWM1_B_MARK, }; -/* - PWM1_C ------------------------------------------------------------------- */ static const unsigned int pwm1_c_pins[] = { /* PWM1_C */ RCAR_GP_PIN(2, 17), @@ -2023,7 +2151,7 @@ static const unsigned int pwm1_c_mux[] = { PWM1_C_MARK, }; -/* - PWM2_A ------------------------------------------------------------------- */ +/* - PWM2 --------------------------------------------------------------------- */ static const unsigned int pwm2_a_pins[] = { /* PWM2_A */ RCAR_GP_PIN(3, 14), @@ -2032,7 +2160,6 @@ static const unsigned int pwm2_a_mux[] = { PWM2_A_MARK, }; -/* - PWM2_B ------------------------------------------------------------------- */ static const unsigned int pwm2_b_pins[] = { /* PWM2_B */ RCAR_GP_PIN(2, 14), @@ -2041,7 +2168,6 @@ static const unsigned int pwm2_b_mux[] = { PWM2_B_MARK, }; -/* - PWM2_C ------------------------------------------------------------------- */ static const unsigned int pwm2_c_pins[] = { /* PWM2_C */ RCAR_GP_PIN(2, 19), @@ -2050,7 +2176,7 @@ static const unsigned int pwm2_c_mux[] = { PWM2_C_MARK, }; -/* - PWM3_A ------------------------------------------------------------------- */ +/* - PWM3 --------------------------------------------------------------------- */ static const unsigned int pwm3_a_pins[] = { /* PWM3_A */ RCAR_GP_PIN(4, 14), @@ -2059,7 +2185,6 @@ static const unsigned int pwm3_a_mux[] = { PWM3_A_MARK, }; -/* - PWM3_B ------------------------------------------------------------------- */ static const unsigned int pwm3_b_pins[] = { /* PWM3_B */ RCAR_GP_PIN(2, 15), @@ -2068,7 +2193,6 @@ static const unsigned int pwm3_b_mux[] = { PWM3_B_MARK, }; -/* - PWM3_C ------------------------------------------------------------------- */ static const unsigned int pwm3_c_pins[] = { /* PWM3_C */ RCAR_GP_PIN(1, 22), @@ -2145,7 +2269,7 @@ static const unsigned int scif0_ctrl_mux[] = { RTS0_N_MARK, CTS0_N_MARK, }; -/* - SCIF1_A ------------------------------------------------------------------ */ +/* - SCIF1 -------------------------------------------------------------------- */ static const unsigned int scif1_data_a_pins[] = { /* RX1_A, TX1_A */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), @@ -2168,7 +2292,6 @@ static const unsigned int scif1_ctrl_a_mux[] = { RTS1_N_A_MARK, CTS1_N_A_MARK, }; -/* - SCIF1_B ------------------------------------------------------------------ */ static const unsigned int scif1_data_b_pins[] = { /* RX1_B, TX1_B */ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), @@ -2191,7 +2314,7 @@ static const unsigned int scif1_ctrl_b_mux[] = { RTS1_N_B_MARK, CTS1_N_B_MARK, }; -/* - SCIF3_A ------------------------------------------------------------------ */ +/* - SCIF3 -------------------------------------------------------------------- */ static const unsigned int scif3_data_a_pins[] = { /* RX3_A, TX3_A */ RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28), @@ -2214,7 +2337,6 @@ static const unsigned int scif3_ctrl_a_mux[] = { RTS3_N_A_MARK, CTS3_N_A_MARK, }; -/* - SCIF3_B ------------------------------------------------------------------ */ static const unsigned int scif3_data_b_pins[] = { /* RX3_B, TX3_B */ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), @@ -2293,7 +2415,7 @@ static const unsigned int ssi_ctrl_mux[] = { SSI_SCK_MARK, SSI_WS_MARK, }; -/* - TPU_A ------------------------------------------------------------------- */ +/* - TPU --------------------------------------------------------------------- */ static const unsigned int tpu_to0_a_pins[] = { /* TPU0TO0_A */ RCAR_GP_PIN(2, 8), @@ -2323,7 +2445,6 @@ static const unsigned int tpu_to3_a_mux[] = { TPU0TO3_A_MARK, }; -/* - TPU_B ------------------------------------------------------------------- */ static const unsigned int tpu_to0_b_pins[] = { /* TPU0TO0_B */ RCAR_GP_PIN(1, 25), @@ -2361,6 +2482,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb0_magic), SH_PFC_PIN_GROUP(avb0_phy_int), SH_PFC_PIN_GROUP(avb0_mdio), + SH_PFC_PIN_GROUP(avb0_mii), SH_PFC_PIN_GROUP(avb0_rgmii), SH_PFC_PIN_GROUP(avb0_txcrefclk), SH_PFC_PIN_GROUP(avb0_avtp_pps), @@ -2371,6 +2493,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb1_magic), SH_PFC_PIN_GROUP(avb1_phy_int), SH_PFC_PIN_GROUP(avb1_mdio), + SH_PFC_PIN_GROUP(avb1_mii), SH_PFC_PIN_GROUP(avb1_rgmii), SH_PFC_PIN_GROUP(avb1_txcrefclk), SH_PFC_PIN_GROUP(avb1_avtp_pps), @@ -2417,6 +2540,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c2), SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(intc_ex_irq0_a), + SH_PFC_PIN_GROUP(intc_ex_irq0_b), + SH_PFC_PIN_GROUP(intc_ex_irq1_a), + SH_PFC_PIN_GROUP(intc_ex_irq1_b), + SH_PFC_PIN_GROUP(intc_ex_irq2_a), + SH_PFC_PIN_GROUP(intc_ex_irq2_b), + SH_PFC_PIN_GROUP(intc_ex_irq3_a), + SH_PFC_PIN_GROUP(intc_ex_irq3_b), + SH_PFC_PIN_GROUP(intc_ex_irq4_a), + SH_PFC_PIN_GROUP(intc_ex_irq4_b), + SH_PFC_PIN_GROUP(intc_ex_irq5), + BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), @@ -2533,6 +2668,7 @@ static const char * const avb0_groups[] = { "avb0_magic", "avb0_phy_int", "avb0_mdio", + "avb0_mii", "avb0_rgmii", "avb0_txcrefclk", "avb0_avtp_pps", @@ -2545,6 +2681,7 @@ static const char * const avb1_groups[] = { "avb1_magic", "avb1_phy_int", "avb1_mdio", + "avb1_mii", "avb1_rgmii", "avb1_txcrefclk", "avb1_avtp_pps", @@ -2630,6 +2767,20 @@ static const char * const i2c3_groups[] = { "i2c3", }; +static const char * const intc_ex_groups[] = { + "intc_ex_irq0_a", + "intc_ex_irq0_b", + "intc_ex_irq1_a", + "intc_ex_irq1_b", + "intc_ex_irq2_a", + "intc_ex_irq2_b", + "intc_ex_irq3_a", + "intc_ex_irq3_b", + "intc_ex_irq4_a", + "intc_ex_irq4_b", + "intc_ex_irq5", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -2814,6 +2965,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index a4a12069b36..1503153ddc9 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # Core -obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE) += pinctrl-starfive.o +obj-$(CONFIG_$(PHASE_)PINCTRL_STARFIVE) += pinctrl-starfive.o # SoC Drivers -obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE_JH7110) += pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o +obj-$(CONFIG_$(PHASE_)PINCTRL_STARFIVE_JH7110) += pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile index 75d3cabc62b..b1dda417475 100644 --- a/drivers/pinctrl/tegra/Makefile +++ b/drivers/pinctrl/tegra/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifdef CONFIG_TEGRA20 obj-y += pinctrl-tegra20.o else diff --git a/drivers/pinctrl/tegra/funcmux-tegra30.c b/drivers/pinctrl/tegra/funcmux-tegra30.c index e31b859beb8..5d3403ae441 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra30.c +++ b/drivers/pinctrl/tegra/funcmux-tegra30.c @@ -33,6 +33,22 @@ int funcmux_select(enum periph_id id, int config) break; } break; + case PERIPH_ID_UART5: + switch (config) { + case FUNCMUX_UART5_SDMMC1: + pinmux_set_func(PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_FUNC_UARTE); + pinmux_set_func(PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_FUNC_UARTE); + + pinmux_set_io(PMUX_PINGRP_SDMMC1_DAT3_PY4, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_SDMMC1_DAT2_PY5, PMUX_PIN_INPUT); + + pinmux_tristate_disable(PMUX_PINGRP_SDMMC1_DAT3_PY4); + pinmux_tristate_disable(PMUX_PINGRP_SDMMC1_DAT2_PY5); + break; + } + break; /* Add other periph IDs here as needed */ diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 5951835d6e8..da7bb4f6377 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -126,7 +126,7 @@ struct uniphier_pinctrl_socdata { #define __UNIPHIER_PINMUX_FUNCTION(func) #func -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL, * suppressing "defined but not used" warnings. diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 6f7e6fb0a6b..3f4d56f5139 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -3,13 +3,13 @@ # Copyright (c) 2009 Wind River Systems, Inc. # Tom Rix <Tom.Rix at windriver.com> -obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/ -obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/ +obj-$(CONFIG_$(PHASE_)ACPI_PMC) += acpi_pmc/ +obj-$(CONFIG_$(PHASE_)POWER_DOMAIN) += domain/ obj-y += pmic/ obj-y += regulator/ obj-$(CONFIG_AXP221_POWER) += axp221.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_AXP305_POWER) += axp_spl.o @@ -23,9 +23,9 @@ obj-$(CONFIG_SY8106A_POWER) += sy8106a.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o obj-$(CONFIG_PALMAS_POWER) += palmas.o -obj-$(CONFIG_$(SPL_TPL_)POWER_LEGACY) += power_core.o +obj-$(CONFIG_$(PHASE_)POWER_LEGACY) += power_core.o obj-$(CONFIG_DIALOG_POWER) += power_dialog.o obj-$(CONFIG_POWER_FSL) += power_fsl.o -obj-$(CONFIG_$(SPL_TPL_)POWER_I2C) += power_i2c.o +obj-$(CONFIG_$(PHASE_)POWER_I2C) += power_i2c.o obj-$(CONFIG_POWER_SPI) += power_spi.o obj-$(CONFIG_POWER_MT6323) += mt6323.o diff --git a/drivers/power/acpi_pmc/Makefile b/drivers/power/acpi_pmc/Makefile index 0db52a65824..3259b397a9a 100644 --- a/drivers/power/acpi_pmc/Makefile +++ b/drivers/power/acpi_pmc/Makefile @@ -3,4 +3,4 @@ # Copyright 2019 Google LLC obj-y += acpi-pmc-uclass.o -obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC_SANDBOX) += sandbox.o pmc_emul.o +obj-$(CONFIG_$(PHASE_)ACPI_PMC_SANDBOX) += sandbox.o pmc_emul.o diff --git a/drivers/power/acpi_pmc/acpi-pmc-uclass.c b/drivers/power/acpi_pmc/acpi-pmc-uclass.c index c289cede15b..1e94104091e 100644 --- a/drivers/power/acpi_pmc/acpi-pmc-uclass.c +++ b/drivers/power/acpi_pmc/acpi-pmc-uclass.c @@ -60,7 +60,7 @@ int pmc_gpe_init(struct udevice *dev) * are different and if they aren't, use the reset values. */ if (dw[0] == dw[1] || dw[1] == dw[2]) { - if (spl_phase() > PHASE_TPL) + if (xpl_phase() > PHASE_TPL) log_info("PMC: Using default GPE route"); gpio_cfg = readl(upriv->gpe_cfg); for (i = 0; i < upriv->gpe0_count; i++) diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c index 9e38e1a7450..ec3eca1ac4b 100644 --- a/drivers/power/axp809.c +++ b/drivers/power/axp809.c @@ -93,7 +93,7 @@ int axp_set_dcdc4(unsigned int mvolt) return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1, AXP809_OUTPUT_CTRL1_DCDC4_EN); - ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg); + ret = pmic_bus_write(AXP809_DCDC4_CTRL, cfg); if (ret) return ret; diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 2daab73eb75..110646c503a 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2016, NVIDIA CORPORATION. # -obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o +obj-$(CONFIG_$(XPL_)POWER_DOMAIN) += power-domain-uclass.o obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c index 20e9f32b381..4d9f3bba644 100644 --- a/drivers/power/domain/meson-ee-pwrc.c +++ b/drivers/power/domain/meson-ee-pwrc.c @@ -60,6 +60,7 @@ struct meson_ee_pwrc_domain_desc { unsigned int mem_pd_count; struct meson_ee_pwrc_mem_domain *mem_pd; bool (*get_power)(struct power_domain *power_domain); + bool enabled; }; struct meson_ee_pwrc_domain_data { @@ -306,6 +307,8 @@ static int meson_ee_pwrc_off(struct power_domain *power_domain) clk_disable_bulk(&priv->clks); } + pwrc_domain->enabled = false; + return 0; } @@ -317,6 +320,9 @@ static int meson_ee_pwrc_on(struct power_domain *power_domain) pwrc_domain = &priv->data->domains[power_domain->id]; + if (pwrc_domain->enabled) + return 0; + if (pwrc_domain->top_pd) regmap_update_bits(priv->regmap_ao, pwrc_domain->top_pd->sleep_reg, @@ -347,8 +353,13 @@ static int meson_ee_pwrc_on(struct power_domain *power_domain) return ret; } - if (pwrc_domain->clk_names_count) - return clk_enable_bulk(&priv->clks); + if (pwrc_domain->clk_names_count) { + ret = clk_enable_bulk(&priv->clks); + if (ret) + return ret; + } + + pwrc_domain->enabled = true; return 0; } diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index a2d59deeed8..bc138f563ff 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -3,34 +3,34 @@ # Copyright (C) 2012 Samsung Electronics # Lukasz Majewski <l.majewski@samsung.com> -obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o -obj-$(CONFIG_$(SPL_)DM_PMIC_FAN53555) += fan53555.o -obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o -obj-$(CONFIG_$(SPL_)DM_PMIC_MAX77663) += max77663.o +obj-$(CONFIG_$(PHASE_)DM_PMIC) += pmic-uclass.o +obj-$(CONFIG_$(XPL_)DM_PMIC_FAN53555) += fan53555.o +obj-$(CONFIG_$(XPL_)DM_PMIC_DA9063) += da9063.o +obj-$(CONFIG_$(XPL_)DM_PMIC_MAX77663) += max77663.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o -obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o -obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o -obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o -obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o +obj-$(CONFIG_$(XPL_)DM_PMIC_BD71837) += bd71837.o +obj-$(CONFIG_$(XPL_)DM_PMIC_MP5416) += mp5416.o +obj-$(CONFIG_$(XPL_)DM_PMIC_PFUZE100) += pfuze100.o +obj-$(CONFIG_$(XPL_)DM_PMIC_PCA9450) += pca9450.o obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_AB8500) += ab8500.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o -obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o +obj-$(CONFIG_$(XPL_)PMIC_AXP) += axp.o obj-$(CONFIG_PMIC_MAX8997) += max8997.o obj-$(CONFIG_PMIC_QCOM) += pmic_qcom.o -obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o -obj-$(CONFIG_$(SPL_)PMIC_RN5T567) += rn5t567.o +obj-$(CONFIG_$(PHASE_)PMIC_RK8XX) += rk8xx.o +obj-$(CONFIG_$(XPL_)PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o -obj-$(CONFIG_$(SPL_)DM_PMIC_TPS80031) += tps80031.o -obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o -obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o -obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o +obj-$(CONFIG_$(XPL_)DM_PMIC_TPS80031) += tps80031.o +obj-$(CONFIG_$(XPL_)PMIC_PALMAS) += palmas.o +obj-$(CONFIG_$(XPL_)PMIC_LP873X) += lp873x.o +obj-$(CONFIG_$(XPL_)PMIC_LP87565) += lp87565.o obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o obj-$(CONFIG_PMIC_TPS65219) += tps65219.o @@ -38,7 +38,7 @@ obj-$(CONFIG_PMIC_TPS65941) += tps65941.o obj-$(CONFIG_PMIC_RAA215300) += raa215300.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o -ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) +ifeq ($(CONFIG_$(XPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o @@ -47,5 +47,5 @@ obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o endif -obj-$(CONFIG_$(SPL_)POWER_TPS62362) += pmic_tps62362.o +obj-$(CONFIG_$(XPL_)POWER_TPS62362) += pmic_tps62362.o obj-$(CONFIG_SPL_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 07af6273d8a..9d875f8bdbe 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -42,7 +42,7 @@ static int pca9450_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -53,7 +53,7 @@ static int pca9450_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -121,6 +121,7 @@ static const struct udevice_id pca9450_ids[] = { { .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, }, { .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, }, { .compatible = "nxp,pca9451a", .data = NXP_CHIP_TYPE_PCA9451A, }, + { .compatible = "nxp,pca9452", .data = NXP_CHIP_TYPE_PCA9452, }, { } }; diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 4d5a5ceafad..a14555cf472 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -237,7 +237,7 @@ static int rk8xx_bind(struct udevice *dev) if (!children) debug("%s: %s - no child found\n", __func__, dev->name); - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON)) dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); @@ -331,7 +331,7 @@ static int rk8xx_probe(struct udevice *dev) pmic_reg_read(dev, init_data[i].reg)); } - if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { printf("PMIC: RK%x ", show_variant); if (on_source && off_source) printf("(on=0x%02x, off=0x%02x)", diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c index c99a0c27b33..f0415fbd172 100644 --- a/drivers/power/pmic/stpmic1.c +++ b/drivers/power/pmic/stpmic1.c @@ -91,7 +91,7 @@ static int stpmic1_bind(struct udevice *dev) dev_dbg(dev, "no child found\n"); #endif /* DM_REGULATOR */ - if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { ret = device_bind_driver(dev, "stpmic1-nvm", "stpmic1-nvm", NULL); if (ret) @@ -124,7 +124,7 @@ U_BOOT_DRIVER(pmic_stpmic1) = { .ops = &stpmic1_ops, }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len, enum pmic_nvm_op op) { @@ -230,7 +230,7 @@ U_BOOT_DRIVER(stpmic1_nvm) = { .id = UCLASS_MISC, .ops = &stpmic1_nvm_ops, }; -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #ifdef CONFIG_SYSRESET static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type) diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c index 1caf9f09346..61b2fe5f54a 100644 --- a/drivers/power/power_core.c +++ b/drivers/power/power_core.c @@ -78,7 +78,7 @@ struct pmic *pmic_get(const char *s) return NULL; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int pmic_dump(struct pmic *p) { int i, ret; diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 54db0885657..ca6c89d13b5 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -4,41 +4,41 @@ # Przemyslaw Marczak <p.marczak@samsung.com> # -obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR) += regulator-uclass.o obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o -obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o -obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_MAX77663) += max77663_regulator.o +obj-$(CONFIG_$(XPL_)REGULATOR_AXP) += axp_regulator.o +obj-$(CONFIG_$(XPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_DA9063) += da9063.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_MAX77663) += max77663_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o -obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_PCA9450) += pca9450.o -obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o +obj-$(CONFIG_$(XPL_)DM_PMIC_PFUZE100) += pfuze100.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_BD71837) += bd71837.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_PCA9450) += pca9450.o +obj-$(CONFIG_$(XPL_)REGULATOR_PWM) += pwm_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_FAN53555) += fan53555.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_COMMON) += regulator_common.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_FIXED) += fixed.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_GPIO) += gpio-regulator.o obj-$(CONFIG_DM_REGULATOR_QCOM_RPMH) += qcom-rpmh-regulator.o -obj-$(CONFIG_$(SPL_TPL_)REGULATOR_RK8XX) += rk8xx.o +obj-$(CONFIG_$(PHASE_)REGULATOR_RK8XX) += rk8xx.o obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_STPMIC1) += stpmic1.o obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o -obj-$(CONFIG_$(SPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o +obj-$(CONFIG_$(XPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c index 9faf1eab5f9..a2a34244723 100644 --- a/drivers/power/regulator/pca9450.c +++ b/drivers/power/regulator/pca9450.c @@ -71,6 +71,10 @@ static struct pca9450_vrange pca9450_buck123_vranges[] = { PCA_RANGE(600000, 12500, 0, 0x7f), }; +static struct pca9450_vrange pca9450_trim_buck13_vranges[] = { + PCA_RANGE(650000, 12500, 0, 0x7f), +}; + static struct pca9450_vrange pca9450_buck456_vranges[] = { PCA_RANGE(600000, 25000, 0, 0x70), PCA_RANGE(3400000, 0, 0x71, 0x7f), @@ -105,12 +109,18 @@ static struct pca9450_plat pca9450_reg_data[] = { PCA_DATA("BUCK1", PCA9450_BUCK1CTRL, HW_STATE_CONTROL, PCA9450_BUCK1OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK, pca9450_buck123_vranges), + PCA_DATA("BUCK1_TRIM", PCA9450_BUCK1CTRL, HW_STATE_CONTROL, + PCA9450_BUCK1OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK, + pca9450_trim_buck13_vranges), PCA_DATA("BUCK2", PCA9450_BUCK2CTRL, HW_STATE_CONTROL, PCA9450_BUCK2OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK, pca9450_buck123_vranges), PCA_DATA("BUCK3", PCA9450_BUCK3CTRL, HW_STATE_CONTROL, PCA9450_BUCK3OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK, pca9450_buck123_vranges), + PCA_DATA("BUCK3_TRIM", PCA9450_BUCK3CTRL, HW_STATE_CONTROL, + PCA9450_BUCK3OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK, + pca9450_trim_buck13_vranges), /* Bucks 4-6 which do not support dynamic voltage scaling */ PCA_DATA("BUCK4", PCA9450_BUCK4CTRL, HW_STATE_CONTROL, PCA9450_BUCK4OUT, PCA9450_DVS_BUCK_RUN_MASK, @@ -271,20 +281,38 @@ static int pca9450_set_value(struct udevice *dev, int uvolt) static int pca9450_regulator_probe(struct udevice *dev) { struct pca9450_plat *plat = dev_get_plat(dev); - int i, type; + int i, type, ret; + unsigned int val; + bool pmic_trim = false; type = dev_get_driver_data(dev_get_parent(dev)); if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC && - type != NXP_CHIP_TYPE_PCA9451A) { + type != NXP_CHIP_TYPE_PCA9451A && type != NXP_CHIP_TYPE_PCA9452) { debug("Unknown PMIC type\n"); return -EINVAL; } + ret = pmic_reg_read(dev->parent, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if ((type == NXP_CHIP_TYPE_PCA9451A || type == NXP_CHIP_TYPE_PCA9452) && + (val & PCA9450_REG_PWRCTRL_TOFF_DEB)) + pmic_trim = true; + for (i = 0; i < ARRAY_SIZE(pca9450_reg_data); i++) { if (strcmp(dev->name, pca9450_reg_data[i].name)) continue; + if (pmic_trim && (!strcmp(pca9450_reg_data[i].name, "BUCK1") || + !strcmp(pca9450_reg_data[i].name, "BUCK3"))) { + *plat = pca9450_reg_data[i + 1]; + return 0; + } + /* PCA9450B/PCA9450C uses BUCK1 and BUCK3 in dual-phase */ if (type == NXP_CHIP_TYPE_PCA9450BC && !strcmp(pca9450_reg_data[i].name, "BUCK3")) { @@ -299,6 +327,12 @@ static int pca9450_regulator_probe(struct udevice *dev) continue; } + if (type == NXP_CHIP_TYPE_PCA9452 && + (!strcmp(pca9450_reg_data[i].name, "BUCK3") || + !strcmp(pca9450_reg_data[i].name, "LDO2"))) { + continue; + } + *plat = pca9450_reg_data[i]; return 0; diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index 375d06e3207..368675ebb9f 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -16,7 +16,7 @@ #include <power/pmic.h> #include <power/regulator.h> -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define ENABLE_DRIVER #endif diff --git a/drivers/power/sy8106a.c b/drivers/power/sy8106a.c index fb6028de71a..d9a2b6904b0 100644 --- a/drivers/power/sy8106a.c +++ b/drivers/power/sy8106a.c @@ -10,7 +10,7 @@ #define SY8106A_VOUT1_SEL 1 #define SY8106A_VOUT1_SEL_ENABLE (1 << 7) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static u8 sy8106a_mvolt_to_cfg(int mvolt, int min, int max, int div) { if (mvolt < min) diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index fdb2e78ec9e..f92e86eaa3f 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2015 Google, Inc # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -obj-$(CONFIG_$(SPL_TPL_)DM) += ram-uclass.o +obj-$(CONFIG_$(PHASE_)DM) += ram-uclass.o obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/ @@ -20,7 +20,7 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o obj-$(CONFIG_RAM_SIFIVE) += sifive/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/ endif diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c index c27c4593b9d..e9791697066 100644 --- a/drivers/ram/mediatek/ddr3-mt7629.c +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -233,7 +233,7 @@ struct mtk_ddr3_priv { struct clk mem_mux; }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static int mtk_ddr3_rank_size_detect(struct udevice *dev) { struct mtk_ddr3_priv *priv = dev_get_priv(dev); @@ -697,7 +697,7 @@ static int mtk_ddr3_probe(struct udevice *dev) if (priv->dramc_ao == FDT_ADDR_T_NONE) return -EINVAL; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int ret; ret = clk_get_by_index(dev, 0, &priv->phy); diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index 618bce5c9f4..ffff7d55f33 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -84,7 +84,7 @@ const int ddrconf_table[] = { #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void copy_to_reg(u32 *dest, const u32 *src, u32 n) { int i; @@ -851,7 +851,7 @@ static int rk3188_dmc_of_to_plat(struct udevice *dev) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #if CONFIG_IS_ENABLED(OF_PLATDATA) static int conv_of_plat(struct udevice *dev) @@ -878,7 +878,7 @@ static int conv_of_plat(struct udevice *dev) static int rk3188_dmc_probe(struct udevice *dev) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct rk3188_sdram_params *plat = dev_get_plat(dev); struct regmap *map; struct udevice *dev_clk; @@ -888,7 +888,7 @@ static int rk3188_dmc_probe(struct udevice *dev) priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = conv_of_plat(dev); if (ret) @@ -950,12 +950,12 @@ U_BOOT_DRIVER(rockchip_rk3188_dmc) = { .id = UCLASS_RAM, .of_match = rk3188_dmc_ids, .ops = &rk3188_dmc_ops, -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .of_to_plat = rk3188_dmc_of_to_plat, #endif .probe = rk3188_dmc_probe, .priv_auto = sizeof(struct dram_info), -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .plat_auto = sizeof(struct rk3188_sdram_params), #endif }; diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index c9f61e933e9..25ceab98ee9 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -84,7 +84,7 @@ const int ddrconf_table[] = { #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) static void copy_to_reg(u32 *dest, const u32 *src, u32 n) { int i; @@ -1013,7 +1013,7 @@ static int rk3288_dmc_of_to_plat(struct udevice *dev) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #if CONFIG_IS_ENABLED(OF_PLATDATA) static int conv_of_plat(struct udevice *dev) @@ -1041,7 +1041,7 @@ static int conv_of_plat(struct udevice *dev) static int rk3288_dmc_probe(struct udevice *dev) { #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) struct rk3288_sdram_params *plat = dev_get_plat(dev); struct udevice *dev_clk; struct regmap *map; @@ -1051,7 +1051,7 @@ static int rk3288_dmc_probe(struct udevice *dev) priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = conv_of_plat(dev); if (ret) @@ -1119,13 +1119,13 @@ U_BOOT_DRIVER(rockchip_rk3288_dmc) = { .of_match = rk3288_dmc_ids, .ops = &rk3288_dmc_ops, #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) .of_to_plat = rk3288_dmc_of_to_plat, #endif .probe = rk3288_dmc_probe, .priv_auto = sizeof(struct dram_info), #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) .plat_auto = sizeof(struct rk3288_sdram_params), #endif }; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 45270e27184..6fa8f268770 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -193,10 +193,10 @@ struct io_setting { */ static bool phase_sdram_init(void) { - return spl_phase() == PHASE_TPL || + return xpl_phase() == PHASE_TPL || (!IS_ENABLED(CONFIG_TPL) && !IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL) && - !spl_in_proper()); + !not_xpl()); } static struct io_setting * @@ -3196,7 +3196,7 @@ U_BOOT_DRIVER(dmc_rk3399) = { .probe = rk3399_dmc_probe, .priv_auto = sizeof(struct dram_info), #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) .plat_auto = sizeof(struct rockchip_dmc_plat), #endif }; diff --git a/drivers/ram/rockchip/sdram_rv1126.c b/drivers/ram/rockchip/sdram_rv1126.c index 4fbb088a8d9..b371f597d23 100644 --- a/drivers/ram/rockchip/sdram_rv1126.c +++ b/drivers/ram/rockchip/sdram_rv1126.c @@ -34,7 +34,7 @@ struct dram_info { #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) void __iomem *pctl; void __iomem *phy; struct rv1126_cru *cru; @@ -49,7 +49,7 @@ struct dram_info { }; #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) #define GRF_BASE_ADDR 0xfe000000 #define PMU_GRF_BASE_ADDR 0xfe020000 @@ -3507,7 +3507,7 @@ error: static int rv1126_dmc_probe(struct udevice *dev) { #if defined(CONFIG_TPL_BUILD) || \ - (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD)) if (rv1126_dmc_init(dev)) return 0; #else diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c index bd2f438d727..c555d2af2d0 100644 --- a/drivers/ram/sifive/sifive_ddr.c +++ b/drivers/ram/sifive/sifive_ddr.c @@ -91,7 +91,7 @@ struct sifive_ddr_info { u32 *physical_filter_ctrl; }; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) struct sifive_ddr_params { struct sifive_ddrctl pctl_regs; struct sifive_ddrphy phy_regs; @@ -337,7 +337,7 @@ static int sifive_ddr_probe(struct udevice *dev) priv->info.base = gd->ram_base; priv->info.size = gd->ram_size; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) int ret; u32 clock = 0; @@ -404,7 +404,7 @@ U_BOOT_DRIVER(sifive_ddr) = { .ops = &sifive_ddr_ops, .probe = sifive_ddr_probe, .priv_auto = sizeof(struct sifive_ddr_info), -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) .plat_auto = sizeof(struct sifive_dmc_plat), #endif }; diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile index 1df42c377bd..f1567b04b4c 100644 --- a/drivers/ram/starfive/Makefile +++ b/drivers/ram/starfive/Makefile @@ -2,10 +2,10 @@ # # Copyright (c) 2022 StarFive, Inc # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o -endif
\ No newline at end of file +endif diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index debc458c0e2..e9cd6229ec4 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -371,7 +371,7 @@ static int stm32mp1_ddr_probe(struct udevice *dev) priv->info.base = STM32_DDR_BASE; - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { priv->info.size = 0; ret = stm32mp1_ddr_setup(dev); diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index e09ed1aa4d4..801b0965e4f 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -4,7 +4,7 @@ # Texas Instruments Incorporated - https://www.ti.com/ # -obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o +obj-$(CONFIG_$(XPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o # Remote proc drivers - Please keep this list alphabetically sorted. obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 2eb639e4a65..d99a78c9828 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -32,4 +32,4 @@ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o obj-$(CONFIG_RESET_DRA7) += reset-dra7.o obj-$(CONFIG_RESET_AT91) += reset-at91.o -obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o +obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 866437fd24f..76d108080d9 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -46,7 +46,7 @@ struct socfpga_reset_data { */ static bool socfpga_reset_keep_enabled(void) { -#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT) +#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT) const char *env_str; long val; diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile index 30553c9d6e9..30c58272d41 100644 --- a/drivers/rng/Makefile +++ b/drivers/rng/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2019, Linaro Limited # -obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng-uclass.o +obj-$(CONFIG_$(PHASE_)DM_RNG) += rng-uclass.o obj-$(CONFIG_RNG_MESON) += meson-rng.o obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o obj-$(CONFIG_RNG_MSM) += msm_rng.o diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 03a424c31a5..99b5a2a346a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. #ccflags-y += -DDEBUG -obj-$(CONFIG_$(SPL_TPL_)DM_RTC) += rtc-uclass.o +obj-$(CONFIG_$(PHASE_)DM_RTC) += rtc-uclass.o obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o @@ -17,7 +17,7 @@ obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o obj-$(CONFIG_RTC_GOLDFISH) += goldfish_rtc.o obj-$(CONFIG_RTC_HT1380) += ht1380.o -obj-$(CONFIG_$(SPL_TPL_)RTC_SANDBOX) += i2c_rtc_emul.o +obj-$(CONFIG_$(PHASE_)RTC_SANDBOX) += i2c_rtc_emul.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o obj-$(CONFIG_RTC_M41T62) += m41t62.o obj-$(CONFIG_RTC_MAX313XX) += max313xx.o @@ -37,6 +37,6 @@ obj-$(CONFIG_RTC_RX8025) += rx8025.o obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o obj-$(CONFIG_RTC_S35392A) += s35392a.o obj-$(CONFIG_RTC_STM32) += stm32_rtc.o -obj-$(CONFIG_$(SPL_TPL_)RTC_SANDBOX) += sandbox_rtc.o +obj-$(CONFIG_$(PHASE_)RTC_SANDBOX) += sandbox_rtc.o obj-$(CONFIG_RTC_ABX80X) += abx80x.o obj-$(CONFIG_RTC_ZYNQMP) += zynqmp_rtc.o diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index 628be4c89fb..b76de1b22a8 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -3,16 +3,16 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o ifdef CONFIG_SCSI -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += scsi_bootdev.o +obj-$(CONFIG_$(PHASE_)BOOTSTD) += scsi_bootdev.o obj-$(CONFIG_SANDBOX) += sandbox_scsi.o obj-$(CONFIG_SANDBOX) += scsi_emul.o endif endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_SATA obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 78810f98367..ebe692a9963 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2006-2009 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifeq ($(CONFIG_$(SPL_TPL_)DM_SERIAL),y) +ifeq ($(CONFIG_$(PHASE_)DM_SERIAL),y) obj-y += serial-uclass.o else obj-y += serial.o @@ -11,7 +11,7 @@ endif obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o -obj-$(CONFIG_$(SPL_)SYS_NS16550_SERIAL) += serial_ns16550.o +obj-$(CONFIG_$(XPL_)SYS_NS16550_SERIAL) += serial_ns16550.o obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o @@ -63,7 +63,7 @@ obj-$(CONFIG_XEN_SERIAL) += serial_xen.o obj-$(CONFIG_XTENSA_SEMIHOSTING_SERIAL) += serial_xtensa_semihosting.o obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o endif obj-$(CONFIG_UART4_SERIAL) += serial_adi_uart4.o diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 7e45a80969e..0b35582aaa4 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,7 +218,7 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, }; -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK) +#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_SPL_CLK) static int atmel_serial_enable_clk(struct udevice *dev) { struct atmel_serial_priv *priv = dev_get_priv(dev); diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 07f9ac00e11..3f6860f3916 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -227,7 +227,7 @@ static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor) void ns16550_init(struct ns16550 *com_port, int baud_divisor) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_OMAP34XX) /* * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode * before SPL starts only THRE bit is set. We have to empty the @@ -303,7 +303,7 @@ void ns16550_putc(struct ns16550 *com_port, char c) char ns16550_getc(struct ns16550 *com_port) { while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_TTY) extern void usbtty_poll(void); usbtty_poll(); #endif @@ -473,7 +473,7 @@ static int ns16550_serial_getinfo(struct udevice *dev, struct ns16550_plat *plat = com_port->plat; /* save code size */ - if (!spl_in_proper()) + if (!not_xpl()) return -ENOSYS; info->type = SERIAL_CHIP_16550_COMPATIBLE; @@ -555,7 +555,7 @@ int ns16550_serial_of_to_plat(struct udevice *dev) struct clk clk; int err; - addr = spl_in_proper() ? dev_read_addr_size(dev, &size) : + addr = not_xpl() ? dev_read_addr_size(dev, &size) : dev_read_addr(dev); err = ns16550_serial_assign_base(plat, addr, size); if (err && !device_is_on_pci_bus(dev)) diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 84f02f7ac76..9feaa1eceec 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -101,7 +101,7 @@ static void serial_find_console_or_panic(void) } } } - if (!IS_ENABLED(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(OF_CONTROL) || + if (!IS_ENABLED(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) { /* * Try to use CONFIG_CONS_INDEX if available (it is numbered diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index dc4bb06fa99..e10ca6eef76 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -315,7 +315,7 @@ static struct serial_device *get_current(void) /* We must have a console device */ if (!dev) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD puts("Cannot find console\n"); hang(); #else diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 801b7645afa..734780a124a 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -117,7 +117,7 @@ static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, u8 reg_width, writeb(val % 16, &uart->rest.value); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int s5p_serial_setbrg(struct udevice *dev, int baudrate) { struct s5p_serial_plat *plat = dev_get_plat(dev); diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 55f13c00ddf..b74712f3eeb 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -152,7 +152,7 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate) return 0; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) static int zynq_serial_setconfig(struct udevice *dev, uint serial_config) { struct zynq_uart_plat *plat = dev_get_plat(dev); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index cd785aefd56..fa817ec4883 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -20,6 +20,12 @@ menuconfig SPI if SPI +config SPI_ADVANCE + bool "Enable the advance feature" + help + Enable the SPI advance feature support. By default this is disabled. + If you intend to use the advance feature support you should enable. + config DM_SPI bool "Enable Driver Model for SPI drivers" depends on DM @@ -93,6 +99,7 @@ config ATMEL_QSPI config ATMEL_SPI bool "Atmel SPI driver" + depends on ARCH_AT91 default y if ARCH_AT91 help This enables driver for the Atmel SPI Controller, present on @@ -126,6 +133,7 @@ config BCM63XX_SPI config BCMSTB_SPI bool "BCMSTB SPI driver" + depends on ARCH_BCMSTB help Enable the Broadcom set-top box SPI driver. This driver can be used to access the SPI flash on platforms embedding this @@ -164,6 +172,7 @@ config CADENCE_OSPI_VERSAL config CF_SPI bool "ColdFire SPI driver" + depends on M68K help Enable the ColdFire SPI driver. This driver can be used on some m68k SoCs. @@ -191,6 +200,7 @@ config DESIGNWARE_SPI config EXYNOS_SPI bool "Samsung Exynos SPI driver" + depends on ARCH_EXYNOS help Enable the Samsung Exynos SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Samsung @@ -198,6 +208,7 @@ config EXYNOS_SPI config FSL_DSPI bool "Freescale DSPI driver" + depends on FSL_LAYERSCAPE || ARCH_VF610 || ARCH_LS1021A || ARCH_LS1028A help Enable the Freescale DSPI driver. This driver can be used to access the SPI NOR flash and SPI Data flash on platforms embedding @@ -228,6 +239,7 @@ config GXP_SPI config ICH_SPI bool "Intel ICH SPI driver" + depends on X86 help Enable the Intel ICH SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Intel @@ -241,6 +253,7 @@ config IPROC_QSPI config KIRKWOOD_SPI bool "Marvell Kirkwood SPI Driver" + depends on ARCH_KIRKWOOD || ARCH_MVEBU help Enable support for SPI on various Marvell SoCs, such as Kirkwood and Armada 375. @@ -276,6 +289,7 @@ config MPC8XX_SPI config MPC8XXX_SPI bool "MPC8XXX SPI Driver" + depends on MPC83xx || MPC85xx help Enable support for SPI on the MPC8XXX PowerPC SoCs. @@ -335,6 +349,7 @@ config MVEBU_A3700_SPI config MXS_SPI bool "MXS SPI Driver" + depends on MACH_IMX help Enable the MXS SPI controller driver. This driver can be used on the i.MX23 and i.MX28 SoCs. @@ -416,6 +431,7 @@ config RENESAS_RPC_SPI config ROCKCHIP_SFC bool "Rockchip SFC Driver" + select BOUNCE_BUFFER help Enable the Rockchip SFC Driver for SPI NOR flash. This device is a limited purpose SPI controller for driving NOR flash on certain @@ -520,6 +536,7 @@ config STM32_SPI config TEGRA114_SPI bool "nVidia Tegra114 SPI driver" + depends on ARCH_TEGRA help Enable the nVidia Tegra114 SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this nVidia Tegra114 @@ -530,6 +547,7 @@ config TEGRA114_SPI config TEGRA20_SFLASH bool "nVidia Tegra20 Serial Flash controller driver" + depends on ARCH_TEGRA help Enable the nVidia Tegra20 Serial Flash controller driver. This driver can be used to access the SPI NOR flash on platforms embedding this @@ -537,6 +555,7 @@ config TEGRA20_SFLASH config TEGRA20_SLINK bool "nVidia Tegra20/Tegra30 SLINK driver" + depends on ARCH_TEGRA help Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can be used to access the SPI NOR flash on platforms embedding this @@ -544,6 +563,7 @@ config TEGRA20_SLINK config TEGRA210_QSPI bool "nVidia Tegra210 QSPI driver" + depends on ARCH_TEGRA help Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver be used to access SPI chips on platforms embedding this @@ -552,6 +572,7 @@ config TEGRA210_QSPI config TI_QSPI bool "TI QSPI driver" imply TI_EDMA3 + depends on ARCH_OMAP2PLUS help Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. This driver support spi flash single, quad and memory reads. @@ -607,12 +628,14 @@ config FSL_ESPI config SH_QSPI bool "Renesas Quad SPI driver" + depends on ARCH_RENESAS help Enable the Renesas Quad SPI controller driver. This driver can be used on Renesas SoCs. config MXC_SPI bool "MXC SPI Driver" + depends on MACH_IMX help Enable the MXC SPI controller driver. This driver can be used on various i.MX SoCs such as i.MX31/35/51/6/7. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 32d7bf7237a..7051e2a00c6 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # There are many options which enable SPI, so make this library available -ifdef CONFIG_$(SPL_TPL_)DM_SPI +ifdef CONFIG_$(PHASE_)DM_SPI obj-y += spi-uclass.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CADENCE_OSPI_VERSAL) += cadence_ospi_versal.o diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 8e227d187b0..dafaf1130bb 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -95,7 +95,7 @@ static int altera_spi_xfer(struct udevice *dev, unsigned int bitlen, uint32_t reg, data, start; debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, - dev_seq(bus), slave_plat->cs, bitlen, bytes, flags); + dev_seq(bus), slave_plat->cs[0], bitlen, bytes, flags); if (bitlen == 0) goto done; @@ -110,7 +110,7 @@ static int altera_spi_xfer(struct udevice *dev, unsigned int bitlen, readl(®s->rxdata); if (flags & SPI_XFER_BEGIN) - spi_cs_activate(dev, slave_plat->cs); + spi_cs_activate(dev, slave_plat->cs[0]); while (bytes--) { if (txp) diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index 2178534baf0..72b612c6560 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -319,7 +319,7 @@ static int atcspi200_spi_claim_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct nds_spi_slave *ns = dev_get_priv(bus); - if (slave_plat->cs >= ns->num_cs) { + if (slave_plat->cs[0] >= ns->num_cs) { printf("Invalid SPI chipselect\n"); return -EINVAL; } diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c index fb2d77d7d4a..b0ed14f0cfc 100644 --- a/drivers/spi/ath79_spi.c +++ b/drivers/spi/ath79_spi.c @@ -73,7 +73,7 @@ static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen, if (restbits) bytes++; - out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs[0])); while (bytes > 0) { bytes--; curbyte = 0; diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 79f01001318..aaf3eddae42 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -125,7 +125,7 @@ static int atmel_spi_claim_bus(struct udevice *dev) struct atmel_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); struct at91_spi *reg_base = bus_plat->regs; - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; u32 freq = priv->freq; u32 scbr, csrx, mode; @@ -174,7 +174,7 @@ static void atmel_spi_cs_activate(struct udevice *dev) struct udevice *bus = dev_get_parent(dev); struct atmel_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) return; @@ -189,7 +189,7 @@ static void atmel_spi_cs_deactivate(struct udevice *dev) struct udevice *bus = dev_get_parent(dev); struct atmel_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) return; diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 1aa43fd3a23..e9f0b343abb 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -174,7 +174,7 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, set = DIV_ROUND_UP(2048, set); set &= SPI_PFL_CLK_FREQ_MASK; set |= SPI_PFL_CLK_RSTLOOP_MASK; - writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); + writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs[0])); /* profile signal */ set = 0; @@ -192,29 +192,29 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, if (speed > SPI_MAX_SYNC_CLOCK) set |= SPI_PFL_SIG_ASYNCIN_MASK; - clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); + clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs[0]), clr, set); /* global control */ set = 0; clr = 0; if (priv->xfer_mode == HSSPI_XFER_MODE_PREPEND) { - if (priv->cs_pols & BIT(plat->cs)) - set |= BIT(plat->cs); + if (priv->cs_pols & BIT(plat->cs[0])) + set |= BIT(plat->cs[0]); else - clr |= BIT(plat->cs); + clr |= BIT(plat->cs[0]); } else { /* invert cs polarity */ - if (priv->cs_pols & BIT(plat->cs)) - clr |= BIT(plat->cs); + if (priv->cs_pols & BIT(plat->cs[0])) + clr |= BIT(plat->cs[0]); else - set |= BIT(plat->cs); + set |= BIT(plat->cs[0]); /* invert dummy cs polarity */ - if (priv->cs_pols & BIT(!plat->cs)) - clr |= BIT(!plat->cs); + if (priv->cs_pols & BIT(!plat->cs[0])) + clr |= BIT(!plat->cs[0]); else - set |= BIT(!plat->cs); + set |= BIT(!plat->cs[0]); } clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); @@ -290,7 +290,7 @@ static int bcm63xx_hsspi_xfer_dummy_cs(struct udevice *dev, unsigned int data_by if (plat->mode & SPI_3WIRE) val |= SPI_PFL_MODE_3WIRE_MASK; - writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs[0])); /* transfer loop */ while (data_bytes > 0) { @@ -310,9 +310,9 @@ static int bcm63xx_hsspi_xfer_dummy_cs(struct udevice *dev, unsigned int data_by /* issue the transfer */ val = SPI_CMD_OP_START; - val |= (plat->cs << SPI_CMD_PFL_SHIFT) & + val |= (plat->cs[0] << SPI_CMD_PFL_SHIFT) & SPI_CMD_PFL_MASK; - val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) & + val |= (!plat->cs[0] << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK; writel(val, priv->regs + SPI_CMD_REG); @@ -450,7 +450,7 @@ static int bcm63xx_hsspi_xfer_prepend(struct udevice *dev, unsigned int data_byt } } val |= (priv->prepend_cnt << SPI_PFL_MODE_PREPCNT_SHIFT); - writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs[0])); /* set fifo operation */ val = opcode | (data_bytes & HSSPI_FIFO_OP_BYTES_MASK); @@ -459,9 +459,9 @@ static int bcm63xx_hsspi_xfer_prepend(struct udevice *dev, unsigned int data_byt /* issue the transfer */ val = SPI_CMD_OP_START; - val |= (plat->cs << SPI_CMD_PFL_SHIFT) & + val |= (plat->cs[0] << SPI_CMD_PFL_SHIFT) & SPI_CMD_PFL_MASK; - val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & + val |= (plat->cs[0] << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK; writel(val, priv->regs + SPI_CMD_REG); @@ -537,16 +537,16 @@ static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev) struct spi_slave *slave = dev_get_parent_priv(dev); /* check cs */ - if (plat->cs >= priv->num_cs) { - printf("no cs %u\n", plat->cs); + if (plat->cs[0] >= priv->num_cs) { + printf("no cs %u\n", plat->cs[0]); return -ENODEV; } /* cs polarity */ if (plat->mode & SPI_CS_HIGH) - priv->cs_pols |= BIT(plat->cs); + priv->cs_pols |= BIT(plat->cs[0]); else - priv->cs_pols &= ~BIT(plat->cs); + priv->cs_pols &= ~BIT(plat->cs[0]); /* * set the max read/write size to make sure each xfer are within the diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c index 595b41c8ab8..e02ec7e8bd7 100644 --- a/drivers/spi/bcm63xx_spi.c +++ b/drivers/spi/bcm63xx_spi.c @@ -275,7 +275,7 @@ static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen, /* issue the transfer */ cmd = SPI_CMD_OP_START; - cmd |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK; + cmd |= (plat->cs[0] << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK; cmd |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT); if (plat->mode & SPI_3WIRE) cmd |= SPI_CMD_3WIRE_MASK; @@ -353,8 +353,8 @@ static int bcm63xx_spi_child_pre_probe(struct udevice *dev) struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); /* check cs */ - if (plat->cs >= priv->num_cs) { - printf("no cs %u\n", plat->cs); + if (plat->cs[0] >= priv->num_cs) { + printf("no cs %u\n", plat->cs[0]); return -ENODEV; } diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c index eff9e1117d3..209ca713279 100644 --- a/drivers/spi/bcmbca_hsspi.c +++ b/drivers/spi/bcmbca_hsspi.c @@ -155,7 +155,7 @@ static void bcmbca_hsspi_setup_clock(struct bcmbca_hsspi_priv *priv, set = DIV_ROUND_UP(2048, set); set &= SPI_PFL_CLK_FREQ_MASK; set |= SPI_PFL_CLK_RSTLOOP_MASK; - writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); + writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs[0])); /* profile signal */ set = 0; @@ -173,16 +173,16 @@ static void bcmbca_hsspi_setup_clock(struct bcmbca_hsspi_priv *priv, if (priv->speed > SPI_MAX_SYNC_CLOCK) set |= SPI_PFL_SIG_ASYNCIN_MASK; - clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); + clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs[0]), clr, set); /* global control */ set = 0; clr = 0; - if (priv->cs_pols & BIT(plat->cs)) - set |= BIT(plat->cs); + if (priv->cs_pols & BIT(plat->cs[0])) + set |= BIT(plat->cs[0]); else - clr |= BIT(plat->cs); + clr |= BIT(plat->cs[0]); clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); } @@ -194,7 +194,7 @@ static void bcmbca_hsspi_activate_cs(struct bcmbca_hsspi_priv *priv, /* set the override bit */ val = readl(priv->spim_ctrl); - val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); + val |= BIT(plat->cs[0] + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); writel(val, priv->spim_ctrl); } @@ -205,7 +205,7 @@ static void bcmbca_hsspi_deactivate_cs(struct bcmbca_hsspi_priv *priv, /* clear the cs override bit */ val = readl(priv->spim_ctrl); - val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); + val &= ~BIT(plat->cs[0] + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); writel(val, priv->spim_ctrl); } @@ -250,7 +250,7 @@ static int bcmbca_hsspi_xfer(struct udevice *dev, unsigned int bitlen, if (plat->mode & SPI_3WIRE) val |= SPI_PFL_MODE_3WIRE_MASK; - writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs[0])); /* transfer loop */ while (data_bytes > 0) { @@ -276,9 +276,9 @@ static int bcmbca_hsspi_xfer(struct udevice *dev, unsigned int bitlen, /* issue the transfer */ val = SPI_CMD_OP_START; - val |= (plat->cs << SPI_CMD_PFL_SHIFT) & + val |= (plat->cs[0] << SPI_CMD_PFL_SHIFT) & SPI_CMD_PFL_MASK; - val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & + val |= (plat->cs[0] << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK; writel(val, priv->regs + SPI_CMD_REG); @@ -326,22 +326,22 @@ static int bcmbca_hsspi_child_pre_probe(struct udevice *dev) u32 val; /* check cs */ - if (plat->cs >= priv->num_cs) { - dev_err(dev, "no cs %u\n", plat->cs); + if (plat->cs[0] >= priv->num_cs) { + dev_err(dev, "no cs %u\n", plat->cs[0]); return -EINVAL; } /* cs polarity */ if (plat->mode & SPI_CS_HIGH) - priv->cs_pols |= BIT(plat->cs); + priv->cs_pols |= BIT(plat->cs[0]); else - priv->cs_pols &= ~BIT(plat->cs); + priv->cs_pols &= ~BIT(plat->cs[0]); /* set the polarity to spim cs register */ val = readl(priv->spim_ctrl); - val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); - if (priv->cs_pols & BIT(plat->cs)) - val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); + val &= ~BIT(plat->cs[0] + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); + if (priv->cs_pols & BIT(plat->cs[0])) + val |= BIT(plat->cs[0] + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); writel(val, priv->spim_ctrl); return 0; diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c index a99a8a4485a..db32e39add2 100644 --- a/drivers/spi/ca_sflash.c +++ b/drivers/spi/ca_sflash.c @@ -10,6 +10,7 @@ #include <malloc.h> #include <clk.h> #include <dm.h> +#include <dm/device_compat.h> #include <errno.h> #include <fdtdec.h> #include <linux/compat.h> diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 8234468b1d4..84077c01d83 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -123,7 +123,7 @@ static int coldfire_spi_claim_bus(struct udevice *dev) /* Clear FIFO and resume transfer */ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); - dspi_chip_select(slave_plat->cs); + dspi_chip_select(slave_plat->cs[0]); return 0; } @@ -139,7 +139,7 @@ static int coldfire_spi_release_bus(struct udevice *dev) /* Clear FIFO */ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); - dspi_chip_unselect(slave_plat->cs); + dspi_chip_unselect(slave_plat->cs[0]); return 0; } @@ -168,7 +168,7 @@ static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen, if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) ctrl |= DSPI_TFR_CONT; - ctrl = setup_ctrl(ctrl, slave_plat->cs); + ctrl = setup_ctrl(ctrl, slave_plat->cs[0]); if (len > 1) { int tmp_len = len - 1; diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 19bd06cf872..eeac1339c23 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -329,13 +329,13 @@ static int davinci_spi_claim_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct davinci_spi_slave *ds = dev_get_priv(bus); - if (slave_plat->cs >= ds->num_cs) { + if (slave_plat->cs[0] >= ds->num_cs) { printf("Invalid SPI chipselect\n"); return -EINVAL; } ds->half_duplex = slave_plat->mode & SPI_PREAMBLE; - return __davinci_spi_claim_bus(ds, slave_plat->cs); + return __davinci_spi_claim_bus(ds, slave_plat->cs[0]); } static int davinci_spi_release_bus(struct udevice *dev) @@ -354,11 +354,11 @@ static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen, struct udevice *bus = dev->parent; struct davinci_spi_slave *ds = dev_get_priv(bus); - if (slave->cs >= ds->num_cs) { + if (slave->cs[0] >= ds->num_cs) { printf("Invalid SPI chipselect\n"); return -EINVAL; } - ds->cur_cs = slave->cs; + ds->cur_cs = slave->cs[0]; return __davinci_spi_xfer(ds, bitlen, dout, din, flags); } diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 6bd48b1b373..b520c727900 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -219,7 +219,7 @@ static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv) static int request_gpio_cs(struct udevice *bus) { -#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD) +#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_XPL_BUILD) struct dw_spi_priv *priv = dev_get_priv(bus); int ret; @@ -482,7 +482,7 @@ static int poll_transfer(struct dw_spi_priv *priv) */ __weak void external_cs_manage(struct udevice *dev, bool on) { -#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD) +#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_XPL_BUILD) struct dw_spi_priv *priv = dev_get_priv(dev->parent); if (!dm_gpio_is_valid(&priv->cs_gpio)) diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 1d4d90ce5aa..f2393c041f4 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -452,9 +452,9 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev) unsigned char pcssck = 0, cssck = 0; unsigned char pasc = 0, asc = 0; - if (slave_plat->cs >= priv->num_chipselect) { + if (slave_plat->cs[0] >= priv->num_chipselect) { debug("DSPI invalid chipselect number %d(max %d)!\n", - slave_plat->cs, priv->num_chipselect - 1); + slave_plat->cs[0], priv->num_chipselect - 1); return -EINVAL; } @@ -469,12 +469,12 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev) /* Set After SCK delay scale values */ ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk); - priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE | + priv->ctar_val[slave_plat->cs[0]] = DSPI_CTAR_DEFAULT_VALUE | DSPI_CTAR_PCSSCK(pcssck) | DSPI_CTAR_PASC(pasc); debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n", - slave_plat->cs, slave_plat->max_hz, slave_plat->mode); + slave_plat->cs[0], slave_plat->max_hz, slave_plat->mode); return 0; } @@ -527,13 +527,13 @@ static int fsl_dspi_claim_bus(struct udevice *dev) priv = dev_get_priv(bus); /* processor special preparation work */ - cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs); + cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs[0]); /* configure transfer mode */ - fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode); + fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs[0], priv->mode); /* configure active state of CSX */ - fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs, + fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs[0], priv->mode); fsl_dspi_clr_fifo(priv); @@ -559,7 +559,7 @@ static int fsl_dspi_release_bus(struct udevice *dev) dspi_halt(priv, 1); /* processor special release work */ - cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs); + cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs[0]); return 0; } @@ -615,7 +615,7 @@ static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen, bus = dev->parent; priv = dev_get_priv(bus); - return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags); + return dspi_xfer(priv, slave_plat->cs[0], bitlen, dout, din, flags); } static int fsl_dspi_set_speed(struct udevice *bus, uint speed) diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 2638ed25200..7ed35aa3e66 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -513,8 +513,8 @@ static int fsl_espi_child_pre_probe(struct udevice *dev) struct udevice *bus = dev->parent; struct fsl_spi_slave *fsl = dev_get_priv(bus); - debug("%s cs %u\n", __func__, slave_plat->cs); - fsl->cs = slave_plat->cs; + debug("%s cs %u\n", __func__, slave_plat->cs[0]); + fsl->cs = slave_plat->cs[0]; return 0; } diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 8a0a53cb372..c7f554826c3 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -510,10 +510,10 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave) struct dm_spi_slave_plat *plat = dev_get_parent_plat(slave->dev); - if (q->selected == plat->cs) + if (q->selected == plat->cs[0]) return; - q->selected = plat->cs; + q->selected = plat->cs[0]; fsl_qspi_invalidate(q); } diff --git a/drivers/spi/gxp_spi.c b/drivers/spi/gxp_spi.c index 70d76ac66ad..3ee369c5a03 100644 --- a/drivers/spi/gxp_spi.c +++ b/drivers/spi/gxp_spi.c @@ -87,7 +87,7 @@ static int gxp_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *do value = readl(priv->base + OFFSET_SPIMCFG); value &= ~(1 << 24); /* set chipselect */ - value |= (slave_plat->cs << 24); + value |= (slave_plat->cs[0] << 24); /* addr reg and addr size */ if (len >= 4) { diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index e48ca65fe72..2264ca83d66 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -779,7 +779,7 @@ static int ich_init_controller(struct udevice *dev, struct ich_spi_plat *plat, struct ich_spi_priv *ctlr) { - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { struct ich_spi_plat *plat = dev_get_plat(dev); int ret; @@ -867,7 +867,7 @@ static int ich_spi_probe(struct udevice *dev) if (ret) return ret; - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { /* Cache the BIOS to speed things up */ ret = ich_cache_bios_region(dev); if (ret) diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index 7e72fb9e23d..51cc487271d 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -148,7 +148,7 @@ static void mpc8xx_spi_cs_activate(struct udevice *dev) struct mpc8xx_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev); - dm_gpio_set_value(&priv->gpios[platdata->cs], 1); + dm_gpio_set_value(&priv->gpios[platdata->cs[0]], 1); } static void mpc8xx_spi_cs_deactivate(struct udevice *dev) @@ -156,7 +156,7 @@ static void mpc8xx_spi_cs_deactivate(struct udevice *dev) struct mpc8xx_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev); - dm_gpio_set_value(&priv->gpios[platdata->cs], 0); + dm_gpio_set_value(&priv->gpios[platdata->cs[0]], 0); } static int mpc8xx_spi_xfer_one(struct udevice *dev, size_t count, diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index cd624f4d6f0..b34e1c2129c 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -113,7 +113,7 @@ static void mpc8xxx_spi_cs_activate(struct udevice *dev) struct mpc8xxx_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); - dm_gpio_set_value(&priv->gpios[plat->cs], 1); + dm_gpio_set_value(&priv->gpios[plat->cs[0]], 1); } static void mpc8xxx_spi_cs_deactivate(struct udevice *dev) @@ -121,7 +121,7 @@ static void mpc8xxx_spi_cs_deactivate(struct udevice *dev) struct mpc8xxx_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); - dm_gpio_set_value(&priv->gpios[plat->cs], 0); + dm_gpio_set_value(&priv->gpios[plat->cs[0]], 0); } static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, @@ -137,10 +137,10 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, ulong type = dev_get_driver_data(bus); debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__, - bus->name, plat->cs, (uint)dout, (uint)din, bitlen); - if (plat->cs >= priv->cs_count) { + bus->name, plat->cs[0], (uint)dout, (uint)din, bitlen); + if (plat->cs[0] >= priv->cs_count) { dev_err(dev, "chip select index %d too large (cs_count=%d)\n", - plat->cs, priv->cs_count); + plat->cs[0], priv->cs_count); return -EINVAL; } if (bitlen % 8) { diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c index ad4daeba3cd..75ab4ab1dda 100644 --- a/drivers/spi/mscc_bb_spi.c +++ b/drivers/spi/mscc_bb_spi.c @@ -123,11 +123,11 @@ int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen, u8 *rxd = din; debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n", - dev->parent->name, dev->name, plat->cs, plat->mode, dout, + dev->parent->name, dev->name, plat->cs[0], plat->mode, dout, din, bitlen); if (flags & SPI_XFER_BEGIN) - mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs); + mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs[0]); count = bitlen / 8; for (i = 0; i < count; i++) { diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c index b360eca2b91..b66bcfc4233 100644 --- a/drivers/spi/mtk_spim.c +++ b/drivers/spi/mtk_spim.c @@ -18,7 +18,6 @@ #include <dm/devres.h> #include <dm/pinctrl.h> #include <linux/bitops.h> -#include <linux/completion.h> #include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/iopoll.h> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index e7c393ae188..9ab39a188b2 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -135,7 +135,7 @@ static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs) struct udevice *dev = mxcs->dev; struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs])) return; @@ -153,7 +153,7 @@ static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs) struct udevice *dev = mxcs->dev; struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs])) return; @@ -632,7 +632,7 @@ static int mxc_spi_claim_bus(struct udevice *dev) mxcs->dev = dev; - return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs); + return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs[0]); } static int mxc_spi_release_bus(struct udevice *dev) diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c index 73c506442ae..7b8271c8bbc 100644 --- a/drivers/spi/npcm_fiu_spi.c +++ b/drivers/spi/npcm_fiu_spi.c @@ -203,7 +203,7 @@ static int npcm_fiu_spi_xfer(struct udevice *dev, unsigned int bitlen, int len; if (flags & SPI_XFER_BEGIN) - activate_cs(regs, slave_plat->cs); + activate_cs(regs, slave_plat->cs[0]); while (bytes) { len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes; @@ -222,7 +222,7 @@ static int npcm_fiu_spi_xfer(struct udevice *dev, unsigned int bitlen, } if (flags & SPI_XFER_END) - deactivate_cs(regs, slave_plat->cs); + deactivate_cs(regs, slave_plat->cs[0]); return ret; } @@ -325,9 +325,9 @@ static int npcm_fiu_exec_op(struct spi_slave *slave, bytes = op->data.nbytes; addr = (u32)op->addr.val; if (!bytes) { - activate_cs(regs, slave_plat->cs); + activate_cs(regs, slave_plat->cs[0]); ret = npcm_fiu_uma_operation(priv, op, addr, NULL, NULL, 0, false); - deactivate_cs(regs, slave_plat->cs); + deactivate_cs(regs, slave_plat->cs[0]); return ret; } @@ -339,9 +339,9 @@ static int npcm_fiu_exec_op(struct spi_slave *slave, * Use HW-control CS for read to avoid clock and timing issues. */ if (op->data.dir == SPI_MEM_DATA_OUT) - activate_cs(regs, slave_plat->cs); + activate_cs(regs, slave_plat->cs[0]); else - writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, slave_plat->cs) | UMA_CTS_SW_CS, + writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, slave_plat->cs[0]) | UMA_CTS_SW_CS, ®s->uma_cts); while (bytes) { len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes; @@ -361,7 +361,7 @@ static int npcm_fiu_exec_op(struct spi_slave *slave, rx += len; } if (op->data.dir == SPI_MEM_DATA_OUT) - deactivate_cs(regs, slave_plat->cs); + deactivate_cs(regs, slave_plat->cs[0]); return 0; } diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index fefdaaa9e90..7489c896f9d 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -962,7 +962,7 @@ static int nxp_fspi_claim_bus(struct udevice *dev) bus = dev->parent; f = dev_get_priv(bus); - nxp_fspi_select_mem(f, slave_plat->cs); + nxp_fspi_select_mem(f, slave_plat->cs[0]); return 0; } diff --git a/drivers/spi/octeon_spi.c b/drivers/spi/octeon_spi.c index 4bc38beaa68..0e6e0f7dbe7 100644 --- a/drivers/spi/octeon_spi.c +++ b/drivers/spi/octeon_spi.c @@ -93,7 +93,7 @@ static u64 octeon_spi_set_mpicfg(struct udevice *dev) if (max_speed > OCTEON_SPI_MAX_CLOCK_HZ) max_speed = OCTEON_SPI_MAX_CLOCK_HZ; - debug("\n slave params %d %d %d\n", slave->cs, + debug("\n slave params %d %d %d\n", slave->cs[0], slave->max_hz, slave->mode); cpha = !!(slave->mode & SPI_CPHA); cpol = !!(slave->mode & SPI_CPOL); diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 3d82fc74ff5..35bd8766097 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -393,7 +393,7 @@ static int omap3_spi_claim_bus(struct udevice *dev) struct omap3_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - priv->cs = slave_plat->cs; + priv->cs = slave_plat->cs[0]; if (!priv->freq) priv->freq = slave_plat->max_hz; @@ -422,7 +422,7 @@ static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen) struct omap3_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - priv->cs = slave_plat->cs; + priv->cs = slave_plat->cs[0]; priv->wordlen = wordlen; _omap3_spi_set_wordlen(priv); diff --git a/drivers/spi/pic32_spi.c b/drivers/spi/pic32_spi.c index e11ae7fc7a4..c4b31dc2a61 100644 --- a/drivers/spi/pic32_spi.c +++ b/drivers/spi/pic32_spi.c @@ -247,7 +247,7 @@ static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen, slave_plat = dev_get_parent_plat(slave); debug("spi_xfer: bus:%i cs:%i flags:%lx\n", - dev_seq(bus), slave_plat->cs, flags); + dev_seq(bus), slave_plat->cs[0], flags); debug("msg tx %p, rx %p submitted of %d byte(s)\n", tx_buf, rx_buf, len); diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 4571dc9f9b6..2c3d70ba715 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -444,7 +444,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, /* Assert CS before transfer */ if (flags & SPI_XFER_BEGIN) - spi_cs_activate(dev, slave_plat->cs); + spi_cs_activate(dev, slave_plat->cs[0]); /* * To ensure fast loading of firmware images (e.g. full U-Boot @@ -507,7 +507,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, /* Deassert CS after transfer */ if (flags & SPI_XFER_END) - spi_cs_deactivate(dev, slave_plat->cs); + spi_cs_deactivate(dev, slave_plat->cs[0]); rkspi_enable_chip(regs, false); if (!out) diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index 596c22aa010..73738ab26d3 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -229,7 +229,7 @@ static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) sfc->regbase = dev_read_addr_ptr(bus); sfc->use_dma = !dev_read_bool(bus, "rockchip,sfc-no-dma"); - if (IS_ENABLED(CONFIG_SPL_BUILD) && sfc->use_dma) + if (IS_ENABLED(CONFIG_XPL_BUILD) && sfc->use_dma) sfc->use_dma = !dev_read_bool(bus, "u-boot,spl-sfc-no-dma"); #if CONFIG_IS_ENABLED(CLK) @@ -409,7 +409,7 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, /* set the Controller */ ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; - cmd |= plat->cs << SFC_CMD_CS_SHIFT; + cmd |= plat->cs[0] << SFC_CMD_CS_SHIFT; dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", op->addr.nbytes, op->addr.buswidth, diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 12320367e97..ca29cfd7c88 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -192,7 +192,7 @@ static u32 ast2400_get_clk_setting(struct udevice *dev, uint max_hz) if (found) { hclk_div = hclk_masks[i] << 8; - priv->flashes[slave_plat->cs].max_freq = hclk_clk / (i + 1); + priv->flashes[slave_plat->cs[0]].max_freq = hclk_clk / (i + 1); } dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no", @@ -200,7 +200,7 @@ static u32 ast2400_get_clk_setting(struct udevice *dev, uint max_hz) if (found) { dev_dbg(dev, "h_div: %d (mask %x), speed: %d\n", - i + 1, hclk_masks[i], priv->flashes[slave_plat->cs].max_freq); + i + 1, hclk_masks[i], priv->flashes[slave_plat->cs[0]].max_freq); } return hclk_div; @@ -311,7 +311,7 @@ static u32 ast2500_get_clk_setting(struct udevice *dev, uint max_hz) for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { if (hclk_clk / (i + 1) <= max_hz) { found = true; - priv->flashes[slave_plat->cs].max_freq = + priv->flashes[slave_plat->cs[0]].max_freq = hclk_clk / (i + 1); break; } @@ -325,7 +325,7 @@ static u32 ast2500_get_clk_setting(struct udevice *dev, uint max_hz) for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { if (hclk_clk / ((i + 1) * 4) <= max_hz) { found = true; - priv->flashes[slave_plat->cs].max_freq = + priv->flashes[slave_plat->cs[0]].max_freq = hclk_clk / ((i + 1) * 4); break; } @@ -340,7 +340,7 @@ end: if (found) { dev_dbg(dev, "h_div: %d (mask %x), speed: %d\n", - i + 1, hclk_masks[i], priv->flashes[slave_plat->cs].max_freq); + i + 1, hclk_masks[i], priv->flashes[slave_plat->cs[0]].max_freq); } return hclk_div; @@ -456,7 +456,7 @@ static u32 ast2600_get_clk_setting(struct udevice *dev, uint max_hz) if (found) { hclk_div = ((j << 24) | hclk_masks[i] << 8); - priv->flashes[slave_plat->cs].max_freq = + priv->flashes[slave_plat->cs[0]].max_freq = hclk_clk / (i + 1 + j * 16); break; } @@ -467,7 +467,7 @@ static u32 ast2600_get_clk_setting(struct udevice *dev, uint max_hz) if (found) { dev_dbg(dev, "base_clk: %d, h_div: %d (mask %x), speed: %d\n", - j, i + 1, hclk_masks[i], priv->flashes[slave_plat->cs].max_freq); + j, i + 1, hclk_masks[i], priv->flashes[slave_plat->cs[0]].max_freq); } return hclk_div; @@ -588,7 +588,7 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, struct udevice *bus = dev->parent; struct aspeed_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; u32 ce_ctrl_val; struct aspeed_spi_flash *flash = &priv->flashes[cs]; @@ -668,7 +668,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) const struct aspeed_spi_info *info = priv->info; struct spi_mem_op op_tmpl = desc->info.op_tmpl; u32 i; - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; u32 cmd_io_conf; u32 ce_ctrl_reg; @@ -725,7 +725,7 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, struct udevice *dev = desc->slave->dev; struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; int ret; dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n", @@ -750,7 +750,7 @@ static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); struct aspeed_spi_plat *plat = dev_get_plat(bus); struct aspeed_spi_priv *priv = dev_get_priv(bus); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; if (cs >= plat->max_cs) { dev_err(dev, "invalid CS %u\n", cs); @@ -1068,10 +1068,10 @@ static int aspeed_spi_claim_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); - struct aspeed_spi_flash *flash = &priv->flashes[slave_plat->cs]; + struct aspeed_spi_flash *flash = &priv->flashes[slave_plat->cs[0]]; u32 clk_setting; - dev_dbg(bus, "%s: claim bus CS%u\n", bus->name, slave_plat->cs); + dev_dbg(bus, "%s: claim bus CS%u\n", bus->name, slave_plat->cs[0]); if (flash->max_freq == 0) { clk_setting = priv->info->get_clk_setting(dev, slave_plat->max_hz); @@ -1089,7 +1089,7 @@ static int aspeed_spi_release_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - dev_dbg(bus, "%s: release bus CS%u\n", bus->name, slave_plat->cs); + dev_dbg(bus, "%s: release bus CS%u\n", bus->name, slave_plat->cs[0]); if (!aspeed_spi_get_flash(dev)) return -ENODEV; diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index b98bcd9b6ba..3835865ea7d 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -366,8 +366,8 @@ static int mxic_spi_mem_exec_op(struct spi_slave *slave, nio = 2; writel(HC_CFG_NIO(nio) | - HC_CFG_TYPE(slave_plat->cs, HC_CFG_TYPE_SPI_NOR) | - HC_CFG_SLV_ACT(slave_plat->cs) | HC_CFG_IDLE_SIO_LVL(1) | + HC_CFG_TYPE(slave_plat->cs[0], HC_CFG_TYPE_SPI_NOR) | + HC_CFG_SLV_ACT(slave_plat->cs[0]) | HC_CFG_IDLE_SIO_LVL(1) | HC_CFG_MAN_CS_EN, priv->regs + HC_CFG); writel(HC_EN_BIT, priv->regs + HC_EN); @@ -396,7 +396,7 @@ static int mxic_spi_mem_exec_op(struct spi_slave *slave, ss_ctrl |= OP_READ; } - writel(ss_ctrl, priv->regs + SS_CTRL(slave_plat->cs)); + writel(ss_ctrl, priv->regs + SS_CTRL(slave_plat->cs[0])); writel(readl(priv->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, priv->regs + HC_CFG); diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 836c550b0bb..dc001e6e4cc 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -718,7 +718,7 @@ static int qup_spi_xfer(struct udevice *dev, unsigned int bitlen, if (ret != 0) return ret; - ret = qup_spi_set_cs(bus, slave_plat->cs, false); + ret = qup_spi_set_cs(bus, slave_plat->cs[0], false); if (ret != 0) return ret; } @@ -736,7 +736,7 @@ static int qup_spi_xfer(struct udevice *dev, unsigned int bitlen, } if (flags & SPI_XFER_END) { - ret = qup_spi_set_cs(bus, slave_plat->cs, true); + ret = qup_spi_set_cs(bus, slave_plat->cs[0], true); if (ret != 0) return ret; } diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 0c8666c05f9..15407d482c9 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -108,13 +108,13 @@ static void sifive_spi_prep_device(struct sifive_spi *spi, { /* Update the chip select polarity */ if (slave_plat->mode & SPI_CS_HIGH) - spi->cs_inactive &= ~BIT(slave_plat->cs); + spi->cs_inactive &= ~BIT(slave_plat->cs[0]); else - spi->cs_inactive |= BIT(slave_plat->cs); + spi->cs_inactive |= BIT(slave_plat->cs[0]); writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); /* Select the correct device */ - writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID); + writel(slave_plat->cs[0], spi->regs + SIFIVE_SPI_REG_CSID); } static int sifive_spi_set_cs(struct sifive_spi *spi, diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c index fc82791006e..364ba4b3a97 100644 --- a/drivers/spi/spi-sn-f-ospi.c +++ b/drivers/spi/spi-sn-f-ospi.c @@ -497,7 +497,7 @@ static int f_ospi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) int err = 0; slave_plat = dev_get_parent_plat(slave->dev); - ospi->chip_select = slave_plat->cs; + ospi->chip_select = slave_plat->cs[0]; switch (op->data.dir) { case SPI_MEM_DATA_IN: diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index 88550b8ea84..e00532a371b 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -360,7 +360,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, } if (flags & SPI_XFER_BEGIN) - sun4i_spi_set_cs(bus, slave_plat->cs, true); + sun4i_spi_set_cs(bus, slave_plat->cs[0], true); /* Reset FIFOs */ setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) | @@ -391,7 +391,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, false, SUN4I_SPI_TIMEOUT_MS, false); if (ret < 0) { printf("ERROR: sun4i_spi: Timeout transferring data\n"); - sun4i_spi_set_cs(bus, slave_plat->cs, false); + sun4i_spi_set_cs(bus, slave_plat->cs[0], false); return ret; } @@ -402,7 +402,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, } if (flags & SPI_XFER_END) - sun4i_spi_set_cs(bus, slave_plat->cs, false); + sun4i_spi_set_cs(bus, slave_plat->cs[0], false); return 0; } diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index eb522fd7b3d..a3c0ad17121 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -193,12 +193,12 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) /* if nothing to do */ if (slave_plat->mode == priv->mode && rwflag == priv->rwflag && - slave_plat->cs == priv->cs && + slave_plat->cs[0] == priv->cs && slave_plat->max_hz == priv->speed) return; priv->rwflag = rwflag; - priv->cs = slave_plat->cs; + priv->cs = slave_plat->cs[0]; priv->mode = slave_plat->mode; priv->speed = slave_plat->max_hz; diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 6e281725239..36b7d383aa9 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -224,7 +224,7 @@ int spi_chip_select(struct udevice *dev) { struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); - return plat ? plat->cs : -ENOENT; + return plat ? plat->cs[0] : -ENOENT; } int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp) @@ -261,8 +261,8 @@ int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp) struct dm_spi_slave_plat *plat; plat = dev_get_parent_plat(dev); - dev_dbg(bus, "%s: plat=%p, cs=%d\n", __func__, plat, plat->cs); - if (plat->cs == cs) { + dev_dbg(bus, "%s: plat=%p, cs=%d\n", __func__, plat, plat->cs[0]); + if (plat->cs[0] == cs) { *devp = dev; return 0; } @@ -415,7 +415,7 @@ int _spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, return ret; } plat = dev_get_parent_plat(dev); - plat->cs = cs; + plat->cs[0] = cs; if (speed) { plat->max_hz = speed; } else { @@ -446,6 +446,12 @@ int _spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, slave = dev_get_parent_priv(dev); bus_data = dev_get_uclass_priv(bus); +#if CONFIG_IS_ENABLED(SPI_ADVANCE) + if ((dev_read_bool(dev, "parallel-memories")) && !slave->multi_cs_cap) { + dev_err(dev, "controller doesn't support multi CS\n"); + return -EINVAL; + } +#endif /* * In case the operation speed is not yet established by * dm_spi_claim_bus() ensure the bus is configured properly. @@ -509,7 +515,21 @@ int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) int mode = 0; int value; - plat->cs = dev_read_u32_default(dev, "reg", -1); +#if CONFIG_IS_ENABLED(SPI_ADVANCE) + int ret; + + ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); + + if (ret == -EOVERFLOW || ret == -FDT_ERR_BADLAYOUT) { + dev_read_u32(dev, "reg", &plat->cs[0]); + } else { + dev_err(dev, "has no valid 'reg' property (%d)\n", ret); + return ret; + } +#else + plat->cs[0] = dev_read_u32_default(dev, "reg", -1); +#endif + plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", SPI_DEFAULT_SPEED_HZ); if (dev_read_bool(dev, "spi-cpol")) @@ -538,7 +558,7 @@ int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) mode |= SPI_TX_OCTAL; break; default: - warn_non_spl("spi-tx-bus-width %d not supported\n", value); + warn_non_xpl("spi-tx-bus-width %d not supported\n", value); break; } @@ -556,7 +576,7 @@ int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) mode |= SPI_RX_OCTAL; break; default: - warn_non_spl("spi-rx-bus-width %d not supported\n", value); + warn_non_xpl("spi-rx-bus-width %d not supported\n", value); break; } diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 2812a4da411..3216ec8010e 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -394,7 +394,7 @@ static int stm32_qspi_claim_bus(struct udevice *dev) { struct stm32_qspi_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - int slave_cs = slave_plat->cs; + int slave_cs = slave_plat->cs[0]; if (slave_cs >= STM32_QSPI_MAX_CHIP) return -ENODEV; diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c index 97b83b17167..a1f31cf653c 100644 --- a/drivers/spi/stm32_spi.c +++ b/drivers/spi/stm32_spi.c @@ -434,7 +434,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, slave_plat = dev_get_parent_plat(slave); if (flags & SPI_XFER_BEGIN) - stm32_spi_set_cs(bus, slave_plat->cs, false); + stm32_spi_set_cs(bus, slave_plat->cs[0], false); /* Be sure to have data in fifo before starting data transfer */ if (priv->tx_buf) @@ -485,7 +485,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, stm32_spi_stopxfer(bus); if (flags & SPI_XFER_END) - stm32_spi_set_cs(bus, slave_plat->cs, true); + stm32_spi_set_cs(bus, slave_plat->cs[0], true); return xfer_status; } diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index a16412ec6fb..1f2494e592c 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -163,7 +163,7 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, uchar *rxp = din; uint status; int timeout; - unsigned int cs = slave->cs; + unsigned int cs = slave->cs[0]; bus = dev->parent; priv = dev_get_priv(bus); @@ -344,7 +344,7 @@ static int ti_qspi_exec_mem_op(struct spi_slave *slave, if (from + op->data.nbytes > priv->mmap_size) return -ENOTSUPP; - ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode, + ti_qspi_setup_mmap_read(priv, slave_plat->cs[0], op->cmd.opcode, op->data.buswidth, op->addr.nbytes, op->dummy.nbytes); @@ -363,7 +363,7 @@ static int ti_qspi_claim_bus(struct udevice *dev) bus = dev->parent; priv = dev_get_priv(bus); - if (slave_plat->cs > priv->num_cs) { + if (slave_plat->cs[0] > priv->num_cs) { debug("invalid qspi chip select\n"); return -EINVAL; } @@ -371,13 +371,13 @@ static int ti_qspi_claim_bus(struct udevice *dev) writel(MM_SWITCH, &priv->base->memswitch); if (priv->ctrl_mod_mmap) ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, - slave_plat->cs, true); + slave_plat->cs[0], true); writel(priv->dc, &priv->base->dc); writel(0, &priv->base->cmd); writel(0, &priv->base->data); - priv->dc <<= slave_plat->cs * 8; + priv->dc <<= slave_plat->cs[0] * 8; writel(priv->dc, &priv->base->dc); return 0; @@ -395,12 +395,12 @@ static int ti_qspi_release_bus(struct udevice *dev) writel(~MM_SWITCH, &priv->base->memswitch); if (priv->ctrl_mod_mmap) ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, - slave_plat->cs, false); + slave_plat->cs[0], false); writel(0, &priv->base->dc); writel(0, &priv->base->cmd); writel(0, &priv->base->data); - writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs)); + writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs[0])); return 0; } diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 0e7fa3a4525..b2af17ebae9 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -291,7 +291,7 @@ static void xilinx_spi_startup_block(struct udevice *dev) * Perform a dummy read as a work around for * the startup block issue. */ - spi_cs_activate(dev, slave_plat->cs); + spi_cs_activate(dev, slave_plat->cs[0]); txp = 0x9f; start_transfer(dev, (void *)&txp, NULL, 1); @@ -306,7 +306,7 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen, struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); int ret; - spi_cs_activate(dev, slave_plat->cs); + spi_cs_activate(dev, slave_plat->cs[0]); ret = start_transfer(dev, dout, din, bitlen / 8); spi_cs_deactivate(dev); return ret; @@ -331,7 +331,7 @@ static int xilinx_spi_mem_exec_op(struct spi_slave *spi, startup++; } - spi_cs_activate(spi->dev, slave_plat->cs); + spi_cs_activate(spi->dev, slave_plat->cs[0]); if (op->cmd.opcode) { ret = start_transfer(spi->dev, (void *)&op->cmd.opcode, diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index b71b9a6fd6c..f5b3fb5c125 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013 Xilinx, Inc. + * (C) Copyright 2013 - 2022, Xilinx, Inc. * (C) Copyright 2015 Jagan Teki <jteki@openedev.com> + * (C) Copyright 2023, Advanced Micro Devices, Inc. * * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only) */ @@ -12,10 +13,12 @@ #include <log.h> #include <malloc.h> #include <spi.h> +#include <spi_flash.h> #include <asm/global_data.h> #include <asm/io.h> #include <linux/bitops.h> #include <spi-mem.h> +#include "../mtd/spi/sf_internal.h" DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +44,21 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */ #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */ #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */ +#define ZYNQ_QSPI_FR_QOUT_CODE 0x6B /* read instruction code */ + +#define QSPI_SELECT_LOWER_CS BIT(0) +#define QSPI_SELECT_UPPER_CS BIT(1) + +/* + * QSPI Linear Configuration Register + * + * It is named Linear Configuration but it controls other modes when not in + * linear mode also. + */ +#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK 0x40000000 /* QSPI Enable Bit Mask */ +#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK 0x20000000 /* QSPI Enable Bit Mask */ +#define ZYNQ_QSPI_LCFG_U_PAGE 0x10000000 /* QSPI Upper memory set */ +#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/ #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */ @@ -100,7 +118,11 @@ struct zynq_qspi_priv { int bytes_to_transfer; int bytes_to_receive; unsigned int is_inst; + unsigned int is_parallel; + unsigned int is_stacked; + unsigned int u_page; unsigned cs_change:1; + unsigned is_strip:1; }; static int zynq_qspi_of_to_plat(struct udevice *bus) @@ -111,7 +133,6 @@ static int zynq_qspi_of_to_plat(struct udevice *bus) plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob, node, "reg"); - return 0; } @@ -146,6 +167,9 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) /* Disable Interrupts */ writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr); + /* Disable linear mode as the boot loader may have used it */ + writel(0x0, ®s->lqspicfg); + /* Clear the TX and RX threshold reg */ writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr); writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr); @@ -163,12 +187,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK | ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK | ZYNQ_QSPI_CR_MSTREN_MASK; - writel(confr, ®s->cr); - /* Disable the LQSPI feature */ - confr = readl(®s->lqspicfg); - confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; - writel(confr, ®s->lqspicfg); + if (priv->is_stacked) + confr |= 0x10; + + writel(confr, ®s->cr); /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); @@ -180,6 +203,7 @@ static int zynq_qspi_child_pre_probe(struct udevice *bus) struct zynq_qspi_priv *priv = dev_get_priv(bus->parent); priv->max_hz = slave->max_hz; + slave->multi_cs_cap = true; return 0; } @@ -362,8 +386,8 @@ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size) unsigned len, offset; struct zynq_qspi_regs *regs = priv->regs; static const unsigned offsets[4] = { - ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET, - ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET }; + ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET, + ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET }; while ((fifocount < size) && (priv->bytes_to_transfer > 0)) { @@ -385,7 +409,11 @@ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size) return; len = priv->bytes_to_transfer; zynq_qspi_write_data(priv, &data, len); - offset = (priv->rx_buf) ? offsets[0] : offsets[len]; + if ((priv->is_parallel || priv->is_stacked) && + !priv->is_inst && (len % 2)) + len++; + offset = (priv->rx_buf) ? + offsets[3] : offsets[len - 1]; writel(data, ®s->cr + (offset / 4)); } } @@ -490,6 +518,7 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) */ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) { + static u8 current_u_page; u32 data = 0; struct zynq_qspi_regs *regs = priv->regs; @@ -499,6 +528,34 @@ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) priv->bytes_to_transfer = priv->len; priv->bytes_to_receive = priv->len; + if (priv->is_parallel) + writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | + ZYNQ_QSPI_LCFG_SEP_BUS_MASK | + (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | + ZYNQ_QSPI_FR_QOUT_CODE), ®s->lqspicfg); + + if (priv->is_inst && priv->is_stacked && current_u_page != priv->u_page) { + if (priv->u_page) { + /* Configure two memories on shared bus + * by enabling upper mem + */ + writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | + ZYNQ_QSPI_LCFG_U_PAGE | + (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | + ZYNQ_QSPI_FR_QOUT_CODE), + ®s->lqspicfg); + } else { + /* Configure two memories on shared bus + * by enabling lower mem + */ + writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | + (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | + ZYNQ_QSPI_FR_QOUT_CODE), + ®s->lqspicfg); + } + current_u_page = priv->u_page; + } + if (priv->len < 4) zynq_qspi_fill_tx_fifo(priv, priv->len); else @@ -585,20 +642,21 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen, struct zynq_qspi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - priv->cs = slave_plat->cs; + priv->cs = slave_plat->cs[0]; priv->tx_buf = dout; priv->rx_buf = din; priv->len = bitlen / 8; - debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", - dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags); + debug("zynq_qspi_xfer: bus:%i cs[0]:%i bitlen:%i len:%i flags:%lx\n", + dev_seq(bus), slave_plat->cs[0], bitlen, priv->len, flags); /* * Festering sore. * Assume that the beginning of a transfer with bits to * transmit must contain a device command. */ - if (dout && flags & SPI_XFER_BEGIN) + if ((dout && flags & SPI_XFER_BEGIN) || + (flags & SPI_XFER_END && !priv->is_strip)) priv->is_inst = 1; else priv->is_inst = 0; @@ -608,6 +666,11 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen, else priv->cs_change = 0; + if (flags & SPI_XFER_U_PAGE) + priv->u_page = 1; + else + priv->u_page = 0; + zynq_qspi_transfer(priv); return 0; @@ -671,14 +734,35 @@ static int zynq_qspi_set_mode(struct udevice *bus, uint mode) return 0; } +bool update_stripe(const struct spi_mem_op *op) +{ + if (op->cmd.opcode == SPINOR_OP_BE_4K || + op->cmd.opcode == SPINOR_OP_CHIP_ERASE || + op->cmd.opcode == SPINOR_OP_SE || + op->cmd.opcode == SPINOR_OP_WREAR || + op->cmd.opcode == SPINOR_OP_WRSR + ) + return false; + + return true; +} + static int zynq_qspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { + struct udevice *bus = slave->dev->parent; + struct zynq_qspi_priv *priv = dev_get_priv(bus); int op_len, pos = 0, ret, i; unsigned int flag = 0; const u8 *tx_buf = NULL; u8 *rx_buf = NULL; + if ((slave->flags & QSPI_SELECT_LOWER_CS) && + (slave->flags & QSPI_SELECT_UPPER_CS)) + priv->is_parallel = true; + if (slave->flags & SPI_XFER_STACKED) + priv->is_stacked = true; + if (op->data.nbytes) { if (op->data.dir == SPI_MEM_DATA_IN) rx_buf = op->data.buf.in; @@ -703,6 +787,9 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, if (op->dummy.nbytes) memset(op_buf + pos, 0xff, op->dummy.nbytes); + if (slave->flags & SPI_XFER_U_PAGE) + flag |= SPI_XFER_U_PAGE; + /* 1st transfer: opcode + address + dummy cycles */ /* Make sure to set END bit if no tx or rx data messages follow */ if (!tx_buf && !rx_buf) @@ -713,6 +800,9 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, if (ret) return ret; + if (priv->is_parallel) + priv->is_strip = update_stripe(op); + /* 2nd transfer: rx or tx data path */ if (tx_buf || rx_buf) { ret = zynq_qspi_xfer(slave->dev, op->data.nbytes * 8, tx_buf, @@ -721,6 +811,9 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, return ret; } + priv->is_parallel = false; + priv->is_stacked = false; + slave->flags &= ~SPI_XFER_MASK; spi_release_bus(slave); return 0; diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index d15d91a1d24..37fa12b96b5 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -240,15 +240,15 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, u8 *rx_buf = din, buf; u32 ts, status; - debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", - dev_seq(bus), slave_plat->cs, bitlen, len, flags); + debug("spi_xfer: bus:%i cs[0]:%i bitlen:%i len:%i flags:%lx\n", + dev_seq(bus), slave_plat->cs[0], bitlen, len, flags); if (bitlen % 8) { debug("spi_xfer: Non byte aligned SPI transfer\n"); return -1; } - priv->cs = slave_plat->cs; + priv->cs = slave_plat->cs[0]; if (flags & SPI_XFER_BEGIN) spi_cs_activate(dev); diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index ae795e50b0a..1d19b2606c5 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2018 Xilinx - * + * (C) Copyright 2013 - 2022, Xilinx, Inc. + * (C) Copyright 2023, Advanced Micro Devices, Inc. * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) */ @@ -24,6 +24,8 @@ #include <linux/bitops.h> #include <linux/err.h> #include <linux/sizes.h> +#include <linux/mtd/spi-nor.h> +#include "../mtd/spi/sf_internal.h" #include <zynqmp_firmware.h> #define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) @@ -87,6 +89,9 @@ #define SPI_XFER_ON_LOWER 1 #define SPI_XFER_ON_UPPER 2 +#define GQSPI_SELECT_LOWER_CS BIT(0) +#define GQSPI_SELECT_UPPER_CS BIT(1) + #define GQSPI_DMA_ALIGN 0x4 #define GQSPI_MAX_BAUD_RATE_VAL 7 #define GQSPI_DFLT_BAUD_RATE_VAL 2 @@ -183,13 +188,14 @@ struct zynqmp_qspi_priv { int bytes_to_transfer; int bytes_to_receive; const struct spi_mem_op *op; + unsigned int is_parallel; + unsigned int u_page; + unsigned int bus; + unsigned int stripe; + unsigned int flags; + u32 max_hz; }; -__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) -{ - return 0; -} - static int zynqmp_qspi_of_to_plat(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); @@ -234,8 +240,30 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) { u32 gqspi_fifo_reg = 0; - gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | - GQSPI_GFIFO_CS_LOWER; + if (priv->is_parallel) { + if (priv->bus == SPI_XFER_ON_BOTH) + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | + GQSPI_GFIFO_UP_BUS | + GQSPI_GFIFO_CS_UPPER | + GQSPI_GFIFO_CS_LOWER; + else if (priv->bus == SPI_XFER_ON_LOWER) + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | + GQSPI_GFIFO_CS_UPPER | + GQSPI_GFIFO_CS_LOWER; + else if (priv->bus == SPI_XFER_ON_UPPER) + gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS | + GQSPI_GFIFO_CS_LOWER | + GQSPI_GFIFO_CS_UPPER; + else + debug("Wrong Bus selection:0x%x\n", priv->bus); + } else { + if (priv->u_page) + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | + GQSPI_GFIFO_CS_UPPER; + else + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | + GQSPI_GFIFO_CS_LOWER; + } return gqspi_fifo_reg; } @@ -295,8 +323,15 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI | GQSPI_IMD_DATA_CS_ASSERT; } else { - gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS; - gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT; + if (priv->is_parallel) { + gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS | + GQSPI_GFIFO_LOW_BUS; + } else if (priv->u_page) { + gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS; + } else { + gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS; + gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT; + } } zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg); @@ -367,12 +402,13 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency); - if (speed > plat->frequency) - speed = plat->frequency; + /* + * If speed == 0 or speed > max freq, then set speed to highest + */ + if (!speed || speed > priv->max_hz) + speed = priv->max_hz; if (plat->speed_hz != speed) { - /* Set the clock frequency */ - /* If speed == 0, default to lowest speed */ while ((baud_rate_val < 8) && ((plat->frequency / (2 << baud_rate_val)) > speed)) @@ -394,6 +430,18 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) return 0; } +static int zynqmp_qspi_child_pre_probe(struct udevice *bus) +{ + struct spi_slave *slave = dev_get_parent_priv(bus); + struct zynqmp_qspi_priv *priv = dev_get_priv(bus->parent); + + slave->multi_cs_cap = true; + slave->bytemode = SPI_4BYTE_MODE; + priv->max_hz = slave->max_hz; + + return 0; +} + static int zynqmp_qspi_probe(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); @@ -458,12 +506,17 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode) static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) { - u32 data; + u32 data, ier; int ret = 0; struct zynqmp_qspi_regs *regs = priv->regs; u32 *buf = (u32 *)priv->tx_buf; u32 len = size; + /* Enable interrupts */ + ier = readl(®s->ier); + ier |= GQSPI_IXR_ALL_MASK | GQSPI_IXR_TXFIFOEMPTY_MASK; + writel(ier, ®s->ier); + while (size) { ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1, GQSPI_TIMEOUT, 1); @@ -586,6 +639,9 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK; + if (priv->stripe) + gen_fifo_cmd |= GQSPI_GFIFO_STRIPE_MASK; + while (priv->len) { len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); @@ -720,6 +776,9 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK; + if (priv->stripe) + gen_fifo_cmd |= GQSPI_GFIFO_STRIPE_MASK; + /* * Check if receive buffer is aligned to 4 byte and length * is multiples of four byte as we are using dma to receive. @@ -760,6 +819,33 @@ static int zynqmp_qspi_release_bus(struct udevice *dev) return 0; } +static bool zynqmp_qspi_update_stripe(const struct spi_mem_op *op) +{ + /* + * This is a list of opcodes for which we must not use striped access + * even in dual parallel mode, but instead broadcast the same data to + * both chips. This is primarily erase commands and writing some + * registers. + */ + switch (op->cmd.opcode) { + case SPINOR_OP_BE_4K: + case SPINOR_OP_BE_32K: + case SPINOR_OP_CHIP_ERASE: + case SPINOR_OP_SE: + case SPINOR_OP_BE_32K_4B: + case SPINOR_OP_SE_4B: + case SPINOR_OP_BE_4K_4B: + case SPINOR_OP_WRSR: + case SPINOR_OP_WREAR: + case SPINOR_OP_BRWR: + return false; + case SPINOR_OP_WRSR2: + return op->addr.nbytes != 0; + default: + return true; + } +} + static int zynqmp_qspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { @@ -771,6 +857,25 @@ static int zynqmp_qspi_exec_op(struct spi_slave *slave, priv->rx_buf = op->data.buf.in; priv->len = op->data.nbytes; + if (slave->flags & SPI_XFER_U_PAGE) + priv->u_page = 1; + else + priv->u_page = 0; + + if ((slave->flags & GQSPI_SELECT_LOWER_CS) && + (slave->flags & GQSPI_SELECT_UPPER_CS)) + priv->is_parallel = true; + + priv->stripe = 0; + priv->bus = 0; + + if (priv->is_parallel) { + if (slave->flags & SPI_XFER_MASK) + priv->bus = (slave->flags & SPI_XFER_MASK) >> 8; + if (zynqmp_qspi_update_stripe(op)) + priv->stripe = 1; + } + zynqmp_qspi_chipselect(priv, 1); /* Send opcode, addr, dummy */ @@ -784,6 +889,9 @@ static int zynqmp_qspi_exec_op(struct spi_slave *slave, zynqmp_qspi_chipselect(priv, 0); + priv->is_parallel = false; + slave->flags &= ~SPI_XFER_MASK; + return ret; } @@ -814,4 +922,5 @@ U_BOOT_DRIVER(zynqmp_qspi) = { .plat_auto = sizeof(struct zynqmp_qspi_plat), .priv_auto = sizeof(struct zynqmp_qspi_priv), .probe = zynqmp_qspi_probe, + .child_pre_probe = zynqmp_qspi_child_pre_probe, }; diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index a6a0584585c..796fc9effa5 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -2,7 +2,7 @@ # # (C) Copyright 2016 Cadence Design Systems Inc. -obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o +obj-$(CONFIG_$(PHASE_)SYSRESET) += sysreset-uclass.o obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o obj-$(CONFIG_ARCH_STI) += sysreset_sti.o @@ -10,24 +10,24 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_SYSRESET_CV1800B) += sysreset_cv1800b.o obj-$(CONFIG_POWEROFF_GPIO) += poweroff_gpio.o obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o -obj-$(CONFIG_$(SPL_TPL_)SYSRESET_MAX77663) += sysreset_max77663.o +obj-$(CONFIG_$(PHASE_)SYSRESET_MAX77663) += sysreset_max77663.o obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o -obj-$(CONFIG_$(SPL_TPL_)SYSRESET_PALMAS) += sysreset_palmas.o +obj-$(CONFIG_$(PHASE_)SYSRESET_PALMAS) += sysreset_palmas.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o obj-$(CONFIG_SYSRESET_TEGRA) += sysreset_tegra.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o -obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS65910) += sysreset_tps65910.o -obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS80031) += sysreset_tps80031.o +obj-$(CONFIG_$(PHASE_)SYSRESET_TPS65910) += sysreset_tps65910.o +obj-$(CONFIG_$(PHASE_)SYSRESET_TPS80031) += sysreset_tps80031.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o -obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o -obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o +obj-$(CONFIG_$(PHASE_)SYSRESET_AT91) += sysreset_at91.o +obj-$(CONFIG_$(PHASE_)SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o obj-$(CONFIG_SYSRESET_QCOM_PSHOLD) += sysreset_qcom-pshold.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index d30b008bf9a..536ac727142 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -102,7 +102,7 @@ void sysreset_walk_halt(enum sysreset_t type) mdelay(100); /* Still no reset? Give up */ - if (spl_phase() <= PHASE_SPL) + if (xpl_phase() <= PHASE_SPL) log_err("no sysreset\n"); else log_err("System reset not supported on this platform\n"); diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c index ef09440bbef..4e15ebd53cc 100644 --- a/drivers/sysreset/sysreset_ast.c +++ b/drivers/sysreset/sysreset_ast.c @@ -33,7 +33,7 @@ static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type) return -EPROTONOSUPPORT; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) ret = wdt_expire_now(wdt, reset_mode); if (ret) { debug("Sysreset failed: %d", ret); diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index fec4af392e6..7a847e8388b 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -5,14 +5,14 @@ obj-y += timer-uclass.o obj-$(CONFIG_ADI_SC5XX_TIMER) += adi_sc5xx_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o -obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o +obj-$(CONFIG_$(XPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_AST_IBEX_TIMER) += ast_ibex_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o -obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o -obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o +obj-$(CONFIG_$(XPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o +obj-$(CONFIG_$(XPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_FTTMR010_TIMER) += fttmr010_timer.o @@ -27,7 +27,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_SP804_TIMER) += sp804_timer.o -obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += riscv_aclint_timer.o +obj-$(CONFIG_$(XPL_)RISCV_ACLINT) += riscv_aclint_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index 9540fd7fe78..76e516dbbaf 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (c) 2011 The Chromium OS Authors. All rights reserved. -obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm-uclass.o +obj-$(CONFIG_$(PHASE_)TPM) += tpm-uclass.o obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o obj-$(CONFIG_TPM_TIS_INFINEON) += tpm_tis_infineon.o @@ -10,7 +10,7 @@ obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o sandbox_common.o obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o -obj-$(CONFIG_$(SPL_TPL_)TPM2_CR50_I2C) += cr50_i2c.o +obj-$(CONFIG_$(PHASE_)TPM2_CR50_I2C) += cr50_i2c.o obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o sandbox_common.o obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_core.o tpm2_tis_spi.o obj-$(CONFIG_TPM2_TIS_I2C) += tpm2_tis_core.o tpm2_tis_i2c.o diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig index 7da46faed6b..b08ca08b07c 100644 --- a/drivers/ufs/Kconfig +++ b/drivers/ufs/Kconfig @@ -26,6 +26,13 @@ config UFS_PCI If unsure, say N. +config QCOM_UFS + bool "Qualcomm Host Controller driver for UFS" + depends on UFS && ARCH_SNAPDRAGON + help + This selects the platform driver for the UFS host + controller present on Qualcomm Snapdragon SoCs. + config TI_J721E_UFS bool "Glue Layer driver for UFS on TI J721E devices" help @@ -41,4 +48,12 @@ config UFS_RENESAS UFS host on Renesas needs some vendor specific configuration before accessing the hardware. +config UFS_AMD_VERSAL2 + bool "AMD Versal Gen 2 UFS controller platform driver" + depends on UFS && ZYNQMP_FIRMWARE + help + This selects the AMD specific additions to UFSHCD platform driver. + UFS host on AMD needs some vendor specific configuration before accessing + the hardware. + endmenu diff --git a/drivers/ufs/Makefile b/drivers/ufs/Makefile index 67c42621aba..2a378e45111 100644 --- a/drivers/ufs/Makefile +++ b/drivers/ufs/Makefile @@ -5,6 +5,8 @@ obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o obj-$(CONFIG_CADENCE_UFS) += cdns-platform.o +obj-$(CONFIG_QCOM_UFS) += ufs-qcom.o obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o obj-$(CONFIG_UFS_PCI) += ufs-pci.o obj-$(CONFIG_UFS_RENESAS) += ufs-renesas.o +obj-$(CONFIG_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c new file mode 100644 index 00000000000..bfd844e4193 --- /dev/null +++ b/drivers/ufs/ufs-amd-versal2.c @@ -0,0 +1,501 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Advanced Micro Devices, Inc. + */ + +#include <clk.h> +#include <dm.h> +#include <ufs.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <zynqmp_firmware.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/time.h> +#include <reset.h> + +#include "ufs.h" +#include "ufshcd-dwc.h" +#include "ufshci-dwc.h" + +#define VERSAL2_UFS_DEVICE_ID 4 + +#define SRAM_CSR_INIT_DONE_MASK BIT(0) +#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) +#define SRAM_CSR_BYPASS_MASK BIT(2) + +#define MPHY_FAST_RX_AFE_CAL BIT(2) +#define MPHY_FW_CALIB_CFG_VAL BIT(8) + +#define TX_RX_CFG_RDY_MASK GENMASK(3, 0) + +#define TIMEOUT_MICROSEC 1000000L + +#define IOCTL_UFS_TXRX_CFGRDY_GET 40 +#define IOCTL_UFS_SRAM_CSR_SEL 41 + +#define PM_UFS_SRAM_CSR_WRITE 0 +#define PM_UFS_SRAM_CSR_READ 1 + +struct ufs_versal2_priv { + struct ufs_hba *hba; + struct reset_ctl *rstc; + struct reset_ctl *rstphy; + u32 phy_mode; + u32 host_clk; + u32 pd_dev_id; + u8 attcompval0; + u8 attcompval1; + u8 ctlecompval0; + u8 ctlecompval1; +}; + +static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) +{ + static struct ufshcd_dme_attr_val phy_write_attrs[] = { + { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + phy_write_attrs[0].mib_val = (u8)addr; + phy_write_attrs[1].mib_val = (u8)(addr >> 8); + phy_write_attrs[2].mib_val = (u8)val; + phy_write_attrs[3].mib_val = (u8)(val >> 8); + + return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs)); +} + +static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) +{ + u32 mib_val; + int ret; + static struct ufshcd_dme_attr_val phy_read_attrs[] = { + { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + phy_read_attrs[0].mib_val = (u8)addr; + phy_read_attrs[1].mib_val = (u8)(addr >> 8); + + ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs)); + if (ret) + return ret; + + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); + if (ret) + return ret; + + *val = mib_val; + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); + if (ret) + return ret; + + *val |= (mib_val << 8); + + return 0; +} + +int versal2_pm_ufs_get_txrx_cfgrdy(u32 node_id, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_TXRX_CFGRDY_GET, + 0, 0, ret_payload); + *value = ret_payload[1]; + + return ret; +} + +int versal2_pm_ufs_sram_csr_sel(u32 node_id, u32 type, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + if (type == PM_UFS_SRAM_CSR_READ) { + ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL, + type, 0, ret_payload); + *value = ret_payload[1]; + } else { + ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL, + type, *value, 0); + } + + return ret; +} + +static int ufs_versal2_enable_phy(struct ufs_hba *hba) +{ + u32 offset, reg; + int ret; + + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0); + if (ret) + return ret; + + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); + if (ret) + return ret; + + /* Check Tx/Rx FSM states */ + for (offset = 0; offset < 2; offset++) { + u32 time_left, mibsel; + + time_left = TIMEOUT_MICROSEC; + mibsel = UIC_ARG_MIB_SEL(MTX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(offset)); + do { + ret = ufshcd_dme_get(hba, mibsel, ®); + if (ret) + return ret; + + if (reg == TX_STATE_HIBERN8 || reg == TX_STATE_SLEEP || + reg == TX_STATE_LSBURST) + break; + + time_left--; + mdelay(5); + } while (time_left); + + if (!time_left) { + dev_err(hba->dev, "Invalid Tx FSM state.\n"); + return -ETIMEDOUT; + } + + time_left = TIMEOUT_MICROSEC; + mibsel = UIC_ARG_MIB_SEL(MRX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(offset)); + do { + ret = ufshcd_dme_get(hba, mibsel, ®); + if (ret) + return ret; + + if (reg == RX_STATE_HIBERN8 || reg == RX_STATE_SLEEP || + reg == RX_STATE_LSBURST) + break; + + time_left--; + mdelay(5); + } while (time_left); + + if (!time_left) { + dev_err(hba->dev, "Invalid Rx FSM state.\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int ufs_versal2_setup_phy(struct ufs_hba *hba) +{ + struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); + int ret; + u32 reg; + + /* Bypass RX-AFE offset calibrations (ATT/CTLE) */ + ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®); + if (ret) + return ret; + + reg |= MPHY_FAST_RX_AFE_CAL; + ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg); + if (ret) + return ret; + + ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®); + if (ret) + return ret; + + reg |= MPHY_FAST_RX_AFE_CAL; + ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg); + if (ret) + return ret; + + /* Program ATT and CTLE compensation values */ + if (priv->attcompval0) { + ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), priv->attcompval0); + if (ret) + return ret; + } + + if (priv->attcompval1) { + ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), priv->attcompval1); + if (ret) + return ret; + } + + if (priv->ctlecompval0) { + ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), priv->ctlecompval0); + if (ret) + return ret; + } + + if (priv->ctlecompval1) { + ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), priv->ctlecompval1); + if (ret) + return ret; + } + + ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); + if (ret) + return ret; + + reg |= MPHY_FW_CALIB_CFG_VAL; + ret = ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); + if (ret) + return ret; + + ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); + if (ret) + return ret; + + reg |= MPHY_FW_CALIB_CFG_VAL; + return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); +} + +static int ufs_versal2_phy_init(struct ufs_hba *hba) +{ + struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); + u32 reg, time_left; + int ret; + static const struct ufshcd_dme_attr_val rmmi_attrs[] = { + { UIC_ARG_MIB(CBREFCLKCTRL2), CBREFREFCLK_GATE_OVR_EN, DME_LOCAL }, + { UIC_ARG_MIB(CBCRCTRL), 1, DME_LOCAL }, + { UIC_ARG_MIB(CBC10DIRECTCONF2), 1, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + /* Wait for Tx/Rx config_rdy */ + time_left = TIMEOUT_MICROSEC; + do { + time_left--; + ret = versal2_pm_ufs_get_txrx_cfgrdy(priv->pd_dev_id, ®); + if (ret) + return ret; + + reg &= TX_RX_CFG_RDY_MASK; + if (!reg) + break; + + mdelay(5); + } while (time_left); + + if (!time_left) { + dev_err(hba->dev, "Tx/Rx configuration signal busy.\n"); + return -ETIMEDOUT; + } + + ret = ufshcd_dwc_dme_set_attrs(hba, rmmi_attrs, ARRAY_SIZE(rmmi_attrs)); + if (ret) + return ret; + + /* DeAssert PHY reset */ + ret = reset_deassert(priv->rstphy); + if (ret) { + dev_err(hba->dev, "ufsphy reset deassert failed\n"); + return ret; + } + + /* Wait for SRAM init done */ + time_left = TIMEOUT_MICROSEC; + do { + time_left--; + ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, + PM_UFS_SRAM_CSR_READ, ®); + if (ret) + return ret; + + reg &= SRAM_CSR_INIT_DONE_MASK; + if (reg) + break; + + mdelay(5); + } while (time_left); + + if (!time_left) { + dev_err(hba->dev, "SRAM initialization failed.\n"); + return -ETIMEDOUT; + } + + ret = ufs_versal2_setup_phy(hba); + if (ret) + return ret; + + return ufs_versal2_enable_phy(hba); +} + +static int ufs_versal2_init(struct ufs_hba *hba) +{ + struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); + struct clk clk; + unsigned long core_clk_rate = 0; + int ret = 0; + + priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM; + priv->pd_dev_id = VERSAL2_UFS_DEVICE_ID; + + ret = clk_get_by_name(hba->dev, "core_clk", &clk); + if (ret) { + dev_err(hba->dev, "failed to get core_clk clock\n"); + return ret; + } + + core_clk_rate = clk_get_rate(&clk); + if (IS_ERR_VALUE(core_clk_rate)) { + dev_err(hba->dev, "%s: unable to find core_clk rate\n", + __func__); + return core_clk_rate; + } + priv->host_clk = core_clk_rate; + + priv->rstc = devm_reset_control_get(hba->dev, "ufshc-rst"); + if (IS_ERR(priv->rstc)) { + dev_err(hba->dev, "failed to get reset ctl: ufshc-rst\n"); + return PTR_ERR(priv->rstc); + } + priv->rstphy = devm_reset_control_get(hba->dev, "ufsphy-rst"); + if (IS_ERR(priv->rstphy)) { + dev_err(hba->dev, "failed to get reset ctl: ufsphy-rst\n"); + return PTR_ERR(priv->rstphy); + } + + return ret; +} + +static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); + u32 sram_csr; + int ret; + + switch (status) { + case PRE_CHANGE: + /* Assert RST_UFS Reset for UFS block in PMX_IOU */ + ret = reset_assert(priv->rstc); + if (ret) { + dev_err(hba->dev, "ufshc reset assert failed, err = %d\n", ret); + return ret; + } + + /* Assert PHY reset */ + ret = reset_assert(priv->rstphy); + if (ret) { + dev_err(hba->dev, "ufsphy reset assert failed, err = %d\n", ret); + return ret; + } + + ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, + PM_UFS_SRAM_CSR_READ, &sram_csr); + if (ret) + return ret; + + if (!priv->phy_mode) { + sram_csr &= ~SRAM_CSR_EXT_LD_DONE_MASK; + sram_csr |= SRAM_CSR_BYPASS_MASK; + } else { + dev_err(hba->dev, "Invalid phy-mode %d.\n", priv->phy_mode); + return -EINVAL; + } + + ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, + PM_UFS_SRAM_CSR_WRITE, &sram_csr); + if (ret) + return ret; + + /* De Assert RST_UFS Reset for UFS block in PMX_IOU */ + ret = reset_deassert(priv->rstc); + if (ret) + dev_err(hba->dev, "ufshc reset deassert failed, err = %d\n", ret); + + break; + case POST_CHANGE: + ret = ufs_versal2_phy_init(hba); + if (ret) + dev_err(hba->dev, "Phy init failed (%d)\n", ret); + + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int ufs_versal2_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); + int ret = 0; + + switch (status) { + case PRE_CHANGE: + if (priv->host_clk) { + u32 core_clk_div = priv->host_clk / TIMEOUT_MICROSEC; + + ufshcd_writel(hba, core_clk_div, DWC_UFS_REG_HCLKDIV); + } + break; + case POST_CHANGE: + ret = ufshcd_dwc_link_startup_notify(hba, status); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static struct ufs_hba_ops ufs_versal2_hba_ops = { + .init = ufs_versal2_init, + .link_startup_notify = ufs_versal2_link_startup_notify, + .hce_enable_notify = ufs_versal2_hce_enable_notify, +}; + +static int ufs_versal2_probe(struct udevice *dev) +{ + int ret; + + /* Perform generic probe */ + ret = ufshcd_probe(dev, &ufs_versal2_hba_ops); + if (ret) + dev_err(dev, "ufshcd_probe() failed %d\n", ret); + + return ret; +} + +static int ufs_versal2_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + + return ufs_scsi_bind(dev, &scsi_dev); +} + +static const struct udevice_id ufs_versal2_ids[] = { + { + .compatible = "amd,versal2-ufs", + }, + {}, +}; + +U_BOOT_DRIVER(ufs_versal2_pltfm) = { + .name = "ufs-versal2-pltfm", + .id = UCLASS_UFS, + .of_match = ufs_versal2_ids, + .probe = ufs_versal2_probe, + .bind = ufs_versal2_bind, +}; diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c new file mode 100644 index 00000000000..843585726c7 --- /dev/null +++ b/drivers/ufs/ufs-qcom.c @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. + * Copyright (C) 2023-2024 Linaro Limited + * Authors: + * - Bhupesh Sharma <bhupesh.sharma@linaro.org> + * - Neil Armstrong <neil.armstrong@linaro.org> + * + * Based on Linux driver + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <generic-phy.h> +#include <ufs.h> +#include <asm/gpio.h> + +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> + +#include "ufs.h" +#include "ufs-qcom.h" + +#define ceil(freq, div) ((freq) % (div) == 0 ? ((freq) / (div)) : ((freq) / (div) + 1)) + +static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable); + +static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv) +{ + int err; + + if (priv->is_clks_enabled) + return 0; + + err = clk_enable_bulk(&priv->clks); + if (err) + return err; + + priv->is_clks_enabled = true; + + return 0; +} + +static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv) +{ + int err; + struct udevice *dev = priv->hba->dev; + + err = clk_get_bulk(dev, &priv->clks); + if (err) + return err; + + return 0; +} + +static int ufs_qcom_check_hibern8(struct ufs_hba *hba) +{ + int err, retry_count = 50; + u32 tx_fsm_val = 0; + + do { + err = ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), + &tx_fsm_val); + if (err || tx_fsm_val == TX_FSM_HIBERN8) + break; + + /* max. 200us */ + udelay(200); + retry_count--; + } while (retry_count != 0); + + /* Check the state again */ + err = ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), + &tx_fsm_val); + + if (err) { + dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", + __func__, err); + } else if (tx_fsm_val != TX_FSM_HIBERN8) { + err = tx_fsm_val; + dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", + __func__, err); + } + + return err; +} + +static void ufs_qcom_select_unipro_mode(struct ufs_qcom_priv *priv) +{ + ufshcd_rmwl(priv->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); + + if (priv->hw_ver.major >= 0x05) + ufshcd_rmwl(priv->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); +} + +/* + * ufs_qcom_reset - reset host controller and PHY + */ +static int ufs_qcom_reset(struct ufs_hba *hba) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + int ret; + + ret = reset_assert(&priv->core_reset); + if (ret) { + dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", + __func__, ret); + return ret; + } + + /* + * The hardware requirement for delay between assert/deassert + * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to + * ~125us (4/32768). To be on the safe side add 200us delay. + */ + udelay(210); + + ret = reset_deassert(&priv->core_reset); + if (ret) + dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", + __func__, ret); + + udelay(1100); + + return 0; +} + +/** + * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks + * @hba: host controller instance + * + * QCOM UFS host controller might have some non standard behaviours (quirks) + * than what is specified by UFSHCI specification. Advertise all such + * quirks to standard UFS host controller driver so standard takes them into + * account. + */ +static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + + if (priv->hw_ver.major == 0x2) + hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; + + if (priv->hw_ver.major > 0x3) + hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; +} + +/** + * ufs_qcom_setup_clocks - enables/disable clocks + * @hba: host controller instance + * @on: If true, enable clocks else disable them. + * @status: PRE_CHANGE or POST_CHANGE notify + * + * Returns 0 on success, non-zero on failure. + */ +static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, + enum ufs_notify_change_status status) +{ + switch (status) { + case PRE_CHANGE: + if (!on) + /* disable device ref_clk */ + ufs_qcom_dev_ref_clk_ctrl(hba, false); + break; + case POST_CHANGE: + if (on) + /* enable the device ref clock for HS mode*/ + ufs_qcom_dev_ref_clk_ctrl(hba, true); + break; + } + + return 0; +} + +static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + + /* + * TOFIX: v4 controllers *should* be able to support HS Gear 4 + * but so far pwr_mode switch is failing on v4 controllers and HS Gear 4. + * only enable HS Gear > 3 for Controlers major version 5 and later. + */ + if (priv->hw_ver.major > 0x4) + return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); + + /* Default is HS-G3 */ + return UFS_HS_G3; +} + +static int ufs_get_max_pwr_mode(struct ufs_hba *hba, + struct ufs_pwr_mode_info *max_pwr_info) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + u32 max_gear = ufs_qcom_get_hs_gear(hba); + + max_pwr_info->info.gear_rx = min(max_pwr_info->info.gear_rx, max_gear); + /* Qualcomm UFS only support symmetric Gear */ + max_pwr_info->info.gear_tx = max_pwr_info->info.gear_rx; + + if (priv->hw_ver.major >= 0x4 && max_pwr_info->info.gear_rx > UFS_HS_G3) + ufshcd_dme_set(hba, + UIC_ARG_MIB(PA_TXHSADAPTTYPE), + PA_INITIAL_ADAPT); + + dev_info(hba->dev, "Max HS Gear: %d\n", max_pwr_info->info.gear_rx); + + return 0; +} + +static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + struct phy phy; + int ret; + + /* Reset UFS Host Controller and PHY */ + ret = ufs_qcom_reset(hba); + if (ret) + dev_warn(hba->dev, "%s: host reset returned %d\n", + __func__, ret); + + /* get phy */ + ret = generic_phy_get_by_name(hba->dev, "ufsphy", &phy); + if (ret) { + dev_warn(hba->dev, "%s: Unable to get QMP ufs phy, ret = %d\n", + __func__, ret); + return ret; + } + + /* phy initialization */ + ret = generic_phy_init(&phy); + if (ret) { + dev_err(hba->dev, "%s: phy init failed, ret = %d\n", + __func__, ret); + return ret; + } + + /* power on phy */ + ret = generic_phy_power_on(&phy); + if (ret) { + dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", + __func__, ret); + goto out_disable_phy; + } + + ufs_qcom_select_unipro_mode(priv); + + return 0; + +out_disable_phy: + generic_phy_exit(&phy); + + return ret; +} + +/* + * The UTP controller has a number of internal clock gating cells (CGCs). + * Internal hardware sub-modules within the UTP controller control the CGCs. + * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved + * in a specific operation, UTP controller CGCs are by default disabled and + * this function enables them (after every UFS link startup) to save some power + * leakage. + */ +static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) +{ + ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, + REG_UFS_CFG2); + + /* Ensure that HW clock gating is enabled before next operations */ + ufshcd_readl(hba, REG_UFS_CFG2); +} + +static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + int err; + + switch (status) { + case PRE_CHANGE: + ufs_qcom_power_up_sequence(hba); + /* + * The PHY PLL output is the source of tx/rx lane symbol + * clocks, hence, enable the lane clocks only after PHY + * is initialized. + */ + err = ufs_qcom_enable_clks(priv); + break; + case POST_CHANGE: + /* check if UFS PHY moved from DISABLED to HIBERN8 */ + err = ufs_qcom_check_hibern8(hba); + ufs_qcom_enable_hw_clk_gating(hba); + break; + default: + dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); + err = -EINVAL; + break; + } + + return err; +} + +/* Look for the maximum core_clk_unipro clock value */ +static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + ofnode node = dev_ofnode(priv->hba->dev); + struct ofnode_phandle_args opp_table; + int pos, ret; + u32 clk = 0; + + /* Get core_clk_unipro clock index */ + pos = ofnode_stringlist_search(node, "clock-names", "core_clk_unipro"); + if (pos < 0) + goto fallback; + + /* Try parsing the opps */ + if (!ofnode_parse_phandle_with_args(node, "required-opps", + NULL, 0, 0, &opp_table) && + ofnode_device_is_compatible(opp_table.node, "operating-points-v2")) { + ofnode opp_node; + + ofnode_for_each_subnode(opp_node, opp_table.node) { + u64 opp_clk; + /* opp-hw contains the OPP frequency */ + ret = ofnode_read_u64_index(opp_node, "opp-hz", pos, &opp_clk); + if (ret) + continue; + + /* We don't handle larger clock values, ignore */ + if (opp_clk > U32_MAX) + continue; + + /* Only keep the largest value */ + if (opp_clk > clk) + clk = opp_clk; + } + + /* If we get a valid clock, return it or check legacy*/ + if (clk) + return clk; + } + + /* Legacy freq-table-hz has a pair of u32 per clocks entry, min then max */ + if (!ofnode_read_u32_index(node, "freq-table-hz", pos * 2 + 1, &clk) && + clk > 0) + return clk; + +fallback: + /* default for backwards compatibility */ + return UNIPRO_CORE_CLK_FREQ_150_MHZ * 1000 * 1000; +}; + +static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, + u32 cycles_in_1us) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + u32 cycles_in_40ns; + int err; + u32 reg; + + /* + * UFS host controller V4.0.0 onwards needs to program + * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed + * frequency of unipro core clk of UFS host controller. + */ + if (priv->hw_ver.major < 4) + return 0; + + /* + * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not + * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will + * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware + * specification expect to be 16. Hence use exact hardware spec + * mandated value for cycles_in_40ns instead of calculating using + * generic formulae. + */ + switch (cycles_in_1us) { + case UNIPRO_CORE_CLK_FREQ_403_MHZ: + cycles_in_40ns = 16; + break; + case UNIPRO_CORE_CLK_FREQ_300_MHZ: + cycles_in_40ns = 12; + break; + case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: + cycles_in_40ns = 8; + break; + case UNIPRO_CORE_CLK_FREQ_150_MHZ: + cycles_in_40ns = 6; + break; + case UNIPRO_CORE_CLK_FREQ_100_MHZ: + cycles_in_40ns = 4; + break; + case UNIPRO_CORE_CLK_FREQ_75_MHZ: + cycles_in_40ns = 3; + break; + case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: + cycles_in_40ns = 2; + break; + default: + dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", + cycles_in_1us); + return -EINVAL; + } + + err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); + if (err) + return err; + + reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; + reg |= cycles_in_40ns; + + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); +} + +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + u32 core_clk_ctrl_reg; + u32 cycles_in_1us; + int err; + + cycles_in_1us = ceil(ufs_qcom_get_core_clk_unipro_max_freq(hba), + (1000 * 1000)); + err = ufshcd_dme_get(hba, + UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), + &core_clk_ctrl_reg); + if (err) + return err; + + /* Bit mask is different for UFS host controller V4.0.0 onwards */ + if (priv->hw_ver.major >= 4) { + core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; + core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); + } else { + core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; + core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); + } + + /* Clear CORE_CLK_DIV_EN */ + core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; + + err = ufshcd_dme_set(hba, + UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), + core_clk_ctrl_reg); + if (err) + return err; + + /* Configure unipro core clk 40ns attribute */ + return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); +} + +static u32 ufs_qcom_get_local_unipro_ver(struct ufs_hba *hba) +{ + /* HCI version 1.0 and 1.1 supports UniPro 1.41 */ + switch (hba->version) { + case UFSHCI_VERSION_10: + case UFSHCI_VERSION_11: + return UFS_UNIPRO_VER_1_41; + + case UFSHCI_VERSION_20: + case UFSHCI_VERSION_21: + default: + return UFS_UNIPRO_VER_1_6; + } +} + +static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int err = 0; + + switch (status) { + case PRE_CHANGE: + err = ufs_qcom_set_core_clk_ctrl(hba); + if (err) + dev_err(hba->dev, "cfg core clk ctrl failed\n"); + /* + * Some UFS devices (and may be host) have issues if LCC is + * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 + * before link startup which will make sure that both host + * and device TX LCC are disabled once link startup is + * completed. + */ + if (ufs_qcom_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) + err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); + + break; + default: + break; + } + + return err; +} + +static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + + if (enable ^ priv->is_dev_ref_clk_enabled) { + u32 temp = readl_relaxed(hba->mmio_base + REG_UFS_CFG1); + + if (enable) + temp |= BIT(26); + else + temp &= ~BIT(26); + + /* + * If we are here to disable this clock it might be immediately + * after entering into hibern8 in which case we need to make + * sure that device ref_clk is active for specific time after + * hibern8 enter. + */ + if (!enable) + udelay(10); + + writel_relaxed(temp, hba->mmio_base + REG_UFS_CFG1); + + /* + * Make sure the write to ref_clk reaches the destination and + * not stored in a Write Buffer (WB). + */ + readl(hba->mmio_base + REG_UFS_CFG1); + + /* + * If we call hibern8 exit after this, we need to make sure that + * device ref_clk is stable for at least 1us before the hibern8 + * exit command. + */ + if (enable) + udelay(1); + + priv->is_dev_ref_clk_enabled = enable; + } +} + +/** + * ufs_qcom_init - bind phy with controller + * @hba: host controller instance + * + * Powers up PHY enabling clocks and regulators. + * + * Returns -EPROBE_DEFER if binding fails, returns negative error + * on phy power up failure and returns zero on success. + */ +static int ufs_qcom_init(struct ufs_hba *hba) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + int err; + + priv->hba = hba; + + /* setup clocks */ + ufs_qcom_setup_clocks(hba, true, PRE_CHANGE); + + if (priv->hw_ver.major >= 0x4) + ufshcd_dme_set(hba, + UIC_ARG_MIB(PA_TXHSADAPTTYPE), + PA_NO_ADAPT); + + ufs_qcom_setup_clocks(hba, true, POST_CHANGE); + + ufs_qcom_get_controller_revision(hba, &priv->hw_ver.major, + &priv->hw_ver.minor, + &priv->hw_ver.step); + dev_info(hba->dev, "Qcom UFS HC version: %d.%d.%d\n", + priv->hw_ver.major, + priv->hw_ver.minor, + priv->hw_ver.step); + + err = ufs_qcom_init_clks(priv); + if (err) { + dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err); + return err; + } + + ufs_qcom_advertise_quirks(hba); + ufs_qcom_setup_clocks(hba, true, POST_CHANGE); + + return 0; +} + +/** + * ufs_qcom_device_reset() - toggle the (optional) device reset line + * @hba: per-adapter instance + * + * Toggles the (optional) reset line to reset the attached device. + */ +static int ufs_qcom_device_reset(struct ufs_hba *hba) +{ + struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + + if (!dm_gpio_is_valid(&priv->reset)) + return 0; + + /* + * The UFS device shall detect reset pulses of 1us, sleep for 10us to + * be on the safe side. + */ + dm_gpio_set_value(&priv->reset, true); + udelay(10); + + dm_gpio_set_value(&priv->reset, false); + udelay(10); + + return 0; +} + +static struct ufs_hba_ops ufs_qcom_hba_ops = { + .init = ufs_qcom_init, + .get_max_pwr_mode = ufs_get_max_pwr_mode, + .hce_enable_notify = ufs_qcom_hce_enable_notify, + .link_startup_notify = ufs_qcom_link_startup_notify, + .device_reset = ufs_qcom_device_reset, +}; + +static int ufs_qcom_probe(struct udevice *dev) +{ + struct ufs_qcom_priv *priv = dev_get_priv(dev); + int ret; + + /* get resets */ + ret = reset_get_by_name(dev, "rst", &priv->core_reset); + if (ret) { + dev_err(dev, "failed to get reset, ret:%d\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "Warning: cannot get reset GPIO\n"); + } + + ret = ufshcd_probe(dev, &ufs_qcom_hba_ops); + if (ret) { + dev_err(dev, "ufshcd_probe() failed, ret:%d\n", ret); + return ret; + } + + return 0; +} + +static int ufs_qcom_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + + return ufs_scsi_bind(dev, &scsi_dev); +} + +static const struct udevice_id ufs_qcom_ids[] = { + { .compatible = "qcom,ufshc" }, + {}, +}; + +U_BOOT_DRIVER(qcom_ufshcd) = { + .name = "qcom-ufshcd", + .id = UCLASS_UFS, + .of_match = ufs_qcom_ids, + .probe = ufs_qcom_probe, + .bind = ufs_qcom_bind, + .priv_auto = sizeof(struct ufs_qcom_priv), +}; diff --git a/drivers/ufs/ufs-qcom.h b/drivers/ufs/ufs-qcom.h new file mode 100644 index 00000000000..de957ae60f3 --- /dev/null +++ b/drivers/ufs/ufs-qcom.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + */ + +#ifndef UFS_QCOM_H_ +#define UFS_QCOM_H_ + +#include <reset.h> +#include <linux/bitfield.h> + +#define MPHY_TX_FSM_STATE 0x41 +#define TX_FSM_HIBERN8 0x1 +#define DEFAULT_CLK_RATE_HZ 1000000 + +#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) +#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) +#define UFS_HW_VER_STEP_MASK GENMASK(15, 0) + +/* QCOM UFS host controller vendor specific registers */ +enum { + REG_UFS_SYS1CLK_1US = 0xC0, + REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4, + REG_UFS_LOCAL_PORT_ID_REG = 0xC8, + REG_UFS_PA_ERR_CODE = 0xCC, + /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ + REG_UFS_PARAM0 = 0xD0, + /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */ + REG_UFS_CFG0 = 0xD8, + REG_UFS_CFG1 = 0xDC, + REG_UFS_CFG2 = 0xE0, + REG_UFS_HW_VERSION = 0xE4, + + UFS_TEST_BUS = 0xE8, + UFS_TEST_BUS_CTRL_0 = 0xEC, + UFS_TEST_BUS_CTRL_1 = 0xF0, + UFS_TEST_BUS_CTRL_2 = 0xF4, + UFS_UNIPRO_CFG = 0xF8, + + /* + * QCOM UFS host controller vendor specific registers + * added in HW Version 3.0.0 + */ + UFS_AH8_CFG = 0xFC, + + REG_UFS_CFG3 = 0x271C, +}; + +/* bit definitions for REG_UFS_CFG0 register */ +#define QUNIPRO_G4_SEL BIT(5) + +/* bit definitions for REG_UFS_CFG1 register */ +#define QUNIPRO_SEL BIT(0) +#define UFS_PHY_SOFT_RESET BIT(1) +#define UTP_DBG_RAMS_EN BIT(17) +#define TEST_BUS_EN BIT(18) +#define TEST_BUS_SEL GENMASK(22, 19) +#define UFS_REG_TEST_BUS_EN BIT(30) + +#define UFS_PHY_RESET_ENABLE 1 +#define UFS_PHY_RESET_DISABLE 0 + +/* bit definitions for REG_UFS_CFG2 register */ +#define UAWM_HW_CGC_EN BIT(0) +#define UARM_HW_CGC_EN BIT(1) +#define TXUC_HW_CGC_EN BIT(2) +#define RXUC_HW_CGC_EN BIT(3) +#define DFC_HW_CGC_EN BIT(4) +#define TRLUT_HW_CGC_EN BIT(5) +#define TMRLUT_HW_CGC_EN BIT(6) +#define OCSC_HW_CGC_EN BIT(7) + +/* bit definitions for REG_UFS_PARAM0 */ +#define MAX_HS_GEAR_MASK GENMASK(6, 4) +#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) + +/* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ +#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ + +#define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ + TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ + DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\ + TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) + +/* bit offset */ +#define OFFSET_CLK_NS_REG 0xa + +/* bit masks */ +#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0) +#define MASK_CLK_NS_REG GENMASK(23, 10) + +/* QUniPro Vendor specific attributes */ +#define PA_VS_CONFIG_REG1 0x9000 +#define DME_VS_CORE_CLK_CTRL 0xD002 +/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ +#define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16) +#define CLK_1US_CYCLES_MASK GENMASK(7, 0) +#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) +#define PA_VS_CORE_CLK_40NS_CYCLES 0x9007 +#define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0) + +/* QCOM UFS host controller core clk frequencies */ +#define UNIPRO_CORE_CLK_FREQ_37_5_MHZ 38 +#define UNIPRO_CORE_CLK_FREQ_75_MHZ 75 +#define UNIPRO_CORE_CLK_FREQ_100_MHZ 100 +#define UNIPRO_CORE_CLK_FREQ_150_MHZ 150 +#define UNIPRO_CORE_CLK_FREQ_300_MHZ 300 +#define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202 +#define UNIPRO_CORE_CLK_FREQ_403_MHZ 403 + +static inline void +ufs_qcom_get_controller_revision(struct ufs_hba *hba, + u8 *major, u16 *minor, u16 *step) +{ + u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); + + *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); + *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); + *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver); +}; + +/* Host controller hardware version: major.minor.step */ +struct ufs_hw_version { + u16 step; + u16 minor; + u8 major; +}; + +struct gpio_desc; + +struct ufs_qcom_priv { + struct phy *generic_phy; + struct ufs_hba *hba; + + struct clk_bulk clks; + bool is_clks_enabled; + + struct ufs_hw_version hw_ver; + + /* Reset control of HCI */ + struct reset_ctl core_reset; + + struct gpio_desc reset; + + bool is_dev_ref_clk_enabled; +}; + +#endif /* UFS_QCOM_H_ */ diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index be64bf971f1..f7d8c40c448 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -125,6 +125,11 @@ static void ufshcd_print_pwr_info(struct ufs_hba *hba) hba->pwr_info.hs_rate); } +static void ufshcd_device_reset(struct ufs_hba *hba) +{ + ufshcd_vops_device_reset(hba); +} + /** * ufshcd_ready_for_uic_cmd - Check if controller is ready * to accept UIC commands @@ -433,6 +438,12 @@ static int ufshcd_make_hba_operational(struct ufs_hba *hba) REG_UTP_TASK_REQ_LIST_BASE_H); /* + * Make sure base address and interrupt setup are updated before + * enabling the run/stop registers below. + */ + wmb(); + + /* * UCRDY, UTMRLDY and UTRLRDY bits must be 1 */ reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); @@ -456,9 +467,7 @@ static int ufshcd_link_startup(struct ufs_hba *hba) { int ret; int retries = DME_LINKSTARTUP_RETRIES; - bool link_startup_again = true; -link_startup: do { ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); @@ -484,12 +493,6 @@ link_startup: /* failed to get the link up... retire */ goto out; - if (link_startup_again) { - link_startup_again = false; - retries = DME_LINKSTARTUP_RETRIES; - goto link_startup; - } - /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ ufshcd_init_pwr_info(hba); @@ -504,6 +507,8 @@ link_startup: if (ret) goto out; + /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ + ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); ret = ufshcd_make_hba_operational(hba); out: if (ret) @@ -633,7 +638,9 @@ static int ufshcd_memory_alloc(struct ufs_hba *hba) /* Allocate one Transfer Request Descriptor * Should be aligned to 1k boundary. */ - hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc)); + hba->utrdl = memalign(1024, + ALIGN(sizeof(struct utp_transfer_req_desc), + ARCH_DMA_MINALIGN)); if (!hba->utrdl) { dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n"); return -ENOMEM; @@ -642,7 +649,9 @@ static int ufshcd_memory_alloc(struct ufs_hba *hba) /* Allocate one Command Descriptor * Should be aligned to 1k boundary. */ - hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc)); + hba->ucdl = memalign(1024, + ALIGN(sizeof(struct utp_transfer_cmd_desc), + ARCH_DMA_MINALIGN)); if (!hba->ucdl) { dev_err(hba->dev, "Command descriptor memory allocation failed\n"); return -ENOMEM; @@ -692,18 +701,29 @@ static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) } /** - * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache + * ufshcd_cache_flush - Flush cache + * + * Flush cache in aligned address..address+size range. + */ +static void ufshcd_cache_flush(void *addr, unsigned long size) +{ + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + size, ARCH_DMA_MINALIGN); + + flush_dcache_range(start_addr, end_addr); +} + +/** + * ufshcd_cache_invalidate - Invalidate cache * - * Flush and invalidate cache in aligned address..address+size range. - * The invalidation is in place to avoid stale data in cache. + * Invalidate cache in aligned address..address+size range. */ -static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) +static void ufshcd_cache_invalidate(void *addr, unsigned long size) { - uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); - unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + size, ARCH_DMA_MINALIGN); - flush_dcache_range(aaddr, aaddr + asize); - invalidate_dcache_range(aaddr, aaddr + asize); + invalidate_dcache_range(start_addr, end_addr); } /** @@ -750,7 +770,7 @@ static void ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, req_desc->prd_table_length = 0; - ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); + ufshcd_cache_flush(req_desc, sizeof(*req_desc)); } static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, @@ -781,13 +801,13 @@ static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, /* Copy the Descriptor */ if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) { memcpy(ucd_req_ptr + 1, query->descriptor, len); - ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 2 * sizeof(*ucd_req_ptr)); + ufshcd_cache_flush(ucd_req_ptr, 2 * sizeof(*ucd_req_ptr)); } else { - ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); + ufshcd_cache_flush(ucd_req_ptr, sizeof(*ucd_req_ptr)); } memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); - ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); + ufshcd_cache_flush(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); } static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) @@ -805,8 +825,8 @@ static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); - ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); - ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); + ufshcd_cache_flush(ucd_req_ptr, sizeof(*ucd_req_ptr)); + ufshcd_cache_flush(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); } /** @@ -844,6 +864,9 @@ static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); + /* Make sure doorbell reg is updated before reading interrupt status */ + wmb(); + start = get_timer(0); do { intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); @@ -873,6 +896,8 @@ static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) */ static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) { + ufshcd_cache_invalidate(ucd_rsp_ptr, sizeof(*ucd_rsp_ptr)); + return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; } @@ -884,6 +909,8 @@ static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba) { struct utp_transfer_req_desc *req_desc = hba->utrdl; + ufshcd_cache_invalidate(req_desc, sizeof(*req_desc)); + return le32_to_cpu(req_desc->header.dword_2) & MASK_OCS; } @@ -1433,8 +1460,8 @@ void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len); memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); - ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); - ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); + ufshcd_cache_flush(ucd_req_ptr, sizeof(*ucd_req_ptr)); + ufshcd_cache_flush(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); } static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, @@ -1449,7 +1476,6 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) { struct utp_transfer_req_desc *req_desc = hba->utrdl; struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr; - uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1); ulong datalen = pccb->datalen; int table_length; u8 *buf; @@ -1457,19 +1483,10 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) if (!datalen) { req_desc->prd_table_length = 0; - ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); + ufshcd_cache_flush(req_desc, sizeof(*req_desc)); return; } - if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ - flush_dcache_range(aaddr, aaddr + - ALIGN(datalen, ARCH_DMA_MINALIGN)); - } - - /* In any case, invalidate cache to avoid stale data in it. */ - invalidate_dcache_range(aaddr, aaddr + - ALIGN(datalen, ARCH_DMA_MINALIGN)); - table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); buf = pccb->pdata; i = table_length; @@ -1483,8 +1500,8 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); req_desc->prd_table_length = table_length; - ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length); - ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); + ufshcd_cache_flush(prd_table, sizeof(*prd_table) * table_length); + ufshcd_cache_flush(req_desc, sizeof(*req_desc)); } static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) @@ -1498,8 +1515,12 @@ static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags); prepare_prdt_table(hba, pccb); + ufshcd_cache_flush(pccb->pdata, pccb->datalen); + ufshcd_send_command(hba, TASK_TAG); + ufshcd_cache_invalidate(pccb->pdata, pccb->datalen); + ocs = ufshcd_get_tr_ocs(hba); switch (ocs) { case OCS_SUCCESS: @@ -1723,7 +1744,7 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) } hba->max_pwr_info.is_valid = true; - return 0; + return ufshcd_ops_get_max_pwr_mode(hba, &hba->max_pwr_info); } static int ufshcd_change_power_mode(struct ufs_hba *hba, @@ -1901,7 +1922,7 @@ int ufs_start(struct ufs_hba *hba) return ret; } - printf("Device at %s up at:", hba->dev->name); + debug("UFS Device %s is up!\n", hba->dev->name); ufshcd_print_pwr_info(hba); } @@ -1953,7 +1974,8 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) hba->version != UFSHCI_VERSION_20 && hba->version != UFSHCI_VERSION_21 && hba->version != UFSHCI_VERSION_30 && - hba->version != UFSHCI_VERSION_31) + hba->version != UFSHCI_VERSION_31 && + hba->version != UFSHCI_VERSION_40) dev_err(hba->dev, "invalid UFS version 0x%x\n", hba->version); @@ -1979,6 +2001,11 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) REG_INTERRUPT_STATUS); ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); + mb(); + + /* Reset the attached device */ + ufshcd_device_reset(hba); + err = ufshcd_hba_enable(hba); if (err) { dev_err(hba->dev, "Host controller enable failed\n"); diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index 43042c294bb..00ecca350c3 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -3,6 +3,7 @@ #define __UFS_H #include <linux/types.h> +#include <asm/io.h> #include "unipro.h" struct udevice; @@ -695,11 +696,177 @@ struct ufs_dev_cmd { struct ufs_hba_ops { int (*init)(struct ufs_hba *hba); + int (*get_max_pwr_mode)(struct ufs_hba *hba, + struct ufs_pwr_mode_info *max_pwr_info); int (*hce_enable_notify)(struct ufs_hba *hba, enum ufs_notify_change_status); int (*link_startup_notify)(struct ufs_hba *hba, enum ufs_notify_change_status); int (*phy_initialization)(struct ufs_hba *hba); + int (*device_reset)(struct ufs_hba *hba); +}; + +enum ufshcd_quirks { + /* Interrupt aggregation support is broken */ + UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, + + /* + * delay before each dme command is required as the unipro + * layer has shown instabilities + */ + UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, + + /* + * If UFS host controller is having issue in processing LCC (Line + * Control Command) coming from device then enable this quirk. + * When this quirk is enabled, host controller driver should disable + * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE + * attribute of device to 0). + */ + UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, + + /* + * The attribute PA_RXHSUNTERMCAP specifies whether or not the + * inbound Link supports unterminated line in HS mode. Setting this + * attribute to 1 fixes moving to HS gear. + */ + UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, + + /* + * This quirk needs to be enabled if the host controller only allows + * accessing the peer dme attributes in AUTO mode (FAST AUTO or + * SLOW AUTO). + */ + UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, + + /* + * This quirk needs to be enabled if the host controller doesn't + * advertise the correct version in UFS_VER register. If this quirk + * is enabled, standard UFS host driver will call the vendor specific + * ops (get_ufs_hci_version) to get the correct version. + */ + UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, + + /* + * Clear handling for transfer/task request list is just opposite. + */ + UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, + + /* + * This quirk needs to be enabled if host controller doesn't allow + * that the interrupt aggregation timer and counter are reset by s/w. + */ + UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, + + /* + * This quirks needs to be enabled if host controller cannot be + * enabled via HCE register. + */ + UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, + + /* + * This quirk needs to be enabled if the host controller regards + * resolution of the values of PRDTO and PRDTL in UTRD as byte. + */ + UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, + + /* + * This quirk needs to be enabled if the host controller reports + * OCS FATAL ERROR with device error through sense data + */ + UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, + + /* + * This quirk needs to be enabled if the host controller has + * auto-hibernate capability but it doesn't work. + */ + UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, + + /* + * This quirk needs to disable manual flush for write booster + */ + UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, + + /* + * This quirk needs to disable unipro timeout values + * before power mode change + */ + UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, + + /* + * This quirk needs to be enabled if the host controller does not + * support UIC command + */ + UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, + + /* + * This quirk needs to be enabled if the host controller cannot + * support physical host configuration. + */ + UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, + + /* + * This quirk needs to be enabled if the host controller has + * 64-bit addressing supported capability but it doesn't work. + */ + UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, + + /* + * This quirk needs to be enabled if the host controller has + * auto-hibernate capability but it's FASTAUTO only. + */ + UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, + + /* + * This quirk needs to be enabled if the host controller needs + * to reinit the device after switching to maximum gear. + */ + UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, + + /* + * Some host raises interrupt (per queue) in addition to + * CQES (traditional) when ESI is disabled. + * Enable this quirk will disable CQES and use per queue interrupt. + */ + UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, + + /* + * Some host does not implement SQ Run Time Command (SQRTC) register + * thus need this quirk to skip related flow. + */ + UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, + + /* + * This quirk needs to be enabled if the host controller supports inline + * encryption but it needs to initialize the crypto capabilities in a + * nonstandard way and/or needs to override blk_crypto_ll_ops. If + * enabled, the standard code won't initialize the blk_crypto_profile; + * ufs_hba_variant_ops::init() must do it instead. + */ + UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22, + + /* + * This quirk needs to be enabled if the host controller supports inline + * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e. + * host controller initialization fails if that bit is set. + */ + UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23, + + /* + * This quirk needs to be enabled if the host controller driver copies + * cryptographic keys into the PRDT in order to send them to hardware, + * and therefore the PRDT should be zeroized after each request (as per + * the standard best practice for managing keys). + */ + UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24, + + /* + * This quirk indicates that the controller reports the value 1 (not + * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the + * Controller Capabilities register although it supports the legacy + * single doorbell mode. + */ + UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25, }; struct ufs_hba { @@ -710,27 +877,7 @@ struct ufs_hba { u32 capabilities; u32 version; u32 intr_mask; - u32 quirks; -/* - * If UFS host controller is having issue in processing LCC (Line - * Control Command) coming from device then enable this quirk. - * When this quirk is enabled, host controller driver should disable - * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE - * attribute of device to 0). - */ -#define UFSHCD_QUIRK_BROKEN_LCC BIT(0) - -/* - * This quirk needs to be enabled if the host controller has - * 64-bit addressing supported capability but it doesn't work. - */ -#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS BIT(1) - -/* - * This quirk needs to be enabled if the host controller has - * auto-hibernate capability but it's FASTAUTO only. - */ -#define UFSHCD_QUIRK_HIBERN_FASTAUTO BIT(2) + enum ufshcd_quirks quirks; /* Virtual memory reference */ struct utp_transfer_cmd_desc *ucdl; @@ -758,6 +905,15 @@ static inline int ufshcd_ops_init(struct ufs_hba *hba) return 0; } +static inline int ufshcd_ops_get_max_pwr_mode(struct ufs_hba *hba, + struct ufs_pwr_mode_info *max_pwr_info) +{ + if (hba->ops && hba->ops->get_max_pwr_mode) + return hba->ops->get_max_pwr_mode(hba, max_pwr_info); + + return 0; +} + static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba, bool status) { @@ -776,6 +932,14 @@ static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba, return 0; } +static inline int ufshcd_vops_device_reset(struct ufs_hba *hba) +{ + if (hba->ops && hba->ops->device_reset) + return hba->ops->device_reset(hba); + + return 0; +} + /* Controller UFSHCI version */ enum { UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ @@ -784,6 +948,7 @@ enum { UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */ UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */ + UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */ }; /* Interrupt disable masks */ @@ -921,6 +1086,23 @@ enum { #define ufshcd_readl(hba, reg) \ readl((hba)->mmio_base + (reg)) +/** + * ufshcd_rmwl - perform read/modify/write for a controller register + * @hba: per adapter instance + * @mask: mask to apply on read value + * @val: actual value to write + * @reg: register address + */ +static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) +{ + u32 tmp; + + tmp = ufshcd_readl(hba, reg); + tmp &= ~mask; + tmp |= (val & mask); + ufshcd_writel(hba, tmp, reg); +} + /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 diff --git a/drivers/ufs/ufshcd-dwc.c b/drivers/ufs/ufshcd-dwc.c new file mode 100644 index 00000000000..3f62e59a060 --- /dev/null +++ b/drivers/ufs/ufshcd-dwc.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UFS Host driver for Synopsys Designware Core + * + * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) + * + */ +#include <clk.h> +#include <dm.h> +#include <ufs.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/time.h> + +#include "ufs.h" +#include "ufshci-dwc.h" +#include "ufshcd-dwc.h" + +int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, + const struct ufshcd_dme_attr_val *v, int n) +{ + int ret = 0; + int attr_node = 0; + + for (attr_node = 0; attr_node < n; attr_node++) { + ret = ufshcd_dme_set_attr(hba, v[attr_node].attr_sel, + ATTR_SET_NOR, v[attr_node].mib_val, v[attr_node].peer); + if (ret) + return ret; + } + + return 0; +} + +/** + * ufshcd_dwc_program_clk_div() - program clock divider. + * @hba: Private Structure pointer + * @divider_val: clock divider value to be programmed + * + */ +static void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val) +{ + ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV); +} + +/** + * ufshcd_dwc_link_is_up() - check if link is up. + * @hba: private structure pointer + * + * Return: 0 on success, non-zero value on failure. + */ +static int ufshcd_dwc_link_is_up(struct ufs_hba *hba) +{ + int dme_result = 0; + + ufshcd_dme_get(hba, UIC_ARG_MIB(VS_POWERSTATE), &dme_result); + + if (dme_result == UFSHCD_LINK_IS_UP) + return 0; + + return 1; +} + +/** + * ufshcd_dwc_connection_setup() - configure unipro attributes. + * @hba: pointer to drivers private data + * + * This function configures both the local side (host) and the peer side + * (device) unipro attributes to establish the connection to application/ + * cport. + * This function is not required if the hardware is properly configured to + * have this connection setup on reset. But invoking this function does no + * harm and should be fine even working with any ufs device. + * + * Return: 0 on success non-zero value on failure. + */ +static int ufshcd_dwc_connection_setup(struct ufs_hba *hba) +{ + static const struct ufshcd_dme_attr_val setup_attrs[] = { + { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_LOCAL }, + { UIC_ARG_MIB(N_DEVICEID), 0, DME_LOCAL }, + { UIC_ARG_MIB(N_DEVICEID_VALID), 0, DME_LOCAL }, + { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_LOCAL }, + { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_LOCAL }, + { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_LOCAL }, + { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_LOCAL }, + { UIC_ARG_MIB(T_CPORTMODE), 1, DME_LOCAL }, + { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_LOCAL }, + { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_PEER }, + { UIC_ARG_MIB(N_DEVICEID), 1, DME_PEER }, + { UIC_ARG_MIB(N_DEVICEID_VALID), 1, DME_PEER }, + { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_PEER }, + { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_PEER }, + { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_PEER }, + { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_PEER }, + { UIC_ARG_MIB(T_CPORTMODE), 1, DME_PEER }, + { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_PEER } + }; + return ufshcd_dwc_dme_set_attrs(hba, setup_attrs, ARRAY_SIZE(setup_attrs)); +} + +/** + * ufshcd_dwc_link_startup_notify() - program clock divider. + * @hba: private structure pointer + * @status: Callback notify status + * + * Return: 0 on success, non-zero value on failure. + */ +int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int err = 0; + + if (status == PRE_CHANGE) { + ufshcd_dwc_program_clk_div(hba, DWC_UFS_REG_HCLKDIV_DIV_125); + } else { /* POST_CHANGE */ + err = ufshcd_dwc_link_is_up(hba); + if (err) { + dev_err(hba->dev, "Link is not up\n"); + return err; + } + + err = ufshcd_dwc_connection_setup(hba); + if (err) + dev_err(hba->dev, "Connection setup failed (%d)\n", + err); + } + + return err; +} diff --git a/drivers/ufs/ufshcd-dwc.h b/drivers/ufs/ufshcd-dwc.h new file mode 100644 index 00000000000..fc1bcca8ccb --- /dev/null +++ b/drivers/ufs/ufshcd-dwc.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * UFS Host driver for Synopsys Designware Core + * + * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) + * + * Authors: Joao Pinto <jpinto@synopsys.com> + */ + +#ifndef _UFSHCD_DWC_H +#define _UFSHCD_DWC_H + +/* PHY modes */ +#define UFSHCD_DWC_PHY_MODE_ROM 0 + +/* RMMI Attributes */ +#define CBREFCLKCTRL2 0x8132 +#define CBCRCTRL 0x811F +#define CBC10DIRECTCONF2 0x810E +#define CBCREGADDRLSB 0x8116 +#define CBCREGADDRMSB 0x8117 +#define CBCREGWRLSB 0x8118 +#define CBCREGWRMSB 0x8119 +#define CBCREGRDLSB 0x811A +#define CBCREGRDMSB 0x811B +#define CBCREGRDWRSEL 0x811C + +#define CBREFREFCLK_GATE_OVR_EN BIT(7) + +/* M-PHY Attributes */ +#define MTX_FSM_STATE 0x41 +#define MRX_FSM_STATE 0xC1 + +/* M-PHY registers */ +#define FAST_FLAGS(n) (0x401C + ((n) * 0x100)) +#define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100)) +#define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100)) +#define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100)) + +/* Tx/Rx FSM state */ +enum rx_fsm_state { + RX_STATE_DISABLED = 0, + RX_STATE_HIBERN8 = 1, + RX_STATE_SLEEP = 2, + RX_STATE_STALL = 3, + RX_STATE_LSBURST = 4, + RX_STATE_HSBURST = 5, +}; + +enum tx_fsm_state { + TX_STATE_DISABLED = 0, + TX_STATE_HIBERN8 = 1, + TX_STATE_SLEEP = 2, + TX_STATE_STALL = 3, + TX_STATE_LSBURST = 4, + TX_STATE_HSBURST = 5, +}; + +struct ufshcd_dme_attr_val { + u32 attr_sel; + u32 mib_val; + u8 peer; +}; + +int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status); +int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, + const struct ufshcd_dme_attr_val *v, int n); +#endif /* End of Header */ diff --git a/drivers/ufs/ufshci-dwc.h b/drivers/ufs/ufshci-dwc.h new file mode 100644 index 00000000000..9e24c230c64 --- /dev/null +++ b/drivers/ufs/ufshci-dwc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * UFS Host driver for Synopsys Designware Core + * + * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) + * + * Authors: Joao Pinto <jpinto@synopsys.com> + */ + +#ifndef _UFSHCI_DWC_H +#define _UFSHCI_DWC_H + +/* DWC HC UFSHCI specific Registers */ +enum dwc_specific_registers { + DWC_UFS_REG_HCLKDIV = 0xFC, +}; + +/* Clock Divider Values: Hex equivalent of frequency in MHz */ +enum clk_div_values { + DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e, + DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d, + DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8, +}; + +/* Selector Index */ +enum selector_index { + SELIND_LN0_TX = 0x00, + SELIND_LN1_TX = 0x01, + SELIND_LN0_RX = 0x04, + SELIND_LN1_RX = 0x05, +}; +#endif diff --git a/drivers/ufs/unipro.h b/drivers/ufs/unipro.h index b30b17fa5ad..6df953e6e60 100644 --- a/drivers/ufs/unipro.h +++ b/drivers/ufs/unipro.h @@ -140,6 +140,12 @@ #define PA_SLEEPNOCONFIGTIME 0x15A2 #define PA_STALLNOCONFIGTIME 0x15A3 #define PA_SAVECONFIGTIME 0x15A4 +#define PA_TXHSADAPTTYPE 0x15D4 + +/* Adapt type for PA_TXHSADAPTTYPE attribute */ +#define PA_REFRESH_ADAPT 0x00 +#define PA_INITIAL_ADAPT 0x01 +#define PA_NO_ADAPT 0x03 #define PA_TACTIVATE_TIME_UNIT_US 10 #define PA_HIBERN8_TIME_UNIT_US 100 @@ -148,6 +154,7 @@ #define VS_MPHYCFGUPDT 0xD085 #define VS_DEBUGOMC 0xD09E #define VS_POWERSTATE 0xD083 +#define VS_MPHYDISABLE 0xD0C1 #define PA_GRANULARITY_MIN_VAL 1 #define PA_GRANULARITY_MAX_VAL 6 diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile index 18d7190755d..d6047856091 100644 --- a/drivers/usb/cdns3/Makefile +++ b/drivers/usb/cdns3/Makefile @@ -4,8 +4,8 @@ cdns3-y := core.o drd.o obj-$(CONFIG_USB_CDNS3) += cdns3.o -cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET) += gadget.o ep0.o +cdns3-$(CONFIG_$(XPL_)USB_CDNS3_GADGET) += gadget.o ep0.o -cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST) += host.o +cdns3-$(CONFIG_$(XPL_)USB_CDNS3_HOST) += host.o obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index cbe06a9e7b6..4cfd38ec245 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -149,7 +149,7 @@ static int cdns3_core_init_role(struct cdns3 *cdns) dr_mode = best_dr_mode; -#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_XPL_BUILD) if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { ret = cdns3_host_init(cdns); if (ret) { @@ -412,7 +412,7 @@ int cdns3_bind(struct udevice *parent) switch (dr_mode) { #if defined(CONFIG_SPL_USB_HOST) || \ - (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)) + (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST)) case USB_DR_MODE_HOST: debug("%s: dr_mode: HOST\n", __func__); driver = "cdns-usb3-host"; @@ -498,7 +498,7 @@ int dm_usb_gadget_handle_interrupts(struct udevice *dev) #endif #if defined(CONFIG_SPL_USB_HOST) || \ - (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)) + (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST)) static int cdns3_host_probe(struct udevice *dev) { struct cdns3_host_priv *priv = dev_get_priv(dev); diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile index 2e9353b76a6..11cc4657a0f 100644 --- a/drivers/usb/common/Makefile +++ b/drivers/usb/common/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2016 Freescale Semiconductor, Inc. # -obj-$(CONFIG_$(SPL_)DM_USB) += common.o +obj-$(CONFIG_$(XPL_)DM_USB) += common.o obj-$(CONFIG_USB_ISP1760) += usb_urb.o obj-$(CONFIG_USB_MUSB_HOST) += usb_urb.o obj-$(CONFIG_USB_MUSB_GADGET) += usb_urb.o diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index a46b6824ab7..a085c9d4628 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -6,11 +6,11 @@ dwc3-y := core.o obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o -obj-$(CONFIG_$(SPL_)USB_DWC3_AM62) += dwc3-am62.o +obj-$(CONFIG_$(XPL_)USB_DWC3_AM62) += dwc3-am62.o obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o -obj-$(CONFIG_$(SPL_)USB_DWC3_GENERIC) += dwc3-generic.o +obj-$(CONFIG_$(XPL_)USB_DWC3_GENERIC) += dwc3-generic.o obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index a9ba315463c..2ab41cbae45 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -246,12 +246,12 @@ static int dwc3_generic_host_probe(struct udevice *dev) return rc; rc = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply); - if (rc) + if (rc && rc != -ENOSYS) debug("%s: No vbus regulator found: %d\n", dev->name, rc); - /* Only returns an error if regulator is valid and failed to enable due to a driver issue */ + /* Does not return an error if regulator is invalid - but does so when DM_REGULATOR is disabled */ rc = regulator_set_enable_if_allowed(priv->vbus_supply, true); - if (rc) + if (rc && rc != -ENOSYS) return rc; hccr = (struct xhci_hccr *)priv->gen_priv.base; diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index da76b6524de..4bda224ff1a 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -3,11 +3,11 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_$(SPL_TPL_)USB_GADGET) += epautoconf.o config.o usbstring.o -obj-$(CONFIG_$(SPL_TPL_)USB_ETHER) += epautoconf.o config.o usbstring.o ether.o -obj-$(CONFIG_$(SPL_TPL_)USB_ETH_RNDIS) += rndis.o +obj-$(CONFIG_$(PHASE_)USB_GADGET) += epautoconf.o config.o usbstring.o +obj-$(CONFIG_$(PHASE_)USB_ETHER) += epautoconf.o config.o usbstring.o ether.o +obj-$(CONFIG_$(PHASE_)USB_ETH_RNDIS) += rndis.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_USB_GADGET) += g_dnl.o obj-$(CONFIG_SPL_DFU) += f_dfu.o obj-$(CONFIG_SPL_USB_SDP_SUPPORT) += f_sdp.o @@ -22,7 +22,7 @@ obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o obj-$(CONFIG_USB_RENESAS_USBHS) += rcar/ -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o obj-$(CONFIG_DFU_OVER_USB) += f_dfu.o diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 5d62eb475d0..36934b1bcf7 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -411,7 +411,7 @@ static void sdp_rx_data_complete(struct usb_ep *ep, struct usb_request *req) return; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD env_set_hex("filesize", sdp->dnl_bytes); #endif printf("done\n"); @@ -736,7 +736,7 @@ static u32 sdp_jump_imxheader(void *address) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static ulong sdp_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { @@ -825,7 +825,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, /* If imx header fails, try some U-Boot specific headers */ if (status) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) sdp_func->jmp_address = (u32)search_container_header((ulong)sdp_func->jmp_address, sdp_func->dnl_bytes); else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) @@ -907,7 +907,7 @@ static void sdp_handle_out_ep(void) } } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int sdp_handle(struct udevice *udc) #else int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image, @@ -928,7 +928,7 @@ int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image, schedule(); dm_usb_gadget_handle_interrupts(udc); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD flag = sdp_handle_in_ep(spl_image, bootdev); #else flag = sdp_handle_in_ep(NULL, NULL); diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile index 467c566f6d3..4b6a8fdfeee 100644 --- a/drivers/usb/gadget/udc/Makefile +++ b/drivers/usb/gadget/udc/Makefile @@ -2,9 +2,9 @@ # # USB peripheral controller drivers -ifndef CONFIG_$(SPL_)DM_USB_GADGET +ifndef CONFIG_$(XPL_)DM_USB_GADGET obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o endif -obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-core.o +obj-$(CONFIG_$(XPL_)DM_USB_GADGET) += udc-core.o obj-y += udc-uclass.o diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 8dad36f9369..792956e647a 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -3,13 +3,13 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_$(SPL_)DM_USB +ifdef CONFIG_$(XPL_)DM_USB obj-y += usb-uclass.o obj-$(CONFIG_SANDBOX) += usb-sandbox.o endif -ifdef CONFIG_$(SPL_TPL_)USB_STORAGE -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += usb_bootdev.o +ifdef CONFIG_$(PHASE_)USB_STORAGE +obj-$(CONFIG_$(PHASE_)BOOTSTD) += usb_bootdev.o endif # ohci diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 343893b9f19..7c73eb66b60 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -66,9 +66,24 @@ enum usb_ctlr_type { USB_CTRL_COUNT, }; +struct tegra_utmip_config { + u32 hssync_start_delay; + u32 elastic_limit; + u32 idle_wait_delay; + u32 term_range_adj; + bool xcvr_setup_use_fuses; + u32 xcvr_setup; + u32 xcvr_lsfslew; + u32 xcvr_lsrslew; + u32 xcvr_hsslew; + u32 hssquelch_level; + u32 hsdiscon_level; +}; + /* Information about a USB port */ struct fdt_usb { struct ehci_ctrl ehci; + struct tegra_utmip_config utmip_config; struct usb_ctlr *reg; /* address of registers in physical memory */ unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ @@ -192,15 +207,6 @@ static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 } }; -/* UTMIP Idle Wait Delay */ -static const u8 utmip_idle_wait_delay = 17; - -/* UTMIP Elastic limit */ -static const u8 utmip_elastic_limit = 16; - -/* UTMIP High Speed Sync Start Delay */ -static const u8 utmip_hs_sync_start_delay = 9; - struct fdt_usb_controller { /* flag to determine whether controller supports hostpc register */ u32 has_hostpc:1; @@ -377,6 +383,7 @@ static int init_utmi_usb_controller(struct fdt_usb *config, u32 b_sess_valid_mask, val; int loop_count; const unsigned *timing; + struct tegra_utmip_config *utmip_config = &config->utmip_config; struct usb_ctlr *usbctlr = config->reg; struct clk_rst_ctlr *clkrst; struct usb_ctlr *usb1ctlr; @@ -463,16 +470,29 @@ static int init_utmi_usb_controller(struct fdt_usb *config, /* Recommended PHY settings for EYE diagram */ val = readl(&usbctlr->utmip_xcvr_cfg0); - clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, - 0x4 << UTMIP_XCVR_SETUP_SHIFT); - clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, - 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); - clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, - 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); + + if (!utmip_config->xcvr_setup_use_fuses) { + clrsetbits_le32(&val, UTMIP_XCVR_SETUP(~0), + UTMIP_XCVR_SETUP(utmip_config->xcvr_setup)); + clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB(~0), + UTMIP_XCVR_SETUP_MSB(utmip_config->xcvr_setup)); + } + + clrsetbits_le32(&val, UTMIP_XCVR_LSFSLEW(~0), + UTMIP_XCVR_LSFSLEW(utmip_config->xcvr_lsfslew)); + clrsetbits_le32(&val, UTMIP_XCVR_LSRSLEW(~0), + UTMIP_XCVR_LSRSLEW(utmip_config->xcvr_lsrslew)); + + clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW(~0), + UTMIP_XCVR_HSSLEW(utmip_config->xcvr_hsslew)); + clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB(~0), + UTMIP_XCVR_HSSLEW_MSB(utmip_config->xcvr_hsslew)); writel(val, &usbctlr->utmip_xcvr_cfg0); + clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_XCVR_TERM_RANGE_ADJ_MASK, - 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); + utmip_config->term_range_adj << + UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); /* Some registers can be controlled from USB1 only. */ if (config->periph_id != PERIPH_ID_USBD) { @@ -485,9 +505,11 @@ static int init_utmi_usb_controller(struct fdt_usb *config, val = readl(&usb1ctlr->utmip_bias_cfg0); setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, - 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); + utmip_config->hsdiscon_level << + UTMIP_HSDISCON_LEVEL_SHIFT); clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, - 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); + utmip_config->hssquelch_level << + UTMIP_HSSQUELCH_LEVEL_SHIFT); writel(val, &usb1ctlr->utmip_bias_cfg0); /* Miscellaneous setting mentioned in Programming Guide */ @@ -521,7 +543,11 @@ static int init_utmi_usb_controller(struct fdt_usb *config, setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); - setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + + if (utmip_config->xcvr_setup_use_fuses) + setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + else + clrbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); /* * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT @@ -535,15 +561,16 @@ static int init_utmi_usb_controller(struct fdt_usb *config, /* Set PLL enable delay count and Crystal frequency count */ val = readl(&usbctlr->utmip_hsrx_cfg0); clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, - utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); + utmip_config->idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, - utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); + utmip_config->elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); writel(val, &usbctlr->utmip_hsrx_cfg0); /* Configure the UTMIP_HS_SYNC_START_DLY */ clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, UTMIP_HS_SYNC_START_DLY_MASK, - utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); + utmip_config->hssync_start_delay << + UTMIP_HS_SYNC_START_DLY_SHIFT); /* Preceed the crystal clock disable by >100ns delay. */ udelay(1); @@ -763,6 +790,69 @@ static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config) return 0; } +static void fdt_decode_usb_phy(struct udevice *dev) +{ + struct fdt_usb *priv = dev_get_priv(dev); + struct tegra_utmip_config *utmip_config = &priv->utmip_config; + u32 usb_phy_phandle; + ofnode usb_phy_node; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), "nvidia,phy", &usb_phy_phandle); + if (ret) + log_debug("%s: required usb phy node isn't provided\n", __func__); + + usb_phy_node = ofnode_get_by_phandle(usb_phy_phandle); + if (!ofnode_valid(usb_phy_node) || !ofnode_is_enabled(usb_phy_node)) { + log_debug("%s: failed to find usb phy node or it is disabled\n", __func__); + utmip_config->xcvr_setup_use_fuses = true; + } else { + utmip_config->xcvr_setup_use_fuses = + ofnode_read_bool(usb_phy_node, "nvidia,xcvr-setup-use-fuses"); + } + + utmip_config->hssync_start_delay = + ofnode_read_u32_default(usb_phy_node, + "nvidia,hssync-start-delay", 0x9); + + utmip_config->elastic_limit = + ofnode_read_u32_default(usb_phy_node, + "nvidia,elastic-limit", 0x10); + + utmip_config->idle_wait_delay = + ofnode_read_u32_default(usb_phy_node, + "nvidia,idle-wait-delay", 0x11); + + utmip_config->term_range_adj = + ofnode_read_u32_default(usb_phy_node, + "nvidia,term-range-adj", 0x7); + + utmip_config->xcvr_lsfslew = + ofnode_read_u32_default(usb_phy_node, + "nvidia,xcvr-lsfslew", 0x0); + + utmip_config->xcvr_lsrslew = + ofnode_read_u32_default(usb_phy_node, + "nvidia,xcvr-lsrslew", 0x3); + + utmip_config->xcvr_hsslew = + ofnode_read_u32_default(usb_phy_node, + "nvidia,xcvr-hsslew", 0x8); + + utmip_config->hssquelch_level = + ofnode_read_u32_default(usb_phy_node, + "nvidia,hssquelch-level", 0x2); + + utmip_config->hsdiscon_level = + ofnode_read_u32_default(usb_phy_node, + "nvidia,hsdiscon-level", 0x1); + + if (!utmip_config->xcvr_setup_use_fuses) { + ofnode_read_u32(usb_phy_node, "nvidia,xcvr-setup", + &utmip_config->xcvr_setup); + } +} + int usb_common_init(struct fdt_usb *config, enum usb_init_type init) { int ret = 0; @@ -850,6 +940,8 @@ static int ehci_usb_of_to_plat(struct udevice *dev) priv->type = dev_get_driver_data(dev); + fdt_decode_usb_phy(dev); + return 0; } diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c index f8e14eabfb2..26fee141f6e 100644 --- a/drivers/usb/mtu3/mtu3_plat.c +++ b/drivers/usb/mtu3/mtu3_plat.c @@ -266,7 +266,7 @@ U_BOOT_DRIVER(mtu3_peripheral) = { #endif #if defined(CONFIG_SPL_USB_HOST) || \ - (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)) + (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST)) static int mtu3_host_probe(struct udevice *dev) { struct ssusb_mtk *ssusb = dev_to_ssusb(dev->parent); @@ -334,7 +334,7 @@ static int mtu3_glue_bind(struct udevice *parent) #endif #if defined(CONFIG_SPL_USB_HOST) || \ - (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)) + (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST)) case USB_DR_MODE_HOST: dev_dbg(parent, "%s: dr_mode: host\n", __func__); driver = "mtu3-host"; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6e79694fd19..3c3cebaacd0 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -599,6 +599,15 @@ config VIDEO_LCD_SAMSUNG_LTL106HL02 LCD module found in Microsoft Surface 2. The panel has a FullHD resolution (1920x1080). +config VIDEO_LCD_SHARP_LQ101R1SX01 + tristate "Sharp LQ101R1SX01 2560x1600 DSI video mode panel" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for Sharp LQ101R1SX01 + LCD module found in ASUS Transformer TF701T. The panel has a + WQXGA resolution (2560x1600). + config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" ---help--- diff --git a/drivers/video/Makefile b/drivers/video/Makefile index f3f70cd04a1..5a00438ce06 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -4,12 +4,12 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. ifdef CONFIG_DM -obj-$(CONFIG_$(SPL_TPL_)BACKLIGHT) += backlight-uclass.o +obj-$(CONFIG_$(PHASE_)BACKLIGHT) += backlight-uclass.o obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o -obj-$(CONFIG_$(SPL_TPL_)CONSOLE_NORMAL) += console_normal.o +obj-$(CONFIG_$(PHASE_)CONSOLE_NORMAL) += console_normal.o obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o -ifdef CONFIG_$(SPL_TPL_)CONSOLE_NORMAL +ifdef CONFIG_$(PHASE_)CONSOLE_NORMAL obj-y += console_core.o else ifdef CONFIG_CONSOLE_ROTATION obj-y += console_core.o @@ -18,14 +18,14 @@ obj-$(CONFIG_CONSOLE_ROTATION) += console_core.o obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/ obj-$(CONFIG_DISPLAY) += display-uclass.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o -obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video-uclass.o vidconsole-uclass.o -obj-$(CONFIG_$(SPL_TPL_)VIDEO) += video_bmp.o -obj-$(CONFIG_$(SPL_TPL_)PANEL) += panel-uclass.o +obj-$(CONFIG_$(PHASE_)VIDEO) += video-uclass.o vidconsole-uclass.o +obj-$(CONFIG_$(PHASE_)VIDEO) += video_bmp.o +obj-$(CONFIG_$(PHASE_)PANEL) += panel-uclass.o obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o -obj-$(CONFIG_$(SPL_TPL_)SIMPLE_PANEL) += simple_panel.o +obj-$(CONFIG_$(PHASE_)SIMPLE_PANEL) += simple_panel.o obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.o -obj-$(CONFIG_$(SPL_TPL_)BMP) += bmp.o +obj-$(CONFIG_$(PHASE_)BMP) += bmp.o endif @@ -34,7 +34,7 @@ obj-${CONFIG_EXYNOS_FB} += exynos/ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/ obj-${CONFIG_VIDEO_STM32} += stm32/ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ -obj-${CONFIG_$(SPL_)VIDEO_TIDSS} += tidss/ +obj-${CONFIG_$(XPL_)VIDEO_TIDSS} += tidss/ obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o @@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o +obj-$(CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01) += sharp-lq101r1sx01.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index c435162d3f9..17a29817664 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -802,7 +802,7 @@ static int truetype_entry_save(struct udevice *dev, struct abuf *buf) struct console_tt_store store; const uint size = sizeof(store); - if (spl_phase() <= PHASE_SPL) + if (xpl_phase() <= PHASE_SPL) return -ENOSYS; /* @@ -826,7 +826,7 @@ static int truetype_entry_restore(struct udevice *dev, struct abuf *buf) struct console_tt_priv *priv = dev_get_priv(dev); struct console_tt_store store; - if (spl_phase() <= PHASE_SPL) + if (xpl_phase() <= PHASE_SPL) return -ENOSYS; memcpy(&store, abuf_data(buf), sizeof(store)); @@ -853,7 +853,7 @@ static int truetype_set_cursor_visible(struct udevice *dev, bool visible, uint out, val; int ret; - if (spl_phase() <= PHASE_SPL) + if (xpl_phase() <= PHASE_SPL) return -ENOSYS; if (!visible) diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index 587df7beb9b..1631dc38416 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -418,8 +418,8 @@ static int meson_dw_hdmi_probe(struct udevice *dev) } if (!ret) { - ret = regulator_set_enable(supply, true); - if (ret) + ret = regulator_set_enable_if_allowed(supply, true); + if (ret && ret != -ENOSYS) return ret; } #endif diff --git a/drivers/video/sharp-lq101r1sx01.c b/drivers/video/sharp-lq101r1sx01.c new file mode 100644 index 00000000000..5d8453fd796 --- /dev/null +++ b/drivers/video/sharp-lq101r1sx01.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Sharp LQ101R1SX01 DSI panel driver + * + * Copyright (C) 2014 NVIDIA Corporation + * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <mipi_dsi.h> +#include <linux/delay.h> +#include <power/regulator.h> + +struct sharp_lq101r1sx01_priv { + struct udevice *backlight; + struct udevice *panel_sec; + struct udevice *vcc; +}; + +static struct display_timing default_timing = { + .pixelclock.typ = 278000000, + .hactive.typ = 2560, + .hfront_porch.typ = 128, + .hback_porch.typ = 64, + .hsync_len.typ = 64, + .vactive.typ = 1600, + .vfront_porch.typ = 4, + .vback_porch.typ = 8, + .vsync_len.typ = 32, +}; + +static int sharp_lq101r1sx01_write(struct mipi_dsi_device *dsi, + u16 offset, u8 value) +{ + u8 payload[3] = { offset >> 8, offset & 0xff, value }; + int ret; + + ret = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); + if (ret < 0) { + log_debug("%s: failed to write %02x to %04x: %zd\n", + __func__, value, offset, ret); + return ret; + } + + ret = mipi_dsi_dcs_nop(dsi); + if (ret < 0) { + log_debug("%s: failed to send DCS nop: %zd\n", + __func__, ret); + return ret; + } + + udelay(20); + + return 0; +} + +static int sharp_setup_symmetrical_split(struct mipi_dsi_device *left, + struct mipi_dsi_device *right, + struct display_timing *timing) +{ + int ret; + + ret = mipi_dsi_dcs_set_column_address(left, 0, + timing->hactive.typ / 2 - 1); + if (ret < 0) { + log_debug("%s: failed to set column address: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_page_address(left, 0, timing->vactive.typ - 1); + if (ret < 0) { + log_debug("%s: failed to set page address: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_column_address(right, timing->hactive.typ / 2, + timing->hactive.typ - 1); + if (ret < 0) { + log_debug("%s: failed to set column address: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_page_address(right, 0, timing->vactive.typ - 1); + if (ret < 0) { + log_debug("%s: failed to set page address: %d\n", + __func__, ret); + return ret; + } + + return 0; +} + +static int sharp_lq101r1sx01_enable_backlight(struct udevice *dev) +{ + struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev); + + if (!priv->panel_sec) + return 0; + + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_panel_plat *plat_sec = dev_get_plat(priv->panel_sec); + struct mipi_dsi_device *link1 = plat->device; + struct mipi_dsi_device *link2 = plat_sec->device; + int ret; + + ret = mipi_dsi_dcs_exit_sleep_mode(link1); + if (ret < 0) { + log_debug("%s: failed to exit sleep mode: %d\n", + __func__, ret); + return ret; + } + + /* set left-right mode */ + ret = sharp_lq101r1sx01_write(link1, 0x1000, 0x2a); + if (ret < 0) { + log_debug("%s: failed to set left-right mode: %d\n", + __func__, ret); + return ret; + } + + /* enable command mode */ + ret = sharp_lq101r1sx01_write(link1, 0x1001, 0x01); + if (ret < 0) { + log_debug("%s: failed to enable command mode: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_pixel_format(link1, MIPI_DCS_PIXEL_FMT_24BIT); + if (ret < 0) { + log_debug("%s: failed to set pixel format: %d\n", + __func__, ret); + return ret; + } + + /* + * TODO: The device supports both left-right and even-odd split + * configurations, but this driver currently supports only the left- + * right split. To support a different mode a mechanism needs to be + * put in place to communicate the configuration back to the DSI host + * controller. + */ + ret = sharp_setup_symmetrical_split(link1, link2, &default_timing); + if (ret < 0) { + log_debug("%s: failed to set up symmetrical split: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_display_on(link1); + if (ret < 0) { + log_debug("%s: failed to set panel on: %d\n", + __func__, ret); + return ret; + } + mdelay(20); + + return 0; +} + +static int sharp_lq101r1sx01_set_backlight(struct udevice *dev, int percent) +{ + struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev); + int ret; + + if (!priv->panel_sec) + return 0; + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + return backlight_set_brightness(priv->backlight, percent); +} + +static int sharp_lq101r1sx01_timings(struct udevice *dev, + struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int sharp_lq101r1sx01_of_to_plat(struct udevice *dev) +{ + struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev); + int ret; + + /* If node has no link2 it is secondary panel */ + if (!dev_read_bool(dev, "link2")) + return 0; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, + "link2", &priv->panel_sec); + if (ret) { + log_debug("%s: cannot get secondary panel: ret = %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_debug("%s: cannot get backlight: ret = %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "power-supply", &priv->vcc); + if (ret) { + log_debug("%s: cannot get power-supply: ret = %d\n", + __func__, ret); + return ret; + } + + return 0; +} + +static int sharp_lq101r1sx01_hw_init(struct udevice *dev) +{ + struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev); + int ret; + + if (!priv->panel_sec) + return 0; + + ret = regulator_set_enable_if_allowed(priv->vcc, 1); + if (ret) { + log_debug("%s: enabling power-supply failed (%d)\n", + __func__, ret); + return ret; + } + + /* + * According to the datasheet, the panel needs around 10 ms to fully + * power up. At least another 120 ms is required before exiting sleep + * mode to make sure the panel is ready. Throw in another 20 ms for + * good measure. + */ + mdelay(150); + + return 0; +} + +static int sharp_lq101r1sx01_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + /* fill characteristics of DSI data link */ + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + + return sharp_lq101r1sx01_hw_init(dev); +} + +static const struct panel_ops sharp_lq101r1sx01_ops = { + .enable_backlight = sharp_lq101r1sx01_enable_backlight, + .set_backlight = sharp_lq101r1sx01_set_backlight, + .get_display_timing = sharp_lq101r1sx01_timings, +}; + +static const struct udevice_id sharp_lq101r1sx01_ids[] = { + { .compatible = "sharp,lq101r1sx01" }, + { } +}; + +U_BOOT_DRIVER(sharp_lq101r1sx01) = { + .name = "sharp_lq101r1sx01", + .id = UCLASS_PANEL, + .of_match = sharp_lq101r1sx01_ids, + .ops = &sharp_lq101r1sx01_ops, + .of_to_plat = sharp_lq101r1sx01_of_to_plat, + .probe = sharp_lq101r1sx01_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct sharp_lq101r1sx01_priv), +}; diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index accabbf4dbb..d24aa375b39 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -26,8 +26,6 @@ #include "tegra-dc.h" -DECLARE_GLOBAL_DATA_PTR; - /* Holder of Tegra per-SOC DC differences */ struct tegra_dc_soc_info { bool has_timer; diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index 35a8e6c176b..6327266dd22 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -20,6 +20,7 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h> #include "tegra-dc.h" #include "tegra-dsi.h" @@ -50,6 +51,10 @@ struct tegra_dsi_priv { int host_fifo_depth; u32 version; + + /* for ganged-mode support */ + struct udevice *master; + struct udevice *slave; }; static void tegra_dc_enable_controller(struct udevice *dev) @@ -595,6 +600,17 @@ static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming, writel(value, &ptiming->dsi_bta_timing); } +static void tegra_dsi_ganged_enable(struct udevice *dev, unsigned int start, + unsigned int size) +{ + struct tegra_dsi_priv *priv = dev_get_priv(dev); + struct dsi_ganged_mode_reg *ganged = &priv->dsi->ganged; + + writel(start, &ganged->ganged_mode_start); + writel(size << 16 | size, &ganged->ganged_mode_size); + writel(DSI_GANGED_MODE_CONTROL_ENABLE, &ganged->ganged_mode_ctrl); +} + static void tegra_dsi_configure(struct udevice *dev, unsigned long mode_flags) { @@ -679,9 +695,19 @@ static void tegra_dsi_configure(struct udevice *dev, writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3); writel(hfp, &len->dsi_pkt_len_4_5); writel(0x0f0f << 16, &len->dsi_pkt_len_6_7); + + /* set SOL delay (for non-burst mode only) */ + writel(8 * mul / div, &misc->dsi_sol_delay); } else { - /* 1 byte (DCS command) + pixel data */ - value = 1 + timing->hactive.typ * mul / div; + if (priv->master || priv->slave) { + /* + * For ganged mode, assume symmetric left-right mode. + */ + value = 1 + (timing->hactive.typ / 2) * mul / div; + } else { + /* 1 byte (DCS command) + pixel data */ + value = 1 + timing->hactive.typ * mul / div; + } writel(0, &len->dsi_pkt_len_0_1); writel(value << 16, &len->dsi_pkt_len_2_3); @@ -691,10 +717,40 @@ static void tegra_dsi_configure(struct udevice *dev, value = MIPI_DCS_WRITE_MEMORY_START << 8 | MIPI_DCS_WRITE_MEMORY_CONTINUE; writel(value, &len->dsi_dcs_cmds); + + /* set SOL delay */ + if (priv->master || priv->slave) { + unsigned long delay, bclk, bclk_ganged; + unsigned int lanes = device->lanes; + unsigned long htotal = timing->hactive.typ + timing->hfront_porch.typ + + timing->hback_porch.typ + timing->hsync_len.typ; + + /* SOL to valid, valid to FIFO and FIFO write delay */ + delay = 4 + 4 + 2; + delay = DIV_ROUND_UP(delay * mul, div * lanes); + /* FIFO read delay */ + delay = delay + 6; + + bclk = DIV_ROUND_UP(htotal * mul, div * lanes); + bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); + value = bclk - bclk_ganged + delay + 20; + } else { + /* TODO: revisit for non-ganged mode */ + value = 8 * mul / div; + } + + writel(value, &misc->dsi_sol_delay); } - /* set SOL delay (for non-burst mode only) */ - writel(8 * mul / div, &misc->dsi_sol_delay); + if (priv->slave) { + /* + * TODO: Support modes other than symmetrical left-right + * split. + */ + tegra_dsi_ganged_enable(dev, 0, timing->hactive.typ / 2); + tegra_dsi_ganged_enable(priv->slave, timing->hactive.typ / 2, + timing->hactive.typ / 2); + } } static int tegra_dsi_encoder_enable(struct udevice *dev) @@ -774,6 +830,9 @@ static int tegra_dsi_encoder_enable(struct udevice *dev) value |= DSI_POWER_CONTROL_ENABLE; writel(value, &misc->dsi_pwr_ctrl); + if (priv->slave) + tegra_dsi_encoder_enable(priv->slave); + return 0; } @@ -803,6 +862,14 @@ static void tegra_dsi_init_clocks(struct udevice *dev) unsigned int mul, div; unsigned long bclk, plld; + if (!priv->slave) { + /* Change DSIB clock parent to match DSIA */ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + clrbits_le32(&clkrst->plld2.pll_base, BIT(25)); /* DSIB_CLK_SRC */ + } + tegra_dsi_get_muldiv(device->format, &mul, &div); bclk = (priv->timing.pixelclock.typ * mul) / @@ -854,6 +921,24 @@ static void tegra_dsi_init_clocks(struct udevice *dev) reset_set_enable(priv->dsi_clk, 0); } +static int tegra_dsi_ganged_probe(struct udevice *dev) +{ + struct tegra_dsi_priv *mpriv = dev_get_priv(dev); + struct udevice *gangster; + + uclass_get_device_by_phandle(UCLASS_PANEL, dev, + "nvidia,ganged-mode", &gangster); + if (gangster) { + /* Ganged mode is set */ + struct tegra_dsi_priv *spriv = dev_get_priv(gangster); + + mpriv->slave = gangster; + spriv->master = dev; + } + + return 0; +} + static int tegra_dsi_bridge_probe(struct udevice *dev) { struct tegra_dsi_priv *priv = dev_get_priv(dev); @@ -873,6 +958,8 @@ static int tegra_dsi_bridge_probe(struct udevice *dev) priv->video_fifo_depth = 1920; priv->host_fifo_depth = 64; + tegra_dsi_ganged_probe(dev); + ret = reset_get_by_name(dev, "dsi", &reset_ctl); if (ret) { log_debug("%s: reset_get_by_name() failed: %d\n", diff --git a/drivers/video/tegra20/tegra-dsi.h b/drivers/video/tegra20/tegra-dsi.h index 69dac4bd1b8..683c5e31a34 100644 --- a/drivers/video/tegra20/tegra-dsi.h +++ b/drivers/video/tegra20/tegra-dsi.h @@ -98,9 +98,9 @@ struct dsi_timeout_reg { uint dsi_to_tally; /* _DSI_TO_TALLY_0 */ }; -/* DSI PAD control register 0x04b ~ 0x04e */ +/* DSI PAD control register 0x04b ~ 0x052 */ struct dsi_pad_ctrl_reg { - /* Address 0x04b ~ 0x04e */ + /* Address 0x04b ~ 0x052 */ uint pad_ctrl; /* _PAD_CONTROL_0 */ uint pad_ctrl_cd; /* _PAD_CONTROL_CD_0 */ uint pad_cd_status; /* _PAD_CD_STATUS_0 */ @@ -111,6 +111,14 @@ struct dsi_pad_ctrl_reg { uint pad_ctrl_4; /* _PAD_CONTROL_4 */ }; +/* DSI ganged mode register 0x053 ~ 0x04e */ +struct dsi_ganged_mode_reg { + /* Address 0x053 ~ 0x055 */ + uint ganged_mode_ctrl; /* _DSI_GANGED_MODE_CONTROL_0 */ + uint ganged_mode_start; /* _DSI_GANGED_MODE_START_0 */ + uint ganged_mode_size; /* _DSI_GANGED_MODE_SIZE_0 */ +}; + /* Display Serial Interface (DSI_) regs */ struct dsi_ctlr { struct dsi_syncpt_reg syncpt; /* SYNCPT register 0x000 ~ 0x002 */ @@ -133,6 +141,7 @@ struct dsi_ctlr { uint reserved5[4]; /* reserved_5[4] */ struct dsi_pad_ctrl_reg pad; /* PAD registers 0x04b ~ 0x04e */ + struct dsi_ganged_mode_reg ganged; /* GANGED registers 0x053 ~ 0x055 */ }; #define DSI_POWER_CONTROL_ENABLE BIT(0) @@ -202,6 +211,8 @@ struct dsi_ctlr { #define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) +#define DSI_GANGED_MODE_CONTROL_ENABLE BIT(0) + /* * pixel format as used in the DSI_CONTROL_FORMAT field */ diff --git a/drivers/video/tidss/Makefile b/drivers/video/tidss/Makefile index a29cee2a414..f0cbe1d4ed1 100644 --- a/drivers/video/tidss/Makefile +++ b/drivers/video/tidss/Makefile @@ -9,4 +9,4 @@ # Author: Tomi Valkeinen <tomi.valkeinen@ti.com> -obj-${CONFIG_$(SPL_)VIDEO_TIDSS} = tidss_drv.o +obj-${CONFIG_$(XPL_)VIDEO_TIDSS} = tidss_drv.o diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 41bb7647fda..9823673f817 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -128,7 +128,7 @@ int video_reserve(ulong *addrp) struct udevice *dev; ulong size; - if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() == PHASE_BOARD_F) + if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() == PHASE_BOARD_F) return 0; gd->video_top = *addrp; @@ -421,7 +421,7 @@ bool video_is_active(void) struct udevice *dev; /* Assume video to be active if SPL passed video hand-off to U-boot */ - if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) + if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() > PHASE_SPL) return true; for (uclass_find_first_device(UCLASS_VIDEO, &dev); @@ -573,7 +573,7 @@ static int video_post_probe(struct udevice *dev) * NOTE: * This assumes that reserved video memory only uses a single framebuffer */ - if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { + if (xpl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { struct video_handoff *ho; ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0); diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 6b564b7f96d..51be6ab9abe 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o -obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o +obj-$(CONFIG_$(PHASE_)WDT) += wdt-uclass.o obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o obj-$(CONFIG_WDT_ALARM_SANDBOX) += sandbox_alarm-wdt.o obj-$(CONFIG_WDT_APPLE) += apple_wdt.o diff --git a/dts/Makefile b/dts/Makefile index d6c2c9daf31..62a65688cf5 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -53,7 +53,7 @@ PHONY += arch-dtbs arch-dtbs: $(Q)$(MAKE) $(build)=$(dt_dir) dtbs -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_OF_EMBED) := dt-spl.dtb.o # support "out-of-tree" build for dtb-spl $(obj)/dt-spl.dtb.o: $(obj)/dt-spl.dtb.S FORCE diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi index b29ce732131..e88c1fbac6a 100644 --- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi +++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi @@ -914,6 +914,8 @@ dmas = <&dma 48>, <&dma 48>; dma-names = "rx", "tx"; resets = <&r_ccu RST_R_APB2_I2C>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index afb49e65859..f01ace649c2 100644 --- a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -201,12 +201,12 @@ vcc-pi-supply = <®_cldo3>; }; -&r_rsb { +&r_i2c { status = "okay"; - axp717: pmic@3a3 { + axp717: pmic@34 { compatible = "x-powers,axp717"; - reg = <0x3a3>; + reg = <0x34>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&nmi_intc>; diff --git a/env/Makefile b/env/Makefile index 673b979fdfa..a54e924d419 100644 --- a/env/Makefile +++ b/env/Makefile @@ -3,12 +3,12 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += common.o -obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += env.o -obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += attr.o -obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += flags.o +obj-$(CONFIG_$(PHASE_)ENV_SUPPORT) += common.o +obj-$(CONFIG_$(PHASE_)ENV_SUPPORT) += env.o +obj-$(CONFIG_$(PHASE_)ENV_SUPPORT) += attr.o +obj-$(CONFIG_$(PHASE_)ENV_SUPPORT) += flags.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += callback.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += embedded.o @@ -20,12 +20,12 @@ obj-$(CONFIG_ENV_IS_IN_REMOTE) += remote.o obj-$(CONFIG_ENV_IS_IN_UBI) += ubi.o endif -obj-$(CONFIG_$(SPL_TPL_)ENV_IS_NOWHERE) += nowhere.o -obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MMC) += mmc.o -obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FAT) += fat.o -obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_EXT4) += ext4.o -obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NAND) += nand.o -obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_SPI_FLASH) += sf.o -obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o +obj-$(CONFIG_$(PHASE_)ENV_IS_NOWHERE) += nowhere.o +obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MMC) += mmc.o +obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) += fat.o +obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o +obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o +obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o +obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o CFLAGS_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null) diff --git a/env/common.c b/env/common.c index 6cba7f1c187..a58955a4f42 100644 --- a/env/common.c +++ b/env/common.c @@ -61,7 +61,7 @@ int env_do_env_set(int flag, int argc, char *const argv[], int env_flag) debug("Initial value for argc=%d\n", argc); -#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_CMD_NVEDIT_EFI) +#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_CMD_NVEDIT_EFI) if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e') return do_env_set_efi(NULL, flag, --argc, ++argv); #endif @@ -551,7 +551,7 @@ int env_export(env_t *env_out) void env_relocate(void) { if (gd->env_valid == ENV_INVALID) { -#if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_XPL_BUILD) /* Environment not changable */ env_set_default(NULL, 0); #else diff --git a/env/fat.c b/env/fat.c index f3f8b7301ee..b04b1d9c315 100644 --- a/env/fat.c +++ b/env/fat.c @@ -22,7 +22,7 @@ #include <asm/global_data.h> #include <linux/stddef.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* TODO(sjg@chromium.org): Figure out why this is needed */ # if !defined(CONFIG_TARGET_AM335X_EVM) || defined(CONFIG_SPL_OS_BOOT) # define LOADENV @@ -129,7 +129,7 @@ static int env_fat_load(void) if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) scsi_scan(true); diff --git a/env/flash.c b/env/flash.c index 1bd6e7003d6..0f7393d830c 100644 --- a/env/flash.c +++ b/env/flash.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD # if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_FLASH) # include <flash.h> # define CMD_SAVEENV @@ -35,11 +35,11 @@ DECLARE_GLOBAL_DATA_PTR; #if (!defined(CONFIG_MICROBLAZE) && !defined(CONFIG_ARCH_ZYNQ) && \ !defined(CONFIG_TARGET_MCCMON6) && !defined(CONFIG_TARGET_X600) && \ !defined(CONFIG_TARGET_EDMINIV2)) || \ - !defined(CONFIG_SPL_BUILD) + !defined(CONFIG_XPL_BUILD) #define LOADENV #endif -#if !defined(CONFIG_TARGET_X600) || !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_TARGET_X600) || !defined(CONFIG_XPL_BUILD) #define INITENV #endif diff --git a/env/mmc.c b/env/mmc.c index e2f8e7ece28..379f5ec9be7 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -298,7 +298,7 @@ static void fini_mmc_for_env(struct mmc *mmc) mmc_set_env_part_restore(mmc); } -#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_XPL_BUILD) static inline int write_env(struct mmc *mmc, unsigned long size, unsigned long offset, const void *buffer) { @@ -427,7 +427,7 @@ fini: fini_mmc_for_env(mmc); return ret; } -#endif /* CONFIG_CMD_SAVEENV && !CONFIG_SPL_BUILD */ +#endif /* CONFIG_CMD_SAVEENV && !CONFIG_XPL_BUILD */ static inline int read_env(struct mmc *mmc, unsigned long size, unsigned long offset, const void *buffer) @@ -557,7 +557,7 @@ U_BOOT_ENV_LOCATION(mmc) = { .location = ENVL_MMC, ENV_NAME("MMC") .load = env_mmc_load, -#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_XPL_BUILD) .save = env_save_ptr(env_mmc_save), .erase = ENV_ERASE_PTR(env_mmc_erase) #endif diff --git a/env/nand.c b/env/nand.c index fef5697ec39..fdaa903cd61 100644 --- a/env/nand.c +++ b/env/nand.c @@ -26,9 +26,9 @@ #include <u-boot/crc.h> #if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND) && \ - !defined(CONFIG_SPL_BUILD) + !defined(CONFIG_XPL_BUILD) #define CMD_SAVEENV -#elif defined(CONFIG_ENV_OFFSET_REDUND) && !defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_ENV_OFFSET_REDUND) && !defined(CONFIG_XPL_BUILD) #error CONFIG_ENV_OFFSET_REDUND must have CONFIG_CMD_SAVEENV & CONFIG_CMD_NAND #endif @@ -224,7 +224,7 @@ static int env_nand_save(void) } #endif /* CMD_SAVEENV */ -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) static int readenv(size_t offset, u_char *buf) { return nand_spl_load_image(offset, CONFIG_ENV_SIZE, buf); @@ -265,7 +265,7 @@ static int readenv(size_t offset, u_char *buf) return 0; } -#endif /* #if defined(CONFIG_SPL_BUILD) */ +#endif /* #if defined(CONFIG_XPL_BUILD) */ #ifdef CONFIG_ENV_OFFSET_OOB int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result) diff --git a/env/nowhere.c b/env/nowhere.c index 326f27db2e9..6b9b6e2fe0b 100644 --- a/env/nowhere.c +++ b/env/nowhere.c @@ -33,7 +33,7 @@ static int env_nowhere_load(void) * searches default_environment array in that case. * For U-Boot proper, import the default environment to allow reload. */ - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) env_set_default(NULL, 0); gd->env_valid = ENV_INVALID; @@ -329,7 +329,7 @@ done: __weak void *env_sf_get_env_addr(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD return (void *)CONFIG_ENV_ADDR; #else return NULL; diff --git a/fs/Makefile b/fs/Makefile index a3ee0a361d3..1e54ac11ab7 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_FS_LOADER) += fs.o obj-$(CONFIG_SPL_FS_FAT) += fat/ obj-$(CONFIG_SPL_FS_EXT4) += ext4/ diff --git a/fs/fat/Makefile b/fs/fat/Makefile index f84efaccc75..7414b3602aa 100644 --- a/fs/fat/Makefile +++ b/fs/fat/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_$(SPL_)FS_FAT) = fat.o -obj-$(CONFIG_$(SPL_)FAT_WRITE) = fat_write.o +obj-$(CONFIG_$(XPL_)FS_FAT) = fat.o +obj-$(CONFIG_$(XPL_)FAT_WRITE) = fat_write.o @@ -237,7 +237,7 @@ static struct fstype_info fstypes[] = { .mkdir = fs_mkdir_unsupported, }, #endif -#if IS_ENABLED(CONFIG_SANDBOX) && !IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_SANDBOX) && !IS_ENABLED(CONFIG_XPL_BUILD) { .fstype = FS_TYPE_SANDBOX, .name = "sandbox", @@ -275,7 +275,7 @@ static struct fstype_info fstypes[] = { .ln = fs_ln_unsupported, }, #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifdef CONFIG_CMD_UBIFS { .fstype = FS_TYPE_UBIFS, @@ -296,7 +296,7 @@ static struct fstype_info fstypes[] = { }, #endif #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifdef CONFIG_FS_BTRFS { .fstype = FS_TYPE_BTRFS, diff --git a/fs/sandbox/Makefile b/fs/sandbox/Makefile index 880d59dd693..54ad842d1fe 100644 --- a/fs/sandbox/Makefile +++ b/fs/sandbox/Makefile @@ -9,4 +9,4 @@ # Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de obj-y := sandboxfs.o -obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += host_bootdev.o +obj-$(CONFIG_$(PHASE_)BOOTSTD) += host_bootdev.o diff --git a/fs/squashfs/Makefile b/fs/squashfs/Makefile index ba66ee821c2..0772e1a497d 100644 --- a/fs/squashfs/Makefile +++ b/fs/squashfs/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_$(SPL_)FS_SQUASHFS) = sqfs.o \ +obj-$(CONFIG_$(XPL_)FS_SQUASHFS) = sqfs.o \ sqfs_inode.o \ sqfs_dir.o \ sqfs_decompressor.o diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index d6c15e2c406..644a0d77873 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -55,7 +55,7 @@ struct global_data { * @cur_serial_dev: current serial device */ struct udevice *cur_serial_dev; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /** * @jt: jump table * diff --git a/include/bootcount.h b/include/bootcount.h index bc06e17c9fb..847c0f02d98 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -120,13 +120,13 @@ static inline void bootcount_inc(void) return; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Only increment bootcount when no bootcount support in SPL */ #if !defined(CONFIG_SPL_BOOTCOUNT_LIMIT) && !defined(CONFIG_TPL_BOOTCOUNT_LIMIT) bootcount_store(++bootcount); #endif env_set_ulong("bootcount", bootcount); -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ } #else diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 2a136b96a6d..0a4e4b8ff85 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -63,7 +63,7 @@ #define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc) #define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) #define BOOTENV_SHARED_MMC #define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV_NONE #define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV_NONE @@ -198,7 +198,7 @@ #define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata) #define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) #define BOOTENV_SHARED_SATA #define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV_NONE #define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV_NONE @@ -305,7 +305,7 @@ BOOTENV_SHARED_BLKDEV_BODY(usb) #define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) #define BOOTENV_RUN_NET_USB_START #define BOOTENV_SHARED_USB #define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV_NONE @@ -412,7 +412,7 @@ "\0" #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \ "dhcp " -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) #define BOOTENV_DEV_DHCP BOOTENV_DEV_BLKDEV_NONE #define BOOTENV_DEV_NAME_DHCP BOOTENV_DEV_NAME_BLKDEV_NONE #else @@ -433,7 +433,7 @@ "fi\0" #define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \ "pxe " -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) #define BOOTENV_DEV_PXE BOOTENV_DEV_BLKDEV_NONE #define BOOTENV_DEV_NAME_PXE BOOTENV_DEV_NAME_BLKDEV_NONE #else diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 9efae58ce90..20fded56b77 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -43,7 +43,7 @@ #define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10) #define CFG_SYS_NAND_U_BOOT_DST (0x11000000) #define CFG_SYS_NAND_U_BOOT_START (0x11000000) -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) #define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CFG_SYS_NAND_U_BOOT_DST 0xD0000000 #define CFG_SYS_NAND_U_BOOT_START 0xD0000000 @@ -290,7 +290,7 @@ extern unsigned long get_sdram_size(void); /* * Config the L2 Cache as L2 SRAM */ -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) #define CFG_SYS_INIT_L2_ADDR 0xD0000000 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 67f46562539..19d3c72a6f1 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -75,7 +75,7 @@ #include <config_distro_bootcmd.h> -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #include <env/ti/dfu.h> #define CFG_EXTRA_ENV_SETTINGS \ @@ -181,7 +181,7 @@ #endif /* !CONFIG_MTD_RAW_NAND */ /* USB Device Firmware Update support */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define DFUARGS \ DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_MMC \ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index a8fa61c7e50..96efd38594a 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -16,7 +16,7 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x80000000\0" \ @@ -70,7 +70,7 @@ "setenv boot_syslinux_conf \"extlinux/extlinux.conf\"; " \ "run bootcmd_ubifs0;\0" -#endif /* ! CONFIG_SPL_BUILD */ +#endif /* ! CONFIG_XPL_BUILD */ #define SPLASH_SCREEN_NAND_PART "nand0,10" #define SPLASH_SCREEN_BMP_FILE_SIZE 0x26000 diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index dedef91ba59..55d5190b221 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -20,7 +20,7 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "kloadaddr=0x84000000\0" \ @@ -117,7 +117,7 @@ "setenv mmcpart 5; " \ "fi; " \ "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif /* #ifndef CONFIG_XPL_BUILD */ #if defined CONFIG_SHC_NETBOOT /* Network Boot */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 87ffa769d15..036995cbb48 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -35,7 +35,7 @@ /* NS16550 Configuration */ #define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* USB Device Firmware Update support */ #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ @@ -63,7 +63,7 @@ #include <config_distro_bootcmd.h> -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #include <env/ti/dfu.h> #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 4b4362ccfd8..aa31f3b05a0 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -18,7 +18,7 @@ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ DFU_ALT_INFO_MMC \ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 71d4727ca98..4c690a17856 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -18,64 +18,6 @@ #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" -/* - * Custom Distro Boot configuration: - * 1. 8bit SD port (MMC1) - * 2. 4bit SD port (MMC2) - * 3. eMMC (MMC0) - */ -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \ - "boot part 0 1 mmcpart 0; " \ - "rootfs part 0 2 mmcpart 0; " \ - "zImage fat 0 1 mmcpart 0; " \ - "tegra124-apalis-eval.dtb fat 0 1 mmcpart 0" - -#define UBOOT_UPDATE \ - "uboot_hwpart=1\0" \ - "uboot_blk=0\0" \ - "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ - "setexpr blkcnt ${blkcnt} / 0x200\0" \ - "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ - "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ - -#define BOARD_EXTRA_ENV_SETTINGS \ - "boot_file=zImage\0" \ - "boot_script_dhcp=boot.scr\0" \ - "console=ttyS0\0" \ - "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \ - "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \ - "user_debug=30 pcie_aspm=off\0" \ - "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ - "fdt_board=eval\0" \ - "fdt_fixup=;\0" \ - "fdt_module=" FDT_MODULE "\0" \ - UBOOT_UPDATE \ - "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ - "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ - "flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ - "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \ - "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1 " \ - "${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "setup=setenv setupargs igb_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8 debug_uartport=lsport,0 " \ - "${memargs}\0" \ - "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ - "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ - "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "vidargs=fbcon=map:1\0" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 80204d706d1..87a679efde6 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -22,18 +22,6 @@ */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define UBOOT_UPDATE \ - "uboot_hwpart=1\0" \ - "uboot_blk=0\0" \ - "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ - "setexpr blkcnt ${blkcnt} / 0x200\0" \ - "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ - "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ - -#define BOARD_EXTRA_ENV_SETTINGS \ - UBOOT_UPDATE \ - "boot_script_dhcp=boot.scr\0" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 9dcacad2fc0..1f61b2b6af6 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -13,10 +13,10 @@ #include "siemens-env-common.h" /* SPL config */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x00120000 -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* ENET1 connects to base board and MUX with ESAI */ #define CFG_FEC_ENET_DEV 1 diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 82729eb95cf..3412b883cbb 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -13,10 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu" -#define BOARD_EXTRA_ENV_SETTINGS \ - "board_name=cardhu-a04\0" \ - "fdtfile=tegra30-cardhu-a04.dtb\0" - /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 98d4d8cf4bd..0d338389cb9 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -11,7 +11,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index ea7d648eb6a..bc616d14368 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -13,17 +13,6 @@ /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* NAND support */ - -#define UBOOT_UPDATE \ - "update_uboot=nand erase.part u-boot && " \ - "nand write ${loadaddr} u-boot ${filesize}\0" \ - -/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ -#define BOARD_EXTRA_ENV_SETTINGS \ - "boot_script_dhcp=boot.scr\0" \ - UBOOT_UPDATE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 7edb2c0b26d..1f474669a73 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -23,18 +23,6 @@ */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define UBOOT_UPDATE \ - "uboot_hwpart=1\0" \ - "uboot_blk=0\0" \ - "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ - "setexpr blkcnt ${blkcnt} / 0x200\0" \ - "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ - "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ - -#define BOARD_EXTRA_ENV_SETTINGS \ - UBOOT_UPDATE \ - "boot_script_dhcp=boot.scr\0" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 416aa96366c..8db849c6d09 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -157,7 +157,7 @@ "console=ttyS2,115200n8\0" \ "hwconfig=dsp:wake=yes" -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* defines for SPL */ #endif diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 633ec1f32fa..96dcd731cb6 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -28,7 +28,7 @@ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ DFU_ALT_INFO_MMC \ @@ -37,7 +37,7 @@ DFU_ALT_INFO_QSPI #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_SPL_DFU #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ diff --git a/include/configs/ds116.h b/include/configs/ds116.h index c2326596811..2f2bc43269e 100644 --- a/include/configs/ds116.h +++ b/include/configs/ds116.h @@ -18,7 +18,7 @@ */ #include "mv-common.h" -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define KERNEL_ADDR_R __stringify(0x1000000) #define FDT_ADDR_R __stringify(0x2000000) @@ -39,6 +39,6 @@ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "console=ttyS0,115200\0" -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #endif /* _CONFIG_DS116_H */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 95256575583..431a78de416 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -43,7 +43,7 @@ */ #include "mv-common.h" -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define KERNEL_ADDR_R __stringify(0x1000000) #define FDT_ADDR_R __stringify(0x2000000) @@ -80,6 +80,6 @@ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "console=ttyS0,115200\0" -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #endif /* _CONFIG_SYNOLOGY_DS414_H */ diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h index 348078f9770..33d0021ec13 100644 --- a/include/configs/endeavoru.h +++ b/include/configs/endeavoru.h @@ -10,54 +10,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <linux/sizes.h> - #include "tegra30-common.h" /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "HTC One X" -#define ENDEAVORU_FLASH_UBOOT \ - "flash_uboot=echo Preparing RAM;" \ - "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ - "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ - "echo Reading BCT;" \ - "mmc dev 0 1;" \ - "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ - "echo Reading bootloader;" \ - "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \ - "then echo Calculating bootloader size;" \ - "size mmc 0:1 ${bootloader_file};" \ - "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ - "echo Writing bootloader to eMMC;" \ - "mmc dev 0 1;" \ - "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ - "mmc dev 0 2;" \ - "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ - "echo Bootloader written successfully;" \ - "pause 'Press ANY key to reboot device...'; reset;" \ - "else echo Reading bootloader failed;" \ - "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" - -#define ENDEAVORU_BOOTMENU \ - ENDEAVORU_FLASH_UBOOT \ - "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ - "bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ - "bootmenu_2=update bootloader=run flash_uboot\0" \ - "bootmenu_3=reboot RCM=enterrcm\0" \ - "bootmenu_4=reboot=reset\0" \ - "bootmenu_5=power off=poweroff\0" \ - "bootmenu_delay=-1\0" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "boot_block_size_r=0x200000\0" \ - "boot_block_size=0x1000\0" \ - "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "button_cmd_0_name=Volume Down\0" \ - "button_cmd_0=bootmenu\0" \ - "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ - ENDEAVORU_BOOTMENU - /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 1b97ae22fc6..a89d298b525 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -15,7 +15,7 @@ #define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CFG_SYS_NS16550_CLK 40000000 #define CFG_SYS_NS16550_COM1 0xb0000c00 #endif diff --git a/include/configs/grouper.h b/include/configs/grouper.h index 8064b88902e..b6ef6ff2ecb 100644 --- a/include/configs/grouper.h +++ b/include/configs/grouper.h @@ -6,56 +6,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <linux/sizes.h> - #include "tegra30-common.h" /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)" -#define GROUPER_FLASH_UBOOT \ - "flash_uboot=echo Preparing RAM;" \ - "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ - "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ - "echo Reading BCT;" \ - "mmc dev 0 1;" \ - "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ - "echo Reading bootloader;" \ - "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \ - "then echo Calculating bootloader size;" \ - "size mmc 0:1 ${bootloader_file};" \ - "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ - "echo Writing bootloader to eMMC;" \ - "mmc dev 0 1;" \ - "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ - "mmc dev 0 2;" \ - "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ - "echo Bootloader written successfully;" \ - "pause 'Press ANY key to reboot device...'; reset;" \ - "else echo Reading bootloader failed;" \ - "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" - -#define GROUPER_BOOTMENU \ - GROUPER_FLASH_UBOOT \ - "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ - "bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ - "bootmenu_2=update bootloader=run flash_uboot\0" \ - "bootmenu_3=reboot RCM=enterrcm\0" \ - "bootmenu_4=reboot=reset\0" \ - "bootmenu_5=power off=poweroff\0" \ - "bootmenu_delay=-1\0" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "boot_block_size_r=0x200000\0" \ - "boot_block_size=0x1000\0" \ - "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "button_cmd_0_name=Volume Down\0" \ - "button_cmd_0=bootmenu\0" \ - "button_cmd_1_name=Lid\0" \ - "button_cmd_1=poweroff\0" \ - "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ - GROUPER_BOOTMENU - /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h index 12c7649f788..c4e6b2a647c 100644 --- a/include/configs/ideapad-yoga-11.h +++ b/include/configs/ideapad-yoga-11.h @@ -11,64 +11,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11" -#define IDEAPAD_FLASH_UBOOT \ - "flash_uboot=sf probe 0:1;" \ - "echo Dumping current SPI flash content ...;" \ - "sf read ${kernel_addr_r} 0x0 ${spi_size};" \ - "if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size};" \ - "then echo SPI flash content was successfully written into spi-flash-backup.bin;" \ - "echo Reading SPI flash binary;" \ - "if load mmc 1:1 ${kernel_addr_r} repart-block.bin;" \ - "then echo Writing bootloader into SPI flash;" \ - "sf probe 0:1;" \ - "sf update ${kernel_addr_r} 0x0 ${spi_size};" \ - "echo Bootloader SUCCESSFULLY written into SPI flash;" \ - "pause 'Press ANY key to reboot...'; reset;" \ - "else echo Preparing RAM;" \ - "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ - "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ - "echo Reading BCT;" \ - "sf read ${kernel_addr_r} 0x0 ${boot_block_size_r};" \ - "echo Reading bootloader;" \ - "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \ - "then echo Calculating bootloader size;" \ - "size mmc 1:1 ${bootloader_file};" \ - "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ - "echo Writing bootloader into SPI flash;" \ - "sf probe 0:1;" \ - "sf update ${kernel_addr_r} 0x0 ${boot_block_size_r};" \ - "sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r};" \ - "echo Bootloader written SUCCESSFULLY;" \ - "pause 'Press ANY key to reboot...'; reset;" \ - "else echo Reading bootloader failed;" \ - "pause 'Press ANY key to reboot...'; reset; fi;" \ - "fi;" \ - "else echo SPI flash backup FAILED! Aborting ...;" \ - "pause 'Press ANY key to reboot...'; reset; fi\0" - -#define IDEAPAD_BOOTMENU \ - IDEAPAD_FLASH_UBOOT \ - "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ - "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ - "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ - "bootmenu_3=update bootloader=run flash_uboot\0" \ - "bootmenu_4=reboot RCM=enterrcm\0" \ - "bootmenu_5=reboot=reset\0" \ - "bootmenu_6=power off=poweroff\0" \ - "bootmenu_delay=-1\0" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "spi_size=0x400000\0" \ - "boot_block_size_r=0x200000\0" \ - "boot_block_size=0x1000\0" \ - "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "button_cmd_0_name=Volume Down\0" \ - "button_cmd_0=bootmenu\0" \ - "button_cmd_1_name=Lid sensor\0" \ - "button_cmd_1=poweroff\0" \ - "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ - IDEAPAD_BOOTMENU - /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index fab5063b73f..64ddbf711d3 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -92,7 +92,7 @@ /* SPL */ #ifdef CONFIG_SPL -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_SYS_FSL_USDHC_NUM 2 #ifdef CONFIG_SYS_BOOT_EMMC diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 9da98d0af27..44a3fc02e8a 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -14,14 +14,14 @@ #define CFG_MXC_UART_BASE UART4_BASE -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(NAND, nand, 0) \ #include <config_distro_bootcmd.h> -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 146f7945719..6ed4a6fd3fc 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -14,7 +14,7 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x912000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index fa20651d2df..2ec7f3d8b6f 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -21,7 +21,7 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 9a5e5bd009d..d323f84ac7a 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 9dd63fc1196..3bbbd900dd4 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -22,7 +22,7 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 2158b0af74f..145dab91215 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -13,11 +13,11 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ # define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 2) \ diff --git a/include/configs/imx8mm_phg.h b/include/configs/imx8mm_phg.h index d2d7ffa0f5b..038d3a7ce3f 100644 --- a/include/configs/imx8mm_phg.h +++ b/include/configs/imx8mm_phg.h @@ -14,7 +14,7 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x930000 #endif diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 66816618b0c..ed09dd09bcb 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -12,7 +12,7 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x930000 #endif diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index b82e35f4963..8b96f7fd1e4 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -23,7 +23,7 @@ EFI_GUID(0xb5fb6f08, 0xe142, 0x4db1, 0x97, 0xea, \ 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ * GD_FLG_FULL_MALLOC_INIT \ * set \ diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 2bbd6b1680f..ccbb0f85559 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 9eefc31dc6f..666f46ac105 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index cd73a72d2b7..3bc4b0034e8 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h index 7fa441a8a83..40f96a5f219 100644 --- a/include/configs/imx8mq_reform2.h +++ b/include/configs/imx8mq_reform2.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 4d5abe2d073..842184bcae2 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 93999509948..1b6eb2b81cf 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -10,7 +10,7 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index aa9da19a11f..9308f5234f4 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -11,7 +11,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x22040000 #endif diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index ce6567e2af6..53fb8c9b1ba 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -13,7 +13,7 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MALLOC_F_ADDR 0x204D0000 #endif diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h index da6adf6c413..b76e049f09c 100644 --- a/include/configs/khadas-vim3_android.h +++ b/include/configs/khadas-vim3_android.h @@ -21,8 +21,8 @@ "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \ "name=vbmeta_a,size=512K,uuid=${uuid_gpt_vbmeta_a};" \ "name=vbmeta_b,size=512K,uuid=${uuid_gpt_vbmeta_b};" \ - "name=boot_a,size=32M,bootable,uuid=${uuid_gpt_boot_a};" \ - "name=boot_b,size=32M,bootable,uuid=${uuid_gpt_boot_b};" \ + "name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \ + "name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \ "name=super,size=3072M,uuid=${uuid_gpt_super};" \ "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID @@ -33,8 +33,8 @@ "name=misc,size=512K,uuid=${uuid_gpt_misc};" \ "name=dtbo,size=8M,uuid=${uuid_gpt_dtbo};" \ "name=vbmeta,size=512K,uuid=${uuid_gpt_vbmeta};" \ - "name=boot,size=32M,bootable,uuid=${uuid_gpt_boot};" \ - "name=recovery,size=32M,uuid=${uuid_gpt_recovery};" \ + "name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \ + "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=super,size=1792M,uuid=${uuid_gpt_super};" \ "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \ diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h index b1768e2d821..0ab8ffd372a 100644 --- a/include/configs/khadas-vim3l_android.h +++ b/include/configs/khadas-vim3l_android.h @@ -21,8 +21,8 @@ "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \ "name=vbmeta_a,size=512K,uuid=${uuid_gpt_vbmeta_a};" \ "name=vbmeta_b,size=512K,uuid=${uuid_gpt_vbmeta_b};" \ - "name=boot_a,size=32M,bootable,uuid=${uuid_gpt_boot_a};" \ - "name=boot_b,size=32M,bootable,uuid=${uuid_gpt_boot_b};" \ + "name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \ + "name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \ "name=super,size=3072M,uuid=${uuid_gpt_super};" \ "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID @@ -33,8 +33,8 @@ "name=misc,size=512K,uuid=${uuid_gpt_misc};" \ "name=dtbo,size=8M,uuid=${uuid_gpt_dtbo};" \ "name=vbmeta,size=512K,uuid=${uuid_gpt_vbmeta};" \ - "name=boot,size=32M,bootable,uuid=${uuid_gpt_boot};" \ - "name=recovery,size=32M,uuid=${uuid_gpt_recovery};" \ + "name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \ + "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=super,size=1792M,uuid=${uuid_gpt_super};" \ "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \ diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 3a129c5cce7..72a28a6a413 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -10,7 +10,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <config.h> #endif @@ -39,7 +39,7 @@ #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x930000 #endif diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 3dda7b66806..3f52d00d6c8 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -12,7 +12,7 @@ EFI_GUID(0xc898e959, 0x5b1f, 0x4e6d, 0x88, 0xe0, \ 0x40, 0xd4, 0x5c, 0xca, 0x13, 0x99) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 876b02f4da6..571c7724eaf 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -41,7 +41,7 @@ #define CONSOLE "ttymxc0" #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index e8f7a59c401..ec1aa14be01 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -15,7 +15,7 @@ #define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CFG_SYS_NS16550_CLK 40000000 #define CFG_SYS_NS16550_COM3 0xb0000e00 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e500a7d80ff..a02c752bbcf 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -8,7 +8,7 @@ #define __LS1043A_COMMON_H /* SPL build */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SPL_NO_FMAN #define SPL_NO_DSPI #define SPL_NO_PCIE @@ -19,10 +19,10 @@ #define SPL_NO_QE #define SPL_NO_EEPROM #endif -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) +#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_NAND_BOOT)) #define SPL_NO_MMC #endif -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) +#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) #define SPL_NO_IFC #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 867b098a073..53ef5975a28 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -8,7 +8,7 @@ #define __LS1046A_COMMON_H /* SPL build */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SPL_NO_QBMAN #define SPL_NO_FMAN #define SPL_NO_ENV @@ -17,11 +17,11 @@ #define SPL_NO_USB #define SPL_NO_SATA #endif -#if defined(CONFIG_SPL_BUILD) && \ +#if defined(CONFIG_XPL_BUILD) && \ (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT)) #define SPL_NO_MMC #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #define SPL_NO_IFC #endif diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 34085eeecc7..cdf281947dc 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -7,7 +7,7 @@ #define __LS1088_COMMON_H /* SPL build */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SPL_NO_BOARDINFO #define SPL_NO_QIXIS #define SPL_NO_PCI diff --git a/include/configs/meson64.h b/include/configs/meson64.h index ccb8ea2e716..f3275b37a51 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -77,6 +77,15 @@ #define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) #endif +#ifdef CONFIG_CMD_MMC + #define BOOT_TARGET_MMC(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) +#else + #define BOOT_TARGET_MMC(func) +#endif + #ifdef CONFIG_CMD_USB #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) #else @@ -95,18 +104,27 @@ #define BOOT_TARGET_SCSI(func) #endif +#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE) + #define BOOT_TARGET_PXE(func) func(PXE, pxe, na) + #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#elif defined(CONFIG_CMD_DHCP) + #define BOOT_TARGET_PXE(func) + #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else + #define BOOT_TARGET_PXE(func) + #define BOOT_TARGET_DHCP(func) +#endif + #ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(ROMUSB, romusb, na) \ func(USB_DFU, usbdfu, na) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ + BOOT_TARGET_MMC(func) \ BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_NVME(func) \ BOOT_TARGET_SCSI(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) #endif #define BOOTM_SIZE __stringify(0x1700000) diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index c0e977abb01..fa520265800 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -116,31 +116,7 @@ "fi; " \ "abootimg get dtb --index=$dtb_index dtb_start dtb_size; " \ "cp.b $dtb_start $fdt_addr_r $dtb_size; " \ - "fdt addr $fdt_addr_r 0x80000; " \ - "if test $board_name = sei510; then " \ - "echo \" Reading DTBO for sei510...\"; " \ - "setenv dtbo_index 0;" \ - "elif test $board_name = sei610; then " \ - "echo \" Reading DTBO for sei610...\"; " \ - "setenv dtbo_index 1;" \ - "elif test $board_name = vim3l; then " \ - "echo \" Reading DTBO for vim3l...\"; " \ - "setenv dtbo_index 2;" \ - "elif test $board_name = vim3; then " \ - "echo \" Reading DTBO for vim3...\"; " \ - "setenv dtbo_index 3;" \ - "else " \ - "echo Error: Android boot is not supported for $board_name; " \ - "exit; " \ - "fi; " \ - "part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; " \ - "part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; " \ - "mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; " \ - "echo \" Applying DTBOs...\"; " \ - "adtimg addr $dtboaddr; " \ - "adtimg get dt --index=$dtbo_index dtbo0_addr; " \ - "fdt apply $dtbo0_addr;" \ - "setenv bootargs \"$bootargs androidboot.dtbo_idx=$dtbo_index \";"\ + "fdt addr $fdt_addr_r 0x80000; " #define BOOT_CMD "bootm ${loadaddr} ${loadaddr} ${fdt_addr_r};" diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index ea5c93ecf69..985b1ca91e6 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -20,7 +20,7 @@ #define CFG_FEC_MXC_PHYADDR 1 #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index e6dba707195..636d62dd883 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -15,7 +15,7 @@ #define CFG_SYS_INIT_SP_OFFSET 0x800000 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CFG_SYS_NS16550_CLK 50000000 #define CFG_SYS_NS16550_COM1 0xbe000c00 #endif diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 1df06811d65..ba876ac3029 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -13,7 +13,7 @@ #define CFG_SYS_INIT_SP_OFFSET 0x80000 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CFG_SYS_NS16550_CLK 40000000 #define CFG_SYS_NS16550_COM1 0xb0000c00 #endif diff --git a/include/configs/n2350.h b/include/configs/n2350.h index f98b9f8582d..c789df55bfb 100644 --- a/include/configs/n2350.h +++ b/include/configs/n2350.h @@ -18,7 +18,7 @@ */ #include "mv-common.h" -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define KERNEL_ADDR_R __stringify(0x1000000) #define FDT_ADDR_R __stringify(0x2000000) @@ -39,6 +39,6 @@ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "console=ttyS0,115200\0" -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #endif /* _CONFIG_N2350_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f5bd0913449..23d8917b718 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -98,7 +98,7 @@ #define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CFG_SYS_NAND_U_BOOT_DST (0x11000000) #define CFG_SYS_NAND_U_BOOT_START (0x11000000) -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) #define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000 #define CFG_SYS_NAND_U_BOOT_START 0xf8f80000 @@ -280,7 +280,7 @@ /* * Config the L2 Cache as L2 SRAM */ -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) #define CFG_SYS_INIT_L2_ADDR 0xf8f80000 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h index e409cc3896d..fc1b7c0302d 100644 --- a/include/configs/p2771-0000.h +++ b/include/configs/p2771-0000.h @@ -15,26 +15,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define BOARD_EXTRA_ENV_SETTINGS \ - "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ - "ramdisk_addr_r\0" \ - "kernel_addr_r_align=00200000\0" \ - "kernel_addr_r_offset=00080000\0" \ - "kernel_addr_r_size=02000000\0" \ - "kernel_addr_r_aliases=loadaddr\0" \ - "fdt_addr_r_align=00200000\0" \ - "fdt_addr_r_offset=00000000\0" \ - "fdt_addr_r_size=00200000\0" \ - "scriptaddr_align=00200000\0" \ - "scriptaddr_offset=00000000\0" \ - "scriptaddr_size=00200000\0" \ - "pxefile_addr_r_align=00200000\0" \ - "pxefile_addr_r_offset=00000000\0" \ - "pxefile_addr_r_size=00200000\0" \ - "ramdisk_addr_r_align=00200000\0" \ - "ramdisk_addr_r_offset=00000000\0" \ - "ramdisk_addr_r_size=02000000\0" - #include "tegra-common-post.h" #endif diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index e60f42eaa72..1138c1d306f 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -15,19 +15,6 @@ /* Board-specific serial config */ -/* Only MMC/PXE/DHCP for now, add USB back in later when supported */ -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#define BOARD_EXTRA_ENV_SETTINGS \ - "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \ - "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \ - "source ${scriptaddr}; " \ - "fi\0" - /* General networking support */ #include "tegra-common-post.h" diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 0910ae2d870..e74a3f184c6 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -14,7 +14,7 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 422b89a3dd3..3012f64c0ae 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -9,7 +9,7 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ diff --git a/include/configs/qc750.h b/include/configs/qc750.h index ce6665d0f34..ad9f9146bb7 100644 --- a/include/configs/qc750.h +++ b/include/configs/qc750.h @@ -15,48 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Wexler QC750" -#define QC750_FLASH_UBOOT \ - "flash_uboot=echo Preparing RAM;" \ - "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ - "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ - "echo Reading BCT;" \ - "mmc dev 0 1;" \ - "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ - "echo Reading bootloader;" \ - "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \ - "then echo Calculating bootloader size;" \ - "size mmc 1:1 ${bootloader_file};" \ - "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ - "echo Writing bootloader to eMMC;" \ - "mmc dev 0 1;" \ - "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ - "mmc dev 0 2;" \ - "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ - "echo Bootloader written successfully;" \ - "pause 'Press ANY key to reboot device...'; reset;" \ - "else echo Reading bootloader failed;" \ - "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" - -#define QC750_BOOTMENU \ - QC750_FLASH_UBOOT \ - "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ - "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ - "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ - "bootmenu_3=update bootloader=run flash_uboot\0" \ - "bootmenu_4=reboot RCM=enterrcm\0" \ - "bootmenu_5=reboot=reset\0" \ - "bootmenu_6=power off=poweroff\0" \ - "bootmenu_delay=-1\0" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "boot_block_size_r=0x200000\0" \ - "boot_block_size=0x1000\0" \ - "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "button_cmd_0_name=Volume Down\0" \ - "button_cmd_0=bootmenu\0" \ - "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ - QC750_BOOTMENU - /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index d652ae4ca34..c5bcd7dc5e8 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -13,7 +13,7 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifndef ROCKCHIP_DEVICE_SETTINGS #define ROCKCHIP_DEVICE_SETTINGS @@ -38,6 +38,6 @@ ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #endif /* __CONFIG_RK3399_COMMON_H */ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9121bba3738..9b8ab3cdf20 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -11,7 +11,7 @@ #define CFG_CPUID_OFFSET 0x7 #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define BOOT_TARGETS "mmc1 mmc0 nvme scsi usb pxe dhcp spi" diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4838bfd4f13..2acfdc7df4a 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -117,7 +117,7 @@ /* SPL NAND boot support */ /* Extra Environment */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifdef CONFIG_CMD_DHCP #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 29a1197b5ae..af6dd4a8095 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -33,7 +33,7 @@ #ifdef CONFIG_DISTRO_DEFAULTS /*****************************************************************************/ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #ifdef CONFIG_CMD_MMC #define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0) @@ -129,7 +129,7 @@ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV -#endif /* ifndef CONFIG_SPL_BUILD */ +#endif /* ifndef CONFIG_XPL_BUILD */ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ #endif /* __CONFIG_STM32MP15_COMMMON_H */ diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index 6fe6e7b9b8c..0f466711cae 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -10,7 +10,7 @@ /* PHY needs a longer autoneg timeout */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_EXTRA_ENV_SETTINGS \ "dfu_alt_info_ram=u-boot.itb ram " \ __stringify(CONFIG_SPL_LOAD_FIT_ADDRESS) \ diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h index 30f6450cf38..1f0837e179b 100644 --- a/include/configs/surface-rt.h +++ b/include/configs/surface-rt.h @@ -13,24 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT" -#define SURFACE_RT_BOOTMENU \ - "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ - "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ - "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ - "bootmenu_3=boot from USB=usb reset; usb start; bootflow scan\0" \ - "bootmenu_4=reboot RCM=enterrcm\0" \ - "bootmenu_5=reboot=reset\0" \ - "bootmenu_6=power off=poweroff\0" \ - "bootmenu_delay=-1\0" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "button_cmd_0_name=Volume Down\0" \ - "button_cmd_0=bootmenu\0" \ - "button_cmd_1_name=Hall Sensor\0" \ - "button_cmd_1=poweroff\0" \ - "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ - SURFACE_RT_BOOTMENU - /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 45f7179f035..4a7474ff3f9 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -31,7 +31,7 @@ 115200} /* Select serial console configuration */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_SYS_NS16550_COM1 OMAP34XX_UART1 #define CFG_SYS_NS16550_COM2 OMAP34XX_UART2 #define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index c4f116aabf8..7a333090b18 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -95,7 +95,7 @@ * So moving TEXT_BASE down to non-HS limit. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ #endif diff --git a/include/configs/transformer-common.h b/include/configs/transformer-common.h deleted file mode 100644 index bb6817c8d2b..00000000000 --- a/include/configs/transformer-common.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com>. - */ - -#ifndef __TRANSFORMER_COMMON_H -#define __TRANSFORMER_COMMON_H - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" - -#define TRANSFORMER_FLASH_UBOOT \ - "flash_uboot=echo Preparing RAM;" \ - "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ - "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ - "echo Reading BCT;" \ - "mmc dev 0 1;" \ - "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ - "echo Reading bootloader;" \ - "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \ - "then echo Calculating bootloader size;" \ - "size mmc 1:1 ${bootloader_file};" \ - "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ - "echo Writing bootloader to eMMC;" \ - "mmc dev 0 1;" \ - "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ - "mmc dev 0 2;" \ - "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ - "echo Bootloader written successfully;" \ - "pause 'Press ANY key to reboot device...'; reset;" \ - "else echo Reading bootloader failed;" \ - "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" - -#define TRANSFORMER_FLASH_SPI \ - "update_spi=sf probe 0:1;" \ - "echo Dumping current SPI flash content ...;" \ - "sf read ${kernel_addr_r} 0x0 ${spi_size};" \ - "if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size};" \ - "then echo SPI flash content was successfully written into spi-flash-backup.bin;" \ - "echo Reading SPI flash binary;" \ - "if load mmc 1:1 ${kernel_addr_r} repart-block.bin;" \ - "then echo Writing bootloader into SPI flash;" \ - "sf probe 0:1;" \ - "sf update ${kernel_addr_r} 0x0 ${spi_size};" \ - "poweroff;" \ - "else echo Preparing RAM;" \ - "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ - "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ - "echo Reading BCT;" \ - "sf read ${kernel_addr_r} 0x0 ${boot_block_size_r};" \ - "echo Reading bootloader;" \ - "if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file};" \ - "then echo Calculating bootloader size;" \ - "size mmc 1:1 ${bootloader_file};" \ - "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ - "echo Writing bootloader into SPI flash;" \ - "sf probe 0:1;" \ - "sf update ${kernel_addr_r} 0x0 ${boot_block_size_r};" \ - "sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r};" \ - "echo Bootloader written successfully; poweroff;" \ - "else echo Reading bootloader failed;" \ - "poweroff; fi;" \ - "fi;" \ - "else echo SPI flash backup FAILED! Aborting ...;" \ - "poweroff; fi\0" - -#define TRANSFORMER_BOOTMENU \ - TRANSFORMER_FLASH_UBOOT \ - TRANSFORMER_FLASH_SPI \ - "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ - "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ - "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ - "bootmenu_3=update bootloader=run flash_uboot\0" \ - "bootmenu_4=reboot RCM=enterrcm\0" \ - "bootmenu_5=reboot=reset\0" \ - "bootmenu_6=power off=poweroff\0" \ - "bootmenu_delay=-1\0" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "spi_size=0x400000\0" \ - "boot_block_size_r=0x200000\0" \ - "boot_block_size=0x1000\0" \ - "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "button_cmd_0_name=Volume Down\0" \ - "button_cmd_0=bootmenu\0" \ - "button_cmd_1_name=Lid sensor\0" \ - "button_cmd_1=poweroff\0" \ - "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ - TRANSFORMER_BOOTMENU - -#endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h index ca1e70caa71..6a3d9b24036 100644 --- a/include/configs/transformer-t20.h +++ b/include/configs/transformer-t20.h @@ -11,7 +11,9 @@ #define __CONFIG_H #include "tegra20-common.h" -#include "transformer-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h index d2a16f12c18..792b958a302 100644 --- a/include/configs/transformer-t30.h +++ b/include/configs/transformer-t30.h @@ -10,10 +10,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <linux/sizes.h> - #include "tegra30-common.h" -#include "transformer-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/turris_1x.h b/include/configs/turris_1x.h index 3d398a6c1ec..c05614950c7 100644 --- a/include/configs/turris_1x.h +++ b/include/configs/turris_1x.h @@ -63,7 +63,7 @@ /* * For SD card builds without SPL it is needed to set CONFIG_SYS_RAMBOOT * - * if CONFIG_SPL_BUILD + * if CONFIG_XPL_BUILD * if CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR * define CONFIG_SPL_MAX_SIZE = (CONFIG_SYS_L2_SIZE+CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * * SZ_512) @@ -121,7 +121,7 @@ */ /* Initial SRAM is used only for SD card boot in first stage image */ -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) #define CFG_SYS_INIT_L2_ADDR 0xf8f80000 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR /* diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 302194bc90f..03a12d519f2 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -31,7 +31,7 @@ #include "mv-common.h" /* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ @@ -86,6 +86,6 @@ "bootcmd_rescue=" TURRIS_OMNIA_BOOTCMD_RESCUE "\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #endif /* _CONFIG_TURRIS_OMNIA_H */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index b018bbe29dd..c54383b886e 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -12,7 +12,7 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 0b88e95603d..bff417fdafb 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -12,13 +12,13 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define MEM_LAYOUT_ENV_SETTINGS \ "fdt_addr_r=0x50200000\0" \ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 2cf7bc70d8d..752b23d055c 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -47,7 +47,7 @@ /* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define CFG_MXC_UART_BASE UART1_BASE #endif diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index 78a20128611..c152af9b7e2 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -10,55 +10,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <linux/sizes.h> - #include "tegra30-common.h" /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "LG X3 Board" -#define X3_FLASH_UBOOT \ - "flash_uboot=echo Preparing RAM;" \ - "mw ${kernel_addr_r} 0 ${boot_block_size_r};" \ - "mw ${ramdisk_addr_r} 0 ${boot_block_size_r};" \ - "echo Reading BCT;" \ - "mmc dev 0 1;" \ - "mmc read ${kernel_addr_r} 0 ${boot_block_size};" \ - "echo Reading bootloader;" \ - "if load mmc 0:1 ${ramdisk_addr_r} ${bootloader_file};" \ - "then echo Calculating bootloader size;" \ - "size mmc 0:1 ${bootloader_file};" \ - "ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};" \ - "echo Writing bootloader to eMMC;" \ - "mmc dev 0 1;" \ - "mmc write ${kernel_addr_r} 0 ${boot_block_size};" \ - "mmc dev 0 2;" \ - "mmc write ${ramdisk_addr_r} 0 ${boot_block_size};" \ - "echo Bootloader written successfully;" \ - "pause 'Press ANY key to reboot device...'; reset;" \ - "else echo Reading bootloader failed;" \ - "pause 'Press ANY key to return to bootmenu...'; bootmenu; fi\0" - -#define X3_BOOTMENU \ - X3_FLASH_UBOOT \ - "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ - "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ - "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ - "bootmenu_3=update bootloader=run flash_uboot\0" \ - "bootmenu_4=reboot RCM=enterrcm\0" \ - "bootmenu_5=reboot=reset\0" \ - "bootmenu_6=power off=poweroff\0" \ - "bootmenu_delay=-1\0" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "boot_block_size_r=0x200000\0" \ - "boot_block_size=0x1000\0" \ - "bootloader_file=u-boot-dtb-tegra.bin\0" \ - "button_cmd_0_name=Volume Down\0" \ - "button_cmd_0=bootmenu\0" \ - "partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ - X3_BOOTMENU - /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index de0db7bb63f..bb0db7c5ca3 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -183,7 +183,7 @@ #endif /* SPL can't handle all huge variables - define just DFU */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_DFU) #undef CFG_EXTRA_ENV_SETTINGS # define CFG_EXTRA_ENV_SETTINGS \ "dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 03af859c951..37c77aa1611 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -44,7 +44,7 @@ /* Boot configuration */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define BOOTENV #else @@ -167,7 +167,7 @@ BOOT_TARGET_DEVICES_DHCP(func) #include <config_distro_bootcmd.h> -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* Default environment */ #ifndef CFG_EXTRA_ENV_SETTINGS diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 5795115c490..0787758926f 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -1588,6 +1588,47 @@ int ofnode_conf_read_int(const char *prop_name, int default_val); const char *ofnode_conf_read_str(const char *prop_name); /** + * ofnode_options_read_bool() - Read a boolean value from the U-Boot options + * + * This reads a property from the /options/u-boot/ node of the devicetree. + * + * This only works with the control FDT. + * + * See dtschema/schemas/options/u-boot.yaml in dt-schema project for bindings + * + * @prop_name: property name to look up + * Return: true, if it exists, false if not + */ +bool ofnode_options_read_bool(const char *prop_name); + +/** + * ofnode_options_read_int() - Read an integer value from the U-Boot options + * + * This reads a property from the /options/u-boot/ node of the devicetree. + * + * See dtschema/schemas/options/u-boot.yaml in dt-schema project for bindings + * + * @prop_name: property name to look up + * @default_val: default value to return if the property is not found + * Return: integer value, if found, or @default_val if not + */ +int ofnode_options_read_int(const char *prop_name, int default_val); + +/** + * ofnode_options_read_str() - Read a string value from the U-Boot options + * + * This reads a property from the /options/u-boot/ node of the devicetree. + * + * This only works with the control FDT. + * + * See dtschema/schemas/options/u-boot.yaml in dt-schema project for bindings + * + * @prop_name: property name to look up + * Return: string value, if found, or NULL if not + */ +const char *ofnode_options_read_str(const char *prop_name); + +/** * ofnode_read_bootscript_address() - Read bootscr-address or bootscr-ram-offset * * @bootscr_address: pointer to 64bit address where bootscr-address property value diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h deleted file mode 100644 index 6f8f01e6762..00000000000 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 Arm Ltd. - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_ -#define _DT_BINDINGS_CLK_SUN50I_H616_H_ - -#define CLK_PLL_PERIPH0 4 - -#define CLK_CPUX 21 - -#define CLK_APB1 26 - -#define CLK_DE 29 -#define CLK_BUS_DE 30 -#define CLK_DEINTERLACE 31 -#define CLK_BUS_DEINTERLACE 32 -#define CLK_G2D 33 -#define CLK_BUS_G2D 34 -#define CLK_GPU0 35 -#define CLK_BUS_GPU 36 -#define CLK_GPU1 37 -#define CLK_CE 38 -#define CLK_BUS_CE 39 -#define CLK_VE 40 -#define CLK_BUS_VE 41 -#define CLK_BUS_DMA 42 -#define CLK_BUS_HSTIMER 43 -#define CLK_AVS 44 -#define CLK_BUS_DBG 45 -#define CLK_BUS_PSI 46 -#define CLK_BUS_PWM 47 -#define CLK_BUS_IOMMU 48 - -#define CLK_MBUS_DMA 50 -#define CLK_MBUS_VE 51 -#define CLK_MBUS_CE 52 -#define CLK_MBUS_TS 53 -#define CLK_MBUS_NAND 54 -#define CLK_MBUS_G2D 55 - -#define CLK_NAND0 57 -#define CLK_NAND1 58 -#define CLK_BUS_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC1 61 -#define CLK_MMC2 62 -#define CLK_BUS_MMC0 63 -#define CLK_BUS_MMC1 64 -#define CLK_BUS_MMC2 65 -#define CLK_BUS_UART0 66 -#define CLK_BUS_UART1 67 -#define CLK_BUS_UART2 68 -#define CLK_BUS_UART3 69 -#define CLK_BUS_UART4 70 -#define CLK_BUS_UART5 71 -#define CLK_BUS_I2C0 72 -#define CLK_BUS_I2C1 73 -#define CLK_BUS_I2C2 74 -#define CLK_BUS_I2C3 75 -#define CLK_BUS_I2C4 76 -#define CLK_SPI0 77 -#define CLK_SPI1 78 -#define CLK_BUS_SPI0 79 -#define CLK_BUS_SPI1 80 -#define CLK_EMAC_25M 81 -#define CLK_BUS_EMAC0 82 -#define CLK_BUS_EMAC1 83 -#define CLK_TS 84 -#define CLK_BUS_TS 85 -#define CLK_BUS_THS 86 -#define CLK_SPDIF 87 -#define CLK_BUS_SPDIF 88 -#define CLK_DMIC 89 -#define CLK_BUS_DMIC 90 -#define CLK_AUDIO_CODEC_1X 91 -#define CLK_AUDIO_CODEC_4X 92 -#define CLK_BUS_AUDIO_CODEC 93 -#define CLK_AUDIO_HUB 94 -#define CLK_BUS_AUDIO_HUB 95 -#define CLK_USB_OHCI0 96 -#define CLK_USB_PHY0 97 -#define CLK_USB_OHCI1 98 -#define CLK_USB_PHY1 99 -#define CLK_USB_OHCI2 100 -#define CLK_USB_PHY2 101 -#define CLK_USB_OHCI3 102 -#define CLK_USB_PHY3 103 -#define CLK_BUS_OHCI0 104 -#define CLK_BUS_OHCI1 105 -#define CLK_BUS_OHCI2 106 -#define CLK_BUS_OHCI3 107 -#define CLK_BUS_EHCI0 108 -#define CLK_BUS_EHCI1 109 -#define CLK_BUS_EHCI2 110 -#define CLK_BUS_EHCI3 111 -#define CLK_BUS_OTG 112 -#define CLK_BUS_KEYADC 113 -#define CLK_HDMI 114 -#define CLK_HDMI_SLOW 115 -#define CLK_HDMI_CEC 116 -#define CLK_BUS_HDMI 117 -#define CLK_BUS_TCON_TOP 118 -#define CLK_TCON_TV0 119 -#define CLK_TCON_TV1 120 -#define CLK_BUS_TCON_TV0 121 -#define CLK_BUS_TCON_TV1 122 -#define CLK_TVE0 123 -#define CLK_BUS_TVE_TOP 124 -#define CLK_BUS_TVE0 125 -#define CLK_HDCP 126 -#define CLK_BUS_HDCP 127 -#define CLK_PLL_SYSTEM_32K 128 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h deleted file mode 100644 index 1bd8bb0a11b..00000000000 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 Arm Ltd. - */ - -#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_ -#define _DT_BINDINGS_RESET_SUN50I_H616_H_ - -#define RST_MBUS 0 -#define RST_BUS_DE 1 -#define RST_BUS_DEINTERLACE 2 -#define RST_BUS_GPU 3 -#define RST_BUS_CE 4 -#define RST_BUS_VE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_HSTIMER 7 -#define RST_BUS_DBG 8 -#define RST_BUS_PSI 9 -#define RST_BUS_PWM 10 -#define RST_BUS_IOMMU 11 -#define RST_BUS_DRAM 12 -#define RST_BUS_NAND 13 -#define RST_BUS_MMC0 14 -#define RST_BUS_MMC1 15 -#define RST_BUS_MMC2 16 -#define RST_BUS_UART0 17 -#define RST_BUS_UART1 18 -#define RST_BUS_UART2 19 -#define RST_BUS_UART3 20 -#define RST_BUS_UART4 21 -#define RST_BUS_UART5 22 -#define RST_BUS_I2C0 23 -#define RST_BUS_I2C1 24 -#define RST_BUS_I2C2 25 -#define RST_BUS_I2C3 26 -#define RST_BUS_I2C4 27 -#define RST_BUS_SPI0 28 -#define RST_BUS_SPI1 29 -#define RST_BUS_EMAC0 30 -#define RST_BUS_EMAC1 31 -#define RST_BUS_TS 32 -#define RST_BUS_THS 33 -#define RST_BUS_SPDIF 34 -#define RST_BUS_DMIC 35 -#define RST_BUS_AUDIO_CODEC 36 -#define RST_BUS_AUDIO_HUB 37 -#define RST_USB_PHY0 38 -#define RST_USB_PHY1 39 -#define RST_USB_PHY2 40 -#define RST_USB_PHY3 41 -#define RST_BUS_OHCI0 42 -#define RST_BUS_OHCI1 43 -#define RST_BUS_OHCI2 44 -#define RST_BUS_OHCI3 45 -#define RST_BUS_EHCI0 46 -#define RST_BUS_EHCI1 47 -#define RST_BUS_EHCI2 48 -#define RST_BUS_EHCI3 49 -#define RST_BUS_OTG 50 -#define RST_BUS_HDMI 51 -#define RST_BUS_HDMI_SUB 52 -#define RST_BUS_TCON_TOP 53 -#define RST_BUS_TCON_TV0 54 -#define RST_BUS_TCON_TV1 55 -#define RST_BUS_TVE_TOP 56 -#define RST_BUS_TVE0 57 -#define RST_BUS_HDCP 58 -#define RST_BUS_KEYADC 59 - -#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ diff --git a/include/efi_loader.h b/include/efi_loader.h index f84852e384f..511281e150e 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -567,7 +567,7 @@ efi_status_t EFIAPI efi_convert_pointer(efi_uintn_t debug_disposition, /* Carve out DT reserved memory ranges */ void efi_carve_out_dt_rsv(void *fdt); /* Purge unused kaslr-seed */ -void efi_try_purge_kaslr_seed(void *fdt); +void efi_try_purge_rng_seed(void *fdt); /* Called by bootefi to make console interface available */ efi_status_t efi_console_register(void); /* Called by efi_init_obj_list() to proble all block devices */ diff --git a/include/env.h b/include/env.h index d2a5954ded8..01c3eeae7e2 100644 --- a/include/env.h +++ b/include/env.h @@ -44,7 +44,7 @@ struct env_clbk_tbl { * For SPL these are silently dropped to reduce code size, since environment * callbacks are not supported with SPL. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define U_BOOT_ENV_CALLBACK(name, callback) \ static inline __maybe_unused void _u_boot_env_noop_##name(void) \ { \ diff --git a/include/env/nvidia/prod_upd.env b/include/env/nvidia/prod_upd.env new file mode 100644 index 00000000000..f4e381994be --- /dev/null +++ b/include/env/nvidia/prod_upd.env @@ -0,0 +1,60 @@ +boot_block_size_r=0x200000 +boot_block_size=0x1000 +bootloader_file=u-boot-dtb-tegra.bin +spi_size=0x400000 +boot_dev=0 + +flash_uboot=echo Preparing RAM; + mw ${kernel_addr_r} 0 ${boot_block_size_r}; + mw ${ramdisk_addr_r} 0 ${boot_block_size_r}; + echo Reading BCT; + mmc dev 0 1; + mmc read ${kernel_addr_r} 0 ${boot_block_size}; + echo Reading bootloader; + if load mmc ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file}; + then echo Calculating bootloader size; + size mmc ${boot_dev}:1 ${bootloader_file}; + ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize}; + echo Writing bootloader to eMMC; + mmc dev 0 1; + mmc write ${kernel_addr_r} 0 ${boot_block_size}; + mmc dev 0 2; + mmc write ${ramdisk_addr_r} 0 ${boot_block_size}; + echo Bootloader written successfully; + pause 'Press ANY key to reboot device...'; reset; + else echo Reading bootloader failed; + pause 'Press ANY key to return to bootmenu...'; bootmenu; fi + +update_spi=sf probe 0:1; + echo Dumping current SPI flash content ...; + sf read ${kernel_addr_r} 0x0 ${spi_size}; + if fatwrite mmc 1:1 ${kernel_addr_r} spi-flash-backup.bin ${spi_size}; + then echo SPI flash content was successfully written into spi-flash-backup.bin; + echo Reading SPI flash binary; + if load mmc 1:1 ${kernel_addr_r} repart-block.bin; + then echo Writing bootloader into SPI flash; + sf probe 0:1; + sf update ${kernel_addr_r} 0x0 ${spi_size}; + echo Bootloader SUCCESSFULLY written into SPI flash; + pause 'Press ANY key to reboot...'; reset; + else echo Preparing RAM; + mw ${kernel_addr_r} 0 ${boot_block_size_r}; + mw ${ramdisk_addr_r} 0 ${boot_block_size_r}; + echo Reading BCT; + sf read ${kernel_addr_r} 0x0 ${boot_block_size_r}; + echo Reading bootloader; + if load mmc 1:1 ${ramdisk_addr_r} ${bootloader_file}; + then echo Calculating bootloader size; + size mmc 1:1 ${bootloader_file}; + ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize}; + echo Writing bootloader into SPI flash; + sf probe 0:1; + sf update ${kernel_addr_r} 0x0 ${boot_block_size_r}; + sf update ${ramdisk_addr_r} ${boot_block_size_r} ${boot_block_size_r}; + echo Bootloader written SUCCESSFULLY; + pause 'Press ANY key to reboot...'; reset; + else echo Reading bootloader failed; + pause 'Press ANY key to reboot...'; reset; fi; + fi; + else echo SPI flash backup FAILED! Aborting ...; + pause 'Press ANY key to reboot...'; reset; fi diff --git a/include/env_callback.h b/include/env_callback.h index 66cc8309e71..bc8ff1923e1 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -92,7 +92,7 @@ "serial#:serialno," \ CFG_ENV_CALLBACK_LIST_STATIC -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD void env_callback_init(struct env_entry *var_entry); #else static inline void env_callback_init(struct env_entry *var_entry) diff --git a/include/fdtdec.h b/include/fdtdec.h index e80de24076c..555c9520379 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -143,7 +143,7 @@ extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ static inline u8 *dtb_dt_embedded(void) { #ifdef CONFIG_OF_EMBED -# ifdef CONFIG_SPL_BUILD +# ifdef CONFIG_XPL_BUILD return __dtb_dt_spl_begin; # else return __dtb_dt_begin; diff --git a/include/image-android-dt.h b/include/image-android-dt.h index 9a3aa8fa30f..d255744e8cb 100644 --- a/include/image-android-dt.h +++ b/include/image-android-dt.h @@ -13,7 +13,7 @@ bool android_dt_check_header(ulong hdr_addr); bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr, u32 *size); -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) void android_dt_print_contents(ulong hdr_addr); #endif diff --git a/include/iotrace.h b/include/iotrace.h index d5610426cc8..5527c984fd2 100644 --- a/include/iotrace.h +++ b/include/iotrace.h @@ -42,7 +42,7 @@ struct iotrace_record { */ #if defined(CONFIG_IO_TRACE) && !defined(IOTRACE_IMPL) && \ - !defined(CONFIG_SPL_BUILD) + !defined(CONFIG_XPL_BUILD) #undef readl #define readl(addr) iotrace_readl((const void *)(addr)) diff --git a/include/led.h b/include/led.h index 99f93c5ef86..64247cd3a70 100644 --- a/include/led.h +++ b/include/led.h @@ -9,6 +9,47 @@ #include <stdbool.h> #include <cyclic.h> +#include <dm/ofnode.h> + +/** + * DOC: Overview + * + * Generic LED API provided when a supported compatible is defined in DeviceTree. + * + * To enable support for LEDs, enable the `CONFIG_LED` Kconfig option. + * + * The most common implementation is for GPIO-connected LEDs. If using GPIO-connected LEDs, + * enable the `LED_GPIO` Kconfig option. + * + * `LED_BLINK` support requires LED driver support and is therefore optional. If LED blink + * functionality is needed, enable the `LED_BLINK` Kconfig option. If LED driver doesn't + * support HW Blink, SW Blink can be used with the Cyclic framework by enabling the + * CONFIG_LED_SW_BLINK. + * + * Boot and Activity LEDs are also supported. These LEDs can signal various system operations + * during runtime, such as boot initialization, file transfers, and flash write/erase operations. + * + * To enable a Boot LED, enable `CONFIG_LED_BOOT` and define in `/options/u-boot` root node the + * property `boot-led`. This will enable the specified LED to blink and turn ON when + * the bootloader initializes correctly. + * + * To enable an Activity LED, enable `CONFIG_LED_ACTIVITY` and define in `/options/u-boot` root + * node the property `activity-led`. + * This will enable the specified LED to blink and turn ON during file transfers or flash + * write/erase operations. + * + * Both Boot and Activity LEDs provide a simple API to turn the LED ON or OFF: + * `led_boot_on()`, `led_boot_off()`, `led_activity_on()`, and `led_activity_off()`. + * + * Both configurations can optionally define a `boot/activity-led-period` property + * if `CONFIG_LED_BLINK` or `CONFIG_LED_SW_BLINK` is enabled for LED blink operations, which + * is usually used by the Activity LED. If not defined the default value of 250 (ms) is used. + * + * When `CONFIG_LED_BLINK` or `CONFIG_LED_SW_BLINK` is enabled, additional APIs are exposed: + * `led_boot_blink()` and `led_activity_blink()`. Note that if `CONFIG_LED_BLINK` or + * `CONFIG_LED_SW_BLINK` is disabled, these APIs will behave like the `led_boot_on()` and + * `led_activity_on()` APIs, respectively. + */ struct udevice; @@ -40,6 +81,7 @@ struct led_sw_blink { * * @label: LED label * @default_state: LED default state + * @sw_blink: LED software blink struct */ struct led_uc_plat { const char *label; @@ -52,10 +94,22 @@ struct led_uc_plat { /** * struct led_uc_priv - Private data the uclass stores about each device * - * @period_ms: Flash period in milliseconds + * @boot_led_label: Boot LED label + * @activity_led_label: Activity LED label + * @boot_led_dev: Boot LED dev + * @activity_led_dev: Activity LED dev + * @boot_led_period: Boot LED blink period + * @activity_led_period: Activity LED blink period */ struct led_uc_priv { - int period_ms; +#ifdef CONFIG_LED_BOOT + const char *boot_led_label; + int boot_led_period; +#endif +#ifdef CONFIG_LED_ACTIVITY + const char *activity_led_label; + int activity_led_period; +#endif }; struct led_ops { @@ -141,4 +195,93 @@ int led_sw_set_period(struct udevice *dev, int period_ms); bool led_sw_is_blinking(struct udevice *dev); bool led_sw_on_state_change(struct udevice *dev, enum led_state_t state); +#ifdef CONFIG_LED_BOOT + +/** + * led_boot_on() - turn ON the designated LED for booting + * + * Return: 0 if OK, -ve on error + */ +int led_boot_on(void); + +/** + * led_boot_off() - turn OFF the designated LED for booting + * + * Return: 0 if OK, -ve on error + */ +int led_boot_off(void); + +#if defined(CONFIG_LED_BLINK) || defined(CONFIG_LED_SW_BLINK) +/** + * led_boot_blink() - turn ON the designated LED for booting + * + * Return: 0 if OK, -ve on error + */ +int led_boot_blink(void); + +#else +/* If LED BLINK is not supported/enabled, fallback to LED ON */ +#define led_boot_blink led_boot_on +#endif +#else +static inline int led_boot_on(void) +{ + return -ENOSYS; +} + +static inline int led_boot_off(void) +{ + return -ENOSYS; +} + +static inline int led_boot_blink(void) +{ + return -ENOSYS; +} +#endif + +#ifdef CONFIG_LED_ACTIVITY + +/** + * led_activity_on() - turn ON the designated LED for activity + * + * Return: 0 if OK, -ve on error + */ +int led_activity_on(void); + +/** + * led_activity_off() - turn OFF the designated LED for activity + * + * Return: 0 if OK, -ve on error + */ +int led_activity_off(void); + +#if defined(CONFIG_LED_BLINK) || defined(CONFIG_LED_SW_BLINK) +/** + * led_activity_blink() - turn ON the designated LED for activity + * + * Return: 0 if OK, -ve on error + */ +int led_activity_blink(void); +#else +/* If LED BLINK is not supported/enabled, fallback to LED ON */ +#define led_activity_blink led_activity_on +#endif +#else +static inline int led_activity_on(void) +{ + return -ENOSYS; +} + +static inline int led_activity_off(void) +{ + return -ENOSYS; +} + +static inline int led_activity_blink(void) +{ + return -ENOSYS; +} +#endif + #endif diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h index 2bc704e1104..ec9584b2426 100644 --- a/include/linux/kconfig.h +++ b/include/linux/kconfig.h @@ -53,7 +53,7 @@ /* * CONFIG_VAL(FOO) evaluates to the value of * CONFIG_TOOLS_FOO if USE_HOSTCC is defined, - * CONFIG_FOO if CONFIG_SPL_BUILD is undefined, + * CONFIG_FOO if CONFIG_XPL_BUILD is undefined, * CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined. * CONFIG_TPL_FOO if CONFIG_TPL_BUILD is defined. * CONFIG_VPL_FOO if CONFIG_VPL_BUILD is defined. @@ -106,21 +106,21 @@ long invalid_use_of_IF_ENABLED_INT(void); /* * CONFIG_IS_ENABLED(FOO) expands to * 1 if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y', - * 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', + * 1 if CONFIG_XPL_BUILD is undefined and CONFIG_FOO is set to 'y', * 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', * 1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', * 0 otherwise. * * CONFIG_IS_ENABLED(FOO, (abc)) expands to * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y', - * abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', + * abc if CONFIG_XPL_BUILD is undefined and CONFIG_FOO is set to 'y', * abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', * abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', * nothing otherwise. * * CONFIG_IS_ENABLED(FOO, (abc), (def)) expands to * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y', - * abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', + * abc if CONFIG_XPL_BUILD is undefined and CONFIG_FOO is set to 'y', * abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', * abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', * def otherwise. diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d1dbf3eadbf..047e83e8463 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -13,6 +13,9 @@ #include <linux/mtd/mtd.h> #include <spi-mem.h> +/* In parallel configuration enable multiple CS */ +#define SPI_NOR_ENABLE_MULTI_CS (BIT(0) | BIT(1)) + /* * Manufacturer IDs * @@ -45,6 +48,8 @@ #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ +#define SPINOR_OP_RDSR3 0x15 /* Read status register 3 */ +#define SPINOR_OP_WRSR3 0x11 /* Write status register 3 */ #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ @@ -177,6 +182,15 @@ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) +/* + * Maximum number of flashes that can be connected + * in stacked/parallel configuration + */ +#define SNOR_FLASH_CNT_MAX 2 + +/* Status Register 3 bits. */ +#define SR3_WPS BIT(2) + /* For Cypress flash. */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ @@ -294,6 +308,13 @@ enum spi_nor_option_flags { SNOR_F_BROKEN_RESET = BIT(6), SNOR_F_SOFT_RESET = BIT(7), SNOR_F_IO_MODE_EN_VOLATILE = BIT(8), +#if defined(CONFIG_SPI_ADVANCE) + SNOR_F_HAS_STACKED = BIT(9), + SNOR_F_HAS_PARALLEL = BIT(10), +#else + SNOR_F_HAS_STACKED = 0, + SNOR_F_HAS_PARALLEL = 0, +#endif }; struct spi_nor; @@ -551,6 +572,7 @@ struct spi_nor { u8 bank_read_cmd; u8 bank_write_cmd; u8 bank_curr; + u8 upage_prev; #endif enum spi_nor_protocol read_proto; enum spi_nor_protocol write_proto; diff --git a/include/log.h b/include/log.h index 7c25bf0b081..bf81a27011f 100644 --- a/include/log.h +++ b/include/log.h @@ -246,10 +246,10 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, #define _DEBUG 0 #endif -#ifdef CONFIG_SPL_BUILD -#define _SPL_BUILD 1 +#ifdef CONFIG_XPL_BUILD +#define _XPL_BUILD 1 #else -#define _SPL_BUILD 0 +#define _XPL_BUILD 0 #endif #if CONFIG_IS_ENABLED(LOG) @@ -281,9 +281,9 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, #define debug(fmt, args...) \ debug_cond(_DEBUG, fmt, ##args) -/* Show a message if not in SPL */ -#define warn_non_spl(fmt, args...) \ - debug_cond(!_SPL_BUILD, fmt, ##args) +/* Show a message if not in xPL */ +#define warn_non_xpl(fmt, args...) \ + debug_cond(!_XPL_BUILD, fmt, ##args) /* * An assertion is run-time check done in debug mode only. If DEBUG is not diff --git a/include/mmc.h b/include/mmc.h index 0044ff8bef7..e4b960b7294 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -726,7 +726,7 @@ struct mmc { u64 capacity_boot; u64 capacity_rpmb; u64 capacity_gp[4]; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD u64 enh_user_start; u64 enh_user_size; #endif diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index f4aecaac75f..be292e3ceb2 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -163,7 +163,7 @@ struct cfi_pri_hdr { #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) /* map to cfi_flash_num_flash_banks only when supported */ #if IS_ENABLED(CONFIG_FLASH_CFI_DRIVER) && \ - (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD)) + (!IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD)) #define CFI_FLASH_BANKS (cfi_flash_num_flash_banks) /* board code can update this variable before CFI detection */ extern int cfi_flash_num_flash_banks; diff --git a/include/net.h b/include/net.h index bb2ae20f52a..dc8b5e9cc34 100644 --- a/include/net.h +++ b/include/net.h @@ -683,7 +683,7 @@ int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, /* Processes a received packet */ void net_process_received_packet(uchar *in_packet, int len); -#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD) void nc_start(void); int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port, unsigned src_port, unsigned len); @@ -691,7 +691,7 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port, static __always_inline int eth_is_on_demand_init(void) { -#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD) extern enum proto_t net_loop_last_protocol; return net_loop_last_protocol != NETCONS; @@ -702,7 +702,7 @@ static __always_inline int eth_is_on_demand_init(void) static inline void eth_set_last_protocol(int protocol) { -#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD) extern enum proto_t net_loop_last_protocol; net_loop_last_protocol = protocol; diff --git a/include/part.h b/include/part.h index 797b542ef1f..92662677551 100644 --- a/include/part.h +++ b/include/part.h @@ -439,7 +439,7 @@ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt); * We don't support printing partition information in SPL and only support * getting partition information in a few cases. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD # define part_print_ptr(x) NULL # if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \ defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION) diff --git a/include/power/mp5416.h b/include/power/mp5416.h index dc096fed3f2..4326baaa42a 100644 --- a/include/power/mp5416.h +++ b/include/power/mp5416.h @@ -32,7 +32,7 @@ enum { #define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000) #define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) #define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) -#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_LDO_SVAL(x) (((x) - 800000) / 25000) #define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500) #define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000) #define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500) diff --git a/include/power/pca9450.h b/include/power/pca9450.h index f896d829d37..e5ab09fb8c8 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -62,6 +62,7 @@ enum { NXP_CHIP_TYPE_PCA9450A = 0, NXP_CHIP_TYPE_PCA9450BC, NXP_CHIP_TYPE_PCA9451A, + NXP_CHIP_TYPE_PCA9452, NXP_CHIP_TYPE_AMOUNT }; diff --git a/include/sdp.h b/include/sdp.h index 5492f9c47d2..0a97f28073a 100644 --- a/include/sdp.h +++ b/include/sdp.h @@ -11,7 +11,7 @@ int sdp_init(struct udevice *udc); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <spl.h> int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image, diff --git a/include/search.h b/include/search.h index 7faf23f4aca..3952198a0df 100644 --- a/include/search.h +++ b/include/search.h @@ -29,7 +29,7 @@ enum env_action { struct env_entry { const char *key; char *data; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int (*callback)(const char *name, const char *value, enum env_op op, int flags); #endif diff --git a/include/spi.h b/include/spi.h index 9e9851284c8..3a92d02f215 100644 --- a/include/spi.h +++ b/include/spi.h @@ -38,6 +38,18 @@ #define SPI_DEFAULT_WORDLEN 8 +#define SPI_3BYTE_MODE 0x0 +#define SPI_4BYTE_MODE 0x1 + +/* SPI transfer flags */ +#define SPI_XFER_STRIPE (1 << 6) +#define SPI_XFER_MASK (3 << 8) +#define SPI_XFER_LOWER (1 << 8) +#define SPI_XFER_UPPER (2 << 8) + +/* Max no. of CS supported per spi device */ +#define SPI_CS_CNT_MAX 2 + /** * struct dm_spi_bus - SPI bus info * @@ -71,7 +83,7 @@ struct dm_spi_bus { * @mode: SPI mode to use for this device (see SPI mode flags) */ struct dm_spi_slave_plat { - unsigned int cs; + unsigned int cs[SPI_CS_CNT_MAX]; uint max_hz; uint mode; }; @@ -155,6 +167,15 @@ struct spi_slave { #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) +#define SPI_XFER_U_PAGE BIT(4) +#define SPI_XFER_STACKED BIT(5) + /* + * Flag indicating that the spi-controller has multi chip select + * capability and can assert/de-assert more than one chip select + * at once. + */ + bool multi_cs_cap; + u32 bytemode; }; /** diff --git a/include/spl.h b/include/spl.h index de808ccd413..269e36bb441 100644 --- a/include/spl.h +++ b/include/spl.h @@ -34,24 +34,26 @@ struct spl_boot_device; enum boot_device; /* - * u_boot_first_phase() - check if this is the first U-Boot phase + * xpl_is_first_phase() - check if this is the first U-Boot phase * - * U-Boot has up to three phases: TPL, SPL and U-Boot proper. Depending on the - * build flags we can determine whether the current build is for the first + * U-Boot has up to four phases: TPL, VPL, SPL and U-Boot proper. Depending on + * the build flags we can determine whether the current build is for the first * phase of U-Boot or not. If there is no SPL, then this is U-Boot proper. If * there is SPL but no TPL, the the first phase is SPL. If there is TPL, then - * it is the first phase. + * it is the first phase, etc. * - * @returns true if this is the first phase of U-Boot + * Note that VPL can never be the first phase. If it exists, it is loaded from + * TPL * + * Return: true if this is the first phase of U-Boot */ -static inline bool u_boot_first_phase(void) +static inline bool xpl_is_first_phase(void) { if (IS_ENABLED(CONFIG_TPL)) { if (IS_ENABLED(CONFIG_TPL_BUILD)) return true; } else if (IS_ENABLED(CONFIG_SPL)) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return true; } else { return true; @@ -60,7 +62,7 @@ static inline bool u_boot_first_phase(void) return false; } -enum u_boot_phase { +enum xpl_phase_t { PHASE_NONE, /* Invalid phase, signifying before U-Boot */ PHASE_TPL, /* Running in TPL */ PHASE_VPL, /* Running in VPL */ @@ -72,7 +74,7 @@ enum u_boot_phase { }; /** - * spl_phase() - Find out the phase of U-Boot + * xpl_phase() - Find out the phase of U-Boot * * This can be used to avoid #ifdef logic and use if() instead. * @@ -84,43 +86,43 @@ enum u_boot_phase { * * but with this you can use: * - * if (spl_phase() == PHASE_TPL) { + * if (xpl_phase() == PHASE_TPL) { * ... * } * * To include code only in SPL, you might do: * - * #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) + * #if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) * ... * #endif * * but with this you can use: * - * if (spl_phase() == PHASE_SPL) { + * if (xpl_phase() == PHASE_SPL) { * ... * } * * To include code only in U-Boot proper, you might do: * - * #ifndef CONFIG_SPL_BUILD + * #ifndef CONFIG_XPL_BUILD * ... * #endif * * but with this you can use: * - * if (spl_phase() == PHASE_BOARD_F) { + * if (xpl_phase() == PHASE_BOARD_F) { * ... * } * * Return: U-Boot phase */ -static inline enum u_boot_phase spl_phase(void) +static inline enum xpl_phase_t xpl_phase(void) { #ifdef CONFIG_TPL_BUILD return PHASE_TPL; #elif defined(CONFIG_VPL_BUILD) return PHASE_VPL; -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) return PHASE_SPL; #else DECLARE_GLOBAL_DATA_PTR; @@ -132,29 +134,39 @@ static inline enum u_boot_phase spl_phase(void) #endif } -/* returns true if in U-Boot proper, false if in SPL */ -static inline bool spl_in_proper(void) +/* returns true if in U-Boot proper, false if in xPL */ +static inline bool not_xpl(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD return false; #endif return true; } +/* returns true if in xPL, false if in U-Boot proper */ +static inline bool is_xpl(void) +{ +#ifdef CONFIG_XPL_BUILD + return true; +#endif + + return false; +} + /** - * spl_prev_phase() - Figure out the previous U-Boot phase + * xpl_prev_phase() - Figure out the previous U-Boot phase * * Return: the previous phase from this one, e.g. if called in SPL this returns * PHASE_TPL, if TPL is enabled */ -static inline enum u_boot_phase spl_prev_phase(void) +static inline enum xpl_phase_t xpl_prev_phase(void) { #ifdef CONFIG_TPL_BUILD return PHASE_NONE; #elif defined(CONFIG_VPL_BUILD) return PHASE_TPL; /* VPL requires TPL */ -#elif defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_XPL_BUILD) return IS_ENABLED(CONFIG_VPL) ? PHASE_VPL : IS_ENABLED(CONFIG_TPL) ? PHASE_TPL : PHASE_NONE; @@ -165,12 +177,12 @@ static inline enum u_boot_phase spl_prev_phase(void) } /** - * spl_next_phase() - Figure out the next U-Boot phase + * xpl_next_phase() - Figure out the next U-Boot phase * * Return: the next phase from this one, e.g. if called in TPL this returns * PHASE_SPL */ -static inline enum u_boot_phase spl_next_phase(void) +static inline enum xpl_phase_t xpl_next_phase(void) { #ifdef CONFIG_TPL_BUILD return IS_ENABLED(CONFIG_VPL) ? PHASE_VPL : PHASE_SPL; @@ -182,11 +194,11 @@ static inline enum u_boot_phase spl_next_phase(void) } /** - * spl_phase_name() - Get the name of the current phase + * xpl_name() - Get the name of a phase * * Return: phase name */ -static inline const char *spl_phase_name(enum u_boot_phase phase) +static inline const char *xpl_name(enum xpl_phase_t phase) { switch (phase) { case PHASE_TPL: @@ -204,12 +216,12 @@ static inline const char *spl_phase_name(enum u_boot_phase phase) } /** - * spl_phase_prefix() - Get the prefix of the current phase + * xpl_prefix() - Get the prefix of the current phase * * @phase: Phase to look up * Return: phase prefix ("spl", "tpl", etc.) */ -static inline const char *spl_phase_prefix(enum u_boot_phase phase) +static inline const char *xpl_prefix(enum xpl_phase_t phase) { switch (phase) { case PHASE_TPL: @@ -227,18 +239,18 @@ static inline const char *spl_phase_prefix(enum u_boot_phase phase) } /* A string name for SPL or TPL */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD # ifdef CONFIG_TPL_BUILD -# define SPL_TPL_NAME "TPL" +# define PHASE_NAME "TPL" # elif defined(CONFIG_VPL_BUILD) -# define SPL_TPL_NAME "VPL" -# else -# define SPL_TPL_NAME "SPL" +# define PHASE_NAME "VPL" +# elif defined(CONFIG_SPL_BUILD) +# define PHASE_NAME "SPL" # endif -# define SPL_TPL_PROMPT SPL_TPL_NAME ": " +# define PHASE_PROMPT PHASE_NAME ": " #else -# define SPL_TPL_NAME "" -# define SPL_TPL_PROMPT "" +# define PHASE_NAME "" +# define PHASE_PROMPT "" #endif /** diff --git a/include/spl_gpio.h b/include/spl_gpio.h index e39ac3f624b..b33261a6485 100644 --- a/include/spl_gpio.h +++ b/include/spl_gpio.h @@ -59,4 +59,23 @@ int spl_gpio_output(void *regs, uint gpio, int value); */ int spl_gpio_input(void *regs, uint gpio); +/** + * spl_gpio_get_value() - Get GPIO value + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * Return: return GPIO value if OK, -ve on error + */ +int spl_gpio_get_value(void *regs, uint gpio); + +/** + * spl_gpio_set_value() - Set value on GPIO + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @value: 0 to set the output low, 1 to set it high + * Return: return 0 if OK, -ve on error + */ +int spl_gpio_set_value(void *regs, uint gpio, int value); + #endif /* __SPL_GPIO_H */ diff --git a/include/status_led.h b/include/status_led.h index 6707ab1d29d..1282022253e 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -39,6 +39,13 @@ void status_led_init(void); void status_led_tick(unsigned long timestamp); void status_led_set(int led, int state); +static inline void status_led_boot_blink(void) +{ +#ifdef CONFIG_LED_STATUS_BOOT_ENABLE + status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_BLINKING); +#endif +} + /***** MVS v1 **********************************************************/ #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) # define STATUS_LED_PAR im_ioport.iop_pdpar @@ -72,6 +79,12 @@ void __led_blink(led_id_t mask, int freq); # include <asm/status_led.h> #endif +#else + +static inline void status_led_init(void) { } +static inline void status_led_set(int led, int state) { } +static inline void status_led_boot_blink(void) { } + #endif /* CONFIG_LED_STATUS */ /* diff --git a/include/stdio.h b/include/stdio.h index 7b999a519ba..d42fdd2728c 100644 --- a/include/stdio.h +++ b/include/stdio.h @@ -9,10 +9,7 @@ int getchar(void); int tstc(void); /* stdout */ -#if !defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL)) || \ - (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && \ - defined(CONFIG_SPL_SERIAL)) +#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(SERIAL) void putc(const char c); void puts(const char *s); #ifdef CONFIG_CONSOLE_FLUSH_SUPPORT diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index db3742c0397..122987c395e 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -206,7 +206,7 @@ void sunxi_gpio_set_pull(u32 pin, u32 val); void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val); int sunxi_name_to_gpio(const char *name); -#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO +#if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO int axp_gpio_init(void); #else static inline int axp_gpio_init(void) { return 0; } diff --git a/include/upl.h b/include/upl.h index 2ec5ef1b5cf..4d0eca88047 100644 --- a/include/upl.h +++ b/include/upl.h @@ -320,7 +320,7 @@ int upl_read_handoff(struct upl *upl, oftree tree); int upl_get_test_data(struct unit_test_state *uts, struct upl *upl); #endif /* USE_HOSTCC */ -#if CONFIG_IS_ENABLED(UPL) && defined(CONFIG_SPL_BUILD) +#if CONFIG_IS_ENABLED(UPL) && defined(CONFIG_XPL_BUILD) /** * upl_set_fit_info() - Set up basic info about the FIT @@ -367,7 +367,7 @@ int _upl_add_image(int node, ulong load_addr, ulong size, const char *desc); static inline int upl_add_image(const void *fit, int node, ulong load_addr, ulong size) { - if (CONFIG_IS_ENABLED(UPL) && IS_ENABLED(CONFIG_SPL_BUILD)) { + if (CONFIG_IS_ENABLED(UPL) && IS_ENABLED(CONFIG_XPL_BUILD)) { const char *desc = fdt_getprop(fit, node, FIT_DESC_PROP, NULL); return _upl_add_image(node, load_addr, size, desc); diff --git a/include/vbe.h b/include/vbe.h index 5ede8181b98..56bff63362f 100644 --- a/include/vbe.h +++ b/include/vbe.h @@ -41,7 +41,7 @@ struct vbe_handoff { */ static inline enum vbe_phase_t vbe_phase(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return VBE_PHASE_FIRMWARE; return VBE_PHASE_OS; diff --git a/lib/Makefile b/lib/Makefile index 561e0d44a16..3fc428cff1d 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_EFI_LOADER) += efi_driver/ @@ -20,7 +20,7 @@ obj-$(CONFIG_OPTEE_LIB) += optee/ obj-$(CONFIG_AES) += aes.o obj-$(CONFIG_AES) += aes/ -obj-$(CONFIG_$(SPL_TPL_)BINMAN_FDT) += binman.o +obj-$(CONFIG_$(PHASE_)BINMAN_FDT) += binman.o ifndef API_BUILD ifneq ($(CONFIG_CHARSET),) @@ -55,8 +55,8 @@ obj-$(CONFIG_BITREVERSE) += bitrev.o obj-y += list_sort.o endif -obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm-common.o -ifeq ($(CONFIG_$(SPL_TPL_)TPM),y) +obj-$(CONFIG_$(PHASE_)TPM) += tpm-common.o +ifeq ($(CONFIG_$(PHASE_)TPM),y) obj-$(CONFIG_TPM) += tpm_api.o obj-$(CONFIG_TPM_V1) += tpm-v1.o obj-$(CONFIG_TPM_V2) += tpm-v2.o @@ -64,44 +64,44 @@ obj-$(CONFIG_EFI_TCG2_PROTOCOL) += tpm_tcg2.o obj-$(CONFIG_MEASURED_BOOT) += tpm_tcg2.o endif -obj-$(CONFIG_$(SPL_TPL_)CRC8) += crc8.o -obj-$(CONFIG_$(SPL_TPL_)CRC16) += crc16.o +obj-$(CONFIG_$(PHASE_)CRC8) += crc8.o +obj-$(CONFIG_$(PHASE_)CRC16) += crc16.o obj-y += crypto/ -obj-$(CONFIG_$(SPL_TPL_)ACPI) += acpi/ +obj-$(CONFIG_$(PHASE_)ACPI) += acpi/ obj-$(CONFIG_ECDSA) += ecdsa/ -obj-$(CONFIG_$(SPL_)RSA) += rsa/ +obj-$(CONFIG_$(XPL_)RSA) += rsa/ obj-$(CONFIG_HASH) += hash-checksum.o obj-$(CONFIG_BLAKE2) += blake2/blake2b.o -obj-$(CONFIG_$(SPL_)MD5_LEGACY) += md5.o -obj-$(CONFIG_$(SPL_)SHA1_LEGACY) += sha1.o -obj-$(CONFIG_$(SPL_)SHA256_LEGACY) += sha256.o -obj-$(CONFIG_$(SPL_)SHA512_LEGACY) += sha512.o +obj-$(CONFIG_$(XPL_)MD5_LEGACY) += md5.o +obj-$(CONFIG_$(XPL_)SHA1_LEGACY) += sha1.o +obj-$(CONFIG_$(XPL_)SHA256_LEGACY) += sha256.o +obj-$(CONFIG_$(XPL_)SHA512_LEGACY) += sha512.o obj-$(CONFIG_CRYPT_PW) += crypt/ -obj-$(CONFIG_$(SPL_)ASN1_DECODER_LEGACY) += asn1_decoder.o +obj-$(CONFIG_$(XPL_)ASN1_DECODER_LEGACY) += asn1_decoder.o -obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ -obj-$(CONFIG_$(SPL_)ZSTD) += zstd/ -obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o -obj-$(CONFIG_$(SPL_)LZO) += lzo/ -obj-$(CONFIG_$(SPL_)LZMA) += lzma/ -obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o +obj-$(CONFIG_$(XPL_)ZLIB) += zlib/ +obj-$(CONFIG_$(XPL_)ZSTD) += zstd/ +obj-$(CONFIG_$(XPL_)GZIP) += gunzip.o +obj-$(CONFIG_$(XPL_)LZO) += lzo/ +obj-$(CONFIG_$(XPL_)LZMA) += lzma/ +obj-$(CONFIG_$(XPL_)LZ4) += lz4_wrapper.o -obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o +obj-$(CONFIG_$(XPL_)LIB_RATIONAL) += rational.o obj-$(CONFIG_LIBAVB) += libavb/ -obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ -obj-$(CONFIG_$(SPL_TPL_)OF_REAL) += fdtdec_common.o fdtdec.o +obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += libfdt/ +obj-$(CONFIG_$(PHASE_)OF_REAL) += fdtdec_common.o fdtdec.o obj-$(CONFIG_MBEDTLS_LIB) += mbedtls/ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16-ccitt.o -obj-$(CONFIG_$(SPL_TPL_)HASH) += crc16-ccitt.o +obj-$(CONFIG_$(PHASE_)HASH) += crc16-ccitt.o obj-$(CONFIG_MMC_SPI_CRC_ON) += crc16-ccitt.o obj-y += net_utils.o endif @@ -113,15 +113,15 @@ obj-y += display_options.o CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"') obj-$(CONFIG_BCH) += bch.o obj-$(CONFIG_MMC_SPI) += crc7.o -obj-$(CONFIG_$(SPL_TPL_)CRC32) += crc32.o +obj-$(CONFIG_$(PHASE_)CRC32) += crc32.o obj-$(CONFIG_CRC32C) += crc32c.o obj-y += ctype.o obj-y += div64.o -obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdtdec.o fdtdec_common.o +obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += fdtdec.o fdtdec_common.o obj-y += hang.o obj-y += linux_compat.o obj-y += linux_string.o -obj-$(CONFIG_$(SPL_TPL_)LMB) += lmb.o +obj-$(CONFIG_$(PHASE_)LMB) += lmb.o obj-y += membuff.o obj-$(CONFIG_REGEX) += slre.o obj-y += string.o @@ -134,20 +134,20 @@ obj-$(CONFIG_LIB_UUID) += uuid.o obj-$(CONFIG_LIB_RAND) += rand.o obj-y += panic.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) # SPL U-Boot may use full-printf, tiny-printf or none at all -ifdef CONFIG_$(SPL_TPL_)USE_TINY_PRINTF -obj-$(CONFIG_$(SPL_TPL_)SPRINTF) += tiny-printf.o +ifdef CONFIG_$(PHASE_)USE_TINY_PRINTF +obj-$(CONFIG_$(PHASE_)SPRINTF) += tiny-printf.o else -obj-$(CONFIG_$(SPL_TPL_)SPRINTF) += vsprintf.o +obj-$(CONFIG_$(PHASE_)SPRINTF) += vsprintf.o endif -obj-$(CONFIG_$(SPL_TPL_)STRTO) += strto.o +obj-$(CONFIG_$(PHASE_)STRTO) += strto.o else # Main U-Boot always uses the full printf support obj-y += vsprintf.o strto.o obj-$(CONFIG_SSCANF) += sscanf.o endif -obj-$(CONFIG_$(SPL_)OID_REGISTRY) += oid_registry.o +obj-$(CONFIG_$(XPL_)OID_REGISTRY) += oid_registry.o obj-y += abuf.o obj-y += alist.o @@ -155,7 +155,7 @@ obj-y += date.o obj-y += rtc-lib.o obj-$(CONFIG_LIB_ELF) += elf.o -obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o +obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o # # Build a fast OID lookup registry from include/linux/oid_registry.h diff --git a/lib/acpi/Makefile b/lib/acpi/Makefile index cc2868488a0..dcca0c67268 100644 --- a/lib/acpi/Makefile +++ b/lib/acpi/Makefile @@ -3,12 +3,12 @@ obj-y += acpi.o -ifdef CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE +ifdef CONFIG_$(PHASE_)GENERATE_ACPI_TABLE -obj-$(CONFIG_$(SPL_)ACPIGEN) += acpigen.o -obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_device.o -obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_dp.o -obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_table.o +obj-$(CONFIG_$(XPL_)ACPIGEN) += acpigen.o +obj-$(CONFIG_$(XPL_)ACPIGEN) += acpi_device.o +obj-$(CONFIG_$(XPL_)ACPIGEN) += acpi_dp.o +obj-$(CONFIG_$(XPL_)ACPIGEN) += acpi_table.o obj-y += acpi_writer.o # With QEMU the ACPI tables come from there, not from U-Boot diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c index ed94194346d..0f3044bca79 100644 --- a/lib/acpi/acpi_device.c +++ b/lib/acpi/acpi_device.c @@ -728,7 +728,7 @@ static int acpi_device_set_spi(const struct udevice *dev, struct acpi_spi *spi, plat = dev_get_parent_plat(slave->dev); memset(spi, '\0', sizeof(*spi)); - spi->device_select = plat->cs; + spi->device_select = plat->cs[0]; spi->device_select_polarity = SPI_POLARITY_LOW; spi->wire_mode = SPI_4_WIRE_MODE; spi->speed = plat->max_hz; diff --git a/lib/aes/Makefile b/lib/aes/Makefile index daed52a713b..ad6228a7dad 100644 --- a/lib/aes/Makefile +++ b/lib/aes/Makefile @@ -2,4 +2,4 @@ # # Copyright (c) 2019, Softathome -obj-$(CONFIG_$(SPL_)FIT_CIPHER) += aes-decrypt.o +obj-$(CONFIG_$(XPL_)FIT_CIPHER) += aes-decrypt.o diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile index 72b413d85a9..b729824df3c 100644 --- a/lib/crypto/Makefile +++ b/lib/crypto/Makefile @@ -3,37 +3,37 @@ # Makefile for asymmetric cryptographic keys # -obj-$(CONFIG_$(SPL_)ASYMMETRIC_KEY_TYPE) += asymmetric_keys.o +obj-$(CONFIG_$(XPL_)ASYMMETRIC_KEY_TYPE) += asymmetric_keys.o asymmetric_keys-y := asymmetric_type.o -obj-$(CONFIG_$(SPL_)ASYMMETRIC_PUBLIC_KEY_SUBTYPE) += public_key_helper.o -obj-$(CONFIG_$(SPL_)ASYMMETRIC_PUBLIC_KEY_LEGACY) += public_key.o +obj-$(CONFIG_$(XPL_)ASYMMETRIC_PUBLIC_KEY_SUBTYPE) += public_key_helper.o +obj-$(CONFIG_$(XPL_)ASYMMETRIC_PUBLIC_KEY_LEGACY) += public_key.o # # RSA public key parser # -obj-$(CONFIG_$(SPL_)RSA_PUBLIC_KEY_PARSER_LEGACY) += rsa_public_key.o +obj-$(CONFIG_$(XPL_)RSA_PUBLIC_KEY_PARSER_LEGACY) += rsa_public_key.o rsa_public_key-y := \ rsapubkey.asn1.o \ rsa_helper.o $(obj)/rsapubkey.asn1.o: $(obj)/rsapubkey.asn1.c $(obj)/rsapubkey.asn1.h -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD CFLAGS_rsapubkey.asn1.o += -I$(obj) endif $(obj)/rsa_helper.o: $(obj)/rsapubkey.asn1.h -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD CFLAGS_rsa_helper.o += -I$(obj) endif # # X.509 Certificate handling # -obj-$(CONFIG_$(SPL_)X509_CERTIFICATE_PARSER) += x509_key_parser.o +obj-$(CONFIG_$(XPL_)X509_CERTIFICATE_PARSER) += x509_key_parser.o x509_key_parser-y := x509_helper.o -x509_key_parser-$(CONFIG_$(SPL_)X509_CERTIFICATE_PARSER_LEGACY) += \ +x509_key_parser-$(CONFIG_$(XPL_)X509_CERTIFICATE_PARSER_LEGACY) += \ x509.asn1.o \ x509_akid.asn1.o \ x509_cert_parser.o \ @@ -49,7 +49,7 @@ $(obj)/x509_akid.asn1.o: $(obj)/x509_akid.asn1.c $(obj)/x509_akid.asn1.h # # PKCS#7 message handling # -obj-$(CONFIG_$(SPL_)PKCS7_MESSAGE_PARSER) += pkcs7_message.o +obj-$(CONFIG_$(XPL_)PKCS7_MESSAGE_PARSER) += pkcs7_message.o pkcs7_message-y := pkcs7_helper.o pkcs7_message-$(CONFIG_$(SPL_)PKCS7_MESSAGE_PARSER_LEGACY) += \ pkcs7.asn1.o \ @@ -58,12 +58,12 @@ pkcs7_message-$(CONFIG_$(SPL_)PKCS7_MESSAGE_PARSER_LEGACY) += \ $(obj)/pkcs7_parser.o: $(obj)/pkcs7.asn1.h $(obj)/pkcs7.asn1.o: $(obj)/pkcs7.asn1.c $(obj)/pkcs7.asn1.h -obj-$(CONFIG_$(SPL_)PKCS7_VERIFY) += pkcs7_verify.o +obj-$(CONFIG_$(XPL_)PKCS7_VERIFY) += pkcs7_verify.o # # Signed PE binary-wrapped key handling # -obj-$(CONFIG_$(SPL_)MSCODE_PARSER_LEGACY) += mscode.o +obj-$(CONFIG_$(XPL_)MSCODE_PARSER_LEGACY) += mscode.o mscode-y := \ mscode_parser.o \ diff --git a/lib/display_options.c b/lib/display_options.c index d5df53ab15f..2c15cc5b5c4 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -236,7 +236,7 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, addr += thislinelen * width; count -= thislinelen; - if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) + if (!IS_ENABLED(CONFIG_XPL_BUILD) && ctrlc()) return -EINTR; } diff --git a/lib/ecdsa/Makefile b/lib/ecdsa/Makefile index 771d6d3135b..32b6183f6ff 100644 --- a/lib/ecdsa/Makefile +++ b/lib/ecdsa/Makefile @@ -1 +1 @@ -obj-$(CONFIG_$(SPL_)ECDSA_VERIFY) += ecdsa-verify.o +obj-$(CONFIG_$(XPL_)ECDSA_VERIFY) += ecdsa-verify.o diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e58b8825605..6f6fa8d629d 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -552,6 +552,18 @@ config EFI_HTTP_BOOT directly boot from network. endmenu +config BOOTEFI_HELLO_COMPILE + bool "Compile a standard EFI hello world binary for testing" + default y + help + This compiles a standard EFI hello world application with U-Boot so + that it can be used with the test/py testing framework. This is useful + for testing that EFI is working at a basic level, and for bringing + up EFI support on a new architecture. + + No additional space will be required in the resulting U-Boot binary + when this option is enabled. + endif source "lib/efi/Kconfig" diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 2af6f2066b5..00d18966f9e 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -11,40 +11,14 @@ asflags-y += -I. CFLAGS_efi_boottime.o += \ -DFW_VERSION="0x$(VERSION)" \ -DFW_PATCHLEVEL="0x$(PATCHLEVEL)" -CFLAGS_boothart.o := $(CFLAGS_EFI) -Os -ffreestanding -CFLAGS_REMOVE_boothart.o := $(CFLAGS_NON_EFI) -CFLAGS_helloworld.o := $(CFLAGS_EFI) -Os -ffreestanding -CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI) -CFLAGS_smbiosdump.o := $(CFLAGS_EFI) -Os -ffreestanding -CFLAGS_REMOVE_smbiosdump.o := $(CFLAGS_NON_EFI) -CFLAGS_dtbdump.o := $(CFLAGS_EFI) -Os -ffreestanding -CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI) -CFLAGS_initrddump.o := $(CFLAGS_EFI) -Os -ffreestanding -CFLAGS_REMOVE_initrddump.o := $(CFLAGS_NON_EFI) - -ifdef CONFIG_RISCV -always += boothart.efi -targets += boothart.o -endif - -ifneq ($(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),) -always += helloworld.efi -targets += helloworld.o -endif - -ifneq ($(CONFIG_GENERATE_SMBIOS_TABLE),) -always += smbiosdump.efi -targets += smbiosdump.o -endif +# These are the apps that are built +apps-$(CONFIG_RISCV) += boothart +apps-$(CONFIG_BOOTEFI_HELLO_COMPILE) += helloworld +apps-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbiosdump +apps-$(CONFIG_EFI_LOAD_FILE2_INITRD) += initrddump ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) -always += dtbdump.efi -targets += dtbdump.o -endif - -ifdef CONFIG_EFI_LOAD_FILE2_INITRD -always += initrddump.efi -targets += initrddump.o +apps-y += dtbdump endif obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o @@ -95,3 +69,11 @@ obj-$(CONFIG_EFI_ECPT) += efi_conformance.o EFI_VAR_SEED_FILE := $(subst $\",,$(CONFIG_EFI_VAR_SEED_FILE)) $(obj)/efi_var_seed.o: $(srctree)/$(EFI_VAR_SEED_FILE) + +# Set the C flags to add and remove for each app +$(foreach f,$(apps-y),\ + $(eval CFLAGS_$(f).o := $(CFLAGS_EFI) -Os -ffreestanding)\ + $(eval CFLAGS_REMOVE_$(f).o := $(CFLAGS_NON_EFI))) + +always += $(foreach f,$(apps-y),$(f).efi) +targets += $(foreach f,$(apps-y),$(f).o) diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c index 9d017804eea..0dac94b0c6c 100644 --- a/lib/efi_loader/efi_dt_fixup.c +++ b/lib/efi_loader/efi_dt_fixup.c @@ -41,7 +41,7 @@ static void efi_reserve_memory(u64 addr, u64 size, bool nomap) } /** - * efi_try_purge_kaslr_seed() - Remove unused kaslr-seed + * efi_try_purge_rng_seed() - Remove unused kaslr-seed, rng-seed * * Kernel's EFI STUB only relies on EFI_RNG_PROTOCOL for randomization * and completely ignores the kaslr-seed for its own randomness needs @@ -51,8 +51,9 @@ static void efi_reserve_memory(u64 addr, u64 size, bool nomap) * * @fdt: Pointer to device tree */ -void efi_try_purge_kaslr_seed(void *fdt) +void efi_try_purge_rng_seed(void *fdt) { + const char * const prop[] = {"kaslr-seed", "rng-seed"}; const efi_guid_t efi_guid_rng_protocol = EFI_RNG_PROTOCOL_GUID; struct efi_handler *handler; efi_status_t ret; @@ -67,9 +68,13 @@ void efi_try_purge_kaslr_seed(void *fdt) if (nodeoff < 0) return; - err = fdt_delprop(fdt, nodeoff, "kaslr-seed"); - if (err < 0 && err != -FDT_ERR_NOTFOUND) - log_err("Error deleting kaslr-seed\n"); + for (size_t i = 0; i < ARRAY_SIZE(prop); ++i) { + err = fdt_delprop(fdt, nodeoff, prop[i]); + if (err < 0 && err != -FDT_ERR_NOTFOUND) + log_err("Error deleting %s\n", prop[i]); + else + log_debug("Deleted /chosen/%s\n", prop[i]); + } } /** diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c index 96f847652ec..a481eb4b7e3 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c @@ -522,7 +522,7 @@ efi_status_t efi_install_fdt(void *fdt) /* Create memory reservations as indicated by the device tree */ efi_carve_out_dt_rsv(fdt); - efi_try_purge_kaslr_seed(fdt); + efi_try_purge_rng_seed(fdt); if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) { ret = efi_tcg2_measure_dtb(fdt); diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c index 586177de0c8..d10a5229f74 100644 --- a/lib/efi_loader/helloworld.c +++ b/lib/efi_loader/helloworld.c @@ -72,6 +72,33 @@ static void uint2dec(u32 value, u16 **buf) } /** + * Print an unsigned 32bit value as hexadecimal number to an u16 string + * + * @value: value to be printed + * @buf: pointer to buffer address + * on return position of terminating zero word + */ +static void uint2hex(u32 value, u16 **buf) +{ + u16 *pos = *buf; + int i; + u16 c; + + for (i = 0; i < 8; ++i) { + /* Write current digit */ + c = value >> 28; + value <<= 4; + if (c < 10) + c += '0'; + else + c += 'a' - 10; + *pos++ = c; + } + *pos = 0; + *buf = pos; +} + +/** * print_uefi_revision() - print UEFI revision number */ static void print_uefi_revision(void) @@ -96,6 +123,16 @@ static void print_uefi_revision(void) con_out->output_string(con_out, u"Running on UEFI "); con_out->output_string(con_out, rev); con_out->output_string(con_out, u"\r\n"); + + con_out->output_string(con_out, u"Firmware vendor: "); + con_out->output_string(con_out, systable->fw_vendor); + con_out->output_string(con_out, u"\r\n"); + + buf = rev; + uint2hex(systable->fw_revision, &buf); + con_out->output_string(con_out, u"Firmware revision: "); + con_out->output_string(con_out, rev); + con_out->output_string(con_out, u"\r\n"); } /** diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 106bb406365..85f4426f904 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -608,7 +608,7 @@ int fdtdec_get_chosen_node(const void *blob, const char *name) static int fdtdec_prepare_fdt(const void *blob) { if (!blob || ((uintptr_t)blob & 3) || fdt_check_header(blob)) { - if (spl_phase() <= PHASE_SPL) { + if (xpl_phase() <= PHASE_SPL) { puts("Missing DTB\n"); } else { printf("No valid device tree binary found at %p\n", @@ -1230,7 +1230,7 @@ static void *fdt_find_separate(void) if (IS_ENABLED(CONFIG_SANDBOX)) return NULL; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* FDT is at end of BSS unless it is in a different memory region */ if (CONFIG_IS_ENABLED(SEPARATE_BSS)) fdt_blob = (ulong *)_image_binary_end; @@ -1676,7 +1676,7 @@ int fdtdec_setup(void) * not whether this phase creates one. */ if (CONFIG_IS_ENABLED(BLOBLIST) && - (spl_prev_phase() != PHASE_TPL || + (xpl_prev_phase() != PHASE_TPL || !IS_ENABLED(CONFIG_TPL_BLOBLIST))) { ret = bloblist_maybe_init(); if (!ret) { @@ -1714,7 +1714,7 @@ int fdtdec_setup(void) } /* Allow the early environment to override the fdt address */ - if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { ulong addr; addr = env_get_hex("fdtcontroladdr", 0); diff --git a/lib/hang.c b/lib/hang.c index 3cfb06e9ca8..f3c3c896f0a 100644 --- a/lib/hang.c +++ b/lib/hang.c @@ -22,7 +22,7 @@ */ void hang(void) { -#if !defined(CONFIG_SPL_BUILD) || \ +#if !defined(CONFIG_XPL_BUILD) || \ (CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && \ CONFIG_IS_ENABLED(SERIAL)) puts("### ERROR ### Please RESET the board ###\n"); diff --git a/lib/hashtable.c b/lib/hashtable.c index 9613adc5540..e8a59e2dcac 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -221,7 +221,7 @@ static int do_callback(const struct env_entry *e, const char *name, const char *value, enum env_op op, int flags) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD if (e->callback) return e->callback(name, value, op, flags); #endif @@ -487,7 +487,7 @@ int hdelete_r(const char *key, struct hsearch_data *htab, int flag) return 0; } -#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV)) +#if !(defined(CONFIG_XPL_BUILD) && !defined(CONFIG_SPL_SAVEENV)) /* * hexport() */ diff --git a/lib/hexdump.c b/lib/hexdump.c index 2bc508ff504..29feccd60fc 100644 --- a/lib/hexdump.c +++ b/lib/hexdump.c @@ -157,7 +157,7 @@ int print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, printf("%s%s\n", prefix_str, linebuf); break; } - if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) + if (!IS_ENABLED(CONFIG_XPL_BUILD) && ctrlc()) return -EINTR; } diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile index 1fe50ecbe52..c492377032b 100644 --- a/lib/libfdt/Makefile +++ b/lib/libfdt/Makefile @@ -16,4 +16,4 @@ obj-y += \ obj-$(CONFIG_OF_LIBFDT_OVERLAY) += fdt_overlay.o ccflags-y := -I$(srctree)/scripts/dtc/libfdt \ - -DFDT_ASSUME_MASK=$(CONFIG_$(SPL_TPL_)OF_LIBFDT_ASSUME_MASK) + -DFDT_ASSUME_MASK=$(CONFIG_$(PHASE_)OF_LIBFDT_ASSUME_MASK) diff --git a/lib/lmb.c b/lib/lmb.c index 3ed570fb29b..380d92a6718 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -749,9 +749,9 @@ int lmb_init(void) lmb_add_memory(); /* Reserve the U-Boot image region once U-Boot has relocated */ - if (spl_phase() == PHASE_SPL) + if (xpl_phase() == PHASE_SPL) lmb_reserve_common_spl(); - else if (spl_phase() == PHASE_BOARD_R) + else if (xpl_phase() == PHASE_BOARD_R) lmb_reserve_common((void *)gd->fdt_blob); return 0; diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile index c9ac72c1e26..1f9b24001bf 100644 --- a/lib/rsa/Makefile +++ b/lib/rsa/Makefile @@ -5,6 +5,6 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_$(SPL_TPL_)RSA_VERIFY) += rsa-verify.o -obj-$(CONFIG_$(SPL_TPL_)RSA_VERIFY_WITH_PKEY) += rsa-keyprop.o +obj-$(CONFIG_$(PHASE_)RSA_VERIFY) += rsa-verify.o +obj-$(CONFIG_$(PHASE_)RSA_VERIFY_WITH_PKEY) += rsa-keyprop.o obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o diff --git a/lib/time.c b/lib/time.c index 872f73d521e..d88edafb196 100644 --- a/lib/time.c +++ b/lib/time.c @@ -100,7 +100,7 @@ uint64_t notrace get_ticks(void) ret = timer_get_count(gd->timer, &count); if (ret) { - if (spl_phase() > PHASE_TPL) + if (xpl_phase() > PHASE_TPL) panic("Could not read count from timer (err %d)\n", ret); else diff --git a/lib/uuid.c b/lib/uuid.c index 11b86ffb02e..c6a27b7d044 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -477,7 +477,7 @@ void gen_rand_uuid_str(char *uuid_str, int str_format) uuid_bin_to_str(uuid_bin, uuid_str, str_format); } -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CMD_UUID) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_CMD_UUID) int do_uuid(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { char uuid[UUID_STR_LEN + 1]; diff --git a/net/Makefile b/net/Makefile index 64ab7ec740a..a7075c36a04 100644 --- a/net/Makefile +++ b/net/Makefile @@ -10,14 +10,14 @@ obj-$(CONFIG_CMD_BOOTP) += bootp.o obj-$(CONFIG_CMD_CDP) += cdp.o obj-$(CONFIG_CMD_DNS) += dns.o obj-$(CONFIG_DM_DSA) += dsa-uclass.o -obj-$(CONFIG_$(SPL_)DM_ETH) += eth-uclass.o -obj-$(CONFIG_$(SPL_TPL_)BOOTDEV_ETH) += eth_bootdev.o +obj-$(CONFIG_$(XPL_)DM_ETH) += eth-uclass.o +obj-$(CONFIG_$(PHASE_)BOOTDEV_ETH) += eth_bootdev.o obj-$(CONFIG_DM_MDIO) += mdio-uclass.o obj-$(CONFIG_DM_MDIO_MUX) += mdio-mux-uclass.o -obj-$(CONFIG_$(SPL_)DM_ETH) += eth_common.o +obj-$(CONFIG_$(XPL_)DM_ETH) += eth_common.o obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o obj-$(CONFIG_IPV6) += ndisc.o -obj-$(CONFIG_$(SPL_)DM_ETH) += net.o +obj-$(CONFIG_$(XPL_)DM_ETH) += net.o obj-$(CONFIG_IPV6) += net6.o obj-$(CONFIG_CMD_NFS) += nfs.o obj-$(CONFIG_CMD_PING) += ping.o @@ -27,8 +27,8 @@ obj-$(CONFIG_CMD_PCAP) += pcap.o obj-$(CONFIG_CMD_RARP) += rarp.o obj-$(CONFIG_CMD_SNTP) += sntp.o obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o -obj-$(CONFIG_$(SPL_TPL_)UDP_FUNCTION_FASTBOOT) += fastboot_udp.o -obj-$(CONFIG_$(SPL_TPL_)TCP_FUNCTION_FASTBOOT) += fastboot_tcp.o +obj-$(CONFIG_$(PHASE_)UDP_FUNCTION_FASTBOOT) += fastboot_udp.o +obj-$(CONFIG_$(PHASE_)TCP_FUNCTION_FASTBOOT) += fastboot_tcp.o obj-$(CONFIG_CMD_WOL) += wol.o obj-$(CONFIG_PROT_UDP) += udp.o obj-$(CONFIG_PROT_TCP) += tcp.o diff --git a/net/bootp.c b/net/bootp.c index 512ab2ed7c8..afd5b48094a 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -434,7 +434,7 @@ static u8 *add_vci(u8 *e) char *vci = NULL; char *env_vci = env_get("bootp_vci"); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING) vci = CONFIG_SPL_NET_VCI_STRING; #elif defined(CONFIG_BOOTP_VCI_STRING) vci = CONFIG_BOOTP_VCI_STRING; diff --git a/net/net.c b/net/net.c index 1e0b7c85624..64bcf69d83f 100644 --- a/net/net.c +++ b/net/net.c @@ -87,6 +87,7 @@ #include <env_internal.h> #include <errno.h> #include <image.h> +#include <led.h> #include <log.h> #include <net.h> #include <net6.h> @@ -305,7 +306,7 @@ U_BOOT_ENV_CALLBACK(dnsip, on_dnsip); */ void net_auto_load(void) { -#if defined(CONFIG_CMD_NFS) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_NFS) && !defined(CONFIG_XPL_BUILD) const char *s = env_get("autoload"); if (s != NULL && strcmp(s, "NFS") == 0) { @@ -559,7 +560,7 @@ restart: ping6_start(); break; #endif -#if defined(CONFIG_CMD_NFS) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_NFS) && !defined(CONFIG_XPL_BUILD) case NFS: nfs_start(); break; @@ -574,7 +575,7 @@ restart: cdp_start(); break; #endif -#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD) case NETCONS: nc_start(); break; @@ -664,6 +665,9 @@ restart: /* Invalidate the last protocol */ eth_set_last_protocol(BOOTP); + /* Turn off activity LED if triggered */ + led_activity_off(); + puts("\nAbort\n"); /* include a debug print as well incase the debug messages are directed to stderr */ @@ -1439,7 +1443,7 @@ void net_process_received_packet(uchar *in_packet, int len) } } -#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_XPL_BUILD) nc_input_packet((uchar *)ip + IP_UDP_HDR_SIZE, src_ip, ntohs(ip->udp_dst), diff --git a/net/tftp.c b/net/tftp.c index d6744bc24e2..704b20b4ff8 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -10,6 +10,7 @@ #include <efi_loader.h> #include <env.h> #include <image.h> +#include <led.h> #include <lmb.h> #include <log.h> #include <mapmem.h> @@ -185,6 +186,7 @@ static void new_transfer(void) #ifdef CONFIG_CMD_TFTPPUT tftp_put_final_block_sent = 0; #endif + led_activity_blink(); } #ifdef CONFIG_CMD_TFTPPUT @@ -294,6 +296,9 @@ static void tftp_complete(void) time_start * 1000, "/s"); } puts("\ndone\n"); + + led_activity_off(); + if (!tftp_put_active) efi_set_bootdev("Net", "", tftp_filename, map_sysmem(tftp_load_addr, 0), diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index 5daceb26061..edc91b24e45 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -324,18 +324,18 @@ endif # do not delete intermediate files automatically .SECONDARY: -ifdef CONFIG_SPL_BUILD -SPL_ := SPL_ +ifdef CONFIG_XPL_BUILD +XPL_ := SPL_ ifeq ($(CONFIG_VPL_BUILD),y) -SPL_TPL_ := VPL_ +PHASE_ := VPL_ else ifeq ($(CONFIG_TPL_BUILD),y) -SPL_TPL_ := TPL_ +PHASE_ := TPL_ else -SPL_TPL_ := SPL_ +PHASE_ := SPL_ endif endif else -SPL_ := -SPL_TPL_ := +XPL_ := +PHASE_ := endif diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index b42f9b525fe..c1eab2f3a1d 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -83,15 +83,15 @@ u-boot.cfg: include/config.h FORCE spl/u-boot.cfg: include/config.h FORCE $(Q)mkdir -p $(dir $@) - $(call cmd,u_boot_cfg,-DCONFIG_SPL_BUILD) + $(call cmd,u_boot_cfg,-DCONFIG_XPL_BUILD -DCONFIG_SPL_BUILD) tpl/u-boot.cfg: include/config.h FORCE $(Q)mkdir -p $(dir $@) - $(call cmd,u_boot_cfg,-DCONFIG_SPL_BUILD -DCONFIG_TPL_BUILD) + $(call cmd,u_boot_cfg,-DCONFIG_XPL_BUILD -DCONFIG_TPL_BUILD) vpl/u-boot.cfg: include/config.h FORCE $(Q)mkdir -p $(dir $@) - $(call cmd,u_boot_cfg,-DCONFIG_SPL_BUILD -DCONFIG_VPL_BUILD) + $(call cmd,u_boot_cfg,-DCONFIG_XPL_BUILD -DCONFIG_VPL_BUILD) include/autoconf.mk: u-boot.cfg $(call cmd,autoconf) diff --git a/scripts/Makefile.spl b/scripts/Makefile.xpl index 1868f1beef6..dca5f4539d0 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.xpl @@ -20,11 +20,21 @@ _dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) include $(srctree)/scripts/Kbuild.include -include include/config/auto.conf + +# This file contains 0, or 2 lines +# It is empty for U-Boot proper (where $(obj) is empty) +# For any xPL build it contains CONFIG_XPL_BUILD=y +# - for SPL builds it also contains CONFIG_SPL_BUILD=y +# - for TPL builds it also contains CONFIG_TPL_BUILD=y +# - for VPL builds it also contains CONFIG_VPL_BUILD=y -include $(obj)/include/autoconf.mk UBOOTINCLUDE := -I$(obj)/include $(UBOOTINCLUDE) +KBUILD_CPPFLAGS += -DCONFIG_XPL_BUILD +ifeq ($(CONFIG_SPL_BUILD),y) KBUILD_CPPFLAGS += -DCONFIG_SPL_BUILD +endif ifeq ($(CONFIG_TPL_BUILD),y) KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD else @@ -48,20 +58,20 @@ endif export SPL_NAME -ifdef CONFIG_SPL_BUILD -SPL_ := SPL_ +ifdef CONFIG_XPL_BUILD +XPL_ := SPL_ ifeq ($(CONFIG_VPL_BUILD),y) -SPL_TPL_ := VPL_ +PHASE_ := VPL_ else ifeq ($(CONFIG_TPL_BUILD),y) -SPL_TPL_ := TPL_ +PHASE_ := TPL_ else -SPL_TPL_ := SPL_ +PHASE_ := SPL_ endif endif else -SPL_ := -SPL_TPL_ := +XPL_ := +PHASE_ := endif ifeq ($(obj)$(CONFIG_SUPPORT_SPL),spl) @@ -83,7 +93,7 @@ include $(srctree)/scripts/Makefile.lib KBUILD_CFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections -ifeq ($(CONFIG_$(SPL_TPL_)STACKPROTECTOR),y) +ifeq ($(CONFIG_$(PHASE_)STACKPROTECTOR),y) KBUILD_CFLAGS += -fstack-protector-strong else KBUILD_CFLAGS += -fno-stack-protector @@ -107,8 +117,8 @@ endif libs-y += common/init/ # Special handling for a few options which support SPL/TPL/VPL -libs-$(CONFIG_$(SPL_TPL_)LIBCOMMON_SUPPORT) += boot/ common/ cmd/ env/ -libs-$(CONFIG_$(SPL_TPL_)LIBGENERIC_SUPPORT) += lib/ +libs-$(CONFIG_$(PHASE_)LIBCOMMON_SUPPORT) += boot/ common/ cmd/ env/ +libs-$(CONFIG_$(PHASE_)LIBGENERIC_SUPPORT) += lib/ ifdef CONFIG_SPL_FRAMEWORK libs-$(CONFIG_PARTITIONS) += disk/ endif @@ -121,7 +131,7 @@ libs-y += dts/ libs-y += fs/ libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ libs-$(CONFIG_SPL_NET) += net/ -libs-$(CONFIG_$(SPL_TPL_)UNIT_TEST) += test/ +libs-$(CONFIG_$(PHASE_)UNIT_TEST) += test/ head-y := $(addprefix $(obj)/,$(head-y)) libs-y := $(addprefix $(obj)/,$(libs-y)) @@ -137,12 +147,12 @@ endif u-boot-spl-init := $(head-y) u-boot-spl-main := $(libs-y) -ifdef CONFIG_$(SPL_TPL_)OF_PLATDATA +ifdef CONFIG_$(PHASE_)OF_PLATDATA platdata-hdr := include/generated/dt-structs-gen.h include/generated/dt-decl.h platdata-inst := $(obj)/dts/dt-uclass.o $(obj)/dts/dt-device.o platdata-noinst := $(obj)/dts/dt-plat.o -ifdef CONFIG_$(SPL_TPL_)OF_PLATDATA_INST +ifdef CONFIG_$(PHASE_)OF_PLATDATA_INST u-boot-spl-platdata := $(platdata-inst) u-boot-spl-old-platdata := $(platdata-noinst) else @@ -159,9 +169,9 @@ endif # OF_PLATDATA # Linker Script # First test whether there's a linker-script for the specific stage defined... -ifneq ($(CONFIG_$(SPL_TPL_)LDSCRIPT),) +ifneq ($(CONFIG_$(PHASE_)LDSCRIPT),) # need to strip off double quotes -LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(SPL_TPL_)LDSCRIPT:"%"=%)) +LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(PHASE_)LDSCRIPT:"%"=%)) else # ...then fall back to the generic SPL linker-script ifneq ($(CONFIG_SPL_LDSCRIPT),) @@ -195,11 +205,11 @@ LDPPFLAGS += \ # Turn various CONFIG symbols into IMAGE symbols for easy reuse of # the scripts between SPL, TPL and VPL. -ifneq ($(CONFIG_$(SPL_TPL_)MAX_SIZE),0x0) -LDPPFLAGS += -DIMAGE_MAX_SIZE=$(CONFIG_$(SPL_TPL_)MAX_SIZE) +ifneq ($(CONFIG_$(PHASE_)MAX_SIZE),0x0) +LDPPFLAGS += -DIMAGE_MAX_SIZE=$(CONFIG_$(PHASE_)MAX_SIZE) endif -ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),) -LDPPFLAGS += -DIMAGE_TEXT_BASE=$(CONFIG_$(SPL_TPL_)TEXT_BASE) +ifneq ($(CONFIG_$(PHASE_)TEXT_BASE),) +LDPPFLAGS += -DIMAGE_TEXT_BASE=$(CONFIG_$(PHASE_)TEXT_BASE) endif MKIMAGEOUTPUT ?= /dev/null @@ -313,7 +323,7 @@ endif # - OF_REAL is enabled # - we have either OF_SEPARATE or OF_HOSTFILE build_dtb := -ifneq ($(CONFIG_$(SPL_TPL_)OF_REAL),) +ifneq ($(CONFIG_$(PHASE_)OF_REAL),) ifneq ($(CONFIG_OF_SEPARATE)$(CONFIG_SANDBOX),) build_dtb := y endif @@ -321,7 +331,7 @@ endif ifneq ($(build_dtb),) $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ - $(if $(CONFIG_$(SPL_TPL_)SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ + $(if $(CONFIG_$(PHASE_)SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ $(FINAL_DTB_CONTAINER) FORCE $(call if_changed,cat) @@ -345,7 +355,7 @@ pythonpath = PYTHONPATH=scripts/dtc/pylibfdt DTOC_ARGS := $(pythonpath) $(srctree)/tools/dtoc/dtoc \ -d $(obj)/$(SPL_BIN).dtb -p $(SPL_NAME) -ifneq ($(CONFIG_$(SPL_TPL_)OF_PLATDATA_INST),) +ifneq ($(CONFIG_$(PHASE_)OF_PLATDATA_INST),) DTOC_ARGS += -i endif @@ -390,7 +400,7 @@ quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary \ - $(if $(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),-R .start16 -R .resetvec) + $(if $(CONFIG_$(PHASE_)X86_16BIT_INIT),-R .start16 -R .resetvec) $(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE $(call if_changed,objcopy) @@ -419,8 +429,8 @@ LDFLAGS_$(SPL_BIN) += $(call ld-option, --no-dynamic-linker) LDFLAGS_$(SPL_BIN) += --build-id=none # Pick the best match (e.g. SPL_TEXT_BASE for SPL, TPL_TEXT_BASE for TPL) -ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),) -LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(SPL_TPL_)TEXT_BASE) +ifneq ($(CONFIG_$(PHASE_)TEXT_BASE),) +LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(PHASE_)TEXT_BASE) endif ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 diff --git a/test/Makefile b/test/Makefile index ed312cd0a48..145c952d2c3 100644 --- a/test/Makefile +++ b/test/Makefile @@ -4,32 +4,32 @@ obj-y += test-main.o -ifneq ($(CONFIG_$(SPL_)BLOBLIST),) -obj-$(CONFIG_$(SPL_)CMDLINE) += bloblist.o -obj-$(CONFIG_$(SPL_)CMDLINE) += bootm.o +ifneq ($(CONFIG_$(XPL_)BLOBLIST),) +obj-$(CONFIG_$(XPL_)CMDLINE) += bloblist.o +obj-$(CONFIG_$(XPL_)CMDLINE) += bootm.o endif -obj-$(CONFIG_$(SPL_)CMDLINE) += cmd/ -obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_ut.o -obj-$(CONFIG_$(SPL_)CMDLINE) += command_ut.o -obj-$(CONFIG_$(SPL_)UT_COMPRESSION) += compression.o +obj-$(CONFIG_$(XPL_)CMDLINE) += cmd/ +obj-$(CONFIG_$(XPL_)CMDLINE) += cmd_ut.o +obj-$(CONFIG_$(XPL_)CMDLINE) += command_ut.o +obj-$(CONFIG_$(XPL_)UT_COMPRESSION) += compression.o obj-y += dm/ obj-$(CONFIG_FUZZ) += fuzz/ ifndef CONFIG_SANDBOX_VPL obj-$(CONFIG_UNIT_TEST) += lib/ endif ifneq ($(CONFIG_HUSH_PARSER),) -obj-$(CONFIG_$(SPL_)CMDLINE) += hush/ +obj-$(CONFIG_$(XPL_)CMDLINE) += hush/ endif -obj-$(CONFIG_$(SPL_)CMDLINE) += print_ut.o -obj-$(CONFIG_$(SPL_)CMDLINE) += str_ut.o +obj-$(CONFIG_$(XPL_)CMDLINE) += print_ut.o +obj-$(CONFIG_$(XPL_)CMDLINE) += str_ut.o obj-$(CONFIG_UT_TIME) += time_ut.o obj-y += ut.o -ifeq ($(CONFIG_SPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD),) obj-y += boot/ obj-$(CONFIG_UNIT_TEST) += common/ obj-y += log/ -obj-$(CONFIG_$(SPL_)UT_UNICODE) += unicode_ut.o +obj-$(CONFIG_$(XPL_)UT_UNICODE) += unicode_ut.o else obj-$(CONFIG_SPL_UT_LOAD) += image/ endif diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 38ba89ee33e..53fddebd49d 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -256,7 +256,7 @@ U_BOOT_LONGHELP(ut, "\ntime - very basic test of time functions" #endif #if defined(CONFIG_UT_UNICODE) && \ - !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD) + !defined(CONFIG_XPL_BUILD) && !defined(API_BUILD) "\nunicode - Unicode functions" #endif ); diff --git a/test/dm/Makefile b/test/dm/Makefile index c12589d487c..6c9ebb8d07c 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_UT_DM) += test-dm.o # Tests for particular subsystems - when enabling driver model for a new # subsystem you must add sandbox tests here. -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_SPL_OF_PLATDATA) += of_platdata.o else obj-$(CONFIG_UT_DM) += bus.o @@ -42,7 +42,7 @@ obj-$(CONFIG_CLK) += clk.o clk_ccf.o obj-$(CONFIG_CPU) += cpu.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o -obj-$(CONFIG_$(SPL_TPL_)DEVRES) += devres.o +obj-$(CONFIG_$(PHASE_)DEVRES) += devres.o obj-$(CONFIG_DMA) += dma.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o obj-$(CONFIG_DM_DSA) += dsa.o @@ -102,7 +102,7 @@ obj-$(CONFIG_DM_RESET) += reset.o obj-$(CONFIG_SYSRESET) += sysreset.o obj-$(CONFIG_DM_REGULATOR) += regulator.o obj-$(CONFIG_CMD_RKMTD) += rkmtd.o -obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng.o +obj-$(CONFIG_$(PHASE_)DM_RNG) += rng.o obj-$(CONFIG_DM_RTC) += rtc.o obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o obj-$(CONFIG_SCSI) += scsi.o diff --git a/test/dm/led.c b/test/dm/led.c index e1509c397d8..884f6410b70 100644 --- a/test/dm/led.c +++ b/test/dm/led.c @@ -137,3 +137,75 @@ static int dm_test_led_blink(struct unit_test_state *uts) } DM_TEST(dm_test_led_blink, UTF_SCAN_PDATA | UTF_SCAN_FDT); #endif + +/* Test LED boot */ +#ifdef CONFIG_LED_BOOT +static int dm_test_led_boot(struct unit_test_state *uts) +{ + struct udevice *dev + + /* options/u-boot/boot-led is set to "sandbox:green" */ + ut_assertok(led_get_by_label("sandbox:green", &dev)); + ut_asserteq(LEDST_OFF, led_get_state(dev)); + ut_assertok(led_boot_on()); + ut_asserteq(LEDST_ON, led_get_state(dev)); + ut_assertok(led_boot_off()); + ut_asserteq(LEDST_OFF, led_get_state(dev)); + + return 0; +} + +/* Test LED boot blink fallback */ +#ifndef CONFIG_LED_BLINK +static int dm_test_led_boot(struct unit_test_state *uts) +{ + struct udevice *dev + + /* options/u-boot/boot-led is set to "sandbox:green" */ + ut_assertok(led_get_by_label("sandbox:green", &dev)); + ut_asserteq(LEDST_OFF, led_get_state(dev)); + ut_assertok(led_boot_blink()); + ut_asserteq(LEDST_ON, led_get_state(dev)); + ut_assertok(led_boot_off()); + ut_asserteq(LEDST_OFF, led_get_state(dev)); + + return 0; +} +#endif +#endif + +/* Test LED activity */ +#ifdef CONFIG_LED_ACTIVITY +static int dm_test_led_boot(struct unit_test_state *uts) +{ + struct udevice *dev + + /* options/u-boot/activity-led is set to "sandbox:red" */ + ut_assertok(led_get_by_label("sandbox:red", &dev)); + ut_asserteq(LEDST_OFF, led_get_state(dev)); + ut_assertok(led_activity_on()); + ut_asserteq(LEDST_ON, led_get_state(dev)); + ut_assertok(led_activity_off()); + ut_asserteq(LEDST_OFF, led_get_state(dev)); + + return 0; +} + +/* Test LED activity blink fallback */ +#ifndef CONFIG_LED_BLINK +static int dm_test_led_boot(struct unit_test_state *uts) +{ + struct udevice *dev + + /* options/u-boot/activity-led is set to "sandbox:red" */ + ut_assertok(led_get_by_label("sandbox:red", &dev)); + ut_asserteq(LEDST_OFF, led_get_state(dev)); + ut_assertok(led_activity_blink()); + ut_asserteq(LEDST_ON, led_get_state(dev)); + ut_assertok(led_activity_off()); + ut_asserteq(LEDST_OFF, led_get_state(dev)); + + return 0; +} +#endif +#endif diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 859fc3ae0d0..ce996567c3c 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -614,6 +614,15 @@ static int dm_test_ofnode_options(struct unit_test_state *uts) u64 bootscr_address, bootscr_offset; u64 bootscr_flash_offset, bootscr_flash_size; + ut_assert(!ofnode_options_read_bool("missing")); + ut_assert(ofnode_options_read_bool("testing-bool")); + + ut_asserteq(123, ofnode_options_read_int("testing-int", 0)); + ut_asserteq(6, ofnode_options_read_int("missing", 6)); + + ut_assertnull(ofnode_options_read_str("missing")); + ut_asserteq_str("testing", ofnode_options_read_str("testing-str")); + ut_assertok(ofnode_read_bootscript_address(&bootscr_address, &bootscr_offset)); ut_asserteq_64(0, bootscr_address); diff --git a/test/fuzz/Makefile b/test/fuzz/Makefile index 663b79ce80b..8a135b65e4b 100644 --- a/test/fuzz/Makefile +++ b/test/fuzz/Makefile @@ -4,5 +4,5 @@ # Written by Andrew Scull <ascull@google.com> # -obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_fuzz.o +obj-$(CONFIG_$(XPL_)CMDLINE) += cmd_fuzz.o obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o diff --git a/test/lib/Makefile b/test/lib/Makefile index 70f14c46b1e..a54387a058e 100644 --- a/test/lib/Makefile +++ b/test/lib/Makefile @@ -2,7 +2,7 @@ # # (C) Copyright 2018 # Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc -ifeq ($(CONFIG_SPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD),) obj-y += cmd_ut_lib.o obj-y += abuf.o obj-y += alist.o diff --git a/test/py/tests/test_efi_fit.py b/test/py/tests/test_efi_fit.py index 0ad483500f8..550058a30fd 100644 --- a/test/py/tests/test_efi_fit.py +++ b/test/py/tests/test_efi_fit.py @@ -119,7 +119,7 @@ FDT_DATA = ''' ''' @pytest.mark.buildconfigspec('bootm_efi') -@pytest.mark.buildconfigspec('cmd_bootefi_hello_compile') +@pytest.mark.buildconfigspec('BOOTEFI_HELLO_COMPILE') @pytest.mark.buildconfigspec('fit') @pytest.mark.notbuildconfigspec('generate_acpi_table') @pytest.mark.requiredtool('dtc') diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py index 5f3b448a066..707b2c9e795 100644 --- a/test/py/tests/test_efi_loader.py +++ b/test/py/tests/test_efi_loader.py @@ -170,7 +170,7 @@ def do_test_efi_helloworld_net(u_boot_console, proto): assert expected_text not in output @pytest.mark.buildconfigspec('of_control') -@pytest.mark.buildconfigspec('cmd_bootefi_hello_compile') +@pytest.mark.buildconfigspec('bootefi_hello_compile') @pytest.mark.buildconfigspec('cmd_tftpboot') def test_efi_helloworld_net_tftp(u_boot_console): """Run the helloworld.efi binary via TFTP. diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py index 43f24245582..310d8ed294a 100644 --- a/test/py/tests/test_efi_selftest.py +++ b/test/py/tests/test_efi_selftest.py @@ -58,7 +58,7 @@ def test_efi_selftest_watchdog_reboot(u_boot_console): u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False) if u_boot_console.p.expect(['resetting', 'U-Boot']): raise Exception('Reset failed in \'watchdog reboot\' test') - u_boot_console.restart_uboot() + u_boot_console.run_command(cmd='', send_nl=False, wait_for_reboot=True) @pytest.mark.buildconfigspec('cmd_bootefi_selftest') def test_efi_selftest_text_input(u_boot_console): diff --git a/test/test-main.c b/test/test-main.c index b3d3e24cdce..479dbb33b72 100644 --- a/test/test-main.c +++ b/test/test-main.c @@ -47,7 +47,7 @@ enum fdtchk_t { static enum fdtchk_t fdt_action(void) { /* For sandbox SPL builds, do nothing */ - if (IS_ENABLED(CONFIG_SANDBOX) && IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_SANDBOX) && IS_ENABLED(CONFIG_XPL_BUILD)) return FDTCHK_NONE; /* Do a copy for sandbox (but only the U-Boot build, not SPL) */ diff --git a/tools/binman/etype/nxp_imx8mcst.py b/tools/binman/etype/nxp_imx8mcst.py index 8221517b0c4..a7d8db4eec4 100644 --- a/tools/binman/etype/nxp_imx8mcst.py +++ b/tools/binman/etype/nxp_imx8mcst.py @@ -23,7 +23,9 @@ from u_boot_pylib import tools MAGIC_NXP_IMX_IVT = 0x412000d1 MAGIC_FITIMAGE = 0xedfe0dd0 -csf_config_template = """ +KEY_NAME = 'sha256_4096_65537_v3_usr_crt' + +CSF_CONFIG_TEMPLATE = f''' [Header] Version = 4.3 Hash Algorithm = sha256 @@ -36,8 +38,11 @@ csf_config_template = """ File = "SRK_1_2_3_4_table.bin" Source index = 0 +[Install NOCAK] + File = "SRK1_{KEY_NAME}.pem" + [Install CSFK] - File = "CSF1_1_sha256_4096_65537_v3_usr_crt.pem" + File = "CSF1_1_{KEY_NAME}.pem" [Authenticate CSF] @@ -48,12 +53,12 @@ csf_config_template = """ [Install Key] Verification index = 0 Target Index = 2 - File = "IMG1_1_sha256_4096_65537_v3_usr_crt.pem" + File = "IMG1_1_{KEY_NAME}.pem" [Authenticate Data] Verification index = 2 Blocks = 0x1234 0x78 0xabcd "data.bin" -""" +''' class Entry_nxp_imx8mcst(Entry_mkimage): """NXP i.MX8M CST .cfg file generator and cst invoker @@ -69,9 +74,22 @@ class Entry_nxp_imx8mcst(Entry_mkimage): def ReadNode(self): super().ReadNode() self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address') - self.srk_table = os.getenv('SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table', 'SRK_1_2_3_4_table.bin')) - self.csf_crt = os.getenv('CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt', 'CSF1_1_sha256_4096_65537_v3_usr_crt.pem')) - self.img_crt = os.getenv('IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt', 'IMG1_1_sha256_4096_65537_v3_usr_crt.pem')) + self.srk_table = os.getenv( + 'SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table', + 'SRK_1_2_3_4_table.bin')) + self.fast_auth = fdt_util.GetBool(self._node, 'nxp,fast-auth') + if not self.fast_auth: + self.csf_crt = os.getenv( + 'CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt', + f'CSF1_1_{KEY_NAME}.pem')) + self.img_crt = os.getenv( + 'IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt', + f'IMG1_1_{KEY_NAME}.pem')) + else: + self.srk_crt = os.getenv( + 'SRK_KEY', fdt_util.GetString(self._node, 'nxp,srk-crt', + f'SRK1_{KEY_NAME}.pem')) + self.unlock = fdt_util.GetBool(self._node, 'nxp,unlock') self.ReadEntries() @@ -118,16 +136,26 @@ class Entry_nxp_imx8mcst(Entry_mkimage): tools.write_file(output_dname, data) # Generate CST configuration file used to sign payload - cfg_fname = tools.get_output_filename('nxp.csf-config-txt.%s' % uniq) + cfg_fname = tools.get_output_filename(f'nxp.csf-config-txt.{uniq}') config = configparser.ConfigParser() # Do not make key names lowercase config.optionxform = str # Load configuration template and modify keys of interest - config.read_string(csf_config_template) - config['Install SRK']['File'] = '"' + self.srk_table + '"' - config['Install CSFK']['File'] = '"' + self.csf_crt + '"' - config['Install Key']['File'] = '"' + self.img_crt + '"' - config['Authenticate Data']['Blocks'] = hex(signbase) + ' 0 ' + hex(len(data)) + ' "' + str(output_dname) + '"' + config.read_string(CSF_CONFIG_TEMPLATE) + config['Install SRK']['File'] = f'"{self.srk_table}"' + if not self.fast_auth: + config.remove_section('Install NOCAK') + config['Install CSFK']['File'] = f'"{self.csf_crt}"' + config['Install Key']['File'] = f'"{self.img_crt}"' + else: + config.remove_section('Install CSFK') + config.remove_section('Install Key') + config['Install NOCAK']['File'] = f'"{self.srk_crt}"' + config['Authenticate Data']['Verification index'] = '0' + + config['Authenticate Data']['Blocks'] = \ + f'{signbase:#x} 0 {len(data):#x} "{output_dname}"' + if not self.unlock: config.remove_section('Unlock') with open(cfg_fname, 'w') as cfgf: diff --git a/tools/qconfig.py b/tools/qconfig.py index 8c2fc9efc5f..058d72cf4bc 100755 --- a/tools/qconfig.py +++ b/tools/qconfig.py @@ -77,7 +77,7 @@ IGNORE_SYMS = ['DEBUG_SECTION_MISMATCH', 'FTRACE_MCOUNT_RECORD', 'GCOV_KERNEL', 'IS_ENABLED_', 'IS_ENABLED_1', 'IS_ENABLED_2', 'IS_ENABLED_3', 'SPL_', 'TPL_', 'SPL_FOO', 'TPL_FOO', 'TOOLS_FOO', 'ACME', 'SPL_ACME', 'TPL_ACME', 'TRACE_BRANCH_PROFILING', - 'VAL', '_UNDEFINED', 'SPL_BUILD', ] + 'VAL', '_UNDEFINED', 'SPL_BUILD', 'XPL_BUILD', ] SPL_PREFIXES = ['SPL_', 'TPL_', 'VPL_', 'TOOLS_'] @@ -1175,7 +1175,7 @@ def prefix_config(cfg): return oper + cfg -RE_MK_CONFIGS = re.compile(r'CONFIG_(\$\(SPL_(?:TPL_)?\))?([A-Za-z0-9_]*)') +RE_MK_CONFIGS = re.compile(r'CONFIG_(\$\(XPL_\)|\$\(PHASE_\))?([A-Za-z0-9_]*)') RE_IFDEF = re.compile(r'(ifdef|ifndef)') RE_C_CONFIGS = re.compile(r'CONFIG_([A-Za-z0-9_]*)') RE_CONFIG_IS = re.compile(r'CONFIG_IS_ENABLED\(([A-Za-z0-9_]*)\)') @@ -1186,7 +1186,7 @@ class ConfigUse: """Set up a new ConfigUse Args: - cfg (str): CONFIG option, without any CONFIG_ or SPL_ prefix + cfg (str): CONFIG option, without any CONFIG_ or xPL_ prefix is_spl (bool): True if this option relates to SPL fname (str): Makefile filename where the CONFIG option was found rest (str): Line of the Makefile @@ -1220,10 +1220,10 @@ def scan_makefiles(fnames): >>> RE_MK_CONFIGS.search('CONFIG_FRED').groups() (None, 'FRED') - >>> RE_MK_CONFIGS.search('CONFIG_$(SPL_)MARY').groups() - ('$(SPL_)', 'MARY') - >>> RE_MK_CONFIGS.search('CONFIG_$(SPL_TPL_)MARY').groups() - ('$(SPL_TPL_)', 'MARY') + >>> RE_MK_CONFIGS.search('CONFIG_$(XPL_)MARY').groups() + ('$(XPL_)', 'MARY') + >>> RE_MK_CONFIGS.search('CONFIG_$(PHASE_)MARY').groups() + ('$(PHASE_)', 'MARY') """ all_uses = collections.defaultdict(list) fname_uses = {} @@ -1319,10 +1319,10 @@ def do_scan_source(path, do_update): key (ConfigUse): object value (list of str): matching lines spl_mode (int): If MODE_SPL, look at source code which implies - an SPL_ option, but for which there is none; + an xPL_ option, but for which there is none; for MOD_PROPER, look at source code which implies a Proper - option (i.e. use of CONFIG_IS_ENABLED() or $(SPL_) or - $(SPL_TPL_) but for which there none; + option (i.e. use of CONFIG_IS_ENABLED() or $(XPL_) or + $(PHASE_) but for which there none; if MODE_NORMAL, ignore SPL Returns: @@ -1341,7 +1341,7 @@ def do_scan_source(path, do_update): if spl_mode == MODE_SPL: check = use.is_spl - # If it is an SPL symbol, try prepending all SPL_ prefixes to + # If it is an SPL symbol, try prepending all xPL_ prefixes to # find at least one SPL symbol if use.is_spl: for prefix in SPL_PREFIXES: @@ -1354,7 +1354,7 @@ def do_scan_source(path, do_update): continue elif spl_mode == MODE_PROPER: # Try to find the Proper version of this symbol, i.e. without - # the SPL_ prefix + # the xPL_ prefix proper_name = is_not_proper(name) if proper_name: name = proper_name @@ -1450,7 +1450,7 @@ def do_scan_source(path, do_update): show_uses(not_found) spl_not_found |= {is_not_proper(key) or key for key in not_found.keys()} - print('\nCONFIG options used as Proper in Makefiles but without a non-SPL_ variant:') + print('\nCONFIG options used as Proper in Makefiles but without a non-xPL_ variant:') not_found = check_not_found(all_uses, MODE_PROPER) show_uses(not_found) proper_not_found |= {not_found.keys()} @@ -1468,16 +1468,16 @@ def do_scan_source(path, do_update): show_uses(not_found) spl_not_found |= {is_not_proper(key) or key for key in not_found.keys()} - print('\nCONFIG options used as Proper in source but without a non-SPL_ variant:') + print('\nCONFIG options used as Proper in source but without a non-xPL_ variant:') not_found = check_not_found(all_uses, MODE_PROPER) show_uses(not_found) proper_not_found |= {not_found.keys()} - print('\nCONFIG options used as SPL but without an SPL_ variant:') + print('\nCONFIG options used as SPL but without an xPL_ variant:') for item in sorted(spl_not_found): print(f' {item}') - print('\nCONFIG options used as Proper but without a non-SPL_ variant:') + print('\nCONFIG options used as Proper but without a non-xPL_ variant:') for item in sorted(proper_not_found): print(f' {item}') |