diff options
165 files changed, 12979 insertions, 2867 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fba7dfed26b..6e9c5f07999 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -396,25 +396,43 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-a2197-revA.dtb \ zynqmp-dlc21-revA.dtb \ zynqmp-e-a2197-00-revA.dtb \ + zynqmp-e-a2197-00-revB.dtb \ zynqmp-g-a2197-00-revA.dtb \ zynqmp-m-a2197-01-revA.dtb \ zynqmp-m-a2197-02-revA.dtb \ zynqmp-m-a2197-03-revA.dtb \ zynqmp-p-a2197-00-revA.dtb \ + zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo \ + zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo \ + zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo \ + zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo \ + zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-mini-qspi.dtb \ + zynqmp-sc-revB.dtb \ + zynqmp-sc-revC.dtb \ + zynqmp-sc-vek280-revA.dtbo \ + zynqmp-sc-vek280-revB.dtbo \ + zynqmp-sc-vhk158-revA.dtbo \ + zynqmp-sc-vpk120-revB.dtbo \ + zynqmp-sc-vpk180-revA.dtbo \ + zynqmp-sc-vpk180-revB.dtbo \ + zynqmp-sc-vn-p-b2197-00-revA.dtbo \ zynqmp-sm-k24-revA.dtb \ zynqmp-smk-k24-revA.dtb \ zynqmp-sm-k26-revA.dtb \ zynqmp-smk-k26-revA.dtb \ + zynqmp-sck-kd-g-revA.dtbo \ zynqmp-sck-kr-g-revA.dtbo \ zynqmp-sck-kr-g-revB.dtbo \ zynqmp-sck-kv-g-revA.dtbo \ zynqmp-sck-kv-g-revB.dtbo \ zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \ + zynqmp-vpk120-revA.dtb \ + zynqmp-vp-x-a2785-00-revA.dtb \ zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ @@ -430,6 +448,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu1285-revA.dtb \ zynqmp-zcu208-revA.dtb \ zynqmp-zcu216-revA.dtb \ + zynqmp-zcu670-revA.dtb \ + zynqmp-zcu670-revB.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts index 96a6403efaf..4c1bd69e755 100644 --- a/arch/arm/dts/avnet-ultra96-rev1.dts +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -2,7 +2,7 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts index 6c47396ce75..0228b4b30e5 100644 --- a/arch/arm/dts/bitmain-antminer-s9.dts +++ b/arch/arm/dts/bitmain-antminer-s9.dts @@ -52,6 +52,9 @@ &nfc0 { status = "okay"; + nand@0 { + reg = <0>; + }; }; &smcc { diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index 79faa1b5737..4f34347586e 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -1,69 +1,36 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-j721s2-binman.dtsi" -/ { - chosen { - stdout-path = "serial2:115200n8"; - tick-timer = &timer1; - }; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart8; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &mcu_i2c1; - i2c3 = &main_i2c0; - ethernet0 = &cpsw_port1; - mmc1 = &main_sdhci1; - }; -}; - &wkup_i2c0 { - bootph-pre-ram; + bootph-all; }; &cbass_main { - bootph-pre-ram; + bootph-all; }; &main_navss { - bootph-pre-ram; + bootph-all; }; &cbass_mcu_wakeup { - bootph-pre-ram; - - timer1: timer@40400000 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x40400000 0x0 0x80>; - ti,timer-alwon; - clock-frequency = <250000000>; - bootph-pre-ram; - }; + bootph-all; chipid@43000014 { - bootph-pre-ram; + bootph-all; }; }; &mcu_navss { - bootph-pre-ram; + bootph-all; }; &mcu_ringacc { - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - bootph-pre-ram; + bootph-all; }; &mcu_udmap { @@ -75,78 +42,94 @@ <0x0 0x28400000 0x0 0x2000>; reg-names = "gcfg", "rchan", "rchanrt", "tchan", "tchanrt", "rflow"; - bootph-pre-ram; + bootph-all; }; &secure_proxy_main { - bootph-pre-ram; + bootph-all; }; &sms { - bootph-pre-ram; + bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - bootph-pre-ram; + bootph-all; }; }; &main_pmx0 { - bootph-pre-ram; + bootph-all; }; &main_uart8_pins_default { - bootph-pre-ram; + bootph-all; }; &main_mmc1_pins_default { - bootph-pre-ram; + bootph-all; +}; + +&main_usbss0_pins_default { + bootph-all; }; &wkup_pmx0 { - bootph-pre-ram; + bootph-all; +}; + +&wkup_pmx1 { + bootph-all; +}; + +&wkup_pmx2 { + bootph-all; +}; + +&wkup_pmx3 { + bootph-all; }; &k3_pds { - bootph-pre-ram; + bootph-all; }; &k3_clks { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &main_uart8 { - bootph-pre-ram; + bootph-all; }; &mcu_uart0 { - bootph-pre-ram; + bootph-all; }; &wkup_uart0 { - bootph-pre-ram; + bootph-all; }; -&mcu_cpsw { - reg = <0x0 0x46000000 0x0 0x200000>, - <0x0 0x40f00200 0x0 0x8>; - reg-names = "cpsw_nuss", "mac_efuse"; - /delete-property/ ranges; +&main_sdhci1 { + bootph-all; +}; - cpsw-phy-sel@40f04040 { - compatible = "ti,am654-cpsw-phy-sel"; - reg= <0x0 0x40f04040 0x0 0x4>; - reg-names = "gmii-sel"; - }; +&ospi0 { + status = "disabled"; }; -&main_sdhci0 { +&ospi1 { status = "disabled"; }; -&main_sdhci1 { - bootph-pre-ram; +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; }; diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts index 8fc03324ab8..5df5946687b 100644 --- a/arch/arm/dts/k3-am68-sk-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-base-board.dts @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ * - * Base Board: **Yet to Add** + * Base Board: https://www.ti.com/lit/zip/SPRR463 */ /dts-v1/; @@ -12,21 +12,28 @@ #include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy.h> +#include "k3-serdes.h" + / { compatible = "ti,am68-sk", "ti,j721s2"; model = "Texas Instruments AM68 SK"; chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000"; }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc1 = &main_sdhci1; + can0 = &mcu_mcan0; + can1 = &mcu_mcan1; + can2 = &main_mcan6; + can3 = &main_mcan7; }; - vusb_main: fixedregulator-vusb-main5v0 { + vusb_main: regulator-vusb-main5v0 { /* USB MAIN INPUT 5V DC */ compatible = "regulator-fixed"; regulator-name = "vusb-main5v0"; @@ -36,7 +43,7 @@ regulator-boot-on; }; - vsys_3v3: fixedregulator-vsys3v3 { + vsys_3v3: regulator-vsys3v3 { /* Output of LM5141 */ compatible = "regulator-fixed"; regulator-name = "vsys_3v3"; @@ -47,7 +54,7 @@ regulator-boot-on; }; - vdd_mmc1: fixedregulator-sd { + vdd_mmc1: regulator-sd { /* Output of TPS22918 */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; @@ -56,10 +63,10 @@ regulator-boot-on; enable-active-high; vin-supply = <&vsys_3v3>; - gpio = <&exp1 10 GPIO_ACTIVE_HIGH>; + gpio = <&exp1 8 GPIO_ACTIVE_HIGH>; }; - vdd_sd_dv: gpio-regulator-TLV71033 { + vdd_sd_dv: regulator-tlv71033 { /* Output of TLV71033 */ compatible = "regulator-gpio"; regulator-name = "tlv71033"; @@ -73,30 +80,115 @@ states = <1800000 0x0>, <3300000 0x1>; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins_default>; + ddc-i2c-bus = <&mcu_i2c1>; + /* HDMI_HPD */ + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + bridge-dvi { + compatible = "ti,tfp410"; + /* HDMI_PDn */ + powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; + ti,deskew = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out0>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < - J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ - J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; }; - main_i2c0_pins_default: i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < - J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ - J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ + J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ @@ -105,102 +197,222 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; -}; -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + main_mcan6_pins_default: main-mcan6-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ + J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ >; }; -}; -&main_gpio2 { - status = "disabled"; -}; + main_mcan7_pins_default: main-mcan7-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ + J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ + >; + }; -&main_gpio4 { - status = "disabled"; -}; + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ + >; + }; -&main_gpio6 { - status = "disabled"; -}; + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ + J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ + J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ + J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ + J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ + J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ + J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ + J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ + J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ + J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ + J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ + J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ + >; + }; -&wkup_gpio1 { - status = "disabled"; -}; + dss_vout0_pins_default: dss-vout0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ + J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ + J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ + J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ + J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ + J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ + J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ + J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ + J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ + J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ + J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ + J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ + J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ + J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ + J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ + J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ + J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ + J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ + J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ + J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ + J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ + J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ + J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ + J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ + J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ + >; + }; -&wkup_uart0 { - status = "reserved"; + hdmi_hpd_pins_default: hdmi-hpd-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ + >; + }; }; -&main_uart0 { - status = "disabled"; -}; +&wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ + >; + }; -&main_uart1 { - status = "disabled"; -}; + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ + >; + }; + + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ + >; + }; -&main_uart2 { - status = "disabled"; + mcu_i2c1_pins_default: mcu-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ + J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ + J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ + J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ + J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ + J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ + >; + }; }; -&main_uart3 { - status = "disabled"; +&wkup_pmx3 { + mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ + >; + }; }; -&main_uart4 { - status = "disabled"; +&main_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; -&main_uart5 { - status = "disabled"; +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; }; -&main_uart6 { - status = "disabled"; +&wkup_uart0 { + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; -&main_uart7 { - status = "disabled"; +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; }; -&main_uart9 { - status = "disabled"; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -211,45 +423,47 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; - gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPN", "HDMI_PDN", - "HDMI_LS_OE", "DP0_3V3_EN", "BOARDID_EEPROM_WP", - "CAN_STB", "","GPIO_uSD_PWR_EN", "EDP_ENABLE", - "IO_EXP_PCIE1_M2_RSTZ", "IO_EXP_MCU_RGMII_RSTZ", - "IO_EXP_CSI1_EXP_RSTZ", "","CSI0_B_GPIO1", - "CSI1_B_GPIO1"; + gpio-line-names = " ", " ", " ", " ", " ", + "BOARDID_EEPROM_WP", "CAN_STB", " ", + "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz", + "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " "; }; }; -&main_i2c1 { - status = "disabled"; -}; - -&main_i2c2 { - status = "disabled"; -}; - -&main_i2c3 { - status = "disabled"; -}; - &main_i2c4 { - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; }; -&main_i2c5 { - status = "disabled"; +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; }; -&main_i2c6 { - status = "disabled"; -}; +&mcu_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c1_pins_default>; + /* i2c1 is used for DVI DDC, so we need to use 100kHz */ + clock-frequency = <100000>; -&main_sdhci0 { - status = "disabled"; + exp2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HDMI_PDn","HDMI_LS_OE", + "DP0_3V3_EN","eDP_ENABLE"; + }; }; &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; disable-wp; @@ -259,7 +473,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { @@ -277,77 +491,65 @@ }; &mcu_mcan0 { - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; }; &mcu_mcan1 { - status = "disabled"; -}; - -&main_mcan0 { - status = "disabled"; -}; - -&main_mcan1 { - status = "disabled"; -}; - -&main_mcan2 { - status = "disabled"; -}; - -&main_mcan3 { - status = "disabled"; -}; - -&main_mcan4 { - status = "disabled"; -}; - -&main_mcan5 { - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; }; &main_mcan6 { - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan6_pins_default>; + phys = <&transceiver3>; }; &main_mcan7 { - status = "disabled"; -}; - -&main_mcan8 { - status = "disabled"; -}; - -&main_mcan9 { - status = "disabled"; -}; - -&main_mcan10 { - status = "disabled"; -}; - -&main_mcan11 { - status = "disabled"; -}; - -&main_mcan12 { - status = "disabled"; -}; - -&main_mcan13 { - status = "disabled"; -}; - -&main_mcan14 { - status = "disabled"; -}; - -&main_mcan15 { - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan7_pins_default>; + phys = <&transceiver4>; }; -&main_mcan17 { - status = "disabled"; +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout0_pins_default>; + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP0 - DisplayPort SST + * VP1 - DPI0 + * VP2 - DSI + * VP3 - DPI1 + */ + assigned-clocks = <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + assigned-clock-parents = <&k3_clks 158 3>, + <&k3_clks 158 7>, + <&k3_clks 158 16>, + <&k3_clks 158 22>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* HDMI */ + port@1 { + reg = <1>; + + dpi_out0: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; }; diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index a64baba1498..695aadc287b 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -1,19 +1,18 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; -#include "k3-am68-sk-som.dtsi" +#include "k3-am68-sk-base-board.dts" #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" +#include "k3-am68-sk-base-board-u-boot.dtsi" / { chosen { - firmware-loader = &fs_loader0; - stdout-path = &main_uart8; - tick-timer = &timer1; + tick-timer = &mcu_timer0; }; aliases { @@ -21,11 +20,6 @@ remoteproc1 = &a72_0; }; - fs_loader0: fs_loader@0 { - compatible = "u-boot,fs-loader"; - bootph-all; - }; - a72_0: a72@0 { compatible = "ti,am654-rproc"; reg = <0x0 0x00a90000 0x0 0x10>; @@ -42,145 +36,44 @@ bootph-pre-ram; }; - clk_200mhz: dummy_clock_200mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - bootph-pre-ram; - }; - - clk_19_2mhz: dummy_clock_19_2mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - bootph-pre-ram; - }; -}; - -&cbass_mcu_wakeup { - sa3_secproxy: secproxy@44880000 { - bootph-pre-ram; - compatible = "ti,am654-secure-proxy"; - reg = <0x0 0x44880000 0x0 0x20000>, - <0x0 0x44860000 0x0 0x20000>, - <0x0 0x43600000 0x0 0x10000>; - reg-names = "rt", "scfg", "target_data"; - #mbox-cells = <1>; - }; - - mcu_secproxy: secproxy@2a380000 { - compatible = "ti,am654-secure-proxy"; - reg = <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>, - <0x0 0x2a480000 0x0 0x80000>; - reg-names = "rt", "scfg", "target_data"; - #mbox-cells = <1>; - bootph-pre-ram; - }; - - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; - dm_tifs: dm-tifs { compatible = "ti,j721e-dm-sci"; ti,host-id = <3>; ti,secure-host; mbox-names = "rx", "tx"; - mboxes= <&mcu_secproxy 21>, - <&mcu_secproxy 23>; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; bootph-pre-ram; }; }; -&main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { - pinctrl-single,pins = < - J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ - J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ - >; - }; - - main_mmc1_pins_default: main-mmc1-pins-default { - pinctrl-single,pins = < - J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ - J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ - J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ - J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ - J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ - J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ - >; - }; +&mcu_timer0 { + clock-frequency = <250000000>; + bootph-pre-ram; +}; - main_usbss0_pins_default: main-usbss0-pins-default { - pinctrl-single,pins = < - J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ - >; - }; +&secure_proxy_mcu { + bootph-pre-ram; }; -&wkup_pmx0 { - mcu_uart0_pins_default: mcu-uart0-pins-default { - bootph-pre-ram; - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /*(C24) WKUP_GPIO0_13.MCU_UART0_RXD*/ - J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /*(C25) WKUP_GPIO0_12.MCU_UART0_TXD*/ - >; - }; +&secure_proxy_sa3 { + bootph-pre-ram; +}; - wkup_uart0_pins_default: wkup-uart0-pins-default { +&cbass_mcu_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; + mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /*(E25) WKUP_GPIO0_6.WKUP_UART0_CTSn*/ - J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /*(F28) WKUP_GPIO0_7.WKUP_UART0_RTSn*/ - J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ - >; }; - }; &sms { - mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx", "notify"; ti,host-id = <4>; ti,secure-host; - bootph-pre-ram; -}; - -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; -}; - -&main_sdhci0 { - status = "disabled"; -}; - -&main_sdhci1 { - /delete-property/ power-domains; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - clock-names = "clk_xin"; - clocks = <&clk_200mhz>; - ti,driver-strength-ohm = <50>; }; &mcu_ringacc { @@ -190,5 +83,3 @@ &mcu_udmap { ti,sci = <&dm_tifs>; }; - -#include "k3-am68-sk-base-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi index cb1c58fcd15..6c9139f7320 100644 --- a/arch/arm/dts/k3-am68-sk-som.dtsi +++ b/arch/arm/dts/k3-am68-sk-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -16,7 +16,6 @@ <0x08 0x80000000 0x03 0x80000000>; }; - /* Reserving memory regions still pending */ reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -24,104 +23,29 @@ secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; no-map; }; }; }; -&mailbox0_cluster0 { - status = "disabled"; -}; - -&mailbox0_cluster1 { - status = "disabled"; -}; - -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - -&mailbox1_cluster0 { - status = "disabled"; -}; - -&mailbox1_cluster1 { - status = "disabled"; -}; - -&mailbox1_cluster2 { - status = "disabled"; -}; - -&mailbox1_cluster3 { - status = "disabled"; -}; - -&mailbox1_cluster4 { - status = "disabled"; -}; - -&mailbox1_cluster5 { - status = "disabled"; -}; - -&mailbox1_cluster6 { - status = "disabled"; -}; - -&mailbox1_cluster7 { - status = "disabled"; -}; - -&mailbox1_cluster8 { - status = "disabled"; +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; }; -&mailbox1_cluster9 { - status = "disabled"; -}; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; -&mailbox1_cluster10 { - status = "disabled"; -}; - -&mailbox1_cluster11 { - status = "disabled"; + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index f25c7136c98..60ca6d21abb 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -1,200 +1,210 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-j7200-binman.dtsi" / { chosen { - stdout-path = "serial2:115200n8"; - tick-timer = &timer1; - }; - - aliases { - ethernet0 = &cpsw_port1; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &mcu_i2c1; - i2c3 = &main_i2c0; + tick-timer = &mcu_timer0; }; }; &cbass_main { - bootph-pre-ram; + bootph-all; }; &main_navss { - bootph-pre-ram; + bootph-all; +}; + +&main_esm { + bootph-all; }; &cbass_mcu_wakeup { - bootph-pre-ram; - - timer1: timer@40400000 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x40400000 0x0 0x80>; - ti,timer-alwon; - clock-frequency = <250000000>; - bootph-pre-ram; - }; + bootph-all; chipid@43000014 { - bootph-pre-ram; + bootph-all; }; +}; - mcu_navss: bus@28380000 { - bootph-pre-ram; - #address-cells = <2>; - #size-cells = <2>; - - ringacc@2b800000 { - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - bootph-pre-ram; - }; - - dma-controller@285c0000 { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; - bootph-pre-ram; - }; - }; +&mcu_navss { + bootph-all; +}; + +&mcu_ringacc { + bootph-all; +}; + +&mcu_udmap { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; + bootph-all; }; &secure_proxy_main { - bootph-pre-ram; + bootph-all; }; &dmsc { - bootph-pre-ram; + bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - bootph-pre-ram; + bootph-all; }; }; &k3_pds { - bootph-pre-ram; + bootph-all; }; &k3_clks { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &wkup_pmx0 { - bootph-pre-ram; + bootph-all; +}; + +&wkup_pmx2 { + bootph-all; }; &main_pmx0 { - bootph-pre-ram; + bootph-all; }; &main_uart0 { - bootph-pre-ram; + bootph-all; +}; + +&main_uart2 { + bootph-all; }; &mcu_uart0 { - bootph-pre-ram; + bootph-all; }; &main_sdhci0 { - bootph-pre-ram; + bootph-all; }; &main_sdhci1 { - bootph-pre-ram; + bootph-all; }; &wkup_i2c0 { - bootph-pre-ram; + bootph-all; }; &main_i2c0 { - bootph-pre-ram; + bootph-all; }; -&main_i2c0_pins_default { - bootph-pre-ram; +&exp1 { + bootph-all; }; &exp2 { - bootph-pre-ram; + bootph-all; }; &mcu_cpsw { - reg = <0x0 0x46000000 0x0 0x200000>, - <0x0 0x40f00200 0x0 0x8>; - reg-names = "cpsw_nuss", "mac_efuse"; - /delete-property/ ranges; - - cpsw-phy-sel@40f04040 { - compatible = "ti,am654-cpsw-phy-sel"; - reg= <0x0 0x40f04040 0x0 0x4>; - reg-names = "gmii-sel"; - }; + bootph-all; }; -&main_usbss0_pins_default { - bootph-pre-ram; +&mcu_uart0 { + bootph-all; }; -&usbss0 { - bootph-pre-ram; - ti,usb2-only; +&wkup_i2c0 { + bootph-all; }; -&usb0 { - dr_mode = "peripheral"; - bootph-pre-ram; +&wkup_uart0 { + bootph-all; }; -&mcu_fss0_hpb0_pins_default { - bootph-pre-ram; +&fss { + bootph-all; }; -&fss { - bootph-pre-ram; +&main_uart0_pins_default { + bootph-all; +}; + +&main_mmc1_pins_default { + bootph-all; +}; + +&main_i2c0_pins_default { + bootph-all; +}; + +&wkup_i2c0_pins_default { + bootph-all; +}; + +&wkup_uart0_pins_default { + bootph-all; +}; + +&wkup_gpio_pins_default { + bootph-all; +}; + +&wkup_gpio0 { + bootph-all; }; &hbmc { - bootph-pre-ram; + bootph-all; flash@0,0 { - bootph-pre-ram; + bootph-all; }; }; &hbmc_mux { - bootph-pre-ram; + bootph-all; +}; + +&usbss0 { + bootph-all; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; + +&ospi0 { + bootph-all; }; &serdes_ln_ctrl { - u-boot,mux-autoprobe; + bootph-all; }; &usb_serdes_mux { - u-boot,mux-autoprobe; + bootph-all; }; &serdes0 { - bootph-pre-ram; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; + bootph-all; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index ef5e807a80b..cee2b4b0eb8 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -9,12 +9,25 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/phy/phy.h> + #include "k3-serdes.h" / { + compatible = "ti,j7200-evm", "ti,j7200"; + model = "Texas Instruments J7200 EVM"; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial5 = &main_uart3; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; evm_12v0: fixedregulator-evm12v0 { @@ -78,47 +91,87 @@ }; &wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; +}; + +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + wkup_gpio_pins_default: wkup-gpio-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ + J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ + J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ + J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ + J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ + J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ + >; + }; + + main_uart3_pins_default: main-uart3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ + J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ @@ -131,15 +184,17 @@ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < - J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ + J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; }; +}; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { +&main_pmx1 { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < - J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ + J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; }; }; @@ -147,11 +202,30 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + clock-frequency = <96000000>; }; &main_uart0 { + status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&main_uart1 { + status = "okay"; + /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { @@ -160,59 +234,25 @@ }; &main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart4 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart6 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart7 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; + /* Shared with MCAN Interface */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins_default>; }; -&main_gpio6 { - status = "disabled"; +&main_gpio0 { + status = "okay"; }; -&wkup_gpio1 { - status = "disabled"; +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; }; &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { @@ -229,6 +269,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -256,6 +297,7 @@ * The i2c1 of the CPB (as it is labeled) is not connected to j7200. */ &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -273,6 +315,7 @@ &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -280,6 +323,7 @@ &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; vmmc-supply = <&vdd_mmc1>; diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index e8a41d09b45..cdb1d6b2a98 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -32,13 +32,20 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; - serdes_ln_ctrl: serdes-ln-ctrl@4080 { + serdes_ln_ctrl: mux-controller@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ }; + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; + ti,qsgmii-main-ports = <1>; + reg = <0x4044 0x10>; + #phy-cells = <1>; + }; + usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -54,7 +61,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -139,6 +149,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -148,6 +159,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -157,6 +169,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -166,6 +179,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -175,6 +189,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -184,6 +199,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -193,6 +209,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -202,6 +219,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -211,6 +229,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -220,6 +239,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -229,6 +249,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -238,15 +259,17 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x3c000000 0x00 0x400000>, - <0x00 0x38000000 0x00 0x400000>, - <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + reg = <0x00 0x3c000000 0x00 0x400000>, + <0x00 0x38000000 0x00 0x400000>, + <0x00 0x31120000 0x00 0x100>, + <0x00 0x33000000 0x00 0x40000>, + <0x00 0x31080000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -256,9 +279,9 @@ main_udmap: dma-controller@31150000 { compatible = "ti,j721e-navss-main-udmap"; - reg = <0x00 0x31150000 0x00 0x100>, - <0x00 0x34000000 0x00 0x100000>, - <0x00 0x35000000 0x00 0x100000>; + reg = <0x00 0x31150000 0x00 0x100>, + <0x00 0x34000000 0x00 0x100000>, + <0x00 0x35000000 0x00 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; @@ -289,10 +312,118 @@ }; }; + cpsw0: ethernet@c000000 { + compatible = "ti,j7200-cpswxg-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0xc000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + clocks = <&k3_clks 19 33>; + clock-names = "fck"; + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + cpsw0_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + status = "disabled"; + }; + + cpsw0_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + status = "disabled"; + }; + + cpsw0_port3: port@3 { + reg = <3>; + ti,mac-only; + label = "port3"; + status = "disabled"; + }; + + cpsw0_port4: port@4 { + reg = <4>; + ti,mac-only; + label = "port4"; + status = "disabled"; + }; + }; + + cpsw5g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 19 33>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 19 16>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x0 0x104200 0x0 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x0 0x104280 0x0 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x11c000 0x00 0x2b4>; + reg = <0x00 0x11c000 0x00 0x10c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinctrl@11c11c { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x11c11c 0x00 0xc>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; @@ -307,6 +438,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -318,6 +450,7 @@ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -329,6 +462,7 @@ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -340,6 +474,7 @@ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -351,6 +486,7 @@ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -362,6 +498,7 @@ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -373,6 +510,7 @@ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart7: serial@2870000 { @@ -384,6 +522,7 @@ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart8: serial@2880000 { @@ -395,6 +534,7 @@ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart9: serial@2890000 { @@ -406,6 +546,7 @@ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 2>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@2000000 { @@ -417,6 +558,7 @@ clock-names = "fck"; clocks = <&k3_clks 187 1>; power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; + status = "disabled"; }; main_i2c1: i2c@2010000 { @@ -428,6 +570,7 @@ clock-names = "fck"; clocks = <&k3_clks 188 1>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -439,6 +582,7 @@ clock-names = "fck"; clocks = <&k3_clks 189 1>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -450,6 +594,7 @@ clock-names = "fck"; clocks = <&k3_clks 190 1>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c4: i2c@2040000 { @@ -461,6 +606,7 @@ clock-names = "fck"; clocks = <&k3_clks 191 1>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c5: i2c@2050000 { @@ -472,6 +618,7 @@ clock-names = "fck"; clocks = <&k3_clks 192 1>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c6: i2c@2060000 { @@ -483,6 +630,7 @@ clock-names = "fck"; clocks = <&k3_clks 193 1>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_sdhci0: mmc@4f80000 { @@ -507,6 +655,7 @@ mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status = "disabled"; }; main_sdhci1: mmc@4fb0000 { @@ -530,6 +679,7 @@ ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; + status = "disabled"; }; serdes_wiz0: wiz@5060000 { @@ -606,10 +756,10 @@ clock-names = "fck"; #address-cells = <3>; #size-cells = <2>; - bus-range = <0x0 0xf>; + bus-range = <0x0 0xff>; cdns,no-bar-match-nbits = <64>; - vendor-id = /bits/ 16 <0x104c>; - device-id = /bits/ 16 <0xb00f>; + vendor-id = <0x104c>; + device-id = <0xb00f>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, @@ -633,6 +783,7 @@ clocks = <&k3_clks 240 6>; clock-names = "fck"; max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; dma-coherent; }; @@ -682,6 +833,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -699,6 +851,7 @@ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -716,6 +869,7 @@ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -733,6 +887,353 @@ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; + }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 266 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 267 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 268 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 269 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 270 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 271 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 272 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 273 1>; + status = "disabled"; + }; + + watchdog0: watchdog@2200000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x0 0x2200000 0x0 0x100>; + clocks = <&k3_clks 252 1>; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 252 1>; + assigned-clock-parents = <&k3_clks 252 5>; + }; + + watchdog1: watchdog@2210000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x0 0x2210000 0x0 0x100>; + clocks = <&k3_clks 253 1>; + power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 253 1>; + assigned-clock-parents = <&k3_clks 253 5>; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; + assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; + assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; + assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; + assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; + assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; + assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; + assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; + assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; + assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; + assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; }; main_r5fss0: r5fss@5c00000 { @@ -774,4 +1275,10 @@ ti,loczrama = <1>; }; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <656>, <657>; + }; }; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index 1044ec6c4b0..6ffaf85fa63 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -12,8 +12,8 @@ mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 11>, + <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44083000 0x00 0x1000>; @@ -34,6 +34,136 @@ }; }; + mcu_timer0: timer@40400000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer1: timer@40410000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; + assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer2: timer@40420000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer3: timer@40430000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; + assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer4: timer@40440000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer5: timer@40450000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; + assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer6: timer@40460000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer7: timer@40470000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; + assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer8: timer@40480000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer9: timer@40490000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; + assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + mcu_conf: syscon@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; @@ -53,10 +183,57 @@ reg = <0x00 0x43000014 0x00 0x4>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x34>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x8>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0xec>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c174 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c174 0x00 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; @@ -79,6 +256,7 @@ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 2>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart0: serial@40a00000 { @@ -90,6 +268,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 2>; clock-names = "fclk"; + status = "disabled"; }; wkup_gpio_intr: interrupt-controller@42200000 { @@ -118,6 +297,7 @@ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -134,6 +314,7 @@ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; mcu_navss: bus@28380000 { @@ -147,11 +328,13 @@ mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x2b800000 0x00 0x400000>, - <0x00 0x2b000000 0x00 0x400000>, - <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + reg = <0x00 0x2b800000 0x00 0x400000>, + <0x00 0x2b000000 0x00 0x400000>, + <0x00 0x28590000 0x00 0x100>, + <0x00 0x2a500000 0x00 0x40000>, + <0x00 0x28440000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", + "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -161,9 +344,9 @@ mcu_udmap: dma-controller@285c0000 { compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x00 0x285c0000 0x00 0x100>, - <0x00 0x2a800000 0x00 0x40000>, - <0x00 0x2aa00000 0x00 0x40000>; + reg = <0x00 0x285c0000 0x00 0x100>, + <0x00 0x2a800000 0x00 0x40000>, + <0x00 0x2aa00000 0x00 0x40000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; @@ -180,6 +363,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; @@ -249,6 +447,7 @@ clock-names = "fck"; clocks = <&k3_clks 194 1>; power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c1: i2c@40b10000 { @@ -260,6 +459,7 @@ clock-names = "fck"; clocks = <&k3_clks 195 1>; power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -271,6 +471,40 @@ clock-names = "fck"; clocks = <&k3_clks 197 1>; power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; + status = "disabled"; + }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 274 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 275 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 0>; + status = "disabled"; }; fss: syscon@47000000 { @@ -314,6 +548,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -325,7 +560,7 @@ clocks = <&k3_clks 0 1>; assigned-clocks = <&k3_clks 0 3>; assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; + clock-names = "fck"; dmas = <&main_udmap 0x7400>, <&main_udmap 0x7401>; dma-names = "fifo0", "fifo1"; @@ -375,4 +610,31 @@ ti,loczrama = <1>; }; }; + + mcu_crypto: crypto@40900000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, + <&mcu_udmap 0x7503>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@40910000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x40910000 0x00 0x7d>; + interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; /* Used by OP-TEE */ + }; + }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index e62f9218e83..f0a73605020 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -1,13 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; -#include "k3-j7200-som-p0.dtsi" +#include "k3-j7200-common-proc-board.dts" #include "k3-j7200-ddr-evm-lp4-2666.dtsi" #include "k3-j721e-ddr.dtsi" +#include "k3-j7200-common-proc-board-u-boot.dtsi" / { aliases { @@ -15,17 +16,6 @@ remoteproc1 = &a72_0; }; - chosen { - stdout-path = &main_uart0; - tick-timer = &timer1; - firmware-loader = &fs_loader0; - }; - - fs_loader0: fs_loader@0 { - bootph-all; - compatible = "u-boot,fs-loader"; - }; - a72_0: a72@0 { compatible = "ti,am654-rproc"; reg = <0x0 0x00a90000 0x0 0x10>; @@ -42,17 +32,13 @@ bootph-pre-ram; }; - clk_200mhz: dummy_clock_200mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - bootph-pre-ram; - }; - - clk_19_2mhz: dummy_clock_19_2mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes = <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; bootph-pre-ram; }; }; @@ -61,275 +47,38 @@ power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>, <&k3_pds 90 TI_SCI_PD_SHARED>; clocks = <&k3_clks 8 5>, <&k3_clks 30 9>; + bootph-pre-ram; }; -&cbass_mcu_wakeup { - mcu_secproxy: secproxy@2a380000 { - bootph-pre-ram; - compatible = "ti,am654-secure-proxy"; - reg = <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>, - <0x0 0x2a480000 0x0 0x80000>; - reg-names = "rt", "scfg", "target_data"; - #mbox-cells = <1>; - }; +&mcu_timer0 { + clock-frequency = <25000000>; + bootph-pre-ram; +}; +&secure_proxy_mcu { + bootph-pre-ram; + status = "okay"; +}; + +&cbass_mcu_wakeup { sysctrler: sysctrler { - bootph-pre-ram; compatible = "ti,am654-system-controller"; - mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; + mboxes= <&secure_proxy_mcu 4>, + <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&mcu_secproxy 21>, - <&mcu_secproxy 23>; bootph-pre-ram; }; - - wkup_vtm0: vtm@42040000 { - compatible = "ti,am654-vtm", "ti,j721e-avs"; - reg = <0x0 0x42040000 0x0 0x330>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; }; &dmsc { - mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; + mboxes = <&secure_proxy_mcu 8>, + <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx", "notify"; ti,host-id = <4>; ti,secure-host; -}; - -&wkup_pmx0 { - bootph-pre-ram; - wkup_uart0_pins_default: wkup_uart0_pins_default { - bootph-pre-ram; - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu_uart0_pins_default { - bootph-pre-ram; - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */ - J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */ - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ - >; - }; - - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ - >; - }; - - wkup_gpio_pins_default: wkup-gpio-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ - >; - }; -}; - -&main_pmx0 { - bootph-pre-ram; - - main_uart0_pins_default: main_uart0_pins_default { - bootph-pre-ram; - pinctrl-single,pins = < - J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ - J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ - J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ - J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ - >; - }; - - main_i2c0_pins_default: main-i2c0-pins-default { - bootph-pre-ram; - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; - - main_mmc1_pins_default: main_mmc1_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ - J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ - J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ - J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ - J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ - J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ - J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ - >; - }; - - main_usbss0_pins_default: main_usbss0_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ - >; - }; -}; - -&wkup_uart0 { bootph-pre-ram; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; - status = "okay"; -}; - -&mcu_uart0 { - /delete-property/ power-domains; - /delete-property/ clocks; - /delete-property/ clock-names; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; - status = "okay"; - clock-frequency = <96000000>; -}; - -&main_uart0 { - status = "okay"; - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - status = "okay"; -}; - -&main_sdhci0 { - /delete-property/ power-domains; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - clock-names = "clk_xin"; - clocks = <&clk_200mhz>; - ti,driver-strength-ohm = <50>; - non-removable; - bus-width = <8>; -}; - -&main_sdhci1 { - /delete-property/ power-domains; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - clock-names = "clk_xin"; - clocks = <&clk_200mhz>; - ti,driver-strength-ohm = <50>; -}; - -&wkup_i2c0 { - bootph-pre-ram; - lp876441: lp876441@4c { - compatible = "ti,lp876441"; - reg = <0x4c>; - bootph-pre-ram; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - regulators: regulators { - bootph-pre-ram; - buck1_reg: buck1 { - /*VDD_CPU_AVS_REG*/ - regulator-name = "buck1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - bootph-pre-ram; - }; - }; - }; - }; &wkup_vtm0 { - vdd-supply-2 = <&buck1_reg>; bootph-pre-ram; }; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&hbmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - reg = <0x0 0x47040000 0x0 0x100>, - <0x0 0x50000000 0x0 0x8000000>; - ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */ - <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x0 0x0 0x4000000>; - }; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; -#include "k3-j7200-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi index 34724440171..5a300d4c8ba 100644 --- a/arch/arm/dts/k3-j7200-som-p0.dtsi +++ b/arch/arm/dts/k3-j7200-som-p0.dtsi @@ -83,7 +83,7 @@ }; &wkup_pmx0 { - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ @@ -101,7 +101,7 @@ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ @@ -118,8 +118,17 @@ }; }; +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ @@ -140,10 +149,42 @@ flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "hbmc.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "hbmc.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "hbmc.env"; + reg = <0x700000 0x40000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; }; }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -158,6 +199,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -171,66 +213,26 @@ }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; @@ -252,11 +254,24 @@ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -267,7 +282,46 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; diff --git a/arch/arm/dts/k3-j7200-thermal.dtsi b/arch/arm/dts/k3-j7200-thermal.dtsi new file mode 100644 index 00000000000..e7e3a643a6f --- /dev/null +++ b/arch/arm/dts/k3-j7200-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/thermal/thermal.h> + +thermal_zones: thermal-zones { + mcu_thermal: mcu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main_thermal: main-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi index b7005b80314..ef73e6d7e85 100644 --- a/arch/arm/dts/k3-j7200.dtsi +++ b/arch/arm/dts/k3-j7200.dtsi @@ -7,9 +7,10 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J7200 SoC"; compatible = "ti,j7200"; @@ -17,21 +18,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - }; - chosen { }; cpus { @@ -60,7 +46,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; @@ -74,7 +60,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; }; @@ -82,15 +68,17 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; - cache-sets = <2048>; + cache-sets = <1024>; next-level-cache = <&msmc_l3>; }; msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { @@ -124,9 +112,11 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ @@ -165,6 +155,8 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ }; }; + + #include "k3-j7200-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi index a0285ce0520..5a6f9b11b8e 100644 --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 - * This file was generated on 04/12/2023 - */ + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1 + * This file was generated on 07/17/2022 +*/ #define DDRSS_PLL_FHS_CNT 10 #define DDRSS_PLL_FREQUENCY_0 27500000 @@ -54,11 +54,11 @@ #define DDRSS_CTL_41_DATA 0x1B60008B #define DDRSS_CTL_42_DATA 0x2000422B #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x040003C5 +#define DDRSS_CTL_44_DATA 0x0400078A #define DDRSS_CTL_45_DATA 0x1E161104 -#define DDRSS_CTL_46_DATA 0x1000922C +#define DDRSS_CTL_46_DATA 0x10012458 #define DDRSS_CTL_47_DATA 0x1E161110 -#define DDRSS_CTL_48_DATA 0x1000922C +#define DDRSS_CTL_48_DATA 0x10012458 #define DDRSS_CTL_49_DATA 0x02030410 #define DDRSS_CTL_50_DATA 0x2C040500 #define DDRSS_CTL_51_DATA 0x082D2C2D @@ -71,11 +71,11 @@ #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 #define DDRSS_CTL_60_DATA 0x00001008 -#define DDRSS_CTL_61_DATA 0x00000063 +#define DDRSS_CTL_61_DATA 0x000000CE #define DDRSS_CTL_62_DATA 0x00000256 -#define DDRSS_CTL_63_DATA 0x00001035 +#define DDRSS_CTL_63_DATA 0x00002073 #define DDRSS_CTL_64_DATA 0x00000256 -#define DDRSS_CTL_65_DATA 0x00001035 +#define DDRSS_CTL_65_DATA 0x00002073 #define DDRSS_CTL_66_DATA 0x00000005 #define DDRSS_CTL_67_DATA 0x00040000 #define DDRSS_CTL_68_DATA 0x00950012 @@ -112,27 +112,27 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x000018C0 -#define DDRSS_CTL_103_DATA 0x000018C0 -#define DDRSS_CTL_104_DATA 0x000018C0 -#define DDRSS_CTL_105_DATA 0x000018C0 -#define DDRSS_CTL_106_DATA 0x000018C0 +#define DDRSS_CTL_102_DATA 0x00003380 +#define DDRSS_CTL_103_DATA 0x00003380 +#define DDRSS_CTL_104_DATA 0x00003380 +#define DDRSS_CTL_105_DATA 0x00003380 +#define DDRSS_CTL_106_DATA 0x00003380 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x000002B5 -#define DDRSS_CTL_109_DATA 0x00040D40 -#define DDRSS_CTL_110_DATA 0x00040D40 -#define DDRSS_CTL_111_DATA 0x00040D40 -#define DDRSS_CTL_112_DATA 0x00040D40 -#define DDRSS_CTL_113_DATA 0x00040D40 +#define DDRSS_CTL_108_DATA 0x000005A2 +#define DDRSS_CTL_109_DATA 0x00081CC0 +#define DDRSS_CTL_110_DATA 0x00081CC0 +#define DDRSS_CTL_111_DATA 0x00081CC0 +#define DDRSS_CTL_112_DATA 0x00081CC0 +#define DDRSS_CTL_113_DATA 0x00081CC0 #define DDRSS_CTL_114_DATA 0x00000000 -#define DDRSS_CTL_115_DATA 0x00007173 -#define DDRSS_CTL_116_DATA 0x00040D40 -#define DDRSS_CTL_117_DATA 0x00040D40 -#define DDRSS_CTL_118_DATA 0x00040D40 -#define DDRSS_CTL_119_DATA 0x00040D40 -#define DDRSS_CTL_120_DATA 0x00040D40 +#define DDRSS_CTL_115_DATA 0x0000E325 +#define DDRSS_CTL_116_DATA 0x00081CC0 +#define DDRSS_CTL_117_DATA 0x00081CC0 +#define DDRSS_CTL_118_DATA 0x00081CC0 +#define DDRSS_CTL_119_DATA 0x00081CC0 +#define DDRSS_CTL_120_DATA 0x00081CC0 #define DDRSS_CTL_121_DATA 0x00000000 -#define DDRSS_CTL_122_DATA 0x00007173 +#define DDRSS_CTL_122_DATA 0x0000E325 #define DDRSS_CTL_123_DATA 0x00000000 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x00000000 @@ -399,29 +399,29 @@ #define DDRSS_CTL_386_DATA 0x00000000 #define DDRSS_CTL_387_DATA 0x3A3A1B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x000000C6 +#define DDRSS_CTL_389_DATA 0x0000019C #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x00000252 -#define DDRSS_CTL_395_DATA 0x000007BC +#define DDRSS_CTL_394_DATA 0x000004D4 +#define DDRSS_CTL_395_DATA 0x00001018 #define DDRSS_CTL_396_DATA 0x00000204 -#define DDRSS_CTL_397_DATA 0x0000206A +#define DDRSS_CTL_397_DATA 0x000040E6 #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x00000200 #define DDRSS_CTL_400_DATA 0x00000200 #define DDRSS_CTL_401_DATA 0x00000200 -#define DDRSS_CTL_402_DATA 0x0000613E -#define DDRSS_CTL_403_DATA 0x00014424 +#define DDRSS_CTL_402_DATA 0x0000C2B2 +#define DDRSS_CTL_403_DATA 0x000288FC #define DDRSS_CTL_404_DATA 0x00000E15 -#define DDRSS_CTL_405_DATA 0x0000206A +#define DDRSS_CTL_405_DATA 0x000040E6 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 #define DDRSS_CTL_409_DATA 0x00000200 -#define DDRSS_CTL_410_DATA 0x0000613E -#define DDRSS_CTL_411_DATA 0x00014424 +#define DDRSS_CTL_410_DATA 0x0000C2B2 +#define DDRSS_CTL_411_DATA 0x000288FC #define DDRSS_CTL_412_DATA 0x02020E15 #define DDRSS_CTL_413_DATA 0x03030202 #define DDRSS_CTL_414_DATA 0x00000022 @@ -640,11 +640,11 @@ #define DDRSS_PI_167_DATA 0x02000200 #define DDRSS_PI_168_DATA 0x48120C04 #define DDRSS_PI_169_DATA 0x00104812 -#define DDRSS_PI_170_DATA 0x00000063 +#define DDRSS_PI_170_DATA 0x000000CE #define DDRSS_PI_171_DATA 0x00000256 -#define DDRSS_PI_172_DATA 0x00001035 +#define DDRSS_PI_172_DATA 0x00002073 #define DDRSS_PI_173_DATA 0x00000256 -#define DDRSS_PI_174_DATA 0x04001035 +#define DDRSS_PI_174_DATA 0x04002073 #define DDRSS_PI_175_DATA 0x01010404 #define DDRSS_PI_176_DATA 0x00001501 #define DDRSS_PI_177_DATA 0x00150015 @@ -689,22 +689,22 @@ #define DDRSS_PI_216_DATA 0x3212005B #define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x04000364 +#define DDRSS_PI_219_DATA 0x040006C9 #define DDRSS_PI_220_DATA 0x0A032001 #define DDRSS_PI_221_DATA 0x2C31110A #define DDRSS_PI_222_DATA 0x00002D1C -#define DDRSS_PI_223_DATA 0x6000838E +#define DDRSS_PI_223_DATA 0x6001071C #define DDRSS_PI_224_DATA 0x1E202008 #define DDRSS_PI_225_DATA 0x2C311116 #define DDRSS_PI_226_DATA 0x00002D1C -#define DDRSS_PI_227_DATA 0x6000838E +#define DDRSS_PI_227_DATA 0x6001071C #define DDRSS_PI_228_DATA 0x1E202008 -#define DDRSS_PI_229_DATA 0x0000C616 -#define DDRSS_PI_230_DATA 0x000007BC -#define DDRSS_PI_231_DATA 0x0000206A -#define DDRSS_PI_232_DATA 0x00014424 -#define DDRSS_PI_233_DATA 0x0000206A -#define DDRSS_PI_234_DATA 0x00014424 +#define DDRSS_PI_229_DATA 0x00019C16 +#define DDRSS_PI_230_DATA 0x00001018 +#define DDRSS_PI_231_DATA 0x000040E6 +#define DDRSS_PI_232_DATA 0x000288FC +#define DDRSS_PI_233_DATA 0x000040E6 +#define DDRSS_PI_234_DATA 0x000288FC #define DDRSS_PI_235_DATA 0x02660010 #define DDRSS_PI_236_DATA 0x03030266 #define DDRSS_PI_237_DATA 0x002AF803 diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index f940ffee878..a3ebf5996ea 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -1,68 +1,36 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-j721s2-binman.dtsi" -/ { - chosen { - stdout-path = "serial2:115200n8"; - tick-timer = &timer1; - }; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart8; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &mcu_i2c1; - i2c3 = &main_i2c0; - ethernet0 = &cpsw_port1; - }; -}; - &wkup_i2c0 { - bootph-pre-ram; + bootph-all; }; &cbass_main { - bootph-pre-ram; + bootph-all; }; &main_navss { - bootph-pre-ram; + bootph-all; }; &cbass_mcu_wakeup { - bootph-pre-ram; - - timer1: timer@40400000 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x40400000 0x0 0x80>; - ti,timer-alwon; - clock-frequency = <250000000>; - bootph-pre-ram; - }; + bootph-all; chipid@43000014 { - bootph-pre-ram; + bootph-all; }; }; &mcu_navss { - bootph-pre-ram; + bootph-all; }; &mcu_ringacc { - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - bootph-pre-ram; + bootph-all; }; &mcu_udmap { @@ -74,78 +42,86 @@ <0x0 0x28400000 0x0 0x2000>; reg-names = "gcfg", "rchan", "rchanrt", "tchan", "tchanrt", "rflow"; - bootph-pre-ram; + bootph-all; }; &secure_proxy_main { - bootph-pre-ram; + bootph-all; }; &sms { - bootph-pre-ram; + bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - bootph-pre-ram; + bootph-all; }; }; &main_pmx0 { - bootph-pre-ram; + bootph-all; }; &main_uart8_pins_default { - bootph-pre-ram; + bootph-all; }; &main_mmc1_pins_default { - bootph-pre-ram; + bootph-all; +}; + +&main_usbss0_pins_default { + bootph-all; }; &wkup_pmx0 { - bootph-pre-ram; + bootph-all; }; &k3_pds { - bootph-pre-ram; + bootph-all; }; &k3_clks { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &main_uart8 { - bootph-pre-ram; + bootph-all; }; &mcu_uart0 { - bootph-pre-ram; + bootph-all; }; &wkup_uart0 { - bootph-pre-ram; + bootph-all; +}; + +&main_sdhci0 { + bootph-all; }; -&mcu_cpsw { - reg = <0x0 0x46000000 0x0 0x200000>, - <0x0 0x40f00200 0x0 0x8>; - reg-names = "cpsw_nuss", "mac_efuse"; - /delete-property/ ranges; +&main_sdhci1 { + bootph-all; +}; - cpsw-phy-sel@40f04040 { - compatible = "ti,am654-cpsw-phy-sel"; - reg= <0x0 0x40f04040 0x0 0x4>; - reg-names = "gmii-sel"; - }; +&ospi0 { + status = "disabled"; }; -&main_sdhci0 { - bootph-pre-ram; +&ospi1 { + status = "disabled"; }; -&main_sdhci1 { - bootph-pre-ram; +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; }; diff --git a/arch/arm/dts/k3-j721s2-common-proc-board.dts b/arch/arm/dts/k3-j721s2-common-proc-board.dts index 3bba6473a3b..c6b85bbf9a1 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-common-proc-board.dts @@ -2,13 +2,17 @@ /* * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * - * Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439 + * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM */ /dts-v1/; #include "k3-j721s2-som-p0.dtsi" #include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-cadence.h> +#include <dt-bindings/phy/phy.h> + +#include "k3-serdes.h" / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -16,16 +20,18 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000"; }; aliases { + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; can0 = &main_mcan16; can1 = &mcu_mcan0; can2 = &mcu_mcan1; + can3 = &main_mcan3; + can4 = &main_mcan5; }; evm_12v0: fixedregulator-evm12v0 { @@ -106,10 +112,26 @@ standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; }; + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states = <&mux0 1>; + }; + + transceiver4: can-phy4 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; + mux-states = <&mux1 1>; + }; }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ @@ -118,14 +140,14 @@ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ @@ -138,129 +160,173 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; -}; -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + main_mcan3_pins_default: main-mcan3-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + main_mcan5_pins_default: main-mcan5-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ >; }; +}; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { +&wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; }; - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; -}; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; -&main_gpio6 { - status = "disabled"; -}; + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; -&wkup_gpio1 { - status = "disabled"; -}; + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; -&wkup_uart0 { - status = "reserved"; -}; + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ + >; + }; -&main_uart0 { - status = "disabled"; -}; + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + >; + }; -&main_uart1 { - status = "disabled"; -}; + mcu_adc0_pins_default: mcu-adc0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ + J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ + J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ + J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ + J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ + J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ + J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ + >; + }; -&main_uart2 { - status = "disabled"; + mcu_adc1_pins_default: mcu-adc1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ + J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ + J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ + J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ + J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ + J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ + J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ + J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ + >; + }; }; -&main_uart3 { - status = "disabled"; +&wkup_pmx1 { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; -&main_uart4 { - status = "disabled"; +&main_gpio0 { + status = "okay"; }; -&main_uart5 { - status = "disabled"; +&wkup_gpio0 { + status = "okay"; }; -&main_uart6 { - status = "disabled"; +&wkup_uart0 { + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; -&main_uart7 { - status = "disabled"; +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; }; -&main_uart9 { - status = "disabled"; -}; - &main_i2c0 { clock-frequency = <400000>; @@ -290,32 +356,9 @@ }; }; -&main_i2c1 { - status = "disabled"; -}; - -&main_i2c2 { - status = "disabled"; -}; - -&main_i2c3 { - status = "disabled"; -}; - -&main_i2c4 { - status = "disabled"; -}; - -&main_i2c5 { - status = "disabled"; -}; - -&main_i2c6 { - status = "disabled"; -}; - &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -323,6 +366,7 @@ &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; disable-wp; @@ -332,7 +376,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { @@ -349,82 +393,112 @@ phy-handle = <&phy0>; }; -&mcu_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; +&serdes_ln_ctrl { + idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, + <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; }; -&main_mcan0 { - status = "disabled"; +&serdes_refclk { + clock-frequency = <100000000>; }; -&main_mcan1 { - status = "disabled"; -}; - -&main_mcan2 { - status = "disabled"; -}; - -&main_mcan3 { - status = "disabled"; -}; - -&main_mcan4 { - status = "disabled"; -}; - -&main_mcan5 { - status = "disabled"; +&serdes0 { + status = "okay"; + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; }; -&main_mcan6 { - status = "disabled"; +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ }; -&main_mcan7 { - status = "disabled"; +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; + ti,usb2-only; }; -&main_mcan8 { - status = "disabled"; +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; }; -&main_mcan9 { - status = "disabled"; +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + }; }; -&main_mcan10 { - status = "disabled"; +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; }; -&main_mcan11 { - status = "disabled"; +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; }; -&main_mcan12 { - status = "disabled"; +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; }; -&main_mcan13 { - status = "disabled"; +&tscadc0 { + pinctrl-0 = <&mcu_adc0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; }; -&main_mcan14 { - status = "disabled"; +&tscadc1 { + pinctrl-0 = <&mcu_adc1_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; }; -&main_mcan15 { - status = "disabled"; +&main_mcan3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan3_pins_default>; + phys = <&transceiver3>; }; -&main_mcan17 { - status = "disabled"; +&main_mcan5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan5_pins_default>; + phys = <&transceiver4>; }; diff --git a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi index 45fa0619160..c91576bf093 100644 --- a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 - * This file was generated on 04/12/2023 + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0 + * This file was generated on 10/14/2021 */ -#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FHS_CNT 10 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -60,11 +60,11 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x040003C5 +#define DDRSS0_CTL_44_DATA 0x0400078A #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x1000922C +#define DDRSS0_CTL_46_DATA 0x10012458 #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x1000922C +#define DDRSS0_CTL_48_DATA 0x10012458 #define DDRSS0_CTL_49_DATA 0x02030410 #define DDRSS0_CTL_50_DATA 0x2C040500 #define DDRSS0_CTL_51_DATA 0x08292C29 @@ -77,11 +77,11 @@ #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x00000063 +#define DDRSS0_CTL_61_DATA 0x000000CE #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00001035 +#define DDRSS0_CTL_63_DATA 0x00002073 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00001035 +#define DDRSS0_CTL_65_DATA 0x00002073 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 #define DDRSS0_CTL_68_DATA 0x00CB0012 @@ -118,27 +118,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x000018C0 -#define DDRSS0_CTL_103_DATA 0x000018C0 -#define DDRSS0_CTL_104_DATA 0x000018C0 -#define DDRSS0_CTL_105_DATA 0x000018C0 -#define DDRSS0_CTL_106_DATA 0x000018C0 +#define DDRSS0_CTL_102_DATA 0x00003380 +#define DDRSS0_CTL_103_DATA 0x00003380 +#define DDRSS0_CTL_104_DATA 0x00003380 +#define DDRSS0_CTL_105_DATA 0x00003380 +#define DDRSS0_CTL_106_DATA 0x00003380 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000002B5 -#define DDRSS0_CTL_109_DATA 0x00040D40 -#define DDRSS0_CTL_110_DATA 0x00040D40 -#define DDRSS0_CTL_111_DATA 0x00040D40 -#define DDRSS0_CTL_112_DATA 0x00040D40 -#define DDRSS0_CTL_113_DATA 0x00040D40 +#define DDRSS0_CTL_108_DATA 0x000005A2 +#define DDRSS0_CTL_109_DATA 0x00081CC0 +#define DDRSS0_CTL_110_DATA 0x00081CC0 +#define DDRSS0_CTL_111_DATA 0x00081CC0 +#define DDRSS0_CTL_112_DATA 0x00081CC0 +#define DDRSS0_CTL_113_DATA 0x00081CC0 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x00007173 -#define DDRSS0_CTL_116_DATA 0x00040D40 -#define DDRSS0_CTL_117_DATA 0x00040D40 -#define DDRSS0_CTL_118_DATA 0x00040D40 -#define DDRSS0_CTL_119_DATA 0x00040D40 -#define DDRSS0_CTL_120_DATA 0x00040D40 +#define DDRSS0_CTL_115_DATA 0x0000E325 +#define DDRSS0_CTL_116_DATA 0x00081CC0 +#define DDRSS0_CTL_117_DATA 0x00081CC0 +#define DDRSS0_CTL_118_DATA 0x00081CC0 +#define DDRSS0_CTL_119_DATA 0x00081CC0 +#define DDRSS0_CTL_120_DATA 0x00081CC0 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x00007173 +#define DDRSS0_CTL_122_DATA 0x0000E325 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -192,17 +192,17 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0xB3003FF4 -#define DDRSS0_CTL_177_DATA 0x0000B3B3 -#define DDRSS0_CTL_178_DATA 0x36000000 -#define DDRSS0_CTL_179_DATA 0x27270036 +#define DDRSS0_CTL_176_DATA 0x33003FF4 +#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_178_DATA 0x56000000 +#define DDRSS0_CTL_179_DATA 0x27270056 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0xB3B3B300 +#define DDRSS0_CTL_184_DATA 0x33333300 #define DDRSS0_CTL_185_DATA 0x00000000 -#define DDRSS0_CTL_186_DATA 0x00363600 +#define DDRSS0_CTL_186_DATA 0x00565600 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 @@ -245,17 +245,17 @@ #define DDRSS0_CTL_226_DATA 0x00000000 #define DDRSS0_CTL_227_DATA 0x15110000 #define DDRSS0_CTL_228_DATA 0x00040C18 -#define DDRSS0_CTL_229_DATA 0xF000C000 -#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_229_DATA 0x00000000 +#define DDRSS0_CTL_230_DATA 0x00000000 #define DDRSS0_CTL_231_DATA 0x00000000 #define DDRSS0_CTL_232_DATA 0x00000000 -#define DDRSS0_CTL_233_DATA 0xC0000000 -#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_233_DATA 0x00000000 +#define DDRSS0_CTL_234_DATA 0x00000000 #define DDRSS0_CTL_235_DATA 0x00000000 #define DDRSS0_CTL_236_DATA 0x00000000 #define DDRSS0_CTL_237_DATA 0x00000000 -#define DDRSS0_CTL_238_DATA 0xF000C000 -#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_238_DATA 0x00000000 +#define DDRSS0_CTL_239_DATA 0x00000000 #define DDRSS0_CTL_240_DATA 0x00000000 #define DDRSS0_CTL_241_DATA 0x00000000 #define DDRSS0_CTL_242_DATA 0x00030000 @@ -283,7 +283,7 @@ #define DDRSS0_CTL_264_DATA 0x00000040 #define DDRSS0_CTL_265_DATA 0x006B0003 #define DDRSS0_CTL_266_DATA 0x0100006B -#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_267_DATA 0x00000000 #define DDRSS0_CTL_268_DATA 0x00000000 #define DDRSS0_CTL_269_DATA 0x00000202 #define DDRSS0_CTL_270_DATA 0x00001FFF @@ -307,7 +307,7 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000101 +#define DDRSS0_CTL_291_DATA 0x00000001 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 @@ -405,29 +405,29 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x000000C6 +#define DDRSS0_CTL_389_DATA 0x0000019C #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x00000252 -#define DDRSS0_CTL_395_DATA 0x000007BC +#define DDRSS0_CTL_394_DATA 0x000004D4 +#define DDRSS0_CTL_395_DATA 0x00001018 #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x0000206A +#define DDRSS0_CTL_397_DATA 0x000040E6 #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000613E -#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_402_DATA 0x0000C2B2 +#define DDRSS0_CTL_403_DATA 0x000288FC #define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x0000206A +#define DDRSS0_CTL_405_DATA 0x000040E6 #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000613E -#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_410_DATA 0x0000C2B2 +#define DDRSS0_CTL_411_DATA 0x000288FC #define DDRSS0_CTL_412_DATA 0x02020E15 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 @@ -488,8 +488,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000003 -#define DDRSS0_PI_13_DATA 0x00010001 +#define DDRSS0_PI_12_DATA 0x00000007 +#define DDRSS0_PI_13_DATA 0x00010002 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +537,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020201 +#define DDRSS0_PI_61_DATA 0x10020101 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 -#define DDRSS0_PI_66_DATA 0x01000100 -#define DDRSS0_PI_67_DATA 0x0102020F +#define DDRSS0_PI_66_DATA 0x00000100 +#define DDRSS0_PI_67_DATA 0x0001010F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x01000000 +#define DDRSS0_PI_72_DATA 0x00000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -646,19 +646,19 @@ #define DDRSS0_PI_167_DATA 0x02000200 #define DDRSS0_PI_168_DATA 0x48120C04 #define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x00000063 +#define DDRSS0_PI_170_DATA 0x000000CE #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00001035 +#define DDRSS0_PI_172_DATA 0x00002073 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04001035 +#define DDRSS0_PI_174_DATA 0x04002073 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001500 +#define DDRSS0_PI_176_DATA 0x00001501 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000000 +#define DDRSS0_PI_182_DATA 0x00000101 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 #define DDRSS0_PI_185_DATA 0x15040000 @@ -667,7 +667,7 @@ #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01000101 +#define DDRSS0_PI_191_DATA 0x01010101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -693,24 +693,24 @@ #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 #define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_217_DATA 0x09000301 #define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x04000364 +#define DDRSS0_PI_219_DATA 0x040006C9 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6000838E +#define DDRSS0_PI_223_DATA 0x6001071C #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6000838E +#define DDRSS0_PI_227_DATA 0x6001071C #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x0000C616 -#define DDRSS0_PI_230_DATA 0x000007BC -#define DDRSS0_PI_231_DATA 0x0000206A -#define DDRSS0_PI_232_DATA 0x00014424 -#define DDRSS0_PI_233_DATA 0x0000206A -#define DDRSS0_PI_234_DATA 0x00014424 +#define DDRSS0_PI_229_DATA 0x00019C16 +#define DDRSS0_PI_230_DATA 0x00001018 +#define DDRSS0_PI_231_DATA 0x000040E6 +#define DDRSS0_PI_232_DATA 0x000288FC +#define DDRSS0_PI_233_DATA 0x000040E6 +#define DDRSS0_PI_234_DATA 0x000288FC #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -751,29 +751,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00B30084 +#define DDRSS0_PI_275_DATA 0x00330084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x36B33FF4 +#define DDRSS0_PI_277_DATA 0x56333FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x36B33FF4 +#define DDRSS0_PI_279_DATA 0x56333FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00B30084 +#define DDRSS0_PI_281_DATA 0x00330084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x36B33FF4 +#define DDRSS0_PI_283_DATA 0x56333FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x36B33FF4 +#define DDRSS0_PI_285_DATA 0x56333FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00B30084 +#define DDRSS0_PI_287_DATA 0x00330084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x36B33FF4 +#define DDRSS0_PI_289_DATA 0x56333FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x36B33FF4 +#define DDRSS0_PI_291_DATA 0x56333FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00B30084 +#define DDRSS0_PI_293_DATA 0x00330084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x36B33FF4 +#define DDRSS0_PI_295_DATA 0x56333FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x36B33FF4 +#define DDRSS0_PI_297_DATA 0x56333FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +789,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000200 +#define DDRSS0_PHY_12_DATA 0x00000100 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,9 +808,9 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F08 -#define DDRSS0_PHY_32_DATA 0x10400000 -#define DDRSS0_PHY_33_DATA 0x0C002002 +#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_32_DATA 0x10200000 +#define DDRSS0_PHY_33_DATA 0x0C002006 #define DDRSS0_PHY_34_DATA 0x00000000 #define DDRSS0_PHY_35_DATA 0x00000000 #define DDRSS0_PHY_36_DATA 0x55555555 @@ -877,7 +877,7 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB01AB +#define DDRSS0_PHY_100_DATA 0x07AB0340 #define DDRSS0_PHY_101_DATA 0x00C0C001 #define DDRSS0_PHY_102_DATA 0x0E0D0001 #define DDRSS0_PHY_103_DATA 0x10001000 @@ -913,7 +913,7 @@ #define DDRSS0_PHY_133_DATA 0x00000000 #define DDRSS0_PHY_134_DATA 0x00080200 #define DDRSS0_PHY_135_DATA 0x00000000 -#define DDRSS0_PHY_136_DATA 0x20202020 +#define DDRSS0_PHY_136_DATA 0x20202000 #define DDRSS0_PHY_137_DATA 0x20202020 #define DDRSS0_PHY_138_DATA 0xF0F02020 #define DDRSS0_PHY_139_DATA 0x00000000 @@ -1045,7 +1045,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000200 +#define DDRSS0_PHY_268_DATA 0x00000100 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,9 +1064,9 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F08 -#define DDRSS0_PHY_288_DATA 0x10400000 -#define DDRSS0_PHY_289_DATA 0x0C002002 +#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_288_DATA 0x10200000 +#define DDRSS0_PHY_289_DATA 0x0C002006 #define DDRSS0_PHY_290_DATA 0x00000000 #define DDRSS0_PHY_291_DATA 0x00000000 #define DDRSS0_PHY_292_DATA 0x55555555 @@ -1133,7 +1133,7 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB01AB +#define DDRSS0_PHY_356_DATA 0x07AB0340 #define DDRSS0_PHY_357_DATA 0x00C0C001 #define DDRSS0_PHY_358_DATA 0x0E0D0001 #define DDRSS0_PHY_359_DATA 0x10001000 @@ -1169,7 +1169,7 @@ #define DDRSS0_PHY_389_DATA 0x00000000 #define DDRSS0_PHY_390_DATA 0x00080200 #define DDRSS0_PHY_391_DATA 0x00000000 -#define DDRSS0_PHY_392_DATA 0x20202020 +#define DDRSS0_PHY_392_DATA 0x20202000 #define DDRSS0_PHY_393_DATA 0x20202020 #define DDRSS0_PHY_394_DATA 0xF0F02020 #define DDRSS0_PHY_395_DATA 0x00000000 @@ -1301,7 +1301,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000200 +#define DDRSS0_PHY_524_DATA 0x00000100 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,9 +1320,9 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F08 -#define DDRSS0_PHY_544_DATA 0x10400000 -#define DDRSS0_PHY_545_DATA 0x0C002002 +#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_544_DATA 0x10200000 +#define DDRSS0_PHY_545_DATA 0x0C002006 #define DDRSS0_PHY_546_DATA 0x00000000 #define DDRSS0_PHY_547_DATA 0x00000000 #define DDRSS0_PHY_548_DATA 0x55555555 @@ -1389,7 +1389,7 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB01AB +#define DDRSS0_PHY_612_DATA 0x07AB0340 #define DDRSS0_PHY_613_DATA 0x00C0C001 #define DDRSS0_PHY_614_DATA 0x0E0D0001 #define DDRSS0_PHY_615_DATA 0x10001000 @@ -1425,7 +1425,7 @@ #define DDRSS0_PHY_645_DATA 0x00000000 #define DDRSS0_PHY_646_DATA 0x00080200 #define DDRSS0_PHY_647_DATA 0x00000000 -#define DDRSS0_PHY_648_DATA 0x20202020 +#define DDRSS0_PHY_648_DATA 0x20202000 #define DDRSS0_PHY_649_DATA 0x20202020 #define DDRSS0_PHY_650_DATA 0xF0F02020 #define DDRSS0_PHY_651_DATA 0x00000000 @@ -1557,7 +1557,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000200 +#define DDRSS0_PHY_780_DATA 0x00000100 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,9 +1576,9 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F08 -#define DDRSS0_PHY_800_DATA 0x10400000 -#define DDRSS0_PHY_801_DATA 0x0C002002 +#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_800_DATA 0x10200000 +#define DDRSS0_PHY_801_DATA 0x0C002006 #define DDRSS0_PHY_802_DATA 0x00000000 #define DDRSS0_PHY_803_DATA 0x00000000 #define DDRSS0_PHY_804_DATA 0x55555555 @@ -1645,7 +1645,7 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB01AB +#define DDRSS0_PHY_868_DATA 0x07AB0340 #define DDRSS0_PHY_869_DATA 0x00C0C001 #define DDRSS0_PHY_870_DATA 0x0E0D0001 #define DDRSS0_PHY_871_DATA 0x10001000 @@ -1681,7 +1681,7 @@ #define DDRSS0_PHY_901_DATA 0x00000000 #define DDRSS0_PHY_902_DATA 0x00080200 #define DDRSS0_PHY_903_DATA 0x00000000 -#define DDRSS0_PHY_904_DATA 0x20202020 +#define DDRSS0_PHY_904_DATA 0x20202000 #define DDRSS0_PHY_905_DATA 0x20202020 #define DDRSS0_PHY_906_DATA 0xF0F02020 #define DDRSS0_PHY_907_DATA 0x00000000 @@ -2080,14 +2080,14 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x00000064 +#define DDRSS0_PHY_1303_DATA 0x0000FFFF #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 #define DDRSS0_PHY_1307_DATA 0x01200F02 #define DDRSS0_PHY_1308_DATA 0x00194280 #define DDRSS0_PHY_1309_DATA 0x00000004 -#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1310_DATA 0x00052000 #define DDRSS0_PHY_1311_DATA 0x00000000 #define DDRSS0_PHY_1312_DATA 0x00000000 #define DDRSS0_PHY_1313_DATA 0x00000000 @@ -2174,7 +2174,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x040207AB +#define DDRSS0_PHY_1397_DATA 0x010207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2236,7 +2236,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12501250 +#define DDRSS1_CTL_35_DATA 0x12481248 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2245,11 +2245,11 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x040003C5 +#define DDRSS1_CTL_44_DATA 0x0400078A #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x1000922C +#define DDRSS1_CTL_46_DATA 0x10012458 #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x1000922C +#define DDRSS1_CTL_48_DATA 0x10012458 #define DDRSS1_CTL_49_DATA 0x02030410 #define DDRSS1_CTL_50_DATA 0x2C040500 #define DDRSS1_CTL_51_DATA 0x08292C29 @@ -2262,11 +2262,11 @@ #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x00000063 +#define DDRSS1_CTL_61_DATA 0x000000CE #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00001035 +#define DDRSS1_CTL_63_DATA 0x00002073 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00001035 +#define DDRSS1_CTL_65_DATA 0x00002073 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 #define DDRSS1_CTL_68_DATA 0x00CB0012 @@ -2303,27 +2303,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x000018C0 -#define DDRSS1_CTL_103_DATA 0x000018C0 -#define DDRSS1_CTL_104_DATA 0x000018C0 -#define DDRSS1_CTL_105_DATA 0x000018C0 -#define DDRSS1_CTL_106_DATA 0x000018C0 +#define DDRSS1_CTL_102_DATA 0x00003380 +#define DDRSS1_CTL_103_DATA 0x00003380 +#define DDRSS1_CTL_104_DATA 0x00003380 +#define DDRSS1_CTL_105_DATA 0x00003380 +#define DDRSS1_CTL_106_DATA 0x00003380 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000002B5 -#define DDRSS1_CTL_109_DATA 0x00040D40 -#define DDRSS1_CTL_110_DATA 0x00040D40 -#define DDRSS1_CTL_111_DATA 0x00040D40 -#define DDRSS1_CTL_112_DATA 0x00040D40 -#define DDRSS1_CTL_113_DATA 0x00040D40 +#define DDRSS1_CTL_108_DATA 0x000005A2 +#define DDRSS1_CTL_109_DATA 0x00081CC0 +#define DDRSS1_CTL_110_DATA 0x00081CC0 +#define DDRSS1_CTL_111_DATA 0x00081CC0 +#define DDRSS1_CTL_112_DATA 0x00081CC0 +#define DDRSS1_CTL_113_DATA 0x00081CC0 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x00007173 -#define DDRSS1_CTL_116_DATA 0x00040D40 -#define DDRSS1_CTL_117_DATA 0x00040D40 -#define DDRSS1_CTL_118_DATA 0x00040D40 -#define DDRSS1_CTL_119_DATA 0x00040D40 -#define DDRSS1_CTL_120_DATA 0x00040D40 +#define DDRSS1_CTL_115_DATA 0x0000E325 +#define DDRSS1_CTL_116_DATA 0x00081CC0 +#define DDRSS1_CTL_117_DATA 0x00081CC0 +#define DDRSS1_CTL_118_DATA 0x00081CC0 +#define DDRSS1_CTL_119_DATA 0x00081CC0 +#define DDRSS1_CTL_120_DATA 0x00081CC0 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x00007173 +#define DDRSS1_CTL_122_DATA 0x0000E325 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2377,17 +2377,17 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0xF3003FF4 -#define DDRSS1_CTL_177_DATA 0x0000F3F3 -#define DDRSS1_CTL_178_DATA 0x36000000 -#define DDRSS1_CTL_179_DATA 0x27270036 +#define DDRSS1_CTL_176_DATA 0x33003FF4 +#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_178_DATA 0x56000000 +#define DDRSS1_CTL_179_DATA 0x27270056 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0xF3F3F300 +#define DDRSS1_CTL_184_DATA 0x33333300 #define DDRSS1_CTL_185_DATA 0x00000000 -#define DDRSS1_CTL_186_DATA 0x00363600 +#define DDRSS1_CTL_186_DATA 0x00565600 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 @@ -2430,17 +2430,17 @@ #define DDRSS1_CTL_226_DATA 0x00000000 #define DDRSS1_CTL_227_DATA 0x15110000 #define DDRSS1_CTL_228_DATA 0x00040C18 -#define DDRSS1_CTL_229_DATA 0xF000C000 -#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_229_DATA 0x00000000 +#define DDRSS1_CTL_230_DATA 0x00000000 #define DDRSS1_CTL_231_DATA 0x00000000 #define DDRSS1_CTL_232_DATA 0x00000000 -#define DDRSS1_CTL_233_DATA 0xC0000000 -#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_233_DATA 0x00000000 +#define DDRSS1_CTL_234_DATA 0x00000000 #define DDRSS1_CTL_235_DATA 0x00000000 #define DDRSS1_CTL_236_DATA 0x00000000 #define DDRSS1_CTL_237_DATA 0x00000000 -#define DDRSS1_CTL_238_DATA 0xF000C000 -#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_238_DATA 0x00000000 +#define DDRSS1_CTL_239_DATA 0x00000000 #define DDRSS1_CTL_240_DATA 0x00000000 #define DDRSS1_CTL_241_DATA 0x00000000 #define DDRSS1_CTL_242_DATA 0x00030000 @@ -2468,7 +2468,7 @@ #define DDRSS1_CTL_264_DATA 0x00000040 #define DDRSS1_CTL_265_DATA 0x006B0003 #define DDRSS1_CTL_266_DATA 0x0100006B -#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_267_DATA 0x00000000 #define DDRSS1_CTL_268_DATA 0x00000000 #define DDRSS1_CTL_269_DATA 0x00000202 #define DDRSS1_CTL_270_DATA 0x00001FFF @@ -2492,7 +2492,7 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00010101 +#define DDRSS1_CTL_291_DATA 0x00000001 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 @@ -2520,7 +2520,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10082323 +#define DDRSS1_CTL_319_DATA 0x10081F1F #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2590,30 +2590,30 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x000000C6 +#define DDRSS1_CTL_389_DATA 0x0000019C #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x00000252 -#define DDRSS1_CTL_395_DATA 0x000007BC +#define DDRSS1_CTL_394_DATA 0x000004D4 +#define DDRSS1_CTL_395_DATA 0x00001018 #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x0000206A +#define DDRSS1_CTL_397_DATA 0x000040E6 #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000613E -#define DDRSS1_CTL_403_DATA 0x00014424 -#define DDRSS1_CTL_404_DATA 0x00000E19 -#define DDRSS1_CTL_405_DATA 0x0000206A +#define DDRSS1_CTL_402_DATA 0x0000C2B2 +#define DDRSS1_CTL_403_DATA 0x000288FC +#define DDRSS1_CTL_404_DATA 0x00000E15 +#define DDRSS1_CTL_405_DATA 0x000040E6 #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000613E -#define DDRSS1_CTL_411_DATA 0x00014424 -#define DDRSS1_CTL_412_DATA 0x02020E19 +#define DDRSS1_CTL_410_DATA 0x0000C2B2 +#define DDRSS1_CTL_411_DATA 0x000288FC +#define DDRSS1_CTL_412_DATA 0x02020E15 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2630,7 +2630,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B220B22 +#define DDRSS1_CTL_429_DATA 0x0B1E0B1E #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2673,8 +2673,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000003 -#define DDRSS1_PI_13_DATA 0x00010001 +#define DDRSS1_PI_12_DATA 0x00000007 +#define DDRSS1_PI_13_DATA 0x00010002 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2722,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020201 +#define DDRSS1_PI_61_DATA 0x10020101 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0002020F +#define DDRSS1_PI_67_DATA 0x0001010F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x01000000 +#define DDRSS1_PI_72_DATA 0x00000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2826,33 +2826,33 @@ #define DDRSS1_PI_162_DATA 0x00000000 #define DDRSS1_PI_163_DATA 0x2B2B0200 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000068 -#define DDRSS1_PI_166_DATA 0x00020068 +#define DDRSS1_PI_165_DATA 0x00000064 +#define DDRSS1_PI_166_DATA 0x00020064 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x50120C04 -#define DDRSS1_PI_169_DATA 0x00155012 -#define DDRSS1_PI_170_DATA 0x00000063 +#define DDRSS1_PI_168_DATA 0x48120C04 +#define DDRSS1_PI_169_DATA 0x00154812 +#define DDRSS1_PI_170_DATA 0x000000CE #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00001035 +#define DDRSS1_PI_172_DATA 0x00002073 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04001035 +#define DDRSS1_PI_174_DATA 0x04002073 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001500 +#define DDRSS1_PI_176_DATA 0x00001501 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000000 +#define DDRSS1_PI_182_DATA 0x00000101 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x19040000 -#define DDRSS1_PI_186_DATA 0x0E0E0219 +#define DDRSS1_PI_185_DATA 0x15040000 +#define DDRSS1_PI_186_DATA 0x0E0E0215 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01000101 +#define DDRSS1_PI_191_DATA 0x01010101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2874,28 +2874,28 @@ #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 #define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005F0036 +#define DDRSS1_PI_213_DATA 0x005B0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005F -#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_216_DATA 0x3212005B +#define DDRSS1_PI_217_DATA 0x09000301 #define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x04000364 +#define DDRSS1_PI_219_DATA 0x040006C9 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6000838E +#define DDRSS1_PI_223_DATA 0x6001071C #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6000838E +#define DDRSS1_PI_227_DATA 0x6001071C #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x0000C616 -#define DDRSS1_PI_230_DATA 0x000007BC -#define DDRSS1_PI_231_DATA 0x0000206A -#define DDRSS1_PI_232_DATA 0x00014424 -#define DDRSS1_PI_233_DATA 0x0000206A -#define DDRSS1_PI_234_DATA 0x00014424 +#define DDRSS1_PI_229_DATA 0x00019C16 +#define DDRSS1_PI_230_DATA 0x00001018 +#define DDRSS1_PI_231_DATA 0x000040E6 +#define DDRSS1_PI_232_DATA 0x000288FC +#define DDRSS1_PI_233_DATA 0x000040E6 +#define DDRSS1_PI_234_DATA 0x000288FC #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2936,29 +2936,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00F30084 +#define DDRSS1_PI_275_DATA 0x00330084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x36F33FF4 +#define DDRSS1_PI_277_DATA 0x56333FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x36F33FF4 +#define DDRSS1_PI_279_DATA 0x56333FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00F30084 +#define DDRSS1_PI_281_DATA 0x00330084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x36F33FF4 +#define DDRSS1_PI_283_DATA 0x56333FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x36F33FF4 +#define DDRSS1_PI_285_DATA 0x56333FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00F30084 +#define DDRSS1_PI_287_DATA 0x00330084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x36F33FF4 +#define DDRSS1_PI_289_DATA 0x56333FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x36F33FF4 +#define DDRSS1_PI_291_DATA 0x56333FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00F30084 +#define DDRSS1_PI_293_DATA 0x00330084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x36F33FF4 +#define DDRSS1_PI_295_DATA 0x56333FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x36F33FF4 +#define DDRSS1_PI_297_DATA 0x56333FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +2974,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000200 +#define DDRSS1_PHY_12_DATA 0x00000100 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,8 +2993,8 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F08 -#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_32_DATA 0x10200000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 #define DDRSS1_PHY_35_DATA 0x00000000 @@ -3062,9 +3062,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB01AB +#define DDRSS1_PHY_100_DATA 0x07AB0340 #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0101 +#define DDRSS1_PHY_102_DATA 0x0E0D0001 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3098,7 +3098,7 @@ #define DDRSS1_PHY_133_DATA 0x00000000 #define DDRSS1_PHY_134_DATA 0x00080200 #define DDRSS1_PHY_135_DATA 0x00000000 -#define DDRSS1_PHY_136_DATA 0x20202020 +#define DDRSS1_PHY_136_DATA 0x20202000 #define DDRSS1_PHY_137_DATA 0x20202020 #define DDRSS1_PHY_138_DATA 0xF0F02020 #define DDRSS1_PHY_139_DATA 0x00000000 @@ -3230,7 +3230,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000200 +#define DDRSS1_PHY_268_DATA 0x00000100 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,8 +3249,8 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F08 -#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_288_DATA 0x10200000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 #define DDRSS1_PHY_291_DATA 0x00000000 @@ -3318,9 +3318,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB01AB +#define DDRSS1_PHY_356_DATA 0x07AB0340 #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0101 +#define DDRSS1_PHY_358_DATA 0x0E0D0001 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3354,7 +3354,7 @@ #define DDRSS1_PHY_389_DATA 0x00000000 #define DDRSS1_PHY_390_DATA 0x00080200 #define DDRSS1_PHY_391_DATA 0x00000000 -#define DDRSS1_PHY_392_DATA 0x20202020 +#define DDRSS1_PHY_392_DATA 0x20202000 #define DDRSS1_PHY_393_DATA 0x20202020 #define DDRSS1_PHY_394_DATA 0xF0F02020 #define DDRSS1_PHY_395_DATA 0x00000000 @@ -3486,7 +3486,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000200 +#define DDRSS1_PHY_524_DATA 0x00000100 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,8 +3505,8 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F08 -#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_544_DATA 0x10200000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 #define DDRSS1_PHY_547_DATA 0x00000000 @@ -3574,9 +3574,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB01AB +#define DDRSS1_PHY_612_DATA 0x07AB0340 #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0101 +#define DDRSS1_PHY_614_DATA 0x0E0D0001 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3610,7 +3610,7 @@ #define DDRSS1_PHY_645_DATA 0x00000000 #define DDRSS1_PHY_646_DATA 0x00080200 #define DDRSS1_PHY_647_DATA 0x00000000 -#define DDRSS1_PHY_648_DATA 0x20202020 +#define DDRSS1_PHY_648_DATA 0x20202000 #define DDRSS1_PHY_649_DATA 0x20202020 #define DDRSS1_PHY_650_DATA 0xF0F02020 #define DDRSS1_PHY_651_DATA 0x00000000 @@ -3742,7 +3742,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000200 +#define DDRSS1_PHY_780_DATA 0x00000100 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,8 +3761,8 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F08 -#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_800_DATA 0x10200000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 #define DDRSS1_PHY_803_DATA 0x00000000 @@ -3830,9 +3830,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB01AB +#define DDRSS1_PHY_868_DATA 0x07AB0340 #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0101 +#define DDRSS1_PHY_870_DATA 0x0E0D0001 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -3866,7 +3866,7 @@ #define DDRSS1_PHY_901_DATA 0x00000000 #define DDRSS1_PHY_902_DATA 0x00080200 #define DDRSS1_PHY_903_DATA 0x00000000 -#define DDRSS1_PHY_904_DATA 0x20202020 +#define DDRSS1_PHY_904_DATA 0x20202000 #define DDRSS1_PHY_905_DATA 0x20202020 #define DDRSS1_PHY_906_DATA 0xF0F02020 #define DDRSS1_PHY_907_DATA 0x00000000 @@ -4265,14 +4265,14 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x00000064 +#define DDRSS1_PHY_1303_DATA 0x0000FFFF #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 #define DDRSS1_PHY_1307_DATA 0x01200F02 #define DDRSS1_PHY_1308_DATA 0x00194280 #define DDRSS1_PHY_1309_DATA 0x00000004 -#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1310_DATA 0x00052000 #define DDRSS1_PHY_1311_DATA 0x00000000 #define DDRSS1_PHY_1312_DATA 0x00000000 #define DDRSS1_PHY_1313_DATA 0x00000000 @@ -4359,7 +4359,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x040207AB +#define DDRSS1_PHY_1397_DATA 0x010207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index 976ba1e95ab..084f8f5b669 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/phy/phy-cadence.h> +#include <dt-bindings/phy/phy-ti.h> + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +37,101 @@ }; }; + scm_conf: syscon@104000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00104000 0x00 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible = "mmio-mux"; + reg = <0x0 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + + phy_gmii_sel_cpsw: phy@34 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x34 0x4>; + #phy-cells = <1>; + }; + + serdes_ln_ctrl: mux-controller@80 { + compatible = "mmio-mux"; + reg = <0x80 0x10>; + #mux-control-cells = <1>; + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; + + ehrpwm_tbclk: clock-controller@140 { + compatible = "ti,am654-ehrpwm-tbclk"; + reg = <0x140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -33,8 +139,11 @@ ranges; #interrupt-cells = <3>; interrupt-controller; - reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -57,7 +166,7 @@ #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <148>; - ti,interrupt-ranges = <8 360 56>; + ti,interrupt-ranges = <8 392 56>; }; main_pmx0: pinctrl@11c000 { @@ -69,6 +178,283 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x00 0x04e00000 0x00 0x1200>; + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; + + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, + <&main_udmap 0x4a41>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x04e10000 0x00 0x7d>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>; + assigned-clock-parents = <&k3_clks 64 2>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>; + assigned-clock-parents = <&k3_clks 66 2>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>; + assigned-clock-parents = <&k3_clks 68 2>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>; + assigned-clock-parents = <&k3_clks 70 2>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>; + assigned-clock-parents = <&k3_clks 71 2>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>; + assigned-clock-parents = <&k3_clks 73 2>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>; + assigned-clock-parents = <&k3_clks 75 2>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>; + assigned-clock-parents = <&k3_clks 77 2>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>; + assigned-clock-parents = <&k3_clks 79 2>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 80 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 80 1>; + assigned-clock-parents = <&k3_clks 80 2>; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 81 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 81 1>; + assigned-clock-parents = <&k3_clks 81 2>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 82 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 82 1>; + assigned-clock-parents = <&k3_clks 82 2>; + power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; @@ -77,6 +463,7 @@ clocks = <&k3_clks 146 3>; clock-names = "fclk"; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -87,6 +474,7 @@ clocks = <&k3_clks 350 3>; clock-names = "fclk"; power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -97,6 +485,7 @@ clocks = <&k3_clks 351 3>; clock-names = "fclk"; power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -107,6 +496,7 @@ clocks = <&k3_clks 352 3>; clock-names = "fclk"; power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -117,6 +507,7 @@ clocks = <&k3_clks 353 3>; clock-names = "fclk"; power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -127,6 +518,7 @@ clocks = <&k3_clks 354 3>; clock-names = "fclk"; power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -137,6 +529,7 @@ clocks = <&k3_clks 355 3>; clock-names = "fclk"; power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart7: serial@2870000 { @@ -147,6 +540,7 @@ clocks = <&k3_clks 356 3>; clock-names = "fclk"; power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart8: serial@2880000 { @@ -157,6 +551,7 @@ clocks = <&k3_clks 357 3>; clock-names = "fclk"; power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart9: serial@2890000 { @@ -167,6 +562,7 @@ clocks = <&k3_clks 358 3>; clock-names = "fclk"; power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_gpio0: gpio@600000 { @@ -183,6 +579,7 @@ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -199,6 +596,7 @@ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 112 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -215,6 +613,7 @@ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -231,6 +630,7 @@ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; main_i2c0: i2c@2000000 { @@ -253,6 +653,7 @@ clocks = <&k3_clks 215 1>; clock-names = "fck"; power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -264,6 +665,7 @@ clocks = <&k3_clks 216 1>; clock-names = "fck"; power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -275,6 +677,7 @@ clocks = <&k3_clks 217 1>; clock-names = "fck"; power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c4: i2c@2040000 { @@ -286,6 +689,7 @@ clocks = <&k3_clks 218 1>; clock-names = "fck"; power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c5: i2c@2050000 { @@ -297,6 +701,7 @@ clocks = <&k3_clks 219 1>; clock-names = "fck"; power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c6: i2c@2060000 { @@ -308,6 +713,7 @@ clocks = <&k3_clks 220 1>; clock-names = "fck"; power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_sdhci0: mmc@4f80000 { @@ -317,7 +723,7 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; - clock-names = "clk_ahb", "clk_xin"; + clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 98 1>; assigned-clock-parents = <&k3_clks 98 2>; bus-width = <8>; @@ -335,6 +741,7 @@ mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status = "disabled"; }; main_sdhci1: mmc@4fb0000 { @@ -344,7 +751,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; - clock-names = "clk_ahb", "clk_xin"; + clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 99 1>; assigned-clock-parents = <&k3_clks 99 2>; bus-width = <4>; @@ -363,7 +770,8 @@ ti,trm-icp = <0x8>; dma-coherent; /* Masking support for SDR104 capability */ - // sdhci-caps-mask = <0x00000003 0x00000000>; + sdhci-caps-mask = <0x00000003 0x00000000>; + status = "disabled"; }; main_navss: bus@30000000 { @@ -425,6 +833,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -434,6 +843,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -443,6 +853,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -452,6 +863,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -461,6 +873,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -470,6 +883,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -479,6 +893,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -488,6 +903,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -497,6 +913,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -506,6 +923,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -515,6 +933,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -524,6 +943,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster0: mailbox@31f90000 { @@ -533,6 +953,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster1: mailbox@31f91000 { @@ -542,6 +963,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster2: mailbox@31f92000 { @@ -551,6 +973,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster3: mailbox@31f93000 { @@ -560,6 +983,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster4: mailbox@31f94000 { @@ -569,6 +993,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster5: mailbox@31f95000 { @@ -578,6 +1003,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster6: mailbox@31f96000 { @@ -587,6 +1013,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster7: mailbox@31f97000 { @@ -596,6 +1023,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster8: mailbox@31f98000 { @@ -605,6 +1033,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster9: mailbox@31f99000 { @@ -614,6 +1043,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster10: mailbox@31f9a000 { @@ -623,6 +1053,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster11: mailbox@31f9b000 { @@ -632,6 +1063,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; main_ringacc: ringacc@3c000000 { @@ -639,8 +1071,9 @@ reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; @@ -676,6 +1109,8 @@ reg-names = "cpts"; clocks = <&k3_clks 226 5>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ + assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&main_navss_intr 391>; interrupt-names = "cpts"; ti,cpts-periodic-outputs = <6>; @@ -683,6 +1118,180 @@ }; }; + main_cpsw: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + clocks = <&k3_clks 28 28>; + clock-names = "fck"; + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel_cpsw 1>; + status = "disabled"; + }; + }; + + main_cpsw_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 28 28>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 28 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x04104000 0x00 0x100>; + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 360 17>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + + status = "disabled"; /* Needs pinmux */ + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721s2-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 365 3>; + assigned-clock-parents = <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x800000>, + <0x00 0x18000000 0x00 0x1000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status = "disabled"; /* Needs gpio and serdes info */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, @@ -695,6 +1304,7 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan1: can@2711000 { @@ -709,6 +1319,7 @@ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan2: can@2721000 { @@ -723,6 +1334,7 @@ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan3: can@2731000 { @@ -737,6 +1349,7 @@ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan4: can@2741000 { @@ -751,6 +1364,7 @@ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan5: can@2751000 { @@ -765,6 +1379,7 @@ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan6: can@2761000 { @@ -779,6 +1394,7 @@ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan7: can@2771000 { @@ -793,6 +1409,7 @@ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan8: can@2781000 { @@ -807,6 +1424,7 @@ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan9: can@2791000 { @@ -821,6 +1439,7 @@ <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan10: can@27a1000 { @@ -835,6 +1454,7 @@ <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan11: can@27b1000 { @@ -849,6 +1469,7 @@ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan12: can@27c1000 { @@ -863,6 +1484,7 @@ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan13: can@27d1000 { @@ -877,6 +1499,7 @@ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan14: can@2681000 { @@ -891,6 +1514,7 @@ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan15: can@2691000 { @@ -905,6 +1529,7 @@ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan16: can@26a1000 { @@ -919,6 +1544,7 @@ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan17: can@26b1000 { @@ -933,5 +1559,140 @@ <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 339 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 340 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 341 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 342 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 343 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 344 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 345 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 346 1>; + status = "disabled"; + }; + + dss: dss@4a00000 { + compatible = "ti,j721e-dss"; + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + clocks = <&k3_clks 158 0>, + <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + status = "disabled"; + + dss_ports: ports { + }; }; }; diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi index 7521963719f..2ddad931855 100644 --- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi @@ -12,8 +12,8 @@ mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 11>, + <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44083000 0x00 0x1000>; @@ -39,6 +39,21 @@ reg = <0x00 0x43000014 0x00 0x4>; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; @@ -50,12 +65,61 @@ wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x034>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02C>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; reg = <0x00 0x42200000 0x00 0x400>; @@ -65,7 +129,7 @@ #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <125>; - ti,interrupt-ranges = <16 928 16>; + ti,interrupt-ranges = <16 960 16>; }; mcu_conf: syscon@40f00000 { @@ -83,6 +147,146 @@ }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 83 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 83 1>; + assigned-clock-parents = <&k3_clks 83 2>; + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 84 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 84 1>; + assigned-clock-parents = <&k3_clks 84 2>; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 85 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 85 1>; + assigned-clock-parents = <&k3_clks 85 2>; + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 86 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 86 1>; + assigned-clock-parents = <&k3_clks 86 2>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 87 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 87 1>; + assigned-clock-parents = <&k3_clks 87 2>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 88 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 88 1>; + assigned-clock-parents = <&k3_clks 88 2>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 89 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 89 1>; + assigned-clock-parents = <&k3_clks 89 2>; + power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 90 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 90 1>; + assigned-clock-parents = <&k3_clks 90 2>; + power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 91 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 91 1>; + assigned-clock-parents = <&k3_clks 91 2>; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; @@ -91,6 +295,7 @@ clocks = <&k3_clks 359 3>; clock-names = "fclk"; power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_uart0: serial@40a00000 { @@ -101,6 +306,7 @@ clocks = <&k3_clks 149 3>; clock-names = "fclk"; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_gpio0: gpio@42110000 { @@ -108,7 +314,7 @@ reg = <0x00 0x42110000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; + interrupt-parent = <&wkup_gpio_intr>; interrupts = <103>, <104>, <105>, <106>, <107>, <108>; interrupt-controller; #interrupt-cells = <2>; @@ -117,6 +323,7 @@ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 115 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -124,7 +331,7 @@ reg = <0x00 0x42100000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; + interrupt-parent = <&wkup_gpio_intr>; interrupts = <112>, <113>, <114>, <115>, <116>, <117>; interrupt-controller; #interrupt-cells = <2>; @@ -133,6 +340,7 @@ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 116 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -144,6 +352,7 @@ clocks = <&k3_clks 223 1>; clock-names = "fck"; power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c0: i2c@40b00000 { @@ -155,6 +364,7 @@ clocks = <&k3_clks 221 1>; clock-names = "fck"; power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c1: i2c@40b10000 { @@ -166,6 +376,7 @@ clocks = <&k3_clks 222 1>; clock-names = "fck"; power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_mcan0: can@40528000 { @@ -180,6 +391,7 @@ <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; mcu_mcan1: can@40568000 { @@ -194,9 +406,43 @@ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 347 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 348 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 349 0>; + status = "disabled"; }; - mcu_navss: bus@28380000{ + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; @@ -211,8 +457,9 @@ reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; @@ -240,6 +487,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x2a480000 0x00 0x80000>, + <0x00 0x2a380000 0x00 0x80000>, + <0x00 0x2a400000 0x00 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; @@ -293,10 +555,104 @@ reg = <0x0 0x3d000 0x0 0x400>; clocks = <&k3_clks 29 3>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ + assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; ti,cpts-ext-ts-inputs = <4>; ti,cpts-periodic-outputs = <2>; }; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40210000 0x00 0x1000>; + interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + fss: bus@47000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 109 5>; + assigned-clocks = <&k3_clks 109 5>; + assigned-clock-parents = <&k3_clks 109 7>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 110 5>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x0 0x350>, + <0x00 0x42050000 0x0 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index c74e8e58ae8..03bd680f442 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -1,20 +1,18 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; -#include "k3-j721s2-som-p0.dtsi" +#include "k3-j721s2-common-proc-board.dts" #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" -#include "k3-j721s2-binman.dtsi" +#include "k3-j721s2-common-proc-board-u-boot.dtsi" / { chosen { - firmware-loader = &fs_loader0; - stdout-path = &main_uart8; - tick-timer = &timer1; + tick-timer = &mcu_timer0; }; aliases { @@ -22,11 +20,6 @@ remoteproc1 = &a72_0; }; - fs_loader0: fs_loader@0 { - compatible = "u-boot,fs-loader"; - bootph-all; - }; - a72_0: a72@0 { compatible = "ti,am654-rproc"; reg = <0x0 0x00a90000 0x0 0x10>; @@ -44,149 +37,46 @@ bootph-pre-ram; }; - clk_200mhz: dummy_clock_200mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - bootph-pre-ram; - }; - - clk_19_2mhz: dummy_clock_19_2mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - bootph-pre-ram; - }; -}; - -&cbass_mcu_wakeup { - sa3_secproxy: secproxy@44880000 { - bootph-pre-ram; - compatible = "ti,am654-secure-proxy"; - reg = <0x0 0x44880000 0x0 0x20000>, - <0x0 0x44860000 0x0 0x20000>, - <0x0 0x43600000 0x0 0x10000>; - reg-names = "rt", "scfg", "target_data"; - #mbox-cells = <1>; - }; - - mcu_secproxy: secproxy@2a380000 { - compatible = "ti,am654-secure-proxy"; - reg = <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>, - <0x0 0x2a480000 0x0 0x80000>; - reg-names = "rt", "scfg", "target_data"; - #mbox-cells = <1>; - bootph-pre-ram; - }; - - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; - dm_tifs: dm-tifs { compatible = "ti,j721e-dm-sci"; ti,host-id = <3>; ti,secure-host; mbox-names = "rx", "tx"; - mboxes= <&mcu_secproxy 21>, - <&mcu_secproxy 23>; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; bootph-pre-ram; }; }; -&main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { - pinctrl-single,pins = < - J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ - J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ - J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ - J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ - >; - }; +&mcu_timer0 { + clock-frequency = <250000000>; + bootph-pre-ram; +}; - main_mmc1_pins_default: main-mmc1-pins-default { - pinctrl-single,pins = < - J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ - J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ - J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ - J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ - J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ - J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ - >; - }; +&secure_proxy_sa3 { + bootph-pre-ram; + status = "okay"; }; -&wkup_pmx0 { - mcu_uart0_pins_default: mcu-uart0-pins-default { - bootph-pre-ram; - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; +&secure_proxy_mcu { + bootph-pre-ram; + status = "okay"; +}; - wkup_uart0_pins_default: wkup-uart0-pins-default { +&cbass_mcu_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; + mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ - >; }; }; &sms { - mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx", "notify"; ti,host-id = <4>; ti,secure-host; - bootph-pre-ram; -}; - -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; -}; - -&main_sdhci0 { - /delete-property/ power-domains; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - clock-names = "clk_xin"; - clocks = <&clk_200mhz>; - ti,driver-strength-ohm = <50>; - non-removable; - bus-width = <8>; -}; - -&main_sdhci1 { - /delete-property/ power-domains; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - clock-names = "clk_xin"; - clocks = <&clk_200mhz>; - ti,driver-strength-ohm = <50>; }; &mcu_ringacc { @@ -196,5 +86,3 @@ &mcu_udmap { ti,sci = <&dm_tifs>; }; - -#include "k3-j721s2-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi index c0687fece01..a4006f32802 100644 --- a/arch/arm/dts/k3-j721s2-som-p0.dtsi +++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* + * SoM: https://www.ti.com/lit/zip/sprr439 + * * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ @@ -16,6 +18,7 @@ <0x08 0x80000000 0x03 0x80000000>; }; + /* Reserving memory regions still pending */ reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -26,7 +29,18 @@ alignment = <0x1000>; no-map; }; + }; + + mux0: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; }; transceiver0: can-phy0 { @@ -37,15 +51,43 @@ }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ >; }; - main_mcan16_pins_default: main-mcan16-pins-default { + main_mcan16_pins_default: main-mcan16-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ @@ -53,7 +95,21 @@ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -71,103 +127,27 @@ }; &main_mcan16 { + status = "okay"; pinctrl-0 = <&main_mcan16_pins_default>; pinctrl-names = "default"; phys = <&transceiver0>; }; -&mailbox0_cluster0 { - status = "disabled"; -}; - -&mailbox0_cluster1 { - status = "disabled"; -}; - -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - -&mailbox1_cluster0 { - status = "disabled"; -}; - -&mailbox1_cluster1 { - status = "disabled"; -}; - -&mailbox1_cluster2 { - status = "disabled"; -}; - -&mailbox1_cluster3 { - status = "disabled"; -}; - -&mailbox1_cluster4 { - status = "disabled"; -}; - -&mailbox1_cluster5 { - status = "disabled"; -}; - -&mailbox1_cluster6 { - status = "disabled"; -}; - -&mailbox1_cluster7 { - status = "disabled"; -}; - -&mailbox1_cluster8 { - status = "disabled"; -}; - -&mailbox1_cluster9 { - status = "disabled"; -}; - -&mailbox1_cluster10 { - status = "disabled"; -}; - -&mailbox1_cluster11 { - status = "disabled"; +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + }; }; diff --git a/arch/arm/dts/k3-j721s2-thermal.dtsi b/arch/arm/dts/k3-j721s2-thermal.dtsi new file mode 100644 index 00000000000..f7b1a15b8fa --- /dev/null +++ b/arch/arm/dts/k3-j721s2-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/thermal/thermal.h> + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm/dts/k3-j721s2.dtsi b/arch/arm/dts/k3-j721s2.dtsi index fe5234c40f6..1f636acd4ee 100644 --- a/arch/arm/dts/k3-j721s2.dtsi +++ b/arch/arm/dts/k3-j721s2.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721S2 SoC Family * - * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28 + * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 * * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * @@ -10,9 +10,10 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J721S2 SoC"; @@ -69,6 +70,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x100000>; cache-line-size = <64>; @@ -79,6 +81,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { @@ -119,6 +122,7 @@ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ @@ -160,6 +164,10 @@ }; }; + + thermal_zones: thermal-zones { + #include "k3-j721s2-thermal.dtsi" + }; }; /* Now include peripherals from each bus segment */ diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index bd685ddfdb4..60b1c0e1fc4 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index fbdcf5d77f5..751cc38ee5c 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 5683a2306bd..1abe44f4042 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi index 2fec92ce3ec..9347ea32c9c 100644 --- a/arch/arm/dts/versal-mini-qspi.dtsi +++ b/arch/arm/dts/versal-mini-qspi.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts index a213b745bc2..844e3840ace 100644 --- a/arch/arm/dts/versal-mini.dts +++ b/arch/arm/dts/versal-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index dc942b0f595..593ca4a49cf 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -55,7 +55,6 @@ &qspi { status = "okay"; - is-dual = <0>; num-cs = <1>; flash@0 { /* 16 MB */ compatible = "n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index d06838c5eeb..8d007378033 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -66,7 +66,6 @@ &qspi { bootph-all; status = "okay"; - is-dual = <0>; num-cs = <1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts index 3214ee49e28..96d2937de8b 100644 --- a/arch/arm/dts/zynq-minized.dts +++ b/arch/arm/dts/zynq-minized.dts @@ -39,7 +39,6 @@ &qspi { status = "okay"; - is-dual = <0>; num-cs = <1>; flash@0 { compatible = "micron,m25p128"; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index 57cb86aafd2..8307a2ef9dd 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -33,7 +33,6 @@ &qspi { bootph-all; status = "okay"; - is-dual = <0>; num-cs = <1>; flash@0 { compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; diff --git a/arch/arm/dts/zynq-topic-miamilite.dts b/arch/arm/dts/zynq-topic-miamilite.dts index 366fd5bbb10..af0bc7ecf70 100644 --- a/arch/arm/dts/zynq-topic-miamilite.dts +++ b/arch/arm/dts/zynq-topic-miamilite.dts @@ -12,5 +12,4 @@ }; &qspi { - is-dual = <1>; }; diff --git a/arch/arm/dts/zynq-topic-miamiplus.dts b/arch/arm/dts/zynq-topic-miamiplus.dts index df538865296..36a7db355e5 100644 --- a/arch/arm/dts/zynq-topic-miamiplus.dts +++ b/arch/arm/dts/zynq-topic-miamiplus.dts @@ -21,5 +21,4 @@ }; &qspi { - is-dual = <1>; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 02214349feb..d1e971254e5 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -49,6 +49,9 @@ &nfc0 { status = "okay"; + nand@0 { + reg = <0>; + }; }; &smcc { diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 1ae8ea2e43f..5f1b0b23c12 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -15,24 +16,6 @@ clocks = <&zynqmp_clk PL0_REF>; }; - fclk1: fclk1 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL1_REF>; - }; - - fclk2: fclk2 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL2_REF>; - }; - - fclk3: fclk3 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL3_REF>; - }; - pss_ref_clk: pss_ref_clk { bootph-all; compatible = "fixed-clock"; @@ -253,10 +236,12 @@ &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART0_REF>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART1_REF>; }; &usb0 { diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 016081ef7b9..f737004d794 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -88,9 +88,13 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revB.dts b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts new file mode 100644 index 00000000000..8310df9ed36 --- /dev/null +++ b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevB System Controller + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-e-a2197-00-revA.dts" + +/ { + model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ + compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", + "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + /delete-node/ ina226-vcco-500; + /delete-node/ ina226-vcco-501; + /delete-node/ ina226-vcco-502; +}; + +&i2c0 { + i2c-mux@74 { /* u33 */ + i2c@2 { /* PCIE_CLK */ + /delete-node/ clock-generator@6c; + }; + i2c@3 { /* PMBUS2_INA226 */ + /delete-node/ ina226@42; + /delete-node/ ina226@43; + /delete-node/ ina226@44; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index d5cfc61faf7..36a0db44fd2 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -81,10 +81,14 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; - phy0: ethernet-phy@0 { /* marwell m88e1512 */ - reg = <0>; - reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* marwell m88e1512 */ + reg = <0>; + reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ + }; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 97500b13287..25ef646c846 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -71,7 +71,6 @@ &qspi { status = "okay"; - is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; @@ -110,10 +109,14 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ + }; }; }; @@ -360,25 +363,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 3bdcf052a55..ece9e691454 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -67,7 +67,6 @@ &qspi { status = "okay"; - is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; @@ -106,9 +105,13 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; + }; }; }; @@ -362,25 +365,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 9a693a57a93..7372968e573 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -67,7 +67,6 @@ &qspi { status = "okay"; - is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; @@ -106,9 +105,13 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; + }; }; }; @@ -356,25 +359,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index 08ec2f7b4a9..02e80bd85e1 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 905de08fdb0..ce1cdb20753 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index e5688fd703e..e0517cf4601 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index fc0a2e801e4..ee8be536000 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso new file mode 100644 index 00000000000..197dc252353 --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-01 revA (SE1) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J242 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u116 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso new file mode 100644 index 00000000000..8eb6e40dd9d --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u16 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u17 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J242 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u12 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso new file mode 100644 index 00000000000..af7a3ce9c1a --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u1 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u3 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + x_prc_si5338: clock-generator@70 { /* U9 */ + compatible = "silabs,si5338"; + reg = <0x70>; /* FIXME */ + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J90/J91 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u2 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso new file mode 100644 index 00000000000..29a6c2a627b --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + + si570_gem_tsu: clock-generator@5d { /* u164 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; /* FIXME */ + clock-frequency = <300000000>; + clock-output-names = "si570_gem_tsu_clk"; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u153 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso new file mode 100644 index 00000000000..6ddf18cf643 --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + + si570_gem_tsu: clock-generator@5d { /* u164 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; /* FIXME */ + clock-frequency = <300000000>; + clock-output-names = "si570_gem_tsu_clk"; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u153 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 16691a85e15..c456c375ac8 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -91,9 +91,13 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; @@ -423,25 +427,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts new file mode 100644 index 00000000000..e0b554c9c54 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP Generic System Controller + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP Generic System Controller"; + compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + nvmem0 = &eeprom; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + spi1 = &spi0; + spi2 = &spi1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + fwuen { + label = "sw16"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + ds40-led { + label = "heartbeat"; + gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + ds44-led { + label = "status"; + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; + }; + + si5332_2: si5332_2 { /* u42 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + pwm-fan { + compatible = "pwm-fan"; + status = "okay"; + pwms = <&ttc0 2 40000 1>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ + "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */ + "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */ + "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */ + "", "", "", "", "I2C0_SCL", /* 30 - 34 */ + "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */ + "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */ + "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */ + "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ + "", "", "", "", "", /* 65 - 69 */ + "", "", "", "", "", /* 70 - 74 */ + "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + reset-assert-us = <100>; + reset-deassert-us = <280>; + }; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c1 { /* i2c1 MIO 24-25 */ + status = "okay"; + bootph-all; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u34 - m24128 16kB */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x54>; /* & 0x5c */ + bootph-all; + }; +}; + +/* USB 3.0 only */ +&psgtr { + status = "okay"; + /* nc, nc, usb3 */ + clocks = <&si5332_2>; + clock-names = "ref2"; +}; + +&qspi { /* MIO 0-5 */ + status = "okay"; + /* QSPI should also have PINCTRL setup */ + flash@0 { + compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; /* 40MHz */ + partition@0 { + label = "Image Selector"; + reg = <0x0 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@80000 { + label = "Image Selector Golden"; + reg = <0x80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@100000 { + label = "Persistent Register"; + reg = <0x100000 0x20000>; /* 128KB */ + }; + partition@120000 { + label = "Persistent Register Backup"; + reg = <0x120000 0x20000>; /* 128KB */ + }; + partition@140000 { + label = "Open_1"; + reg = <0x140000 0xC0000>; /* 768KB */ + }; + partition@200000 { + label = "Image A (FSBL, PMU, ATF, U-Boot)"; + reg = <0x200000 0xD00000>; /* 13MB */ + }; + partition@f00000 { + label = "ImgSel Image A Catch"; + reg = <0xF00000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@f80000 { + label = "Image B (FSBL, PMU, ATF, U-Boot)"; + reg = <0xF80000 0xD00000>; /* 13MB */ + }; + partition@1c80000 { + label = "ImgSel Image B Catch"; + reg = <0x1C80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@1d00000 { + label = "Open_2"; + reg = <0x1D00000 0x100000>; /* 1MB */ + }; + partition@1e00000 { + label = "Recovery Image"; + reg = <0x1E00000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2000000 { + label = "Recovery Image Backup"; + reg = <0x2000000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2200000 { + label = "U-Boot storage variables"; + reg = <0x2200000 0x20000>; /* 128KB */ + }; + partition@2220000 { + label = "U-Boot storage variables backup"; + reg = <0x2220000 0x20000>; /* 128KB */ + }; + partition@2240000 { + label = "SHA256"; + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ + read-only; + lock; + }; + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22A0000 { + label = "User"; + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + }; + }; +}; + +&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio-bank = <0>; +}; + +&ttc0 { + status = "okay"; + #pwm-cells = <3>; +}; + +&uart1 { /* uart0 MIO36-37 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_8_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_8_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_34_grp", "gpio0_35_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_34_grp", "gpio0_35_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts new file mode 100644 index 00000000000..530a4a5f080 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-revC.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP Generic System Controller + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-sc-revB.dts" + +/ { + model = "ZynqMP Generic System Controller"; + compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; +}; + +&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ + /delete-node/ mdio; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { /* ADI1300 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id0283.bc30"; + reg = <1>; + adi,rx-internal-delay-ps = <2400>; + adi,tx-internal-delay-ps = <2400>; + adi,fifo-depth-bits = <8>; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso new file mode 100644 index 00000000000..3320bbc11fc --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VEK280 revA + * + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", + "xlnx,zynqmp-vek280", "xlnx,zynqmp"; + + vc7_xin: vc7-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir35215_46: pmic@46 { /* IR35215 - u152 */ + compatible = "infineon,ir35215"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + irps5401_48: pmic@48 { /* IRPS5401 - u279 */ + compatible = "infineon,irps5401"; + reg = <0x48>; /* i2c addr 0x18 */ + }; + ir38064_49: regulator@49 { /* IR38064 - u295 */ + compatible = "infineon,ir38064"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38060_4e: regulator@4e { /* IR38060 - u282 */ + compatible = "infineon,ir38060"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* alerts coming to u233 and SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <500>; /* r440 */ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <500>; /* r1702 */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r382 */ + }; + vcc_ram: ina226@43 { /* u355 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r2417 */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; /* r1830 */ + }; + vcc_psfp: ina226@45 { /* u260 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r2386 */ + }; + vcco_hdio: ina226@46 { /* u356 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; /* r2392 */ + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* alerts coming to u233 and SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; /* r2384 */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r2000 */ + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1829 */ + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r2397 */ + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r2401 */ + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <500>; /* r1384 */ + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; /* r1994 */ + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; /* r2384 */ + }; + vcc1v1_lp4: ina226@49 { /* u306 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <500>; /* r2064 */ + }; + vadj_fmc: ina226@4a { /* u281 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; /* r2031 */ + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; /* r2004 */ + }; + lpdmgtyavtt: ina226@4c { /* u309 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <5000>; /* r1229 */ + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; /* r1679 */ + }; + }; + i2c@4 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + rc21008a_gtclk1: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* connector j374 */ + /* rc21008a at 0x9 u299 */ + vc7: clock-generator@9 { + compatible = "renesas,rc21008a"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + }; + fmcp1_iic: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* to j51c */ + }; + sfp: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* sfp+ connector J376 */ + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso new file mode 100644 index 00000000000..a3983f330d0 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VEK280 revB + * + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-sc-vek280-revA.dtso" + +&{/} { + compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", + "xlnx,zynqmp-vek280", "xlnx,zynqmp"; +}; diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso new file mode 100644 index 00000000000..2ce69374c15 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VHK158 revA + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA", + "xlnx,zynqmp-vhk158", "xlnx,zynqmp"; + + vc7_xin: vc7-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38064_41: regulator@41 { /* IR38064 - u294 */ + compatible = "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + irps5401_45: pmic5401@45 { /* IRPS5401 - u280 */ + compatible = "infineon,irps5401"; + reg = <0x45>; /* i2c addr 0x15 */ + }; + ir35221_46: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + irps5401_48: regulator@48 { /* IRPS5401 - u279 */ + compatible = "infineon,irps5401"; + reg = <0x48>; /* i2c addr 0x18 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u295 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + ir38060_4a: regulator@4a { /* IR38060 - u259 */ + compatible = "infineon,ir38164"; + reg = <0x4a>; /* i2c addr 0x1a */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38060_4e: regulator@4e { /* IR38060 - u282 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <500>; /* R440 */ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <500>; /* R1702 */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* R382 */ + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <500>; /* R121 */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; /* R1830 */ + }; + vcc_psfp: ina226@45 { /* u260 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* R1834 */ + }; + vcco_hbm: ina226@46 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <500>; /* R2056 */ + }; + vcc_hbm: ina226@47 { /* u307 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <500>; /* R2068 */ + }; + vccaux_hbm: ina226@48 { /* u308 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; /* R2019 */ + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; /* R2060 */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <500>; /* R2000 */ + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <500>; /* R1829 */ + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <500>; /* R1221 */ + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <500>; /* R2015 */ + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <500>; /* R1384 */ + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <500>; /* R1994 */ + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <500>; /* R1232 */ + }; + vcc1v2_rdimm: ina226@49 { /* u306 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <500>; /* R2064 */ + }; + vadj_fmc: ina226@4a { /* u281 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; /* R2031 */ + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <500>; /* R2004 */ + }; + lpdmgtyavtt: ina226@4c { /* u309 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <500>; /* R1229 */ + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <500>; /* R1679 */ + }; + }; + i2c@4 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + rc21008a_gtclk1: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + vc7_1: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-0"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* i2c@9 - U299 */ + }; + rc21008a_gtclk2: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + vc7_2: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-1"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* i2c@9 - U300 */ + }; + sync_8a34001: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* U219 - i2c address UNKNOWN */ + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + ddr4_dimm0: i2c@0 { /* wired but NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + qsfp1_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J350 connector */ + }; + qsfp2_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* J351 connector */ + }; + qsfp3_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* J352 connector */ + }; + qsfp4_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* J353 connector */ + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2 connectors */ + }; + ddr4_dimm1: i2c@7 { /* wired but NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso new file mode 100644 index 00000000000..5333767361f --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) + * + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "xlnx,zynqmp-sc-vn-p-b2197-revA", + "xlnx,zynqmp-sc-vn-p-b2197", "xlnx,zynqmp"; + + aliases { + nvmem1 = &x_prc_eeprom; + }; + + ina226-u1700 { + compatible = "iio-hwmon"; + io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; + }; + ina226-u1732 { + compatible = "iio-hwmon"; + io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>; + }; + ina226-u1733 { + compatible = "iio-hwmon"; + io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; + }; + ina226-u1736 { + compatible = "iio-hwmon"; + io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>; + }; + ina226-u1737 { + compatible = "iio-hwmon"; + io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; + }; + ina226-u1739 { + compatible = "iio-hwmon"; + io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; + }; + ina226-u1741 { + compatible = "iio-hwmon"; + io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; + }; + ina226-u1743 { + compatible = "iio-hwmon"; + io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; + }; + ina226-u1745 { + compatible = "iio-hwmon"; + io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>; + }; + ina226-u1747 { + compatible = "iio-hwmon"; + io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>; + }; + ina226-u1750 { + compatible = "iio-hwmon"; + io-channels = <>yp_avcc_ina 0>, <>yp_avcc_ina 1>, <>yp_avcc_ina 2>; + }; + ina226-u1752 { + compatible = "iio-hwmon"; + io-channels = <>yp_avtt_ina 0>, <>yp_avtt_ina 1>, <>yp_avtt_ina 2>; + }; + ina226-u1754 { + compatible = "iio-hwmon"; + io-channels = <>yp_avccaux_ina 0>, <>yp_avccaux_ina 1>, <>yp_avccaux_ina 2>; + }; + ina226-u1756 { + compatible = "iio-hwmon"; + io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; + }; + ina226-u1758 { + compatible = "iio-hwmon"; + io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; + }; + ina226-u1760 { + compatible = "iio-hwmon"; + io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; + }; + + /* sc_vpk180_axi_iic_0_0: i2c@80050000 - UNUSED NOW */ /* SI5332 */ + + /* Connect to J212G pin G29/G30 - sysmon connector */ + /* sc_vpk180_axi_iic_1_0: i2c@80060000 */ /* SYSMON */ + + /* FIXME Fan control via u1702 - max6643 and mux via J1703 - not SW controllable - via EMIO */ +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */ + /* DC/SE eeprom at 0x52 */ + x_prc_eeprom: eeprom@52 { /* u4 - DC card identification - possible WP */ + compatible = "atmel,24c02"; + reg = <0x52>; + bootph-all; + }; + + x_prc_tca9534: gpio@22 { /* u5 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "xprc_sw_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "xprc_sw_1"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "xprc_sw_1"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "xprc_sw_1"; + }; + }; + + /* FMC eeproms at 0x50/0x51 */ + /* via j3/j5 to 0x68 to u32/9FGV1006C + + /* i2c_main_1 - u147 - j157 - disable translation, add 8 */ + /* J1 - OE for u43@55 + 8 - 161,132813MHz - QSFP56G_0 */ + qsfp56g_0_clk: clock-controller@5d { + compatible = "renesas,proxo-xp"; + reg = <0x5d>; + #clock-cells = <0>; + clock-output-names = "qsfp56g_0_clk"; + }; + + /* J2 - OE for u41@57 + 8 - 322,265625MHz - QSFP56G_1 */ + qsfp56g_1_clk: clock-controller@5f { + compatible = "renesas,proxo-xp"; + reg = <0x5f>; + #clock-cells = <0>; + clock-output-names = "qsfp56g_1_clk"; + }; + + /* J81 - OE for u115@50 + 8 - 320MHz - LPDDR5_C0 */ + lpddr5_c0_clk: clock-controller@58 { + compatible = "renesas,proxo-xp"; + reg = <0x58>; + #clock-cells = <0>; + clock-output-names = "lpddr5_c0_clk"; + }; + + /* i2c_main_2 - u148 - j122 - disable translation, add 9 */ + /* J112 - OE for u63@50 + 9 - 320MHz - LPDDR5_C2 */ + lpddr5_c2_clk: clock-controller@59 { + compatible = "renesas,proxo-xp"; + reg = <0x59>; + #clock-cells = <0>; + clock-output-names = "lpddr5_c2_clk"; + }; + + /* i2c_main_3 - u149 - j154 - disable translation, add 6 */ + /* J78 - OE for u116@50 + 6 - 320MHz - DDR5_UDIMM */ + ddr5_udimm_clk: clock-controller@56 { + compatible = "renesas,proxo-xp"; + reg = <0x56>; + #clock-cells = <0>; + clock-output-names = "ddr5_udimm_clk"; + }; + + /* i2c_main_4 - u150 - j146 - disable translation, add 5 */ + /* J107 - OE for u39@50 + 5 - 33,3333MHz - PS_REFCLK */ + ps_refclk: clock-controller@55 { + compatible = "renesas,proxo-xp"; + reg = <0x55>; + #clock-cells = <0>; + clock-output-names = "ps_refclk"; + }; + + /* i2c_main_5 - u1782 - j1798 - disable translation, add 7 */ + /* J77 - OE for u1783@50 + 7 - 320MHz - DDR4 */ + ddr4_clk: clock-controller@57 { + compatible = "renesas,proxo-xp"; + reg = <0x57>; + #clock-cells = <0>; + clock-output-names = "ddr4_clk"; + }; + + /* LTC4316 - not wired XORH/XORL - FIXME */ + /* J3 gate - FIXME should be connected for SW handling */ + /* i2c_main_1 bus */ + i2c1_u32: clock-controller@68 { + compatible = "renesas,9fgv1006"; + reg = <0x68>; + }; + + /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */ + /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */ + /* this should be SW controlable too */ +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + /* Via j11/j12 can also go to u17/IML3112 - 1:2 multiplexer - also accessed from Versal NET */ + /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */ + /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */ + + /* ina226_pmbus - J55 - disable INA226_PMBUS */ + vcc_ram_ina: power-monitor@40 { /* u1700 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x40>; + shunt-resistor = <1000>; /* R1996 */ + }; + + vcc_lpd_ina: power-monitor@41 { /* u1732 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x41>; + shunt-resistor = <1000>; /* R2017 */ + }; + + vccaux_ina: power-monitor@42 { /* u1733 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x42>; + shunt-resistor = <1000>; /* R2037 */ + }; + + vccaux_lpd_ina: power-monitor@43 { /* u1736 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x43>; + shunt-resistor = <1000>; /* R2057 */ + }; + + vcco_500_ina: power-monitor@44 { /* u1737 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x44>; + shunt-resistor = <1000>; /* R2069 */ + }; + + vcco_501_ina: power-monitor@45 { /* u1739 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x45>; + shunt-resistor = <1000>; /* R2089 */ + }; + + vcco_502_ina: power-monitor@46 { /* u1741 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x46>; + shunt-resistor = <1000>; /* R2108 */ + }; + + vcco_503_ina: power-monitor@47 { /* u1743 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x47>; + shunt-resistor = <1000>; /* R2127 */ + }; + + vcco_700_ina: power-monitor@48 { /* u1745 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x48>; + shunt-resistor = <1000>; /* R2154 */ + }; + + vcco_706_ina: power-monitor@49 { /* u1747 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x49>; + shunt-resistor = <1000>; /* R2175 */ + }; + + gtyp_avcc_ina: power-monitor@4a { /* u1750 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4a>; + shunt-resistor = <1000>; /* R2195 */ + }; + + gtyp_avtt_ina: power-monitor@4b { /* u1752 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4b>; + shunt-resistor = <1000>; /* R2215 */ + }; + + gtyp_avccaux_ina: power-monitor@4c { /* u1754 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4c>; + shunt-resistor = <5000>; /* R2235 */ + }; + + gtm_avcc_ina: power-monitor@4d { /* u1756 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4d>; + shunt-resistor = <1000>; /* R2256 */ + }; + + gtm_avtt_ina: power-monitor@4e { /* u1758 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4e>; + shunt-resistor = <1000>; /* R2276 */ + }; + + gtm_avccaux_ina: power-monitor@4f { /* u1760 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4f>; + shunt-resistor = <5000>; /* R2296 */ + }; + + /* pmbus - J50 - disable main PMBUS - also going to j132 */ + vcc_ram: regulator@a { /* u1730 */ + compatible = "ti,tps544b25"; + reg = <0xa>; + }; + + vcc_lpd: regulator@b { /* u1731 */ + compatible = "ti,tps544b25"; + reg = <0xb>; + }; + + vccaux: regulator@1a { /* u1734 */ + compatible = "ti,tps544b25"; + reg = <0x1a>; + }; + + vcco_503: regulator@12 { /* u1744 */ + compatible = "ti,tps546b24a"; + reg = <0x12>; + }; + + vcco_700: regulator@16 { /* u1746 */ + compatible = "ti,tps544b25"; + reg = <0x16>; + }; + + vcco_706: regulator@17 { /* u1748 */ + compatible = "ti,tps544b25"; + reg = <0x17>; + }; + + gtm_avcc: regulator@23 { /* u1755 */ + compatible = "ti,tps544b25"; + reg = <0x23>; + }; + + gtm_avtt: regulator@24 { /* u1757 */ + compatible = "ti,tps544b25"; + reg = <0x24>; + }; + + gtm_avccaux: regulator@25 { /* u1759 */ + compatible = "ti,tps544b25"; + reg = <0x25>; + }; + + util_1v8: regulator@15 { /* u1765 */ + compatible = "ti,tps544b25"; + reg = <0x15>; + }; + + ucd90320: power-sequencer@73 { /* u1768 */ + compatible = "ti,ucd90320"; + reg = <0x73>; + }; + + /* EXT_PMBUS main - J10 - disable extended PMBUS */ + vccint: tps53681@60 { /* u1712 - J1770 reset jumper */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0x60>; + /* vccint, vcc_cpm5n */ + }; + + vcc_io_soc: tps53681@61 { /* u1721 - J1772 reset jumper */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0x61>; + /* vcc_io_soc, vcc_fpd */ + }; + + vccaux_lpd: regulator@d { /* u1735 */ + compatible = "ti,tps544b25"; + reg = <0xd>; + }; + + vcco_500: regulator@13 { /* u1738 */ + compatible = "ti,tps546b24a"; + reg = <0x13>; + }; + + vcco_501: regulator@10 { /* u1740 */ + compatible = "ti,tps546b24a"; + reg = <0x10>; + }; + + vcco_502: regulator@11 { /* u1742 */ + compatible = "ti,tps546b24a"; + reg = <0x11>; + }; + + gtyp_avcc: regulator@20 { /* u1749 */ + compatible = "ti,tps544b25"; + reg = <0x20>; + }; + + gtyp_avtt: regulator@21 { /* u1751 */ + compatible = "ti,tps544b25"; + reg = <0x21>; + }; + + gtyp_avccaux: regulator@22 { /* u1753 */ + compatible = "ti,tps544b25"; + reg = <0x22>; + }; + + lp5_vdd1_1v8: regulator@e { /* u1761 - FIXME no ina226 */ + compatible = "ti,tps544b25"; + reg = <0xe>; + }; + + lp5_vdd2_1v05: regulator@f { /* u1762 - FIXME no ina226 */ + compatible = "ti,tps544b25"; + reg = <0xf>; + }; + + lp5_vddq_0v5: regulator@14 { /* u1763 - FIXME no ina226 */ + compatible = "ti,tps546b24a"; + reg = <0x14>; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso new file mode 100644 index 00000000000..750bc39139c --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VPK120 revB + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + + +&{/} { + compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB", + "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38060_41: regulator@41 { /* IR38060 - u259 */ + compatible = "infineon,ir38060", "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + ir38164_43: regulator@43 { /* IR38164 - u13 */ + compatible = "infineon,ir38164"; + reg = <0x43>; /* i2c addr 0x13 */ + }; + ir35221_46: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u189 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38164_4e: regulator@4e { /* IR38164 - u185 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + ir38164_4f: regulator@4f { /* IR38164 - u187 */ + compatible = "infineon,ir38164"; + reg = <0x4f>; /* i2c addr 0x1f */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vcc1v1_lp4: ina226@49 { /* u186 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <2000>; + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <2000>; + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + lpdmgtyavtt: ina226@4c { /* u260 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <2000>; + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + }; + i2c@4 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + i2c@5 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + user_si570: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5f>; + temperature-stability = <50>; + factory-fout = <100000000>; + clock-frequency = <100000000>; + clock-output-names = "fmc_si570"; + silabs,skip-recall; + }; + + }; + /* 7 unused */ + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + ref_clk_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + silabs,skip-recall; + }; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + i2c@2 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + lpddr4_si570_clk3_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + lpddr4_clk3: clock-generator@60 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk3"; + silabs,skip-recall; + }; + }; + lpddr4_si570_clk2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + lpddr4_clk2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk2"; + silabs,skip-recall; + }; + }; + lpddr4_si570_clk1_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + lpddr4_clk1: clock-generator@60 { /* u248 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk1"; + silabs,skip-recall; + }; + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2 connectors */ + }; + idt8a34001_i2c: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* Via J310 connector */ + idt_8a34001: phc@5b { + compatible = "idt,8a34001"; /* u219B */ + reg = <0x5b>; /* FIXME not in schematics */ + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso new file mode 100644 index 00000000000..551341f31bd --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VPK180 revA + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + + +&{/} { + compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA", + "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38060_41: regulator@41 { /* IR38060 - u259 */ + compatible = "infineon,ir38060", "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + ir35221_45: pmic@45 { /* IR35221 - u291 */ + compatible = "infineon,ir35221"; + reg = <0x45>; /* i2c addr - 0x15 */ + }; + ir35221_46: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + irps5401_48: pmic@48 { /* IRPS5401 - u295 */ + compatible = "infineon,irps5401"; + reg = <0x48>; /* i2c addr 0x18 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u189 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38164_4e: regulator@4e { /* IR38164 - u185 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + ir38164_4f: regulator@4f { /* IR38164 - u187 */ + compatible = "infineon,ir38164"; + reg = <0x4f>; /* i2c addr 0x1f */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; /* r440 */ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r2174 */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1214 */ + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r2108 */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; /* r1830 */ + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r2086 */ + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; /* r2109 */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r1246 */ + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1829 */ + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r1221 */ + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r1219 */ + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; /* r1384 */ + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; /* r1825 */ + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; /* r1232 */ + }; + vcc1v1_lp4: ina226@49 { /* u186 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <2000>; /* r1367 */ + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <2000>; /* r1350 */ + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; /* r2097 */ + }; + lpdmgtyavtt: ina226@4c { /* u260 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <2000>; /* r1834 */ + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; /* r1679 */ + }; + }; + /* 4 - 7 unused */ + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c-mux-idle-disconnect; + /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + ref_clk_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + silabs,skip-recall; + }; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + osfp_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J362 connector */ + }; + lpddr4_si570_clk3_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + lpddr4_clk3: clock-generator@60 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk3"; + silabs,skip-recall; + }; + /* alternative option DNP - u305 at 0x50 */ + }; + lpddr4_si570_clk2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + lpddr4_clk2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk2"; + silabs,skip-recall; + }; + /* alternative option DNP - u303 at 0x50 */ + }; + lpddr4_si570_clk1_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + lpddr4_clk1: clock-generator@60 { /* u248 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk1"; + silabs,skip-recall; + }; + /* alternative option DNP - u301 at 0x50 */ + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2/J355/J354/J359/J358 connectors */ + }; + idt8a34001_i2c: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* Via J310 connector */ + idt_8a34001: phc@5b { /* u219B */ + compatible = "idt,8a34001"; + reg = <0x5b>; + }; + }; + }; + i2c-mux@75 { /* u322 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + sfpdd1_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* J350 sfp-dd at 0x50 */ + }; + sfpdd2_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* J352 sfp-dd at 0x50 */ + }; + sfpdd3_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J385 sfp-dd at 0x50 */ + }; + sfpdd4_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* J387 sfp-dd at 0x50 */ + }; + rc21008a_gtclk1_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + vc7_1: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-0"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* u298 - rc21008a at 0x9 */ + /* connector J370 */ + }; + rc21008a_gtclk2_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + vc7_2: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-1"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* u299 - rc21008a at 0x9 */ + /* connector J371 */ + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso new file mode 100644 index 00000000000..e70eb4dc947 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VPK180 revA + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + + +&{/} { + compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB", + "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + + vc7_xin: vc7-xin { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <50000000>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38060_41: regulator@41 { /* IR38060 - u259 */ + compatible = "infineon,ir38060", "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + ir35221_45: pmic@45 { /* IR35221 - u291 */ + compatible = "infineon,ir35221"; + reg = <0x45>; /* i2c addr - 0x15 */ + }; + ir35221_46: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + irps5401_48: pmic@48 { /* IRPS5401 - u295 */ + compatible = "infineon,irps5401"; + reg = <0x48>; /* i2c addr 0x18 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u189 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38164_4e: regulator@4e { /* IR38164 - u185 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + ir38164_4f: regulator@4f { /* IR38164 - u187 */ + compatible = "infineon,ir38164"; + reg = <0x4f>; /* i2c addr 0x1f */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; /* r440 */ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r2174 */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1214 */ + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r2108 */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; /* r1830 */ + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r2086 */ + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; /* r2109 */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r1246 */ + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1829 */ + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r1221 */ + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r1219 */ + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; /* r1384 */ + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; /* r1825 */ + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; /* r1232 */ + }; + vcc1v1_lp4: ina226@49 { /* u186 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <2000>; /* r1367 */ + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <2000>; /* r1350 */ + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; /* r2097 */ + }; + lpdmgtyavtt: ina226@4c { /* u260 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <2000>; /* r1834 */ + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; /* r1679 */ + }; + }; + /* 4 - 7 unused */ + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c-mux-idle-disconnect; + /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + osfp_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J362 connector */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* alternative option DNP - u305 at 0x50 */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* alternative option DNP - u303 at 0x50 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* alternative option DNP - u301 at 0x50 */ + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2/J355/J354/J359/J358 connectors */ + }; + idt8a34001_i2c: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* Via J310 connector */ + idt_8a34001: phc@5b { /* u219B */ + compatible = "idt,8a34001"; + reg = <0x5b>; + }; + }; + }; + i2c-mux@75 { /* u322 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + sfpdd1_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* J350 sfp-dd at 0x50 */ + }; + sfpdd2_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* J352 sfp-dd at 0x50 */ + }; + sfpdd3_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J385 sfp-dd at 0x50 */ + }; + sfpdd4_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* J387 sfp-dd at 0x50 */ + }; + rc21008a_gtclk1_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + vc7_1: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-0"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* u298 - rc21008a at 0x9 */ + /* connector J370 */ + }; + rc21008a_gtclk2_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + vc7_2: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-1"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* u299 - rc21008a at 0x9 */ + /* connector J371 */ + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso new file mode 100644 index 00000000000..5a5c1efd6b9 --- /dev/null +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KD240 revA Carrier Card + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kd240-rev1", + "xlnx,zynqmp-sk-kd240-revB", + "xlnx,zynqmp-sk-kd240-revA", + "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; + model = "ZynqMP KD240 revA/B/1"; + + ina260-u3 { + compatible = "iio-hwmon"; + io-channels = <&u3 0>, <&u3 1>, <&u3 2>; + }; + + clk_26: clock2 { /* u17 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u3: ina260@40 { /* u3 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u13 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "", + "SD_RESET_B", "USB0_HUB_RESET_B", + "", "PS_GEM0_RESET_B", + "", ""; + }; + + /* usb5744@2d */ +}; + +/* USB 3.0 */ +&psgtr { + status = "okay"; + /* usb */ + clocks = <&clk_26>; + clock-names = "ref2"; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub0: usb-hub { /* u36 */ + i2c-bus = <&i2c1>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + usb2244: usb-sd { /* u41 */ + compatible = "microchip,usb2244"; + reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&gem1 { /* mdio mio50/51 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + assigned-clock-rates = <250000000>; + + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@8 { /* Adin u31 */ + reg = <8>; + adi,rx-internal-delay-ps = <2000>; + adi,tx-internal-delay-ps = <2000>; + adi,fifo-depth-bits = <8>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* 2 more ethernet phys u32@2 and u34@3 */ + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_can0_default: can0-default { + mux { + function = "can0"; + groups = "can0_16_grp"; + }; + + conf { + groups = "can0_16_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO66"; + bias-pull-up; + }; + + conf-tx { + pins = "MIO67"; + bias-pull-up; + drive-strength = <4>; + }; + }; + + pinctrl_uart0_default: uart0-default { + conf { + groups = "uart0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO70"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO71"; + bias-disable; + }; + + mux { + groups = "uart0_17_grp"; + function = "uart0"; + }; + }; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO45", "MIO46", "MIO47", "MIO48"; + bias-disable; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO44", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + output-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + assigned-clock-rates = <100000000>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 55bef1df75d..22e7d68d02b 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -2,12 +2,13 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * SD level shifter: - * "A" – A01 board un-modified (NXP) - * "Y" – A01 board modified with legacy interposer (Nexperia) - * "Z" – A01 board modified with Diode interposer + * "A" - A01 board un-modified (NXP) + * "Y" - A01 board modified with legacy interposer (Nexperia) + * "Z" - A01 board modified with Diode interposer * * Michal Simek <michal.simek@amd.com> */ @@ -156,7 +157,7 @@ disable-wp; xlnx,mio-bank = <1>; assigned-clock-rates = <187498123>; - bus-width = <8>; + bus-width = <4>; }; &gem3 { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 1b1d9e772f5..eadc2563064 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -2,7 +2,8 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -144,7 +145,7 @@ clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; assigned-clock-rates = <187498123>; - bus-width = <8>; + bus-width = <4>; }; &gem3 { diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 80b9face748..1d62c48e062 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -145,8 +145,6 @@ status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; @@ -235,9 +233,9 @@ label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; - partition@22A0000 { + partition@22a0000 { label = "User"; - reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ }; }; }; diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 3750bb38b58..0d96c6f9f04 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -56,7 +56,6 @@ &qspi { status = "okay"; - is-dual = <1>; flash@0 { compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; m25p,fast-read; @@ -66,7 +65,6 @@ spi-max-frequency = <166000000>; #address-cells = <1>; #size-cells = <1>; - is-dual = <1>; partition@0 { label = "qspi-boot-bin"; reg = <0x00000 0x60000>; diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts new file mode 100644 index 00000000000..2f88aa4a0d2 --- /dev/null +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; + compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", + "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + usb1 = &usb1; + nvmem0 = &eeprom; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + j383 { + label = "j383"; + gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat-led { /* ds52 */ + label = "heartbeat"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + si5332_0: si5332_0 { /* ps_ref_clk - u142 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + si5332_1: si5332_1 { /* clk0_sgmii - u142 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; /* FIXME */ + }; + + si5332_2: si5332_2 { /* clk1_usb - u142 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&qspi { /* MIO 0-5 */ + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; /* maybe 4 here */ + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; + }; +}; + +&sdhci1 { /* sd MIO 45-51 */ + status = "okay"; + no-1-8-v; + disable-wp; + xlnx,mio-bank = <1>; +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + bootph-all; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + is-internal-pcspma; + /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ + /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { /* u131 - M88e1512 */ + reg = <0>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ + "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ + "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ + "", "", "", "", "", /* 15 - 19 */ + "", "", "", "", "", /* 20 - 24 */ + "", "", "", "", "", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ + "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ + "", "", "", "", "", /* 65 - 69 */ + "", "", "", "", "", /* 70 - 74 */ + "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ + "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ + "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + reg_vccint: tps53681@60 { /* u266 - 0xc0 */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0x60>; + }; + reg_vcc1v1_lp4: tps544@d { /* u85 */ + compatible = "ti,tps544b25"; + reg = <0xd>; + }; + reg_mgtyavcc: tps544@10 { /* u274 */ + compatible = "ti,tps544b25"; + reg = <0x10>; + }; + reg_mgtyavtt: tps544@11 { /* u275 */ + compatible = "ti,tps544b25"; + reg = <0x11>; + }; + reg_vccaux: tps544@12 { /* u276 */ + compatible = "ti,tps544b25"; + reg = <0x12>; + }; + reg_vcc_cpm: tps544@14 { /* u272 */ + compatible = "ti,tps544b25"; + reg = <0x14>; + }; + reg_util_3v3: tps544@1d { /* u278 */ + compatible = "ti,tps544b25"; + reg = <0x1d>; + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vcc_cpm: ina226@44 { /* u273 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pcie_smbus: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + pcie2_smbus: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + i2c@5 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + user_si570: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + /* 7 unused */ + }; +}; + +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + dc_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u34 - m24128 16kB */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x54>; /* & 0x5c */ + }; + si570_ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + silabs,skip-recall; + }; + }; + i2c@1 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c@2 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2c@3 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + lpddr4_si570_clk2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + lpddr4_clk2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk2"; + }; + }; + lpddr4_si570_clk1_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + lpddr4_clk1: clock-generator@60 { /* u248 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk1"; + }; + }; + /* 6-7 unused */ + }; +}; + +&usb0 { /* MIO52 - MIO63 */ + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; +}; + +&psgtr { + status = "okay"; + /* sgmii, usb3 */ + clocks = <&si5332_1>, <&si5332_2>; + clock-names = "ref0", "ref1"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + maximum-speed = "super-speed"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_8_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_8_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_34_grp", "gpio0_35_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_34_grp", "gpio0_35_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_9_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_9_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_36_grp", "gpio0_37_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_36_grp", "gpio0_37_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts new file mode 100644 index 00000000000..66919f578e0 --- /dev/null +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VPK120 RevA System Controller + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP System Controller on VPK120 board RevA"; + compatible = "xlnx,zynqmp-vpk120-revA", + "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + usb1 = &usb1; + nvmem0 = &eeprom; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + sw16 { + label = "sw16"; + gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat-led { /* ds40 */ + label = "heartbeat"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + si5332_0: si5332_0 { /* ps_ref_clk */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + si5332_1: si5332_1 { /* clk0_sgmii */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; /* FIXME */ + }; + + si5332_2: si5332_2 { /* clk1_usb */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&qspi { /* MIO 0-5 */ + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; + }; +}; + +&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio-bank = <0>; +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + bootph-all; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + is-internal-pcspma; + /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ + /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ + "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ + "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ + "", "", "", "", "", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ + "", "", "", "", "", /* 45 - 49 */ + "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ + "", "", "", "", "", /* 65 - 69 */ + "", "", "", "", "", /* 70 - 74 */ + "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ + "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ + "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ + "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38060_41: regulator@41 { /* IR38060 - u259 */ + compatible = "infineon,ir38060", "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + ir38164_43: regulator@43 { /* IR38164 - u13 */ + compatible = "infineon,ir38164"; + reg = <0x43>; /* i2c addr 0x13 */ + }; + ir35221_45: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* PMBUS - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u189 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1c */ + }; + ir38164_4e: regulator@4e { /* IR38164 - u184 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + ir38164_4f: regulator@4f { /* IR38164 - u187 */ + compatible = "infineon,ir38164"; + reg = <0x4f>; /* i2c addr 0x1f */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vcc1v1_lp4: ina226@49 { /* u186 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <2000>; + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <2000>; + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + lpdmgtyavtt: ina226@4c { /* u260 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <2000>; + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + }; + i2c@4 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + i2c@5 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + user_si570: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5f>; + temperature-stability = <50>; + factory-fout = <100000000>; + clock-frequency = <100000000>; + clock-output-names = "fmc_si570"; + }; + + }; + /* 7 unused */ + }; +}; + +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + ref_clk_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u34 - m24128 16kB */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x54>; /* & 0x5c */ + }; + ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + silabs,skip-recall; + }; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + i2c@2 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + lpddr4_si570_clk3_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + lpddr4_clk3: clock-generator@60 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk3"; + }; + }; + lpddr4_si570_clk2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + lpddr4_clk2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk2"; + }; + }; + lpddr4_si570_clk1_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + lpddr4_clk1: clock-generator@60 { /* u248 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk1"; + }; + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2 connectors */ + }; + idt8a34001_i2c: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* Via J310 connector */ + idt_8a34001: phc@5b { + compatible = "idt,8a34001"; /* u219B */ + reg = <0x5b>; /* FIXME not in schematics */ + }; + }; + }; +}; + +&usb0 { /* MIO52 - MIO63 */ + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; +}; + +&psgtr { + status = "okay"; + /* sgmii, usb3 */ + clocks = <&si5332_1>, <&si5332_2>; + clock-names = "ref0", "ref1"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + maximum-speed = "super-speed"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_8_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_8_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_34_grp", "gpio0_35_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_34_grp", "gpio0_35_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_9_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_9_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_36_grp", "gpio0_37_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_36_grp", "gpio0_37_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 5c4acd17cc5..cb9ef374680 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -2,10 +2,10 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index cffad447406..e72ed50b1cb 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -97,8 +98,12 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; @@ -349,11 +354,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index bb0477825a9..23a3ff2fed9 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -90,12 +91,16 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; - phy0: ethernet-phy@5 { - reg = <5>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@5 { + reg = <5>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 69ad58039e7..b97f7ee8d44 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -88,8 +88,12 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { /* VSC8211 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* VSC8211 */ + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 3017c9b29a2..2b66abc9f7e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -116,17 +116,21 @@ status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; - ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ - reg = <0>; - }; - ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ - reg = <7>; - }; - ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ - reg = <3>; - }; - ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ - reg = <8>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 74a5b020e86..b1857e17ab7 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ @@ -77,8 +77,12 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index a84cd86694e..44d1b24677d 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> * Nathalie Chan King Choy @@ -131,13 +132,13 @@ io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; - si5335_0: si5335_0 { /* clk0_usb - u23 */ + si5335_0: si5335-0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5335_1: si5335_1 { /* clk1_dp - u23 */ + si5335_1: si5335-1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index c0a4d913afe..c8f71a1aec8 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 0f7230b9526..e166c955506 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -970,12 +971,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index ce0a6e5f60a..3c28130909b 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 90fbfca87f2..cdfeea2fdd8 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 69470f8dede..4b942acd413 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -1,8 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index f8019c592a7..b90ff61d241 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -150,6 +151,18 @@ #clock-cells = <0>; clock-frequency = <114285000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -965,12 +978,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ @@ -1065,4 +1079,12 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index c9ff99f8a83..ba9e4891fcc 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -788,12 +789,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 9404c139a24..095c972f132 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -5,7 +5,7 @@ * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index c06d262506d..4060dc3613a 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -5,7 +5,7 @@ * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 99ea143c02e..4f85837e64f 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -5,7 +5,7 @@ * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 0c1f50943ac..22ad8d33a11 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -57,7 +57,7 @@ leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -643,12 +643,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; - reg = <0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 8ca01f01a3a..575ff5b1b77 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -57,7 +57,7 @@ leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -653,12 +653,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts new file mode 100644 index 00000000000..edbbf0b30e7 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP ZCU670 (67DR) + * + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU670 RevA"; + compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", + "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + nvmem0 = &eeprom; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>; + /* Another 4GB connected to PL */ + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + sw1 { + label = "sw1"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat-led { + label = "heartbeat"; /* DS1 */ + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + ina226-vccint { + compatible = "iio-hwmon"; + io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; + }; + ina226-vccint-io-bram-ps { + compatible = "iio-hwmon"; + io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; + }; + ina226-vcc1v8 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; + }; + ina226-vcc1v2 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; + }; + ina226-vadj-fmc { + compatible = "iio-hwmon"; + io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; + }; + ina226-mgtavcc { + compatible = "iio-hwmon"; + io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; + }; + ina226-mgt1v2 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; + }; + ina226-mgt1v8 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; + }; + ina226-vccint-ams { + compatible = "iio-hwmon"; + io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; + }; + ina226-dac-avtt { + compatible = "iio-hwmon"; + io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; + }; + ina226-dac-avccaux { + compatible = "iio-hwmon"; + io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; + }; + ina226-adc-avcc { + compatible = "iio-hwmon"; + io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; + }; + ina226-adc-avccaux { + compatible = "iio-hwmon"; + io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; + }; + ina226-dac-avcc { + compatible = "iio-hwmon"; + io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; + }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5381_6: si5381_6 { /* refclk_usb3 - u43 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ + "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ + "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ + "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ + "", "", "BUTTON", "LED", "", /* 20 - 24 */ + "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ + "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ + "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ + "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ + "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ + "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ + "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ + "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ + "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ + "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ + "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + tca6416_u15: gpio@20 { /* u15 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ + "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ + "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@75 { /* u17 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccint_io_bram_ps: ina226@41 { /* u57 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-io-bram-ps"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc1v8: ina226@42 { /* u60 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v8"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + vcc1v2: ina226@43 { /* u58 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vadj_fmc: ina226@45 { /* u62 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vadj-fmc"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@46 { /* u67 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtavcc"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + mgt1v2: ina226@47 { /* u63 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v2"; + reg = <0x47>; + shunt-resistor = <5000>; /* Not in schematics */ + }; + mgt1v8: ina226@48 { /* u64 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v8"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vccint_ams: ina226@49 { /* u61 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-ams"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + dac_avtt: ina226@4a { /* u59 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avtt"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + dac_avccaux: ina226@4b { /* u124 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avccaux"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + adc_avcc: ina226@4c { /* u75 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avcc"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + adc_avccaux: ina226@4d { /* u71 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avccaux"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + dac_avcc: ina226@4e { /* u77 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avcc"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* u104 - ir35215 0x10/0x40 */ + /* u127 - ir38164 0x1b/0x4b */ + /* u112 - ir38164 0x13/0x43 */ + /* u123 - ir38164 0x1c/0x4c */ + + irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ + compatible = "infineon,irps5401"; + reg = <0x44>; /* i2c addr 0x14 */ + }; + irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ + compatible = "infineon,irps5401"; + reg = <0x45>; /* i2c addr 0x15 */ + }; + /* J21 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; + /* u38 MPS430 */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; /* u20 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c_eeprom: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u21 */ + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + i2c_si5381: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* SI5381 - u43 */ + /* si5381: clock-generator@68 { + reg = <0x68>; + };*/ + }; + i2c_si570_user_c0: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + clock-output-names = "si570_user_c0"; + }; + }; + i2c_si570_mgt: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "si570_mgt"; + }; + }; + i2c_8a34001: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* U409B - 8a34001 */ + }; + i2c_clk104: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* CLK104_SDA */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* RFMCP connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u22 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c_si570_psrefclk: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "si570_ps_ref_clk"; + silabs,skip-recall; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; + /* u38 MPS430 */ +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; +}; + +&qspi { + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&rtc { + status = "okay"; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + disable-wp; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; + xlnx,mio-bank = <1>; +}; + +&psgtr { + status = "okay"; + /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ + clocks = <&si5381_6>; + clock-names = "ref2"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; +}; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts new file mode 100644 index 00000000000..97599c5658f --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -0,0 +1,672 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP ZCU670 (67DR) revB + * + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU670 RevB"; + compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", + "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + nvmem0 = &eeprom; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>; + /* Another 4GB connected to PL */ + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + sw1 { + label = "sw1"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat-led { + label = "heartbeat"; /* DS1 */ + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + ina226-vccint { + compatible = "iio-hwmon"; + io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; + }; + ina226-vccint-io-bram-ps { + compatible = "iio-hwmon"; + io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; + }; + ina226-vcc1v8 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; + }; + ina226-vcc1v2 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; + }; + ina226-vadj-fmc { + compatible = "iio-hwmon"; + io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; + }; + ina226-mgtavcc { + compatible = "iio-hwmon"; + io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; + }; + ina226-mgt1v2 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; + }; + ina226-mgt1v8 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; + }; + ina226-vccint-ams { + compatible = "iio-hwmon"; + io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; + }; + ina226-dac-avtt { + compatible = "iio-hwmon"; + io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; + }; + ina226-dac-avccaux { + compatible = "iio-hwmon"; + io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; + }; + ina226-adc-avcc { + compatible = "iio-hwmon"; + io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; + }; + ina226-adc-avccaux { + compatible = "iio-hwmon"; + io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; + }; + ina226-dac-avcc { + compatible = "iio-hwmon"; + io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; + }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5381_6: si5381_6 { /* refclk_usb3 - u43 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ + "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ + "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ + "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ + "", "", "BUTTON", "LED", "", /* 20 - 24 */ + "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ + "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ + "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ + "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ + "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ + "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ + "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ + "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ + "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ + "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ + "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + tca6416_u15: gpio@20 { /* u15 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ + "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ + "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@75 { /* u17 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccint_io_bram_ps: ina226@41 { /* u57 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-io-bram-ps"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc1v8: ina226@42 { /* u60 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v8"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + vcc1v2: ina226@43 { /* u58 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vadj_fmc: ina226@45 { /* u62 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vadj-fmc"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@46 { /* u67 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtavcc"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + mgt1v2: ina226@47 { /* u63 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v2"; + reg = <0x47>; + shunt-resistor = <5000>; /* Not in schematics */ + }; + mgt1v8: ina226@48 { /* u64 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v8"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vccint_ams: ina226@49 { /* u61 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-ams"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + dac_avtt: ina226@4a { /* u59 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avtt"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + dac_avccaux: ina226@4b { /* u124 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avccaux"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + adc_avcc: ina226@4c { /* u75 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avcc"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + adc_avccaux: ina226@4d { /* u71 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avccaux"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + dac_avcc: ina226@4e { /* u77 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avcc"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* u104 - ir35215 0x10/0x40 */ + /* u127 - ir38164 0x1b/0x4b */ + /* u112 - ir38164 0x13/0x43 */ + /* u123 - ir38164 0x1c/0x4c */ + + irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ + compatible = "infineon,irps5401"; + reg = <0x44>; /* i2c addr 0x14 */ + }; + irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ + compatible = "infineon,irps5401"; + reg = <0x45>; /* i2c addr 0x15 */ + }; + /* J21 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; + /* u38 MPS430 */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; /* u20 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c_eeprom: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u21 */ + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + i2c_si5381: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* SI5381 - u43 */ + /* si5381: clock-generator@68 { + reg = <0x68>; + };*/ + }; + i2c_si570_user_c0: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + clock-output-names = "si570_user_c0"; + }; + }; + i2c_si570_mgt: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "si570_mgt"; + }; + }; + i2c_8a34001: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* U409B - 8a34001 */ + }; + i2c_clk104: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* CLK104_SDA */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* RFMCP connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u22 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c_si570_psrefclk: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "si570_ps_ref_clk"; + silabs,skip-recall; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; + /* u38 MPS430 */ +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; +}; + +&qspi { + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&rtc { + status = "okay"; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + disable-wp; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; + xlnx,mio-bank = <1>; + clk-phase-sd-hs = <120>, <60>; + clk-phase-uhs-sdr25 = <132>, <60>; + clk-phase-uhs-ddr50 = <153>, <48>; +}; + +&psgtr { + status = "okay"; + /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ + clocks = <&si5381_6>; + clock-names = "ref2"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 79c5af24110..f03c201caee 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -14,6 +14,8 @@ #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> @@ -118,11 +120,27 @@ }; }; - zynqmp_ipi: zynqmp_ipi { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rproc_0_fw_image: memory@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + + rproc_1_fw_image: memory@3ef00000 { + no-map; + reg = <0x0 0x3ef00000 0x0 0x40000>; + }; + }; + + zynqmp_ipi: zynqmp-ipi { bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; @@ -152,10 +170,10 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; - interrupts = <0 143 4>, - <0 144 4>, - <0 145 4>, - <0 146 4>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, @@ -183,17 +201,17 @@ bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; - nvmem_firmware { + nvmem-firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; - soc_revision: soc_revision@0 { + soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; }; @@ -227,10 +245,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; edac { @@ -246,6 +264,23 @@ power-domains = <&zynqmp_firmware PD_PL>; }; + remoteproc { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_0>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_1>; + memory-region = <&rproc_1_fw_image>; + }; + }; + amba: axi { compatible = "simple-bus"; bootph-all; @@ -258,7 +293,7 @@ status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <0 23 4>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -271,7 +306,7 @@ status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <0 24 4>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -291,11 +326,11 @@ compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; - interrupts = <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -305,7 +340,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 124 4>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -318,7 +353,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 125 4>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -331,7 +366,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 126 4>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -344,7 +379,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 127 4>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -357,7 +392,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 128 4>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -370,7 +405,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 129 4>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -383,7 +418,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 130 4>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -396,7 +431,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 131 4>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -413,7 +448,7 @@ <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpu: gpu@fd4b0000 { @@ -421,7 +456,12 @@ compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; - interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; @@ -436,7 +476,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 77 4>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -449,7 +489,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -462,7 +502,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 79 4>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -475,7 +515,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -488,7 +528,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -501,7 +541,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 82 4>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -514,7 +554,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 83 4>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -527,7 +567,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 84 4>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -539,7 +579,7 @@ compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; - interrupts = <0 112 4>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; }; nand0: nand-controller@ff100000 { @@ -548,7 +588,7 @@ reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; - interrupts = <0 14 4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; @@ -559,11 +599,10 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 57 4>, <0 57 4>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; @@ -574,11 +613,10 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 59 4>, <0 59 4>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; @@ -589,11 +627,10 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 61 4>, <0 61 4>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; @@ -604,11 +641,10 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 63 4>, <0 63 4>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; @@ -621,7 +657,7 @@ #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; - interrupts = <0 16 4>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; @@ -632,7 +668,7 @@ compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 17 4>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; @@ -644,7 +680,7 @@ compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 18 4>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; @@ -668,11 +704,11 @@ msi-controller; device_type = "pci"; interrupt-parent = <&gic>; - interrupts = <0 118 4>, - <0 117 4>, - <0 116 4>, - <0 115 4>, /* MSI_1 [63...32] */ - <0 114 4>; /* MSI_0 [31...0] */ + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; @@ -702,7 +738,7 @@ compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; - interrupts = <0 15 4>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, @@ -727,7 +763,8 @@ status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; @@ -737,7 +774,7 @@ status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; - interrupts = <0 133 4>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, @@ -750,7 +787,7 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 48 4>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; @@ -765,7 +802,7 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 49 4>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; @@ -782,18 +819,30 @@ status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; - interrupts = <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 19 4>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -805,7 +854,7 @@ compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 20 4>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -817,7 +866,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 36 4>, <0 37 4>, <0 38 4>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; @@ -827,7 +878,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 39 4>, <0 40 4>, <0 41 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; @@ -837,7 +890,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 42 4>, <0 43 4>, <0 44 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; @@ -847,7 +902,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 45 4>, <0 46 4>, <0 47 4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; @@ -858,7 +915,7 @@ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 21 4>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; @@ -869,7 +926,7 @@ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 22 4>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; @@ -896,7 +953,9 @@ reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; - interrupts = <0 65 4>, <0 69 4>, <0 75 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; @@ -927,7 +986,9 @@ reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; - interrupts = <0 70 4>, <0 74 4>, <0 76 4>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; @@ -942,7 +1003,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 113 1>; + interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; @@ -952,7 +1013,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 52 1>; + interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; @@ -961,7 +1022,7 @@ compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 56 4>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xffa50000 0x0 0x800>; #address-cells = <1>; #size-cells = <1>; @@ -987,7 +1048,7 @@ compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; - interrupts = <0 122 4>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; @@ -1003,7 +1064,7 @@ <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; - interrupts = <0 119 4>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; @@ -1014,6 +1075,30 @@ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + port@3 { + reg = <3>; + }; + port@4 { + reg = <4>; + }; + port@5 { + reg = <5>; + }; + }; }; }; }; diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c index 4ddc34210eb..8ce6796fd04 100644 --- a/arch/arm/mach-k3/j7200/dev-data.c +++ b/arch/arm/mach-k3/j7200/dev-data.c @@ -46,6 +46,7 @@ static struct ti_lpsc soc_lpsc_list[] = { static struct ti_dev soc_dev_list[] = { PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(61, &soc_lpsc_list[1]), PSC_DEV(90, &soc_lpsc_list[2]), PSC_DEV(8, &soc_lpsc_list[3]), diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c index 8c999a3c5a8..df70c5e5d7c 100644 --- a/arch/arm/mach-k3/j721s2/dev-data.c +++ b/arch/arm/mach-k3/j721s2/dev-data.c @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(108, &soc_lpsc_list[0]), PSC_DEV(109, &soc_lpsc_list[0]), PSC_DEV(110, &soc_lpsc_list[0]), diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 712a7e253fa..a5be84b147c 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -219,7 +219,7 @@ void k3_mem_init(void) struct udevice *dev; int ret; - if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) { + if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) { ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev); if (ret) panic("Probe of msmc failed: %d\n", ret); diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h index 9bddb8b0072..767cdd36868 100644 --- a/arch/arm/mach-versal-net/include/mach/hardware.h +++ b/arch/arm/mach-versal-net/include/mach/hardware.h @@ -66,6 +66,7 @@ struct crp_regs { #define EMMC_MODE 0x00000006 #define USB_MODE 0x00000007 #define OSPI_MODE 0x00000008 +#define SELECTMAP_MODE 0x0000000A #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 000af974e86..9d1c2f0dcfc 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -82,6 +82,7 @@ struct crp_regs { #define EMMC_MODE 0x00000006 #define USB_MODE 0x00000007 #define OSPI_MODE 0x00000008 +#define SELECTMAP_MODE 0x0000000A #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 7bd39289fac..2487b482ddb 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ #include <common.h> diff --git a/arch/sandbox/dts/cedit.dtsi b/arch/sandbox/dts/cedit.dtsi index a9eb4c2d594..9bd84e62936 100644 --- a/arch/sandbox/dts/cedit.dtsi +++ b/arch/sandbox/dts/cedit.dtsi @@ -51,6 +51,14 @@ item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>; }; + + machine-name { + id = <ID_MACHINE_NAME>; + type = "textline"; + max-chars = <20>; + title = "Machine name"; + edit-id = <ID_MACHINE_NAME_EDIT>; + }; }; }; diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env index 22a6c2c91b1..e53a55c38fb 100644 --- a/board/ti/am62x/am62x.env +++ b/board/ti/am62x/am62x.env @@ -8,7 +8,7 @@ args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 ${mtdparts} run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} -boot_targets=ti_mmc mmc0 mmc1 usb pxe dhcp +boot_targets=mmc1 mmc0 usb pxe dhcp boot=mmc mmcdev=1 bootpart=1:2 diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index 68e42222b7f..efd736b99be 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -15,6 +15,7 @@ console=ttyS2,115200n8 args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts} run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} +boot_targets=mmc1 mmc0 usb pxe dhcp boot=mmc mmcdev=1 bootpart=1:2 diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS index 323bd2353a7..08c8d110ac0 100644 --- a/board/ti/j721s2/MAINTAINERS +++ b/board/ti/j721s2/MAINTAINERS @@ -1,16 +1,23 @@ J721S2 BOARD -M: Aswath Govindraju <a-govindraju@ti.com> +M: Manorit Chawdhry <m-chawdhry@ti.com> S: Maintained F: board/ti/j721s2 +F: arch/arm/mach-k3/j721s2 +F: doc/board/ti/j721s2_evm.rst F: include/configs/j721s2_evm.h F: configs/j721s2_evm_r5_defconfig F: configs/j721s2_evm_a72_defconfig F: arch/arm/dts/k3-j721s2.dtsi F: arch/arm/dts/k3-j721s2-main.dtsi F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi +F: arch/arm/dts/k3-j721s2-thermal.dtsi F: arch/arm/dts/k3-j721s2-som-p0.dtsi F: arch/arm/dts/k3-j721s2-common-proc-board.dts F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi -F: arch/arm/dts//k3-j721s2-r5-common-proc-board.dts +F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts F: arch/arm/dts/k3-j721s2-ddr.dtsi F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi +F: arch/arm/dts/k3-am68-sk-som.dtsi +F: arch/arm/dts/k3-am68-sk-base-board.dts +F: arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +F: arch/arm/dts/k3-am68-sk-r5-base-board.dts diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index c18be0c26c9..990ca1650aa 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -252,6 +252,9 @@ static int boot_targets_setup(void) mode = "mmc"; bootseq = dev_seq(dev); break; + case SELECTMAP_MODE: + puts("SELECTMAP_MODE\n"); + break; case SD_MODE: puts("SD_MODE\n"); if (uclass_get_device_by_name(UCLASS_MMC, diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index e4bdd5d7a38..8c2e614ad8a 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -174,6 +174,9 @@ static int boot_targets_setup(void) mode = "mmc"; bootseq = dev_seq(dev); break; + case SELECTMAP_MODE: + puts("SELECTMAP_MODE\n"); + break; case SD_MODE: puts("SD_MODE\n"); if (uclass_get_device_by_name(UCLASS_MMC, @@ -312,6 +315,7 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_SPI_FLASH; return ENVL_NOWHERE; case JTAG_MODE: + case SELECTMAP_MODE: default: return ENVL_NOWHERE; } diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c index 45102302dc2..166e61431ba 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c @@ -602,129 +602,6 @@ static unsigned long psu_peripherals_init_data(void) return 1; } -static unsigned long psu_serdes_init_data(void) -{ - psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); - psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); - psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); - psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U); - psu_mask_write(0xFD402868, 0x00000082U, 0x00000002U); - psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); - psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); - psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); - psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); - psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); - psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); - psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); - psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); - psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); - psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); - psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); - psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); - - serdes_illcalib(0, 0, 3, 0, 4, 0, 4, 0); - psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); - psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); - psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); - psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); - psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); - psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); - - return 1; -} - -static unsigned long psu_resetout_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); - psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); - psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); - psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); - psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); - psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); - psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD4063E4, 0x00000010U); - mask_poll(0xFD40A3E4, 0x00000010U); - - return 1; -} - -static unsigned long psu_resetin_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); - psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); - psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); - - return 1; -} - static unsigned long psu_afi_config(void) { psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); diff --git a/boot/Makefile b/boot/Makefile index 6ce983b83fa..ad608598d29 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -56,7 +56,8 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o endif -obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo.o scene.o scene_menu.o expo_build.o +obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo.o scene.o expo_build.o +obj-$(CONFIG_$(SPL_TPL_)EXPO) += scene_menu.o scene_textline.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE) += vbe.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_VBE_REQUEST) += vbe_request.o diff --git a/boot/cedit.c b/boot/cedit.c index 73645f70b6c..8c654dba6dc 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -71,10 +71,22 @@ int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id) y = 100; list_for_each_entry(obj, &scn->obj_head, sibling) { - if (obj->type == SCENEOBJT_MENU) { + switch (obj->type) { + case SCENEOBJT_NONE: + case SCENEOBJT_IMAGE: + case SCENEOBJT_TEXT: + break; + case SCENEOBJT_MENU: scene_obj_set_pos(scn, obj->id, 50, y); scene_menu_arrange(scn, (struct scene_obj_menu *)obj); y += 50; + break; + case SCENEOBJT_TEXTLINE: + scene_obj_set_pos(scn, obj->id, 50, y); + scene_textline_arrange(scn, + (struct scene_obj_textline *)obj); + y += 50; + break; } } @@ -170,7 +182,7 @@ int cedit_run(struct expo *exp) key = 0; if (ichar) { key = bootmenu_conv_key(ichar); - if (key == BKEY_NONE) + if (key == BKEY_NONE || key >= BKEY_FIRST_EXTRA) key = ichar; } if (!key) @@ -229,6 +241,16 @@ static int check_space(int ret, struct abuf *buf) return 0; } +/** + * get_cur_menuitem_text() - Get the text of the currently selected item + * + * Looks up the object for the current item, finds text object for it and looks + * up the string for that text + * + * @menu: Menu to look at + * @strp: Returns a pointer to the next + * Return: 0 if OK, -ENOENT if something was not found + */ static int get_cur_menuitem_text(const struct scene_obj_menu *menu, const char **strp) { @@ -253,22 +275,55 @@ static int get_cur_menuitem_text(const struct scene_obj_menu *menu, return 0; } +static int write_dt_string(struct abuf *buf, const char *name, const char *str) +{ + int ret, i; + + /* write the text of the current item */ + ret = -EAGAIN; + for (i = 0; ret && i < 2; i++) { + ret = fdt_property_string(abuf_data(buf), name, str); + if (!i) { + ret = check_space(ret, buf); + if (ret) + return log_msg_ret("rs2", -ENOMEM); + } + } + + /* this should not happen */ + if (ret) + return log_msg_ret("str", -EFAULT); + + return 0; +} + static int h_write_settings(struct scene_obj *obj, void *vpriv) { struct cedit_iter_priv *priv = vpriv; struct abuf *buf = priv->buf; + int ret; switch (obj->type) { case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: break; + case SCENEOBJT_TEXTLINE: { + const struct scene_obj_textline *tline; + + tline = (struct scene_obj_textline *)obj; + ret = write_dt_string(buf, obj->name, abuf_data(&tline->buf)); + if (ret) + return log_msg_ret("wr2", ret); + break; + } case SCENEOBJT_MENU: { const struct scene_obj_menu *menu; const char *str; char name[80]; - int ret, i; + int i; + /* write the ID of the current item */ menu = (struct scene_obj_menu *)obj; ret = -EAGAIN; for (i = 0; ret && i < 2; i++) { @@ -288,20 +343,11 @@ static int h_write_settings(struct scene_obj *obj, void *vpriv) if (ret) return log_msg_ret("mis", ret); + /* write the text of the current item */ snprintf(name, sizeof(name), "%s-str", obj->name); - ret = -EAGAIN; - for (i = 0; ret && i < 2; i++) { - ret = fdt_property_string(abuf_data(buf), name, str); - if (!i) { - ret = check_space(ret, buf); - if (ret) - return log_msg_ret("rs2", -ENOMEM); - } - } - - /* this should not happen */ + ret = write_dt_string(buf, name, str); if (ret) - return log_msg_ret("wr2", -EFAULT); + return log_msg_ret("wr2", ret); break; } @@ -364,6 +410,19 @@ static int h_read_settings(struct scene_obj *obj, void *vpriv) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: break; + case SCENEOBJT_TEXTLINE: { + const struct scene_obj_textline *tline; + const char *val; + int len; + + tline = (struct scene_obj_textline *)obj; + + val = ofnode_read_prop(node, obj->name, &len); + if (len >= tline->max_chars) + return log_msg_ret("str", -ENOSPC); + strcpy(abuf_data(&tline->buf), val); + break; + } case SCENEOBJT_MENU: { struct scene_obj_menu *menu; uint val; @@ -412,31 +471,51 @@ static int h_write_settings_env(struct scene_obj *obj, void *vpriv) const char *str; int val, ret; - if (obj->type != SCENEOBJT_MENU) - return 0; - - menu = (struct scene_obj_menu *)obj; - val = menu->cur_item_id; snprintf(var, sizeof(var), "c.%s", obj->name); - if (priv->verbose) - printf("%s=%d\n", var, val); + switch (obj->type) { + case SCENEOBJT_NONE: + case SCENEOBJT_IMAGE: + case SCENEOBJT_TEXT: + break; + case SCENEOBJT_MENU: + menu = (struct scene_obj_menu *)obj; + val = menu->cur_item_id; - ret = env_set_ulong(var, val); - if (ret) - return log_msg_ret("set", ret); + if (priv->verbose) + printf("%s=%d\n", var, val); - ret = get_cur_menuitem_text(menu, &str); - if (ret) - return log_msg_ret("mis", ret); + ret = env_set_ulong(var, val); + if (ret) + return log_msg_ret("set", ret); - snprintf(name, sizeof(name), "c.%s-str", obj->name); - if (priv->verbose) - printf("%s=%s\n", name, str); + ret = get_cur_menuitem_text(menu, &str); + if (ret) + return log_msg_ret("mis", ret); - ret = env_set(name, str); - if (ret) - return log_msg_ret("st2", ret); + snprintf(name, sizeof(name), "c.%s-str", obj->name); + if (priv->verbose) + printf("%s=%s\n", name, str); + + ret = env_set(name, str); + if (ret) + return log_msg_ret("st2", ret); + break; + case SCENEOBJT_TEXTLINE: { + const struct scene_obj_textline *tline; + + tline = (struct scene_obj_textline *)obj; + str = abuf_data(&tline->buf); + ret = env_set(var, str); + if (ret) + return log_msg_ret("set", ret); + + if (priv->verbose) + printf("%s=%s\n", var, str); + + break; + } + } return 0; } @@ -464,24 +543,43 @@ static int h_read_settings_env(struct scene_obj *obj, void *vpriv) char var[60]; int val; - if (obj->type != SCENEOBJT_MENU) - return 0; - - menu = (struct scene_obj_menu *)obj; - val = menu->cur_item_id; snprintf(var, sizeof(var), "c.%s", obj->name); - val = env_get_ulong(var, 10, 0); - if (priv->verbose) - printf("%s=%d\n", var, val); - if (!val) - return log_msg_ret("get", -ENOENT); - - /* - * note that no validation is done here, to make sure the ID is valid - * and actually points to a menu item - */ - menu->cur_item_id = val; + switch (obj->type) { + case SCENEOBJT_NONE: + case SCENEOBJT_IMAGE: + case SCENEOBJT_TEXT: + break; + case SCENEOBJT_MENU: + menu = (struct scene_obj_menu *)obj; + val = env_get_ulong(var, 10, 0); + if (priv->verbose) + printf("%s=%d\n", var, val); + if (!val) + return log_msg_ret("get", -ENOENT); + + /* + * note that no validation is done here, to make sure the ID is + * valid * and actually points to a menu item + */ + menu->cur_item_id = val; + break; + case SCENEOBJT_TEXTLINE: { + const struct scene_obj_textline *tline; + const char *value; + + tline = (struct scene_obj_textline *)obj; + value = env_get(var); + if (value && strlen(value) >= tline->max_chars) + return log_msg_ret("str", -ENOSPC); + if (!value) + value = ""; + if (priv->verbose) + printf("%s=%s\n", var, value); + strcpy(abuf_data(&tline->buf), value); + break; + } + } return 0; } diff --git a/boot/expo_build.c b/boot/expo_build.c index 910f1b47980..04d88a2c308 100644 --- a/boot/expo_build.c +++ b/boot/expo_build.c @@ -23,10 +23,14 @@ * if there is nothing for this ID. Since ID 0 is never used, the first * element of this array is always NULL * @str_count: Number of entries in @str_for_id + * @err_node: Node being processed (for error reporting) + * @err_prop: Property being processed (for error reporting) */ struct build_info { const char **str_for_id; int str_count; + ofnode err_node; + const char *err_prop; }; /** @@ -46,6 +50,7 @@ int add_txt_str(struct build_info *info, ofnode node, struct scene *scn, uint str_id; int ret; + info->err_prop = find_name; text = ofnode_read_string(node, find_name); if (!text) { char name[40]; @@ -54,7 +59,7 @@ int add_txt_str(struct build_info *info, ofnode node, struct scene *scn, snprintf(name, sizeof(name), "%s-id", find_name); ret = ofnode_read_u32(node, name, &id); if (ret) - return log_msg_ret("id", -EINVAL); + return log_msg_ret("id", -ENOENT); if (id >= info->str_count) return log_msg_ret("id", -E2BIG); @@ -164,9 +169,10 @@ static int read_strings(struct build_info *info, ofnode root) int ret; u32 id; + info->err_node = node; ret = ofnode_read_u32(node, "id", &id); if (ret) - return log_msg_ret("id", -EINVAL); + return log_msg_ret("id", -ENOENT); val = ofnode_read_string(node, "value"); if (!val) return log_msg_ret("val", -EINVAL); @@ -241,6 +247,8 @@ static int menu_build(struct build_info *info, ofnode node, struct scene *scn, return log_msg_ret("tit", ret); title_id = ret; ret = scene_menu_set_title(scn, menu_id, title_id); + if (ret) + return log_msg_ret("set", ret); item_ids = ofnode_read_prop(node, "item-id", &size); if (!item_ids) @@ -279,6 +287,49 @@ static int menu_build(struct build_info *info, ofnode node, struct scene *scn, return 0; } +static int textline_build(struct build_info *info, ofnode node, + struct scene *scn, uint id, struct scene_obj **objp) +{ + struct scene_obj_textline *ted; + uint ted_id, edit_id; + const char *name; + u32 max_chars; + int ret; + + name = ofnode_get_name(node); + + info->err_prop = "max-chars"; + ret = ofnode_read_u32(node, "max-chars", &max_chars); + if (ret) + return log_msg_ret("max", -ENOENT); + + ret = scene_textline(scn, name, id, max_chars, &ted); + if (ret < 0) + return log_msg_ret("ted", ret); + ted_id = ret; + + /* Set the title */ + ret = add_txt_str(info, node, scn, "title", 0); + if (ret < 0) + return log_msg_ret("tit", ret); + ted->label_id = ret; + + /* Setup the editor */ + info->err_prop = "edit-id"; + ret = ofnode_read_u32(node, "edit-id", &id); + if (ret) + return log_msg_ret("id", -ENOENT); + edit_id = ret; + + ret = scene_txt_str(scn, "edit", edit_id, 0, abuf_data(&ted->buf), + NULL); + if (ret < 0) + return log_msg_ret("add", ret); + ted->edit_id = ret; + + return 0; +} + /** * obj_build() - Build an expo object and add it to a scene * @@ -300,7 +351,7 @@ static int obj_build(struct build_info *info, ofnode node, struct scene *scn) log_debug("- object %s\n", ofnode_get_name(node)); ret = ofnode_read_u32(node, "id", &id); if (ret) - return log_msg_ret("id", -EINVAL); + return log_msg_ret("id", -ENOENT); type = ofnode_read_string(node, "type"); if (!type) @@ -308,8 +359,10 @@ static int obj_build(struct build_info *info, ofnode node, struct scene *scn) if (!strcmp("menu", type)) ret = menu_build(info, node, scn, id, &obj); - else - ret = -EINVAL; + else if (!strcmp("textline", type)) + ret = textline_build(info, node, scn, id, &obj); + else + ret = -EOPNOTSUPP; if (ret) return log_msg_ret("bld", ret); @@ -341,11 +394,12 @@ static int scene_build(struct build_info *info, ofnode scn_node, ofnode node; int ret; + info->err_node = scn_node; name = ofnode_get_name(scn_node); log_debug("Building scene %s\n", name); ret = ofnode_read_u32(scn_node, "id", &id); if (ret) - return log_msg_ret("id", -EINVAL); + return log_msg_ret("id", -ENOENT); ret = scene_new(exp, name, id, &scn); if (ret < 0) @@ -362,6 +416,7 @@ static int scene_build(struct build_info *info, ofnode scn_node, return log_msg_ret("pr", ret); ofnode_for_each_subnode(node, scn_node) { + info->err_node = node; ret = obj_build(info, node, scn); if (ret < 0) return log_msg_ret("mit", ret); @@ -370,20 +425,19 @@ static int scene_build(struct build_info *info, ofnode scn_node, return 0; } -int expo_build(ofnode root, struct expo **expp) +int build_it(struct build_info *info, ofnode root, struct expo **expp) { - struct build_info info; ofnode scenes, node; struct expo *exp; u32 dyn_start; int ret; - memset(&info, '\0', sizeof(info)); - ret = read_strings(&info, root); + ret = read_strings(info, root); if (ret) return log_msg_ret("str", ret); if (_DEBUG) - list_strings(&info); + list_strings(info); + info->err_node = root; ret = expo_new("name", NULL, &exp); if (ret) @@ -397,7 +451,7 @@ int expo_build(ofnode root, struct expo **expp) return log_msg_ret("sno", -EINVAL); ofnode_for_each_subnode(node, scenes) { - ret = scene_build(&info, node, exp); + ret = scene_build(info, node, exp); if (ret < 0) return log_msg_ret("scn", ret); } @@ -405,3 +459,27 @@ int expo_build(ofnode root, struct expo **expp) return 0; } + +int expo_build(ofnode root, struct expo **expp) +{ + struct build_info info; + struct expo *exp; + int ret; + + memset(&info, '\0', sizeof(info)); + ret = build_it(&info, root, &exp); + if (ret) { + char buf[120]; + int node_ret; + + node_ret = ofnode_get_path(info.err_node, buf, sizeof(buf)); + log_warning("Build failed at node %s, property %s\n", + node_ret ? ofnode_get_name(info.err_node) : buf, + info.err_prop); + + return log_msg_ret("bui", ret); + } + *expp = exp; + + return 0; +} diff --git a/boot/scene.c b/boot/scene.c index 6c52948eb69..d4dfb49ada1 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -32,6 +32,14 @@ int scene_new(struct expo *exp, const char *name, uint id, struct scene **scnp) return log_msg_ret("name", -ENOMEM); } + abuf_init(&scn->buf); + if (!abuf_realloc(&scn->buf, EXPO_MAX_CHARS + 1)) { + free(scn->name); + free(scn); + return log_msg_ret("buf", -ENOMEM); + } + abuf_init(&scn->entry_save); + INIT_LIST_HEAD(&scn->obj_head); scn->id = resolve_id(exp, id); scn->expo = exp; @@ -57,6 +65,8 @@ void scene_destroy(struct scene *scn) list_for_each_entry_safe(obj, next, &scn->obj_head, sibling) scene_obj_destroy(obj); + abuf_uninit(&scn->entry_save); + abuf_uninit(&scn->buf); free(scn->name); free(scn); } @@ -137,7 +147,7 @@ int scene_img(struct scene *scn, const char *name, uint id, char *data, sizeof(struct scene_obj_img), (struct scene_obj **)&img); if (ret < 0) - return log_msg_ret("obj", -ENOMEM); + return log_msg_ret("obj", ret); img->data = data; @@ -157,7 +167,7 @@ int scene_txt(struct scene *scn, const char *name, uint id, uint str_id, sizeof(struct scene_obj_txt), (struct scene_obj **)&txt); if (ret < 0) - return log_msg_ret("obj", -ENOMEM); + return log_msg_ret("obj", ret); txt->str_id = str_id; @@ -176,14 +186,15 @@ int scene_txt_str(struct scene *scn, const char *name, uint id, uint str_id, ret = expo_str(scn->expo, name, str_id, str); if (ret < 0) return log_msg_ret("str", ret); - else if (ret != str_id) + if (str_id && ret != str_id) return log_msg_ret("id", -EEXIST); + str_id = ret; ret = scene_obj_add(scn, name, id, SCENEOBJT_TEXT, sizeof(struct scene_obj_txt), (struct scene_obj **)&txt); if (ret < 0) - return log_msg_ret("obj", -ENOMEM); + return log_msg_ret("obj", ret); txt->str_id = str_id; @@ -269,6 +280,7 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) switch (obj->type) { case SCENEOBJT_NONE: case SCENEOBJT_MENU: + case SCENEOBJT_TEXTLINE: break; case SCENEOBJT_IMAGE: { struct scene_obj_img *img = (struct scene_obj_img *)obj; @@ -314,6 +326,51 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) } /** + * scene_render_background() - Render the background for an object + * + * @obj: Object to render + * @box_only: true to show a box around the object, but keep the normal + * background colour inside + */ +static void scene_render_background(struct scene_obj *obj, bool box_only) +{ + struct expo *exp = obj->scene->expo; + const struct expo_theme *theme = &exp->theme; + struct vidconsole_bbox bbox, label_bbox; + struct udevice *dev = exp->display; + struct video_priv *vid_priv; + struct udevice *cons = exp->cons; + struct vidconsole_colour old; + enum colour_idx fore, back; + uint inset = theme->menu_inset; + + /* draw a background for the object */ + if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) { + fore = VID_BLACK; + back = VID_WHITE; + } else { + fore = VID_LIGHT_GRAY; + back = VID_BLACK; + } + + /* see if this object wants to render a background */ + if (scene_obj_calc_bbox(obj, &bbox, &label_bbox)) + return; + + vidconsole_push_colour(cons, fore, back, &old); + vid_priv = dev_get_uclass_priv(dev); + video_fill_part(dev, label_bbox.x0 - inset, label_bbox.y0 - inset, + label_bbox.x1 + inset, label_bbox.y1 + inset, + vid_priv->colour_fg); + vidconsole_pop_colour(cons, &old); + if (box_only) { + video_fill_part(dev, label_bbox.x0, label_bbox.y0, + label_bbox.x1, label_bbox.y1, + vid_priv->colour_bg); + } +} + +/** * scene_obj_render() - Render an object * */ @@ -396,7 +453,7 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) return -ENOTSUPP; /* draw a background behind the menu items */ - scene_menu_render(menu); + scene_render_background(obj, false); } /* * With a vidconsole, the text and item pointer are rendered as @@ -412,6 +469,10 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) break; } + case SCENEOBJT_TEXTLINE: + if (obj->flags & SCENEOF_OPEN) + scene_render_background(obj, true); + break; } return 0; @@ -423,13 +484,29 @@ int scene_arrange(struct scene *scn) int ret; list_for_each_entry(obj, &scn->obj_head, sibling) { - if (obj->type == SCENEOBJT_MENU) { + switch (obj->type) { + case SCENEOBJT_NONE: + case SCENEOBJT_IMAGE: + case SCENEOBJT_TEXT: + break; + case SCENEOBJT_MENU: { struct scene_obj_menu *menu; menu = (struct scene_obj_menu *)obj, ret = scene_menu_arrange(scn, menu); if (ret) return log_msg_ret("arr", ret); + break; + } + case SCENEOBJT_TEXTLINE: { + struct scene_obj_textline *tline; + + tline = (struct scene_obj_textline *)obj, + ret = scene_textline_arrange(scn, tline); + if (ret) + return log_msg_ret("arr", ret); + break; + } } } @@ -452,9 +529,20 @@ int scene_render_deps(struct scene *scn, uint id) if (ret && ret != -ENOTSUPP) return log_msg_ret("ren", ret); - if (obj->type == SCENEOBJT_MENU) + switch (obj->type) { + case SCENEOBJT_NONE: + case SCENEOBJT_IMAGE: + case SCENEOBJT_TEXT: + break; + case SCENEOBJT_MENU: scene_menu_render_deps(scn, (struct scene_obj_menu *)obj); + break; + case SCENEOBJT_TEXTLINE: + scene_textline_render_deps(scn, + (struct scene_obj_textline *)obj); + break; + } } return 0; @@ -501,7 +589,7 @@ static void send_key_obj(struct scene *scn, struct scene_obj *obj, int key, sibling)) { obj = list_entry(obj->sibling.prev, struct scene_obj, sibling); - if (obj->type == SCENEOBJT_MENU) { + if (scene_obj_can_highlight(obj)) { event->type = EXPOACT_POINT_OBJ; event->select.id = obj->id; log_debug("up to obj %d\n", event->select.id); @@ -513,7 +601,7 @@ static void send_key_obj(struct scene *scn, struct scene_obj *obj, int key, while (!list_is_last(&obj->sibling, &scn->obj_head)) { obj = list_entry(obj->sibling.next, struct scene_obj, sibling); - if (obj->type == SCENEOBJT_MENU) { + if (scene_obj_can_highlight(obj)) { event->type = EXPOACT_POINT_OBJ; event->select.id = obj->id; log_debug("down to obj %d\n", event->select.id); @@ -522,7 +610,7 @@ static void send_key_obj(struct scene *scn, struct scene_obj *obj, int key, } break; case BKEY_SELECT: - if (obj->type == SCENEOBJT_MENU) { + if (scene_obj_can_highlight(obj)) { event->type = EXPOACT_OPEN; event->select.id = obj->id; log_debug("open obj %d\n", event->select.id); @@ -537,7 +625,6 @@ static void send_key_obj(struct scene *scn, struct scene_obj *obj, int key, int scene_send_key(struct scene *scn, int key, struct expo_action *event) { - struct scene_obj_menu *menu; struct scene_obj *obj; int ret; @@ -561,10 +648,30 @@ int scene_send_key(struct scene *scn, int key, struct expo_action *event) return 0; } - menu = (struct scene_obj_menu *)obj, - ret = scene_menu_send_key(scn, menu, key, event); - if (ret) - return log_msg_ret("key", ret); + switch (obj->type) { + case SCENEOBJT_NONE: + case SCENEOBJT_IMAGE: + case SCENEOBJT_TEXT: + break; + case SCENEOBJT_MENU: { + struct scene_obj_menu *menu; + + menu = (struct scene_obj_menu *)obj, + ret = scene_menu_send_key(scn, menu, key, event); + if (ret) + return log_msg_ret("key", ret); + break; + } + case SCENEOBJT_TEXTLINE: { + struct scene_obj_textline *tline; + + tline = (struct scene_obj_textline *)obj, + ret = scene_textline_send_key(scn, tline, key, event); + if (ret) + return log_msg_ret("key", ret); + break; + } + } return 0; } @@ -583,6 +690,32 @@ int scene_send_key(struct scene *scn, int key, struct expo_action *event) return 0; } +int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox *bbox, + struct vidconsole_bbox *label_bbox) +{ + switch (obj->type) { + case SCENEOBJT_NONE: + case SCENEOBJT_IMAGE: + case SCENEOBJT_TEXT: + return -ENOSYS; + case SCENEOBJT_MENU: { + struct scene_obj_menu *menu = (struct scene_obj_menu *)obj; + + scene_menu_calc_bbox(menu, bbox, label_bbox); + break; + } + case SCENEOBJT_TEXTLINE: { + struct scene_obj_textline *tline; + + tline = (struct scene_obj_textline *)obj; + scene_textline_calc_bbox(tline, bbox, label_bbox); + break; + } + } + + return 0; +} + int scene_calc_dims(struct scene *scn, bool do_menus) { struct scene_obj *obj; @@ -616,6 +749,16 @@ int scene_calc_dims(struct scene *scn, bool do_menus) } break; } + case SCENEOBJT_TEXTLINE: { + struct scene_obj_textline *tline; + + tline = (struct scene_obj_textline *)obj; + ret = scene_textline_calc_dims(tline); + if (ret) + return log_msg_ret("men", ret); + + break; + } } } @@ -635,6 +778,7 @@ int scene_apply_theme(struct scene *scn, struct expo_theme *theme) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_MENU: + case SCENEOBJT_TEXTLINE: break; case SCENEOBJT_TEXT: scene_txt_set_font(scn, obj->id, NULL, @@ -660,20 +804,49 @@ void scene_highlight_first(struct scene *scn) struct scene_obj *obj; list_for_each_entry(obj, &scn->obj_head, sibling) { - switch (obj->type) { - case SCENEOBJT_MENU: + if (scene_obj_can_highlight(obj)) { scene_set_highlight_id(scn, obj->id); return; - default: - break; } } } +static int scene_obj_open(struct scene *scn, struct scene_obj *obj) +{ + int ret; + + switch (obj->type) { + case SCENEOBJT_NONE: + case SCENEOBJT_IMAGE: + case SCENEOBJT_MENU: + case SCENEOBJT_TEXT: + break; + case SCENEOBJT_TEXTLINE: + ret = scene_textline_open(scn, + (struct scene_obj_textline *)obj); + if (ret) + return log_msg_ret("op", ret); + break; + } + + return 0; +} + int scene_set_open(struct scene *scn, uint id, bool open) { + struct scene_obj *obj; int ret; + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("find", -ENOENT); + + if (open) { + ret = scene_obj_open(scn, obj); + if (ret) + return log_msg_ret("op", ret); + } + ret = scene_obj_flag_clrset(scn, id, SCENEOF_OPEN, open ? SCENEOF_OPEN : 0); if (ret) @@ -697,3 +870,29 @@ int scene_iter_objs(struct scene *scn, expo_scene_obj_iterator iter, return 0; } + +int scene_bbox_union(struct scene *scn, uint id, int inset, + struct vidconsole_bbox *bbox) +{ + struct scene_obj *obj; + + if (!id) + return 0; + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("obj", -ENOENT); + if (bbox->valid) { + bbox->x0 = min(bbox->x0, obj->dim.x - inset); + bbox->y0 = min(bbox->y0, obj->dim.y); + bbox->x1 = max(bbox->x1, obj->dim.x + obj->dim.w + inset); + bbox->y1 = max(bbox->y1, obj->dim.y + obj->dim.h); + } else { + bbox->x0 = obj->dim.x - inset; + bbox->y0 = obj->dim.y; + bbox->x1 = obj->dim.x + obj->dim.w + inset; + bbox->y1 = obj->dim.y + obj->dim.h; + bbox->valid = true; + } + + return 0; +} diff --git a/boot/scene_internal.h b/boot/scene_internal.h index 695a907dc6a..e72202c9821 100644 --- a/boot/scene_internal.h +++ b/boot/scene_internal.h @@ -9,6 +9,8 @@ #ifndef __SCENE_INTERNAL_H #define __SCENE_INTERNAL_H +struct vidconsole_bbox; + typedef int (*expo_scene_obj_iterator)(struct scene_obj *obj, void *priv); /** @@ -100,6 +102,18 @@ int scene_calc_dims(struct scene *scn, bool do_menus); int scene_menu_arrange(struct scene *scn, struct scene_obj_menu *menu); /** + * scene_textline_arrange() - Set the position of things in a textline + * + * This updates any items associated with a textline to make sure they are + * positioned correctly relative to the textline. + * + * @scn: Scene to update + * @tline: textline to process + * Returns: 0 if OK, -ve on error + */ +int scene_textline_arrange(struct scene *scn, struct scene_obj_textline *tline); + +/** * scene_apply_theme() - Apply a theme to a scene * * @scn: Scene to update @@ -122,6 +136,18 @@ int scene_menu_send_key(struct scene *scn, struct scene_obj_menu *menu, int key, struct expo_action *event); /** + * scene_textline_send_key() - Send a key to a textline for processing + * + * @scn: Scene to use + * @tline: textline to use + * @key: Key code to send (KEY_...) + * @event: Place to put any event which is generated by the key + * Returns: 0 if OK (always) + */ +int scene_textline_send_key(struct scene *scn, struct scene_obj_textline *tline, + int key, struct expo_action *event); + +/** * scene_menu_destroy() - Destroy a menu in a scene * * @scn: Scene to destroy @@ -164,13 +190,6 @@ int scene_render(struct scene *scn); int scene_send_key(struct scene *scn, int key, struct expo_action *event); /** - * scene_menu_render() - Render the background behind a menu - * - * @menu: Menu to render - */ -void scene_menu_render(struct scene_obj_menu *menu); - -/** * scene_render_deps() - Render an object and its dependencies * * @scn: Scene to render @@ -185,12 +204,24 @@ int scene_render_deps(struct scene *scn, uint id); * Renders the menu and all of its attached objects * * @scn: Scene to render - * @menu: Menu render + * @menu: Menu to render * Returns: 0 if OK, -ve on error */ int scene_menu_render_deps(struct scene *scn, struct scene_obj_menu *menu); /** + * scene_textline_render_deps() - Render a textline and its dependencies + * + * Renders the textline and all of its attached objects + * + * @scn: Scene to render + * @tline: textline to render + * Returns: 0 if OK, -ve on error + */ +int scene_textline_render_deps(struct scene *scn, + struct scene_obj_textline *tline); + +/** * scene_menu_calc_dims() - Calculate the dimensions of a menu * * Updates the width and height of the menu based on its contents @@ -246,4 +277,85 @@ struct scene_menitem *scene_menuitem_find(const struct scene_obj_menu *menu, struct scene_menitem *scene_menuitem_find_seq(const struct scene_obj_menu *menu, uint seq); +/** + * scene_bbox_union() - update bouding box with the demensions of an object + * + * Updates @bbox so that it encompasses the bounding box of object @id + * + * @snd: Scene containing object + * @id: Object id + * @inset: Amount of inset to use for width + * @bbox: Bounding box to update + * Return: 0 if OK, -ve on error + */ +int scene_bbox_union(struct scene *scn, uint id, int inset, + struct vidconsole_bbox *bbox); + +/** + * scene_textline_calc_dims() - Calculate the dimensions of a textline + * + * Updates the width and height of the textline based on its contents + * + * @tline: Textline to update + * Returns 0 if OK, -ENOTSUPP if there is no graphical console + */ +int scene_textline_calc_dims(struct scene_obj_textline *tline); + +/** + * scene_menu_calc_bbox() - Calculate bounding boxes for the menu + * + * @menu: Menu to process + * @bbox: Returns bounding box of menu including prompts + * @label_bbox: Returns bounding box of labels + * Return: 0 if OK, -ve on error + */ +void scene_menu_calc_bbox(struct scene_obj_menu *menu, + struct vidconsole_bbox *bbox, + struct vidconsole_bbox *label_bbox); + +/** + * scene_textline_calc_bbox() - Calculate bounding box for the textline + * + * @textline: Menu to process + * @bbox: Returns bounding box of textline including prompt + * @edit_bbox: Returns bounding box of editable part + * Return: 0 if OK, -ve on error + */ +void scene_textline_calc_bbox(struct scene_obj_textline *menu, + struct vidconsole_bbox *bbox, + struct vidconsole_bbox *label_bbox); + +/** + * scene_obj_calc_bbox() - Calculate bounding boxes for an object + * + * @obj: Object to process + * @bbox: Returns bounding box of object including prompts + * @label_bbox: Returns bounding box of labels (active area) + * Return: 0 if OK, -ve on error + */ +int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox *bbox, + struct vidconsole_bbox *label_bbox); + +/** + * scene_textline_open() - Open a textline object + * + * Set up the text editor ready for use + * + * @scn: Scene containing the textline + * @tline: textline object + * Return: 0 if OK, -ve on error + */ +int scene_textline_open(struct scene *scn, struct scene_obj_textline *tline); + +/** + * scene_textline_close() - Close a textline object + * + * Close out the text editor after use + * + * @scn: Scene containing the textline + * @tline: textline object + * Return: 0 if OK, -ve on error + */ +int scene_textline_close(struct scene *scn, struct scene_obj_textline *tline); + #endif /* __SCENE_INTERNAL_H */ diff --git a/boot/scene_menu.c b/boot/scene_menu.c index e0dcd0a4e04..63994165efb 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -114,42 +114,9 @@ static void menu_point_to_item(struct scene_obj_menu *menu, uint item_id) update_pointers(menu, item_id, true); } -static int scene_bbox_union(struct scene *scn, uint id, int inset, - struct vidconsole_bbox *bbox) -{ - struct scene_obj *obj; - - if (!id) - return 0; - obj = scene_obj_find(scn, id, SCENEOBJT_NONE); - if (!obj) - return log_msg_ret("obj", -ENOENT); - if (bbox->valid) { - bbox->x0 = min(bbox->x0, obj->dim.x - inset); - bbox->y0 = min(bbox->y0, obj->dim.y); - bbox->x1 = max(bbox->x1, obj->dim.x + obj->dim.w + inset); - bbox->y1 = max(bbox->y1, obj->dim.y + obj->dim.h); - } else { - bbox->x0 = obj->dim.x - inset; - bbox->y0 = obj->dim.y; - bbox->x1 = obj->dim.x + obj->dim.w + inset; - bbox->y1 = obj->dim.y + obj->dim.h; - bbox->valid = true; - } - - return 0; -} - -/** - * scene_menu_calc_bbox() - Calculate bounding boxes for the menu - * - * @menu: Menu to process - * @bbox: Returns bounding box of menu including prompts - * @label_bbox: Returns bounding box of labels - */ -static void scene_menu_calc_bbox(struct scene_obj_menu *menu, - struct vidconsole_bbox *bbox, - struct vidconsole_bbox *label_bbox) +void scene_menu_calc_bbox(struct scene_obj_menu *menu, + struct vidconsole_bbox *bbox, + struct vidconsole_bbox *label_bbox) { const struct expo_theme *theme = &menu->obj.scene->expo->theme; const struct scene_menitem *item; @@ -549,35 +516,6 @@ int scene_menu_display(struct scene_obj_menu *menu) return -ENOTSUPP; } -void scene_menu_render(struct scene_obj_menu *menu) -{ - struct expo *exp = menu->obj.scene->expo; - const struct expo_theme *theme = &exp->theme; - struct vidconsole_bbox bbox, label_bbox; - struct udevice *dev = exp->display; - struct video_priv *vid_priv; - struct udevice *cons = exp->cons; - struct vidconsole_colour old; - enum colour_idx fore, back; - - if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) { - fore = VID_BLACK; - back = VID_WHITE; - } else { - fore = VID_LIGHT_GRAY; - back = VID_BLACK; - } - - scene_menu_calc_bbox(menu, &bbox, &label_bbox); - vidconsole_push_colour(cons, fore, back, &old); - vid_priv = dev_get_uclass_priv(dev); - video_fill_part(dev, label_bbox.x0 - theme->menu_inset, - label_bbox.y0 - theme->menu_inset, - label_bbox.x1, label_bbox.y1 + theme->menu_inset, - vid_priv->colour_fg); - vidconsole_pop_colour(cons, &old); -} - int scene_menu_render_deps(struct scene *scn, struct scene_obj_menu *menu) { struct scene_menitem *item; diff --git a/boot/scene_textline.c b/boot/scene_textline.c new file mode 100644 index 00000000000..6ea072a1c26 --- /dev/null +++ b/boot/scene_textline.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Implementation of a menu in a scene + * + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY LOGC_EXPO + +#include <common.h> +#include <expo.h> +#include <menu.h> +#include <video_console.h> +#include "scene_internal.h" + +int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars, + struct scene_obj_textline **tlinep) +{ + struct scene_obj_textline *tline; + char *buf; + int ret; + + if (max_chars >= EXPO_MAX_CHARS) + return log_msg_ret("chr", -E2BIG); + + ret = scene_obj_add(scn, name, id, SCENEOBJT_TEXTLINE, + sizeof(struct scene_obj_textline), + (struct scene_obj **)&tline); + if (ret < 0) + return log_msg_ret("obj", -ENOMEM); + abuf_init(&tline->buf); + if (!abuf_realloc(&tline->buf, max_chars + 1)) + return log_msg_ret("buf", -ENOMEM); + buf = abuf_data(&tline->buf); + *buf = '\0'; + tline->pos = max_chars; + tline->max_chars = max_chars; + + if (tlinep) + *tlinep = tline; + + return tline->obj.id; +} + +void scene_textline_calc_bbox(struct scene_obj_textline *tline, + struct vidconsole_bbox *bbox, + struct vidconsole_bbox *edit_bbox) +{ + const struct expo_theme *theme = &tline->obj.scene->expo->theme; + + bbox->valid = false; + scene_bbox_union(tline->obj.scene, tline->label_id, 0, bbox); + scene_bbox_union(tline->obj.scene, tline->edit_id, 0, bbox); + + edit_bbox->valid = false; + scene_bbox_union(tline->obj.scene, tline->edit_id, theme->menu_inset, + edit_bbox); +} + +int scene_textline_calc_dims(struct scene_obj_textline *tline) +{ + struct scene *scn = tline->obj.scene; + struct vidconsole_bbox bbox; + struct scene_obj_txt *txt; + int ret; + + txt = scene_obj_find(scn, tline->edit_id, SCENEOBJT_NONE); + if (!txt) + return log_msg_ret("dim", -ENOENT); + + ret = vidconsole_nominal(scn->expo->cons, txt->font_name, + txt->font_size, tline->max_chars, &bbox); + if (ret) + return log_msg_ret("nom", ret); + + if (bbox.valid) { + tline->obj.dim.w = bbox.x1 - bbox.x0; + tline->obj.dim.h = bbox.y1 - bbox.y0; + + scene_obj_set_size(scn, tline->edit_id, tline->obj.dim.w, + tline->obj.dim.h); + } + + return 0; +} + +int scene_textline_arrange(struct scene *scn, struct scene_obj_textline *tline) +{ + const bool open = tline->obj.flags & SCENEOF_OPEN; + bool point; + int x, y; + int ret; + + x = tline->obj.dim.x; + y = tline->obj.dim.y; + if (tline->label_id) { + ret = scene_obj_set_pos(scn, tline->label_id, tline->obj.dim.x, + y); + if (ret < 0) + return log_msg_ret("tit", ret); + + ret = scene_obj_set_pos(scn, tline->edit_id, + tline->obj.dim.x + 200, y); + if (ret < 0) + return log_msg_ret("tit", ret); + + ret = scene_obj_get_hw(scn, tline->label_id, NULL); + if (ret < 0) + return log_msg_ret("hei", ret); + + y += ret * 2; + } + + point = scn->highlight_id == tline->obj.id; + point &= !open; + scene_obj_flag_clrset(scn, tline->edit_id, SCENEOF_POINT, + point ? SCENEOF_POINT : 0); + + return 0; +} + +int scene_textline_send_key(struct scene *scn, struct scene_obj_textline *tline, + int key, struct expo_action *event) +{ + const bool open = tline->obj.flags & SCENEOF_OPEN; + + log_debug("key=%d\n", key); + switch (key) { + case BKEY_QUIT: + if (open) { + event->type = EXPOACT_CLOSE; + event->select.id = tline->obj.id; + + /* Copy the backup text from the scene buffer */ + memcpy(abuf_data(&tline->buf), abuf_data(&scn->buf), + abuf_size(&scn->buf)); + } else { + event->type = EXPOACT_QUIT; + log_debug("menu quit\n"); + } + break; + case BKEY_SELECT: + if (!open) + break; + event->type = EXPOACT_CLOSE; + event->select.id = tline->obj.id; + key = '\n'; + fallthrough; + default: { + struct udevice *cons = scn->expo->cons; + int ret; + + ret = vidconsole_entry_restore(cons, &scn->entry_save); + if (ret) + return log_msg_ret("sav", ret); + ret = cread_line_process_ch(&scn->cls, key); + ret = vidconsole_entry_save(cons, &scn->entry_save); + if (ret) + return log_msg_ret("sav", ret); + break; + } + } + + return 0; +} + +int scene_textline_render_deps(struct scene *scn, + struct scene_obj_textline *tline) +{ + const bool open = tline->obj.flags & SCENEOF_OPEN; + struct udevice *cons = scn->expo->cons; + struct scene_obj_txt *txt; + int ret; + + scene_render_deps(scn, tline->label_id); + scene_render_deps(scn, tline->edit_id); + + /* show the vidconsole cursor if open */ + if (open) { + /* get the position within the field */ + txt = scene_obj_find(scn, tline->edit_id, SCENEOBJT_NONE); + if (!txt) + return log_msg_ret("cur", -ENOENT); + + if (txt->font_name || txt->font_size) { + ret = vidconsole_select_font(cons, + txt->font_name, + txt->font_size); + } else { + ret = vidconsole_select_font(cons, NULL, 0); + } + + ret = vidconsole_entry_restore(cons, &scn->entry_save); + if (ret) + return log_msg_ret("sav", ret); + + vidconsole_set_cursor_visible(cons, true, txt->obj.dim.x, + txt->obj.dim.y, scn->cls.num); + } + + return 0; +} + +int scene_textline_open(struct scene *scn, struct scene_obj_textline *tline) +{ + struct udevice *cons = scn->expo->cons; + struct scene_obj_txt *txt; + int ret; + + /* Copy the text into the scene buffer in case the edit is cancelled */ + memcpy(abuf_data(&scn->buf), abuf_data(&tline->buf), + abuf_size(&scn->buf)); + + /* get the position of the editable */ + txt = scene_obj_find(scn, tline->edit_id, SCENEOBJT_NONE); + if (!txt) + return log_msg_ret("cur", -ENOENT); + + vidconsole_set_cursor_pos(cons, txt->obj.dim.x, txt->obj.dim.y); + vidconsole_entry_start(cons); + cli_cread_init(&scn->cls, abuf_data(&tline->buf), tline->max_chars); + scn->cls.insert = true; + ret = vidconsole_entry_save(cons, &scn->entry_save); + if (ret) + return log_msg_ret("sav", ret); + + return 0; +} diff --git a/cmd/Kconfig b/cmd/Kconfig index 6470b138d2f..5bc0a92d57a 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -176,6 +176,13 @@ config CMD_FWU_METADATA help Command to read the metadata and dump it's contents +config CMD_HISTORY + bool "history" + depends on CMDLINE_EDITING + help + Show the command-line history, i.e. a list of commands that are in + the history buffer. + config CMD_LICENSE bool "license" select BUILD_BIN2C diff --git a/cmd/Makefile b/cmd/Makefile index 9bebf321c39..971f78a7fbd 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_CMD_FUSE) += fuse.o obj-$(CONFIG_CMD_FWU_METADATA) += fwu_mdata.o obj-$(CONFIG_CMD_GETTIME) += gettime.o obj-$(CONFIG_CMD_GPIO) += gpio.o +obj-$(CONFIG_CMD_HISTORY) += history.o obj-$(CONFIG_CMD_HVC) += smccc.o obj-$(CONFIG_CMD_I2C) += i2c.o obj-$(CONFIG_CMD_IOTRACE) += iotrace.o diff --git a/cmd/history.c b/cmd/history.c new file mode 100644 index 00000000000..b6bf4670b1c --- /dev/null +++ b/cmd/history.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <command.h> +#include <cli.h> + +static int do_history(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + cread_print_hist_list(); + + return 0; +} + +U_BOOT_CMD( + history, CONFIG_SYS_MAXARGS, 1, do_history, + "print command history", + "" +); diff --git a/common/cli_readline.c b/common/cli_readline.c index e83743e90c9..06b8d465044 100644 --- a/common/cli_readline.c +++ b/common/cli_readline.c @@ -89,6 +89,14 @@ static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */ #define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1) +static void getcmd_putchars(int count, int ch) +{ + int i; + + for (i = 0; i < count; i++) + getcmd_putch(ch); +} + static void hist_init(void) { int i; @@ -160,11 +168,10 @@ static char *hist_next(void) return ret; } -#ifndef CONFIG_CMDLINE_EDITING -static void cread_print_hist_list(void) +void cread_print_hist_list(void) { int i; - unsigned long n; + uint n; n = hist_num - hist_max; @@ -179,36 +186,35 @@ static void cread_print_hist_list(void) i++; } } -#endif /* CONFIG_CMDLINE_EDITING */ #define BEGINNING_OF_LINE() { \ - while (num) { \ + while (cls->num) { \ getcmd_putch(CTL_BACKSPACE); \ - num--; \ + cls->num--; \ } \ } #define ERASE_TO_EOL() { \ - if (num < eol_num) { \ - printf("%*s", (int)(eol_num - num), ""); \ + if (cls->num < cls->eol_num) { \ + printf("%*s", (int)(cls->eol_num - cls->num), ""); \ do { \ getcmd_putch(CTL_BACKSPACE); \ - } while (--eol_num > num); \ + } while (--cls->eol_num > cls->num); \ } \ } -#define REFRESH_TO_EOL() { \ - if (num < eol_num) { \ - wlen = eol_num - num; \ - putnstr(buf + num, wlen); \ - num = eol_num; \ - } \ +#define REFRESH_TO_EOL() { \ + if (cls->num < cls->eol_num) { \ + uint wlen = cls->eol_num - cls->num; \ + putnstr(buf + cls->num, wlen); \ + cls->num = cls->eol_num; \ + } \ } -static void cread_add_char(char ichar, int insert, unsigned long *num, - unsigned long *eol_num, char *buf, unsigned long len) +static void cread_add_char(char ichar, int insert, uint *num, + uint *eol_num, char *buf, uint len) { - unsigned long wlen; + uint wlen; /* room ??? */ if (insert || *num == *eol_num) { @@ -239,8 +245,7 @@ static void cread_add_char(char ichar, int insert, unsigned long *num, } static void cread_add_str(char *str, int strsize, int insert, - unsigned long *num, unsigned long *eol_num, - char *buf, unsigned long len) + uint *num, uint *eol_num, char *buf, uint len) { while (strsize--) { cread_add_char(*str, insert, num, eol_num, buf, len); @@ -248,121 +253,115 @@ static void cread_add_str(char *str, int strsize, int insert, } } -static int cread_line(const char *const prompt, char *buf, unsigned int *len, - int timeout) +int cread_line_process_ch(struct cli_line_state *cls, char ichar) { - struct cli_ch_state s_cch, *cch = &s_cch; - unsigned long num = 0; - unsigned long eol_num = 0; - unsigned long wlen; - char ichar; - int insert = 1; - int init_len = strlen(buf); - int first = 1; + char *buf = cls->buf; - cli_ch_init(cch); - - if (init_len) - cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len); - - while (1) { - /* Check for saved characters */ - ichar = cli_ch_process(cch, 0); + /* ichar=0x0 when error occurs in U-Boot getc */ + if (!ichar) + return -EAGAIN; - if (!ichar) { - if (bootretry_tstc_timeout()) - return -2; /* timed out */ - if (first && timeout) { - u64 etime = endtick(timeout); - - while (!tstc()) { /* while no incoming data */ - if (get_ticks() >= etime) - return -2; /* timed out */ - schedule(); - } - first = 0; - } + if (ichar == '\n') { + putc('\n'); + buf[cls->eol_num] = '\0'; /* terminate the string */ + return 0; + } - ichar = getcmd_getch(); - ichar = cli_ch_process(cch, ichar); + switch (ichar) { + case CTL_CH('a'): + BEGINNING_OF_LINE(); + break; + case CTL_CH('c'): /* ^C - break */ + *buf = '\0'; /* discard input */ + return -EINTR; + case CTL_CH('f'): + if (cls->num < cls->eol_num) { + getcmd_putch(buf[cls->num]); + cls->num++; } - - /* ichar=0x0 when error occurs in U-Boot getc */ - if (!ichar) - continue; - - if (ichar == '\n') { - putc('\n'); - break; + break; + case CTL_CH('b'): + if (cls->num) { + getcmd_putch(CTL_BACKSPACE); + cls->num--; } - - switch (ichar) { - case CTL_CH('a'): - BEGINNING_OF_LINE(); - break; - case CTL_CH('c'): /* ^C - break */ - *buf = '\0'; /* discard input */ - return -1; - case CTL_CH('f'): - if (num < eol_num) { - getcmd_putch(buf[num]); - num++; - } - break; - case CTL_CH('b'): - if (num) { - getcmd_putch(CTL_BACKSPACE); - num--; + break; + case CTL_CH('d'): + if (cls->num < cls->eol_num) { + uint wlen; + + wlen = cls->eol_num - cls->num - 1; + if (wlen) { + memmove(&buf[cls->num], &buf[cls->num + 1], + wlen); + putnstr(buf + cls->num, wlen); } - break; - case CTL_CH('d'): - if (num < eol_num) { - wlen = eol_num - num - 1; - if (wlen) { - memmove(&buf[num], &buf[num+1], wlen); - putnstr(buf + num, wlen); - } - getcmd_putch(' '); - do { - getcmd_putch(CTL_BACKSPACE); - } while (wlen--); - eol_num--; - } - break; - case CTL_CH('k'): - ERASE_TO_EOL(); - break; - case CTL_CH('e'): - REFRESH_TO_EOL(); - break; - case CTL_CH('o'): - insert = !insert; - break; - case CTL_CH('x'): - case CTL_CH('u'): - BEGINNING_OF_LINE(); - ERASE_TO_EOL(); - break; - case DEL: - case DEL7: - case 8: - if (num) { - wlen = eol_num - num; - num--; - memmove(&buf[num], &buf[num+1], wlen); + getcmd_putch(' '); + do { getcmd_putch(CTL_BACKSPACE); - putnstr(buf + num, wlen); - getcmd_putch(' '); - do { - getcmd_putch(CTL_BACKSPACE); - } while (wlen--); - eol_num--; - } - break; - case CTL_CH('p'): - case CTL_CH('n'): - { + } while (wlen--); + cls->eol_num--; + } + break; + case CTL_CH('k'): + ERASE_TO_EOL(); + break; + case CTL_CH('e'): + REFRESH_TO_EOL(); + break; + case CTL_CH('o'): + cls->insert = !cls->insert; + break; + case CTL_CH('w'): + if (cls->num) { + uint base, wlen; + + for (base = cls->num - 1; + base >= 0 && buf[base] == ' ';) + base--; + for (; base > 0 && buf[base - 1] != ' ';) + base--; + + /* now delete chars from base to cls->num */ + wlen = cls->num - base; + cls->eol_num -= wlen; + memmove(&buf[base], &buf[cls->num], + cls->eol_num - base + 1); + cls->num = base; + getcmd_putchars(wlen, CTL_BACKSPACE); + puts(buf + base); + getcmd_putchars(wlen, ' '); + getcmd_putchars(wlen + cls->eol_num - cls->num, + CTL_BACKSPACE); + } + break; + case CTL_CH('x'): + case CTL_CH('u'): + BEGINNING_OF_LINE(); + ERASE_TO_EOL(); + break; + case DEL: + case DEL7: + case 8: + if (cls->num) { + uint wlen; + + wlen = cls->eol_num - cls->num; + cls->num--; + memmove(&buf[cls->num], &buf[cls->num + 1], wlen); + getcmd_putch(CTL_BACKSPACE); + putnstr(buf + cls->num, wlen); + getcmd_putch(' '); + do { + getcmd_putch(CTL_BACKSPACE); + } while (wlen--); + cls->eol_num--; + } + break; + case CTL_CH('p'): + case CTL_CH('n'): + if (cls->history) { char *hline; if (ichar == CTL_CH('p')) @@ -372,7 +371,7 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len, if (!hline) { getcmd_cbeep(); - continue; + break; } /* nuke the current line */ @@ -384,39 +383,106 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len, /* copy new line into place and display */ strcpy(buf, hline); - eol_num = strlen(buf); + cls->eol_num = strlen(buf); REFRESH_TO_EOL(); - continue; + break; } -#ifdef CONFIG_AUTO_COMPLETE - case '\t': { + break; + case '\t': + if (IS_ENABLED(CONFIG_AUTO_COMPLETE) && cls->cmd_complete) { int num2, col; /* do not autocomplete when in the middle */ - if (num < eol_num) { + if (cls->num < cls->eol_num) { getcmd_cbeep(); break; } - buf[num] = '\0'; - col = strlen(prompt) + eol_num; - num2 = num; - if (cmd_auto_complete(prompt, buf, &num2, &col)) { - col = num2 - num; - num += col; - eol_num += col; + buf[cls->num] = '\0'; + col = strlen(cls->prompt) + cls->eol_num; + num2 = cls->num; + if (cmd_auto_complete(cls->prompt, buf, &num2, &col)) { + col = num2 - cls->num; + cls->num += col; + cls->eol_num += col; } break; } -#endif - default: - cread_add_char(ichar, insert, &num, &eol_num, buf, - *len); - break; + fallthrough; + default: + cread_add_char(ichar, cls->insert, &cls->num, &cls->eol_num, + buf, cls->len); + break; + } + + /* + * keep the string terminated...if we added a char at the end then we + * want a \0 after it + */ + buf[cls->eol_num] = '\0'; + + return -EAGAIN; +} + +void cli_cread_init(struct cli_line_state *cls, char *buf, uint buf_size) +{ + int init_len = strlen(buf); + + memset(cls, '\0', sizeof(struct cli_line_state)); + cls->insert = true; + cls->buf = buf; + cls->len = buf_size; + + if (init_len) + cread_add_str(buf, init_len, 0, &cls->num, &cls->eol_num, buf, + buf_size); +} + +static int cread_line(const char *const prompt, char *buf, unsigned int *len, + int timeout) +{ + struct cli_ch_state s_cch, *cch = &s_cch; + struct cli_line_state s_cls, *cls = &s_cls; + char ichar; + int first = 1; + + cli_ch_init(cch); + cli_cread_init(cls, buf, *len); + cls->prompt = prompt; + cls->history = true; + cls->cmd_complete = true; + + while (1) { + int ret; + + /* Check for saved characters */ + ichar = cli_ch_process(cch, 0); + + if (!ichar) { + if (bootretry_tstc_timeout()) + return -2; /* timed out */ + if (first && timeout) { + u64 etime = endtick(timeout); + + while (!tstc()) { /* while no incoming data */ + if (get_ticks() >= etime) + return -2; /* timed out */ + schedule(); + } + first = 0; + } + + ichar = getcmd_getch(); + ichar = cli_ch_process(cch, ichar); } + + ret = cread_line_process_ch(cls, ichar); + if (ret == -EINTR) + return -1; + else if (!ret) + break; } - *len = eol_num; - buf[eol_num] = '\0'; /* lose the newline */ + *len = cls->eol_num; if (buf[0] && buf[0] != CREAD_HIST_CHAR) cread_add_to_hist(buf); @@ -425,6 +491,18 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len, return 0; } +#else /* !CONFIG_CMDLINE_EDITING */ + +static inline void hist_init(void) +{ +} + +static int cread_line(const char *const prompt, char *buf, unsigned int *len, + int timeout) +{ + return 0; +} + #endif /* CONFIG_CMDLINE_EDITING */ /****************************************************************************/ @@ -440,41 +518,22 @@ int cli_readline(const char *const prompt) return cli_readline_into_buffer(prompt, console_buffer, 0); } - -int cli_readline_into_buffer(const char *const prompt, char *buffer, - int timeout) +/** + * cread_line_simple() - Simple (small) command-line reader + * + * This supports only basic editing, with no cursor movement + * + * @prompt: Prompt to display + * @p: Text buffer to edit + * Return: length of text buffer, or -1 if input was cannncelled (Ctrl-C) + */ +static int cread_line_simple(const char *const prompt, char *p) { - char *p = buffer; -#ifdef CONFIG_CMDLINE_EDITING - unsigned int len = CONFIG_SYS_CBSIZE; - int rc; - static int initted; - - /* - * History uses a global array which is not - * writable until after relocation to RAM. - * Revert to non-history version if still - * running from flash. - */ - if (gd->flags & GD_FLG_RELOC) { - if (!initted) { - hist_init(); - initted = 1; - } - - if (prompt) - puts(prompt); - - rc = cread_line(prompt, p, &len, timeout); - return rc < 0 ? rc : len; - - } else { -#endif /* CONFIG_CMDLINE_EDITING */ char *p_buf = p; - int n = 0; /* buffer index */ - int plen = 0; /* prompt length */ - int col; /* output column cnt */ - char c; + int n = 0; /* buffer index */ + int plen = 0; /* prompt length */ + int col; /* output column cnt */ + char c; /* print prompt */ if (prompt) { @@ -528,14 +587,15 @@ int cli_readline_into_buffer(const char *const prompt, char *buffer, continue; default: - /* - * Must be a normal character then - */ - if (n < CONFIG_SYS_CBSIZE-2) { - if (c == '\t') { /* expand TABs */ -#ifdef CONFIG_AUTO_COMPLETE + /* Must be a normal character then */ + if (n >= CONFIG_SYS_CBSIZE - 2) { /* Buffer full */ + putc('\a'); + break; + } + if (c == '\t') { /* expand TABs */ + if (IS_ENABLED(CONFIG_AUTO_COMPLETE)) { /* - * if auto completion triggered just + * if auto-completion triggered just * continue */ *p = '\0'; @@ -545,29 +605,55 @@ int cli_readline_into_buffer(const char *const prompt, char *buffer, p = p_buf + n; /* reset */ continue; } -#endif - puts(tab_seq + (col & 07)); - col += 8 - (col & 07); - } else { - char __maybe_unused buf[2]; - - /* - * Echo input using puts() to force an - * LCD flush if we are using an LCD - */ - ++col; - buf[0] = c; - buf[1] = '\0'; - puts(buf); } - *p++ = c; - ++n; - } else { /* Buffer full */ - putc('\a'); + puts(tab_seq + (col & 07)); + col += 8 - (col & 07); + } else { + char __maybe_unused buf[2]; + + /* + * Echo input using puts() to force an LCD + * flush if we are using an LCD + */ + ++col; + buf[0] = c; + buf[1] = '\0'; + puts(buf); } + *p++ = c; + ++n; + break; } } -#ifdef CONFIG_CMDLINE_EDITING +} + +int cli_readline_into_buffer(const char *const prompt, char *buffer, + int timeout) +{ + char *p = buffer; + uint len = CONFIG_SYS_CBSIZE; + int rc; + static int initted; + + /* + * History uses a global array which is not + * writable until after relocation to RAM. + * Revert to non-history version if still + * running from flash. + */ + if (IS_ENABLED(CONFIG_CMDLINE_EDITING) && (gd->flags & GD_FLG_RELOC)) { + if (!initted) { + hist_init(); + initted = 1; + } + + if (prompt) + puts(prompt); + + rc = cread_line(prompt, p, &len, timeout); + return rc < 0 ? rc : len; + + } else { + return cread_line_simple(prompt, p); } -#endif } diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index e92a651416a..20b101acbb7 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -30,8 +30,9 @@ CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 48587270b81..4990e271c3f 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index b284494092a..239bb1f5cce 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -103,7 +103,7 @@ CONFIG_CMD_UBI=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_BOARD=y -CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA" +CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y diff --git a/doc/board/ti/j721s2_evm.rst b/doc/board/ti/j721s2_evm.rst new file mode 100644 index 00000000000..fec2acabe84 --- /dev/null +++ b/doc/board/ti/j721s2_evm.rst @@ -0,0 +1,341 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Manorit Chawdhry <m-chawdhry@ti.com> + +J721S2 and AM68 Platforms +========================= + +Introduction: +------------- +The J721S2 family of SoCs are part of K3 Multicore SoC architecture platform +targeting automotive applications. They are designed as a low power, high +performance and highly integrated device architecture, adding significant +enhancement on processing power, graphics capability, video and imaging +processing, virtualization and coherent memory support. + +The AM68 Starter Kit/Evaluation Module (EVM) is based on the J721S2 family +of SoCs. They are designed for machine vision, traffic monitoring, retail +automation, and factory automation. + +The device is partitioned into three functional domains, each containing +specific processing cores and peripherals: + +1. Wake-up (WKUP) domain: + * ARM Cortex-M4F processor, runs TI Foundational Security (TIFS) + +2. Microcontroller (MCU) domain: + * Dual core ARM Cortex-R5F processor, runs device management + and SoC early boot + +3. MAIN domain: + * Dual core 64-bit ARM Cortex-A72, runs HLOS + +More info can be found in TRM: https://www.ti.com/lit/pdf/spruj28 + +Platform information: + +* https://www.ti.com/tool/J721S2XSOMXEVM +* https://www.ti.com/tool/SK-AM68 + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. image:: img/boot_diagram_k3_current.svg + +- On this platform, "TI Foundational Security" (TIFS) functions as the + security enclave master while "Device Manager" (DM), also known as the + "TISCI server" in TI terminology, offers all the essential services. + +- As illustrated in the diagram above, R5 SPL manages power and clock + services independently before handing over control to "DM". The A72 or + the C7x (Aux core) software components request TIFS/DM to handle + security or device management services. + +Sources: +-------- + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_boot_sources + :end-before: .. k3_rst_include_end_boot_sources + +Build procedure: +---------------- +0. Setup the environment variables: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_desc + :end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_board_env_vars_desc + :end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_defn + :end-before: .. k3_rst_include_end_common_env_vars_defn +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig + $ export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig + $ export TFA_BOARD=generic + $ export TFA_EXTRA_ARGS="K3_USART=0x8" + $ # The following is not a typo, j784s4 is the OP-TEE platform for j721s2 + $ export OPTEE_PLATFORM=k3-j784s4 + $ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8" + +.. j721s2_evm_rst_include_start_build_steps + +1. Trusted Firmware-A: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_build_steps_tfa + :end-before: .. k3_rst_include_end_build_steps_tfa + + +2. OP-TEE: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_build_steps_optee + :end-before: .. k3_rst_include_end_build_steps_optee + +3. U-Boot: + +.. _j721s2_evm_rst_u_boot_r5: + +* 3.1 R5: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_build_steps_spl_r5 + :end-before: .. k3_rst_include_end_build_steps_spl_r5 + +.. _j721s2_evm_rst_u_boot_a72: + +* 3.2 A72: + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_build_steps_uboot + :end-before: .. k3_rst_include_end_build_steps_uboot +.. j721s2_evm_rst_include_end_build_steps + +Target Images +-------------- +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC +variant (GP, HS-FS, HS-SE) requires a different source for these files. + + - GP + + * tiboot3-j721s2-gp-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>` + * tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>` + + - HS-FS + + * tiboot3-j721s2-hs-fs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>` + * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>` + + - HS-SE + + * tiboot3-j721s2-hs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>` + * tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>` + +Image formats: +-------------- + +- tiboot3.bin + +.. image:: img/multi_cert_tiboot3.bin.svg + +- tispl.bin + +.. image:: img/dm_tispl.bin.svg + +R5 Memory Map: +-------------- + +.. list-table:: + :widths: 16 16 16 + :header-rows: 1 + + * - Region + - Start Address + - End Address + + * - SPL + - 0x41c00000 + - 0x41c40000 + + * - EMPTY + - 0x41c40000 + - 0x41c61f20 + + * - STACK + - 0x41c65f20 + - 0x41c61f20 + + * - Global data + - 0x41c65f20 + - 0x41c66000 + + * - Heap + - 0x41c66000 + - 0x41c76000 + + * - BSS + - 0x41c76000 + - 0x41c80000 + + * - DM DATA + - 0x41c80000 + - 0x41c84130 + + * - EMPTY + - 0x41c84130 + - 0x41cff9fc + + * - MCU Scratchpad + - 0x41cff9fc + - 0x41cffbfc + + * - ROM DATA + - 0x41cffbfc + - 0x41cfffff + +Switch Setting for Boot Mode +---------------------------- + +Boot Mode pins provide means to select the boot mode and options before the +device is powered up. After every POR, they are the main source to populate +the Boot Parameter Tables. + +Boot Mode Pins for J721S2-EVM +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following table shows some common boot modes used on J721S2 platform. +More details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruj28 under the `Boot Mode Pins` section. + +.. list-table:: Boot Modes + :widths: 16 16 16 + :header-rows: 1 + + * - Switch Label + - SW9: 12345678 + - SW8: 12345678 + + * - SD + - 00000000 + - 10000010 + + * - EMMC + - 01000000 + - 10000000 + + * - OSPI + - 01000000 + - 00000110 + + * - UART + - 01110000 + - 00000000 + + * - USB DFU + - 00100000 + - 10000000 + +For SW8 and SW9, the switch state in the "ON" position = 1. + +Boot Mode Pins for SK-AM68 +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following table shows some common boot modes used on AM68-SK platform. +More details can be found in the User Guide for AM68-SK: +https://www.ti.com/lit/pdf/spruj68 under the `Bootmode Settings` section. + +.. list-table:: Boot Modes + :widths: 16 16 + :header-rows: 1 + + * - Switch Label + - SW1: 1234 + + * - SD + - 0000 + + * - xSPI + - 0010 + + * - UART + - 1010 + + * - Ethernet + - 0100 + +For SW1, the switch state in the "ON" position = 1. + +Debugging U-Boot +---------------- + +See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. warning:: + + **OpenOCD support since**: v0.12.0 + + If the default package version of OpenOCD in your development + environment's distribution needs to be updated, it might be necessary to + build OpenOCD from the source. + +Debugging U-Boot on J721S2-EVM +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_XDS110 + :end-before: .. k3_rst_include_end_openocd_connect_XDS110 + +To start OpenOCD and connect to the board + +.. code-block:: bash + + openocd -f board/ti_j721s2evm.cfg + +Debugging U-Boot on SK-AM68 +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_cti20 + :end-before: .. k3_rst_include_end_openocd_connect_cti20 + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_cfg_external_intro + :end-before: .. k3_rst_include_end_openocd_cfg_external_intro + +For SK-AM68, the openocd_connect.cfg is as follows: + +.. code-block:: tcl + + # TUMPA example: + # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual + source [find interface/ftdi/tumpa.cfg] + + transport select jtag + + # default JTAG configuration has only SRST and no TRST + reset_config srst_only srst_push_pull + + # delay after SRST goes inactive + adapter srst delay 20 + + if { ![info exists SOC] } { + # Set the SoC of interest + set SOC j721s2 + } + + source [find target/ti_k3.cfg] + + ftdi tdo_sample_edge falling + + # Speeds for FT2232H are in multiples of 2, and 32MHz is tops + # max speed we seem to achieve is ~20MHz.. so we pick 16MHz + adapter speed 16000 diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 8b5c1a88ed0..89d70db8864 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -37,6 +37,7 @@ K3 Based SoCs am65x_evm j7200_evm j721e_evm + j721s2_evm Boot Flow Overview ------------------ diff --git a/doc/develop/cedit.rst b/doc/develop/cedit.rst index 63dff9d3f14..82305b921f0 100644 --- a/doc/develop/cedit.rst +++ b/doc/develop/cedit.rst @@ -162,7 +162,8 @@ Cedit provides several options for persistent settings: - Writing an FDT file to a filesystem - Writing to U-Boot's environment variables, which are then typically stored in a persistent manner -- Writing to CMOS RAM registers (common on x86 machines) +- Writing to CMOS RAM registers (common on x86 machines). Note that textline + objects do not appear in CMOS RAM registers For now, reading and writing settings is not automatic. See the :doc:`../usage/cmd/cedit` for how to do this on the command line or in a diff --git a/doc/develop/expo.rst b/doc/develop/expo.rst index f13761995d3..c87b6ec8128 100644 --- a/doc/develop/expo.rst +++ b/doc/develop/expo.rst @@ -63,9 +63,12 @@ select the item), label and description. All three are shown in a single line within the menu. Items can also have a preview image, which is shown when the item is highlighted. -All components have a name. This is purely for debugging, so it is easy to see -what object is referred to. Of course the ID numbers can help as well, but they -are less easy to distinguish. +A `textline object` contains a label and an editable string. + +All components have a name. This is mostly for debugging, so it is easy to see +what object is referred to, although the name is also used for saving values. +Of course the ID numbers can help as well, but they are less easy to +distinguish. While the expo implementation provides support for handling keypresses and rendering on the display or serial port, it does not actually deal with reading @@ -136,7 +139,9 @@ this is to use `cli_ch_process()`, since it handles conversion of escape sequences into keys. However, expo has some special menu-key codes for navigating the interface. These are defined in `enum bootmenu_key` and include `BKEY_UP` for moving up and `BKEY_SELECT` for selecting an item. You can use -`bootmenu_conv_key()` to convert an ASCII key into one of these. +`bootmenu_conv_key()` to convert an ASCII key into one of these, but if it +returns a value >= `BKEY_FIRST_EXTRA` then you should pass the unmodified ASCII +key to the expo, since it may be used by textline objects. Once a keypress is decoded, call `expo_send_key()` to send it to the expo. This may cause an update to the expo state and may produce an action. @@ -312,6 +317,9 @@ type "menu" Menu containing items which can be selected by the user + "textline" + A line of text which can be edited + id type: u32, required @@ -362,6 +370,26 @@ desc-label / desc-label-id Specifies the description for each item in the menu. These are currently only intended for use in simple mode. +Textline nodes have the following additional properties: + +label / label-id + type: string / u32, required + + Specifies the label of the textline. This is shown to the left of the area + for this textline. + +edit-id + type: u32, required + + Specifies the ID of the of the editable text object. This can be used to + obtain the text from the textline + +max-chars: + type: u32, required + + Specifies the maximum number of characters permitted to be in the textline. + The user will be prevented from adding more. + Expo layout ~~~~~~~~~~~ @@ -401,6 +429,9 @@ strings are provided inline in the nodes where they are used. ID_AC_ON, ID_AC_MEMORY, + ID_MACHINE_NAME, + ID_MACHINE_NAME_EDIT, + ID_DYNAMIC_START, */ @@ -447,6 +478,13 @@ strings are provided inline in the nodes where they are used. item-id = <ID_AC_OFF ID_AC_ON ID_AC_MEMORY>; }; + + machine-name { + id = <ID_MACHINE_NAME>; + type = "textline"; + max-chars = <20>; + title = "Machine name"; + edit-id = <ID_MACHINE_NAME_EDIT>; }; }; @@ -474,7 +512,7 @@ Some ideas for future work: - Image formats other than BMP - Use of ANSI sequences to control a serial terminal - Colour selection -- Support for more widgets, e.g. text, numeric, radio/option +- Support for more widgets, e.g. numeric, radio/option - Mouse support - Integrate Nuklear, NxWidgets or some other library for a richer UI - Optimise rendering by only updating the display with changes since last render diff --git a/doc/mkimage.1 b/doc/mkimage.1 index c1903896f3d..d0a038a880a 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -281,10 +281,8 @@ properties. A \(oqdata-offset\(cq of 0 indicates that it starts in the first .BI \-B " alignment" .TQ .BI \-\-alignment " alignment" -The alignment, in hexadecimal, that the FDT structure will be aligned -to. With -.BR \-E , -also specifies the alignment for the external data. +The alignment, in hexadecimal, that external data will be aligned to. This +option only has an effect when \-E is specified. . .TP .BI \-p " external-position" diff --git a/doc/usage/cmd/history.rst b/doc/usage/cmd/history.rst new file mode 100644 index 00000000000..33d3fcd6247 --- /dev/null +++ b/doc/usage/cmd/history.rst @@ -0,0 +1,67 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +history command +=============== + +Synopis +------- + +:: + + history + +Description +----------- + +The *history* command shows a list of previously entered commands on the +command line. When U-Boot starts, this it is initially empty. Each new command +entered is added to the list. + +Normally these commands can be accessed by pressing the `up arrow` and +`down arrow` keys, which cycle through the list. The `history` command provides +a simple way to view the list. + +Example +------- + +This example shows entering three commands, then `history`. Note that `history` +itself is added to the list. + +:: + + => bootflow scan -l + Scanning for bootflows in all bootdevs + Seq Method State Uclass Part Name Filename + --- ----------- ------ -------- ---- ------------------------ ---------------- + Scanning global bootmeth 'firmware0': + Hunting with: simple_bus + Found 2 extension board(s). + Scanning bootdev 'mmc2.bootdev': + Scanning bootdev 'mmc1.bootdev': + 0 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf + No more bootdevs + --- ----------- ------ -------- ---- ------------------------ ---------------- + (1 bootflow, 1 valid) + => bootflow select 0 + => bootflow info + Name: mmc1.bootdev.part_1 + Device: mmc1.bootdev + Block dev: mmc1.blk + Method: extlinux + State: ready + Partition: 1 + Subdir: (none) + Filename: /extlinux/extlinux.conf + Buffer: aebdea0 + Size: 253 (595 bytes) + OS: Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl) + Cmdline: (none) + Logo: (none) + FDT: <NULL> + Error: 0 + => history + bootflow scan -l + bootflow select 0 + bootflow info + history + => diff --git a/doc/usage/index.rst b/doc/usage/index.rst index fa702920faa..98b4719c408 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -67,6 +67,7 @@ Shell commands cmd/fwu_mdata cmd/gpio cmd/gpt + cmd/history cmd/host cmd/imxtract cmd/load diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 2e004beca2f..c473643603a 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -773,7 +773,6 @@ static struct clk_ops versal_clk_ops = { static const struct udevice_id versal_clk_ids[] = { { .compatible = "xlnx,versal-clk" }, - { .compatible = "xlnx,versal-net-clk" }, { } }; diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index ba925fa3c48..10f7240f77a 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -11,6 +11,7 @@ #include <errno.h> #include <soc.h> #include <clk-uclass.h> +#include <k3-avs.h> #include "k3-clk.h" #define PLL_MIN_FREQ 800000000 @@ -242,7 +243,11 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) const struct clk_ops *ops; ulong new_rate, rem; ulong diff, new_diff; + int freq_scale_up = rate >= ti_clk_get_rate(clk) ? 1 : 0; + if (IS_ENABLED(CONFIG_K3_AVS0) && freq_scale_up) + k3_avs_notify_freq(data->map[clk->id].dev_id, + data->map[clk->id].clk_id, rate); /* * We must propagate rate change to parent if current clock type * does not allow setting it. @@ -339,6 +344,10 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) } } + if (IS_ENABLED(CONFIG_K3_AVS0) && !freq_scale_up) + k3_avs_notify_freq(data->map[clk->id].dev_id, + data->map[clk->id].clk_id, rate); + return new_rate; } diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c index 74df5a397bf..8fc3254c996 100644 --- a/drivers/clk/ti/clk-sci.c +++ b/drivers/clk/ti/clk-sci.c @@ -91,12 +91,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate) const struct ti_sci_handle *sci = data->sci; const struct ti_sci_clk_ops *cops = &sci->ops.clk_ops; int ret; + int freq_scale_up = rate >= ti_sci_clk_get_rate(clk) ? 1 : 0; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); -#ifdef CONFIG_K3_AVS0 - k3_avs_notify_freq(clk->id, clk->data, rate); -#endif + if (IS_ENABLED(CONFIG_K3_AVS0) && freq_scale_up) + k3_avs_notify_freq(clk->id, clk->data, rate); ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX); if (ret) { @@ -104,6 +104,9 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate) return ret; } + if (IS_ENABLED(CONFIG_K3_AVS0) && !freq_scale_up) + k3_avs_notify_freq(clk->id, clk->data, rate); + return rate; } diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index 75e2f6a4215..485586989c8 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -85,27 +85,41 @@ static int mtd_block_op(enum dfu_op op, struct dfu_entity *dfu, while (remaining) { if (erase_op.addr + remaining > lim) { - printf("Limit reached 0x%llx while erasing at offset 0x%llx\n", - lim, off); + printf("Limit reached 0x%llx while erasing at offset 0x%llx, remaining 0x%llx\n", + lim, erase_op.addr, remaining); return -EIO; } + /* Skip the block if it is bad, don't erase it again */ + ret = mtd_block_isbad(mtd, erase_op.addr); + if (ret) { + printf("Skipping %s at 0x%08llx\n", + ret == 1 ? "bad block" : "bbt reserved", + erase_op.addr); + erase_op.addr += mtd->erasesize; + continue; + } + ret = mtd_erase(mtd, &erase_op); if (ret) { - /* Abort if its not a bad block error */ - if (ret != -EIO) { - printf("Failure while erasing at offset 0x%llx\n", - erase_op.fail_addr); - return 0; + /* If this is not -EIO, we have no idea what to do. */ + if (ret == -EIO) { + printf("Marking bad block at 0x%08llx (%d)\n", + erase_op.fail_addr, ret); + ret = mtd_block_markbad(mtd, erase_op.addr); + } + /* Abort if it is not -EIO or can't mark bad */ + if (ret) { + printf("Failure while erasing at offset 0x%llx (%d)\n", + erase_op.fail_addr, ret); + return ret; } - printf("Skipping bad block at 0x%08llx\n", - erase_op.addr); } else { remaining -= mtd->erasesize; } - /* Continue erase behind bad block */ + /* Continue erase behind the current block */ erase_op.addr += mtd->erasesize; } } diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index b1f201fb18b..2656f5fc5ec 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2015 - 2016, Xilinx, Inc, * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ #include <console.h> diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index 6c65b187e86..3051de4f7ef 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o +spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 4ee11e812d8..597b088ca7e 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -17,6 +17,7 @@ #include <linux/mtd/spinand.h> #include <linux/of.h> #include <linux/slab.h> +#include <linux/string.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #else @@ -326,6 +327,13 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand, u16 column = 0; int ret; + /* + * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset + * the cache content to 0xFF (depends on vendor implementation), so we + * must fill the page cache entirely even if we only want to program + * the data portion of the page, otherwise we might corrupt the BBM or + * user data previously programmed in OOB area. + */ memset(spinand->databuf, 0xff, nanddev_page_size(nand) + nanddev_per_page_oobsize(nand)); @@ -452,9 +460,11 @@ out: return status & STATUS_BUSY ? -ETIMEDOUT : 0; } -static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf) +static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, + u8 ndummy, u8 *buf) { - struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf, + struct spi_mem_op op = SPINAND_READID_OP(naddr, ndummy, + spinand->scratchbuf, SPINAND_MAX_ID_LEN); int ret; @@ -596,12 +606,12 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from, if (ret == -EBADMSG) { ecc_failed = true; mtd->ecc_stats.failed++; - ret = 0; } else { mtd->ecc_stats.corrected += ret; max_bitflips = max_t(unsigned int, max_bitflips, ret); } + ret = 0; ops->retlen += iter.req.datalen; ops->oobretlen += iter.req.ooblen; } @@ -667,16 +677,9 @@ static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) .oobbuf.in = marker, .mode = MTD_OPS_RAW, }; - int ret; - - ret = spinand_select_target(spinand, pos->target); - if (ret) - return ret; - - ret = spinand_read_page(spinand, &req, false); - if (ret) - return ret; + spinand_select_target(spinand, pos->target); + spinand_read_page(spinand, &req, false); if (marker[0] != 0xff || marker[1] != 0xff) return true; @@ -720,6 +723,10 @@ static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) if (ret) return ret; + ret = spinand_write_enable_op(spinand); + if (ret) + return ret; + return spinand_write_page(spinand, &req); } @@ -808,21 +815,6 @@ static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs) return ret; } -const struct spi_mem_op * -spinand_find_supported_op(struct spinand_device *spinand, - const struct spi_mem_op *ops, - unsigned int nops) -{ - unsigned int i; - - for (i = 0; i < nops; i++) { - if (spi_mem_supports_op(spinand->slave, &ops[i])) - return &ops[i]; - } - - return NULL; -} - static const struct nand_ops spinand_ops = { .erase = spinand_erase, .markbad = spinand_markbad, @@ -833,28 +825,67 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &gigadevice_spinand_manufacturer, ¯onix_spinand_manufacturer, µn_spinand_manufacturer, + ¶gon_spinand_manufacturer, &toshiba_spinand_manufacturer, &winbond_spinand_manufacturer, }; -static int spinand_manufacturer_detect(struct spinand_device *spinand) +static int spinand_manufacturer_match(struct spinand_device *spinand, + enum spinand_readid_method rdid_method) { + u8 *id = spinand->id.data; unsigned int i; int ret; for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) { - ret = spinand_manufacturers[i]->ops->detect(spinand); - if (ret > 0) { - spinand->manufacturer = spinand_manufacturers[i]; - return 0; - } else if (ret < 0) { - return ret; - } - } + const struct spinand_manufacturer *manufacturer = + spinand_manufacturers[i]; + + if (id[0] != manufacturer->id) + continue; + + ret = spinand_match_and_init(spinand, + manufacturer->chips, + manufacturer->nchips, + rdid_method); + if (ret < 0) + continue; + spinand->manufacturer = manufacturer; + return 0; + } return -ENOTSUPP; } +static int spinand_id_detect(struct spinand_device *spinand) +{ + u8 *id = spinand->id.data; + int ret; + + ret = spinand_read_id_op(spinand, 0, 0, id); + if (ret) + return ret; + ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE); + if (!ret) + return 0; + + ret = spinand_read_id_op(spinand, 1, 0, id); + if (ret) + return ret; + ret = spinand_manufacturer_match(spinand, + SPINAND_READID_METHOD_OPCODE_ADDR); + if (!ret) + return 0; + + ret = spinand_read_id_op(spinand, 0, 1, id); + if (ret) + return ret; + ret = spinand_manufacturer_match(spinand, + SPINAND_READID_METHOD_OPCODE_DUMMY); + + return ret; +} + static int spinand_manufacturer_init(struct spinand_device *spinand) { if (spinand->manufacturer->ops->init) @@ -910,9 +941,9 @@ spinand_select_op_variant(struct spinand_device *spinand, * @spinand: SPI NAND object * @table: SPI NAND device description table * @table_size: size of the device description table + * @rdid_method: read id method to match * - * Should be used by SPI NAND manufacturer drivers when they want to find a - * match between a device ID retrieved through the READ_ID command and an + * Match between a device ID retrieved through the READ_ID command and an * entry in the SPI NAND description table. If a match is found, the spinand * object will be initialized with information provided by the matching * spinand_info entry. @@ -921,8 +952,10 @@ spinand_select_op_variant(struct spinand_device *spinand, */ int spinand_match_and_init(struct spinand_device *spinand, const struct spinand_info *table, - unsigned int table_size, u8 devid) + unsigned int table_size, + enum spinand_readid_method rdid_method) { + u8 *id = spinand->id.data; struct nand_device *nand = spinand_to_nand(spinand); unsigned int i; @@ -930,13 +963,17 @@ int spinand_match_and_init(struct spinand_device *spinand, const struct spinand_info *info = &table[i]; const struct spi_mem_op *op; - if (devid != info->devid) + if (rdid_method != info->devid.method) + continue; + + if (memcmp(id + 1, info->devid.id, info->devid.len)) continue; nand->memorg = table[i].memorg; nand->eccreq = table[i].eccreq; spinand->eccinfo = table[i].eccinfo; spinand->flags = table[i].flags; + spinand->id.len = 1 + table[i].devid.len; spinand->select_target = table[i].select_target; op = spinand_select_op_variant(spinand, @@ -972,13 +1009,7 @@ static int spinand_detect(struct spinand_device *spinand) if (ret) return ret; - ret = spinand_read_id_op(spinand, spinand->id.data); - if (ret) - return ret; - - spinand->id.len = SPINAND_MAX_ID_LEN; - - ret = spinand_manufacturer_detect(spinand); + ret = spinand_id_detect(spinand); if (ret) { dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n", spinand->id.data[0], spinand->id.data[1], @@ -1083,11 +1114,11 @@ static int spinand_init(struct spinand_device *spinand) for (i = 0; i < nand->memorg.ntargets; i++) { ret = spinand_select_target(spinand, i); if (ret) - goto err_free_bufs; + goto err_manuf_cleanup; ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); if (ret) - goto err_free_bufs; + goto err_manuf_cleanup; } ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index a2c93486f49..f2ecf47f8d4 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -7,13 +7,13 @@ */ #ifndef __UBOOT__ -#include <malloc.h> #include <linux/device.h> #include <linux/kernel.h> #endif #include <linux/mtd/spinand.h> #define SPINAND_MFR_GIGADEVICE 0xC8 + #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4) #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4) @@ -22,8 +22,12 @@ #define GD5FXGQXXEXXG_REG_STATUS2 0xf0 -/* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */ -static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants, +#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4) +#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4) +#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4) +#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4) + +static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), @@ -31,14 +35,13 @@ static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */ -static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants, - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), +static SPINAND_OP_VARIANTS(read_cache_variants_f, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); static SPINAND_OP_VARIANTS(write_cache_variants, SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), @@ -48,7 +51,65 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); -static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section, +static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 3) + return -ERANGE; + + region->offset = (16 * section) + 8; + region->length = 8; + + return 0; +} + +static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 3) + return -ERANGE; + + if (section) { + region->offset = 16 * section; + region->length = 8; + } else { + /* section 0 has one byte reserved for bad block mark */ + region->offset = 1; + region->length = 7; + } + return 0; +} + +static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = { + .ecc = gd5fxgq4xa_ooblayout_ecc, + .rfree = gd5fxgq4xa_ooblayout_free, +}; + +static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (status & STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS: + /* 1-7 bits are flipped. return the maximum. */ + return 7; + + case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS: + return 8; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + default: + break; + } + + return -EINVAL; +} + +static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { if (section) @@ -60,7 +121,7 @@ static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section, return 0; } -static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section, +static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { if (section) @@ -73,7 +134,42 @@ static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section, return 0; } -static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand, +/* Valid for Q4/Q5 and Q6 (untested) devices */ +static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = { + .ecc = gd5fxgqx_variant2_ooblayout_ecc, + .rfree = gd5fxgqx_variant2_ooblayout_free, +}; + +static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + if (section) + return -ERANGE; + + oobregion->offset = 128; + oobregion->length = 128; + + return 0; +} + +static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + if (section) + return -ERANGE; + + oobregion->offset = 1; + oobregion->length = 127; + + return 0; +} + +static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = { + .ecc = gd5fxgq4xc_ooblayout_256_ecc, + .rfree = gd5fxgq4xc_ooblayout_256_free, +}; + +static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, u8 status) { u8 status2; @@ -152,59 +248,116 @@ static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, return -EINVAL; } -static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = { - .ecc = gd5fxgqxxexxg_ooblayout_ecc, - .rfree = gd5fxgqxxexxg_ooblayout_free, -}; +static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) { + case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS: + return 0; + + case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS: + return 3; + + case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */ + return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2; + } + + return -EINVAL; +} static const struct spinand_info gigadevice_spinand_table[] = { - SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("GD5F1GQ4xA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F2GQ4xA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants, + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), - 0, - SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout, - gd5fxgq4xexxg_ecc_get_status)), - SPINAND_INFO("GD5F1GQ5UExxG", 0x51, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F4GQ4xA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4), + NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F4GQ4RC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, + gd5fxgq4ufxxg_ecc_get_status)), + SPINAND_INFO("GD5F4GQ4UC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, + gd5fxgq4ufxxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UFxxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4ufxxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ5UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(4, 512), - SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), - 0, - SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout, + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, gd5fxgq5xexxg_ecc_get_status)), }; -static int gigadevice_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * For GD NANDs, There is an address byte needed to shift in before IDs - * are read out, so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_GIGADEVICE) - return 0; - - ret = spinand_match_and_init(spinand, gigadevice_spinand_table, - ARRAY_SIZE(gigadevice_spinand_table), - id[2]); - if (ret) - return ret; - - return 1; -} - static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { - .detect = gigadevice_spinand_detect, }; const struct spinand_manufacturer gigadevice_spinand_manufacturer = { .id = SPINAND_MFR_GIGADEVICE, .name = "GigaDevice", + .chips = gigadevice_spinand_table, + .nchips = ARRAY_SIZE(gigadevice_spinand_table), .ops = &gigadevice_spinand_manuf_ops, }; diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 6d643a8000d..86bffc2800b 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -6,7 +6,6 @@ */ #ifndef __UBOOT__ -#include <malloc.h> #include <linux/device.h> #include <linux/kernel.h> #endif @@ -16,7 +15,6 @@ #define SPINAND_MFR_MACRONIX 0xC2 #define MACRONIX_ECCSR_MASK 0x0F - static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), @@ -62,7 +60,6 @@ static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr) SPI_MEM_OP_DATA_IN(1, eccsr, 1)); int ret = spi_mem_exec_op(spinand->slave, &op); - if (ret) return ret; @@ -105,8 +102,9 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, } static const struct spinand_info macronix_spinand_table[] = { - SPINAND_INFO("MX35LF1GE4AB", 0x12, - NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + SPINAND_INFO("MX35LF1GE4AB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -114,16 +112,65 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35LF2GE4AB", 0x22, - NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), + SPINAND_INFO("MX35LF2GE4AB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), - SPINAND_INFO("MX35UF4GE4AD", 0xb7, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + SPINAND_INFO("MX35LF2GE4AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35LF4GE4AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37), + NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35LF1G24AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_INFO("MX35LF2G24AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_INFO("MX35LF4G24AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_INFO("MX31LF1GE4BC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -131,8 +178,9 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35UF2GE4AD", 0xa6, - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + SPINAND_INFO("MX31UF1GE4BC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -140,8 +188,10 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35UF2GE4AC", 0xa2, - NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), + + SPINAND_INFO("MX35LF2G14AC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -149,8 +199,9 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35UF1GE4AD", 0x96, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("MX35UF4G24AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -158,8 +209,89 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35UF1GE4AC", 0x92, - NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + SPINAND_INFO("MX35UF4GE4AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2G14AC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2G24AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2GE4AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2GE4AC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1G14AC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1G24AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1GE4AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1GE4AC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -170,33 +302,13 @@ static const struct spinand_info macronix_spinand_table[] = { }; -static int macronix_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * Macronix SPI NAND read ID needs a dummy byte, so the first byte in - * raw_id is garbage. - */ - if (id[1] != SPINAND_MFR_MACRONIX) - return 0; - - ret = spinand_match_and_init(spinand, macronix_spinand_table, - ARRAY_SIZE(macronix_spinand_table), - id[2]); - if (ret) - return ret; - - return 1; -} - static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = { - .detect = macronix_spinand_detect, }; const struct spinand_manufacturer macronix_spinand_manufacturer = { .id = SPINAND_MFR_MACRONIX, .name = "Macronix", + .chips = macronix_spinand_table, + .nchips = ARRAY_SIZE(macronix_spinand_table), .ops = ¯onix_spinand_manuf_ops, }; diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 6bacf14aafe..b538213ed8e 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -7,11 +7,9 @@ */ #ifndef __UBOOT__ -#include <malloc.h> #include <linux/device.h> #include <linux/kernel.h> #endif -#include <linux/bitops.h> #include <linux/mtd/spinand.h> #define SPINAND_MFR_MICRON 0x2c @@ -32,7 +30,7 @@ #define MICRON_SELECT_DIE(x) ((x) << 6) -static SPINAND_OP_VARIANTS(read_cache_variants, +static SPINAND_OP_VARIANTS(quadio_read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), @@ -40,14 +38,27 @@ static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -static SPINAND_OP_VARIANTS(write_cache_variants, +static SPINAND_OP_VARIANTS(x4_write_cache_variants, SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), SPINAND_PROG_LOAD(true, 0, NULL, 0)); -static SPINAND_OP_VARIANTS(update_cache_variants, +static SPINAND_OP_VARIANTS(x4_update_cache_variants, SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); +/* Micron MT29F2G01AAAED Device */ +static SPINAND_OP_VARIANTS(x4_read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(x1_write_cache_variants, + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(x1_update_cache_variants, + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { @@ -78,6 +89,47 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = { .rfree = micron_8_ooblayout_free, }; +static int micron_4_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + struct spinand_device *spinand = mtd_to_spinand(mtd); + + if (section >= spinand->base.memorg.pagesize / + mtd->ecc_step_size) + return -ERANGE; + + region->offset = (section * 16) + 8; + region->length = 8; + + return 0; +} + +static int micron_4_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + struct spinand_device *spinand = mtd_to_spinand(mtd); + + if (section >= spinand->base.memorg.pagesize / + mtd->ecc_step_size) + return -ERANGE; + + if (section) { + region->offset = 16 * section; + region->length = 8; + } else { + /* section 0 has two bytes reserved for the BBM */ + region->offset = 2; + region->length = 6; + } + + return 0; +} + +static const struct mtd_ooblayout_ops micron_4_ooblayout = { + .ecc = micron_4_ooblayout_ecc, + .rfree = micron_4_ooblayout_free, +}; + static int micron_select_target(struct spinand_device *spinand, unsigned int target) { @@ -120,120 +172,119 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand, static const struct spinand_info micron_spinand_table[] = { /* M79A 2Gb 3.3V */ - SPINAND_INFO("MT29F2G01ABAGD", 0x24, - NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), + SPINAND_INFO("MT29F2G01ABAGD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), /* M79A 2Gb 1.8V */ - SPINAND_INFO("MT29F2G01ABBGD", 0x25, - NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), + SPINAND_INFO("MT29F2G01ABBGD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), /* M78A 1Gb 3.3V */ - SPINAND_INFO("MT29F1G01ABAFD", 0x14, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("MT29F1G01ABAFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), /* M78A 1Gb 1.8V */ - SPINAND_INFO("MT29F1G01ABAFD", 0x15, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("MT29F1G01ABAFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), /* M79A 4Gb 3.3V */ - SPINAND_INFO("MT29F4G01ADAGD", 0x36, - NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2), + SPINAND_INFO("MT29F4G01ADAGD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36), + NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status), SPINAND_SELECT_TARGET(micron_select_target)), /* M70A 4Gb 3.3V */ - SPINAND_INFO("MT29F4G01ABAFD", 0x34, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + SPINAND_INFO("MT29F4G01ABAFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), /* M70A 4Gb 1.8V */ - SPINAND_INFO("MT29F4G01ABBFD", 0x35, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + SPINAND_INFO("MT29F4G01ABBFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), /* M70A 8Gb 3.3V */ - SPINAND_INFO("MT29F8G01ADAFD", 0x46, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), + SPINAND_INFO("MT29F8G01ADAFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status), SPINAND_SELECT_TARGET(micron_select_target)), /* M70A 8Gb 1.8V */ - SPINAND_INFO("MT29F8G01ADBFD", 0x47, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), + SPINAND_INFO("MT29F8G01ADBFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, + &x4_write_cache_variants, + &x4_update_cache_variants), SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status), SPINAND_SELECT_TARGET(micron_select_target)), + /* M69A 2Gb 3.3V */ + SPINAND_INFO("MT29F2G01AAAED", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9F), + NAND_MEMORG(1, 2048, 64, 64, 2048, 80, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&x4_read_cache_variants, + &x1_write_cache_variants, + &x1_update_cache_variants), + 0, + SPINAND_ECCINFO(µn_4_ooblayout, NULL)), }; -static int micron_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * Micron SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_MICRON) - return 0; - - ret = spinand_match_and_init(spinand, micron_spinand_table, - ARRAY_SIZE(micron_spinand_table), id[2]); - if (ret) - return ret; - - return 1; -} - static int micron_spinand_init(struct spinand_device *spinand) { /* @@ -248,12 +299,13 @@ static int micron_spinand_init(struct spinand_device *spinand) } static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { - .detect = micron_spinand_detect, .init = micron_spinand_init, }; const struct spinand_manufacturer micron_spinand_manufacturer = { .id = SPINAND_MFR_MICRON, .name = "Micron", + .chips = micron_spinand_table, + .nchips = ARRAY_SIZE(micron_spinand_table), .ops = µn_spinand_manuf_ops, }; diff --git a/drivers/mtd/nand/spi/paragon.c b/drivers/mtd/nand/spi/paragon.c new file mode 100644 index 00000000000..0c123930f14 --- /dev/null +++ b/drivers/mtd/nand/spi/paragon.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Jeff Kletsky + * + * Author: Jeff Kletsky <git-commits@allycomm.com> + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/mtd/spinand.h> + + +#define SPINAND_MFR_PARAGON 0xa1 + + +#define PN26G0XA_STATUS_ECC_BITMASK (3 << 4) + +#define PN26G0XA_STATUS_ECC_NONE_DETECTED (0 << 4) +#define PN26G0XA_STATUS_ECC_1_7_CORRECTED (1 << 4) +#define PN26G0XA_STATUS_ECC_ERRORED (2 << 4) +#define PN26G0XA_STATUS_ECC_8_CORRECTED (3 << 4) + + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + + +static int pn26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 3) + return -ERANGE; + + region->offset = 6 + (15 * section); /* 4 BBM + 2 user bytes */ + region->length = 13; + + return 0; +} + +static int pn26g0xa_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 4) + return -ERANGE; + + if (section == 4) { + region->offset = 64; + region->length = 64; + } else { + region->offset = 4 + (15 * section); + region->length = 2; + } + + return 0; +} + +static int pn26g0xa_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (status & PN26G0XA_STATUS_ECC_BITMASK) { + case PN26G0XA_STATUS_ECC_NONE_DETECTED: + return 0; + + case PN26G0XA_STATUS_ECC_1_7_CORRECTED: + return 7; /* Return upper limit by convention */ + + case PN26G0XA_STATUS_ECC_8_CORRECTED: + return 8; + + case PN26G0XA_STATUS_ECC_ERRORED: + return -EBADMSG; + + default: + break; + } + + return -EINVAL; +} + +static const struct mtd_ooblayout_ops pn26g0xa_ooblayout = { + .ecc = pn26g0xa_ooblayout_ecc, + .rfree = pn26g0xa_ooblayout_free, +}; + + +static const struct spinand_info paragon_spinand_table[] = { + SPINAND_INFO("PN26G01A", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe1), + NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&pn26g0xa_ooblayout, + pn26g0xa_ecc_get_status)), + SPINAND_INFO("PN26G02A", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe2), + NAND_MEMORG(1, 2048, 128, 64, 2048, 41, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&pn26g0xa_ooblayout, + pn26g0xa_ecc_get_status)), +}; + +static const struct spinand_manufacturer_ops paragon_spinand_manuf_ops = { +}; + +const struct spinand_manufacturer paragon_spinand_manufacturer = { + .id = SPINAND_MFR_PARAGON, + .name = "Paragon", + .chips = paragon_spinand_table, + .nchips = ARRAY_SIZE(paragon_spinand_table), + .ops = ¶gon_spinand_manuf_ops, +}; diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c index c2cd3b426b3..b9908e79271 100644 --- a/drivers/mtd/nand/spi/toshiba.c +++ b/drivers/mtd/nand/spi/toshiba.c @@ -7,13 +7,13 @@ */ #ifndef __UBOOT__ -#include <malloc.h> #include <linux/device.h> #include <linux/kernel.h> #endif #include <linux/bug.h> #include <linux/mtd/spinand.h> +/* Kioxia is new name of Toshiba memory. */ #define SPINAND_MFR_TOSHIBA 0x98 #define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4) @@ -31,7 +31,7 @@ static SPINAND_OP_VARIANTS(update_cache_x4_variants, SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); -/** +/* * Backward compatibility for 1st generation Serial NAND devices * which don't support Quad Program Load operation. */ @@ -42,7 +42,7 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD(false, 0, NULL, 0)); static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) + struct mtd_oob_region *region) { if (section > 0) return -ERANGE; @@ -54,7 +54,7 @@ static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section, } static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) + struct mtd_oob_region *region) { if (section > 0) return -ERANGE; @@ -72,7 +72,7 @@ static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = { }; static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand, - u8 status) + u8 status) { struct nand_device *nand = spinand_to_nand(spinand); u8 mbf = 0; @@ -111,8 +111,9 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand, static const struct spinand_info toshiba_spinand_table[] = { /* 3.3V 1Gb (1st generation) */ - SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("TC58CVG0S3HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -121,8 +122,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 2Gb (1st generation) */ - SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB, - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + SPINAND_INFO("TC58CVG1S3HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -131,8 +133,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 4Gb (1st generation) */ - SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + SPINAND_INFO("TC58CVG2S0HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -141,8 +144,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 1Gb (1st generation) */ - SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("TC58CYG0S3HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -151,8 +155,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 2Gb (1st generation) */ - SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB, - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + SPINAND_INFO("TC58CYG1S3HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -161,8 +166,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 4Gb (1st generation) */ - SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + SPINAND_INFO("TC58CYG2S0HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -176,8 +182,9 @@ static const struct spinand_info toshiba_spinand_table[] = { * QE_BIT. */ /* 3.3V 1Gb (2nd generation) */ - SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("TC58CVG0S3HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_x4_variants, @@ -186,8 +193,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 2Gb (2nd generation) */ - SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB, - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + SPINAND_INFO("TC58CVG1S3HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_x4_variants, @@ -196,8 +204,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 4Gb (2nd generation) */ - SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + SPINAND_INFO("TC58CVG2S0HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_x4_variants, @@ -206,8 +215,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 8Gb (2nd generation) */ - SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4, - NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), + SPINAND_INFO("TH58CVG3S0HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4), + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_x4_variants, @@ -216,8 +226,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 1Gb (2nd generation) */ - SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2, - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("TC58CYG0S3HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_x4_variants, @@ -226,8 +237,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 2Gb (2nd generation) */ - SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB, - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + SPINAND_INFO("TC58CYG1S3HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_x4_variants, @@ -236,8 +248,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 4Gb (2nd generation) */ - SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD, - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + SPINAND_INFO("TC58CYG2S0HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_x4_variants, @@ -246,8 +259,9 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 8Gb (2nd generation) */ - SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4, - NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), + SPINAND_INFO("TH58CYG3S0HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4), + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_x4_variants, @@ -257,33 +271,13 @@ static const struct spinand_info toshiba_spinand_table[] = { tx58cxgxsxraix_ecc_get_status)), }; -static int toshiba_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * Toshiba SPI NAND read ID needs a dummy byte, - * so the first byte in id is garbage. - */ - if (id[1] != SPINAND_MFR_TOSHIBA) - return 0; - - ret = spinand_match_and_init(spinand, toshiba_spinand_table, - ARRAY_SIZE(toshiba_spinand_table), - id[2]); - if (ret) - return ret; - - return 1; -} - static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { - .detect = toshiba_spinand_detect, }; const struct spinand_manufacturer toshiba_spinand_manufacturer = { .id = SPINAND_MFR_TOSHIBA, .name = "Toshiba", + .chips = toshiba_spinand_table, + .nchips = ARRAY_SIZE(toshiba_spinand_table), .ops = &toshiba_spinand_manuf_ops, }; diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index c119486efb7..dd4ed257a83 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -8,11 +8,10 @@ */ #ifndef __UBOOT__ -#include <malloc.h> #include <linux/device.h> #include <linux/kernel.h> #endif -#include <linux/bitops.h> +#include <linux/bug.h> #include <linux/mtd/spinand.h> #define SPINAND_MFR_WINBOND 0xEF @@ -78,9 +77,76 @@ static int w25m02gv_select_target(struct spinand_device *spinand, return spi_mem_exec_op(spinand->slave, &op); } +static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 3) + return -ERANGE; + + region->offset = 64 + (16 * section); + region->length = 13; + + return 0; +} + +static int w25n02kv_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 3) + return -ERANGE; + + region->offset = (16 * section) + 2; + region->length = 14; + + return 0; +} + +static const struct mtd_ooblayout_ops w25n02kv_ooblayout = { + .ecc = w25n02kv_ooblayout_ecc, + .rfree = w25n02kv_ooblayout_free, +}; + +static int w25n02kv_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + struct nand_device *nand = spinand_to_nand(spinand); + u8 mbf = 0; + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, &mbf); + + switch (status & STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + case STATUS_ECC_HAS_BITFLIPS: + /* + * Let's try to retrieve the real maximum number of bitflips + * in order to avoid forcing the wear-leveling layer to move + * data around if it's not necessary. + */ + if (spi_mem_exec_op(spinand->slave, &op)) + return nand->eccreq.strength; + + mbf >>= 4; + + if (WARN_ON(mbf > nand->eccreq.strength || !mbf)) + return nand->eccreq.strength; + + return mbf; + + default: + break; + } + + return -EINVAL; +} + static const struct spinand_info winbond_spinand_table[] = { - SPINAND_INFO("W25M02GV", 0xAB, - NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2), + SPINAND_INFO("W25M02GV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, @@ -88,41 +154,26 @@ static const struct spinand_info winbond_spinand_table[] = { 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), SPINAND_SELECT_TARGET(w25m02gv_select_target)), - SPINAND_INFO("W25N01GV", 0xAA, - NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + SPINAND_INFO("W25N01GV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), + SPINAND_INFO("W25N02KV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)), }; -/** - * winbond_spinand_detect - initialize device related part in spinand_device - * struct if it is a Winbond device. - * @spinand: SPI NAND device structure - */ -static int winbond_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * Winbond SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_WINBOND) - return 0; - - ret = spinand_match_and_init(spinand, winbond_spinand_table, - ARRAY_SIZE(winbond_spinand_table), id[2]); - if (ret) - return ret; - - return 1; -} - static int winbond_spinand_init(struct spinand_device *spinand) { struct nand_device *nand = spinand_to_nand(spinand); @@ -142,12 +193,13 @@ static int winbond_spinand_init(struct spinand_device *spinand) } static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { - .detect = winbond_spinand_detect, .init = winbond_spinand_init, }; const struct spinand_manufacturer winbond_spinand_manufacturer = { .id = SPINAND_MFR_WINBOND, .name = "Winbond", + .chips = winbond_spinand_table, + .nchips = ARRAY_SIZE(winbond_spinand_table), .ops = &winbond_spinand_manuf_ops, }; diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index 1df639d6f44..c07c780193f 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -99,7 +99,6 @@ static int xilinxphy_startup(struct phy_device *phydev) static int xilinxphy_of_init(struct phy_device *phydev) { - u32 phytype; ofnode node; debug("%s\n", __func__); @@ -107,10 +106,6 @@ static int xilinxphy_of_init(struct phy_device *phydev) if (!ofnode_valid(node)) return -EINVAL; - phytype = ofnode_read_u32_default(node, "xlnx,phy-type", -1); - if (phytype == XAE_PHY_TYPE_1000BASE_X) - phydev->flags |= XAE_PHY_TYPE_1000BASE_X; - return 0; } diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 3377e669f2f..7c57d32614f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -321,11 +321,38 @@ static int zynq_gem_setup_mac(struct udevice *dev) return 0; } +static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv) +{ + u32 config; + unsigned long pclk_hz; + + pclk_hz = clk_get_rate(&priv->pclk); + if (pclk_hz <= 20000000) + config = GEM_MDC_SET(GEM_CLK_DIV8); + else if (pclk_hz <= 40000000) + config = GEM_MDC_SET(GEM_CLK_DIV16); + else if (pclk_hz <= 80000000) + config = GEM_MDC_SET(GEM_CLK_DIV32); + else if (pclk_hz <= 120000000) + config = GEM_MDC_SET(GEM_CLK_DIV48); + else if (pclk_hz <= 160000000) + config = GEM_MDC_SET(GEM_CLK_DIV64); + else if (pclk_hz <= 240000000) + config = GEM_MDC_SET(GEM_CLK_DIV96); + else if (pclk_hz <= 320000000) + config = GEM_MDC_SET(GEM_CLK_DIV128); + else + config = GEM_MDC_SET(GEM_CLK_DIV224); + + return config; +} + static int zynq_phy_init(struct udevice *dev) { - int ret; + int ret, val; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs_mdio = priv->mdiobase; + struct zynq_gem_regs *regs = priv->iobase; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -333,6 +360,10 @@ static int zynq_phy_init(struct udevice *dev) SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full; + val = gem_mdc_clk_div(priv); + if (val) + writel(val, ®s->nwcfg); + /* Enable only MDIO bus */ writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl); @@ -360,35 +391,10 @@ static int zynq_phy_init(struct udevice *dev) return phy_config(priv->phydev); } -static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv) -{ - u32 config; - unsigned long pclk_hz; - - pclk_hz = clk_get_rate(&priv->pclk); - if (pclk_hz <= 20000000) - config = GEM_MDC_SET(GEM_CLK_DIV8); - else if (pclk_hz <= 40000000) - config = GEM_MDC_SET(GEM_CLK_DIV16); - else if (pclk_hz <= 80000000) - config = GEM_MDC_SET(GEM_CLK_DIV32); - else if (pclk_hz <= 120000000) - config = GEM_MDC_SET(GEM_CLK_DIV48); - else if (pclk_hz <= 160000000) - config = GEM_MDC_SET(GEM_CLK_DIV64); - else if (pclk_hz <= 240000000) - config = GEM_MDC_SET(GEM_CLK_DIV96); - else if (pclk_hz <= 320000000) - config = GEM_MDC_SET(GEM_CLK_DIV128); - else - config = GEM_MDC_SET(GEM_CLK_DIV224); - - return config; -} static int zynq_gem_init(struct udevice *dev) { - u32 i, nwconfig; + u32 i, nwconfig, nwcfg; int ret; unsigned long clk_rate = 0; struct zynq_gem_priv *priv = dev_get_priv(dev); @@ -494,8 +500,7 @@ static int zynq_gem_init(struct udevice *dev) return -1; } - nwconfig = gem_mdc_clk_div(priv); - nwconfig |= ZYNQ_GEM_NWCFG_INIT; + nwconfig = ZYNQ_GEM_NWCFG_INIT; /* * Set SGMII enable PCS selection only if internal PCS/PMA @@ -509,19 +514,21 @@ static int zynq_gem_init(struct udevice *dev) switch (priv->phydev->speed) { case SPEED_1000: - writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, - ®s->nwcfg); + nwconfig |= ZYNQ_GEM_NWCFG_SPEED1000; clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: - writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, - ®s->nwcfg); + nwconfig |= ZYNQ_GEM_NWCFG_SPEED100; clk_rate = ZYNQ_GEM_FREQUENCY_100; break; case SPEED_10: clk_rate = ZYNQ_GEM_FREQUENCY_10; break; } + nwcfg = readl(®s->nwcfg); + nwcfg |= nwconfig; + if (nwcfg) + writel(nwcfg, ®s->nwcfg); #ifdef CONFIG_ARM64 if (priv->interface == PHY_INTERFACE_MODE_SGMII && diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 517035961da..eb17a4290b7 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -548,6 +548,8 @@ static int zynqmp_pinctrl_get_pin_muxing(struct udevice *dev, &pinmux.drive_strength); zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_VOLTAGE_STATUS, &pinmux.volt_sts); + zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_TRI_STATE, + &pinmux.tri_state); switch (pinmux.drive_strength) { case PM_PINCTRL_DRIVE_STRENGTH_2MA: @@ -568,13 +570,15 @@ static int zynqmp_pinctrl_get_pin_muxing(struct udevice *dev, return -EINVAL; } - snprintf(buf, size, "slew:%s\tbias:%s\tpull:%s\tinput:%s\tdrive:%dmA\tvolt:%s", + snprintf(buf, size, + "slew:%s\tbias:%s\tpull:%s\tinput:%s\tdrive:%dmA\tvolt:%s\ttri_state:%s", pinmux.slew ? "slow" : "fast", pinmux.bias ? "enabled" : "disabled", pinmux.pull_ctrl ? "up" : "down", pinmux.input_type ? "schmitt" : "cmos", pinmux.drive_strength, - pinmux.volt_sts ? "1.8" : "3.3"); + pinmux.volt_sts ? "1.8" : "3.3", + pinmux.tri_state ? "enabled" : "disabled"); return 0; } diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c index b5d0e3dceca..d17764d0b08 100644 --- a/drivers/video/console_core.c +++ b/drivers/video/console_core.c @@ -176,6 +176,37 @@ int fill_char_horizontally(uchar *pfont, void **line, struct video_priv *vid_pri return ret; } +int draw_cursor_vertically(void **line, struct video_priv *vid_priv, + uint height, bool direction) +{ + int step, line_step, pbytes, ret; + uint value; + void *dst; + + ret = check_bpix_support(vid_priv->bpix); + if (ret) + return ret; + + pbytes = VNBYTES(vid_priv->bpix); + if (direction) { + step = -pbytes; + line_step = -vid_priv->line_length; + } else { + step = pbytes; + line_step = vid_priv->line_length; + } + + value = vid_priv->colour_fg; + + for (int row = 0; row < height; row++) { + dst = *line; + for (int col = 0; col < VIDCONSOLE_CURSOR_WIDTH; col++) + fill_pixel_and_goto_next(&dst, value, pbytes, step); + *line += line_step; + } + return ret; +} + int console_probe(struct udevice *dev) { return console_set_font(dev, fonts); diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 413c7abee9e..a0231293f31 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -97,6 +97,34 @@ static int console_putc_xy(struct udevice *dev, uint x_frac, uint y, char ch) return VID_TO_POS(fontdata->width); } +static int console_set_cursor_visible(struct udevice *dev, bool visible, + uint x, uint y, uint index) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct udevice *vid = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid); + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; + int pbytes = VNBYTES(vid_priv->bpix); + void *start, *line; + + /* for now, this is not used outside expo */ + if (!IS_ENABLED(CONFIG_EXPO)) + return -ENOSYS; + + x += index * fontdata->width; + start = vid_priv->fb + y * vid_priv->line_length + x * pbytes; + + /* place the cursor 1 pixel before the start of the next char */ + x -= 1; + + line = start; + draw_cursor_vertically(&line, vid_priv, vc_priv->y_charsize, + NORMAL_DIRECTION); + + return 0; +} + struct vidconsole_ops console_ops = { .putc_xy = console_putc_xy, .move_rows = console_move_rows, @@ -104,6 +132,7 @@ struct vidconsole_ops console_ops = { .get_font_size = console_simple_get_font_size, .get_font = console_simple_get_font, .select_font = console_simple_select_font, + .set_cursor_visible = console_set_cursor_visible, }; U_BOOT_DRIVER(vidconsole_normal) = { diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index 0f9bb49e44f..14fb81e9563 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <abuf.h> #include <dm.h> #include <log.h> #include <malloc.h> @@ -175,6 +176,17 @@ struct console_tt_priv { int pos_ptr; }; +/** + * struct console_tt_store - Format used for save/restore of entry information + * + * @priv: Private data + * @cur: Current cursor position + */ +struct console_tt_store { + struct console_tt_priv priv; + struct pos_info cur; +}; + static int console_truetype_set_row(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); @@ -706,8 +718,8 @@ static int truetype_select_font(struct udevice *dev, const char *name, return 0; } -int truetype_measure(struct udevice *dev, const char *name, uint size, - const char *text, struct vidconsole_bbox *bbox) +static int truetype_measure(struct udevice *dev, const char *name, uint size, + const char *text, struct vidconsole_bbox *bbox) { struct console_tt_metrics *met; stbtt_fontinfo *font; @@ -750,6 +762,177 @@ int truetype_measure(struct udevice *dev, const char *name, uint size, return 0; } +static int truetype_nominal(struct udevice *dev, const char *name, uint size, + uint num_chars, struct vidconsole_bbox *bbox) +{ + struct console_tt_metrics *met; + stbtt_fontinfo *font; + int lsb, advance; + int width; + int ret; + + ret = get_metrics(dev, name, size, &met); + if (ret) + return log_msg_ret("sel", ret); + + font = &met->font; + width = 0; + + /* First get some basic metrics about this character */ + stbtt_GetCodepointHMetrics(font, 'W', &advance, &lsb); + + width = advance; + + bbox->valid = true; + bbox->x0 = 0; + bbox->y0 = 0; + bbox->x1 = tt_ceil((double)width * num_chars * met->scale); + bbox->y1 = met->font_size; + + return 0; +} + +static int truetype_entry_save(struct udevice *dev, struct abuf *buf) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct console_tt_priv *priv = dev_get_priv(dev); + struct console_tt_store store; + const uint size = sizeof(store); + + /* + * store the whole priv structure as it is simpler that picking out + * what we need + */ + if (!abuf_realloc(buf, size)) + return log_msg_ret("sav", -ENOMEM); + + store.priv = *priv; + store.cur.xpos_frac = vc_priv->xcur_frac; + store.cur.ypos = vc_priv->ycur; + memcpy(abuf_data(buf), &store, size); + + return 0; +} + +static int truetype_entry_restore(struct udevice *dev, struct abuf *buf) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct console_tt_priv *priv = dev_get_priv(dev); + struct console_tt_store store; + + memcpy(&store, abuf_data(buf), sizeof(store)); + + vc_priv->xcur_frac = store.cur.xpos_frac; + vc_priv->ycur = store.cur.ypos; + priv->pos_ptr = store.priv.pos_ptr; + memcpy(priv->pos, store.priv.pos, + store.priv.pos_ptr * sizeof(struct pos_info)); + + return 0; +} + +static int truetype_set_cursor_visible(struct udevice *dev, bool visible, + uint x, uint y, uint index) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct udevice *vid = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid); + struct console_tt_priv *priv = dev_get_priv(dev); + struct console_tt_metrics *met = priv->cur_met; + uint row, width, height, xoff; + void *start, *line; + uint out, val; + int ret; + + if (!visible) + return 0; + + /* + * figure out where to place the cursor. This driver ignores the + * passed-in values, since an entry_restore() must have been done before + * calling this function. + */ + if (index < priv->pos_ptr) + x = VID_TO_PIXEL(priv->pos[index].xpos_frac); + else + x = VID_TO_PIXEL(vc_priv->xcur_frac); + + y = vc_priv->ycur; + height = met->font_size; + xoff = 0; + + val = vid_priv->colour_bg ? 0 : 255; + width = VIDCONSOLE_CURSOR_WIDTH; + + /* Figure out where to write the cursor in the frame buffer */ + start = vid_priv->fb + y * vid_priv->line_length + + x * VNBYTES(vid_priv->bpix); + line = start; + + /* draw a vertical bar in the correct position */ + for (row = 0; row < height; row++) { + switch (vid_priv->bpix) { + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + u8 *dst = line + xoff; + int i; + + out = val; + for (i = 0; i < width; i++) { + if (vid_priv->colour_fg) + *dst++ |= out; + else + *dst++ &= out; + } + } + break; + case VIDEO_BPP16: { + u16 *dst = (u16 *)line + xoff; + int i; + + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + for (i = 0; i < width; i++) { + out = val >> 3 | + (val >> 2) << 5 | + (val >> 3) << 11; + if (vid_priv->colour_fg) + *dst++ |= out; + else + *dst++ &= out; + } + } + break; + } + case VIDEO_BPP32: { + u32 *dst = (u32 *)line + xoff; + int i; + + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + for (i = 0; i < width; i++) { + int out; + + out = val | val << 8 | val << 16; + if (vid_priv->colour_fg) + *dst++ |= out; + else + *dst++ &= out; + } + } + break; + } + default: + return -ENOSYS; + } + + line += vid_priv->line_length; + } + ret = vidconsole_sync_copy(dev, start, line); + if (ret) + return ret; + + return video_sync(vid, true); +} + const char *console_truetype_get_font_size(struct udevice *dev, uint *sizep) { struct console_tt_priv *priv = dev_get_priv(dev); @@ -802,6 +985,10 @@ struct vidconsole_ops console_truetype_ops = { .get_font_size = console_truetype_get_font_size, .select_font = truetype_select_font, .measure = truetype_measure, + .nominal = truetype_nominal, + .entry_save = truetype_entry_save, + .entry_restore = truetype_entry_restore, + .set_cursor_visible = truetype_set_cursor_visible }; U_BOOT_DRIVER(vidconsole_truetype) = { diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index b5b3b662590..22d55df71f6 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -10,6 +10,7 @@ #define LOG_CATEGORY UCLASS_VIDEO_CONSOLE #include <common.h> +#include <abuf.h> #include <command.h> #include <console.h> #include <log.h> @@ -47,7 +48,7 @@ int vidconsole_set_row(struct udevice *dev, uint row, int clr) return ops->set_row(dev, row, clr); } -static int vidconsole_entry_start(struct udevice *dev) +int vidconsole_entry_start(struct udevice *dev) { struct vidconsole_ops *ops = vidconsole_get_ops(dev); @@ -618,6 +619,74 @@ int vidconsole_measure(struct udevice *dev, const char *name, uint size, return 0; } +int vidconsole_nominal(struct udevice *dev, const char *name, uint size, + uint num_chars, struct vidconsole_bbox *bbox) +{ + struct vidconsole_priv *priv = dev_get_uclass_priv(dev); + struct vidconsole_ops *ops = vidconsole_get_ops(dev); + int ret; + + if (ops->measure) { + ret = ops->nominal(dev, name, size, num_chars, bbox); + if (ret != -ENOSYS) + return ret; + } + + bbox->valid = true; + bbox->x0 = 0; + bbox->y0 = 0; + bbox->x1 = priv->x_charsize * num_chars; + bbox->y1 = priv->y_charsize; + + return 0; +} + +int vidconsole_entry_save(struct udevice *dev, struct abuf *buf) +{ + struct vidconsole_ops *ops = vidconsole_get_ops(dev); + int ret; + + if (ops->measure) { + ret = ops->entry_save(dev, buf); + if (ret != -ENOSYS) + return ret; + } + + /* no data so make sure the buffer is empty */ + abuf_realloc(buf, 0); + + return 0; +} + +int vidconsole_entry_restore(struct udevice *dev, struct abuf *buf) +{ + struct vidconsole_ops *ops = vidconsole_get_ops(dev); + int ret; + + if (ops->measure) { + ret = ops->entry_restore(dev, buf); + if (ret != -ENOSYS) + return ret; + } + + return 0; +} + +int vidconsole_set_cursor_visible(struct udevice *dev, bool visible, + uint x, uint y, uint index) +{ + struct vidconsole_ops *ops = vidconsole_get_ops(dev); + int ret; + + if (ops->set_cursor_visible) { + ret = ops->set_cursor_visible(dev, visible, x, y, index); + if (ret != -ENOSYS) + return ret; + } + + return 0; +} + void vidconsole_push_colour(struct udevice *dev, enum colour_idx fg, enum colour_idx bg, struct vidconsole_colour *old) { diff --git a/drivers/video/vidconsole_internal.h b/drivers/video/vidconsole_internal.h index c41edd45249..0ec581b2663 100644 --- a/drivers/video/vidconsole_internal.h +++ b/drivers/video/vidconsole_internal.h @@ -93,6 +93,30 @@ int fill_char_horizontally(uchar *pfont, void **line, struct video_priv *vid_pri struct video_fontdata *fontdata, bool direction); /** + * draw_cursor_vertically() - Draw a simple vertical cursor + * + * @line: pointer to framebuffer buffer: upper left cursor corner + * @vid_priv: driver private data + * @height: height of the cursor in pixels + * @param direction controls cursor orientation. Can be normal or flipped. + * When normal: When flipped: + *|-----------------------------------------------| + *| * | line stepping | + *| ^ * * * * * | | | + *| | * * | v * * | + *| | | * * * * * | + *| line stepping | * | + *| | | + *| stepping -> | <<- stepping | + *|---!!we're starting from upper left char corner| + *|-----------------------------------------------| + * + * Return: 0, if success, or else error code. + */ +int draw_cursor_vertically(void **line, struct video_priv *vid_priv, + uint height, bool direction); + +/** * console probe function. * * @param dev a pointer to device. diff --git a/include/cli.h b/include/cli.h index 094a6602d70..e183d561369 100644 --- a/include/cli.h +++ b/include/cli.h @@ -8,6 +8,7 @@ #define __CLI_H #include <stdbool.h> +#include <linux/types.h> /** * struct cli_ch_state - state information for reading cmdline characters @@ -25,6 +26,29 @@ struct cli_ch_state { }; /** + * struct cli_line_state - state of the line editor + * + * @num: Current cursor position, where 0 is the start + * @eol_num: Number of characters in the buffer + * @insert: true if in 'insert' mode + * @history: true if history should be accessible + * @cmd_complete: true if tab completion should be enabled (requires @prompt to + * be set) + * @buf: Buffer containing line + * @prompt: Prompt for the line + */ +struct cli_line_state { + uint num; + uint eol_num; + uint len; + bool insert; + bool history; + bool cmd_complete; + char *buf; + const char *prompt; +}; + +/** * Go into the command loop * * This will return if we get a timeout waiting for a command. See @@ -229,4 +253,31 @@ void cli_ch_init(struct cli_ch_state *cch); */ int cli_ch_process(struct cli_ch_state *cch, int ichar); +/** + * cread_line_process_ch() - Process a character for line input + * + * @cls: CLI line state + * @ichar: Character to process + * Return: 0 if input is complete, with line in cls->buf, -EINTR if input was + * cancelled with Ctrl-C, -EAGAIN if more characters are needed + */ +int cread_line_process_ch(struct cli_line_state *cls, char ichar); + +/** + * cli_cread_init() - Set up a new cread struct + * + * Sets up a new cread state, with history and cmd_complete set to false + * + * After calling this, you can use cread_line_process_ch() to process characters + * received from the user. + * + * @cls: CLI line state + * @buf: Text buffer containing the initial text + * @buf_size: Buffer size, including nul terminator + */ +void cli_cread_init(struct cli_line_state *cls, char *buf, uint buf_size); + +/** cread_print_hist_list() - Print the command-line history list */ +void cread_print_hist_list(void); + #endif diff --git a/include/command.h b/include/command.h index 34ea989b39b..1c4ec4257a5 100644 --- a/include/command.h +++ b/include/command.h @@ -95,6 +95,12 @@ int var_complete(int argc, char *const argv[], char last_char, int maxv, char *cmdv[]); int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); +#else +static inline int cmd_auto_complete(const char *const prompt, char *buf, + int *np, int *colp) +{ + return 0; +} #endif /** diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 062102a610d..f9f8c7bc2f6 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -9,15 +9,6 @@ #ifndef __CONFIG_AM642_EVM_H #define __CONFIG_AM642_EVM_H -#include <linux/sizes.h> -#include <config_distro_bootcmd.h> -#include <env/ti/mmc.h> -#include <asm/arch/am64_hardware.h> -#include <env/ti/k3_dfu.h> - -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index e3e50afeaff..70d8cc5ecac 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -7,7 +7,7 @@ #define __PINCTRL_H #define PINNAME_SIZE 10 -#define PINMUX_SIZE 80 +#define PINMUX_SIZE 90 /** * struct pinconf_param - pin config parameters diff --git a/include/expo.h b/include/expo.h index 9d2e817eb97..264745f7f01 100644 --- a/include/expo.h +++ b/include/expo.h @@ -7,11 +7,14 @@ #ifndef __EXPO_H #define __EXPO_H +#include <abuf.h> #include <dm/ofnode_decl.h> #include <linux/list.h> struct udevice; +#include <cli.h> + /** * enum expoact_type - types of actions reported by the expo * @@ -121,6 +124,9 @@ struct expo_string { * @id: ID number of the scene * @title_id: String ID of title of the scene (allocated) * @highlight_id: ID of highlighted object, if any + * @cls: cread state to use for input + * @buf: Buffer for input + * @entry_save: Buffer to hold vidconsole text-entry information * @sibling: Node to link this scene to its siblings * @obj_head: List of objects in the scene */ @@ -130,6 +136,9 @@ struct scene { uint id; uint title_id; uint highlight_id; + struct cli_line_state cls; + struct abuf buf; + struct abuf entry_save; struct list_head sibling; struct list_head obj_head; }; @@ -141,12 +150,16 @@ struct scene { * @SCENEOBJT_IMAGE: Image data to render * @SCENEOBJT_TEXT: Text line to render * @SCENEOBJT_MENU: Menu containing items the user can select + * @SCENEOBJT_TEXTLINE: Line of text the user can edit */ enum scene_obj_t { SCENEOBJT_NONE = 0, SCENEOBJT_IMAGE, SCENEOBJT_TEXT, + + /* types from here on can be highlighted */ SCENEOBJT_MENU, + SCENEOBJT_TEXTLINE, }; /** @@ -178,6 +191,11 @@ enum scene_obj_flags_t { SCENEOF_OPEN = 1 << 2, }; +enum { + /* Maximum number of characters allowed in an line editor */ + EXPO_MAX_CHARS = 250, +}; + /** * struct scene_obj - information about an object in a scene * @@ -203,6 +221,12 @@ struct scene_obj { struct list_head sibling; }; +/* object can be highlighted when moving around expo */ +static inline bool scene_obj_can_highlight(const struct scene_obj *obj) +{ + return obj->type >= SCENEOBJT_MENU; +} + /** * struct scene_obj_img - information about an image object in a scene * @@ -297,6 +321,27 @@ struct scene_menitem { }; /** + * struct scene_obj_textline - information about a textline in a scene + * + * A textline has a prompt and a line of editable text + * + * @obj: Basic object information + * @label_id: ID of the label text, or 0 if none + * @edit_id: ID of the editable text + * @max_chars: Maximum number of characters allowed + * @buf: Text buffer containing current text + * @pos: Cursor position + */ +struct scene_obj_textline { + struct scene_obj obj; + uint label_id; + uint edit_id; + uint max_chars; + struct abuf buf; + uint pos; +}; + +/** * expo_new() - create a new expo * * Allocates a new expo @@ -505,7 +550,7 @@ int scene_txt(struct scene *scn, const char *name, uint id, uint str_id, struct scene_obj_txt **txtp); /** - * scene_txt_str() - add a new string to expr and text object to a scene + * scene_txt_str() - add a new string to expo and text object to a scene * * @scn: Scene to update * @name: Name to use (this is allocated by this call) @@ -531,6 +576,19 @@ int scene_menu(struct scene *scn, const char *name, uint id, struct scene_obj_menu **menup); /** + * scene_textline() - create a textline + * + * @scn: Scene to update + * @name: Name to use (this is allocated by this call) + * @id: ID to use for the new object (0 to allocate one) + * @max_chars: Maximum length of the textline in characters + * @tlinep: If non-NULL, returns the new object + * Returns: ID number for the object (typically @id), or -ve on error + */ +int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars, + struct scene_obj_textline **tlinep); + +/** * scene_txt_set_font() - Set the font for an object * * @scn: Scene to update diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index aeb38dec2e0..651f8706df5 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -19,6 +19,7 @@ * @oobsize: OOB area size * @pages_per_eraseblock: number of pages per eraseblock * @eraseblocks_per_lun: number of eraseblocks per LUN (Logical Unit Number) + * @max_bad_eraseblocks_per_lun: maximum number of eraseblocks per LUN * @planes_per_lun: number of planes per LUN * @luns_per_target: number of LUN per target (target is a synonym for die) * @ntargets: total number of targets exposed by the NAND device @@ -29,18 +30,20 @@ struct nand_memory_organization { unsigned int oobsize; unsigned int pages_per_eraseblock; unsigned int eraseblocks_per_lun; + unsigned int max_bad_eraseblocks_per_lun; unsigned int planes_per_lun; unsigned int luns_per_target; unsigned int ntargets; }; -#define NAND_MEMORG(bpc, ps, os, ppe, epl, ppl, lpt, nt) \ +#define NAND_MEMORG(bpc, ps, os, ppe, epl, mbb, ppl, lpt, nt) \ { \ .bits_per_cell = (bpc), \ .pagesize = (ps), \ .oobsize = (os), \ .pages_per_eraseblock = (ppe), \ .eraseblocks_per_lun = (epl), \ + .max_bad_eraseblocks_per_lun = (mbb), \ .planes_per_lun = (ppl), \ .luns_per_target = (lpt), \ .ntargets = (nt), \ diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 15bcd59f341..e8d6feb9705 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -39,9 +39,9 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) -#define SPINAND_READID_OP(ndummy, buf, len) \ +#define SPINAND_READID_OP(naddr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ - SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_ADDR(naddr, 0, 1), \ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 1)) @@ -75,30 +75,60 @@ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 1)) +#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ + SPI_MEM_OP_ADDR(3, addr, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 1)) + #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ SPI_MEM_OP_ADDR(2, addr, 1), \ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 2)) +#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ + SPI_MEM_OP_ADDR(3, addr, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 2)) + #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ SPI_MEM_OP_ADDR(2, addr, 1), \ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 4)) +#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ + SPI_MEM_OP_ADDR(3, addr, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 4)) + #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ SPI_MEM_OP_ADDR(2, addr, 2), \ SPI_MEM_OP_DUMMY(ndummy, 2), \ SPI_MEM_OP_DATA_IN(len, buf, 2)) +#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ + SPI_MEM_OP_ADDR(3, addr, 2), \ + SPI_MEM_OP_DUMMY(ndummy, 2), \ + SPI_MEM_OP_DATA_IN(len, buf, 2)) + #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ SPI_MEM_OP_ADDR(2, addr, 4), \ SPI_MEM_OP_DUMMY(ndummy, 4), \ SPI_MEM_OP_DATA_IN(len, buf, 4)) +#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ + SPI_MEM_OP_ADDR(3, addr, 4), \ + SPI_MEM_OP_DUMMY(ndummy, 4), \ + SPI_MEM_OP_DATA_IN(len, buf, 4)) + #define SPINAND_PROG_EXEC_OP(addr) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ SPI_MEM_OP_ADDR(3, addr, 1), \ @@ -153,37 +183,46 @@ struct spinand_device; * @data: buffer containing the id bytes. Currently 4 bytes large, but can * be extended if required * @len: ID length - * - * struct_spinand_id->data contains all bytes returned after a READ_ID command, - * including dummy bytes if the chip does not emit ID bytes right after the - * READ_ID command. The responsibility to extract real ID bytes is left to - * struct_manufacurer_ops->detect(). */ struct spinand_id { u8 data[SPINAND_MAX_ID_LEN]; int len; }; +enum spinand_readid_method { + SPINAND_READID_METHOD_OPCODE, + SPINAND_READID_METHOD_OPCODE_ADDR, + SPINAND_READID_METHOD_OPCODE_DUMMY, +}; + +/** + * struct spinand_devid - SPI NAND device id structure + * @id: device id of current chip + * @len: number of bytes in device id + * @method: method to read chip id + * There are 3 possible variants: + * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately + * after read_id opcode. + * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after + * read_id opcode + 1-byte address. + * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after + * read_id opcode + 1 dummy byte. + */ +struct spinand_devid { + const u8 *id; + const u8 len; + const enum spinand_readid_method method; +}; + /** * struct manufacurer_ops - SPI NAND manufacturer specific operations - * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed - * the core calls the struct_manufacurer_ops->detect() hook of each - * registered manufacturer until one of them return 1. Note that - * the first thing to check in this hook is that the manufacturer ID - * in struct_spinand_device->id matches the manufacturer whose - * ->detect() hook has been called. Should return 1 if there's a - * match, 0 if the manufacturer ID does not match and a negative - * error code otherwise. When true is returned, the core assumes - * that properties of the NAND chip (spinand->base.memorg and - * spinand->base.eccreq) have been filled * @init: initialize a SPI NAND device * @cleanup: cleanup a SPI NAND device * * Each SPI NAND manufacturer driver should implement this interface so that - * NAND chips coming from this vendor can be detected and initialized properly. + * NAND chips coming from this vendor can be initialized properly. */ struct spinand_manufacturer_ops { - int (*detect)(struct spinand_device *spinand); int (*init)(struct spinand_device *spinand); void (*cleanup)(struct spinand_device *spinand); }; @@ -192,11 +231,16 @@ struct spinand_manufacturer_ops { * struct spinand_manufacturer - SPI NAND manufacturer instance * @id: manufacturer ID * @name: manufacturer name + * @devid_len: number of bytes in device ID + * @chips: supported SPI NANDs under current manufacturer + * @nchips: number of SPI NANDs available in chips array * @ops: manufacturer operations */ struct spinand_manufacturer { u8 id; char *name; + const struct spinand_info *chips; + const size_t nchips; const struct spinand_manufacturer_ops *ops; }; @@ -204,6 +248,7 @@ struct spinand_manufacturer { extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; extern const struct spinand_manufacturer micron_spinand_manufacturer; +extern const struct spinand_manufacturer paragon_spinand_manufacturer; extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; @@ -268,7 +313,7 @@ struct spinand_ecc_info { */ struct spinand_info { const char *model; - u8 devid; + struct spinand_devid devid; u32 flags; struct nand_memory_organization memorg; struct nand_ecc_req eccreq; @@ -282,6 +327,13 @@ struct spinand_info { unsigned int target); }; +#define SPINAND_ID(__method, ...) \ + { \ + .id = (const u8[]){ __VA_ARGS__ }, \ + .len = sizeof((u8[]){ __VA_ARGS__ }), \ + .method = __method, \ + } + #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ { \ .read_cache = __read, \ @@ -440,9 +492,10 @@ static inline void spinand_set_ofnode(struct spinand_device *spinand, } #endif /* __UBOOT__ */ -int spinand_match_and_init(struct spinand_device *dev, +int spinand_match_and_init(struct spinand_device *spinand, const struct spinand_info *table, - unsigned int table_size, u8 devid); + unsigned int table_size, + enum spinand_readid_method rdid_method); int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); int spinand_select_target(struct spinand_device *spinand, unsigned int target); diff --git a/include/menu.h b/include/menu.h index 64ce89b7d26..6571c39b143 100644 --- a/include/menu.h +++ b/include/menu.h @@ -50,12 +50,17 @@ enum bootmenu_key { BKEY_DOWN, BKEY_SELECT, BKEY_QUIT, + BKEY_SAVE, + + /* 'extra' keys, which are used by menus but not cedit */ BKEY_PLUS, BKEY_MINUS, BKEY_SPACE, - BKEY_SAVE, BKEY_COUNT, + + /* Keys from here on are not used by cedit */ + BKEY_FIRST_EXTRA = BKEY_PLUS, }; /** diff --git a/include/test/cedit-test.h b/include/test/cedit-test.h index 349df75b16d..475ecc9c2dc 100644 --- a/include/test/cedit-test.h +++ b/include/test/cedit-test.h @@ -24,6 +24,9 @@ #define ID_AC_ON 11 #define ID_AC_MEMORY 12 -#define ID_DYNAMIC_START 13 +#define ID_MACHINE_NAME 13 +#define ID_MACHINE_NAME_EDIT 14 + +#define ID_DYNAMIC_START 15 #endif diff --git a/include/video_console.h b/include/video_console.h index 2694e44f6ec..bde67fa9a5a 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -8,6 +8,7 @@ #include <video.h> +struct abuf; struct video_priv; #define VID_FRAC_DIV 256 @@ -15,6 +16,11 @@ struct video_priv; #define VID_TO_PIXEL(x) ((x) / VID_FRAC_DIV) #define VID_TO_POS(x) ((x) * VID_FRAC_DIV) +enum { + /* cursor width in pixels */ + VIDCONSOLE_CURSOR_WIDTH = 2, +}; + /** * struct vidconsole_priv - uclass-private data about a console device * @@ -224,6 +230,60 @@ struct vidconsole_ops { */ int (*measure)(struct udevice *dev, const char *name, uint size, const char *text, struct vidconsole_bbox *bbox); + + /** + * nominal() - Measure the expected width of a line of text + * + * Uses an average font width and nominal height + * + * @dev: Console device to use + * @name: Font name, NULL for default + * @size: Font size, ignored if @name is NULL + * @num_chars: Number of characters to use + * @bbox: Returns nounding box of @num_chars characters + * Returns: 0 if OK, -ve on error + */ + int (*nominal)(struct udevice *dev, const char *name, uint size, + uint num_chars, struct vidconsole_bbox *bbox); + + /** + * entry_save() - Save any text-entry information for later use + * + * Saves text-entry context such as a list of positions for each + * character in the string. + * + * @dev: Console device to use + * @buf: Buffer to hold saved data + * Return: 0 if OK, -ENOMEM if out of memory + */ + int (*entry_save)(struct udevice *dev, struct abuf *buf); + + /** + * entry_restore() - Restore text-entry information for current use + * + * Restores text-entry context such as a list of positions for each + * character in the string. + * + * @dev: Console device to use + * @buf: Buffer containing data to restore + * Return: 0 if OK, -ve on error + */ + int (*entry_restore)(struct udevice *dev, struct abuf *buf); + + /** + * set_cursor_visible() - Show or hide the cursor + * + * Shows or hides a cursor at the current position + * + * @dev: Console device to use + * @visible: true to show the cursor, false to hide it + * @x: X position in pixels + * @y: Y position in pixels + * @index: Character position (0 = at start) + * Return: 0 if OK, -ve on error + */ + int (*set_cursor_visible)(struct udevice *dev, bool visible, + uint x, uint y, uint index); }; /* Get a pointer to the driver operations for a video console device */ @@ -264,6 +324,60 @@ int vidconsole_measure(struct udevice *dev, const char *name, uint size, const char *text, struct vidconsole_bbox *bbox); /** + * vidconsole_nominal() - Measure the expected width of a line of text + * + * Uses an average font width and nominal height + * + * @dev: Console device to use + * @name: Font name, NULL for default + * @size: Font size, ignored if @name is NULL + * @num_chars: Number of characters to use + * @bbox: Returns nounding box of @num_chars characters + * Returns: 0 if OK, -ve on error + */ +int vidconsole_nominal(struct udevice *dev, const char *name, uint size, + uint num_chars, struct vidconsole_bbox *bbox); + +/** + * vidconsole_entry_save() - Save any text-entry information for later use + * + * Saves text-entry context such as a list of positions for each + * character in the string. + * + * @dev: Console device to use + * @buf: Buffer to hold saved data + * Return: 0 if OK, -ENOMEM if out of memory + */ +int vidconsole_entry_save(struct udevice *dev, struct abuf *buf); + +/** + * entry_restore() - Restore text-entry information for current use + * + * Restores text-entry context such as a list of positions for each + * character in the string. + * + * @dev: Console device to use + * @buf: Buffer containing data to restore + * Return: 0 if OK, -ve on error + */ +int vidconsole_entry_restore(struct udevice *dev, struct abuf *buf); + +/** + * vidconsole_set_cursor_visible() - Show or hide the cursor + * + * Shows or hides a cursor at the current position + * + * @dev: Console device to use + * @visible: true to show the cursor, false to hide it + * @x: X position in pixels + * @y: Y position in pixels + * @index: Character position (0 = at start) + * Return: 0 if OK, -ve on error + */ +int vidconsole_set_cursor_visible(struct udevice *dev, bool visible, + uint x, uint y, uint index); + +/** * vidconsole_push_colour() - Temporarily change the font colour * * @dev: Device to adjust @@ -321,6 +435,15 @@ int vidconsole_move_rows(struct udevice *dev, uint rowdst, uint rowsrc, int vidconsole_set_row(struct udevice *dev, uint row, int clr); /** + * vidconsole_entry_start() - Set the start position of a vidconsole line + * + * Marks the current cursor position as the start of a line + * + * @dev: Device to adjust + */ +int vidconsole_entry_start(struct udevice *dev); + +/** * vidconsole_put_char() - Output a character to the current console position * * Outputs a character to the console and advances the cursor. This function diff --git a/test/boot/cedit.c b/test/boot/cedit.c index ab2b8a1f9ff..aa417190486 100644 --- a/test/boot/cedit.c +++ b/test/boot/cedit.c @@ -58,6 +58,7 @@ BOOTSTD_TEST(cedit_base, 0); /* Check the cedit write_fdt and read_fdt commands */ static int cedit_fdt(struct unit_test_state *uts) { + struct scene_obj_textline *tline; struct video_priv *vid_priv; extern struct expo *cur_exp; struct scene_obj_menu *menu; @@ -66,6 +67,7 @@ static int cedit_fdt(struct unit_test_state *uts) struct scene *scn; oftree tree; ofnode node; + char *str; void *fdt; int i; @@ -79,6 +81,12 @@ static int cedit_fdt(struct unit_test_state *uts) ut_assertnonnull(menu); menu->cur_item_id = ID_CPU_SPEED_2; + /* get a textline to fiddle with too */ + tline = scene_obj_find(scn, ID_MACHINE_NAME, SCENEOBJT_TEXTLINE); + ut_assertnonnull(tline); + str = abuf_data(&tline->buf); + strcpy(str, "my-machine"); + ut_assertok(run_command("cedit write_fdt hostfs - settings.dtb", 0)); ut_assertok(run_commandf("load hostfs - %lx settings.dtb", addr)); ut_assert_nextlinen("1024 bytes read"); @@ -86,26 +94,29 @@ static int cedit_fdt(struct unit_test_state *uts) fdt = map_sysmem(addr, 1024); tree = oftree_from_fdt(fdt); node = ofnode_find_subnode(oftree_root(tree), CEDIT_NODE_NAME); + ut_assert(ofnode_valid(node)); ut_asserteq(ID_CPU_SPEED_2, ofnode_read_u32_default(node, "cpu-speed", 0)); ut_asserteq_str("2.5 GHz", ofnode_read_string(node, "cpu-speed-str")); - ut_assert(ofnode_valid(node)); + ut_asserteq_str("my-machine", ofnode_read_string(node, "machine-name")); - /* There should only be 4 properties */ + /* There should only be 5 properties */ for (i = 0, ofnode_first_property(node, &prop); ofprop_valid(&prop); i++, ofnode_next_property(&prop)) ; - ut_asserteq(4, i); + ut_asserteq(5, i); ut_assert_console_end(); /* reset the expo */ menu->cur_item_id = ID_CPU_SPEED_1; + *str = '\0'; /* load in the settings and make sure they update */ ut_assertok(run_command("cedit read_fdt hostfs - settings.dtb", 0)); ut_asserteq(ID_CPU_SPEED_2, menu->cur_item_id); + ut_asserteq_str("my-machine", ofnode_read_string(node, "machine-name")); ut_assertnonnull(menu); ut_assert_console_end(); @@ -117,10 +128,12 @@ BOOTSTD_TEST(cedit_fdt, 0); /* Check the cedit write_env and read_env commands */ static int cedit_env(struct unit_test_state *uts) { + struct scene_obj_textline *tline; struct video_priv *vid_priv; extern struct expo *cur_exp; struct scene_obj_menu *menu; struct scene *scn; + char *str; console_record_reset_enable(); ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0)); @@ -132,25 +145,36 @@ static int cedit_env(struct unit_test_state *uts) ut_assertnonnull(menu); menu->cur_item_id = ID_CPU_SPEED_2; + /* get a textline to fiddle with too */ + tline = scene_obj_find(scn, ID_MACHINE_NAME, SCENEOBJT_TEXTLINE); + ut_assertnonnull(tline); + str = abuf_data(&tline->buf); + strcpy(str, "my-machine"); + ut_assertok(run_command("cedit write_env -v", 0)); ut_assert_nextlinen("c.cpu-speed=7"); ut_assert_nextlinen("c.cpu-speed-str=2.5 GHz"); ut_assert_nextlinen("c.power-loss=10"); ut_assert_nextlinen("c.power-loss-str=Always Off"); + ut_assert_nextlinen("c.machine-name=my-machine"); ut_assert_console_end(); ut_asserteq(7, env_get_ulong("c.cpu-speed", 10, 0)); ut_asserteq_str("2.5 GHz", env_get("c.cpu-speed-str")); + ut_asserteq_str("my-machine", env_get("c.machine-name")); /* reset the expo */ menu->cur_item_id = ID_CPU_SPEED_1; + *str = '\0'; ut_assertok(run_command("cedit read_env -v", 0)); ut_assert_nextlinen("c.cpu-speed=7"); ut_assert_nextlinen("c.power-loss=10"); + ut_assert_nextlinen("c.machine-name=my-machine"); ut_assert_console_end(); ut_asserteq(ID_CPU_SPEED_2, menu->cur_item_id); + ut_asserteq_str("my-machine", env_get("c.machine-name")); return 0; } diff --git a/test/boot/expo.c b/test/boot/expo.c index 90027409c81..714fdfa415d 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -654,7 +654,7 @@ static int expo_test_build(struct unit_test_state *uts) ut_asserteq_str("name", exp->name); ut_asserteq(0, exp->scene_id); - ut_asserteq(ID_DYNAMIC_START + 20, exp->next_id); + ut_asserteq(ID_DYNAMIC_START + 24, exp->next_id); ut_asserteq(false, exp->popup); /* check the scene */ diff --git a/test/boot/files/expo_ids.h b/test/boot/files/expo_ids.h index 027d44bf38c..a86e0d06f6b 100644 --- a/test/boot/files/expo_ids.h +++ b/test/boot/files/expo_ids.h @@ -21,5 +21,8 @@ enum { ID_AC_ON, ID_AC_MEMORY, + ID_MACHINE_NAME, + ID_MACHINE_NAME_EDIT, + ID_DYNAMIC_START, }; diff --git a/test/boot/files/expo_layout.dts b/test/boot/files/expo_layout.dts index cb2a674d9d5..bed552288f4 100644 --- a/test/boot/files/expo_layout.dts +++ b/test/boot/files/expo_layout.dts @@ -55,6 +55,14 @@ start-bit = <0x422>; bit-length = <2>; }; + + machine-name { + id = <ID_MACHINE_NAME>; + type = "textline"; + max-chars = <20>; + title = "Machine name"; + edit-id = <ID_MACHINE_NAME_EDIT>; + }; }; }; diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 6e3d7e919ef..8d70ac510a5 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-$(CONFIG_CMD_FDT) += fdt.o obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o +obj-$(CONFIG_CMD_HISTORY) += history.o obj-$(CONFIG_CMD_LOADM) += loadm.o obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o ifdef CONFIG_CMD_PCI diff --git a/test/cmd/history.c b/test/cmd/history.c new file mode 100644 index 00000000000..06517fcdbb5 --- /dev/null +++ b/test/cmd/history.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for history command + * + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <cli.h> +#include <command.h> +#include <test/lib.h> +#include <test/test.h> +#include <test/ut.h> + +static int lib_test_history(struct unit_test_state *uts) +{ + static const char cmd1[] = "setenv fred hello"; + static const char cmd2[] = "print fred"; + + /* running commands directly does not add to history */ + ut_assertok(run_command(cmd1, 0)); + ut_assert_console_end(); + ut_assertok(run_command("history", 0)); + ut_assert_console_end(); + + /* enter commands via the console */ + console_in_puts(cmd1); + console_in_puts("\n"); + ut_asserteq(strlen(cmd1), cli_readline("")); + ut_assert_nextline(cmd1); + + console_in_puts(cmd2); + console_in_puts("\n"); + ut_asserteq(strlen(cmd2), cli_readline("")); + ut_assert_nextline(cmd2); + + ut_assertok(run_command("print fred", 0)); + ut_assert_nextline("fred=hello"); + ut_assert_console_end(); + + ut_assertok(run_command("history", 0)); + ut_assert_nextline(cmd1); + ut_assert_nextline(cmd2); + ut_assert_console_end(); + + return 0; +} +LIB_TEST(lib_test_history, UT_TESTF_CONSOLE_REC); diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py index cd4b4dc53cb..b2241ae6a48 100644 --- a/test/py/tests/test_net.py +++ b/test/py/tests/test_net.py @@ -6,6 +6,7 @@ import pytest import u_boot_utils +import uuid """ Note: This test relies on boardenv_* containing configuration values to define @@ -61,6 +62,16 @@ env__net_nfs_readable_file = { 'crc32': 'c2244b26', } +# Details regarding a file that may be read from a TFTP server. This variable +# may be omitted or set to None if PXE testing is not possible or desired. +env__net_pxe_readable_file = { + 'fn': 'default', + 'addr': 0x2000000, + 'size': 74, + 'timeout': 50000, + 'pattern': 'Linux', +} + # True if a router advertisement service is connected to the network, and should # be tested. If router advertisement testing is not possible or desired, this variable may be omitted or set to False. @@ -260,3 +271,58 @@ def test_net_nfs(u_boot_console): output = u_boot_console.run_command('crc32 %x $filesize' % addr) assert expected_crc in output + +@pytest.mark.buildconfigspec("cmd_net") +@pytest.mark.buildconfigspec("cmd_pxe") +def test_net_pxe_get(u_boot_console): + """Test the pxe get command. + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + + if not net_set_up: + pytest.skip("Network not initialized") + + test_net_setup_static(u_boot_console) + + f = u_boot_console.config.env.get("env__net_pxe_readable_file", None) + if not f: + pytest.skip("No PXE readable file to read") + + addr = f.get("addr", None) + timeout = f.get("timeout", u_boot_console.p.timeout) + + pxeuuid = uuid.uuid1() + u_boot_console.run_command(f"setenv pxeuuid {pxeuuid}") + expected_text_uuid = f"Retrieving file: pxelinux.cfg/{pxeuuid}" + + ethaddr = u_boot_console.run_command("echo $ethaddr") + ethaddr = ethaddr.replace(':', '-') + expected_text_ethaddr = f"Retrieving file: pxelinux.cfg/01-{ethaddr}" + + ip = u_boot_console.run_command("echo $ipaddr") + ip = ip.split('.') + ipaddr_file = "".join(['%02x' % int(x) for x in ip]).upper() + expected_text_ipaddr = f"Retrieving file: pxelinux.cfg/{ipaddr_file}" + expected_text_default = f"Retrieving file: pxelinux.cfg/default" + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command("pxe get") + + assert "TIMEOUT" not in output + assert expected_text_uuid in output + assert expected_text_ethaddr in output + assert expected_text_ipaddr in output + + i = 1 + for i in range(0, len(ipaddr_file) - 1): + expected_text_ip = f"Retrieving file: pxelinux.cfg/{ipaddr_file[:-i]}" + assert expected_text_ip in output + i += 1 + + assert expected_text_default in output + assert "Config file 'default.boot' found" in output diff --git a/tools/mkimage.c b/tools/mkimage.c index a5979fa6fd7..6dfe3e1d42d 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -112,7 +112,7 @@ static void usage(const char *msg) " -f => input filename for FIT source\n" " -i => input filename for ramdisk file\n" " -E => place data outside of the FIT structure\n" - " -B => align size in hex for FIT structure and, with -E, for the external data\n" + " -B => align size in hex for FIT structure and header\n" " -b => append the device tree binary to the FIT\n" " -t => update the timestamp in the FIT\n"); #ifdef CONFIG_FIT_SIGNATURE |