diff options
240 files changed, 8524 insertions, 14439 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 41c881f40fa..c024b41f13c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -133,6 +133,7 @@ F: arch/arm/include/asm/arch-pxa/ ARM RENESAS RMOBILE/R-CAR M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +M: Marek Vasut <marek.vasut+renesas@gmail.com> S: Maintained T: git git://git.denx.de/u-boot-sh.git F: arch/arm/mach-rmobile/ @@ -142,8 +143,20 @@ M: Simon Glass <sjg@chromium.org> M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> S: Maintained T: git git://git.denx.de/u-boot-rockchip.git +F: arch/arm/include/asm/arch-rockchip/ F: arch/arm/mach-rockchip/ F: board/rockchip/ +F: drivers/clk/rockchip/ +F: drivers/gpio/rk_gpio.c +F: drivers/misc/rockchip-efuse.c +F: drivers/pinctrl/rockchip/ +F: drivers/ram/rockchip/ +F: drivers/sysreset/sysreset_rockchip.c +F: tools/rkcommon.c +F: tools/rkcommon.h +F: tools/rkimage.c +F: tools/rksd.c +F: tools/rkspi.c ARM SAMSUNG M: Minkyu Kang <mk7.kang@samsung.com> diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 1a77779db4d..02f61fcc3cb 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -68,8 +68,8 @@ endif checkgcc6: @if test "$(call cc-name)" = "gcc" -a \ "$(call cc-version)" -lt "0600"; then \ - echo -n '*** Your GCC is older than 6.0 and will not be '; \ - echo 'supported starting in v2018.01.'; \ + echo '*** Your GCC is older than 6.0 and is not supported'; \ + false; \ fi diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index adc7e1746f5..6548f3c9121 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -230,7 +230,10 @@ static void add_map(struct mm_region *map) /* Page fits, create block PTE */ debug("Setting PTE %p to block virt=%llx\n", pte, virt); - *pte = phys | attrs; + if (level == 3) + *pte = phys | attrs | PTE_TYPE_PAGE; + else + *pte = phys | attrs; virt += blocksize; phys += blocksize; size -= blocksize; diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S index 4f4f526f932..8c7c1d3eb80 100644 --- a/arch/arm/cpu/armv8/exceptions.S +++ b/arch/arm/cpu/armv8/exceptions.S @@ -12,12 +12,65 @@ #include <linux/linkage.h> /* + * Exception vectors. + */ + .align 11 + .globl vectors +vectors: + .align 7 /* Current EL Synchronous Thread */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_bad_sync + b exception_exit + + .align 7 /* Current EL IRQ Thread */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_bad_irq + b exception_exit + + .align 7 /* Current EL FIQ Thread */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_bad_fiq + b exception_exit + + .align 7 /* Current EL Error Thread */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_bad_error + b exception_exit + + .align 7 /* Current EL Synchronous Handler */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_sync + b exception_exit + + .align 7 /* Current EL IRQ Handler */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_irq + b exception_exit + + .align 7 /* Current EL FIQ Handler */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_fiq + b exception_exit + + .align 7 /* Current EL Error Handler */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_error + b exception_exit + +/* * Enter Exception. * This will save the processor state that is ELR/X0~X30 * to the stack frame. */ -.macro exception_entry - stp x29, x30, [sp, #-16]! +_exception_entry: stp x27, x28, [sp, #-16]! stp x25, x26, [sp, #-16]! stp x23, x24, [sp, #-16]! @@ -46,78 +99,8 @@ 0: stp x2, x0, [sp, #-16]! mov x0, sp -.endm + ret -/* - * Exception vectors. - */ - .align 11 - .globl vectors -vectors: - .align 7 - b _do_bad_sync /* Current EL Synchronous Thread */ - - .align 7 - b _do_bad_irq /* Current EL IRQ Thread */ - - .align 7 - b _do_bad_fiq /* Current EL FIQ Thread */ - - .align 7 - b _do_bad_error /* Current EL Error Thread */ - - .align 7 - b _do_sync /* Current EL Synchronous Handler */ - - .align 7 - b _do_irq /* Current EL IRQ Handler */ - - .align 7 - b _do_fiq /* Current EL FIQ Handler */ - - .align 7 - b _do_error /* Current EL Error Handler */ - - -_do_bad_sync: - exception_entry - bl do_bad_sync - b exception_exit - -_do_bad_irq: - exception_entry - bl do_bad_irq - b exception_exit - -_do_bad_fiq: - exception_entry - bl do_bad_fiq - b exception_exit - -_do_bad_error: - exception_entry - bl do_bad_error - b exception_exit - -_do_sync: - exception_entry - bl do_sync - b exception_exit - -_do_irq: - exception_entry - bl do_irq - b exception_exit - -_do_fiq: - exception_entry - bl do_fiq - b exception_exit - -_do_error: - exception_entry - bl do_error - b exception_exit exception_exit: ldp x2, x0, [sp],#16 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0d055e3abbc..ed85349d3fc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3036-sdk.dtb \ + rk3128-evb.dtb \ rk3188-radxarock.dtb \ rk3288-evb.dtb \ rk3288-fennec.dtb \ @@ -55,7 +56,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb \ - meson-gxl-s905x-p212.dtb + meson-gxl-s905x-p212.dtb \ + meson-gxl-s905x-libretech-cc.dtb \ + meson-gxl-s905x-khadas-vim.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -427,6 +430,9 @@ dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ logicpd-torpedo-37xx-devkit.dtb \ logicpd-som-lv-37xx-devkit.dtb +dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ + at91-sama5d2_ptc_ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index dc8a1a66c1f..5e5a1585518 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -258,6 +258,19 @@ marvell,function = "i2c0"; }; + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", + "mpp38", "mpp28", "mpp40", "mpp42", + "mpp35", "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp41"; + marvell,function = "nand"; + }; + mdio_pins: mdio-pins { marvell,pins = "mpp4", "mpp5"; marvell,function = "ge"; @@ -545,7 +558,7 @@ }; flash@d0000 { - compatible = "marvell,armada370-nand"; + compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/dts/at91-sama5d2_ptc_ek.dts new file mode 100644 index 00000000000..ab5ab21895d --- /dev/null +++ b/arch/arm/dts/at91-sama5d2_ptc_ek.dts @@ -0,0 +1,215 @@ +/* + * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board + * + * Copyright (C) 2017 Microchip Technology Inc, + * Ludovic Desroches <ludovic.desroches@microchip.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" + +/ { + model = "Atmel SAMA5D2 PTC EK"; + compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart0; + }; + + ahb { + usb0: gadget@00300000 { + atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00400000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PB12 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@00500000 { + status = "okay"; + }; + + sdmmc0: sdio-host@a0000000 { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + sdmmc1: sdio-host@b0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + status = "disabled"; /* conflicts with nand and qspi0*/ + u-boot,dm-pre-reloc; + }; + + apb { + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + uart0: serial@f801c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + i2c1: i2c@fc028000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + i2c_eeprom: i2c_eeprom@50 { + compatible = "atmel,24mac402"; + reg = <0x50>; + }; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PC6__TWD1>, + <PIN_PC7__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + }; + + pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA6__SDMMC0_DAT4>, + <PIN_PA7__SDMMC0_DAT5>, + <PIN_PA8__SDMMC0_DAT6>, + <PIN_PA9__SDMMC0_DAT7>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA10__SDMMC0_RSTN>, + <PIN_PA11__SDMMC0_VDDSEL>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pinmux = <PIN_PA28__SDMMC1_CMD>, + <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_uart0_default: uart0_default { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB12__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PB11__GPIO>; + bias-disable; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/bcm2835-rpi-zero-w.dts b/arch/arm/dts/bcm2835-rpi-zero-w.dts new file mode 100644 index 00000000000..78170547752 --- /dev/null +++ b/arch/arm/dts/bcm2835-rpi-zero-w.dts @@ -0,0 +1,26 @@ +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; + model = "Raspberry Pi Zero W"; + + leds { + act { + gpios = <&gpio 47 0>; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi index 85cb5487713..d46ecdbc566 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi @@ -6,6 +6,8 @@ */ / { + model = "LogicPD Zoom OMAP3 Development Kit"; + chosen { stdout-path = &uart1; }; diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts new file mode 100644 index 00000000000..94567eb1787 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> + +#include "meson-gxl-s905x-p212.dtsi" + +/ { + compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; + model = "Khadas VIM"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-function { + label = "Function"; + linux,code = <KEY_FN>; + press-threshold-microvolt = <10000>; + }; + }; + + aliases { + serial2 = &uart_AO_B; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "power"; + linux,code = <KEY_POWER>; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + power { + label = "vim:red:power"; + pwms = <&pwm_AO_ab 1 7812500 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; +}; + +&i2c_B { + status = "okay"; + pinctrl-0 = <&i2c_b_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + /* has to be enabled manually when a battery is connected: */ + status = "disabled"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&ir { + linux,rc-map-name = "rc-geekbox"; +}; + +&pwm_AO_ab { + status = "okay"; + pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; + pinctrl-names = "default"; + clocks = <&xtal> , <&xtal>; + clock-names = "clkin0", "clkin1" ; +}; + +&pwm_ef { + pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; +}; + +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ +&uart_AO { + status = "okay"; +}; + +/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ +&uart_AO_B { + status = "okay"; + pinctrl-0 = <&uart_ao_b_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts new file mode 100644 index 00000000000..266fbcf3e47 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2017 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * Author: Jerome Brunet <jbrunet@baylibre.com> + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; + model = "Libre Technology CC"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + system { + label = "librecomputer:system-status"; + gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + default-state = "on"; + panic-indicator; + }; + + blue { + label = "librecomputer:blue"; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_card: regulator-vcc-card { + compatible = "regulator-gpio"; + + regulator-name = "VCC_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0>, + <1800000 1>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +ðmac { + status = "okay"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_card>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <50000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index 615b6521314..405ae9c7818 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -394,6 +394,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + u-boot,dm-pre-reloc; }; sysc: system-controller@e6180000 { diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 9e6a5f231e9..6a6bfd4e194 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -377,6 +377,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + u-boot,dm-pre-reloc; }; sysc: system-controller@e6180000 { diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts new file mode 100644 index 00000000000..6940af9a5c1 --- /dev/null +++ b/arch/arm/dts/rk3128-evb.dts @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "rk3128.dtsi" + +/ { + model = "Rockchip RK3128 Evaluation board"; + compatible = "rockchip,rk3128-evb", "rockchip,rk3128"; + + chosen { + stdout-path = &uart2; + }; + + vcc5v0_otg: vcc5v0-otg-drv { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-drv { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&emmc { + fifo-mode; + status = "okay"; +}; + +&pinctrl { + usb_otg { + otg_vbus_drv: host-vbus-drv { + rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi new file mode 100644 index 00000000000..3ef2737f5b5 --- /dev/null +++ b/arch/arm/dts/rk3128.dtsi @@ -0,0 +1,804 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3128-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3128"; + rockchip,sram = <&sram>; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + spi0 = &spi0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3128-smp"; + + cpu0:cpu@0x000 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x000>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + + cpu1:cpu@0x001 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x001>; + }; + + cpu2:cpu@0x002 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x002>; + }; + + cpu3:cpu@0x003 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x003>; + }; + }; + + cpu_axi_bus: cpu_axi_bus { + compatible = "rockchip,cpu_axi_bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qos { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + crypto { + reg = <0x10128080 0x20>; + }; + + core { + reg = <0x1012a000 0x20>; + }; + + peri { + reg = <0x1012c000 0x20>; + }; + + gpu { + reg = <0x1012d000 0x20>; + }; + + vpu { + reg = <0x1012e000 0x20>; + }; + + rga { + reg = <0x1012f000 0x20>; + }; + ebc { + reg = <0x1012f080 0x20>; + }; + + iep { + reg = <0x1012f100 0x20>; + }; + + lcdc { + reg = <0x1012f180 0x20>; + rockchip,priority = <3 3>; + }; + + vip { + reg = <0x1012f200 0x20>; + rockchip,priority = <3 3>; + }; + }; + + msch { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + msch@10128000 { + reg = <0x10128000 0x20>; + rockchip,read-latency = <0x3f>; + }; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + migrate = <0x84000005>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + pdma: pdma@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + arm,pl330-broken-no-flushp;//2 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin12m: xin12m { + compatible = "fixed-clock"; + clocks = <&xin24m>; + clock-frequency = <12000000>; + clock-output-names = "xin12m"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + timer@20044000 { + compatible = "arm,armv7-timer"; + reg = <0x20044000 0xb8>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + rockchip,broadcast = <1>; + }; + + watchdog: wdt@2004c000 { + compatible = "rockchip,watch dog"; + reg = <0x2004c000 0x100>; + clock-names = "pclk_wdt"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + rockchip,irq = <1>; + rockchip,timeout = <60>; + rockchip,atboot = <1>; + rockchip,debug = <0>; + }; + + reset: reset@20000110 { + compatible = "rockchip,reset"; + reg = <0x20000110 0x24>; + #reset-cells = <1>; + }; + + nandc: nandc@10500000 { + compatible = "rockchip,rk-nandc"; + reg = <0x10500000 0x4000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; + nandc_id = <0>; + clocks = <&cru SCLK_NANDC>, + <&cru HCLK_NANDC>, + <&cru SRST_NANDC>; + clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; + }; + + dmc: dmc@20004000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3128-dmc", "syscon"; + reg = <0x0 0x20004000 0x0 0x1000>; + }; + + cru: clock-controller@20000000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + uart0: serial0@20060000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + dmas = <&pdma 2>, <&pdma 3>; + #dma-cells = <2>; + }; + + uart1: serial1@20064000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + dmas = <&pdma 4>, <&pdma 5>; + #dma-cells = <2>; + }; + + uart2: serial2@20068000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + dmas = <&pdma 6>, <&pdma 7>; + #dma-cells = <2>; + }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + pwm0: pwm0@20050000 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050000 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + }; + + pwm1: pwm1@20050010 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050010 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + }; + + pwm2: pwm2@20050020 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + }; + + pwm3: pwm3@20050030 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + }; + + sram: sram@10080400 { + compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; + reg = <0x10080400 0x1C00>; + map-exec; + map-cacheable; + }; + + pmu: syscon@100a0000 { + compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; + reg = <0x100a0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; + }; + + u2phy: usb2-phy { + compatible = "rockchip,rk3128-usb2phy"; + reg = <0x017c 0x0c>; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "usb480m_phy"; + #phy-cells = <1>; + status = "disabled"; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", + "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + g-use-dma; + hnp-srp-disable; + phys = <&u2phy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ehci: usb@101c0000 { + compatible = "generic-ehci"; + reg = <0x101c0000 0x20000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2phy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@101e0000 { + compatible = "generic-ohci"; + reg = <0x101e0000 0x20000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2phy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + sdmmc: dwmmc@10214000 { + compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10214000 0x4000>; + max-frequency = <150000000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + bus-width = <4>; + status = "disabled"; + }; + + emmc: dwmmc@1021c000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x1021c000 0x4000>; + max-frequency = <150000000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + bus-width = <8>; + default-sample-phase = <158>; + num-slots = <1>; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + i2c0: i2c0@20072000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <20072000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + }; + + i2c1: i2c1@20056000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + }; + + i2c2: i2c2@2005a000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + }; + + i2c3: i2c3@2005e000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + }; + + spi0: spi@20074000 { + compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; + reg = <0x20074000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; + rockchip,spi-src-clk = <0>; + num-cs = <2>; + clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; + clock-names = "spi","pclk_spi0"; + dmas = <&pdma 8>, <&pdma 9>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + }; + + grf: syscon@20008000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3128-grf", "syscon"; + reg = <0x20008000 0x1000>; + }; + + pinctrl: pinctrl@20008000 { + compatible = "rockchip,rk3128-pinctrl"; + reg = <0x20008000 0xA8>, + <0x200080A8 0x4C>, + <0x20008118 0x20>, + <0x20008100 0x04>; + reg-names = "base", "mux", "pull", "drv"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio2@20088000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20088000 0x100>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + + emmc_clk: emmc-clk { + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>, + <1 28 RK_FUNC_2 &pcfg_pull_none>, + <1 29 RK_FUNC_2 &pcfg_pull_none>, + <1 30 RK_FUNC_2 &pcfg_pull_none>, + <1 31 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + nandc{ + nandc_ale:nandc-ale { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_cle:nandc-cle { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_wrn:nandc-wrn { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_rdn:nandc-rdn { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_rdy:nandc-rdy { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_cs0:nandc-cs0 { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_data: nandc-data { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, + <2 23 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; + }; + + sdmmc_wp: sdmmc-wp { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; + }; + + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, + <1 RK_PC3 1 &pcfg_pull_up>, + <1 RK_PC4 1 &pcfg_pull_up>, + <1 RK_PC5 1 &pcfg_pull_up>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 1 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 27 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, + <0 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 20 3 &pcfg_pull_none>, + <2 21 3 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_txd_mux0:spi0-txd-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + spi0_rxd_mux0:spi0-rxd-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + spi0_clk_mux0:spi0-clk-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + spi0_cs0_mux0:spi0-cs0-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + spi0_cs1_mux0:spi0-cs1-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + }; +}; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 96bd4fec01d..d2c961e3178 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -16,6 +16,7 @@ u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */ u-boot,boot-led = "module_led"; + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; }; chosen { @@ -544,12 +545,17 @@ &dwc3_typec1 { status = "okay"; + tsd,usb-port-power = "usbhub_enable"; }; &vopb { status = "okay"; }; +&gpio1 { + u-boot,dm-pre-reloc; +}; + &gpio3 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 7520446dc1a..6645a553646 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -302,6 +302,7 @@ #clock-cells = <0>; reg = <24>; atmel,clk-output-range = <0 83000000>; + u-boot,dm-pre-reloc; }; uart1_clk: uart1_clk@25 { @@ -315,6 +316,7 @@ #clock-cells = <0>; reg = <26>; atmel,clk-output-range = <0 83000000>; + u-boot,dm-pre-reloc; }; uart3_clk: uart3_clk@27 { @@ -635,6 +637,14 @@ status = "disabled"; }; + uart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x100>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + uart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; @@ -643,6 +653,14 @@ status = "disabled"; }; + uart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x100>; + clocks = <&uart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + i2c0: i2c@f8028000 { compatible = "atmel,sama5d2-i2c"; reg = <0xf8028000 0x100>; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 5f77f578af8..a56ae931210 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -22,3 +22,7 @@ u-boot,dm-pre-reloc; }; }; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 783d4e734e5..f62360f0db5 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -99,12 +99,19 @@ status = "disabled"; u-boot,dm-pre-reloc; }; + + pwrcfg: power-config@58024800 { + compatible = "syscon"; + reg = <0x40007000 0x400>; + }; + rcc: rcc@40023810 { #reset-cells = <1>; #clock-cells = <2>; - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + compatible = "st,stm32f746-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; clocks = <&clk_hse>; + st,syscfg = <&pwrcfg>; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index e21cf332c9b..59fcf711825 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -24,6 +24,15 @@ stdout-path = "serial0:115200n8"; }; + cpld { + compatible = "renesas,ulcb-cpld"; + status = "okay"; + gpio-sck = <&gpio6 8 0>; + gpio-mosi = <&gpio6 7 0>; + gpio-miso = <&gpio6 10 0>; + gpio-sstbz = <&gpio2 3 0>; + }; + audio_clkout: audio-clkout { /* * This is same as <&rcar_sound 0> @@ -190,6 +199,10 @@ }; }; +&i2c_dvfs { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -247,7 +260,7 @@ sdhi2_pins: sd2 { groups = "sdhi2_data8", "sdhi2_ctrl"; function = "sdhi2"; - power-source = <3300>; + power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h new file mode 100644 index 00000000000..3089f13ba00 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/eth.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MESON_ETH_H__ +#define __MESON_ETH_H__ + +#include <phy.h> + +enum { + /* Use GXL Internal RMII PHY */ + MESON_GXL_USE_INTERNAL_RMII_PHY = 1, +}; + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_gx_eth_init(phy_interface_t mode, unsigned int flags); + +#endif /* __MESON_ETH_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h index 95a6fe6998e..ef63dea4496 100644 --- a/arch/arm/include/asm/arch-meson/gxbb.h +++ b/arch/arm/include/asm/arch-meson/gxbb.h @@ -7,10 +7,27 @@ #ifndef __GXBB_H__ #define __GXBB_H__ +#define GXBB_FIRMWARE_MEM_SIZE 0x1000000 + +#define GXBB_AOBUS_BASE 0xc8100000 #define GXBB_PERIPHS_BASE 0xc8834400 #define GXBB_HIU_BASE 0xc883c000 #define GXBB_ETH_BASE 0xc9410000 +/* Always-On Peripherals registers */ +#define GXBB_AO_ADDR(off) (GXBB_AOBUS_BASE + ((off) << 2)) + +#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90) +#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93) +#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94) +#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95) + +#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000 +#define GXBB_AO_MEM_SIZE_SHIFT 16 +#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + /* Peripherals registers */ #define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h new file mode 100644 index 00000000000..86a84170347 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/mem.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MESON_MEM_H__ +#define __MESON_MEM_H__ + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_gx_init_reserved_memory(void *fdt); + +#endif /* __MESON_MEM_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h new file mode 100644 index 00000000000..90012c7fce0 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_CRU_RK3128_H +#define _ASM_ARCH_CRU_RK3128_H + +#include <common.h> + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (594 * MHz) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3128_clk_priv { + struct rk3128_cru *cru; +}; + +struct rk3128_cru { + struct rk3128_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[11]; + unsigned int reserved; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int reserved1[2]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved2[2]; + unsigned int cru_glb_cnt_th; + unsigned int reserved3[3]; + unsigned int cru_glb_rst_st; + unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int reserved5[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved6[4]; + unsigned int cru_pll_prg_en; +}; +check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_RST_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* CRU_MODE */ + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + GPLL_MODE_DEEP, + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORM, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + BUS_ACLK_PLL_SEL_SHIFT = 14, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_CPLL = 0, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_PLL_SEL_GPLL_DIV2, + BUS_ACLK_PLL_SEL_GPLL_DIV3, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL_DIV2, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL1_CON */ + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, + CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, + + /* CRU_CLK_SEL2_CON */ + NANDC_PLL_SEL_SHIFT = 14, + NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, + NANDC_PLL_SEL_CPLL = 0, + NANDC_PLL_SEL_GPLL, + NANDC_CLK_DIV_SHIFT = 8, + NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, + PVTM_CLK_DIV_SHIFT = 0, + PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, + + /* CRU_CLKSEL10_CON */ + PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT, + PERI_PLL_APLL = 0, + PERI_PLL_DPLL, + PERI_PLL_GPLL, + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL11_CON */ + MMC0_PLL_SHIFT = 6, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_SEL_APLL = 0, + MMC0_SEL_GPLL, + MMC0_SEL_GPLL_DIV2, + MMC0_SEL_24M, + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, + + /* CRU_CLKSEL12_CON */ + EMMC_PLL_SHIFT = 14, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_APLL = 0, + EMMC_SEL_GPLL, + EMMC_SEL_GPLL_DIV2, + EMMC_SEL_24M, + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, + + /* CLKSEL_CON24 */ + SARADC_DIV_CON_SHIFT = 8, + SARADC_DIV_CON_MASK = GENMASK(15, 8), + SARADC_DIV_CON_WIDTH = 8, + + /* CRU_CLKSEL27_CON*/ + DCLK_VOP_SEL_SHIFT = 0, + DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_PLL_SEL_CPLL = 0, + DCLK_VOP_DIV_CON_SHIFT = 8, + DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, + + /* CRU_CLKSEL31_CON */ + VIO0_PLL_SHIFT = 5, + VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, + VI00_SEL_CPLL = 0, + VIO0_SEL_GPLL, + VIO0_DIV_SHIFT = 0, + VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, + VIO1_PLL_SHIFT = 13, + VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, + VI01_SEL_CPLL = 0, + VIO1_SEL_GPLL, + VIO1_DIV_SHIFT = 8, + VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h new file mode 100644 index 00000000000..aa6b693520d --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h @@ -0,0 +1,551 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK3128_H +#define _ASM_ARCH_GRF_RK3128_H + +#include <common.h> + +struct rk3128_grf { + unsigned int reserved[0x2a]; + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + unsigned int gpio3a_iomux; + unsigned int gpio3b_iomux; + unsigned int gpio3c_iomux; + unsigned int gpio3d_iomux; + unsigned int gpio2c_iomux2; + unsigned int grf_cif_iomux; + unsigned int grf_cif_iomux1; + unsigned int reserved1[(0x118 - 0xf0) / 4 - 1]; + unsigned int gpio0l_pull; + unsigned int gpio0h_pull; + unsigned int gpio1l_pull; + unsigned int gpio1h_pull; + unsigned int gpio2l_pull; + unsigned int gpio2h_pull; + unsigned int gpio3l_pull; + unsigned int gpio3h_pull; + unsigned int reserved2; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_status0; + unsigned int reserved3[6]; + unsigned int mac_con0; + unsigned int mac_con1; + unsigned int reserved4[4]; + unsigned int uoc0_con0; + unsigned int reserved5; + unsigned int uoc1_con1; + unsigned int uoc1_con2; + unsigned int uoc1_con3; + unsigned int uoc1_con4; + unsigned int uoc1_con5; + unsigned int reserved6; + unsigned int ddrc_stat; + unsigned int reserved9; + unsigned int soc_status1; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int cpu_con3; + unsigned int reserved10; + unsigned int reserved11; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int os_reg[8]; + unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1]; + unsigned int usbphy0_con[8]; + unsigned int usbphy1_con[8]; + unsigned int uoc_status0; + unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1]; + unsigned int chip_tag; + unsigned int sdmmc_det_cnt; +}; +check_member(rk3128_grf, sdmmc_det_cnt, 0x304); + +struct rk3128_pmu { + unsigned int wakeup_cfg; + unsigned int pwrdn_con; + unsigned int pwrdn_st; + unsigned int idle_req; + unsigned int idle_st; + unsigned int pwrmode_con; + unsigned int pwr_state; + unsigned int osc_cnt; + unsigned int core_pwrdwn_cnt; + unsigned int core_pwrup_cnt; + unsigned int sft_con; + unsigned int ddr_sref_st; + unsigned int int_con; + unsigned int int_st; + unsigned int sys_reg[4]; +}; +check_member(rk3128_pmu, int_st, 0x34); + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A7_SHIFT = 14, + GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, + GPIO0A7_GPIO = 0, + GPIO0A7_I2C3_SDA, + + GPIO0A6_SHIFT = 12, + GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, + GPIO0A6_GPIO = 0, + GPIO0A6_I2C3_SCL, + + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 1 << GPIO0A1_SHIFT, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 1 << GPIO0A0_SHIFT, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, + GPIO0B6_GPIO = 0, + GPIO0B6_I2S_SDI, + GPIO0B6_SPI_CSN0, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, + GPIO0B5_GPIO = 0, + GPIO0B5_I2S_SDO, + GPIO0B5_SPI_RXD, + + GPIO0B4_SHIFT = 8, + GPIO0B4_MASK = 1 << GPIO0B4_SHIFT, + GPIO0B4_GPIO = 0, + GPIO0B4_I2S_LRCKTX, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_I2S_LRCKRX, + GPIO0B3_SPI_TXD, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3, + GPIO0B1_GPIO = 0, + GPIO0B1_I2S_SCLK, + GPIO0B1_SPI_CLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_I2S1_MCLK, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_PWM2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM1, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, + + GPIO0D1_SHIFT = 2, + GPIO0D1_MASK = 1 << GPIO0D1_SHIFT, + GPIO0D1_GPIO = 0, + GPIO0D1_UART2_CTSN, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, + GPIO0D0_GPIO = 0, + GPIO0D0_UART2_RTSN, + GPIO0D0_PMIC_SLEEP, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 3 << GPIO1A5_SHIFT, + GPIO1A5_GPIO = 0, + GPIO1A5_I2S_SDI, + GPIO1A5_SDMMC_DATA3, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 3 << GPIO1A4_SHIFT, + GPIO1A4_GPIO = 0, + GPIO1A4_I2S_SD0, + GPIO1A4_SDMMC_DATA2, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, + GPIO1A3_GPIO = 0, + GPIO1A3_I2S_LRCKTX, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, + GPIO1A2_GPIO = 0, + GPIO1A2_I2S_LRCKRX, + GPIO1A2_SDMMC_DATA1, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 3 << GPIO1A1_SHIFT, + GPIO1A1_GPIO = 0, + GPIO1A1_I2S_SCLK, + GPIO1A1_SDMMC_DATA0, + GPIO1A1_PMIC_SLEEP, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 3, + GPIO1A0_GPIO = 0, + GPIO1A0_I2S_MCLK, + GPIO1A0_SDMMC_CLKOUT, + GPIO1A0_XIN32K, + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_MMC0_CMD, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 1 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_MMC_PWREN, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_SPI_RXD, + GPIO1B2_UART1_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_SPI_TXD, + GPIO1B1_UART1_SOUT, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3 << GPIO1B0_SHIFT, + GPIO1B0_GPIO = 0, + GPIO1B0_SPI_CLK, + GPIO1B0_UART1_CTSN +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_NAND_CS2, + GPIO1C6_EMMC_CMD, + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_MMC0_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_MMC0_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_RX, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_TX, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_MMC0_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, + GPIO1C0_GPIO = 0, + GPIO1C0_MMC0_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + GPIO1D7_SPI_CSN1, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + GPIO1D6_SPI_CSN0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + GPIO1D5_SPI_TXD1, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + GPIO1D4_SPI_RXD1, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + GPIO1D3_SFC_SIO3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + GPIO1D2_SFC_SIO2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + GPIO1D1_SFC_SIO1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, + GPIO1D0_SFC_SIO0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_NAND_DQS, + GPIO2A7_EMMC_CLKOUT, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_NAND_CS0, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_NAND_WP, + GPIO2A5_EMMC_PWREN, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + GPIO2A3_SFC_CLK, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SFC_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SFC_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_EMMC_CLKOUT, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI_CLK, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_LCDC0_D13, + GPIO2B7_EBC_SDCE5, + GPIO2B7_GMAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_LCDC0_D12, + GPIO2B6_EBC_SDCE4, + GPIO2B6_GMAC_CLK, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_LCDC0_D11, + GPIO2B5_EBC_SDCE3, + GPIO2B5_GMAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_LCDC0_D10, + GPIO2B4_EBC_SDCE2, + GPIO2B4_GMAC_MDIO, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_LCDC0_DEN, + GPIO2B3_EBC_GDCLK, + GPIO2B3_GMAC_RXCLK, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_LCDC0_VSYNC, + GPIO2B2_EBC_SDOE, + GPIO2B2_GMAC_CRS, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_LCDC0_HSYNC, + GPIO2B1_EBC_SDLE, + GPIO2B1_GMAC_TXCLK, + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_LCDC0_DCLK, + GPIO2B0_EBC_SDCLK, + GPIO2B0_GMAC_RXDV, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_LCDC0_D17, + GPIO2C3_EBC_GDPWR0, + GPIO2C3_GMAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, + GPIO2C2_GPIO = 0, + GPIO2C2_LCDC0_D16, + GPIO2C2_EBC_GDSP, + GPIO2C2_GMAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, + GPIO2C1_GPIO = 0, + GPIO2C1_LCDC0_D15, + GPIO2C1_EBC_GDOE, + GPIO2C1_GMAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, + GPIO2C0_GPIO = 0, + GPIO2C0_LCDC0_D14, + GPIO2C0_EBC_VCOM, + GPIO2C0_GMAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_LCDC0_D22, + GPIO2D6_GMAC_COL = 4, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_GMAC_MDC = 3, +}; + +/* GRF_GPIO2C_IOMUX2 */ +enum { + GPIO2C7_SHIFT = 12, + GPIO2C7_MASK = 7 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_GMAC_TXD3 = 4, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 7 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_GMAC_TXD2 = 4, + + GPIO2C5_SHIFT = 4, + GPIO2C5_MASK = 7 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL = 3, + GPIO2C5_GMAC_RXD2, + + GPIO2C4_SHIFT = 0, + GPIO2C4_MASK = 7 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA = 3, + GPIO2C4_GMAC_RXD2, +}; +#endif diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 6cc19664dd3..e9f3aabb6fc 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -42,41 +42,6 @@ struct stm32_u_id_regs { u32 u_id_high; }; -struct stm32_rcc_regs { - u32 cr; /* RCC clock control */ - u32 pllcfgr; /* RCC PLL configuration */ - u32 cfgr; /* RCC clock configuration */ - u32 cir; /* RCC clock interrupt */ - u32 ahb1rstr; /* RCC AHB1 peripheral reset */ - u32 ahb2rstr; /* RCC AHB2 peripheral reset */ - u32 ahb3rstr; /* RCC AHB3 peripheral reset */ - u32 rsv0; - u32 apb1rstr; /* RCC APB1 peripheral reset */ - u32 apb2rstr; /* RCC APB2 peripheral reset */ - u32 rsv1[2]; - u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ - u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ - u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ - u32 rsv2; - u32 apb1enr; /* RCC APB1 peripheral clock enable */ - u32 apb2enr; /* RCC APB2 peripheral clock enable */ - u32 rsv3[2]; - u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ - u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ - u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ - u32 rsv4; - u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ - u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ - u32 rsv5[2]; - u32 bdcr; /* RCC Backup domain control */ - u32 csr; /* RCC clock control & status */ - u32 rsv6[2]; - u32 sscgr; /* RCC spread spectrum clock generation */ - u32 plli2scfgr; /* RCC PLLI2S configuration */ - u32 pllsaicfgr; - u32 dckcfgr; -}; - struct stm32_pwr_regs { u32 cr; u32 csr; diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h new file mode 100644 index 00000000000..bfe54698b34 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_PWR_H_ + +/* + * Offsets of some PWR registers + */ +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17) + +struct stm32_pwr_regs { + u32 cr1; /* power control register 1 */ + u32 csr1; /* power control/status register 2 */ +}; + +#endif /* __STM32_PWR_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h deleted file mode 100644 index 6475f9d5c89..00000000000 --- a/arch/arm/include/asm/arch-stm32f7/rcc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _STM32_RCC_H -#define _STM32_RCC_H - -#include <dt-bindings/mfd/stm32f7-rcc.h> - -/* - * RCC AHB1ENR specific definitions - */ -#define RCC_AHB1ENR_ETHMAC_EN BIT(25) -#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) -#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) - -/* - * RCC APB1ENR specific definitions - */ -#define RCC_APB1ENR_TIM2EN BIT(0) -#define RCC_APB1ENR_PWREN BIT(28) - -/* - * RCC APB2ENR specific definitions - */ -#define RCC_APB2ENR_SYSCFGEN BIT(14) - -#endif diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index d6412a00cc6..f54e6f19557 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -59,49 +59,8 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { #define STM32_BUS_MASK GENMASK(31, 16) -struct stm32_rcc_regs { - u32 cr; /* RCC clock control */ - u32 pllcfgr; /* RCC PLL configuration */ - u32 cfgr; /* RCC clock configuration */ - u32 cir; /* RCC clock interrupt */ - u32 ahb1rstr; /* RCC AHB1 peripheral reset */ - u32 ahb2rstr; /* RCC AHB2 peripheral reset */ - u32 ahb3rstr; /* RCC AHB3 peripheral reset */ - u32 rsv0; - u32 apb1rstr; /* RCC APB1 peripheral reset */ - u32 apb2rstr; /* RCC APB2 peripheral reset */ - u32 rsv1[2]; - u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ - u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ - u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ - u32 rsv2; - u32 apb1enr; /* RCC APB1 peripheral clock enable */ - u32 apb2enr; /* RCC APB2 peripheral clock enable */ - u32 rsv3[2]; - u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ - u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ - u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ - u32 rsv4; - u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ - u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ - u32 rsv5[2]; - u32 bdcr; /* RCC Backup domain control */ - u32 csr; /* RCC clock control & status */ - u32 rsv6[2]; - u32 sscgr; /* RCC spread spectrum clock generation */ - u32 plli2scfgr; /* RCC PLLI2S configuration */ - u32 pllsaicfgr; /* PLLSAI configuration */ - u32 dckcfgr; /* dedicated clocks configuration register */ -}; #define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE) -struct stm32_pwr_regs { - u32 cr1; /* power control register 1 */ - u32 csr1; /* power control/status register 2 */ - u32 cr2; /* power control register 2 */ - u32 csr2; /* power control/status register 2 */ -}; -#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE) void stm32_flash_latency_cfg(int latency); diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h new file mode 100644 index 00000000000..917dd46d985 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_PWR_H_ + +/* + * Offsets of some PWR registers + */ +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17) + +struct stm32_pwr_regs { + u32 cr1; /* power control register 1 */ + u32 csr1; /* power control/status register 2 */ + u32 cr2; /* power control register 2 */ + u32 csr2; /* power control/status register 2 */ +}; + +#endif /* __STM32_PWR_H_ */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 6121aab547f..765914c7e26 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -43,6 +43,7 @@ #define PTE_TYPE_MASK (3 << 0) #define PTE_TYPE_FAULT (0 << 0) #define PTE_TYPE_TABLE (3 << 0) +#define PTE_TYPE_PAGE (3 << 0) #define PTE_TYPE_BLOCK (1 << 0) #define PTE_TYPE_VALID (1 << 0) diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 7c9cfce69fa..cbcfeec2b03 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -9,6 +9,7 @@ #include <linux/compiler.h> #include <efi_loader.h> +DECLARE_GLOBAL_DATA_PTR; int interrupt_init(void) { @@ -29,8 +30,13 @@ void show_regs(struct pt_regs *regs) { int i; - printf("ELR: %lx\n", regs->elr); - printf("LR: %lx\n", regs->regs[30]); + if (gd->flags & GD_FLG_RELOC) { + printf("ELR: %lx\n", regs->elr - gd->reloc_off); + printf("LR: %lx\n", regs->regs[30] - gd->reloc_off); + } else { + printf("ELR: %lx\n", regs->elr); + printf("LR: %lx\n", regs->regs[30]); + } for (i = 0; i < 29; i += 2) printf("x%-2d: %016lx x%-2d: %016lx\n", i, regs->regs[i], i+1, regs->regs[i+1]); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 7e85b69679d..69072635392 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -143,10 +143,9 @@ config TARGET_AT91SAM9X5EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT -config TARGET_SAMA5D2_PTC - bool "SAMA5D2 PTC board" +config TARGET_SAMA5D2_PTC_EK + bool "SAMA5D2 PTC EK board" select SAMA5D2 - select SUPPORT_SPL select BOARD_EARLY_INIT_F config TARGET_SAMA5D2_XPLAINED @@ -237,6 +236,18 @@ config TARGET_VINCO select SAMA5D4 select SUPPORT_SPL +config TARGET_WB45N + bool "Support Laird WB45N" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_WB50N + bool "Support Laird WB50N" + select BOARD_LATE_INIT + select CPU_V7 + select SUPPORT_SPL + select BOARD_EARLY_INIT_F + endchoice config SYS_SOC @@ -251,7 +262,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" -source "board/atmel/sama5d2_ptc/Kconfig" +source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" @@ -271,6 +282,8 @@ source "board/ronetix/pm9g45/Kconfig" source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" +source "board/laird/wb45n/Kconfig" +source "board/laird/wb50n/Kconfig" config SPL_LDSCRIPT default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index df0f71975ad..e2063167359 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin) at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_B_periph(x, y) \ at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y) +#define at91_set_gpio_deglitch(x, y) \ + at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_output(x, y) \ at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_input(x, y) \ diff --git a/arch/arm/mach-at91/include/mach/sama5d2_smc.h b/arch/arm/mach-at91/include/mach/sama5d2_smc.h new file mode 100644 index 00000000000..7ddb728cf3e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2_smc.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2017 Microchip Corporation. + * + * Static Memory Controllers (SMC) - System peripherals registers. + * Based on SAMA5D2 datasheet. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SAMA5D2_SMC_H +#define SAMA5D2_SMC_H + +#ifdef __ASSEMBLY__ +#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700) +#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704) +#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708) +#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c) +#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710) +#else +struct at91_cs { + u32 setup; /* 0x600 SMC Setup Register */ + u32 pulse; /* 0x604 SMC Pulse Register */ + u32 cycle; /* 0x608 SMC Cycle Register */ + u32 timings; /* 0x60C SMC Cycle Register */ + u32 mode; /* 0x610 SMC Mode Register */ +}; + +struct at91_smc { + struct at91_cs cs[4]; +}; +#endif /* __ASSEMBLY__ */ + +#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) +#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) +#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) +#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) + +#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) +#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) +#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) +#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) + +#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) +#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) + +#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) +#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) +#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) +#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) +#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) +#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) +#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) +#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) + +#define AT91_SMC_MODE_RM_NCS 0x00000000 +#define AT91_SMC_MODE_RM_NRD 0x00000001 +#define AT91_SMC_MODE_WM_NCS 0x00000000 +#define AT91_SMC_MODE_WM_NWE 0x00000002 + +#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 +#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 +#define AT91_SMC_MODE_EXNW_READY 0x00000030 + +#define AT91_SMC_MODE_BAT 0x00000100 +#define AT91_SMC_MODE_DBW_8 0x00000000 +#define AT91_SMC_MODE_DBW_16 0x00001000 +#define AT91_SMC_MODE_DBW_32 0x00002000 +#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) +#define AT91_SMC_MODE_TDF 0x00100000 +#define AT91_SMC_MODE_PMEN 0x01000000 +#define AT91_SMC_MODE_PS_4 0x00000000 +#define AT91_SMC_MODE_PS_8 0x10000000 +#define AT91_SMC_MODE_PS_16 0x20000000 +#define AT91_SMC_MODE_PS_32 0x30000000 + +#endif diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 69f7a4663cf..a78239d63e4 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -44,6 +44,22 @@ config TARGET_RPI This option creates a build targetting the ARM1176 ISA. select BCM2835 +config TARGET_RPI_0_W + bool "Raspberry Pi Zero W" + help + Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as + the RPi Zero model W. + + This option assumes the VideoCore firmware is configured to use the + mini UART (rather than PL011) for the serial console. This is the + default on the RPi Zero W. To enable the UART console, the following + non-default option must be present in config.txt: enable_uart=1. + This is required for U-Boot to operate correctly, even if you only + care about the HDMI/usbkbd console. + + This option creates a build targetting the ARMv7/AArch32 ISA. + select BCM2835 + config TARGET_RPI_2 bool "Raspberry Pi 2" help diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index d4bd230be3b..0350787daa7 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -38,6 +38,20 @@ config TARGET_P212 with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot, eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module. +config TARGET_LIBRETECH_CC + bool "LIBRETECH-CC" + help + LibreTech CC is a single board computer based on Meson GXL + with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, + eMMC, IR receiver and a 40-pin GPIO header. + +config TARGET_KHADAS_VIM + bool "KHADAS-VIM" + help + Khadas VIM is a single board computer based on Meson GXL + with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, + eMMC, IR receiver and a 40-pin GPIO header. + endif config SYS_SOC @@ -50,4 +64,8 @@ source "board/amlogic/odroid-c2/Kconfig" source "board/amlogic/p212/Kconfig" +source "board/amlogic/libretech-cc/Kconfig" + +source "board/amlogic/khadas-vim/Kconfig" + endif diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index bf49b8b1e57..b4e8dded14c 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o sm.o +obj-y += board.o sm.o eth.o diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c index e89c6aace98..908a0cae560 100644 --- a/arch/arm/mach-meson/board.c +++ b/arch/arm/mach-meson/board.c @@ -11,6 +11,9 @@ #include <asm/arch/sm.h> #include <asm/armv8/mmu.h> #include <asm/unaligned.h> +#include <linux/sizes.h> +#include <efi_loader.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -34,15 +37,70 @@ int dram_init(void) return 0; } -int dram_init_banksize(void) +phys_size_t get_effective_memsize(void) { - /* Reserve first 16 MiB of RAM for firmware */ - gd->bd->bi_dram[0].start = 0x1000000; - gd->bd->bi_dram[0].size = 0xf000000; - /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */ - gd->bd->bi_dram[1].start = 0x10000000; - gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000; - return 0; + /* Size is reported in MiB, convert it in bytes */ + return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK) + >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) +{ + int ret; + + ret = fdt_add_mem_rsv(fdt, start, size); + if (ret) + printf("Could not reserve zone @ 0x%llx\n", start); + + if (IS_ENABLED(CONFIG_EFI_LOADER)) { + efi_add_memory_map(start, + ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, + EFI_RESERVED_MEMORY_TYPE, false); + } +} + +void meson_gx_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + + reg = readl(GXBB_AO_SEC_GP_CFG3); + + bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK) + >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(GXBB_AO_SEC_GP_CFG5); + bl32_start = readl(GXBB_AO_SEC_GP_CFG4); + + /* + * Early Meson GXBB Firmware revisions did not provide the reserved + * memory zones in the registers, keep fixed memory zone handling. + */ + if (IS_ENABLED(CONFIG_MESON_GXBB) && + !reg && !bl31_start && !bl32_start) { + bl31_start = 0x10000000; + bl31_size = 0x200000; + } + + /* Add first 16MiB reserved zone */ + meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); } void reset_cpu(ulong addr) diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c new file mode 100644 index 00000000000..2debe93952c --- /dev/null +++ b/arch/arm/mach-meson/eth.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/gxbb.h> +#include <asm/arch/eth.h> +#include <phy.h> + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | + GXBB_ETH_REG_0_TX_PHASE(1) | + GXBB_ETH_REG_0_TX_RATIO(4) | + GXBB_ETH_REG_0_PHY_CLK_EN | + GXBB_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK | + GXBB_ETH_REG_0_CLK_EN); + + /* Use GXL RMII Internal PHY */ + if (IS_ENABLED(CONFIG_MESON_GXL) && + (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { + writel(GXBB_ETH_REG_2, 0x10110181); + writel(GXBB_ETH_REG_3, 0xe40908ff); + } + + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power and clock gate */ + setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); + clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); +} diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1d302761f09..1a06a1e8760 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -111,10 +111,16 @@ #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) /* BootROM error register (also includes some status infos) */ +#if defined(CONFIG_ARMADA_38X) +#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) +#define BOOTROM_ERR_MODE_OFFS 0 +#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) +#else #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) #define BOOTROM_ERR_MODE_OFFS 28 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) #define BOOTROM_ERR_MODE_UART 0x6 +#endif #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ @@ -141,6 +147,7 @@ #define BOOT_DEV_SEL_OFFS 4 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) +#define BOOT_FROM_NAND 0x0A #define BOOT_FROM_UART 0x28 #define BOOT_FROM_UART_ALT 0x3f #define BOOT_FROM_SPI 0x32 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index a72a769f7c7..d16a62d2dd3 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -26,7 +26,16 @@ static u32 get_boot_device(void) val = readl(CONFIG_BOOTROM_ERR_REG); boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); +#if defined(CONFIG_ARMADA_38X) + /* + * If the bootrom error register contains any else than zeros + * in the first 8 bits it's an error condition. And in that case + * try to boot from UART. + */ + if (boot_device) +#else if (boot_device == BOOTROM_ERR_MODE_UART) +#endif return BOOT_DEVICE_UART; /* @@ -36,6 +45,10 @@ static u32 get_boot_device(void) boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); switch (boot_device) { +#if defined(CONFIG_ARMADA_38X) + case BOOT_FROM_NAND: + return BOOT_DEVICE_NAND; +#endif #ifdef CONFIG_SPL_MMC_SUPPORT case BOOT_FROM_MMC: case BOOT_FROM_MMC_ALT: @@ -119,7 +132,15 @@ void board_init_f(ulong dummy) * SPL has no chance to receive this information. So we * need to return to the BootROM to enable this xmodem * UART download. + * + * If booting from NAND lets let the BootROM load the + * rest of the bootloader. */ - if (get_boot_device() == BOOT_DEVICE_UART) - return_to_bootrom(); + switch (get_boot_device()) { + case BOOT_DEVICE_UART: +#if defined(CONFIG_ARMADA_38X) + case BOOT_DEVICE_NAND: +#endif + return_to_bootrom(); + } } diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 2e8778043b7..d11670c0eee 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -215,6 +215,9 @@ void omap_die_id_usbethaddr(void) mac[5] = (die_id[0] >> 8) & 0xff; eth_env_set_enetaddr("usbethaddr", mac); + + if (!env_get("ethaddr")) + eth_env_set_enetaddr("ethaddr", mac); } } diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 2aea527bae2..39493788061 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o -obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o -obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o +obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-rmobile/board.c index d91bc26703a..bdb353062fe 100644 --- a/arch/arm/mach-rmobile/board.c +++ b/arch/arm/mach-rmobile/board.c @@ -8,8 +8,10 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> +#ifndef CONFIG_RCAR_GEN3 int checkboard(void) { printf("Board: %s\n", sysinfo.board_string); return 0; } +#endif diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index c373eef73d4..b443611cbb3 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -8,19 +8,20 @@ #include <common.h> #include <asm/io.h> -#define PRR 0xFF000044 #define PRR_MASK 0x7fff #define R8A7796_REV_1_0 0x5200 #define R8A7796_REV_1_1 0x5210 +static u32 rmobile_get_prr(void); + u32 rmobile_get_cpu_type(void) { - return (readl(PRR) & 0x00007F00) >> 8; + return (rmobile_get_prr() & 0x00007F00) >> 8; } u32 rmobile_get_cpu_rev_integer(void) { - const u32 prr = readl(PRR); + const u32 prr = rmobile_get_prr(); if ((prr & PRR_MASK) == R8A7796_REV_1_1) return 1; @@ -30,10 +31,62 @@ u32 rmobile_get_cpu_rev_integer(void) u32 rmobile_get_cpu_rev_fraction(void) { - const u32 prr = readl(PRR); + const u32 prr = rmobile_get_prr(); if ((prr & PRR_MASK) == R8A7796_REV_1_1) return 1; else return prr & 0x0000000F; } + +#if !CONFIG_IS_ENABLED(DM) || !CONFIG_IS_ENABLED(SYSCON) +static u32 rmobile_get_prr(void) +{ + /* + * On RCar/RMobile Gen2 and older systems, the PRR is always + * located at the address below. On newer systems, the PRR + * may be located at different address, but that information + * is obtained from DT. This code will be removed when all + * of the older systems get converted to DM and OF control. + */ + return readl(0xFF000044); +} +#else + +#include <dm.h> +#include <syscon.h> +#include <regmap.h> + +struct renesas_prr_priv { + fdt_addr_t regs; +}; + +enum { + PRR_RCAR, +}; + +static u32 rmobile_get_prr(void) +{ + struct regmap *map; + + map = syscon_get_regmap_by_driver_data(PRR_RCAR); + if (!map) { + printf("PRR regmap failed!\n"); + hang(); + } + + return readl(map->base); +} + +static const struct udevice_id renesas_prr_ids[] = { + { .compatible = "renesas,prr", .data = PRR_RCAR }, + { } +}; + +U_BOOT_DRIVER(renesas_prr) = { + .name = "renesas_prr", + .id = UCLASS_SYSCON, + .of_match = renesas_prr_ids, + .flags = DM_FLAG_PRE_RELOC, +}; +#endif diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index faa53197d5b..5c8cb3f666a 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -18,6 +18,9 @@ int arch_cpu_init(void) #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { +#if defined(CONFIG_RCAR_GEN3) + rcar_gen3_memmap_fixup(); +#endif dcache_enable(); } #endif @@ -49,15 +52,15 @@ static const struct { u16 cpu_type; u8 cpu_name[10]; } rmobile_cpuinfo[] = { - { 0x37, "SH73A0" }, - { 0x40, "R8A7740" }, - { 0x45, "R8A7790" }, - { 0x47, "R8A7791" }, - { 0x4A, "R8A7792" }, - { 0x4B, "R8A7793" }, - { 0x4C, "R8A7794" }, - { 0x4F, "R8A7795" }, - { 0x52, "R8A7796" }, + { RMOBILE_CPU_TYPE_SH73A0, "SH73A0" }, + { RMOBILE_CPU_TYPE_R8A7740, "R8A7740" }, + { RMOBILE_CPU_TYPE_R8A7790, "R8A7790" }, + { RMOBILE_CPU_TYPE_R8A7791, "R8A7791" }, + { RMOBILE_CPU_TYPE_R8A7792, "R8A7792" }, + { RMOBILE_CPU_TYPE_R8A7793, "R8A7793" }, + { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" }, + { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" }, + { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h index 02b29364c54..448d189e926 100644 --- a/arch/arm/mach-rmobile/include/mach/gpio.h +++ b/arch/arm/mach-rmobile/include/mach/gpio.h @@ -22,12 +22,6 @@ void r8a7793_pinmux_init(void); #elif defined(CONFIG_R8A7794) #include "r8a7794-gpio.h" void r8a7794_pinmux_init(void); -#elif defined(CONFIG_R8A7795) -#include "r8a7795-gpio.h" -void r8a7795_pinmux_init(void); -#elif defined(CONFIG_R8A7796) -#include "r8a7796-gpio.h" -void r8a7796_pinmux_init(void); #endif #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h deleted file mode 100644 index 554063ab8fe..00000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h +++ /dev/null @@ -1,1016 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h - * This file defines pin function control of gpio. - * - * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_R8A7795_GPIO_H__ -#define __ASM_R8A7795_GPIO_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ - -/* V2(ES2.0) */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, - GPIO_GP_1_28, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, - - GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, - GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, - GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, - GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, - GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, - GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, - GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, - GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, - - GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, - - /* GPSR0 */ - GPIO_GFN_D15, - GPIO_GFN_D14, - GPIO_GFN_D13, - GPIO_GFN_D12, - GPIO_GFN_D11, - GPIO_GFN_D10, - GPIO_GFN_D9, - GPIO_GFN_D8, - GPIO_GFN_D7, - GPIO_GFN_D6, - GPIO_GFN_D5, - GPIO_GFN_D4, - GPIO_GFN_D3, - GPIO_GFN_D2, - GPIO_GFN_D1, - GPIO_GFN_D0, - - /* GPSR1 */ - GPIO_GFN_CLKOUT, - GPIO_GFN_EX_WAIT0_A, - GPIO_GFN_WE1x, - GPIO_GFN_WE0x, - GPIO_GFN_RD_WRx, - GPIO_GFN_RDx, - GPIO_GFN_BSx, - GPIO_GFN_CS1x_A26, - GPIO_GFN_CS0x, - GPIO_GFN_A19, - GPIO_GFN_A18, - GPIO_GFN_A17, - GPIO_GFN_A16, - GPIO_GFN_A15, - GPIO_GFN_A14, - GPIO_GFN_A13, - GPIO_GFN_A12, - GPIO_GFN_A11, - GPIO_GFN_A10, - GPIO_GFN_A9, - GPIO_GFN_A8, - GPIO_GFN_A7, - GPIO_GFN_A6, - GPIO_GFN_A5, - GPIO_GFN_A4, - GPIO_GFN_A3, - GPIO_GFN_A2, - GPIO_GFN_A1, - GPIO_GFN_A0, - - /* GPSR2 */ - GPIO_GFN_AVB_AVTP_CAPTURE_A, - GPIO_GFN_AVB_AVTP_MATCH_A, - GPIO_GFN_AVB_LINK, - GPIO_GFN_AVB_PHY_INT, - GPIO_GFN_AVB_MAGIC, - GPIO_GFN_AVB_MDC, - GPIO_GFN_PWM2_A, - GPIO_GFN_PWM1_A, - GPIO_GFN_PWM0, - GPIO_GFN_IRQ5, - GPIO_GFN_IRQ4, - GPIO_GFN_IRQ3, - GPIO_GFN_IRQ2, - GPIO_GFN_IRQ1, - GPIO_GFN_IRQ0, - - /* GPSR3 */ - GPIO_GFN_SD1_WP, - GPIO_GFN_SD1_CD, - GPIO_GFN_SD0_WP, - GPIO_GFN_SD0_CD, - GPIO_GFN_SD1_DAT3, - GPIO_GFN_SD1_DAT2, - GPIO_GFN_SD1_DAT1, - GPIO_GFN_SD1_DAT0, - GPIO_GFN_SD1_CMD, - GPIO_GFN_SD1_CLK, - GPIO_GFN_SD0_DAT3, - GPIO_GFN_SD0_DAT2, - GPIO_GFN_SD0_DAT1, - GPIO_GFN_SD0_DAT0, - GPIO_GFN_SD0_CMD, - GPIO_GFN_SD0_CLK, - - /* GPSR4 */ - GPIO_GFN_SD3_DS, - GPIO_GFN_SD3_DAT7, - GPIO_GFN_SD3_DAT6, - GPIO_GFN_SD3_DAT5, - GPIO_GFN_SD3_DAT4, - GPIO_GFN_SD3_DAT3, - GPIO_GFN_SD3_DAT2, - GPIO_GFN_SD3_DAT1, - GPIO_GFN_SD3_DAT0, - GPIO_GFN_SD3_CMD, - GPIO_GFN_SD3_CLK, - GPIO_GFN_SD2_DS, - GPIO_GFN_SD2_DAT3, - GPIO_GFN_SD2_DAT2, - GPIO_GFN_SD2_DAT1, - GPIO_GFN_SD2_DAT0, - GPIO_GFN_SD2_CMD, - GPIO_GFN_SD2_CLK, - - /* GPSR5 */ - GPIO_GFN_MLB_DAT, - GPIO_GFN_MLB_SIG, - GPIO_GFN_MLB_CLK, - GPIO_FN_MSIOF0_RXD, - GPIO_GFN_MSIOF0_SS2, - GPIO_FN_MSIOF0_TXD, - GPIO_GFN_MSIOF0_SS1, - GPIO_GFN_MSIOF0_SYNC, - GPIO_FN_MSIOF0_SCK, - GPIO_GFN_HRTS0x, - GPIO_GFN_HCTS0x, - GPIO_GFN_HTX0, - GPIO_GFN_HRX0, - GPIO_GFN_HSCK0, - GPIO_GFN_RX2_A, - GPIO_GFN_TX2_A, - GPIO_GFN_SCK2, - GPIO_GFN_RTS1x_TANS, - GPIO_GFN_CTS1x, - GPIO_GFN_TX1_A, - GPIO_GFN_RX1_A, - GPIO_GFN_RTS0x_TANS, - GPIO_GFN_CTS0x, - GPIO_GFN_TX0, - GPIO_GFN_RX0, - GPIO_GFN_SCK0, - - /* GPSR6 */ - GPIO_GFN_USB3_OVC, - GPIO_GFN_USB3_PWEN, - GPIO_GFN_USB30_OVC, - GPIO_GFN_USB30_PWEN, - GPIO_GFN_USB1_OVC, - GPIO_GFN_USB1_PWEN, - GPIO_GFN_USB0_OVC, - GPIO_GFN_USB0_PWEN, - GPIO_GFN_AUDIO_CLKB_B, - GPIO_GFN_AUDIO_CLKA_A, - GPIO_GFN_SSI_SDATA9_A, - GPIO_GFN_SSI_SDATA8, - GPIO_GFN_SSI_SDATA7, - GPIO_GFN_SSI_WS78, - GPIO_GFN_SSI_SCK78, - GPIO_GFN_SSI_SDATA6, - GPIO_GFN_SSI_WS6, - GPIO_GFN_SSI_SCK6, - GPIO_FN_SSI_SDATA5, - GPIO_FN_SSI_WS5, - GPIO_FN_SSI_SCK5, - GPIO_GFN_SSI_SDATA4, - GPIO_GFN_SSI_WS4, - GPIO_GFN_SSI_SCK4, - GPIO_GFN_SSI_SDATA3, - GPIO_GFN_SSI_WS34, - GPIO_GFN_SSI_SCK34, - GPIO_GFN_SSI_SDATA2_A, - GPIO_GFN_SSI_SDATA1_A, - GPIO_GFN_SSI_SDATA0, - GPIO_GFN_SSI_WS01239, - GPIO_GFN_SSI_SCK01239, - - /* GPSR7 */ - GPIO_FN_HDMI1_CEC, - GPIO_FN_HDMI0_CEC, - GPIO_FN_AVS2, - GPIO_FN_AVS1, - - /* IPSR0 */ - GPIO_IFN_AVB_MDC, - GPIO_FN_MSIOF2_SS2_C, - GPIO_IFN_AVB_MAGIC, - GPIO_FN_MSIOF2_SS1_C, - GPIO_FN_SCK4_A, - GPIO_IFN_AVB_PHY_INT, - GPIO_FN_MSIOF2_SYNC_C, - GPIO_FN_RX4_A, - GPIO_IFN_AVB_LINK, - GPIO_FN_MSIOF2_SCK_C, - GPIO_FN_TX4_A, - GPIO_IFN_AVB_AVTP_MATCH_A, - GPIO_FN_MSIOF2_RXD_C, - GPIO_FN_CTS4x_A, - GPIO_FN_FSCLKST2x_A, - GPIO_IFN_AVB_AVTP_CAPTURE_A, - GPIO_FN_MSIOF2_TXD_C, - GPIO_FN_RTS4x_TANS_A, - GPIO_IFN_IRQ0, - GPIO_FN_QPOLB, - GPIO_FN_DU_CDE, - GPIO_FN_VI4_DATA0_B, - GPIO_FN_CAN0_TX_B, - GPIO_FN_CANFD0_TX_B, - GPIO_FN_MSIOF3_SS2_E, - GPIO_IFN_IRQ1, - GPIO_FN_QPOLA, - GPIO_FN_DU_DISP, - GPIO_FN_VI4_DATA1_B, - GPIO_FN_CAN0_RX_B, - GPIO_FN_CANFD0_RX_B, - GPIO_FN_MSIOF3_SS1_E, - - /* IPSR1 */ - GPIO_IFN_IRQ2, - GPIO_FN_QCPV_QDE, - GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE, - GPIO_FN_VI4_DATA2_B, - GPIO_FN_MSIOF3_SYNC_E, - GPIO_FN_PWM3_B, - GPIO_IFN_IRQ3, - GPIO_FN_QSTVB_QVE, - GPIO_FN_A25, - GPIO_FN_DU_DOTCLKOUT1, - GPIO_FN_VI4_DATA3_B, - GPIO_FN_MSIOF3_SCK_E, - GPIO_FN_PWM4_B, - GPIO_IFN_IRQ4, - GPIO_FN_QSTH_QHS, - GPIO_FN_A24, - GPIO_FN_DU_EXHSYNC_DU_HSYNC, - GPIO_FN_VI4_DATA4_B, - GPIO_FN_MSIOF3_RXD_E, - GPIO_FN_PWM5_B, - GPIO_IFN_IRQ5, - GPIO_FN_QSTB_QHE, - GPIO_FN_A23, - GPIO_FN_DU_EXVSYNC_DU_VSYNC, - GPIO_FN_VI4_DATA5_B, - GPIO_FN_FSCLKST2x_B, - GPIO_FN_MSIOF3_TXD_E, - GPIO_FN_PWM6_B, - GPIO_IFN_PWM0, - GPIO_FN_AVB_AVTP_PPS, - GPIO_FN_VI4_DATA6_B, - GPIO_FN_IECLK_B, - GPIO_IFN_PWM1_A, - GPIO_FN_HRX3_D, - GPIO_FN_VI4_DATA7_B, - GPIO_FN_IERX_B, - GPIO_IFN_PWM2_A, - GPIO_FN_HTX3_D, - GPIO_FN_IETX_B, - GPIO_IFN_A0, - GPIO_FN_LCDOUT16, - GPIO_FN_MSIOF3_SYNC_B, - GPIO_FN_VI4_DATA8, - GPIO_FN_DU_DB0, - GPIO_FN_PWM3_A, - - /* IPSR2 */ - GPIO_IFN_A1, - GPIO_FN_LCDOUT17, - GPIO_FN_MSIOF3_TXD_B, - GPIO_FN_VI4_DATA9, - GPIO_FN_DU_DB1, - GPIO_FN_PWM4_A, - GPIO_IFN_A2, - GPIO_FN_LCDOUT18, - GPIO_FN_MSIOF3_SCK_B, - GPIO_FN_VI4_DATA10, - GPIO_FN_DU_DB2, - GPIO_FN_PWM5_A, - GPIO_IFN_A3, - GPIO_FN_LCDOUT19, - GPIO_FN_MSIOF3_RXD_B, - GPIO_FN_VI4_DATA11, - GPIO_FN_DU_DB3, - GPIO_FN_PWM6_A, - GPIO_IFN_A4, - GPIO_FN_LCDOUT20, - GPIO_FN_MSIOF3_SS1_B, - GPIO_FN_VI4_DATA12, - GPIO_FN_VI5_DATA12, - GPIO_FN_DU_DB4, - GPIO_IFN_A5, - GPIO_FN_LCDOUT21, - GPIO_FN_MSIOF3_SS2_B, - GPIO_FN_SCK4_B, - GPIO_FN_VI4_DATA13, - GPIO_FN_VI5_DATA13, - GPIO_FN_DU_DB5, - GPIO_IFN_A6, - GPIO_FN_LCDOUT22, - GPIO_FN_MSIOF2_SS1_A, - GPIO_FN_RX4_B, - GPIO_FN_VI4_DATA14, - GPIO_FN_VI5_DATA14, - GPIO_FN_DU_DB6, - GPIO_IFN_A7, - GPIO_FN_LCDOUT23, - GPIO_FN_MSIOF2_SS2_A, - GPIO_FN_TX4_B, - GPIO_FN_VI4_DATA15, - GPIO_FN_V15_DATA15, - GPIO_FN_DU_DB7, - GPIO_IFN_A8, - GPIO_FN_RX3_B, - GPIO_FN_MSIOF2_SYNC_A, - GPIO_FN_HRX4_B, - GPIO_FN_SDA6_A, - GPIO_FN_AVB_AVTP_MATCH_B, - GPIO_FN_PWM1_B, - - /* IPSR3 */ - GPIO_IFN_A9, - GPIO_FN_MSIOF2_SCK_A, - GPIO_FN_CTS4x_B, - GPIO_FN_VI5_VSYNCx, - GPIO_IFN_A10, - GPIO_FN_MSIOF2_RXD_A, - GPIO_FN_RTS4n_TANS_B, - GPIO_FN_VI5_HSYNCx, - GPIO_IFN_A11, - GPIO_FN_TX3_B, - GPIO_FN_MSIOF2_TXD_A, - GPIO_FN_HTX4_B, - GPIO_FN_HSCK4, - GPIO_FN_VI5_FIELD, - GPIO_FN_SCL6_A, - GPIO_FN_AVB_AVTP_CAPTURE_B, - GPIO_FN_PWM2_B, - GPIO_IFN_A12, - GPIO_FN_LCDOUT12, - GPIO_FN_MSIOF3_SCK_C, - GPIO_FN_HRX4_A, - GPIO_FN_VI5_DATA8, - GPIO_FN_DU_DG4, - GPIO_IFN_A13, - GPIO_FN_LCDOUT13, - GPIO_FN_MSIOF3_SYNC_C, - GPIO_FN_HTX4_A, - GPIO_FN_VI5_DATA9, - GPIO_FN_DU_DG5, - GPIO_IFN_A14, - GPIO_FN_LCDOUT14, - GPIO_FN_MSIOF3_RXD_C, - GPIO_FN_HCTS4x, - GPIO_FN_VI5_DATA10, - GPIO_FN_DU_DG6, - GPIO_IFN_A15, - GPIO_FN_LCDOUT15, - GPIO_FN_MSIOF3_TXD_C, - GPIO_FN_HRTS4x, - GPIO_FN_VI5_DATA11, - GPIO_FN_DU_DG7, - GPIO_IFN_A16, - GPIO_FN_LCDOUT8, - GPIO_FN_VI4_FIELD, - GPIO_FN_DU_DG0, - - /* IPSR4 */ - GPIO_IFN_A17, - GPIO_FN_LCDOUT9, - GPIO_FN_VI4_VSYNCx, - GPIO_FN_DU_DG1, - GPIO_IFN_A18, - GPIO_FN_LCDOUT10, - GPIO_FN_VI4_HSYNCx, - GPIO_FN_DU_DG2, - GPIO_IFN_A19, - GPIO_FN_LCDOUT11, - GPIO_FN_VI4_CLKENB, - GPIO_FN_DU_DG3, - GPIO_IFN_CS0x, - GPIO_FN_VI5_CLKENB, - GPIO_IFN_CS1x_A26, - GPIO_FN_VI5_CLK, - GPIO_FN_EX_WAIT0_B, - GPIO_IFN_BSx, - GPIO_FN_QSTVA_QVS, - GPIO_FN_MSIOF3_SCK_D, - GPIO_FN_SCK3, - GPIO_FN_HSCK3, - GPIO_FN_CAN1_TX, - GPIO_FN_CANFD1_TX, - GPIO_FN_IETX_A, - GPIO_IFN_RDx, - GPIO_FN_MSIOF3_SYNC_D, - GPIO_FN_RX3_A, - GPIO_FN_HRX3_A, - GPIO_FN_CAN0_TX_A, - GPIO_FN_CANFD0_TX_A, - GPIO_IFN_RD_WRx, - GPIO_FN_MSIOF3_RXD_D, - GPIO_FN_TX3_A, - GPIO_FN_HTX3_A, - GPIO_FN_CAN0_RX_A, - GPIO_FN_CANFD0_RX_A, - - /* IPSR5 */ - GPIO_IFN_WE0x, - GPIO_FN_MSIIOF3_TXD_D, - GPIO_FN_CTS3x, - GPIO_FN_HCTS3x, - GPIO_FN_SCL6_B, - GPIO_FN_CAN_CLK, - GPIO_FN_IECLK_A, - GPIO_IFN_WE1x, - GPIO_FN_MSIOF3_SS1_D, - GPIO_FN_RTS3x_TANS, - GPIO_FN_HRTS3x, - GPIO_FN_SDA6_B, - GPIO_FN_CAN1_RX, - GPIO_FN_CANFD1_RX, - GPIO_FN_IERX_A, - GPIO_IFN_EX_WAIT0_A, - GPIO_FN_QCLK, - GPIO_FN_VI4_CLK, - GPIO_FN_DU_DOTCLKOUT0, - GPIO_IFN_D0, - GPIO_FN_MSIOF2_SS1_B, - GPIO_FN_MSIOF3_SCK_A, - GPIO_FN_VI4_DATA16, - GPIO_FN_VI5_DATA0, - GPIO_IFN_D1, - GPIO_FN_MSIOF2_SS2_B, - GPIO_FN_MSIOF3_SYNC_A, - GPIO_FN_VI4_DATA17, - GPIO_FN_VI5_DATA1, - GPIO_IFN_D2, - GPIO_FN_MSIOF3_RXD_A, - GPIO_FN_VI4_DATA18, - GPIO_FN_VI5_DATA2, - GPIO_IFN_D3, - GPIO_FN_MSIOF3_TXD_A, - GPIO_FN_VI4_DATA19, - GPIO_FN_VI5_DATA3, - GPIO_IFN_D4, - GPIO_FN_MSIOF2_SCK_B, - GPIO_FN_VI4_DATA20, - GPIO_FN_VI5_DATA4, - - /* IPSR6 */ - GPIO_IFN_D5, - GPIO_FN_MSIOF2_SYNC_B, - GPIO_FN_VI4_DATA21, - GPIO_FN_VI5_DATA5, - GPIO_IFN_D6, - GPIO_FN_MSIOF2_RXD_B, - GPIO_FN_VI4_DATA22, - GPIO_FN_VI5_DATA6, - GPIO_IFN_D7, - GPIO_FN_MSIOF2_TXD_B, - GPIO_FN_VI4_DATA23, - GPIO_FN_VI5_DATA7, - GPIO_IFN_D8, - GPIO_FN_LCDOUT0, - GPIO_FN_MSIOF2_SCK_D, - GPIO_FN_SCK4_C, - GPIO_FN_VI4_DATA0_A, - GPIO_FN_DU_DR0, - GPIO_IFN_D9, - GPIO_FN_LCDOUT1, - GPIO_FN_MSIOF2_SYNC_D, - GPIO_FN_VI4_DATA1_A, - GPIO_FN_DU_DR1, - GPIO_IFN_D10, - GPIO_FN_LCDOUT2, - GPIO_FN_MSIOF2_RXD_D, - GPIO_FN_HRX3_B, - GPIO_FN_VI4_DATA2_A, - GPIO_FN_CTS4x_C, - GPIO_FN_DU_DR2, - GPIO_IFN_D11, - GPIO_FN_LCDOUT3, - GPIO_FN_MSIOF2_TXD_D, - GPIO_FN_HTX3_B, - GPIO_FN_VI4_DATA3_A, - GPIO_FN_RTS4x_TANS_C, - GPIO_FN_DU_DR3, - GPIO_IFN_D12, - GPIO_FN_LCDOUT4, - GPIO_FN_MSIOF2_SS1_D, - GPIO_FN_RX4_C, - GPIO_FN_VI4_DATA4_A, - GPIO_FN_DU_DR4, - - /* IPSR7 */ - GPIO_IFN_D13, - GPIO_FN_LCDOUT5, - GPIO_FN_MSIOF2_SS2_D, - GPIO_FN_TX4_C, - GPIO_FN_VI4_DATA5_A, - GPIO_FN_DU_DR5, - GPIO_IFN_D14, - GPIO_FN_LCDOUT6, - GPIO_FN_MSIOF3_SS1_A, - GPIO_FN_HRX3_C, - GPIO_FN_VI4_DATA6_A, - GPIO_FN_DU_DR6, - GPIO_FN_SCL6_C, - GPIO_IFN_D15, - GPIO_FN_LCDOUT7, - GPIO_FN_MSIOF3_SS2_A, - GPIO_FN_HTX3_C, - GPIO_FN_VI4_DATA7_A, - GPIO_FN_DU_DR7, - GPIO_FN_SDA6_C, - GPIO_FN_FSCLKST, - GPIO_IFN_SD0_CLK, - GPIO_FN_MSIOF1_SCK_E, - GPIO_FN_STP_OPWM_0_B, - GPIO_IFN_SD0_CMD, - GPIO_FN_MSIOF1_SYNC_E, - GPIO_FN_STP_IVCXO27_0_B, - GPIO_IFN_SD0_DAT0, - GPIO_FN_MSIOF1_RXD_E, - GPIO_FN_TS_SCK0_B, - GPIO_FN_STP_ISCLK_0_B, - GPIO_IFN_SD0_DAT1, - GPIO_FN_MSIOF1_TXD_E, - GPIO_FN_TS_SPSYNC0_B, - GPIO_FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - GPIO_IFN_SD0_DAT2, - GPIO_FN_MSIOF1_SS1_E, - GPIO_FN_TS_SDAT0_B, - GPIO_FN_STP_ISD_0_B, - GPIO_IFN_SD0_DAT3, - GPIO_FN_MSIOF1_SS2_E, - GPIO_FN_TS_SDEN0_B, - GPIO_FN_STP_ISEN_0_B, - GPIO_IFN_SD1_CLK, - GPIO_FN_MSIOF1_SCK_G, - GPIO_FN_SIM0_CLK_A, - GPIO_IFN_SD1_CMD, - GPIO_FN_MSIOF1_SYNC_G, - GPIO_FN_NFCEx_B, - GPIO_FN_SIM0_D_A, - GPIO_FN_STP_IVCXO27_1_B, - GPIO_IFN_SD1_DAT0, - GPIO_FN_SD2_DAT4, - GPIO_FN_MSIOF1_RXD_G, - GPIO_FN_NFWPx_B, - GPIO_FN_TS_SCK1_B, - GPIO_FN_STP_ISCLK_1_B, - GPIO_IFN_SD1_DAT1, - GPIO_FN_SD2_DAT5, - GPIO_FN_MSIOF1_TXD_G, - GPIO_FN_NFDATA14_B, - GPIO_FN_TS_SPSYNC1_B, - GPIO_FN_STP_ISSYNC_1_B, - GPIO_IFN_SD1_DAT2, - GPIO_FN_SD2_DAT6, - GPIO_FN_MSIOF1_SS1_G, - GPIO_FN_NFDATA15_B, - GPIO_FN_TS_SDAT1_B, - GPIO_FN_STP_IOD_1_B, - GPIO_IFN_SD1_DAT3, - GPIO_FN_SD2_DAT7, - GPIO_FN_MSIOF1_SS2_G, - GPIO_FN_NFRBx_B, - GPIO_FN_TS_SDEN1_B, - GPIO_FN_STP_ISEN_1_B, - - /* IPSR9 */ - GPIO_IFN_SD2_CLK, - GPIO_FN_NFDATA8, - GPIO_IFN_SD2_CMD, - GPIO_FN_NFDATA9, - GPIO_IFN_SD2_DAT0, - GPIO_FN_NFDATA10, - GPIO_IFN_SD2_DAT1, - GPIO_FN_NFDATA11, - GPIO_IFN_SD2_DAT2, - GPIO_FN_NFDATA12, - GPIO_IFN_SD2_DAT3, - GPIO_FN_NFDATA13, - GPIO_IFN_SD2_DS, - GPIO_FN_NFALE, - GPIO_FN_SATA_DEVSLP_B, - GPIO_IFN_SD3_CLK, - GPIO_FN_NFWEx, - - /* IPSR10 */ - GPIO_IFN_SD3_CMD, - GPIO_FN_NFREx, - GPIO_IFN_SD3_DAT0, - GPIO_FN_NFDATA0, - GPIO_IFN_SD3_DAT1, - GPIO_FN_NFDATA1, - GPIO_IFN_SD3_DAT2, - GPIO_FN_NFDATA2, - GPIO_IFN_SD3_DAT3, - GPIO_FN_NFDATA3, - GPIO_IFN_SD3_DAT4, - GPIO_FN_SD2_CD_A, - GPIO_FN_NFDATA4, - GPIO_IFN_SD3_DAT5, - GPIO_FN_SD2_WP_A, - GPIO_FN_NFDATA5, - GPIO_IFN_SD3_DAT6, - GPIO_FN_SD3_CD, - GPIO_FN_NFDATA6, - - /* IPSR11 */ - GPIO_IFN_SD3_DAT7, - GPIO_FN_SD3_WP, - GPIO_FN_NFDATA7, - GPIO_IFN_SD3_DS, - GPIO_FN_NFCLE, - GPIO_IFN_SD0_CD, - GPIO_FN_NFDATA14_A, - GPIO_FN_SCL2_B, - GPIO_FN_SIM0_RST_A, - GPIO_IFN_SD0_WP, - GPIO_FN_NFDATA15_A, - GPIO_FN_SDA2_B, - GPIO_IFN_SD1_CD, - GPIO_FN_NFRBx_A, - GPIO_FN_SIM0_CLK_B, - GPIO_IFN_SD1_WP, - GPIO_FN_NFCEx_A, - GPIO_FN_SIM0_D_B, - GPIO_IFN_SCK0, - GPIO_FN_HSCK1_B, - GPIO_FN_MSIOF1_SS2_B, - GPIO_FN_AUDIO_CLKC_B, - GPIO_FN_SDA2_A, - GPIO_FN_SIM0_RST_B, - GPIO_FN_STP_OPWM_0_C, - GPIO_FN_RIF0_CLK_B, - GPIO_FN_ADICHS2, - GPIO_FN_SCK5_B, - GPIO_IFN_RX0, - GPIO_FN_HRX1_B, - GPIO_FN_TS_SCK0_C, - GPIO_FN_STP_ISCLK_0_C, - GPIO_FN_RIF0_D0_B, - - /* IPSR12 */ - GPIO_IFN_TX0, - GPIO_FN_HTX1_B, - GPIO_FN_TS_SPSYNC0_C, - GPIO_FN_STP_ISSYNC_0_C, - GPIO_FN_RIF0_D1_B, - GPIO_IFN_CTS0x, - GPIO_FN_HCTS1x_B, - GPIO_FN_MSIOF1_SYNC_B, - GPIO_FN_TS_SPSYNC1_C, - GPIO_FN_STP_ISSYNC_1_C, - GPIO_FN_RIF1_SYNC_B, - GPIO_FN_AUDIO_CLKOUT_C, - GPIO_FN_ADICS_SAMP, - GPIO_IFN_RTS0x_TANS, - GPIO_FN_HRTS1x_B, - GPIO_FN_MSIOF1_SS1_B, - GPIO_FN_AUDIO_CLKA_B, - GPIO_FN_SCL2_A, - GPIO_FN_STP_IVCXO27_1_C, - GPIO_FN_RIF0_SYNC_B, - GPIO_FN_ADICHS1, - GPIO_IFN_RX1_A, - GPIO_FN_HRX1_A, - GPIO_FN_TS_SDAT0_C, - GPIO_FN_STP_ISD_0_C, - GPIO_FN_RIF1_CLK_C, - GPIO_IFN_TX1_A, - GPIO_FN_HTX1_A, - GPIO_FN_TS_SDEN0_C, - GPIO_FN_STP_ISEN_0_C, - GPIO_FN_RIF1_D0_C, - GPIO_IFN_CTS1x, - GPIO_FN_HCTS1x_A, - GPIO_FN_MSIOF1_RXD_B, - GPIO_FN_TS_SDEN1_C, - GPIO_FN_STP_ISEN_1_C, - GPIO_FN_RIF1_D0_B, - GPIO_FN_ADIDATA, - GPIO_IFN_RTS1x_TANS, - GPIO_FN_HRTS1x_A, - GPIO_FN_MSIOF1_TXD_B, - GPIO_FN_TS_SDAT1_C, - GPIO_FN_STP_ISD_1_C, - GPIO_FN_RIF1_D1_B, - GPIO_FN_ADICHS0, - GPIO_IFN_SCK2, - GPIO_FN_SCIF_CLK_B, - GPIO_FN_MSIOF1_SCK_B, - GPIO_FN_TS_SCK1_C, - GPIO_FN_STP_ISCLK_1_C, - GPIO_FN_RIF1_CLK_B, - GPIO_FN_ADICLK, - - /* IPSR13 */ - GPIO_IFN_TX2_A, - GPIO_FN_SD2_CD_B, - GPIO_FN_SCL1_A, - GPIO_FN_FMCLK_A, - GPIO_FN_RIF1_D1_C, - GPIO_FN_FSO_CFE_0x, - GPIO_IFN_RX2_A, - GPIO_FN_SD2_WP_B, - GPIO_FN_SDA1_A, - GPIO_FN_FMIN_A, - GPIO_FN_RIF1_SYNC_C, - GPIO_FN_FSO_CFE_1x, - GPIO_IFN_HSCK0, - GPIO_FN_MSIOF1_SCK_D, - GPIO_FN_AUDIO_CLKB_A, - GPIO_FN_SSI_SDATA1_B, - GPIO_FN_TS_SCK0_D, - GPIO_FN_STP_ISCLK_0_D, - GPIO_FN_RIF0_CLK_C, - GPIO_FN_RX5_B, - GPIO_IFN_HRX0, - GPIO_FN_MSIOF1_RXD_D, - GPIO_FN_SSI_SDATA2_B, - GPIO_FN_TS_SDEN0_D, - GPIO_FN_STP_ISEN_0_D, - GPIO_FN_RIF0_D0_C, - GPIO_IFN_HTX0, - GPIO_FN_MSIOF1_TXD_D, - GPIO_FN_SSI_SDATA9_B, - GPIO_FN_TS_SDAT0_D, - GPIO_FN_STP_ISD_0_D, - GPIO_FN_RIF0_D1_C, - GPIO_IFN_HCTS0x, - GPIO_FN_RX2_B, - GPIO_FN_MSIOF1_SYNC_D, - GPIO_FN_SSI_SCK9_A, - GPIO_FN_TS_SPSYNC0_D, - GPIO_FN_STP_ISSYNC_0_D, - GPIO_FN_RIF0_SYNC_C, - GPIO_FN_AUDIO_CLKOUT1_A, - GPIO_IFN_HRTS0x, - GPIO_FN_TX2_B, - GPIO_FN_MSIOF1_SS1_D, - GPIO_FN_SSI_WS9_A, - GPIO_FN_STP_IVCXO27_0_D, - GPIO_FN_BPFCLK_A, - GPIO_FN_AUDIO_CLKOUT2_A, - GPIO_IFN_MSIOF0_SYNC, - GPIO_FN_AUDIO_CLKOUT_A, - GPIO_FN_TX5_B, - GPIO_FN_BPFCLK_D, - - /* IPSR14 */ - GPIO_IFN_MSIOF0_SS1, - GPIO_FN_RX5_A, - GPIO_FN_NFWPx_A, - GPIO_FN_AUDIO_CLKA_C, - GPIO_FN_SSI_SCK2_A, - GPIO_FN_STP_IVCXO27_0_C, - GPIO_FN_AUDIO_CLKOUT3_A, - GPIO_FN_TCLK1_B, - GPIO_IFN_MSIOF0_SS2, - GPIO_FN_TX5_A, - GPIO_FN_MSIOF1_SS2_D, - GPIO_FN_AUDIO_CLKC_A, - GPIO_FN_SSI_WS2_A, - GPIO_FN_STP_OPWM_0_D, - GPIO_FN_AUDIO_CLKOUT_D, - GPIO_FN_SPEEDIN_B, - GPIO_IFN_MLB_CLK, - GPIO_FN_MSIOF1_SCK_F, - GPIO_FN_SCL1_B, - GPIO_IFN_MLB_SIG, - GPIO_FN_RX1_B, - GPIO_FN_MSIOF1_SYNC_F, - GPIO_FN_SDA1_B, - GPIO_IFN_MLB_DAT, - GPIO_FN_TX1_B, - GPIO_FN_MSIOF1_RXD_F, - GPIO_IFN_SSI_SCK01239, - GPIO_FN_MSIOF1_TXD_F, - GPIO_FN_MOUT0, - GPIO_IFN_SSI_WS01239, - GPIO_FN_MSIOF1_SS1_F, - GPIO_FN_MOUT1, - GPIO_IFN_SSI_SDATA0, - GPIO_FN_MSIOF1_SS2_F, - GPIO_FN_MOUT2, - - /* IPSR15 */ - GPIO_IFN_SSI_SDATA1_A, - GPIO_FN_MOUT5, - GPIO_IFN_SSI_SDATA2_A, - GPIO_FN_SSI_SCK1_B, - GPIO_FN_MOUT6, - GPIO_IFN_SSI_SCK34, - GPIO_FN_MSIOF1_SS1_A, - GPIO_FN_STP_OPWM_0_A, - GPIO_IFN_SSI_WS34, - GPIO_FN_HCTS2x_A, - GPIO_FN_MSIOF1_SS2_A, - GPIO_FN_STP_IVCXO27_0_A, - GPIO_IFN_SSI_SDATA3, - GPIO_FN_HRTS2x_A, - GPIO_FN_MSIOF1_TXD_A, - GPIO_FN_TS_SCK0_A, - GPIO_FN_STP_ISCLK_0_A, - GPIO_FN_RIF0_D1_A, - GPIO_FN_RIF2_D0_A, - GPIO_IFN_SSI_SCK4, - GPIO_FN_HRX2_A, - GPIO_FN_MSIOF1_SCK_A, - GPIO_FN_TS_SDAT0_A, - GPIO_FN_STP_ISD_0_A, - GPIO_FN_RIF0_CLK_A, - GPIO_FN_RIF2_CLK_A, - GPIO_IFN_SSI_WS4, - GPIO_FN_HTX2_A, - GPIO_FN_MSIOF1_SYNC_A, - GPIO_FN_TS_SDEN0_A, - GPIO_FN_STP_ISEN_0_A, - GPIO_FN_RIF0_SYNC_A, - GPIO_FN_RIF2_SYNC_A, - GPIO_IFN_SSI_SDATA4, - GPIO_FN_HSCK2_A, - GPIO_FN_MSIOF1_RXD_A, - GPIO_FN_TS_SPSYNC0_A, - GPIO_FN_STP_ISSYNC_0_A, - GPIO_FN_RIF0_D0_A, - GPIO_FN_RIF2_D1_A, - - /* IPSR16 */ - GPIO_IFN_SSI_SCK6, - GPIO_FN_SIM0_RST_D, - GPIO_IFN_SSI_WS6, - GPIO_FN_SIM0_D_D, - GPIO_IFN_SSI_SDATA6, - GPIO_FN_SIM0_CLK_D, - GPIO_FN_SATA_DEVSLP_A, - GPIO_IFN_SSI_SCK78, - GPIO_FN_HRX2_B, - GPIO_FN_MSIOF1_SCK_C, - GPIO_FN_TS_SCK1_A, - GPIO_FN_STP_ISCLK_1_A, - GPIO_FN_RIF1_CLK_A, - GPIO_FN_RIF3_CLK_A, - GPIO_IFN_SSI_WS78, - GPIO_FN_HTX2_B, - GPIO_FN_MSIOF1_SYNC_C, - GPIO_FN_TS_SDAT1_A, - GPIO_FN_STP_ISD_1_A, - GPIO_FN_RIF1_SYNC_A, - GPIO_FN_RIF3_SYNC_A, - GPIO_IFN_SSI_SDATA7, - GPIO_FN_HCTS2x_B, - GPIO_FN_MSIOF1_RXD_C, - GPIO_FN_TS_SDEN1_A, - GPIO_FN_STP_ISEN_1_A, - GPIO_FN_RIF1_D0_A, - GPIO_FN_RIF3_D0_A, - GPIO_FN_TCLK2_A, - GPIO_IFN_SSI_SDATA8, - GPIO_FN_HRTS2x_B, - GPIO_FN_MSIOF1_TXD_C, - GPIO_FN_TS_SPSYNC1_A, - GPIO_FN_STP_ISSYNC_1_A, - GPIO_FN_RIF1_D1_A, - GPIO_FN_RIF3_D1_A, - GPIO_IFN_SSI_SDATA9_A, - GPIO_FN_HSCK2_B, - GPIO_FN_MSIOF1_SS1_C, - GPIO_FN_HSCK1_A, - GPIO_FN_SSI_WS1_B, - GPIO_FN_SCK1, - GPIO_FN_STP_IVCXO27_1_A, - GPIO_FN_SCK5_A, - - /* IPSR17 */ - GPIO_IFN_AUDIO_CLKA_A, - GPIO_FN_CC5_OSCOUT, - GPIO_IFN_AUDIO_CLKB_B, - GPIO_FN_SCIF_CLK_A, - GPIO_FN_STP_IVCXO27_1_D, - GPIO_FN_REMOCON_A, - GPIO_FN_TCLK1_A, - GPIO_IFN_USB0_PWEN, - GPIO_FN_SIM0_RST_C, - GPIO_FN_TS_SCK1_D, - GPIO_FN_STP_ISCLK_1_D, - GPIO_FN_BPFCLK_B, - GPIO_FN_RIF3_CLK_B, - GPIO_FN_HSCK2_C, - GPIO_IFN_USB0_OVC, - GPIO_FN_SIM0_D_C, - GPIO_FN_TS_SDAT1_D, - GPIO_FN_STP_ISD_1_D, - GPIO_FN_RIF3_SYNC_B, - GPIO_FN_HRX2_C, - GPIO_IFN_USB1_PWEN, - GPIO_FN_SIM0_CLK_C, - GPIO_FN_SSI_SCK1_A, - GPIO_FN_TS_SCK0_E, - GPIO_FN_STP_ISCLK_0_E, - GPIO_FN_FMCLK_B, - GPIO_FN_RIF2_CLK_B, - GPIO_FN_SPEEDIN_A, - GPIO_FN_HTX2_C, - GPIO_IFN_USB1_OVC, - GPIO_FN_MSIOF1_SS2_C, - GPIO_FN_SSI_WS1_A, - GPIO_FN_TS_SDAT0_E, - GPIO_FN_STP_ISD_0_E, - GPIO_FN_FMIN_B, - GPIO_FN_RIF2_SYNC_B, - GPIO_FN_REMOCON_B, - GPIO_FN_HCTS2x_C, - GPIO_IFN_USB30_PWEN, - GPIO_FN_AUDIO_CLKOUT_B, - GPIO_FN_SSI_SCK2_B, - GPIO_FN_TS_SDEN1_D, - GPIO_FN_STP_ISEN_1_D, - GPIO_FN_STP_OPWM_0_E, - GPIO_FN_RIF3_D0_B, - GPIO_FN_TCLK2_B, - GPIO_FN_TPU0TO0, - GPIO_FN_BPFCLK_C, - GPIO_FN_HRTS2x_C, - GPIO_IFN_USB30_OVC, - GPIO_FN_AUDIO_CLKOUT1_B, - GPIO_FN_SSI_WS2_B, - GPIO_FN_TS_SPSYNC1_D, - GPIO_FN_STP_ISSYNC_1_D, - GPIO_FN_STP_IVCXO27_0_E, - GPIO_FN_RIF3_D1_B, - GPIO_FN_FSO_TOEx, - GPIO_FN_TPU0TO1, - - /* IPSR18 */ - GPIO_IFN_USB3_PWEN, - GPIO_FN_AUDIO_CLKOUT2_B, - GPIO_FN_SSI_SCK9_B, - GPIO_FN_TS_SDEN0_E, - GPIO_FN_STP_ISEN_0_E, - GPIO_FN_RIF2_D0_B, - GPIO_FN_TPU0TO2, - GPIO_FN_FMCLK_C, - GPIO_FN_FMCLK_D, - GPIO_IFN_USB3_OVC, - GPIO_FN_AUDIO_CLKOUT3_B, - GPIO_FN_SSI_WS9_B, - GPIO_FN_TS_SPSYNC0_E, - GPIO_FN_STP_ISSYNC_0_E, - GPIO_FN_RIF2_D1_B, - GPIO_FN_TPU0TO3, - GPIO_FN_FMIN_C, - GPIO_FN_FMIN_D, -}; - -#endif /* __ASM_R8A7795_GPIO_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795.h b/arch/arm/mach-rmobile/include/mach/r8a7795.h deleted file mode 100644 index 2d004b6a540..00000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7795.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/mach-rmobile/include/mach/r8a7795.h - * This file defines registers and value for r8a7795. - * - * Copyright (C) 2015 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_R8A7795_H -#define __ASM_ARCH_R8A7795_H - -#include "rcar-gen3-base.h" - -/* Module stop control/status register bits */ -#define MSTP0_BITS 0x00640800 -#define MSTP1_BITS 0xF3EE9390 -#define MSTP2_BITS 0x340FAFDC -#define MSTP3_BITS 0xD80C7CDF -#define MSTP4_BITS 0x80000184 -#define MSTP5_BITS 0x40BFFF46 -#define MSTP6_BITS 0xE5FBEECF -#define MSTP7_BITS 0x39FFFF0E -#define MSTP8_BITS 0x01F19FF4 -#define MSTP9_BITS 0xFFDFFFFF -#define MSTP10_BITS 0xFFFEFFE0 -#define MSTP11_BITS 0x00000000 - -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 - -#endif /* __ASM_ARCH_R8A7795_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h deleted file mode 100644 index 2359e36a14d..00000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h +++ /dev/null @@ -1,1084 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7796-gpio.h - * This file defines pin function control of gpio. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_R8A7796_GPIO_H__ -#define __ASM_R8A7796_GPIO_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, - GPIO_GP_1_28, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, - - GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, - GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, - GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, - GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, - GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, - GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, - GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, - GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, - - GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, - - /* GPSR0 */ - GPIO_GFN_D15, - GPIO_GFN_D14, - GPIO_GFN_D13, - GPIO_GFN_D12, - GPIO_GFN_D11, - GPIO_GFN_D10, - GPIO_GFN_D9, - GPIO_GFN_D8, - GPIO_GFN_D7, - GPIO_GFN_D6, - GPIO_GFN_D5, - GPIO_GFN_D4, - GPIO_GFN_D3, - GPIO_GFN_D2, - GPIO_GFN_D1, - GPIO_GFN_D0, - - /* GPSR1 */ - GPIO_GFN_CLKOUT, - GPIO_GFN_EX_WAIT0_A, - GPIO_GFN_WE1x, - GPIO_GFN_WE0x, - GPIO_GFN_RD_WRx, - GPIO_GFN_RDx, - GPIO_GFN_BSx, - GPIO_GFN_CS1x_A26, - GPIO_GFN_CS0x, - GPIO_GFN_A19, - GPIO_GFN_A18, - GPIO_GFN_A17, - GPIO_GFN_A16, - GPIO_GFN_A15, - GPIO_GFN_A14, - GPIO_GFN_A13, - GPIO_GFN_A12, - GPIO_GFN_A11, - GPIO_GFN_A10, - GPIO_GFN_A9, - GPIO_GFN_A8, - GPIO_GFN_A7, - GPIO_GFN_A6, - GPIO_GFN_A5, - GPIO_GFN_A4, - GPIO_GFN_A3, - GPIO_GFN_A2, - GPIO_GFN_A1, - GPIO_GFN_A0, - - /* GPSR2 */ - GPIO_GFN_AVB_AVTP_CAPTURE_A, - GPIO_GFN_AVB_AVTP_MATCH_A, - GPIO_GFN_AVB_LINK, - GPIO_GFN_AVB_PHY_INT, - GPIO_GFN_AVB_MAGIC, - GPIO_GFN_AVB_MDC, - GPIO_GFN_PWM2_A, - GPIO_GFN_PWM1_A, - GPIO_GFN_PWM0, - GPIO_GFN_IRQ5, - GPIO_GFN_IRQ4, - GPIO_GFN_IRQ3, - GPIO_GFN_IRQ2, - GPIO_GFN_IRQ1, - GPIO_GFN_IRQ0, - - /* GPSR3 */ - GPIO_GFN_SD1_WP, - GPIO_GFN_SD1_CD, - GPIO_GFN_SD0_WP, - GPIO_GFN_SD0_CD, - GPIO_GFN_SD1_DAT3, - GPIO_GFN_SD1_DAT2, - GPIO_GFN_SD1_DAT1, - GPIO_GFN_SD1_DAT0, - GPIO_GFN_SD1_CMD, - GPIO_GFN_SD1_CLK, - GPIO_GFN_SD0_DAT3, - GPIO_GFN_SD0_DAT2, - GPIO_GFN_SD0_DAT1, - GPIO_GFN_SD0_DAT0, - GPIO_GFN_SD0_CMD, - GPIO_GFN_SD0_CLK, - - /* GPSR4 */ - GPIO_GFN_SD3_DS, - GPIO_GFN_SD3_DAT7, - GPIO_GFN_SD3_DAT6, - GPIO_GFN_SD3_DAT5, - GPIO_GFN_SD3_DAT4, - GPIO_FN_SD3_DAT3, - GPIO_FN_SD3_DAT2, - GPIO_FN_SD3_DAT1, - GPIO_FN_SD3_DAT0, - GPIO_FN_SD3_CMD, - GPIO_FN_SD3_CLK, - GPIO_GFN_SD2_DS, - GPIO_GFN_SD2_DAT3, - GPIO_GFN_SD2_DAT2, - GPIO_GFN_SD2_DAT1, - GPIO_GFN_SD2_DAT0, - GPIO_FN_SD2_CMD, - GPIO_GFN_SD2_CLK, - - /* GPSR5 */ - GPIO_GFN_MLB_DAT, - GPIO_GFN_MLB_SIG, - GPIO_GFN_MLB_CLK, - GPIO_FN_MSIOF0_RXD, - GPIO_GFN_MSIOF0_SS2, - GPIO_FN_MSIOF0_TXD, - GPIO_GFN_MSIOF0_SS1, - GPIO_GFN_MSIOF0_SYNC, - GPIO_FN_MSIOF0_SCK, - GPIO_GFN_HRTS0x, - GPIO_GFN_HCTS0x, - GPIO_GFN_HTX0, - GPIO_GFN_HRX0, - GPIO_GFN_HSCK0, - GPIO_GFN_RX2_A, - GPIO_GFN_TX2_A, - GPIO_GFN_SCK2, - GPIO_GFN_RTS1x_TANS, - GPIO_GFN_CTS1x, - GPIO_GFN_TX1_A, - GPIO_GFN_RX1_A, - GPIO_GFN_RTS0x_TANS, - GPIO_GFN_CTS0x, - GPIO_GFN_TX0, - GPIO_GFN_RX0, - GPIO_GFN_SCK0, - - /* GPSR6 */ - GPIO_GFN_GP6_31, - GPIO_GFN_GP6_30, - GPIO_GFN_USB30_OVC, - GPIO_GFN_USB30_PWEN, - GPIO_GFN_USB1_OVC, - GPIO_GFN_USB1_PWEN, - GPIO_GFN_USB0_OVC, - GPIO_GFN_USB0_PWEN, - GPIO_GFN_AUDIO_CLKB_B, - GPIO_GFN_AUDIO_CLKA_A, - GPIO_GFN_SSI_SDATA9_A, - GPIO_GFN_SSI_SDATA8, - GPIO_GFN_SSI_SDATA7, - GPIO_GFN_SSI_WS78, - GPIO_GFN_SSI_SCK78, - GPIO_GFN_SSI_SDATA6, - GPIO_GFN_SSI_WS6, - GPIO_GFN_SSI_SCK6, - GPIO_FN_SSI_SDATA5, - GPIO_FN_SSI_WS5, - GPIO_FN_SSI_SCK5, - GPIO_GFN_SSI_SDATA4, - GPIO_GFN_SSI_WS4, - GPIO_GFN_SSI_SCK4, - GPIO_GFN_SSI_SDATA3, - GPIO_GFN_SSI_WS34, - GPIO_GFN_SSI_SCK34, - GPIO_GFN_SSI_SDATA2_A, - GPIO_GFN_SSI_SDATA1_A, - GPIO_GFN_SSI_SDATA0, - GPIO_GFN_SSI_WS01239, - GPIO_GFN_SSI_SCK01239, - - /* GPSR7 */ - GPIO_FN_HDMI1_CEC, - GPIO_FN_HDMI0_CEC, - GPIO_FN_AVS2, - GPIO_FN_AVS1, - - /* IPSR0 */ - GPIO_IFN_AVB_MDC, - GPIO_FN_MSIOF2_SS2_C, - GPIO_IFN_AVB_MAGIC, - GPIO_FN_MSIOF2_SS1_C, - GPIO_FN_SCK4_A, - GPIO_IFN_AVB_PHY_INT, - GPIO_FN_MSIOF2_SYNC_C, - GPIO_FN_RX4_A, - GPIO_IFN_AVB_LINK, - GPIO_FN_MSIOF2_SCK_C, - GPIO_FN_TX4_A, - GPIO_IFN_AVB_AVTP_MATCH_A, - GPIO_FN_MSIOF2_RXD_C, - GPIO_FN_CTS4x_A, - GPIO_IFN_AVB_AVTP_CAPTURE_A, - GPIO_FN_MSIOF2_TXD_C, - GPIO_FN_RTS4x_TANS_A, - GPIO_IFN_IRQ0, - GPIO_FN_QPOLB, - GPIO_FN_DU_CDE, - GPIO_FN_VI4_DATA0_B, - GPIO_FN_CAN0_TX_B, - GPIO_FN_CANFD0_TX_B, - GPIO_FN_MSIOF3_SS2_E, - GPIO_IFN_IRQ1, - GPIO_FN_QPOLA, - GPIO_FN_DU_DISP, - GPIO_FN_VI4_DATA1_B, - GPIO_FN_CAN0_RX_B, - GPIO_FN_CANFD0_RX_B, - GPIO_FN_MSIOF3_SS1_E, - - /* IPSR1 */ - GPIO_IFN_IRQ2, - GPIO_FN_QCPV_QDE, - GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE, - GPIO_FN_VI4_DATA2_B, - GPIO_FN_MSIOF3_SYNC_E, - GPIO_FN_PWM3_B, - GPIO_IFN_IRQ3, - GPIO_FN_QSTVB_QVE, - GPIO_FN_DU_DOTCLKOUT1, - GPIO_FN_VI4_DATA3_B, - GPIO_FN_MSIOF3_SCK_E, - GPIO_FN_PWM4_B, - GPIO_IFN_IRQ4, - GPIO_FN_QSTH_QHS, - GPIO_FN_DU_EXHSYNC_DU_HSYNC, - GPIO_FN_VI4_DATA4_B, - GPIO_FN_MSIOF3_RXD_E, - GPIO_FN_PWM5_B, - GPIO_IFN_IRQ5, - GPIO_FN_QSTB_QHE, - GPIO_FN_DU_EXVSYNC_DU_VSYNC, - GPIO_FN_VI4_DATA5_B, - GPIO_FN_MSIOF3_TXD_E, - GPIO_FN_PWM6_B, - GPIO_IFN_PWM0, - GPIO_FN_AVB_AVTP_PPS, - GPIO_FN_VI4_DATA6_B, - GPIO_FN_IECLK_B, - GPIO_IFN_PWM1_A, - GPIO_FN_HRX3_D, - GPIO_FN_VI4_DATA7_B, - GPIO_FN_IERX_B, - GPIO_IFN_PWM2_A, - GPIO_FN_PWMFSW0, - GPIO_FN_HTX3_D, - GPIO_FN_IETX_B, - GPIO_IFN_A0, - GPIO_FN_LCDOUT16, - GPIO_FN_MSIOF3_SYNC_B, - GPIO_FN_VI4_DATA8, - GPIO_FN_DU_DB0, - GPIO_FN_PWM3_A, - - /* IPSR2 */ - GPIO_IFN_A1, - GPIO_FN_LCDOUT17, - GPIO_FN_MSIOF3_TXD_B, - GPIO_FN_VI4_DATA9, - GPIO_FN_DU_DB1, - GPIO_FN_PWM4_A, - GPIO_IFN_A2, - GPIO_FN_LCDOUT18, - GPIO_FN_MSIOF3_SCK_B, - GPIO_FN_VI4_DATA10, - GPIO_FN_DU_DB2, - GPIO_FN_PWM5_A, - GPIO_IFN_A3, - GPIO_FN_LCDOUT19, - GPIO_FN_MSIOF3_RXD_B, - GPIO_FN_VI4_DATA11, - GPIO_FN_DU_DB3, - GPIO_FN_PWM6_A, - GPIO_IFN_A4, - GPIO_FN_LCDOUT20, - GPIO_FN_MSIOF3_SS1_B, - GPIO_FN_VI4_DATA12, - GPIO_FN_VI5_DATA12, - GPIO_FN_DU_DB4, - GPIO_IFN_A5, - GPIO_FN_LCDOUT21, - GPIO_FN_MSIOF3_SS2_B, - GPIO_FN_SCK4_B, - GPIO_FN_VI4_DATA13, - GPIO_FN_VI5_DATA13, - GPIO_FN_DU_DB5, - GPIO_IFN_A6, - GPIO_FN_LCDOUT22, - GPIO_FN_MSIOF2_SS1_A, - GPIO_FN_RX4_B, - GPIO_FN_VI4_DATA14, - GPIO_FN_VI5_DATA14, - GPIO_FN_DU_DB6, - GPIO_IFN_A7, - GPIO_FN_LCDOUT23, - GPIO_FN_MSIOF2_SS2_A, - GPIO_FN_TX4_B, - GPIO_FN_VI4_DATA15, - GPIO_FN_V15_DATA15, - GPIO_FN_DU_DB7, - GPIO_IFN_A8, - GPIO_FN_RX3_B, - GPIO_FN_MSIOF2_SYNC_A, - GPIO_FN_HRX4_B, - GPIO_FN_SDA6_A, - GPIO_FN_AVB_AVTP_MATCH_B, - GPIO_FN_PWM1_B, - - /* IPSR3 */ - GPIO_IFN_A9, - GPIO_FN_MSIOF2_SCK_A, - GPIO_FN_CTS4x_B, - GPIO_FN_VI5_VSYNCx, - GPIO_IFN_A10, - GPIO_FN_MSIOF2_RXD_A, - GPIO_FN_RTS4n_TANS_B, - GPIO_FN_VI5_HSYNCx, - GPIO_IFN_A11, - GPIO_FN_TX3_B, - GPIO_FN_MSIOF2_TXD_A, - GPIO_FN_HTX4_B, - GPIO_FN_HSCK4, - GPIO_FN_VI5_FIELD, - GPIO_FN_SCL6_A, - GPIO_FN_AVB_AVTP_CAPTURE_B, - GPIO_FN_PWM2_B, - GPIO_FN_SPV_EVEN, - GPIO_IFN_A12, - GPIO_FN_LCDOUT12, - GPIO_FN_MSIOF3_SCK_C, - GPIO_FN_HRX4_A, - GPIO_FN_VI5_DATA8, - GPIO_FN_DU_DG4, - GPIO_IFN_A13, - GPIO_FN_LCDOUT13, - GPIO_FN_MSIOF3_SYNC_C, - GPIO_FN_HTX4_A, - GPIO_FN_VI5_DATA9, - GPIO_FN_DU_DG5, - GPIO_IFN_A14, - GPIO_FN_LCDOUT14, - GPIO_FN_MSIOF3_RXD_C, - GPIO_FN_HCTS4x, - GPIO_FN_VI5_DATA10, - GPIO_FN_DU_DG6, - GPIO_IFN_A15, - GPIO_FN_LCDOUT15, - GPIO_FN_MSIOF3_TXD_C, - GPIO_FN_HRTS4x, - GPIO_FN_VI5_DATA11, - GPIO_FN_DU_DG7, - GPIO_IFN_A16, - GPIO_FN_LCDOUT8, - GPIO_FN_VI4_FIELD, - GPIO_FN_DU_DG0, - - /* IPSR4 */ - GPIO_IFN_A17, - GPIO_FN_LCDOUT9, - GPIO_FN_VI4_VSYNCx, - GPIO_FN_DU_DG1, - GPIO_IFN_A18, - GPIO_FN_LCDOUT10, - GPIO_FN_VI4_HSYNCx, - GPIO_FN_DU_DG2, - GPIO_IFN_A19, - GPIO_FN_LCDOUT11, - GPIO_FN_VI4_CLKENB, - GPIO_FN_DU_DG3, - GPIO_IFN_CS0x, - GPIO_FN_VI5_CLKENB, - GPIO_IFN_CS1x_A26, - GPIO_FN_VI5_CLK, - GPIO_FN_EX_WAIT0_B, - GPIO_IFN_BSx, - GPIO_FN_QSTVA_QVS, - GPIO_FN_MSIOF3_SCK_D, - GPIO_FN_SCK3, - GPIO_FN_HSCK3, - GPIO_FN_CAN1_TX, - GPIO_FN_CANFD1_TX, - GPIO_FN_IETX_A, - GPIO_IFN_RDx, - GPIO_FN_MSIOF3_SYNC_D, - GPIO_FN_RX3_A, - GPIO_FN_HRX3_A, - GPIO_FN_CAN0_TX_A, - GPIO_FN_CANFD0_TX_A, - GPIO_IFN_RD_WRx, - GPIO_FN_MSIOF3_RXD_D, - GPIO_FN_TX3_A, - GPIO_FN_HTX3_A, - GPIO_FN_CAN0_RX_A, - GPIO_FN_CANFD0_RX_A, - - /* IPSR5 */ - GPIO_IFN_WE0x, - GPIO_FN_MSIIOF3_TXD_D, - GPIO_FN_CTS3x, - GPIO_FN_HCTS3x, - GPIO_FN_SCL6_B, - GPIO_FN_CAN_CLK, - GPIO_FN_IECLK_A, - GPIO_IFN_WE1x, - GPIO_FN_MSIOF3_SS1_D, - GPIO_FN_RTS3x_TANS, - GPIO_FN_HRTS3x, - GPIO_FN_SDA6_B, - GPIO_FN_CAN1_RX, - GPIO_FN_CANFD1_RX, - GPIO_FN_IERX_A, - GPIO_IFN_EX_WAIT0_A, - GPIO_FN_QCLK, - GPIO_FN_VI4_CLK, - GPIO_FN_DU_DOTCLKOUT0, - GPIO_IFN_D0, - GPIO_FN_MSIOF2_SS1_B, - GPIO_FN_MSIOF3_SCK_A, - GPIO_FN_VI4_DATA16, - GPIO_FN_VI5_DATA0, - GPIO_IFN_D1, - GPIO_FN_MSIOF2_SS2_B, - GPIO_FN_MSIOF3_SYNC_A, - GPIO_FN_VI4_DATA17, - GPIO_FN_VI5_DATA1, - GPIO_IFN_D2, - GPIO_FN_MSIOF3_RXD_A, - GPIO_FN_VI4_DATA18, - GPIO_FN_VI5_DATA2, - GPIO_IFN_D3, - GPIO_FN_MSIOF3_TXD_A, - GPIO_FN_VI4_DATA19, - GPIO_FN_VI5_DATA3, - GPIO_IFN_D4, - GPIO_FN_MSIOF2_SCK_B, - GPIO_FN_VI4_DATA20, - GPIO_FN_VI5_DATA4, - - /* IPSR6 */ - GPIO_IFN_D5, - GPIO_FN_MSIOF2_SYNC_B, - GPIO_FN_VI4_DATA21, - GPIO_FN_VI5_DATA5, - GPIO_IFN_D6, - GPIO_FN_MSIOF2_RXD_B, - GPIO_FN_VI4_DATA22, - GPIO_FN_VI5_DATA6, - GPIO_IFN_D7, - GPIO_FN_MSIOF2_TXD_B, - GPIO_FN_VI4_DATA23, - GPIO_FN_VI5_DATA7, - GPIO_IFN_D8, - GPIO_FN_LCDOUT0, - GPIO_FN_MSIOF2_SCK_D, - GPIO_FN_SCK4_C, - GPIO_FN_VI4_DATA0_A, - GPIO_FN_DU_DR0, - GPIO_IFN_D9, - GPIO_FN_LCDOUT1, - GPIO_FN_MSIOF2_SYNC_D, - GPIO_FN_VI4_DATA1_A, - GPIO_FN_DU_DR1, - GPIO_IFN_D10, - GPIO_FN_LCDOUT2, - GPIO_FN_MSIOF2_RXD_D, - GPIO_FN_HRX3_B, - GPIO_FN_VI4_DATA2_A, - GPIO_FN_CTS4x_C, - GPIO_FN_DU_DR2, - GPIO_IFN_D11, - GPIO_FN_LCDOUT3, - GPIO_FN_MSIOF2_TXD_D, - GPIO_FN_HTX3_B, - GPIO_FN_VI4_DATA3_A, - GPIO_FN_RTS4x_TANS_C, - GPIO_FN_DU_DR3, - GPIO_IFN_D12, - GPIO_FN_LCDOUT4, - GPIO_FN_MSIOF2_SS1_D, - GPIO_FN_RX4_C, - GPIO_FN_VI4_DATA4_A, - GPIO_FN_DU_DR4, - - /* IPSR7 */ - GPIO_IFN_D13, - GPIO_FN_LCDOUT5, - GPIO_FN_MSIOF2_SS2_D, - GPIO_FN_TX4_C, - GPIO_FN_VI4_DATA5_A, - GPIO_FN_DU_DR5, - GPIO_IFN_D14, - GPIO_FN_LCDOUT6, - GPIO_FN_MSIOF3_SS1_A, - GPIO_FN_HRX3_C, - GPIO_FN_VI4_DATA6_A, - GPIO_FN_DU_DR6, - GPIO_FN_SCL6_C, - GPIO_IFN_D15, - GPIO_FN_LCDOUT7, - GPIO_FN_MSIOF3_SS2_A, - GPIO_FN_HTX3_C, - GPIO_FN_VI4_DATA7_A, - GPIO_FN_DU_DR7, - GPIO_FN_SDA6_C, - GPIO_FN_FSCLKST, - GPIO_IFN_SD0_CLK, - GPIO_FN_MSIOF1_SCK_E, - GPIO_FN_STP_OPWM_0_B, - GPIO_IFN_SD0_CMD, - GPIO_FN_MSIOF1_SYNC_E, - GPIO_FN_STP_IVCXO27_0_B, - GPIO_IFN_SD0_DAT0, - GPIO_FN_MSIOF1_RXD_E, - GPIO_FN_TS_SCK0_B, - GPIO_FN_STP_ISCLK_0_B, - GPIO_IFN_SD0_DAT1, - GPIO_FN_MSIOF1_TXD_E, - GPIO_FN_TS_SPSYNC0_B, - GPIO_FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - GPIO_IFN_SD0_DAT2, - GPIO_FN_MSIOF1_SS1_E, - GPIO_FN_TS_SDAT0_B, - GPIO_FN_STP_ISD_0_B, - - GPIO_IFN_SD0_DAT3, - GPIO_FN_MSIOF1_SS2_E, - GPIO_FN_TS_SDEN0_B, - GPIO_FN_STP_ISEN_0_B, - - GPIO_IFN_SD1_CLK, - GPIO_FN_MSIOF1_SCK_G, - GPIO_FN_SIM0_CLK_A, - - GPIO_IFN_SD1_CMD, - GPIO_FN_MSIOF1_SYNC_G, - GPIO_FN_NFCEx_B, - GPIO_FN_SIM0_D_A, - GPIO_FN_STP_IVCXO27_1_B, - - GPIO_IFN_SD1_DAT0, - GPIO_FN_SD2_DAT4, - GPIO_FN_MSIOF1_RXD_G, - GPIO_FN_NFWPx_B, - GPIO_FN_TS_SCK1_B, - GPIO_FN_STP_ISCLK_1_B, - - GPIO_IFN_SD1_DAT1, - GPIO_FN_SD2_DAT5, - GPIO_FN_MSIOF1_TXD_G, - GPIO_FN_NFDATA14_B, - GPIO_FN_TS_SPSYNC1_B, - GPIO_FN_STP_ISSYNC_1_B, - - GPIO_IFN_SD1_DAT2, - GPIO_FN_SD2_DAT6, - GPIO_FN_MSIOF1_SS1_G, - GPIO_FN_NFDATA15_B, - GPIO_FN_TS_SDAT1_B, - GPIO_FN_STP_IOD_1_B, - - GPIO_IFN_SD1_DAT3, - GPIO_FN_SD2_DAT7, - GPIO_FN_MSIOF1_SS2_G, - GPIO_FN_NFRBx_B, - GPIO_FN_TS_SDEN1_B, - GPIO_FN_STP_ISEN_1_B, - - /* IPSR9 */ - GPIO_IFN_SD2_CLK, - GPIO_FN_NFDATA8, - - GPIO_IFN_SD2_CMD, - GPIO_FN_NFDATA9, - - GPIO_IFN_SD2_DAT0, - GPIO_FN_NFDATA10, - - GPIO_IFN_SD2_DAT1, - GPIO_FN_NFDATA11, - - GPIO_IFN_SD2_DAT2, - GPIO_FN_NFDATA12, - - GPIO_IFN_SD2_DAT3, - GPIO_FN_NFDATA13, - - GPIO_IFN_SD2_DS, - GPIO_FN_NFALE, - - GPIO_IFN_SD3_CLK, - GPIO_FN_NFWEx, - - /* IPSR10 */ - GPIO_IFN_SD3_CMD, - GPIO_FN_NFREx, - - GPIO_IFN_SD3_DAT0, - GPIO_FN_NFDATA0, - - GPIO_IFN_SD3_DAT1, - GPIO_FN_NFDATA1, - - GPIO_IFN_SD3_DAT2, - GPIO_FN_NFDATA2, - - GPIO_IFN_SD3_DAT3, - GPIO_FN_NFDATA3, - - GPIO_IFN_SD3_DAT4, - GPIO_FN_SD2_CD_A, - GPIO_FN_NFDATA4, - - GPIO_IFN_SD3_DAT5, - GPIO_FN_SD2_WP_A, - GPIO_FN_NFDATA5, - - GPIO_IFN_SD3_DAT6, - GPIO_FN_SD3_CD, - GPIO_FN_NFDATA6, - - /* IPSR11 */ - GPIO_IFN_SD3_DAT7, - GPIO_FN_SD3_WP, - GPIO_FN_NFDATA7, - - GPIO_IFN_SD3_DS, - GPIO_FN_NFCLE, - - GPIO_IFN_SD0_CD, - GPIO_FN_NFDATA14_A, - GPIO_FN_SCL2_B, - GPIO_FN_SIM0_RST_A, - - GPIO_IFN_SD0_WP, - GPIO_FN_NFDATA15_A, - GPIO_FN_SDA2_B, - - GPIO_IFN_SD1_CD, - GPIO_FN_NFRBx_A, - GPIO_FN_SIM0_CLK_B, - - GPIO_IFN_SD1_WP, - GPIO_FN_NFCEx_A, - GPIO_FN_SIM0_D_B, - - GPIO_IFN_SCK0, - GPIO_FN_HSCK1_B, - GPIO_FN_MSIOF1_SS2_B, - GPIO_FN_AUDIO_CLKC_B, - GPIO_FN_SDA2_A, - GPIO_FN_SIM0_RST_B, - GPIO_FN_STP_OPWM_0_C, - GPIO_FN_RIF0_CLK_B, - GPIO_FN_ADICHS2, - GPIO_FN_SCK5_B, - - GPIO_IFN_RX0, - GPIO_FN_HRX1_B, - GPIO_FN_TS_SCK0_C, - GPIO_FN_STP_ISCLK_0_C, - GPIO_FN_RIF0_D0_B, - - /* IPSR12 */ - GPIO_IFN_TX0, - GPIO_FN_HTX1_B, - GPIO_FN_TS_SPSYNC0_C, - GPIO_FN_STP_ISSYNC_0_C, - GPIO_FN_RIF0_D1_B, - - GPIO_IFN_CTS0x, - GPIO_FN_HCTS1x_B, - GPIO_FN_MSIOF1_SYNC_B, - GPIO_FN_TS_SPSYNC1_C, - GPIO_FN_STP_ISSYNC_1_C, - GPIO_FN_RIF1_SYNC_B, - GPIO_FN_AUDIO_CLKOUT_C, - GPIO_FN_ADICS_SAMP, - - GPIO_IFN_RTS0x_TANS, - GPIO_FN_HRTS1x_B, - GPIO_FN_MSIOF1_SS1_B, - GPIO_FN_AUDIO_CLKA_B, - GPIO_FN_SCL2_A, - GPIO_FN_STP_IVCXO27_1_C, - GPIO_FN_RIF0_SYNC_B, - GPIO_FN_ADICHS1, - - GPIO_IFN_RX1_A, - GPIO_FN_HRX1_A, - GPIO_FN_TS_SDAT0_C, - GPIO_FN_STP_ISD_0_C, - GPIO_FN_RIF1_CLK_C, - - GPIO_IFN_TX1_A, - GPIO_FN_HTX1_A, - GPIO_FN_TS_SDEN0_C, - GPIO_FN_STP_ISEN_0_C, - GPIO_FN_RIF1_D0_C, - - GPIO_IFN_CTS1x, - GPIO_FN_HCTS1x_A, - GPIO_FN_MSIOF1_RXD_B, - GPIO_FN_TS_SDEN1_C, - GPIO_FN_STP_ISEN_1_C, - GPIO_FN_RIF1_D0_B, - GPIO_FN_ADIDATA, - - GPIO_IFN_RTS1x_TANS, - GPIO_FN_HRTS1x_A, - GPIO_FN_MSIOF1_TXD_B, - GPIO_FN_TS_SDAT1_C, - GPIO_FN_STP_ISD_1_C, - GPIO_FN_RIF1_D1_B, - GPIO_FN_ADICHS0, - - GPIO_IFN_SCK2, - GPIO_FN_SCIF_CLK_B, - GPIO_FN_MSIOF1_SCK_B, - GPIO_FN_TS_SCK1_C, - GPIO_FN_STP_ISCLK_1_C, - GPIO_FN_RIF1_CLK_B, - GPIO_FN_ADICLK, - - /* IPSR13 */ - GPIO_IFN_TX2_A, - GPIO_FN_SD2_CD_B, - GPIO_FN_SCL1_A, - GPIO_FN_FMCLK_A, - GPIO_FN_RIF1_D1_C, - GPIO_FN_FSO_CFE_0_B, - - GPIO_IFN_RX2_A, - GPIO_FN_SD2_WP_B, - GPIO_FN_SDA1_A, - GPIO_FN_FMIN_A, - GPIO_FN_RIF1_SYNC_C, - GPIO_FN_FSO_CEF_1_B, - - GPIO_IFN_HSCK0, - GPIO_FN_MSIOF1_SCK_D, - GPIO_FN_AUDIO_CLKB_A, - GPIO_FN_SSI_SDATA1_B, - GPIO_FN_TS_SCK0_D, - GPIO_FN_STP_ISCLK_0_D, - GPIO_FN_RIF0_CLK_C, - GPIO_FN_RX5_B, - - GPIO_IFN_HRX0, - GPIO_FN_MSIOF1_RXD_D, - GPIO_FN_SS1_SDATA2_B, - GPIO_FN_TS_SDEN0_D, - GPIO_FN_STP_ISEN_0_D, - GPIO_FN_RIF0_D0_C, - - GPIO_IFN_HTX0, - GPIO_FN_MSIOF1_TXD_D, - GPIO_FN_SSI_SDATA9_B, - GPIO_FN_TS_SDAT0_D, - GPIO_FN_STP_ISD_0_D, - GPIO_FN_RIF0_D1_C, - - GPIO_IFN_HCTS0x, - GPIO_FN_RX2_B, - GPIO_FN_MSIOF1_SYNC_D, - GPIO_FN_SSI_SCK9_A, - GPIO_FN_TS_SPSYNC0_D, - GPIO_FN_STP_ISSYNC_0_D, - GPIO_FN_RIF0_SYNC_C, - GPIO_FN_AUDIO_CLKOUT1_A, - - GPIO_IFN_HRTS0x, - GPIO_FN_TX2_B, - GPIO_FN_MSIOF1_SS1_D, - GPIO_FN_SSI_WS9_A, - GPIO_FN_STP_IVCXO27_0_D, - GPIO_FN_BPFCLK_A, - GPIO_FN_AUDIO_CLKOUT2_A, - - GPIO_IFN_MSIOF0_SYNC, - GPIO_FN_AUDIO_CLKOUT_A, - GPIO_FN_TX5_B, - GPIO_FN_BPFCLK_D, - - /* IPSR14 */ - GPIO_IFN_MSIOF0_SS1, - GPIO_FN_RX5_A, - GPIO_FN_NFWPx_A, - GPIO_FN_AUDIO_CLKA_C, - GPIO_FN_SSI_SCK2_A, - GPIO_FN_STP_IVCXO27_0_C, - GPIO_FN_AUDIO_CLKOUT3_A, - GPIO_FN_TCLK1_B, - - GPIO_IFN_MSIOF0_SS2, - GPIO_FN_TX5_A, - GPIO_FN_MSIOF1_SS2_D, - GPIO_FN_AUDIO_CLKC_A, - GPIO_FN_SSI_WS2_A, - GPIO_FN_STP_OPWM_0_D, - GPIO_FN_AUDIO_CLKOUT_D, - GPIO_FN_SPEEDIN_B, - - GPIO_IFN_MLB_CLK, - GPIO_FN_MSIOF1_SCK_F, - GPIO_FN_SCL1_B, - - GPIO_IFN_MLB_SIG, - GPIO_FN_RX1_B, - GPIO_FN_MSIOF1_SYNC_F, - GPIO_FN_SDA1_B, - - GPIO_IFN_MLB_DAT, - GPIO_FN_TX1_B, - GPIO_FN_MSIOF1_RXD_F, - - GPIO_IFN_SSI_SCK0129, - GPIO_FN_MSIOF1_TXD_F, - GPIO_FN_MOUT0, - - GPIO_IFN_SSI_WS0129, - GPIO_FN_MSIOF1_SS1_F, - GPIO_FN_MOUT1, - - GPIO_IFN_SSI_SDATA0, - GPIO_FN_MSIOF1_SS2_F, - GPIO_FN_MOUT2, - - /* IPSR15 */ - GPIO_IFN_SSI_SDATA1_A, - GPIO_FN_MOUT5, - - GPIO_IFN_SSI_SDATA2_A, - GPIO_FN_SSI_SCK1_B, - GPIO_FN_MOUT6, - - GPIO_IFN_SSI_SCK34, - GPIO_FN_MSIOF1_SS1_A, - GPIO_FN_STP_OPWM_0_A, - - GPIO_IFN_SSI_WS34, - GPIO_FN_HCTS2x_A, - GPIO_FN_MSIOF1_SS2_A, - GPIO_FN_STP_IVCXO27_0_A, - - GPIO_IFN_SSI_SDATA3, - GPIO_FN_HRTS2x_A, - GPIO_FN_MSIOF1_TXD_A, - GPIO_FN_TS_SCK0_A, - GPIO_FN_STP_ISCLK_0_A, - GPIO_FN_RIF0_D1_A, - GPIO_FN_RIF2_D0_A, - - GPIO_IFN_SSI_SCK4, - GPIO_FN_HRX2_A, - GPIO_FN_MSIOF1_SCK_A, - GPIO_FN_TS_SDAT0_A, - GPIO_FN_STP_ISD_0_A, - GPIO_FN_RIF0_CLK_A, - GPIO_FN_RIF2_CLK_A, - - GPIO_IFN_SSI_WS4, - GPIO_FN_HTX2_A, - GPIO_FN_MSIOF1_SYNC_A, - GPIO_FN_TS_SDEN0_A, - GPIO_FN_STP_ISEN_0_A, - GPIO_FN_RIF0_SYNC_A, - GPIO_FN_RIF2_SYNC_A, - - GPIO_IFN_SSI_SDATA4, - GPIO_FN_HSCK2_A, - GPIO_FN_MSIOF1_RXD_A, - GPIO_FN_TS_SPSYNC0_A, - GPIO_FN_STP_ISSYNC_0_A, - GPIO_FN_RIF0_D0_A, - GPIO_FN_RIF2_D1_A, - - /* IPSR16 */ - GPIO_IFN_SSI_SCK6, - GPIO_FN_SIM0_RST_D, - GPIO_FN_FSO_TOE_A, - - GPIO_IFN_SSI_WS6, - GPIO_FN_SIM0_D_D, - - GPIO_IFN_SSI_SDATA6, - GPIO_FN_SIM0_CLK_D, - - GPIO_IFN_SSI_SCK78, - GPIO_FN_HRX2_B, - GPIO_FN_MSIOF1_SCK_C, - GPIO_FN_TS_SCK1_A, - GPIO_FN_STP_ISCLK_1_A, - GPIO_FN_RIF1_CLK_A, - GPIO_FN_RIF3_CLK_A, - - GPIO_IFN_SSI_WS78, - GPIO_FN_HTX2_B, - GPIO_FN_MSIOF1_SYNC_C, - GPIO_FN_TS_SDAT1_A, - GPIO_FN_STP_ISD_1_A, - GPIO_FN_RIF1_SYNC_A, - GPIO_FN_RIF3_SYNC_A, - - GPIO_IFN_SSI_SDATA7, - GPIO_FN_HCTS2x_B, - GPIO_FN_MSIOF1_RXD_C, - GPIO_FN_TS_SDEN1_A, - GPIO_FN_STP_IEN_1_A, - GPIO_FN_RIF1_D0_A, - GPIO_FN_RIF3_D0_A, - GPIO_FN_TCLK2_A, - - GPIO_IFN_SSI_SDATA8, - GPIO_FN_HRTS2x_B, - GPIO_FN_MSIOF1_TXD_C, - GPIO_FN_TS_SPSYNC1_A, - GPIO_FN_STP_ISSYNC_1_A, - GPIO_FN_RIF1_D1_A, - GPIO_FN_EIF3_D1_A, - - GPIO_IFN_SSI_SDATA9_A, - GPIO_FN_HSCK2_B, - GPIO_FN_MSIOF1_SS1_C, - GPIO_FN_HSCK1_A, - GPIO_FN_SSI_WS1_B, - GPIO_FN_SCK1, - GPIO_FN_STP_IVCXO27_1_A, - GPIO_FN_SCK5, - - /* IPSR17 */ - GPIO_IFN_AUDIO_CLKA_A, - GPIO_FN_CC5_OSCOUT, - - GPIO_IFN_AUDIO_CLKB_B, - GPIO_FN_SCIF_CLK_A, - GPIO_FN_STP_IVCXO27_1_D, - GPIO_FN_REMOCON_A, - GPIO_FN_TCLK1_A, - - GPIO_IFN_USB0_PWEN, - GPIO_FN_SIM0_RST_C, - GPIO_FN_TS_SCK1_D, - GPIO_FN_STP_ISCLK_1_D, - GPIO_FN_BPFCLK_B, - GPIO_FN_RIF3_CLK_B, - GPIO_FN_FSO_CFE_1_A, - GPIO_FN_HSCK2_C, - - GPIO_IFN_USB0_OVC, - GPIO_FN_SIM0_D_C, - GPIO_FN_TS_SDAT1_D, - GPIO_FN_STP_ISD_1_D, - GPIO_FN_RIF3_SYNC_B, - GPIO_FN_HRX2_C, - - GPIO_IFN_USB1_PWEN, - GPIO_FN_SIM0_CLK_C, - GPIO_FN_SSI_SCK1_A, - GPIO_FN_TS_SCK0_E, - GPIO_FN_STP_ISCLK_0_E, - GPIO_FN_FMCLK_B, - GPIO_FN_RIF2_CLK_B, - GPIO_FN_SPEEDIN_A, - GPIO_FN_HTX2_C, - - GPIO_IFN_USB1_OVC, - GPIO_FN_MSIOF1_SS2_C, - GPIO_FN_SSI_WS1_A, - GPIO_FN_TS_SDAT0_E, - GPIO_FN_STP_ISD_0_E, - GPIO_FN_FMIN_B, - GPIO_FN_RIF2_SYNC_B, - GPIO_FN_REMOCON_B, - GPIO_FN_HCTS2x_C, - - GPIO_IFN_USB30_PWEN, - GPIO_FN_AUDIO_CLKOUT_B, - GPIO_FN_SSI_SCK2_B, - GPIO_FN_TS_SDEN1_D, - GPIO_FN_STP_ISEN_1_D, - GPIO_FN_STP_OPWM_0_E, - GPIO_FN_RIF3_D0_B, - GPIO_FN_TCLK2_B, - GPIO_FN_TPU0TO0, - GPIO_FN_BPFCLK_C, - GPIO_FN_HRTS2x_C, - - GPIO_IFN_USB30_OVC, - GPIO_FN_AUDIO_CLKOUT1_B, - GPIO_FN_SSI_WS2_B, - GPIO_FN_TS_SPSYNC1_D, - GPIO_FN_STP_ISSYNC_1_D, - GPIO_FN_STP_IVCXO27_0_E, - GPIO_FN_RIF3_D1_B, - GPIO_FN_FSO_TOE_B, - GPIO_FN_TPU0TO1, - - /* IPSR18 */ - GPIO_IFN_GP6_30, - GPIO_FN_AUDIO_CLKOUT2_B, - GPIO_FN_SSI_SCK9_B, - GPIO_FN_TS_SDEN0_E, - GPIO_FN_STP_ISEN_0_E, - GPIO_FN_RIF2_D0_B, - GPIO_FN_FSO_CFE_0_A, - GPIO_FN_TPU0TO2, - GPIO_FN_FMCLK_C, - GPIO_FN_FMCLK_D, - - GPIO_IFN_GP6_31, - GPIO_FN_AUDIO_CLKOUT3_B, - GPIO_FN_SSI_WS9_B, - GPIO_FN_TS_SPSYNC0_E, - GPIO_FN_STP_ISSYNC_0_E, - GPIO_FN_RIF2_D1_B, - GPIO_FN_TPU0TO3, - GPIO_FN_FMIN_C, - GPIO_FN_FMIN_D, - -}; - -#endif /* __ASM_R8A7796_GPIO_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796.h b/arch/arm/mach-rmobile/include/mach/r8a7796.h deleted file mode 100644 index dab60820124..00000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7796.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7796.h - * This file defines registers and value for r8a7796. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_R8A7796_H -#define __ASM_ARCH_R8A7796_H - -#include "rcar-gen3-base.h" - -/* Module stop control/status register bits */ -#define MSTP0_BITS 0x00200000 -#define MSTP1_BITS 0xFFFFFFFF -#define MSTP2_BITS 0x340E2FDC -#define MSTP3_BITS 0xFFFFFFDF -#define MSTP4_BITS 0x80000184 -#define MSTP5_BITS 0xC3FFFFFF -#define MSTP6_BITS 0xFFFFFFFF -#define MSTP7_BITS 0xFFFFFFFF -#define MSTP8_BITS 0x01F1FFF7 -#define MSTP9_BITS 0xFFFFFFFE -#define MSTP10_BITS 0xFFFEFFE0 -#define MSTP11_BITS 0x000000B7 - -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 - -#endif /* __ASM_ARCH_R8A7796_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h index 39726355e67..507859342c1 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -68,12 +68,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 - /* PFC */ #define PFC_PUEN5 0xE6060414 #define PUEN_SSI_SDATA4 BIT(17) diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 654349b0b3d..b413859a4d0 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -16,19 +16,29 @@ #include <asm/arch/r8a7793.h> #elif defined(CONFIG_R8A7794) #include <asm/arch/r8a7794.h> -#elif defined(CONFIG_R8A7795) -#include <asm/arch/r8a7795.h> -#elif defined(CONFIG_R8A7796) -#include <asm/arch/r8a7796.h> +#elif defined(CONFIG_RCAR_GEN3) +#include <asm/arch/rcar-gen3-base.h> #else #error "SOC Name not defined" #endif #endif /* CONFIG_ARCH_RMOBILE */ +/* PRR CPU IDs */ +#define RMOBILE_CPU_TYPE_SH73A0 0x37 +#define RMOBILE_CPU_TYPE_R8A7740 0x40 +#define RMOBILE_CPU_TYPE_R8A7790 0x45 +#define RMOBILE_CPU_TYPE_R8A7791 0x47 +#define RMOBILE_CPU_TYPE_R8A7792 0x4A +#define RMOBILE_CPU_TYPE_R8A7793 0x4B +#define RMOBILE_CPU_TYPE_R8A7794 0x4C +#define RMOBILE_CPU_TYPE_R8A7795 0x4F +#define RMOBILE_CPU_TYPE_R8A7796 0x52 + #ifndef __ASSEMBLY__ u32 rmobile_get_cpu_type(void); u32 rmobile_get_cpu_rev_integer(void); u32 rmobile_get_cpu_rev_fraction(void); +void rcar_gen3_memmap_fixup(void); #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c new file mode 100644 index 00000000000..f3156ab01a8 --- /dev/null +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -0,0 +1,66 @@ +/* + * Renesas RCar Gen3 memory map tables + * + * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region r8a7795_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +static struct mm_region r8a7796_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe0000000UL, + .phys = 0xe0000000UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = r8a7795_mem_map; + +void rcar_gen3_memmap_fixup(void) +{ + u32 cpu_type = rmobile_get_cpu_type(); + + switch (cpu_type) { + case RMOBILE_CPU_TYPE_R8A7795: + mem_map = r8a7795_mem_map; + break; + case RMOBILE_CPU_TYPE_R8A7796: + mem_map = r8a7796_mem_map; + break; + } +} diff --git a/arch/arm/mach-rmobile/memmap-r8a7795.c b/arch/arm/mach-rmobile/memmap-r8a7795.c deleted file mode 100644 index c2c5e48aaf7..00000000000 --- a/arch/arm/mach-rmobile/memmap-r8a7795.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/armv8/mmu.h> - -static struct mm_region r8a7795_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = r8a7795_mem_map; diff --git a/arch/arm/mach-rmobile/memmap-r8a7796.c b/arch/arm/mach-rmobile/memmap-r8a7796.c deleted file mode 100644 index 648743d51e0..00000000000 --- a/arch/arm/mach-rmobile/memmap-r8a7796.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/armv8/mmu.h> - -static struct mm_region r8a7796_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe0000000UL, - .phys = 0xe0000000UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = r8a7796_mem_map; diff --git a/arch/arm/mach-rmobile/pfc-r8a7795.c b/arch/arm/mach-rmobile/pfc-r8a7795.c deleted file mode 100644 index 93aaf31ed96..00000000000 --- a/arch/arm/mach-rmobile/pfc-r8a7795.c +++ /dev/null @@ -1,5005 +0,0 @@ -/* - * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7795.c - * This file is r8a7795 processor support - PFC hardware block. - * - * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <sh_pfc.h> -#include <asm/gpio.h> - -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT1(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT2(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT_29(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##28, sfx) - -#define CPU_32_PORT_28(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx) - -#define CPU_32_PORT_26(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx) - -#define CPU_32_PORT_18(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##16, sfx), \ - PORT_1(fn, pfx##17, sfx) - -#define CPU_32_PORT_16(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx) - -#define CPU_32_PORT_15(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx) - -#define CPU_32_PORT_4(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), \ - PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##3, sfx) - - -/* --gen3-- */ -/* GP_0_0_DATA -> GP_7_4_DATA */ -/* except for GP0[16] - [31], - GP1[28] - [31], - GP2[15] - [31], - GP3[16] - [31], - GP4[18] - [31], - GP5[26] - [31], - GP7[4] - [31] */ - -#define ES_CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_28(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_29(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) - -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - GP_ALL(DATA), - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - GP_ALL(IN), - PINMUX_INPUT_END, - - PINMUX_OUTPUT_BEGIN, - GP_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - GP_ALL(FN), - - /* GPSR0 */ - GFN_D15, - GFN_D14, - GFN_D13, - GFN_D12, - GFN_D11, - GFN_D10, - GFN_D9, - GFN_D8, - GFN_D7, - GFN_D6, - GFN_D5, - GFN_D4, - GFN_D3, - GFN_D2, - GFN_D1, - GFN_D0, - - /* GPSR1 */ - GFN_CLKOUT, - GFN_EX_WAIT0_A, - GFN_WE1x, - GFN_WE0x, - GFN_RD_WRx, - GFN_RDx, - GFN_BSx, - GFN_CS1x_A26, - GFN_CS0x, - GFN_A19, - GFN_A18, - GFN_A17, - GFN_A16, - GFN_A15, - GFN_A14, - GFN_A13, - GFN_A12, - GFN_A11, - GFN_A10, - GFN_A9, - GFN_A8, - GFN_A7, - GFN_A6, - GFN_A5, - GFN_A4, - GFN_A3, - GFN_A2, - GFN_A1, - GFN_A0, - - /* GPSR2 */ - GFN_AVB_AVTP_CAPTURE_A, - GFN_AVB_AVTP_MATCH_A, - GFN_AVB_LINK, - GFN_AVB_PHY_INT, - GFN_AVB_MAGIC, - GFN_AVB_MDC, - GFN_PWM2_A, - GFN_PWM1_A, - GFN_PWM0, - GFN_IRQ5, - GFN_IRQ4, - GFN_IRQ3, - GFN_IRQ2, - GFN_IRQ1, - GFN_IRQ0, - - /* GPSR3 */ - GFN_SD1_WP, - GFN_SD1_CD, - GFN_SD0_WP, - GFN_SD0_CD, - GFN_SD1_DAT3, - GFN_SD1_DAT2, - GFN_SD1_DAT1, - GFN_SD1_DAT0, - GFN_SD1_CMD, - GFN_SD1_CLK, - GFN_SD0_DAT3, - GFN_SD0_DAT2, - GFN_SD0_DAT1, - GFN_SD0_DAT0, - GFN_SD0_CMD, - GFN_SD0_CLK, - - /* GPSR4 */ - GFN_SD3_DS, - GFN_SD3_DAT7, - GFN_SD3_DAT6, - GFN_SD3_DAT5, - GFN_SD3_DAT4, - GFN_SD3_DAT3, - GFN_SD3_DAT2, - GFN_SD3_DAT1, - GFN_SD3_DAT0, - GFN_SD3_CMD, - GFN_SD3_CLK, - GFN_SD2_DS, - GFN_SD2_DAT3, - GFN_SD2_DAT2, - GFN_SD2_DAT1, - GFN_SD2_DAT0, - GFN_SD2_CMD, - GFN_SD2_CLK, - - /* GPSR5 */ - GFN_MLB_DAT, - GFN_MLB_SIG, - GFN_MLB_CLK, - FN_MSIOF0_RXD, - GFN_MSIOF0_SS2, - FN_MSIOF0_TXD, - GFN_MSIOF0_SS1, - GFN_MSIOF0_SYNC, - FN_MSIOF0_SCK, - GFN_HRTS0x, - GFN_HCTS0x, - GFN_HTX0, - GFN_HRX0, - GFN_HSCK0, - GFN_RX2_A, - GFN_TX2_A, - GFN_SCK2, - GFN_RTS1x_TANS, - GFN_CTS1x, - GFN_TX1_A, - GFN_RX1_A, - GFN_RTS0x_TANS, - GFN_CTS0x, - GFN_TX0, - GFN_RX0, - GFN_SCK0, - - /* GPSR6 */ - GFN_USB3_OVC, - GFN_USB3_PWEN, - GFN_USB30_OVC, - GFN_USB30_PWEN, - GFN_USB1_OVC, - GFN_USB1_PWEN, - GFN_USB0_OVC, - GFN_USB0_PWEN, - GFN_AUDIO_CLKB_B, - GFN_AUDIO_CLKA_A, - GFN_SSI_SDATA9_A, - GFN_SSI_SDATA8, - GFN_SSI_SDATA7, - GFN_SSI_WS78, - GFN_SSI_SCK78, - GFN_SSI_SDATA6, - GFN_SSI_WS6, - GFN_SSI_SCK6, - FN_SSI_SDATA5, - FN_SSI_WS5, - FN_SSI_SCK5, - GFN_SSI_SDATA4, - GFN_SSI_WS4, - GFN_SSI_SCK4, - GFN_SSI_SDATA3, - GFN_SSI_WS34, - GFN_SSI_SCK34, - GFN_SSI_SDATA2_A, - GFN_SSI_SDATA1_A, - GFN_SSI_SDATA0, - GFN_SSI_WS01239, - GFN_SSI_SCK01239, - - /* GPSR7 */ - FN_HDMI1_CEC, - FN_HDMI0_CEC, - FN_AVS2, - FN_AVS1, - - /* IPSR0 */ - IFN_AVB_MDC, - FN_MSIOF2_SS2_C, - IFN_AVB_MAGIC, - FN_MSIOF2_SS1_C, - FN_SCK4_A, - IFN_AVB_PHY_INT, - FN_MSIOF2_SYNC_C, - FN_RX4_A, - IFN_AVB_LINK, - FN_MSIOF2_SCK_C, - FN_TX4_A, - IFN_AVB_AVTP_MATCH_A, - FN_MSIOF2_RXD_C, - FN_CTS4x_A, - FN_FSCLKST2x_A, - IFN_AVB_AVTP_CAPTURE_A, - FN_MSIOF2_TXD_C, - FN_RTS4x_TANS_A, - IFN_IRQ0, - FN_QPOLB, - FN_DU_CDE, - FN_VI4_DATA0_B, - FN_CAN0_TX_B, - FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - IFN_IRQ1, - FN_QPOLA, - FN_DU_DISP, - FN_VI4_DATA1_B, - FN_CAN0_RX_B, - FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - - /* IPSR1 */ - IFN_IRQ2, - FN_QCPV_QDE, - FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, - FN_MSIOF3_SYNC_E, - FN_PWM3_B, - IFN_IRQ3, - FN_QSTVB_QVE, - FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, - FN_MSIOF3_SCK_E, - FN_PWM4_B, - IFN_IRQ4, - FN_QSTH_QHS, - FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, - FN_MSIOF3_RXD_E, - FN_PWM5_B, - IFN_IRQ5, - FN_QSTB_QHE, - FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, - FN_FSCLKST2x_B, - FN_MSIOF3_TXD_E, - FN_PWM6_B, - IFN_PWM0, - FN_AVB_AVTP_PPS, - FN_VI4_DATA6_B, - FN_IECLK_B, - IFN_PWM1_A, - FN_HRX3_D, - FN_VI4_DATA7_B, - FN_IERX_B, - IFN_PWM2_A, - FN_HTX3_D, - FN_IETX_B, - IFN_A0, - FN_LCDOUT16, - FN_MSIOF3_SYNC_B, - FN_VI4_DATA8, - FN_DU_DB0, - FN_PWM3_A, - - /* IPSR2 */ - IFN_A1, - FN_LCDOUT17, - FN_MSIOF3_TXD_B, - FN_VI4_DATA9, - FN_DU_DB1, - FN_PWM4_A, - IFN_A2, - FN_LCDOUT18, - FN_MSIOF3_SCK_B, - FN_VI4_DATA10, - FN_DU_DB2, - FN_PWM5_A, - IFN_A3, - FN_LCDOUT19, - FN_MSIOF3_RXD_B, - FN_VI4_DATA11, - FN_DU_DB3, - FN_PWM6_A, - IFN_A4, - FN_LCDOUT20, - FN_MSIOF3_SS1_B, - FN_VI4_DATA12, - FN_VI5_DATA12, - FN_DU_DB4, - IFN_A5, - FN_LCDOUT21, - FN_MSIOF3_SS2_B, - FN_SCK4_B, - FN_VI4_DATA13, - FN_VI5_DATA13, - FN_DU_DB5, - IFN_A6, - FN_LCDOUT22, - FN_MSIOF2_SS1_A, - FN_RX4_B, - FN_VI4_DATA14, - FN_VI5_DATA14, - FN_DU_DB6, - IFN_A7, - FN_LCDOUT23, - FN_MSIOF2_SS2_A, - FN_TX4_B, - FN_VI4_DATA15, - FN_V15_DATA15, - FN_DU_DB7, - IFN_A8, - FN_RX3_B, - FN_MSIOF2_SYNC_A, - FN_HRX4_B, - FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, - FN_PWM1_B, - - /* IPSR3 */ - IFN_A9, - FN_MSIOF2_SCK_A, - FN_CTS4x_B, - FN_VI5_VSYNCx, - IFN_A10, - FN_MSIOF2_RXD_A, - FN_RTS4n_TANS_B, - FN_VI5_HSYNCx, - IFN_A11, - FN_TX3_B, - FN_MSIOF2_TXD_A, - FN_HTX4_B, - FN_HSCK4, - FN_VI5_FIELD, - FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, - FN_PWM2_B, - IFN_A12, - FN_LCDOUT12, - FN_MSIOF3_SCK_C, - FN_HRX4_A, - FN_VI5_DATA8, - FN_DU_DG4, - IFN_A13, - FN_LCDOUT13, - FN_MSIOF3_SYNC_C, - FN_HTX4_A, - FN_VI5_DATA9, - FN_DU_DG5, - IFN_A14, - FN_LCDOUT14, - FN_MSIOF3_RXD_C, - FN_HCTS4x, - FN_VI5_DATA10, - FN_DU_DG6, - IFN_A15, - FN_LCDOUT15, - FN_MSIOF3_TXD_C, - FN_HRTS4x, - FN_VI5_DATA11, - FN_DU_DG7, - IFN_A16, - FN_LCDOUT8, - FN_VI4_FIELD, - FN_DU_DG0, - - /* IPSR4 */ - IFN_A17, - FN_LCDOUT9, - FN_VI4_VSYNCx, - FN_DU_DG1, - IFN_A18, - FN_LCDOUT10, - FN_VI4_HSYNCx, - FN_DU_DG2, - IFN_A19, - FN_LCDOUT11, - FN_VI4_CLKENB, - FN_DU_DG3, - IFN_CS0x, - FN_VI5_CLKENB, - IFN_CS1x_A26, - FN_VI5_CLK, - FN_EX_WAIT0_B, - IFN_BSx, - FN_QSTVA_QVS, - FN_MSIOF3_SCK_D, - FN_SCK3, - FN_HSCK3, - FN_CAN1_TX, - FN_CANFD1_TX, - FN_IETX_A, - IFN_RDx, - FN_MSIOF3_SYNC_D, - FN_RX3_A, - FN_HRX3_A, - FN_CAN0_TX_A, - FN_CANFD0_TX_A, - IFN_RD_WRx, - FN_MSIOF3_RXD_D, - FN_TX3_A, - FN_HTX3_A, - FN_CAN0_RX_A, - FN_CANFD0_RX_A, - - /* IPSR5 */ - IFN_WE0x, - FN_MSIIOF3_TXD_D, - FN_CTS3x, - FN_HCTS3x, - FN_SCL6_B, - FN_CAN_CLK, - FN_IECLK_A, - IFN_WE1x, - FN_MSIOF3_SS1_D, - FN_RTS3x_TANS, - FN_HRTS3x, - FN_SDA6_B, - FN_CAN1_RX, - FN_CANFD1_RX, - FN_IERX_A, - IFN_EX_WAIT0_A, - FN_QCLK, - FN_VI4_CLK, - FN_DU_DOTCLKOUT0, - IFN_D0, - FN_MSIOF2_SS1_B, - FN_MSIOF3_SCK_A, - FN_VI4_DATA16, - FN_VI5_DATA0, - IFN_D1, - FN_MSIOF2_SS2_B, - FN_MSIOF3_SYNC_A, - FN_VI4_DATA17, - FN_VI5_DATA1, - IFN_D2, - FN_MSIOF3_RXD_A, - FN_VI4_DATA18, - FN_VI5_DATA2, - IFN_D3, - FN_MSIOF3_TXD_A, - FN_VI4_DATA19, - FN_VI5_DATA3, - IFN_D4, - FN_MSIOF2_SCK_B, - FN_VI4_DATA20, - FN_VI5_DATA4, - - /* IPSR6 */ - IFN_D5, - FN_MSIOF2_SYNC_B, - FN_VI4_DATA21, - FN_VI5_DATA5, - IFN_D6, - FN_MSIOF2_RXD_B, - FN_VI4_DATA22, - FN_VI5_DATA6, - IFN_D7, - FN_MSIOF2_TXD_B, - FN_VI4_DATA23, - FN_VI5_DATA7, - IFN_D8, - FN_LCDOUT0, - FN_MSIOF2_SCK_D, - FN_SCK4_C, - FN_VI4_DATA0_A, - FN_DU_DR0, - IFN_D9, - FN_LCDOUT1, - FN_MSIOF2_SYNC_D, - FN_VI4_DATA1_A, - FN_DU_DR1, - IFN_D10, - FN_LCDOUT2, - FN_MSIOF2_RXD_D, - FN_HRX3_B, - FN_VI4_DATA2_A, - FN_CTS4x_C, - FN_DU_DR2, - IFN_D11, - FN_LCDOUT3, - FN_MSIOF2_TXD_D, - FN_HTX3_B, - FN_VI4_DATA3_A, - FN_RTS4x_TANS_C, - FN_DU_DR3, - IFN_D12, - FN_LCDOUT4, - FN_MSIOF2_SS1_D, - FN_RX4_C, - FN_VI4_DATA4_A, - FN_DU_DR4, - - /* IPSR7 */ - IFN_D13, - FN_LCDOUT5, - FN_MSIOF2_SS2_D, - FN_TX4_C, - FN_VI4_DATA5_A, - FN_DU_DR5, - IFN_D14, - FN_LCDOUT6, - FN_MSIOF3_SS1_A, - FN_HRX3_C, - FN_VI4_DATA6_A, - FN_DU_DR6, - FN_SCL6_C, - IFN_D15, - FN_LCDOUT7, - FN_MSIOF3_SS2_A, - FN_HTX3_C, - FN_VI4_DATA7_A, - FN_DU_DR7, - FN_SDA6_C, - FN_FSCLKST, - IFN_SD0_CLK, - FN_MSIOF1_SCK_E, - FN_STP_OPWM_0_B, - IFN_SD0_CMD, - FN_MSIOF1_SYNC_E, - FN_STP_IVCXO27_0_B, - IFN_SD0_DAT0, - FN_MSIOF1_RXD_E, - FN_TS_SCK0_B, - FN_STP_ISCLK_0_B, - IFN_SD0_DAT1, - FN_MSIOF1_TXD_E, - FN_TS_SPSYNC0_B, - FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - IFN_SD0_DAT2, - FN_MSIOF1_SS1_E, - FN_TS_SDAT0_B, - FN_STP_ISD_0_B, - IFN_SD0_DAT3, - FN_MSIOF1_SS2_E, - FN_TS_SDEN0_B, - FN_STP_ISEN_0_B, - IFN_SD1_CLK, - FN_MSIOF1_SCK_G, - FN_SIM0_CLK_A, - IFN_SD1_CMD, - FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - FN_SIM0_D_A, - FN_STP_IVCXO27_1_B, - IFN_SD1_DAT0, - FN_SD2_DAT4, - FN_MSIOF1_RXD_G, - FN_NFWPx_B, - FN_TS_SCK1_B, - FN_STP_ISCLK_1_B, - IFN_SD1_DAT1, - FN_SD2_DAT5, - FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - FN_TS_SPSYNC1_B, - FN_STP_ISSYNC_1_B, - IFN_SD1_DAT2, - FN_SD2_DAT6, - FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - FN_TS_SDAT1_B, - FN_STP_IOD_1_B, - IFN_SD1_DAT3, - FN_SD2_DAT7, - FN_MSIOF1_SS2_G, - FN_NFRBx_B, - FN_TS_SDEN1_B, - FN_STP_ISEN_1_B, - - /* IPSR9 */ - IFN_SD2_CLK, - FN_NFDATA8, - IFN_SD2_CMD, - FN_NFDATA9, - IFN_SD2_DAT0, - FN_NFDATA10, - IFN_SD2_DAT1, - FN_NFDATA11, - IFN_SD2_DAT2, - FN_NFDATA12, - IFN_SD2_DAT3, - FN_NFDATA13, - IFN_SD2_DS, - FN_NFALE, - FN_SATA_DEVSLP_B, - IFN_SD3_CLK, - FN_NFWEx, - - /* IPSR10 */ - IFN_SD3_CMD, - FN_NFREx, - IFN_SD3_DAT0, - FN_NFDATA0, - IFN_SD3_DAT1, - FN_NFDATA1, - IFN_SD3_DAT2, - FN_NFDATA2, - IFN_SD3_DAT3, - FN_NFDATA3, - IFN_SD3_DAT4, - FN_SD2_CD_A, - FN_NFDATA4, - IFN_SD3_DAT5, - FN_SD2_WP_A, - FN_NFDATA5, - IFN_SD3_DAT6, - FN_SD3_CD, - FN_NFDATA6, - - /* IPSR11 */ - IFN_SD3_DAT7, - FN_SD3_WP, - FN_NFDATA7, - IFN_SD3_DS, - FN_NFCLE, - IFN_SD0_CD, - FN_NFDATA14_A, - FN_SCL2_B, - FN_SIM0_RST_A, - IFN_SD0_WP, - FN_NFDATA15_A, - FN_SDA2_B, - IFN_SD1_CD, - FN_NFRBx_A, - FN_SIM0_CLK_B, - IFN_SD1_WP, - FN_NFCEx_A, - FN_SIM0_D_B, - IFN_SCK0, - FN_HSCK1_B, - FN_MSIOF1_SS2_B, - FN_AUDIO_CLKC_B, - FN_SDA2_A, - FN_SIM0_RST_B, - FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - FN_ADICHS2, - FN_SCK5_B, - IFN_RX0, - FN_HRX1_B, - FN_TS_SCK0_C, - FN_STP_ISCLK_0_C, - FN_RIF0_D0_B, - - /* IPSR12 */ - IFN_TX0, - FN_HTX1_B, - FN_TS_SPSYNC0_C, - FN_STP_ISSYNC_0_C, - FN_RIF0_D1_B, - IFN_CTS0x, - FN_HCTS1x_B, - FN_MSIOF1_SYNC_B, - FN_TS_SPSYNC1_C, - FN_STP_ISSYNC_1_C, - FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, - FN_ADICS_SAMP, - IFN_RTS0x_TANS, - FN_HRTS1x_B, - FN_MSIOF1_SS1_B, - FN_AUDIO_CLKA_B, - FN_SCL2_A, - FN_STP_IVCXO27_1_C, - FN_RIF0_SYNC_B, - FN_ADICHS1, - IFN_RX1_A, - FN_HRX1_A, - FN_TS_SDAT0_C, - FN_STP_ISD_0_C, - FN_RIF1_CLK_C, - IFN_TX1_A, - FN_HTX1_A, - FN_TS_SDEN0_C, - FN_STP_ISEN_0_C, - FN_RIF1_D0_C, - IFN_CTS1x, - FN_HCTS1x_A, - FN_MSIOF1_RXD_B, - FN_TS_SDEN1_C, - FN_STP_ISEN_1_C, - FN_RIF1_D0_B, - FN_ADIDATA, - IFN_RTS1x_TANS, - FN_HRTS1x_A, - FN_MSIOF1_TXD_B, - FN_TS_SDAT1_C, - FN_STP_ISD_1_C, - FN_RIF1_D1_B, - FN_ADICHS0, - IFN_SCK2, - FN_SCIF_CLK_B, - FN_MSIOF1_SCK_B, - FN_TS_SCK1_C, - FN_STP_ISCLK_1_C, - FN_RIF1_CLK_B, - FN_ADICLK, - - /* IPSR13 */ - IFN_TX2_A, - FN_SD2_CD_B, - FN_SCL1_A, - FN_FMCLK_A, - FN_RIF1_D1_C, - FN_FSO_CFE_0x, - IFN_RX2_A, - FN_SD2_WP_B, - FN_SDA1_A, - FN_FMIN_A, - FN_RIF1_SYNC_C, - FN_FSO_CFE_1x, - IFN_HSCK0, - FN_MSIOF1_SCK_D, - FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, - FN_TS_SCK0_D, - FN_STP_ISCLK_0_D, - FN_RIF0_CLK_C, - FN_RX5_B, - IFN_HRX0, - FN_MSIOF1_RXD_D, - FN_SSI_SDATA2_B, - FN_TS_SDEN0_D, - FN_STP_ISEN_0_D, - FN_RIF0_D0_C, - IFN_HTX0, - FN_MSIOF1_TXD_D, - FN_SSI_SDATA9_B, - FN_TS_SDAT0_D, - FN_STP_ISD_0_D, - FN_RIF0_D1_C, - IFN_HCTS0x, - FN_RX2_B, - FN_MSIOF1_SYNC_D, - FN_SSI_SCK9_A, - FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, - IFN_HRTS0x, - FN_TX2_B, - FN_MSIOF1_SS1_D, - FN_SSI_WS9_A, - FN_STP_IVCXO27_0_D, - FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, - IFN_MSIOF0_SYNC, - FN_AUDIO_CLKOUT_A, - FN_TX5_B, - FN_BPFCLK_D, - - /* IPSR14 */ - IFN_MSIOF0_SS1, - FN_RX5_A, - FN_NFWPx_A, - FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, - FN_STP_IVCXO27_0_C, - FN_AUDIO_CLKOUT3_A, - FN_TCLK1_B, - IFN_MSIOF0_SS2, - FN_TX5_A, - FN_MSIOF1_SS2_D, - FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, - FN_STP_OPWM_0_D, - FN_AUDIO_CLKOUT_D, - FN_SPEEDIN_B, - IFN_MLB_CLK, - FN_MSIOF1_SCK_F, - FN_SCL1_B, - IFN_MLB_SIG, - FN_RX1_B, - FN_MSIOF1_SYNC_F, - FN_SDA1_B, - IFN_MLB_DAT, - FN_TX1_B, - FN_MSIOF1_RXD_F, - IFN_SSI_SCK01239, - FN_MSIOF1_TXD_F, - FN_MOUT0, - IFN_SSI_WS01239, - FN_MSIOF1_SS1_F, - FN_MOUT1, - IFN_SSI_SDATA0, - FN_MSIOF1_SS2_F, - FN_MOUT2, - - /* IPSR15 */ - IFN_SSI_SDATA1_A, - FN_MOUT5, - IFN_SSI_SDATA2_A, - FN_SSI_SCK1_B, - FN_MOUT6, - IFN_SSI_SCK34, - FN_MSIOF1_SS1_A, - FN_STP_OPWM_0_A, - IFN_SSI_WS34, - FN_HCTS2x_A, - FN_MSIOF1_SS2_A, - FN_STP_IVCXO27_0_A, - IFN_SSI_SDATA3, - FN_HRTS2x_A, - FN_MSIOF1_TXD_A, - FN_TS_SCK0_A, - FN_STP_ISCLK_0_A, - FN_RIF0_D1_A, - FN_RIF2_D0_A, - IFN_SSI_SCK4, - FN_HRX2_A, - FN_MSIOF1_SCK_A, - FN_TS_SDAT0_A, - FN_STP_ISD_0_A, - FN_RIF0_CLK_A, - FN_RIF2_CLK_A, - IFN_SSI_WS4, - FN_HTX2_A, - FN_MSIOF1_SYNC_A, - FN_TS_SDEN0_A, - FN_STP_ISEN_0_A, - FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, - IFN_SSI_SDATA4, - FN_HSCK2_A, - FN_MSIOF1_RXD_A, - FN_TS_SPSYNC0_A, - FN_STP_ISSYNC_0_A, - FN_RIF0_D0_A, - FN_RIF2_D1_A, - - /* IPSR16 */ - IFN_SSI_SCK6, - FN_SIM0_RST_D, - IFN_SSI_WS6, - FN_SIM0_D_D, - IFN_SSI_SDATA6, - FN_SIM0_CLK_D, - FN_SATA_DEVSLP_A, - IFN_SSI_SCK78, - FN_HRX2_B, - FN_MSIOF1_SCK_C, - FN_TS_SCK1_A, - FN_STP_ISCLK_1_A, - FN_RIF1_CLK_A, - FN_RIF3_CLK_A, - IFN_SSI_WS78, - FN_HTX2_B, - FN_MSIOF1_SYNC_C, - FN_TS_SDAT1_A, - FN_STP_ISD_1_A, - FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, - IFN_SSI_SDATA7, - FN_HCTS2x_B, - FN_MSIOF1_RXD_C, - FN_TS_SDEN1_A, - FN_STP_ISEN_1_A, - FN_RIF1_D0_A, - FN_RIF3_D0_A, - FN_TCLK2_A, - IFN_SSI_SDATA8, - FN_HRTS2x_B, - FN_MSIOF1_TXD_C, - FN_TS_SPSYNC1_A, - FN_STP_ISSYNC_1_A, - FN_RIF1_D1_A, - FN_RIF3_D1_A, - IFN_SSI_SDATA9_A, - FN_HSCK2_B, - FN_MSIOF1_SS1_C, - FN_HSCK1_A, - FN_SSI_WS1_B, - FN_SCK1, - FN_STP_IVCXO27_1_A, - FN_SCK5_A, - - /* IPSR17 */ - IFN_AUDIO_CLKA_A, - FN_CC5_OSCOUT, - IFN_AUDIO_CLKB_B, - FN_SCIF_CLK_A, - FN_STP_IVCXO27_1_D, - FN_REMOCON_A, - FN_TCLK1_A, - IFN_USB0_PWEN, - FN_SIM0_RST_C, - FN_TS_SCK1_D, - FN_STP_ISCLK_1_D, - FN_BPFCLK_B, - FN_RIF3_CLK_B, - FN_HSCK2_C, - IFN_USB0_OVC, - FN_SIM0_D_C, - FN_TS_SDAT1_D, - FN_STP_ISD_1_D, - FN_RIF3_SYNC_B, - FN_HRX2_C, - IFN_USB1_PWEN, - FN_SIM0_CLK_C, - FN_SSI_SCK1_A, - FN_TS_SCK0_E, - FN_STP_ISCLK_0_E, - FN_FMCLK_B, - FN_RIF2_CLK_B, - FN_SPEEDIN_A, - FN_HTX2_C, - IFN_USB1_OVC, - FN_MSIOF1_SS2_C, - FN_SSI_WS1_A, - FN_TS_SDAT0_E, - FN_STP_ISD_0_E, - FN_FMIN_B, - FN_RIF2_SYNC_B, - FN_REMOCON_B, - FN_HCTS2x_C, - IFN_USB30_PWEN, - FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, - FN_TS_SDEN1_D, - FN_STP_ISEN_1_D, - FN_STP_OPWM_0_E, - FN_RIF3_D0_B, - FN_TCLK2_B, - FN_TPU0TO0, - FN_BPFCLK_C, - FN_HRTS2x_C, - IFN_USB30_OVC, - FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, - FN_TS_SPSYNC1_D, - FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, - FN_FSO_TOEx, - FN_TPU0TO1, - - /* IPSR18 */ - IFN_USB3_PWEN, - FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, - FN_TS_SDEN0_E, - FN_STP_ISEN_0_E, - FN_RIF2_D0_B, - FN_TPU0TO2, - FN_FMCLK_C, - FN_FMCLK_D, - IFN_USB3_OVC, - FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, - FN_TS_SPSYNC0_E, - FN_STP_ISSYNC_0_E, - FN_RIF2_D1_B, - FN_TPU0TO3, - FN_FMIN_C, - FN_FMIN_D, - - /* MOD_SEL0 */ - /* sel_msiof3[3](0,1,2,3,4) */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, - /* sel_msiof2[2](0,1,2,3) */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* sel_msiof1[3](0,1,2,3,4,5,6) */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, - /* sel_lbsc[1](0,1) */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* sel_iebus[1](0,1) */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* sel_i2c2[1](0,1) */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* sel_i2c1[1](0,1) */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* sel_hscif4[1](0,1) */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* sel_hscif3[2](0,1,2,3) */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* sel_hscif1[1](0,1) */ - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* reserved[1] */ - /* sel_hscif2[2](0,1,2) */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, - /* sel_etheravb[1](0,1) */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* sel_drif3[1](0,1) */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* sel_drif2[1](0,1) */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* sel_drif1[2](0,1,2) */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, - /* sel_drif0[2](0,1,2) */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, - /* sel_canfd0[1](0,1) */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* sel_adg_a[2](0,1,2) */ - FN_SEL_ADG_A_0, FN_SEL_ADG_A_1, - FN_SEL_ADG_A_2, - /* reserved[3]*/ - - /* MOD_SEL1 */ - /* sel_tsif1[2](0,1,2,3) */ - FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, - /* sel_tsif0[3](0,1,2,3,4) */ - FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - /* sel_timer_tmu1[1](0,1) */ - FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1, - /* sel_ssp1_1[2](0,1,2,3) */ - FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3, - /* sel_ssp1_0[3](0,1,2,3,4) */ - FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - /* sel_ssi1[1](0,1) */ - FN_SEL_SSI_0, FN_SEL_SSI_1, - /* sel_speed_pulse_if[1](0,1) */ - FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, - /* sel_simcard[2](0,1,2,3) */ - FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, - /* sel_sdhi2[1](0,1) */ - FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, - /* sel_scif4[2](0,1,2) */ - FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - /* sel_scif3[1](0,1) */ - FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, - /* sel_scif2[1](0,1) */ - FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, - /* sel_scif1[1](0,1) */ - FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, - /* sel_scif[1](0,1) */ - FN_SEL_SCIF_0, FN_SEL_SCIF_1, - /* sel_remocon[1](0,1) */ - FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, - /* reserved[8..7] */ - /* sel_rcan0[1](0,1) */ - FN_SEL_RCAN_0, FN_SEL_RCAN_1, - /* sel_pwm6[1](0,1) */ - FN_SEL_PWM6_0, FN_SEL_PWM6_1, - /* sel_pwm5[1](0,1) */ - FN_SEL_PWM5_0, FN_SEL_PWM5_1, - /* sel_pwm4[1](0,1) */ - FN_SEL_PWM4_0, FN_SEL_PWM4_1, - /* sel_pwm3[1](0,1) */ - FN_SEL_PWM3_0, FN_SEL_PWM3_1, - /* sel_pwm2[1](0,1) */ - FN_SEL_PWM2_0, FN_SEL_PWM2_1, - /* sel_pwm1[1](0,1) */ - FN_SEL_PWM1_0, FN_SEL_PWM1_1, - - /* MOD_SEL2 */ - /* i2c_sel_5[1](0,1) */ - FN_I2C_SEL_5_0, FN_I2C_SEL_5_1, - /* i2c_sel_3[1](0,1) */ - FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, - /* i2c_sel_0[1](0,1) */ - FN_I2C_SEL_0_0, FN_I2C_SEL_0_1, - /* sel_fm[2](0,1,2,3) */ - FN_SEL_FM_0, FN_SEL_FM_1, - FN_SEL_FM_2, FN_SEL_FM_3, - /* sel_scif5[1](0,1) */ - FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - /* sel_i2c6[3](0,1,2) */ - FN_SEL_I2C6_0, FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - /* sel_ndfc[1](0,1) */ - FN_SEL_NDFC_0, FN_SEL_NDFC_1, - /* sel_ssi2[1](0,1) */ - FN_SEL_SSI2_0, FN_SEL_SSI2_1, - /* sel_ssi9[1](0,1) */ - FN_SEL_SSI9_0, FN_SEL_SSI9_1, - /* sel_timer_tmu2[1](0,1) */ - FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1, - /* sel_adg_b[1](0,1) */ - FN_SEL_ADG_B_0, FN_SEL_ADG_B_1, - /* sel_adg_c[1](0,1) */ - FN_SEL_ADG_C_0, FN_SEL_ADG_C_1, - /* reserved[16..16] */ - /* reserved[15..8] */ - /* reserved[7..1] */ - /* sel_vin4[1](0,1) */ - FN_SEL_VIN4_0, FN_SEL_VIN4_1, - - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - /* GPSR0 */ - D15_GMARK, - D14_GMARK, - D13_GMARK, - D12_GMARK, - D11_GMARK, - D10_GMARK, - D9_GMARK, - D8_GMARK, - D7_GMARK, - D6_GMARK, - D5_GMARK, - D4_GMARK, - D3_GMARK, - D2_GMARK, - D1_GMARK, - D0_GMARK, - - /* GPSR1 */ - CLKOUT_GMARK, - EX_WAIT0_A_GMARK, - WE1x_GMARK, - WE0x_GMARK, - RD_WRx_GMARK, - RDx_GMARK, - BSx_GMARK, - CS1x_A26_GMARK, - CS0x_GMARK, - A19_GMARK, - A18_GMARK, - A17_GMARK, - A16_GMARK, - A15_GMARK, - A14_GMARK, - A13_GMARK, - A12_GMARK, - A11_GMARK, - A10_GMARK, - A9_GMARK, - A8_GMARK, - A7_GMARK, - A6_GMARK, - A5_GMARK, - A4_GMARK, - A3_GMARK, - A2_GMARK, - A1_GMARK, - A0_GMARK, - - /* GPSR2 */ - AVB_AVTP_CAPTURE_A_GMARK, - AVB_AVTP_MATCH_A_GMARK, - AVB_LINK_GMARK, - AVB_PHY_INT_GMARK, - AVB_MAGIC_GMARK, - AVB_MDC_GMARK, - PWM2_A_GMARK, - PWM1_A_GMARK, - PWM0_GMARK, - IRQ5_GMARK, - IRQ4_GMARK, - IRQ3_GMARK, - IRQ2_GMARK, - IRQ1_GMARK, - IRQ0_GMARK, - - /* GPSR3 */ - SD1_WP_GMARK, - SD1_CD_GMARK, - SD0_WP_GMARK, - SD0_CD_GMARK, - SD1_DAT3_GMARK, - SD1_DAT2_GMARK, - SD1_DAT1_GMARK, - SD1_DAT0_GMARK, - SD1_CMD_GMARK, - SD1_CLK_GMARK, - SD0_DAT3_GMARK, - SD0_DAT2_GMARK, - SD0_DAT1_GMARK, - SD0_DAT0_GMARK, - SD0_CMD_GMARK, - SD0_CLK_GMARK, - - /* GPSR4 */ - SD3_DS_GMARK, - SD3_DAT7_GMARK, - SD3_DAT6_GMARK, - SD3_DAT5_GMARK, - SD3_DAT4_GMARK, - SD3_DAT3_GMARK, - SD3_DAT2_GMARK, - SD3_DAT1_GMARK, - SD3_DAT0_GMARK, - SD3_CMD_GMARK, - SD3_CLK_GMARK, - SD2_DS_GMARK, - SD2_DAT3_GMARK, - SD2_DAT2_GMARK, - SD2_DAT1_GMARK, - SD2_DAT0_GMARK, - SD2_CMD_GMARK, - SD2_CLK_GMARK, - - /* GPSR5 */ - MLB_DAT_GMARK, - MLB_SIG_GMARK, - MLB_CLK_GMARK, - MSIOF0_RXD_MARK, - MSIOF0_SS2_GMARK, - MSIOF0_TXD_MARK, - MSIOF0_SS1_GMARK, - MSIOF0_SYNC_GMARK, - MSIOF0_SCK_MARK, - HRTS0x_GMARK, - HCTS0x_GMARK, - HTX0_GMARK, - HRX0_GMARK, - HSCK0_GMARK, - RX2_A_GMARK, - TX2_A_GMARK, - SCK2_GMARK, - RTS1x_TANS_GMARK, - CTS1x_GMARK, - TX1_A_GMARK, - RX1_A_GMARK, - RTS0x_TANS_GMARK, - CTS0x_GMARK, - TX0_GMARK, - RX0_GMARK, - SCK0_GMARK, - - /* GPSR6 */ - USB3_OVC_GMARK, - USB3_PWEN_GMARK, - USB30_OVC_GMARK, - USB30_PWEN_GMARK, - USB1_OVC_GMARK, - USB1_PWEN_GMARK, - USB0_OVC_GMARK, - USB0_PWEN_GMARK, - AUDIO_CLKB_B_GMARK, - AUDIO_CLKA_A_GMARK, - SSI_SDATA9_A_GMARK, - SSI_SDATA8_GMARK, - SSI_SDATA7_GMARK, - SSI_WS78_GMARK, - SSI_SCK78_GMARK, - SSI_SDATA6_GMARK, - SSI_WS6_GMARK, - SSI_SCK6_GMARK, - SSI_SDATA5_MARK, - SSI_WS5_MARK, - SSI_SCK5_MARK, - SSI_SDATA4_GMARK, - SSI_WS4_GMARK, - SSI_SCK4_GMARK, - SSI_SDATA3_GMARK, - SSI_WS34_GMARK, - SSI_SCK34_GMARK, - SSI_SDATA2_A_GMARK, - SSI_SDATA1_A_GMARK, - SSI_SDATA0_GMARK, - SSI_WS01239_GMARK, - SSI_SCK01239_GMARK, - - /* GPSR7 */ - HDMI1_CEC_MARK, - HDMI0_CEC_MARK, - AVS2_MARK, - AVS1_MARK, - - /* IPSR0 */ - AVB_MDC_IMARK, - MSIOF2_SS2_C_MARK, - AVB_MAGIC_IMARK, - MSIOF2_SS1_C_MARK, - SCK4_A_MARK, - AVB_PHY_INT_IMARK, - MSIOF2_SYNC_C_MARK, - RX4_A_MARK, - AVB_LINK_IMARK, - MSIOF2_SCK_C_MARK, - TX4_A_MARK, - AVB_AVTP_MATCH_A_IMARK, - MSIOF2_RXD_C_MARK, - CTS4x_A_MARK, - FSCLKST2x_A_MARK, - AVB_AVTP_CAPTURE_A_IMARK, - MSIOF2_TXD_C_MARK, - RTS4x_TANS_A_MARK, - IRQ0_IMARK, - QPOLB_MARK, - DU_CDE_MARK, - VI4_DATA0_B_MARK, - CAN0_TX_B_MARK, - CANFD0_TX_B_MARK, - MSIOF3_SS2_E_MARK, - IRQ1_IMARK, - QPOLA_MARK, - DU_DISP_MARK, - VI4_DATA1_B_MARK, - CAN0_RX_B_MARK, - CANFD0_RX_B_MARK, - MSIOF3_SS1_E_MARK, - - /* IPSR1 */ - IRQ2_IMARK, - QCPV_QDE_MARK, - DU_EXODDF_DU_ODDF_DISP_CDE_MARK, - VI4_DATA2_B_MARK, - MSIOF3_SYNC_E_MARK, - PWM3_B_MARK, - IRQ3_IMARK, - QSTVB_QVE_MARK, - DU_DOTCLKOUT1_MARK, - VI4_DATA3_B_MARK, - MSIOF3_SCK_E_MARK, - PWM4_B_MARK, - IRQ4_IMARK, - QSTH_QHS_MARK, - DU_EXHSYNC_DU_HSYNC_MARK, - VI4_DATA4_B_MARK, - MSIOF3_RXD_E_MARK, - PWM5_B_MARK, - IRQ5_IMARK, - QSTB_QHE_MARK, - DU_EXVSYNC_DU_VSYNC_MARK, - VI4_DATA5_B_MARK, - FSCLKST2x_B_MARK, - MSIOF3_TXD_E_MARK, - PWM6_B_MARK, - PWM0_IMARK, - AVB_AVTP_PPS_MARK, - VI4_DATA6_B_MARK, - IECLK_B_MARK, - PWM1_A_IMARK, - HRX3_D_MARK, - VI4_DATA7_B_MARK, - IERX_B_MARK, - PWM2_A_IMARK, - PWMFSW0_MARK, - HTX3_D_MARK, - IETX_B_MARK, - A0_IMARK, - LCDOUT16_MARK, - MSIOF3_SYNC_B_MARK, - VI4_DATA8_MARK, - DU_DB0_MARK, - PWM3_A_MARK, - - /* IPSR2 */ - A1_IMARK, - LCDOUT17_MARK, - MSIOF3_TXD_B_MARK, - VI4_DATA9_MARK, - DU_DB1_MARK, - PWM4_A_MARK, - A2_IMARK, - LCDOUT18_MARK, - MSIOF3_SCK_B_MARK, - VI4_DATA10_MARK, - DU_DB2_MARK, - PWM5_A_MARK, - A3_IMARK, - LCDOUT19_MARK, - MSIOF3_RXD_B_MARK, - VI4_DATA11_MARK, - DU_DB3_MARK, - PWM6_A_MARK, - A4_IMARK, - LCDOUT20_MARK, - MSIOF3_SS1_B_MARK, - VI4_DATA12_MARK, - VI5_DATA12_MARK, - DU_DB4_MARK, - A5_IMARK, - LCDOUT21_MARK, - MSIOF3_SS2_B_MARK, - SCK4_B_MARK, - VI4_DATA13_MARK, - VI5_DATA13_MARK, - DU_DB5_MARK, - A6_IMARK, - LCDOUT22_MARK, - MSIOF2_SS1_A_MARK, - RX4_B_MARK, - VI4_DATA14_MARK, - VI5_DATA14_MARK, - DU_DB6_MARK, - A7_IMARK, - LCDOUT23_MARK, - MSIOF2_SS2_A_MARK, - TX4_B_MARK, - VI4_DATA15_MARK, - V15_DATA15_MARK, - DU_DB7_MARK, - A8_IMARK, - RX3_B_MARK, - MSIOF2_SYNC_A_MARK, - HRX4_B_MARK, - SDA6_A_MARK, - AVB_AVTP_MATCH_B_MARK, - PWM1_B_MARK, - - /* IPSR3 */ - A9_IMARK, - MSIOF2_SCK_A_MARK, - CTS4x_B_MARK, - VI5_VSYNCx_MARK, - A10_IMARK, - MSIOF2_RXD_A_MARK, - RTS4n_TANS_B_MARK, - VI5_HSYNCx_MARK, - A11_IMARK, - TX3_B_MARK, - MSIOF2_TXD_A_MARK, - HTX4_B_MARK, - HSCK4_MARK, - VI5_FIELD_MARK, - SCL6_A_MARK, - AVB_AVTP_CAPTURE_B_MARK, - PWM2_B_MARK, - A12_IMARK, - LCDOUT12_MARK, - MSIOF3_SCK_C_MARK, - HRX4_A_MARK, - VI5_DATA8_MARK, - DU_DG4_MARK, - A13_IMARK, - LCDOUT13_MARK, - MSIOF3_SYNC_C_MARK, - HTX4_A_MARK, - VI5_DATA9_MARK, - DU_DG5_MARK, - A14_IMARK, - LCDOUT14_MARK, - MSIOF3_RXD_C_MARK, - HCTS4x_MARK, - VI5_DATA10_MARK, - DU_DG6_MARK, - A15_IMARK, - LCDOUT15_MARK, - MSIOF3_TXD_C_MARK, - HRTS4x_MARK, - VI5_DATA11_MARK, - DU_DG7_MARK, - A16_IMARK, - LCDOUT8_MARK, - VI4_FIELD_MARK, - DU_DG0_MARK, - - /* IPSR4 */ - A17_IMARK, - LCDOUT9_MARK, - VI4_VSYNCx_MARK, - DU_DG1_MARK, - A18_IMARK, - LCDOUT10_MARK, - VI4_HSYNCx_MARK, - DU_DG2_MARK, - A19_IMARK, - LCDOUT11_MARK, - VI4_CLKENB_MARK, - DU_DG3_MARK, - CS0x_IMARK, - VI5_CLKENB_MARK, - CS1x_A26_IMARK, - VI5_CLK_MARK, - EX_WAIT0_B_MARK, - BSx_IMARK, - QSTVA_QVS_MARK, - MSIOF3_SCK_D_MARK, - SCK3_MARK, - HSCK3_MARK, - CAN1_TX_MARK, - CANFD1_TX_MARK, - IETX_A_MARK, - RDx_IMARK, - MSIOF3_SYNC_D_MARK, - RX3_A_MARK, - HRX3_A_MARK, - CAN0_TX_A_MARK, - CANFD0_TX_A_MARK, - RD_WRx_IMARK, - MSIOF3_RXD_D_MARK, - TX3_A_MARK, - HTX3_A_MARK, - CAN0_RX_A_MARK, - CANFD0_RX_A_MARK, - - /* IPSR5 */ - WE0x_IMARK, - MSIIOF3_TXD_D_MARK, - CTS3x_MARK, - HCTS3x_MARK, - SCL6_B_MARK, - CAN_CLK_MARK, - IECLK_A_MARK, - WE1x_IMARK, - MSIOF3_SS1_D_MARK, - RTS3x_TANS_MARK, - HRTS3x_MARK, - SDA6_B_MARK, - CAN1_RX_MARK, - CANFD1_RX_MARK, - IERX_A_MARK, - EX_WAIT0_A_IMARK, - QCLK_MARK, - VI4_CLK_MARK, - DU_DOTCLKOUT0_MARK, - D0_IMARK, - MSIOF2_SS1_B_MARK, - MSIOF3_SCK_A_MARK, - VI4_DATA16_MARK, - VI5_DATA0_MARK, - D1_IMARK, - MSIOF2_SS2_B_MARK, - MSIOF3_SYNC_A_MARK, - VI4_DATA17_MARK, - VI5_DATA1_MARK, - D2_IMARK, - MSIOF3_RXD_A_MARK, - VI4_DATA18_MARK, - VI5_DATA2_MARK, - D3_IMARK, - MSIOF3_TXD_A_MARK, - VI4_DATA19_MARK, - VI5_DATA3_MARK, - D4_IMARK, - MSIOF2_SCK_B_MARK, - VI4_DATA20_MARK, - VI5_DATA4_MARK, - - /* IPSR6 */ - D5_IMARK, - MSIOF2_SYNC_B_MARK, - VI4_DATA21_MARK, - VI5_DATA5_MARK, - D6_IMARK, - MSIOF2_RXD_B_MARK, - VI4_DATA22_MARK, - VI5_DATA6_MARK, - D7_IMARK, - MSIOF2_TXD_B_MARK, - VI4_DATA23_MARK, - VI5_DATA7_MARK, - D8_IMARK, - LCDOUT0_MARK, - MSIOF2_SCK_D_MARK, - SCK4_C_MARK, - VI4_DATA0_A_MARK, - DU_DR0_MARK, - D9_IMARK, - LCDOUT1_MARK, - MSIOF2_SYNC_D_MARK, - VI4_DATA1_A_MARK, - DU_DR1_MARK, - D10_IMARK, - LCDOUT2_MARK, - MSIOF2_RXD_D_MARK, - HRX3_B_MARK, - VI4_DATA2_A_MARK, - CTS4x_C_MARK, - DU_DR2_MARK, - D11_IMARK, - LCDOUT3_MARK, - MSIOF2_TXD_D_MARK, - HTX3_B_MARK, - VI4_DATA3_A_MARK, - RTS4x_TANS_C_MARK, - DU_DR3_MARK, - D12_IMARK, - LCDOUT4_MARK, - MSIOF2_SS1_D_MARK, - RX4_C_MARK, - VI4_DATA4_A_MARK, - DU_DR4_MARK, - - /* IPSR7 */ - D13_IMARK, - LCDOUT5_MARK, - MSIOF2_SS2_D_MARK, - TX4_C_MARK, - VI4_DATA5_A_MARK, - DU_DR5_MARK, - D14_IMARK, - LCDOUT6_MARK, - MSIOF3_SS1_A_MARK, - HRX3_C_MARK, - VI4_DATA6_A_MARK, - DU_DR6_MARK, - SCL6_C_MARK, - D15_IMARK, - LCDOUT7_MARK, - MSIOF3_SS2_A_MARK, - HTX3_C_MARK, - VI4_DATA7_A_MARK, - DU_DR7_MARK, - SDA6_C_MARK, - FSCLKST_MARK, - SD0_CLK_IMARK, - MSIOF1_SCK_E_MARK, - STP_OPWM_0_B_MARK, - SD0_CMD_IMARK, - MSIOF1_SYNC_E_MARK, - STP_IVCXO27_0_B_MARK, - SD0_DAT0_IMARK, - MSIOF1_RXD_E_MARK, - TS_SCK0_B_MARK, - STP_ISCLK_0_B_MARK, - SD0_DAT1_IMARK, - MSIOF1_TXD_E_MARK, - TS_SPSYNC0_B_MARK, - STP_ISSYNC_0_B_MARK, - - /* IPSR8 */ - SD0_DAT2_IMARK, - MSIOF1_SS1_E_MARK, - TS_SDAT0_B_MARK, - STP_ISD_0_B_MARK, - SD0_DAT3_IMARK, - MSIOF1_SS2_E_MARK, - TS_SDEN0_B_MARK, - STP_ISEN_0_B_MARK, - SD1_CLK_IMARK, - MSIOF1_SCK_G_MARK, - SIM0_CLK_A_MARK, - SD1_CMD_IMARK, - MSIOF1_SYNC_G_MARK, - NFCEx_B_MARK, - SIM0_D_A_MARK, - STP_IVCXO27_1_B_MARK, - SD1_DAT0_IMARK, - SD2_DAT4_MARK, - MSIOF1_RXD_G_MARK, - NFWPx_B_MARK, - TS_SCK1_B_MARK, - STP_ISCLK_1_B_MARK, - SD1_DAT1_IMARK, - SD2_DAT5_MARK, - MSIOF1_TXD_G_MARK, - NFDATA14_B_MARK, - TS_SPSYNC1_B_MARK, - STP_ISSYNC_1_B_MARK, - SD1_DAT2_IMARK, - SD2_DAT6_MARK, - MSIOF1_SS1_G_MARK, - NFDATA15_B_MARK, - TS_SDAT1_B_MARK, - STP_IOD_1_B_MARK, - SD1_DAT3_IMARK, - SD2_DAT7_MARK, - MSIOF1_SS2_G_MARK, - NFRBx_B_MARK, - TS_SDEN1_B_MARK, - STP_ISEN_1_B_MARK, - - /* IPSR9 */ - SD2_CLK_IMARK, - NFDATA8_MARK, - SD2_CMD_IMARK, - NFDATA9_MARK, - SD2_DAT0_IMARK, - NFDATA10_MARK, - SD2_DAT1_IMARK, - NFDATA11_MARK, - SD2_DAT2_IMARK, - NFDATA12_MARK, - SD2_DAT3_IMARK, - NFDATA13_MARK, - SD2_DS_IMARK, - NFALE_MARK, - SATA_DEVSLP_B_MARK, - SD3_CLK_IMARK, - NFWEx_MARK, - - /* IPSR10 */ - SD3_CMD_IMARK, - NFREx_MARK, - SD3_DAT0_IMARK, - NFDATA0_MARK, - SD3_DAT1_IMARK, - NFDATA1_MARK, - SD3_DAT2_IMARK, - NFDATA2_MARK, - SD3_DAT3_IMARK, - NFDATA3_MARK, - SD3_DAT4_IMARK, - SD2_CD_A_MARK, - NFDATA4_MARK, - SD3_DAT5_IMARK, - SD2_WP_A_MARK, - NFDATA5_MARK, - SD3_DAT6_IMARK, - SD3_CD_MARK, - NFDATA6_MARK, - - /* IPSR11 */ - SD3_DAT7_IMARK, - SD3_WP_MARK, - NFDATA7_MARK, - SD3_DS_IMARK, - NFCLE_MARK, - SD0_CD_IMARK, - NFDATA14_A_MARK, - SCL2_B_MARK, - SIM0_RST_A_MARK, - SD0_WP_IMARK, - NFDATA15_A_MARK, - SDA2_B_MARK, - SD1_CD_IMARK, - NFRBx_A_MARK, - SIM0_CLK_B_MARK, - SD1_WP_IMARK, - NFCEx_A_MARK, - SIM0_D_B_MARK, - SCK0_IMARK, - HSCK1_B_MARK, - MSIOF1_SS2_B_MARK, - AUDIO_CLKC_B_MARK, - SDA2_A_MARK, - SIM0_RST_B_MARK, - STP_OPWM_0_C_MARK, - RIF0_CLK_B_MARK, - ADICHS2_MARK, - SCK5_B_MARK, - RX0_IMARK, - HRX1_B_MARK, - TS_SCK0_C_MARK, - STP_ISCLK_0_C_MARK, - RIF0_D0_B_MARK, - - /* IPSR12 */ - TX0_IMARK, - HTX1_B_MARK, - TS_SPSYNC0_C_MARK, - STP_ISSYNC_0_C_MARK, - RIF0_D1_B_MARK, - CTS0x_IMARK, - HCTS1x_B_MARK, - MSIOF1_SYNC_B_MARK, - TS_SPSYNC1_C_MARK, - STP_ISSYNC_1_C_MARK, - RIF1_SYNC_B_MARK, - AUDIO_CLKOUT_C_MARK, - ADICS_SAMP_MARK, - RTS0x_TANS_IMARK, - HRTS1x_B_MARK, - MSIOF1_SS1_B_MARK, - AUDIO_CLKA_B_MARK, - SCL2_A_MARK, - STP_IVCXO27_1_C_MARK, - RIF0_SYNC_B_MARK, - ADICHS1_MARK, - RX1_A_IMARK, - HRX1_A_MARK, - TS_SDAT0_C_MARK, - STP_ISD_0_C_MARK, - RIF1_CLK_C_MARK, - TX1_A_IMARK, - HTX1_A_MARK, - TS_SDEN0_C_MARK, - STP_ISEN_0_C_MARK, - RIF1_D0_C_MARK, - CTS1x_IMARK, - HCTS1x_A_MARK, - MSIOF1_RXD_B_MARK, - TS_SDEN1_C_MARK, - STP_ISEN_1_C_MARK, - RIF1_D0_B_MARK, - ADIDATA_MARK, - RTS1x_TANS_IMARK, - HRTS1x_A_MARK, - MSIOF1_TXD_B_MARK, - TS_SDAT1_C_MARK, - STP_ISD_1_C_MARK, - RIF1_D1_B_MARK, - ADICHS0_MARK, - SCK2_IMARK, - SCIF_CLK_B_MARK, - MSIOF1_SCK_B_MARK, - TS_SCK1_C_MARK, - STP_ISCLK_1_C_MARK, - RIF1_CLK_B_MARK, - ADICLK_MARK, - - /* IPSR13 */ - TX2_A_IMARK, - SD2_CD_B_MARK, - SCL1_A_MARK, - FMCLK_A_MARK, - RIF1_D1_C_MARK, - FSO_CFE_0x_MARK, - RX2_A_IMARK, - SD2_WP_B_MARK, - SDA1_A_MARK, - FMIN_A_MARK, - RIF1_SYNC_C_MARK, - FSO_CFE_1x_MARK, - HSCK0_IMARK, - MSIOF1_SCK_D_MARK, - AUDIO_CLKB_A_MARK, - SSI_SDATA1_B_MARK, - TS_SCK0_D_MARK, - STP_ISCLK_0_D_MARK, - RIF0_CLK_C_MARK, - RX5_B_MARK, - HRX0_IMARK, - MSIOF1_RXD_D_MARK, - SSI_SDATA2_B_MARK, - TS_SDEN0_D_MARK, - STP_ISEN_0_D_MARK, - RIF0_D0_C_MARK, - HTX0_IMARK, - MSIOF1_TXD_D_MARK, - SSI_SDATA9_B_MARK, - TS_SDAT0_D_MARK, - STP_ISD_0_D_MARK, - RIF0_D1_C_MARK, - HCTS0x_IMARK, - RX2_B_MARK, - MSIOF1_SYNC_D_MARK, - SSI_SCK9_A_MARK, - TS_SPSYNC0_D_MARK, - STP_ISSYNC_0_D_MARK, - RIF0_SYNC_C_MARK, - AUDIO_CLKOUT1_A_MARK, - HRTS0x_IMARK, - TX2_B_MARK, - MSIOF1_SS1_D_MARK, - SSI_WS9_A_MARK, - STP_IVCXO27_0_D_MARK, - BPFCLK_A_MARK, - AUDIO_CLKOUT2_A_MARK, - MSIOF0_SYNC_IMARK, - AUDIO_CLKOUT_A_MARK, - TX5_B_MARK, - BPFCLK_D_MARK, - - /* IPSR14 */ - MSIOF0_SS1_IMARK, - RX5_A_MARK, - NFWPx_A_MARK, - AUDIO_CLKA_C_MARK, - SSI_SCK2_A_MARK, - STP_IVCXO27_0_C_MARK, - AUDIO_CLKOUT3_A_MARK, - TCLK1_B_MARK, - MSIOF0_SS2_IMARK, - TX5_A_MARK, - MSIOF1_SS2_D_MARK, - AUDIO_CLKC_A_MARK, - SSI_WS2_A_MARK, - STP_OPWM_0_D_MARK, - AUDIO_CLKOUT_D_MARK, - SPEEDIN_B_MARK, - MLB_CLK_IMARK, - MSIOF1_SCK_F_MARK, - SCL1_B_MARK, - MLB_SIG_IMARK, - RX1_B_MARK, - MSIOF1_SYNC_F_MARK, - SDA1_B_MARK, - MLB_DAT_IMARK, - TX1_B_MARK, - MSIOF1_RXD_F_MARK, - SSI_SCK01239_IMARK, - MSIOF1_TXD_F_MARK, - MOUT0_MARK, - SSI_WS01239_IMARK, - MSIOF1_SS1_F_MARK, - MOUT1_MARK, - SSI_SDATA0_IMARK, - MSIOF1_SS2_F_MARK, - MOUT2_MARK, - - /* IPSR15 */ - SSI_SDATA1_A_IMARK, - MOUT5_MARK, - SSI_SDATA2_A_IMARK, - SSI_SCK1_B_MARK, - MOUT6_MARK, - SSI_SCK34_IMARK, - MSIOF1_SS1_A_MARK, - STP_OPWM_0_A_MARK, - SSI_WS34_IMARK, - HCTS2x_A_MARK, - MSIOF1_SS2_A_MARK, - STP_IVCXO27_0_A_MARK, - SSI_SDATA3_IMARK, - HRTS2x_A_MARK, - MSIOF1_TXD_A_MARK, - TS_SCK0_A_MARK, - STP_ISCLK_0_A_MARK, - RIF0_D1_A_MARK, - RIF2_D0_A_MARK, - SSI_SCK4_IMARK, - HRX2_A_MARK, - MSIOF1_SCK_A_MARK, - TS_SDAT0_A_MARK, - STP_ISD_0_A_MARK, - RIF0_CLK_A_MARK, - RIF2_CLK_A_MARK, - SSI_WS4_IMARK, - HTX2_A_MARK, - MSIOF1_SYNC_A_MARK, - TS_SDEN0_A_MARK, - STP_ISEN_0_A_MARK, - RIF0_SYNC_A_MARK, - RIF2_SYNC_A_MARK, - SSI_SDATA4_IMARK, - HSCK2_A_MARK, - MSIOF1_RXD_A_MARK, - TS_SPSYNC0_A_MARK, - STP_ISSYNC_0_A_MARK, - RIF0_D0_A_MARK, - RIF2_D1_A_MARK, - - /* IPSR16 */ - SSI_SCK6_IMARK, - SIM0_RST_D_MARK, - SSI_WS6_IMARK, - SIM0_D_D_MARK, - SSI_SDATA6_IMARK, - SIM0_CLK_D_MARK, - SATA_DEVSLP_A_MARK, - SSI_SCK78_IMARK, - HRX2_B_MARK, - MSIOF1_SCK_C_MARK, - TS_SCK1_A_MARK, - STP_ISCLK_1_A_MARK, - RIF1_CLK_A_MARK, - RIF3_CLK_A_MARK, - SSI_WS78_IMARK, - HTX2_B_MARK, - MSIOF1_SYNC_C_MARK, - TS_SDAT1_A_MARK, - STP_ISD_1_A_MARK, - RIF1_SYNC_A_MARK, - RIF3_SYNC_A_MARK, - SSI_SDATA7_IMARK, - HCTS2x_B_MARK, - MSIOF1_RXD_C_MARK, - TS_SDEN1_A_MARK, - STP_ISEN_1_A_MARK, - RIF1_D0_A_MARK, - RIF3_D0_A_MARK, - TCLK2_A_MARK, - SSI_SDATA8_IMARK, - HRTS2x_B_MARK, - MSIOF1_TXD_C_MARK, - TS_SPSYNC1_A_MARK, - STP_ISSYNC_1_A_MARK, - RIF1_D1_A_MARK, - RIF3_D1_A_MARK, - SSI_SDATA9_A_IMARK, - HSCK2_B_MARK, - MSIOF1_SS1_C_MARK, - HSCK1_A_MARK, - SSI_WS1_B_MARK, - SCK1_MARK, - STP_IVCXO27_1_A_MARK, - SCK5_A_MARK, - - /* IPSR17 */ - AUDIO_CLKA_A_IMARK, - CC5_OSCOUT_MARK, - AUDIO_CLKB_B_IMARK, - SCIF_CLK_A_MARK, - STP_IVCXO27_1_D_MARK, - REMOCON_A_MARK, - TCLK1_A_MARK, - USB0_PWEN_IMARK, - SIM0_RST_C_MARK, - TS_SCK1_D_MARK, - STP_ISCLK_1_D_MARK, - BPFCLK_B_MARK, - RIF3_CLK_B_MARK, - HSCK2_C_MARK, - USB0_OVC_IMARK, - SIM0_D_C_MARK, - TS_SDAT1_D_MARK, - STP_ISD_1_D_MARK, - RIF3_SYNC_B_MARK, - HRX2_C_MARK, - USB1_PWEN_IMARK, - SIM0_CLK_C_MARK, - SSI_SCK1_A_MARK, - TS_SCK0_E_MARK, - STP_ISCLK_0_E_MARK, - FMCLK_B_MARK, - RIF2_CLK_B_MARK, - SPEEDIN_A_MARK, - HTX2_C_MARK, - USB1_OVC_IMARK, - MSIOF1_SS2_C_MARK, - SSI_WS1_A_MARK, - TS_SDAT0_E_MARK, - STP_ISD_0_E_MARK, - FMIN_B_MARK, - RIF2_SYNC_B_MARK, - REMOCON_B_MARK, - HCTS2x_C_MARK, - USB30_PWEN_IMARK, - AUDIO_CLKOUT_B_MARK, - SSI_SCK2_B_MARK, - TS_SDEN1_D_MARK, - STP_ISEN_1_D_MARK, - STP_OPWM_0_E_MARK, - RIF3_D0_B_MARK, - TCLK2_B_MARK, - TPU0TO0_MARK, - BPFCLK_C_MARK, - HRTS2x_C_MARK, - USB30_OVC_IMARK, - AUDIO_CLKOUT1_B_MARK, - SSI_WS2_B_MARK, - TS_SPSYNC1_D_MARK, - STP_ISSYNC_1_D_MARK, - STP_IVCXO27_0_E_MARK, - RIF3_D1_B_MARK, - FSO_TOEx_MARK, - TPU0TO1_MARK, - - /* IPSR18 */ - USB3_PWEN_IMARK, - AUDIO_CLKOUT2_B_MARK, - SSI_SCK9_B_MARK, - TS_SDEN0_E_MARK, - STP_ISEN_0_E_MARK, - RIF2_D0_B_MARK, - TPU0TO2_MARK, - FMCLK_C_MARK, - FMCLK_D_MARK, - - USB3_OVC_IMARK, - AUDIO_CLKOUT3_B_MARK, - SSI_WS9_B_MARK, - TS_SPSYNC0_E_MARK, - STP_ISSYNC_0_E_MARK, - RIF2_D1_B_MARK, - TPU0TO3_MARK, - FMIN_C_MARK, - FMIN_D_MARK, - - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - - /* GPSR0 */ - PINMUX_DATA(D15_GMARK, GFN_D15), - PINMUX_DATA(D14_GMARK, GFN_D14), - PINMUX_DATA(D13_GMARK, GFN_D13), - PINMUX_DATA(D12_GMARK, GFN_D12), - PINMUX_DATA(D11_GMARK, GFN_D11), - PINMUX_DATA(D10_GMARK, GFN_D10), - PINMUX_DATA(D9_GMARK, GFN_D9), - PINMUX_DATA(D8_GMARK, GFN_D8), - PINMUX_DATA(D7_GMARK, GFN_D7), - PINMUX_DATA(D6_GMARK, GFN_D6), - PINMUX_DATA(D5_GMARK, GFN_D5), - PINMUX_DATA(D4_GMARK, GFN_D4), - PINMUX_DATA(D3_GMARK, GFN_D3), - PINMUX_DATA(D2_GMARK, GFN_D2), - PINMUX_DATA(D1_GMARK, GFN_D1), - PINMUX_DATA(D0_GMARK, GFN_D0), - - /* GPSR1 */ - PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT), - PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A), - PINMUX_DATA(WE1x_GMARK, GFN_WE1x), - PINMUX_DATA(WE0x_GMARK, GFN_WE0x), - PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx), - PINMUX_DATA(RDx_GMARK, GFN_RDx), - PINMUX_DATA(BSx_GMARK, GFN_BSx), - PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26), - PINMUX_DATA(CS0x_GMARK, GFN_CS0x), - PINMUX_DATA(A19_GMARK, GFN_A19), - PINMUX_DATA(A18_GMARK, GFN_A18), - PINMUX_DATA(A17_GMARK, GFN_A17), - PINMUX_DATA(A16_GMARK, GFN_A16), - PINMUX_DATA(A15_GMARK, GFN_A15), - PINMUX_DATA(A14_GMARK, GFN_A14), - PINMUX_DATA(A13_GMARK, GFN_A13), - PINMUX_DATA(A12_GMARK, GFN_A12), - PINMUX_DATA(A11_GMARK, GFN_A11), - PINMUX_DATA(A10_GMARK, GFN_A10), - PINMUX_DATA(A9_GMARK, GFN_A9), - PINMUX_DATA(A8_GMARK, GFN_A8), - PINMUX_DATA(A7_GMARK, GFN_A7), - PINMUX_DATA(A6_GMARK, GFN_A6), - PINMUX_DATA(A5_GMARK, GFN_A5), - PINMUX_DATA(A4_GMARK, GFN_A4), - PINMUX_DATA(A3_GMARK, GFN_A3), - PINMUX_DATA(A2_GMARK, GFN_A2), - PINMUX_DATA(A1_GMARK, GFN_A1), - PINMUX_DATA(A0_GMARK, GFN_A0), - - /* GPSR2 */ - PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A), - PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A), - PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK), - PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT), - PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC), - PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC), - PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A), - PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A), - PINMUX_DATA(PWM0_GMARK, GFN_PWM0), - PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5), - PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4), - PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3), - PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2), - PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1), - PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), - - /* GPSR3 */ - PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP), - PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD), - PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP), - PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD), - PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3), - PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2), - PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1), - PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0), - PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD), - PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK), - PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3), - PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2), - PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1), - PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0), - PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD), - PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK), - - /* GPSR4 */ - PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS), - PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7), - PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6), - PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5), - PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4), - PINMUX_DATA(SD3_DAT3_GMARK, GFN_SD3_DAT3), - PINMUX_DATA(SD3_DAT2_GMARK, GFN_SD3_DAT2), - PINMUX_DATA(SD3_DAT1_GMARK, GFN_SD3_DAT1), - PINMUX_DATA(SD3_DAT0_GMARK, GFN_SD3_DAT0), - PINMUX_DATA(SD3_CMD_GMARK, GFN_SD3_CMD), - PINMUX_DATA(SD3_CLK_GMARK, GFN_SD3_CLK), - PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS), - PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3), - PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2), - PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1), - PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0), - PINMUX_DATA(SD2_CMD_GMARK, GFN_SD2_CMD), - PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK), - - /* GPSR5 */ - PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT), - PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG), - PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK), - PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD), - PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2), - PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD), - PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1), - PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC), - PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK), - PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x), - PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x), - PINMUX_DATA(HTX0_GMARK, GFN_HTX0), - PINMUX_DATA(HRX0_GMARK, GFN_HRX0), - PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0), - PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A), - PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A), - PINMUX_DATA(SCK2_GMARK, GFN_SCK2), - PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS), - PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x), - PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A), - PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A), - PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS), - PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x), - PINMUX_DATA(TX0_GMARK, GFN_TX0), - PINMUX_DATA(RX0_GMARK, GFN_RX0), - PINMUX_DATA(SCK0_GMARK, GFN_SCK0), - - /* GPSR6 */ - PINMUX_DATA(USB3_OVC_GMARK, GFN_USB3_OVC), - PINMUX_DATA(USB3_PWEN_GMARK, GFN_USB3_PWEN), - PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC), - PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN), - PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC), - PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN), - PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC), - PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN), - PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B), - PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A), - PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A), - PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8), - PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7), - PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78), - PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78), - PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6), - PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6), - PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6), - PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5), - PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5), - PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5), - PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4), - PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4), - PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4), - PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3), - PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34), - PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34), - PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A), - PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A), - PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0), - PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239), - PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239), - - /* GPSR7 */ - PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC), - PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC), - PINMUX_DATA(AVS2_MARK, FN_AVS2), - PINMUX_DATA(AVS1_MARK, FN_AVS1), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - PINMUX_GPIO_GP_ALL(), - /* GPSR0 */ - GPIO_GFN(D15), - GPIO_GFN(D14), - GPIO_GFN(D13), - GPIO_GFN(D12), - GPIO_GFN(D11), - GPIO_GFN(D10), - GPIO_GFN(D9), - GPIO_GFN(D8), - GPIO_GFN(D7), - GPIO_GFN(D6), - GPIO_GFN(D5), - GPIO_GFN(D4), - GPIO_GFN(D3), - GPIO_GFN(D2), - GPIO_GFN(D1), - GPIO_GFN(D0), - /* GPSR1 */ - GPIO_GFN(CLKOUT), - GPIO_GFN(EX_WAIT0_A), - GPIO_GFN(WE1x), - GPIO_GFN(WE0x), - GPIO_GFN(RD_WRx), - GPIO_GFN(RDx), - GPIO_GFN(BSx), - GPIO_GFN(CS1x_A26), - GPIO_GFN(CS0x), - GPIO_GFN(A19), - GPIO_GFN(A18), - GPIO_GFN(A17), - GPIO_GFN(A16), - GPIO_GFN(A15), - GPIO_GFN(A14), - GPIO_GFN(A13), - GPIO_GFN(A12), - GPIO_GFN(A11), - GPIO_GFN(A10), - GPIO_GFN(A9), - GPIO_GFN(A8), - GPIO_GFN(A7), - GPIO_GFN(A6), - GPIO_GFN(A5), - GPIO_GFN(A4), - GPIO_GFN(A3), - GPIO_GFN(A2), - GPIO_GFN(A1), - GPIO_GFN(A0), - - /* GPSR2 */ - GPIO_GFN(AVB_AVTP_CAPTURE_A), - GPIO_GFN(AVB_AVTP_MATCH_A), - GPIO_GFN(AVB_LINK), - GPIO_GFN(AVB_PHY_INT), - GPIO_GFN(AVB_MAGIC), - GPIO_GFN(AVB_MDC), - GPIO_GFN(PWM2_A), - GPIO_GFN(PWM1_A), - GPIO_GFN(PWM0), - GPIO_GFN(IRQ5), - GPIO_GFN(IRQ4), - GPIO_GFN(IRQ3), - GPIO_GFN(IRQ2), - GPIO_GFN(IRQ1), - GPIO_GFN(IRQ0), - - /* GPSR3 */ - GPIO_GFN(SD1_WP), - GPIO_GFN(SD1_CD), - GPIO_GFN(SD0_WP), - GPIO_GFN(SD0_CD), - GPIO_GFN(SD1_DAT3), - GPIO_GFN(SD1_DAT2), - GPIO_GFN(SD1_DAT1), - GPIO_GFN(SD1_DAT0), - GPIO_GFN(SD1_CMD), - GPIO_GFN(SD1_CLK), - GPIO_GFN(SD0_DAT3), - GPIO_GFN(SD0_DAT2), - GPIO_GFN(SD0_DAT1), - GPIO_GFN(SD0_DAT0), - GPIO_GFN(SD0_CMD), - GPIO_GFN(SD0_CLK), - - /* GPSR4 */ - GPIO_GFN(SD3_DS), - GPIO_GFN(SD3_DAT7), - GPIO_GFN(SD3_DAT6), - GPIO_GFN(SD3_DAT5), - GPIO_GFN(SD3_DAT4), - GPIO_GFN(SD3_DAT3), - GPIO_GFN(SD3_DAT2), - GPIO_GFN(SD3_DAT1), - GPIO_GFN(SD3_DAT0), - GPIO_GFN(SD3_CMD), - GPIO_GFN(SD3_CLK), - GPIO_GFN(SD2_DS), - GPIO_GFN(SD2_DAT3), - GPIO_GFN(SD2_DAT2), - GPIO_GFN(SD2_DAT1), - GPIO_GFN(SD2_DAT0), - GPIO_GFN(SD2_CMD), - GPIO_GFN(SD2_CLK), - - /* GPSR5 */ - GPIO_GFN(MLB_DAT), - GPIO_GFN(MLB_SIG), - GPIO_GFN(MLB_CLK), - GPIO_FN(MSIOF0_RXD), - GPIO_GFN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - GPIO_GFN(MSIOF0_SS1), - GPIO_GFN(MSIOF0_SYNC), - GPIO_FN(MSIOF0_SCK), - GPIO_GFN(HRTS0x), - GPIO_GFN(HCTS0x), - GPIO_GFN(HTX0), - GPIO_GFN(HRX0), - GPIO_GFN(HSCK0), - GPIO_GFN(RX2_A), - GPIO_GFN(TX2_A), - GPIO_GFN(SCK2), - GPIO_GFN(RTS1x_TANS), - GPIO_GFN(CTS1x), - GPIO_GFN(TX1_A), - GPIO_GFN(RX1_A), - GPIO_GFN(RTS0x_TANS), - GPIO_GFN(CTS0x), - GPIO_GFN(TX0), - GPIO_GFN(RX0), - GPIO_GFN(SCK0), - - /* GPSR6 */ - GPIO_GFN(USB3_OVC), - GPIO_GFN(USB3_PWEN), - GPIO_GFN(USB30_OVC), - GPIO_GFN(USB30_PWEN), - GPIO_GFN(USB1_OVC), - GPIO_GFN(USB1_PWEN), - GPIO_GFN(USB0_OVC), - GPIO_GFN(USB0_PWEN), - GPIO_GFN(AUDIO_CLKB_B), - GPIO_GFN(AUDIO_CLKA_A), - GPIO_GFN(SSI_SDATA9_A), - GPIO_GFN(SSI_SDATA8), - GPIO_GFN(SSI_SDATA7), - GPIO_GFN(SSI_WS78), - GPIO_GFN(SSI_SCK78), - GPIO_GFN(SSI_SDATA6), - GPIO_GFN(SSI_WS6), - GPIO_GFN(SSI_SCK6), - GPIO_FN(SSI_SDATA5), - GPIO_FN(SSI_WS5), - GPIO_FN(SSI_SCK5), - GPIO_GFN(SSI_SDATA4), - GPIO_GFN(SSI_WS4), - GPIO_GFN(SSI_SCK4), - GPIO_GFN(SSI_SDATA3), - GPIO_GFN(SSI_WS34), - GPIO_GFN(SSI_SCK34), - GPIO_GFN(SSI_SDATA2_A), - GPIO_GFN(SSI_SDATA1_A), - GPIO_GFN(SSI_SDATA0), - GPIO_GFN(SSI_WS01239), - GPIO_GFN(SSI_SCK01239), - - /* GPSR7 */ - GPIO_FN(HDMI1_CEC), - GPIO_FN(HDMI0_CEC), - GPIO_FN(AVS2), - GPIO_FN(AVS1), - - /* IPSR0 */ - GPIO_IFN(AVB_MDC), - GPIO_FN(MSIOF2_SS2_C), - GPIO_IFN(AVB_MAGIC), - GPIO_FN(MSIOF2_SS1_C), - GPIO_FN(SCK4_A), - GPIO_IFN(AVB_PHY_INT), - GPIO_FN(MSIOF2_SYNC_C), - GPIO_FN(RX4_A), - GPIO_IFN(AVB_LINK), - GPIO_FN(MSIOF2_SCK_C), - GPIO_FN(TX4_A), - GPIO_IFN(AVB_AVTP_MATCH_A), - GPIO_FN(MSIOF2_RXD_C), - GPIO_FN(CTS4x_A), - GPIO_FN(FSCLKST2x_A), - GPIO_IFN(AVB_AVTP_CAPTURE_A), - GPIO_FN(MSIOF2_TXD_C), - GPIO_FN(RTS4x_TANS_A), - GPIO_IFN(IRQ0), - GPIO_FN(QPOLB), - GPIO_FN(DU_CDE), - GPIO_FN(VI4_DATA0_B), - GPIO_FN(CAN0_TX_B), - GPIO_FN(CANFD0_TX_B), - GPIO_FN(MSIOF3_SS2_E), - GPIO_IFN(IRQ1), - GPIO_FN(QPOLA), - GPIO_FN(DU_DISP), - GPIO_FN(VI4_DATA1_B), - GPIO_FN(CAN0_RX_B), - GPIO_FN(CANFD0_RX_B), - GPIO_FN(MSIOF3_SS1_E), - - /* IPSR1 */ - GPIO_IFN(IRQ2), - GPIO_FN(QCPV_QDE), - GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE), - GPIO_FN(VI4_DATA2_B), - GPIO_FN(MSIOF3_SYNC_E), - GPIO_FN(PWM3_B), - GPIO_IFN(IRQ3), - GPIO_FN(QSTVB_QVE), - GPIO_FN(DU_DOTCLKOUT1), - GPIO_FN(VI4_DATA3_B), - GPIO_FN(MSIOF3_SCK_E), - GPIO_FN(PWM4_B), - GPIO_IFN(IRQ4), - GPIO_FN(QSTH_QHS), - GPIO_FN(DU_EXHSYNC_DU_HSYNC), - GPIO_FN(VI4_DATA4_B), - GPIO_FN(MSIOF3_RXD_E), - GPIO_FN(PWM5_B), - GPIO_IFN(IRQ5), - GPIO_FN(QSTB_QHE), - GPIO_FN(DU_EXVSYNC_DU_VSYNC), - GPIO_FN(VI4_DATA5_B), - GPIO_FN(FSCLKST2x_B), - GPIO_FN(MSIOF3_TXD_E), - GPIO_FN(PWM6_B), - GPIO_IFN(PWM0), - GPIO_FN(AVB_AVTP_PPS), - GPIO_FN(VI4_DATA6_B), - GPIO_FN(IECLK_B), - GPIO_IFN(PWM1_A), - GPIO_FN(HRX3_D), - GPIO_FN(VI4_DATA7_B), - GPIO_FN(IERX_B), - GPIO_IFN(PWM2_A), - GPIO_FN(HTX3_D), - GPIO_FN(IETX_B), - GPIO_IFN(A0), - GPIO_FN(LCDOUT16), - GPIO_FN(MSIOF3_SYNC_B), - GPIO_FN(VI4_DATA8), - GPIO_FN(DU_DB0), - GPIO_FN(PWM3_A), - - /* IPSR2 */ - GPIO_IFN(A1), - GPIO_FN(LCDOUT17), - GPIO_FN(MSIOF3_TXD_B), - GPIO_FN(VI4_DATA9), - GPIO_FN(DU_DB1), - GPIO_FN(PWM4_A), - GPIO_IFN(A2), - GPIO_FN(LCDOUT18), - GPIO_FN(MSIOF3_SCK_B), - GPIO_FN(VI4_DATA10), - GPIO_FN(DU_DB2), - GPIO_FN(PWM5_A), - GPIO_IFN(A3), - GPIO_FN(LCDOUT19), - GPIO_FN(MSIOF3_RXD_B), - GPIO_FN(VI4_DATA11), - GPIO_FN(DU_DB3), - GPIO_FN(PWM6_A), - GPIO_IFN(A4), - GPIO_FN(LCDOUT20), - GPIO_FN(MSIOF3_SS1_B), - GPIO_FN(VI4_DATA12), - GPIO_FN(VI5_DATA12), - GPIO_FN(DU_DB4), - GPIO_IFN(A5), - GPIO_FN(LCDOUT21), - GPIO_FN(MSIOF3_SS2_B), - GPIO_FN(SCK4_B), - GPIO_FN(VI4_DATA13), - GPIO_FN(VI5_DATA13), - GPIO_FN(DU_DB5), - GPIO_IFN(A6), - GPIO_FN(LCDOUT22), - GPIO_FN(MSIOF2_SS1_A), - GPIO_FN(RX4_B), - GPIO_FN(VI4_DATA14), - GPIO_FN(VI5_DATA14), - GPIO_FN(DU_DB6), - GPIO_IFN(A7), - GPIO_FN(LCDOUT23), - GPIO_FN(MSIOF2_SS2_A), - GPIO_FN(TX4_B), - GPIO_FN(VI4_DATA15), - GPIO_FN(V15_DATA15), - GPIO_FN(DU_DB7), - GPIO_IFN(A8), - GPIO_FN(RX3_B), - GPIO_FN(MSIOF2_SYNC_A), - GPIO_FN(HRX4_B), - GPIO_FN(SDA6_A), - GPIO_FN(AVB_AVTP_MATCH_B), - GPIO_FN(PWM1_B), - - /* IPSR3 */ - GPIO_IFN(A9), - GPIO_FN(MSIOF2_SCK_A), - GPIO_FN(CTS4x_B), - GPIO_FN(VI5_VSYNCx), - GPIO_IFN(A10), - GPIO_FN(MSIOF2_RXD_A), - GPIO_FN(RTS4n_TANS_B), - GPIO_FN(VI5_HSYNCx), - GPIO_IFN(A11), - GPIO_FN(TX3_B), - GPIO_FN(MSIOF2_TXD_A), - GPIO_FN(HTX4_B), - GPIO_FN(HSCK4), - GPIO_FN(VI5_FIELD), - GPIO_FN(SCL6_A), - GPIO_FN(AVB_AVTP_CAPTURE_B), - GPIO_FN(PWM2_B), - GPIO_IFN(A12), - GPIO_FN(LCDOUT12), - GPIO_FN(MSIOF3_SCK_C), - GPIO_FN(HRX4_A), - GPIO_FN(VI5_DATA8), - GPIO_FN(DU_DG4), - GPIO_IFN(A13), - GPIO_FN(LCDOUT13), - GPIO_FN(MSIOF3_SYNC_C), - GPIO_FN(HTX4_A), - GPIO_FN(VI5_DATA9), - GPIO_FN(DU_DG5), - GPIO_IFN(A14), - GPIO_FN(LCDOUT14), - GPIO_FN(MSIOF3_RXD_C), - GPIO_FN(HCTS4x), - GPIO_FN(VI5_DATA10), - GPIO_FN(DU_DG6), - GPIO_IFN(A15), - GPIO_FN(LCDOUT15), - GPIO_FN(MSIOF3_TXD_C), - GPIO_FN(HRTS4x), - GPIO_FN(VI5_DATA11), - GPIO_FN(DU_DG7), - GPIO_IFN(A16), - GPIO_FN(LCDOUT8), - GPIO_FN(VI4_FIELD), - GPIO_FN(DU_DG0), - - /* IPSR4 */ - GPIO_IFN(A17), - GPIO_FN(LCDOUT9), - GPIO_FN(VI4_VSYNCx), - GPIO_FN(DU_DG1), - GPIO_IFN(A18), - GPIO_FN(LCDOUT10), - GPIO_FN(VI4_HSYNCx), - GPIO_FN(DU_DG2), - GPIO_IFN(A19), - GPIO_FN(LCDOUT11), - GPIO_FN(VI4_CLKENB), - GPIO_FN(DU_DG3), - GPIO_IFN(CS0x), - GPIO_FN(VI5_CLKENB), - GPIO_IFN(CS1x_A26), - GPIO_FN(VI5_CLK), - GPIO_FN(EX_WAIT0_B), - GPIO_IFN(BSx), - GPIO_FN(QSTVA_QVS), - GPIO_FN(MSIOF3_SCK_D), - GPIO_FN(SCK3), - GPIO_FN(HSCK3), - GPIO_FN(CAN1_TX), - GPIO_FN(CANFD1_TX), - GPIO_FN(IETX_A), - GPIO_IFN(RDx), - GPIO_FN(MSIOF3_SYNC_D), - GPIO_FN(RX3_A), - GPIO_FN(HRX3_A), - GPIO_FN(CAN0_TX_A), - GPIO_FN(CANFD0_TX_A), - GPIO_IFN(RD_WRx), - GPIO_FN(MSIOF3_RXD_D), - GPIO_FN(TX3_A), - GPIO_FN(HTX3_A), - GPIO_FN(CAN0_RX_A), - GPIO_FN(CANFD0_RX_A), - - /* IPSR5 */ - GPIO_IFN(WE0x), - GPIO_FN(MSIIOF3_TXD_D), - GPIO_FN(CTS3x), - GPIO_FN(HCTS3x), - GPIO_FN(SCL6_B), - GPIO_FN(CAN_CLK), - GPIO_FN(IECLK_A), - GPIO_IFN(WE1x), - GPIO_FN(MSIOF3_SS1_D), - GPIO_FN(RTS3x_TANS), - GPIO_FN(HRTS3x), - GPIO_FN(SDA6_B), - GPIO_FN(CAN1_RX), - GPIO_FN(CANFD1_RX), - GPIO_FN(IERX_A), - GPIO_IFN(EX_WAIT0_A), - GPIO_FN(QCLK), - GPIO_FN(VI4_CLK), - GPIO_FN(DU_DOTCLKOUT0), - GPIO_IFN(D0), - GPIO_FN(MSIOF2_SS1_B), - GPIO_FN(MSIOF3_SCK_A), - GPIO_FN(VI4_DATA16), - GPIO_FN(VI5_DATA0), - GPIO_IFN(D1), - GPIO_FN(MSIOF2_SS2_B), - GPIO_FN(MSIOF3_SYNC_A), - GPIO_FN(VI4_DATA17), - GPIO_FN(VI5_DATA1), - GPIO_IFN(D2), - GPIO_FN(MSIOF3_RXD_A), - GPIO_FN(VI4_DATA18), - GPIO_FN(VI5_DATA2), - GPIO_IFN(D3), - GPIO_FN(MSIOF3_TXD_A), - GPIO_FN(VI4_DATA19), - GPIO_FN(VI5_DATA3), - GPIO_IFN(D4), - GPIO_FN(MSIOF2_SCK_B), - GPIO_FN(VI4_DATA20), - GPIO_FN(VI5_DATA4), - - /* IPSR6 */ - GPIO_IFN(D5), - GPIO_FN(MSIOF2_SYNC_B), - GPIO_FN(VI4_DATA21), - GPIO_FN(VI5_DATA5), - GPIO_IFN(D6), - GPIO_FN(MSIOF2_RXD_B), - GPIO_FN(VI4_DATA22), - GPIO_FN(VI5_DATA6), - GPIO_IFN(D7), - GPIO_FN(MSIOF2_TXD_B), - GPIO_FN(VI4_DATA23), - GPIO_FN(VI5_DATA7), - GPIO_IFN(D8), - GPIO_FN(LCDOUT0), - GPIO_FN(MSIOF2_SCK_D), - GPIO_FN(SCK4_C), - GPIO_FN(VI4_DATA0_A), - GPIO_FN(DU_DR0), - GPIO_IFN(D9), - GPIO_FN(LCDOUT1), - GPIO_FN(MSIOF2_SYNC_D), - GPIO_FN(VI4_DATA1_A), - GPIO_FN(DU_DR1), - GPIO_IFN(D10), - GPIO_FN(LCDOUT2), - GPIO_FN(MSIOF2_RXD_D), - GPIO_FN(HRX3_B), - GPIO_FN(VI4_DATA2_A), - GPIO_FN(CTS4x_C), - GPIO_FN(DU_DR2), - GPIO_IFN(D11), - GPIO_FN(LCDOUT3), - GPIO_FN(MSIOF2_TXD_D), - GPIO_FN(HTX3_B), - GPIO_FN(VI4_DATA3_A), - GPIO_FN(RTS4x_TANS_C), - GPIO_FN(DU_DR3), - GPIO_IFN(D12), - GPIO_FN(LCDOUT4), - GPIO_FN(MSIOF2_SS1_D), - GPIO_FN(RX4_C), - GPIO_FN(VI4_DATA4_A), - GPIO_FN(DU_DR4), - - /* IPSR7 */ - GPIO_IFN(D13), - GPIO_FN(LCDOUT5), - GPIO_FN(MSIOF2_SS2_D), - GPIO_FN(TX4_C), - GPIO_FN(VI4_DATA5_A), - GPIO_FN(DU_DR5), - GPIO_IFN(D14), - GPIO_FN(LCDOUT6), - GPIO_FN(MSIOF3_SS1_A), - GPIO_FN(HRX3_C), - GPIO_FN(VI4_DATA6_A), - GPIO_FN(DU_DR6), - GPIO_FN(SCL6_C), - GPIO_IFN(D15), - GPIO_FN(LCDOUT7), - GPIO_FN(MSIOF3_SS2_A), - GPIO_FN(HTX3_C), - GPIO_FN(VI4_DATA7_A), - GPIO_FN(DU_DR7), - GPIO_FN(SDA6_C), - GPIO_FN(FSCLKST), - GPIO_IFN(SD0_CLK), - GPIO_FN(MSIOF1_SCK_E), - GPIO_FN(STP_OPWM_0_B), - GPIO_IFN(SD0_CMD), - GPIO_FN(MSIOF1_SYNC_E), - GPIO_FN(STP_IVCXO27_0_B), - GPIO_IFN(SD0_DAT0), - GPIO_FN(MSIOF1_RXD_E), - GPIO_FN(TS_SCK0_B), - GPIO_FN(STP_ISCLK_0_B), - GPIO_IFN(SD0_DAT1), - GPIO_FN(MSIOF1_TXD_E), - GPIO_FN(TS_SPSYNC0_B), - GPIO_FN(STP_ISSYNC_0_B), - - /* IPSR8 */ - GPIO_IFN(SD0_DAT2), - GPIO_FN(MSIOF1_SS1_E), - GPIO_FN(TS_SDAT0_B), - GPIO_FN(STP_ISD_0_B), - GPIO_IFN(SD0_DAT3), - GPIO_FN(MSIOF1_SS2_E), - GPIO_FN(TS_SDEN0_B), - GPIO_FN(STP_ISEN_0_B), - GPIO_IFN(SD1_CLK), - GPIO_FN(MSIOF1_SCK_G), - GPIO_FN(SIM0_CLK_A), - GPIO_IFN(SD1_CMD), - GPIO_FN(MSIOF1_SYNC_G), - GPIO_FN(NFCEx_B), - GPIO_FN(SIM0_D_A), - GPIO_FN(STP_IVCXO27_1_B), - GPIO_IFN(SD1_DAT0), - GPIO_FN(SD2_DAT4), - GPIO_FN(MSIOF1_RXD_G), - GPIO_FN(NFWPx_B), - GPIO_FN(TS_SCK1_B), - GPIO_FN(STP_ISCLK_1_B), - GPIO_IFN(SD1_DAT1), - GPIO_FN(SD2_DAT5), - GPIO_FN(MSIOF1_TXD_G), - GPIO_FN(NFDATA14_B), - GPIO_FN(TS_SPSYNC1_B), - GPIO_FN(STP_ISSYNC_1_B), - GPIO_IFN(SD1_DAT2), - GPIO_FN(SD2_DAT6), - GPIO_FN(MSIOF1_SS1_G), - GPIO_FN(NFDATA15_B), - GPIO_FN(TS_SDAT1_B), - GPIO_FN(STP_IOD_1_B), - GPIO_IFN(SD1_DAT3), - GPIO_FN(SD2_DAT7), - GPIO_FN(MSIOF1_SS2_G), - GPIO_FN(NFRBx_B), - GPIO_FN(TS_SDEN1_B), - GPIO_FN(STP_ISEN_1_B), - - /* IPSR9 */ - GPIO_IFN(SD2_CLK), - GPIO_FN(NFDATA8), - GPIO_IFN(SD2_CMD), - GPIO_FN(NFDATA9), - GPIO_IFN(SD2_DAT0), - GPIO_FN(NFDATA10), - GPIO_IFN(SD2_DAT1), - GPIO_FN(NFDATA11), - GPIO_IFN(SD2_DAT2), - GPIO_FN(NFDATA12), - GPIO_IFN(SD2_DAT3), - GPIO_FN(NFDATA13), - GPIO_IFN(SD2_DS), - GPIO_FN(NFALE), - GPIO_FN(SATA_DEVSLP_B), - GPIO_IFN(SD3_CLK), - GPIO_FN(NFWEx), - - /* IPSR10 */ - GPIO_IFN(SD3_CMD), - GPIO_FN(NFREx), - GPIO_IFN(SD3_DAT0), - GPIO_FN(NFDATA0), - GPIO_IFN(SD3_DAT1), - GPIO_FN(NFDATA1), - GPIO_IFN(SD3_DAT2), - GPIO_FN(NFDATA2), - GPIO_IFN(SD3_DAT3), - GPIO_FN(NFDATA3), - GPIO_IFN(SD3_DAT4), - GPIO_FN(SD2_CD_A), - GPIO_FN(NFDATA4), - GPIO_IFN(SD3_DAT5), - GPIO_FN(SD2_WP_A), - GPIO_FN(NFDATA5), - GPIO_IFN(SD3_DAT6), - GPIO_FN(SD3_CD), - GPIO_FN(NFDATA6), - - /* IPSR11 */ - GPIO_IFN(SD3_DAT7), - GPIO_FN(SD3_WP), - GPIO_FN(NFDATA7), - GPIO_IFN(SD3_DS), - GPIO_FN(NFCLE), - GPIO_IFN(SD0_CD), - GPIO_FN(NFDATA14_A), - GPIO_FN(SCL2_B), - GPIO_FN(SIM0_RST_A), - GPIO_IFN(SD0_WP), - GPIO_FN(NFDATA15_A), - GPIO_FN(SDA2_B), - GPIO_IFN(SD1_CD), - GPIO_FN(NFRBx_A), - GPIO_FN(SIM0_CLK_B), - GPIO_IFN(SD1_WP), - GPIO_FN(NFCEx_A), - GPIO_FN(SIM0_D_B), - GPIO_IFN(SCK0), - GPIO_FN(HSCK1_B), - GPIO_FN(MSIOF1_SS2_B), - GPIO_FN(AUDIO_CLKC_B), - GPIO_FN(SDA2_A), - GPIO_FN(SIM0_RST_B), - GPIO_FN(STP_OPWM_0_C), - GPIO_FN(RIF0_CLK_B), - GPIO_FN(ADICHS2), - GPIO_FN(SCK5_B), - GPIO_IFN(RX0), - GPIO_FN(HRX1_B), - GPIO_FN(TS_SCK0_C), - GPIO_FN(STP_ISCLK_0_C), - GPIO_FN(RIF0_D0_B), - - /* IPSR12 */ - GPIO_IFN(TX0), - GPIO_FN(HTX1_B), - GPIO_FN(TS_SPSYNC0_C), - GPIO_FN(STP_ISSYNC_0_C), - GPIO_FN(RIF0_D1_B), - GPIO_IFN(CTS0x), - GPIO_FN(HCTS1x_B), - GPIO_FN(MSIOF1_SYNC_B), - GPIO_FN(TS_SPSYNC1_C), - GPIO_FN(STP_ISSYNC_1_C), - GPIO_FN(RIF1_SYNC_B), - GPIO_FN(AUDIO_CLKOUT_C), - GPIO_FN(ADICS_SAMP), - GPIO_IFN(RTS0x_TANS), - GPIO_FN(HRTS1x_B), - GPIO_FN(MSIOF1_SS1_B), - GPIO_FN(AUDIO_CLKA_B), - GPIO_FN(SCL2_A), - GPIO_FN(STP_IVCXO27_1_C), - GPIO_FN(RIF0_SYNC_B), - GPIO_FN(ADICHS1), - GPIO_IFN(RX1_A), - GPIO_FN(HRX1_A), - GPIO_FN(TS_SDAT0_C), - GPIO_FN(STP_ISD_0_C), - GPIO_FN(RIF1_CLK_C), - GPIO_IFN(TX1_A), - GPIO_FN(HTX1_A), - GPIO_FN(TS_SDEN0_C), - GPIO_FN(STP_ISEN_0_C), - GPIO_FN(RIF1_D0_C), - GPIO_IFN(CTS1x), - GPIO_FN(HCTS1x_A), - GPIO_FN(MSIOF1_RXD_B), - GPIO_FN(TS_SDEN1_C), - GPIO_FN(STP_ISEN_1_C), - GPIO_FN(RIF1_D0_B), - GPIO_FN(ADIDATA), - GPIO_IFN(RTS1x_TANS), - GPIO_FN(HRTS1x_A), - GPIO_FN(MSIOF1_TXD_B), - GPIO_FN(TS_SDAT1_C), - GPIO_FN(STP_ISD_1_C), - GPIO_FN(RIF1_D1_B), - GPIO_FN(ADICHS0), - GPIO_IFN(SCK2), - GPIO_FN(SCIF_CLK_B), - GPIO_FN(MSIOF1_SCK_B), - GPIO_FN(TS_SCK1_C), - GPIO_FN(STP_ISCLK_1_C), - GPIO_FN(RIF1_CLK_B), - GPIO_FN(ADICLK), - - /* IPSR13 */ - GPIO_IFN(TX2_A), - GPIO_FN(SD2_CD_B), - GPIO_FN(SCL1_A), - GPIO_FN(FMCLK_A), - GPIO_FN(RIF1_D1_C), - GPIO_FN(FSO_CFE_0x), - GPIO_IFN(RX2_A), - GPIO_FN(SD2_WP_B), - GPIO_FN(SDA1_A), - GPIO_FN(FMIN_A), - GPIO_FN(RIF1_SYNC_C), - GPIO_FN(FSO_CFE_1x), - GPIO_IFN(HSCK0), - GPIO_FN(MSIOF1_SCK_D), - GPIO_FN(AUDIO_CLKB_A), - GPIO_FN(SSI_SDATA1_B), - GPIO_FN(TS_SCK0_D), - GPIO_FN(STP_ISCLK_0_D), - GPIO_FN(RIF0_CLK_C), - GPIO_FN(RX5_B), - GPIO_IFN(HRX0), - GPIO_FN(MSIOF1_RXD_D), - GPIO_FN(SSI_SDATA2_B), - GPIO_FN(TS_SDEN0_D), - GPIO_FN(STP_ISEN_0_D), - GPIO_FN(RIF0_D0_C), - GPIO_IFN(HTX0), - GPIO_FN(MSIOF1_TXD_D), - GPIO_FN(SSI_SDATA9_B), - GPIO_FN(TS_SDAT0_D), - GPIO_FN(STP_ISD_0_D), - GPIO_FN(RIF0_D1_C), - GPIO_IFN(HCTS0x), - GPIO_FN(RX2_B), - GPIO_FN(MSIOF1_SYNC_D), - GPIO_FN(SSI_SCK9_A), - GPIO_FN(TS_SPSYNC0_D), - GPIO_FN(STP_ISSYNC_0_D), - GPIO_FN(RIF0_SYNC_C), - GPIO_FN(AUDIO_CLKOUT1_A), - GPIO_IFN(HRTS0x), - GPIO_FN(TX2_B), - GPIO_FN(MSIOF1_SS1_D), - GPIO_FN(SSI_WS9_A), - GPIO_FN(STP_IVCXO27_0_D), - GPIO_FN(BPFCLK_A), - GPIO_FN(AUDIO_CLKOUT2_A), - GPIO_IFN(MSIOF0_SYNC), - GPIO_FN(AUDIO_CLKOUT_A), - GPIO_FN(TX5_B), - GPIO_FN(BPFCLK_D), - - /* IPSR14 */ - GPIO_IFN(MSIOF0_SS1), - GPIO_FN(RX5_A), - GPIO_FN(NFWPx_A), - GPIO_FN(AUDIO_CLKA_C), - GPIO_FN(SSI_SCK2_A), - GPIO_FN(STP_IVCXO27_0_C), - GPIO_FN(AUDIO_CLKOUT3_A), - GPIO_FN(TCLK1_B), - GPIO_IFN(MSIOF0_SS2), - GPIO_FN(TX5_A), - GPIO_FN(MSIOF1_SS2_D), - GPIO_FN(AUDIO_CLKC_A), - GPIO_FN(SSI_WS2_A), - GPIO_FN(STP_OPWM_0_D), - GPIO_FN(AUDIO_CLKOUT_D), - GPIO_FN(SPEEDIN_B), - GPIO_IFN(MLB_CLK), - GPIO_FN(MSIOF1_SCK_F), - GPIO_FN(SCL1_B), - GPIO_IFN(MLB_SIG), - GPIO_FN(RX1_B), - GPIO_FN(MSIOF1_SYNC_F), - GPIO_FN(SDA1_B), - GPIO_IFN(MLB_DAT), - GPIO_FN(TX1_B), - GPIO_FN(MSIOF1_RXD_F), - GPIO_IFN(SSI_SCK01239), - GPIO_FN(MSIOF1_TXD_F), - GPIO_FN(MOUT0), - GPIO_IFN(SSI_WS01239), - GPIO_FN(MSIOF1_SS1_F), - GPIO_FN(MOUT1), - GPIO_IFN(SSI_SDATA0), - GPIO_FN(MSIOF1_SS2_F), - GPIO_FN(MOUT2), - - /* IPSR15 */ - GPIO_IFN(SSI_SDATA1_A), - GPIO_FN(MOUT5), - GPIO_IFN(SSI_SDATA2_A), - GPIO_FN(SSI_SCK1_B), - GPIO_FN(MOUT6), - GPIO_IFN(SSI_SCK34), - GPIO_FN(MSIOF1_SS1_A), - GPIO_FN(STP_OPWM_0_A), - GPIO_IFN(SSI_WS34), - GPIO_FN(HCTS2x_A), - GPIO_FN(MSIOF1_SS2_A), - GPIO_FN(STP_IVCXO27_0_A), - GPIO_IFN(SSI_SDATA3), - GPIO_FN(HRTS2x_A), - GPIO_FN(MSIOF1_TXD_A), - GPIO_FN(TS_SCK0_A), - GPIO_FN(STP_ISCLK_0_A), - GPIO_FN(RIF0_D1_A), - GPIO_FN(RIF2_D0_A), - GPIO_IFN(SSI_SCK4), - GPIO_FN(HRX2_A), - GPIO_FN(MSIOF1_SCK_A), - GPIO_FN(TS_SDAT0_A), - GPIO_FN(STP_ISD_0_A), - GPIO_FN(RIF0_CLK_A), - GPIO_FN(RIF2_CLK_A), - GPIO_IFN(SSI_WS4), - GPIO_FN(HTX2_A), - GPIO_FN(MSIOF1_SYNC_A), - GPIO_FN(TS_SDEN0_A), - GPIO_FN(STP_ISEN_0_A), - GPIO_FN(RIF0_SYNC_A), - GPIO_FN(RIF2_SYNC_A), - GPIO_IFN(SSI_SDATA4), - GPIO_FN(HSCK2_A), - GPIO_FN(MSIOF1_RXD_A), - GPIO_FN(TS_SPSYNC0_A), - GPIO_FN(STP_ISSYNC_0_A), - GPIO_FN(RIF0_D0_A), - GPIO_FN(RIF2_D1_A), - - /* IPSR16 */ - GPIO_IFN(SSI_SCK6), - GPIO_FN(SIM0_RST_D), - GPIO_IFN(SSI_WS6), - GPIO_FN(SIM0_D_D), - GPIO_IFN(SSI_SDATA6), - GPIO_FN(SIM0_CLK_D), - GPIO_FN(SATA_DEVSLP_A), - GPIO_IFN(SSI_SCK78), - GPIO_FN(HRX2_B), - GPIO_FN(MSIOF1_SCK_C), - GPIO_FN(TS_SCK1_A), - GPIO_FN(STP_ISCLK_1_A), - GPIO_FN(RIF1_CLK_A), - GPIO_FN(RIF3_CLK_A), - GPIO_IFN(SSI_WS78), - GPIO_FN(HTX2_B), - GPIO_FN(MSIOF1_SYNC_C), - GPIO_FN(TS_SDAT1_A), - GPIO_FN(STP_ISD_1_A), - GPIO_FN(RIF1_SYNC_A), - GPIO_FN(RIF3_SYNC_A), - GPIO_IFN(SSI_SDATA7), - GPIO_FN(HCTS2x_B), - GPIO_FN(MSIOF1_RXD_C), - GPIO_FN(TS_SDEN1_A), - GPIO_FN(STP_ISEN_1_A), - GPIO_FN(RIF1_D0_A), - GPIO_FN(RIF3_D0_A), - GPIO_FN(TCLK2_A), - GPIO_IFN(SSI_SDATA8), - GPIO_FN(HRTS2x_B), - GPIO_FN(MSIOF1_TXD_C), - GPIO_FN(TS_SPSYNC1_A), - GPIO_FN(STP_ISSYNC_1_A), - GPIO_FN(RIF1_D1_A), - GPIO_FN(RIF3_D1_A), - GPIO_IFN(SSI_SDATA9_A), - GPIO_FN(HSCK2_B), - GPIO_FN(MSIOF1_SS1_C), - GPIO_FN(HSCK1_A), - GPIO_FN(SSI_WS1_B), - GPIO_FN(SCK1), - GPIO_FN(STP_IVCXO27_1_A), - GPIO_FN(SCK5_A), - - /* IPSR17 */ - GPIO_IFN(AUDIO_CLKA_A), - GPIO_FN(CC5_OSCOUT), - GPIO_IFN(AUDIO_CLKB_B), - GPIO_FN(SCIF_CLK_A), - GPIO_FN(STP_IVCXO27_1_D), - GPIO_FN(REMOCON_A), - GPIO_FN(TCLK1_A), - GPIO_IFN(USB0_PWEN), - GPIO_FN(SIM0_RST_C), - GPIO_FN(TS_SCK1_D), - GPIO_FN(STP_ISCLK_1_D), - GPIO_FN(BPFCLK_B), - GPIO_FN(RIF3_CLK_B), - GPIO_FN(HSCK2_C), - GPIO_IFN(USB0_OVC), - GPIO_FN(SIM0_D_C), - GPIO_FN(TS_SDAT1_D), - GPIO_FN(STP_ISD_1_D), - GPIO_FN(RIF3_SYNC_B), - GPIO_FN(HRX2_C), - GPIO_IFN(USB1_PWEN), - GPIO_FN(SIM0_CLK_C), - GPIO_FN(SSI_SCK1_A), - GPIO_FN(TS_SCK0_E), - GPIO_FN(STP_ISCLK_0_E), - GPIO_FN(FMCLK_B), - GPIO_FN(RIF2_CLK_B), - GPIO_FN(SPEEDIN_A), - GPIO_FN(HTX2_C), - GPIO_IFN(USB1_OVC), - GPIO_FN(MSIOF1_SS2_C), - GPIO_FN(SSI_WS1_A), - GPIO_FN(TS_SDAT0_E), - GPIO_FN(STP_ISD_0_E), - GPIO_FN(FMIN_B), - GPIO_FN(RIF2_SYNC_B), - GPIO_FN(REMOCON_B), - GPIO_FN(HCTS2x_C), - GPIO_IFN(USB30_PWEN), - GPIO_FN(AUDIO_CLKOUT_B), - GPIO_FN(SSI_SCK2_B), - GPIO_FN(TS_SDEN1_D), - GPIO_FN(STP_ISEN_1_D), - GPIO_FN(STP_OPWM_0_E), - GPIO_FN(RIF3_D0_B), - GPIO_FN(TCLK2_B), - GPIO_FN(TPU0TO0), - GPIO_FN(BPFCLK_C), - GPIO_FN(HRTS2x_C), - GPIO_IFN(USB30_OVC), - GPIO_FN(AUDIO_CLKOUT1_B), - GPIO_FN(SSI_WS2_B), - GPIO_FN(TS_SPSYNC1_D), - GPIO_FN(STP_ISSYNC_1_D), - GPIO_FN(STP_IVCXO27_0_E), - GPIO_FN(RIF3_D1_B), - GPIO_FN(FSO_TOEx), - GPIO_FN(TPU0TO1), - - /* IPSR18 */ - GPIO_IFN(USB3_PWEN), - GPIO_FN(AUDIO_CLKOUT2_B), - GPIO_FN(SSI_SCK9_B), - GPIO_FN(TS_SDEN0_E), - GPIO_FN(STP_ISEN_0_E), - GPIO_FN(RIF2_D0_B), - GPIO_FN(TPU0TO2), - GPIO_FN(FMCLK_C), - GPIO_FN(FMCLK_D), - - GPIO_IFN(USB3_OVC), - GPIO_FN(AUDIO_CLKOUT3_B), - GPIO_FN(SSI_WS9_B), - GPIO_FN(TS_SPSYNC0_E), - GPIO_FN(STP_ISSYNC_0_E), - GPIO_FN(RIF2_D1_B), - GPIO_FN(TPU0TO3), - GPIO_FN(FMIN_C), - GPIO_FN(FMIN_D), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - /* GPSR0(0xE6060100) md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0000FFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_FN, GFN_D15, - GP_0_14_FN, GFN_D14, - GP_0_13_FN, GFN_D13, - GP_0_12_FN, GFN_D12, - GP_0_11_FN, GFN_D11, - GP_0_10_FN, GFN_D10, - GP_0_9_FN, GFN_D9, - GP_0_8_FN, GFN_D8, - GP_0_7_FN, GFN_D7, - GP_0_6_FN, GFN_D6, - GP_0_5_FN, GFN_D5, - GP_0_4_FN, GFN_D4, - GP_0_3_FN, GFN_D3, - GP_0_2_FN, GFN_D2, - GP_0_1_FN, GFN_D1, - GP_0_0_FN, GFN_D0 } - }, - /* GPSR1(0xE6060104) is md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0EFFFFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_FN, GFN_CLKOUT, - GP_1_27_FN, GFN_EX_WAIT0_A, - GP_1_26_FN, GFN_WE1x, - GP_1_25_FN, GFN_WE0x, - GP_1_24_FN, GFN_RD_WRx, - GP_1_23_FN, GFN_RDx, - GP_1_22_FN, GFN_BSx, - GP_1_21_FN, GFN_CS1x_A26, - GP_1_20_FN, GFN_CS0x, - GP_1_19_FN, GFN_A19, - GP_1_18_FN, GFN_A18, - GP_1_17_FN, GFN_A17, - GP_1_16_FN, GFN_A16, - GP_1_15_FN, GFN_A15, - GP_1_14_FN, GFN_A14, - GP_1_13_FN, GFN_A13, - GP_1_12_FN, GFN_A12, - GP_1_11_FN, GFN_A11, - GP_1_10_FN, GFN_A10, - GP_1_9_FN, GFN_A9, - GP_1_8_FN, GFN_A8, - GP_1_7_FN, GFN_A7, - GP_1_6_FN, GFN_A6, - GP_1_5_FN, GFN_A5, - GP_1_4_FN, GFN_A4, - GP_1_3_FN, GFN_A3, - GP_1_2_FN, GFN_A2, - GP_1_1_FN, GFN_A1, - GP_1_0_FN, GFN_A0 } - }, - /* GPSR2(0xE6060108) is md[3:1] controls */ - /* md[3:1] .. 0 : 0x000003C0 */ - /* .. other : 0x00000200 */ - { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A, - GP_2_13_FN, GFN_AVB_AVTP_MATCH_A, - GP_2_12_FN, GFN_AVB_LINK, - GP_2_11_FN, GFN_AVB_PHY_INT, - GP_2_10_FN, GFN_AVB_MAGIC, - GP_2_9_FN, GFN_AVB_MDC, - GP_2_8_FN, GFN_PWM2_A, - GP_2_7_FN, GFN_PWM1_A, - GP_2_6_FN, GFN_PWM0, - GP_2_5_FN, GFN_IRQ5, - GP_2_4_FN, GFN_IRQ4, - GP_2_3_FN, GFN_IRQ3, - GP_2_2_FN, GFN_IRQ2, - GP_2_1_FN, GFN_IRQ1, - GP_2_0_FN, GFN_IRQ0 } - }, - - /* GPSR3 */ - { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_FN, GFN_SD1_WP, - GP_3_14_FN, GFN_SD1_CD, - GP_3_13_FN, GFN_SD0_WP, - GP_3_12_FN, GFN_SD0_CD, - GP_3_11_FN, GFN_SD1_DAT3, - GP_3_10_FN, GFN_SD1_DAT2, - GP_3_9_FN, GFN_SD1_DAT1, - GP_3_8_FN, GFN_SD1_DAT0, - GP_3_7_FN, GFN_SD1_CMD, - GP_3_6_FN, GFN_SD1_CLK, - GP_3_5_FN, GFN_SD0_DAT3, - GP_3_4_FN, GFN_SD0_DAT2, - GP_3_3_FN, GFN_SD0_DAT1, - GP_3_2_FN, GFN_SD0_DAT0, - GP_3_1_FN, GFN_SD0_CMD, - GP_3_0_FN, GFN_SD0_CLK } - }, - /* GPSR4 */ - { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_FN, GFN_SD3_DS, - GP_4_16_FN, GFN_SD3_DAT7, - - GP_4_15_FN, GFN_SD3_DAT6, - GP_4_14_FN, GFN_SD3_DAT5, - GP_4_13_FN, GFN_SD3_DAT4, - GP_4_12_FN, GFN_SD3_DAT3, - GP_4_11_FN, GFN_SD3_DAT2, - GP_4_10_FN, GFN_SD3_DAT1, - GP_4_9_FN, GFN_SD3_DAT0, - GP_4_8_FN, GFN_SD3_CMD, - GP_4_7_FN, GFN_SD3_CLK, - GP_4_6_FN, GFN_SD2_DS, - GP_4_5_FN, GFN_SD2_DAT3, - GP_4_4_FN, GFN_SD2_DAT2, - GP_4_3_FN, GFN_SD2_DAT1, - GP_4_2_FN, GFN_SD2_DAT0, - GP_4_1_FN, GFN_SD2_CMD, - GP_4_0_FN, GFN_SD2_CLK } - }, - /* GPSR5 */ - { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_FN, GFN_MLB_DAT, - GP_5_24_FN, GFN_MLB_SIG, - GP_5_23_FN, GFN_MLB_CLK, - GP_5_22_FN, FN_MSIOF0_RXD, - GP_5_21_FN, GFN_MSIOF0_SS2, - GP_5_20_FN, FN_MSIOF0_TXD, - GP_5_19_FN, GFN_MSIOF0_SS1, - GP_5_18_FN, GFN_MSIOF0_SYNC, - GP_5_17_FN, FN_MSIOF0_SCK, - GP_5_16_FN, GFN_HRTS0x, - GP_5_15_FN, GFN_HCTS0x, - GP_5_14_FN, GFN_HTX0, - GP_5_13_FN, GFN_HRX0, - GP_5_12_FN, GFN_HSCK0, - GP_5_11_FN, GFN_RX2_A, - GP_5_10_FN, GFN_TX2_A, - GP_5_9_FN, GFN_SCK2, - GP_5_8_FN, GFN_RTS1x_TANS, - GP_5_7_FN, GFN_CTS1x, - GP_5_6_FN, GFN_TX1_A, - GP_5_5_FN, GFN_RX1_A, - GP_5_4_FN, GFN_RTS0x_TANS, - GP_5_3_FN, GFN_CTS0x, - GP_5_2_FN, GFN_TX0, - GP_5_1_FN, GFN_RX0, - GP_5_0_FN, GFN_SCK0 } - }, - /* GPSR6 */ - { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) { - GP_6_31_FN, GFN_USB3_OVC, - GP_6_30_FN, GFN_USB3_PWEN, - GP_6_29_FN, GFN_USB30_OVC, - GP_6_28_FN, GFN_USB30_PWEN, - GP_6_27_FN, GFN_USB1_OVC, - GP_6_26_FN, GFN_USB1_PWEN, - GP_6_25_FN, GFN_USB0_OVC, - GP_6_24_FN, GFN_USB0_PWEN, - GP_6_23_FN, GFN_AUDIO_CLKB_B, - GP_6_22_FN, GFN_AUDIO_CLKA_A, - GP_6_21_FN, GFN_SSI_SDATA9_A, - GP_6_20_FN, GFN_SSI_SDATA8, - GP_6_19_FN, GFN_SSI_SDATA7, - GP_6_18_FN, GFN_SSI_WS78, - GP_6_17_FN, GFN_SSI_SCK78, - GP_6_16_FN, GFN_SSI_SDATA6, - GP_6_15_FN, GFN_SSI_WS6, - GP_6_14_FN, GFN_SSI_SCK6, - GP_6_13_FN, FN_SSI_SDATA5, - GP_6_12_FN, FN_SSI_WS5, - GP_6_11_FN, FN_SSI_SCK5, - GP_6_10_FN, GFN_SSI_SDATA4, - GP_6_9_FN, GFN_SSI_WS4, - GP_6_8_FN, GFN_SSI_SCK4, - GP_6_7_FN, GFN_SSI_SDATA3, - GP_6_6_FN, GFN_SSI_WS34, - GP_6_5_FN, GFN_SSI_SCK34, - GP_6_4_FN, GFN_SSI_SDATA2_A, - GP_6_3_FN, GFN_SSI_SDATA1_A, - GP_6_2_FN, GFN_SSI_SDATA0, - GP_6_1_FN, GFN_SSI_WS01239, - GP_6_0_FN, GFN_SSI_SCK01239 } - }, - /* GPSR7 */ - { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_7_3_FN, FN_HDMI1_CEC, - GP_7_2_FN, FN_HDMI0_CEC, - GP_7_1_FN, FN_AVS2, - GP_7_0_FN, FN_AVS1 } - }, - { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR0_31_28 [4] */ - IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP, - FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, FN_MSIOF3_SS1_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_27_24 [4] */ - IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE, - FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, FN_MSIOF3_SS2_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_23_20 [4] */ - IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_19_16 [4] */ - IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A, - 0, FN_FSCLKST2x_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_15_12 [4] */ - IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_11_8 [4] */ - IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_7_4 [4] */ - IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_3_0 [4] */ - IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR1_31_28 [4] */ - IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0, - FN_VI4_DATA8, 0, FN_DU_DB0, 0, - 0, FN_PWM3_A, 0, 0, - 0, 0, 0, 0, - /* IPSR1_27_24 [4] */ - IFN_PWM2_A, 0, 0, FN_HTX3_D, - 0, 0, 0, 0, - 0, FN_IETX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_23_20 [4] */ - IFN_PWM1_A, 0, 0, FN_HRX3_D, - FN_VI4_DATA7_B, 0, 0, 0, - 0, FN_IERX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_19_16 [4] */ - IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0, - FN_VI4_DATA6_B, 0, 0, 0, - 0, FN_IECLK_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_15_12 [4] */ - IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, FN_FSCLKST2x_B, 0, FN_MSIOF3_TXD_E, - 0, FN_PWM6_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_11_8 [4] */ - IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E, - 0, FN_PWM5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_7_4 [4] */ - IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E, - 0, FN_PWM4_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_3_0 [4] */ - IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E, - 0, FN_PWM3_B, 0, 0, - 0, 0, 0, 0 - } - }, - { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR2_31_28 [4] */ - IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B, - 0, 0, 0, FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR2_27_24 [4] */ - IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B, - FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_23_20 [4] */ - IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B, - FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_19_16 [4] */ - IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B, - FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_15_12 [4] */ - IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0, - FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_11_8 [4] */ - IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0, - FN_VI4_DATA11, 0, FN_DU_DB3, 0, - 0, FN_PWM6_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_7_4 [4] */ - IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0, - FN_VI4_DATA10, 0, FN_DU_DB2, 0, - 0, FN_PWM5_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_3_0 [4] */ - IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0, - FN_VI4_DATA9, 0, FN_DU_DB1, 0, - 0, FN_PWM4_A, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR3_31_28 [4] */ - IFN_A16, FN_LCDOUT8, 0, 0, - FN_VI4_FIELD, 0, FN_DU_DG0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_27_24 [4] */ - IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0, - FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_23_20 [4] */ - IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0, - FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_19_16 [4] */ - IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0, - FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_15_12 [4] */ - IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0, - FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_11_8 [4] */ - IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, - FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, 0, 0, - 0, 0, 0, 0, - /* IPSR3_7_4 [4] */ - IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B, - 0, FN_VI5_HSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_3_0 [4] */ - IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B, - 0, FN_VI5_VSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR4_31_28 [4] */ - IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A, - FN_HTX3_A, 0, 0, 0, - FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_27_24 [4] */ - IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A, - FN_HRX3_A, 0, 0, 0, - FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_23_20 [4] */ - IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3, - FN_HSCK3, 0, 0, 0, - FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0, - 0, 0, 0, 0, - /* IPSR4_19_16 [4] */ - IFN_CS1x_A26, 0, 0, 0, - 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_15_12 [4] */ - IFN_CS0x, 0, 0, 0, - 0, FN_VI5_CLKENB, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_11_8 [4] */ - IFN_A19, FN_LCDOUT11, 0, 0, - FN_VI4_CLKENB, 0, FN_DU_DG3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_7_4 [4] */ - IFN_A18, FN_LCDOUT10, 0, 0, - FN_VI4_HSYNCx, 0, FN_DU_DG2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_3_0 [4] */ - IFN_A17, FN_LCDOUT9, 0, 0, - FN_VI4_VSYNCx, 0, FN_DU_DG1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR5_31_28 [4] */ - IFN_D4, FN_MSIOF2_SCK_B, 0, 0, - FN_VI4_DATA20, FN_VI5_DATA4, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_27_24 [4] */ - IFN_D3, 0, FN_MSIOF3_TXD_A, 0, - FN_VI4_DATA19, FN_VI5_DATA3, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_23_20 [4] */ - IFN_D2, 0, FN_MSIOF3_RXD_A, 0, - FN_VI4_DATA18, FN_VI5_DATA2, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_19_16 [4] */ - IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0, - FN_VI4_DATA17, FN_VI5_DATA1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_15_12 [4] */ - IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0, - FN_VI4_DATA16, FN_VI5_DATA0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_11_8 [4] */ - IFN_EX_WAIT0_A, FN_QCLK, 0, 0, - FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_7_4 [4] */ - IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS, - FN_HRTS3x, 0, 0, FN_SDA6_B, - FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0, - 0, 0, 0, 0, - /* IPSR5_3_0 [4] */ - IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x, - FN_HCTS3x, 0, 0, FN_SCL6_B, - FN_CAN_CLK, 0, FN_IECLK_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR6_31_28 [4] */ - IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C, - FN_VI4_DATA4_A, 0, FN_DU_DR4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_27_24 [4] */ - IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B, - FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_23_20 [4] */ - IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B, - FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_19_16 [4] */ - IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0, - FN_VI4_DATA1_A, 0, FN_DU_DR1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_15_12 [4] */ - IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C, - FN_VI4_DATA0_A, 0, FN_DU_DR0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_11_8 [4] */ - IFN_D7, FN_MSIOF2_TXD_B, 0, 0, - FN_VI4_DATA23, FN_VI5_DATA7, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_7_4 [4] */ - IFN_D6, FN_MSIOF2_RXD_B, 0, 0, - FN_VI4_DATA22, FN_VI5_DATA6, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_3_0 [4] */ - IFN_D5, FN_MSIOF2_SYNC_B, 0, 0, - FN_VI4_DATA21, FN_VI5_DATA5, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR7_31_28 [4] */ - IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0, - 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_27_24 [4] */ - IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0, - 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_23_20 [4] */ - IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0, - 0, 0, FN_STP_IVCXO27_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_19_16 [4] */ - IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0, - 0, 0, FN_STP_OPWM_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_15_12 [4] */ - FN_FSCLKST, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_11_8 [4] */ - IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C, - FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_7_4 [4] */ - IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C, - FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_3_0 [4] */ - IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C, - FN_VI4_DATA5_A, 0, FN_DU_DR5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR8_31_28 [4] */ - IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, FN_NFRBx_B, - 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_27_24 [4] */ - IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, FN_NFDATA15_B, - 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_23_20 [4] */ - IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, FN_NFDATA14_B, - 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_19_16 [4] */ - IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, FN_NFWPx_B, - 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_15_12 [4] */ - IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, FN_NFCEx_B, - 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_11_8 [4] */ - IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0, - 0, FN_SIM0_CLK_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_7_4 [4] */ - IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0, - 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_3_0 [4] */ - IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0, - 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR9_31_28 [4] */ - IFN_SD3_CLK, 0, FN_NFWEx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_27_24 [4] */ - IFN_SD2_DS, 0, FN_NFALE, 0, - 0, 0, 0, 0, - FN_SATA_DEVSLP_B, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_23_20 [4] */ - IFN_SD2_DAT3, 0, FN_NFDATA13, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_19_16 [4] */ - IFN_SD2_DAT2, 0, FN_NFDATA12, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_15_12 [4] */ - IFN_SD2_DAT1, 0, FN_NFDATA11, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_11_8 [4] */ - IFN_SD2_DAT0, 0, FN_NFDATA10, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_7_4 [4] */ - IFN_SD2_CMD, 0, FN_NFDATA9, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_3_0 [4] */ - IFN_SD2_CLK, 0, FN_NFDATA8, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR10_31_28 [4] */ - IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_27_24 [4] */ - IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_23_20 [4] */ - IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_19_16 [4] */ - IFN_SD3_DAT3, 0, FN_NFDATA3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_15_12 [4] */ - IFN_SD3_DAT2, 0, FN_NFDATA2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_11_8 [4] */ - IFN_SD3_DAT1, 0, FN_NFDATA1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_7_4 [4] */ - IFN_SD3_DAT0, 0, FN_NFDATA0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_3_0 [4] */ - IFN_SD3_CMD, 0, FN_NFREx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR11_31_28 [4] */ - IFN_RX0, FN_HRX1_B, 0, 0, - 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_27_24 [4] */ - IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, - FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B, - FN_ADICHS2, FN_SCK5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR11_23_20 [4] */ - IFN_SD1_WP, 0, FN_NFCEx_A, 0, - 0, FN_SIM0_D_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_19_16 [4] */ - IFN_SD1_CD, 0, FN_NFRBx_A, 0, - 0, FN_SIM0_CLK_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_15_12 [4] */ - IFN_SD0_WP, 0, FN_NFDATA15_A, 0, - FN_SDA2_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_11_8 [4] */ - IFN_SD0_CD, 0, FN_NFDATA14_A, 0, - FN_SCL2_B, FN_SIM0_RST_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_7_4 [4] */ - IFN_SD3_DS, 0, FN_NFCLE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_3_0 [4] */ - IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR12_31_28 [4] */ - IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, - 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B, - 0, FN_ADICLK, 0, 0, - 0, 0, 0, 0, - /* IPSR12_27_24 [4] */ - IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0, - 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B, - 0, FN_ADICHS0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_23_20 [4] */ - IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0, - 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, - 0, FN_ADIDATA, 0, 0, - 0, 0, 0, 0, - /* IPSR12_19_16 [4] */ - IFN_TX1_A, FN_HTX1_A, 0, 0, - 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_15_12 [4] */ - IFN_RX1_A, FN_HRX1_A, 0, 0, - 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_11_8 [4] */ - IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, - FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, - 0, FN_ADICHS1, 0, 0, - 0, 0, 0, 0, - /* IPSR12_7_4 [4] */ - IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0, - 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0, - 0, 0, 0, 0, - /* IPSR12_3_0 [4] */ - IFN_TX0, FN_HTX1_B, 0, 0, - 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR13_31_28 [4] */ - IFN_MSIOF0_SYNC, 0, 0, 0, - 0, 0, 0, 0, - FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0, - 0, FN_BPFCLK_D, 0, 0, - /* IPSR13_27_24 [4] */ - IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0, - FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_23_20 [4] */ - IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0, - FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_19_16 [4] */ - IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0, - FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_15_12 [4] */ - IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0, - FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_11_8 [4] */ - IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, - 0, 0, FN_RX5_B, 0, - 0, 0, 0, 0, - /* IPSR13_7_4 [4] */ - IFN_RX2_A, 0, 0, FN_SD2_WP_B, - FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C, - 0, FN_FSO_CFE_1x, 0, 0, - 0, 0, 0, 0, - /* IPSR13_3_0 [4] */ - IFN_TX2_A, 0, 0, FN_SD2_CD_B, - FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C, - 0, FN_FSO_CFE_0x, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR14_31_28 [4] */ - IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0, - 0, 0, 0, FN_MOUT2, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_27_24 [4] */ - IFN_SSI_WS01239, 0, FN_MSIOF1_SS1_F, 0, - 0, 0, 0, 0, FN_MOUT1, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_23_20 [4] */ - IFN_SSI_SCK01239, 0, FN_MSIOF1_TXD_F, 0, - 0, 0, 0, FN_MOUT0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_19_16 [4] */ - IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_15_12 [4] */ - IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0, - FN_SDA1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_11_8 [4] */ - IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0, - FN_SCL1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_7_4 [4] */ - IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0, - FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0, - 0, 0, 0, 0, - /* IPSR14_3_0 [4] */ - IFN_MSIOF0_SS1, FN_RX5_A, FN_NFWPx_A, FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0, - FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR15_31_28 [4] */ - IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0, - 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, - FN_RIF2_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_27_24 [4] */ - IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0, - 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_23_20 [4] */ - IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0, - 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A, - FN_RIF2_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_19_16 [4] */ - IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0, - 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A, - FN_RIF2_D0_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_15_12 [4] */ - IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0, - 0, 0, FN_STP_IVCXO27_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_11_8 [4] */ - IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0, - 0, 0, FN_STP_OPWM_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_7_4 [4] */ - IFN_SSI_SDATA2_A, 0, 0, 0, - FN_SSI_SCK1_B, 0, 0, FN_MOUT6, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_3_0 [4] */ - IFN_SSI_SDATA1_A, 0, 0, 0, - 0, 0, 0, FN_MOUT5, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR16_31_28 [4] */ - IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, - FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_27_24 [4] */ - IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0, - 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, - FN_RIF3_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_23_20 [4] */ - IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0, - 0, FN_TS_SDEN1_A, FN_STP_ISEN_1_A, FN_RIF1_D0_A, - FN_RIF3_D0_A, 0, FN_TCLK2_A, 0, - 0, 0, 0, 0, - /* IPSR16_19_16 [4] */ - IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0, - 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_15_12 [4] */ - IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0, - 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, - FN_RIF3_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_11_8 [4] */ - IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D, - 0, 0, 0, 0, - FN_SATA_DEVSLP_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_7_4 [4] */ - IFN_SSI_WS6, 0, 0, FN_SIM0_D_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_3_0 [4] */ - IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR17_31_28 [4] */ - IFN_USB30_OVC, 0, 0, FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, 0, FN_FSO_TOEx, FN_TPU0TO1, - 0, 0, 0, 0, - /* IPSR17_27_24 [4] */ - IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, - FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0, - FN_BPFCLK_C, FN_HRTS2x_C, 0, 0, - /* IPSR17_23_20 [4] */ - IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0, - FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B, - FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0, - 0, FN_HCTS2x_C, 0, 0, - /* IPSR17_19_16 [4] */ - IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C, - FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B, - FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0, - 0, FN_HTX2_C, 0, 0, - /* IPSR17_15_12 [4] */ - IFN_USB0_OVC, 0, 0, FN_SIM0_D_C, - 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0, - FN_RIF3_SYNC_B, 0, 0, 0, - 0, FN_HRX2_C, 0, 0, - /* IPSR17_11_8 [4] */ - IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C, - 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, - FN_RIF3_CLK_B, 0, 0, 0, - 0, FN_HSCK2_C, 0, 0, - /* IPSR17_7_4 [4] */ - IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0, - 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, - 0, 0, FN_TCLK1_A, 0, - 0, 0, 0, 0, - /* IPSR17_3_0 [4] */ - IFN_AUDIO_CLKA_A, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, FN_CC5_OSCOUT, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 4, 4) { - /* reserved [31..24] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [23..16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* IPSR18_7_4 [4] */ - IFN_USB3_OVC, 0, 0, FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0, - FN_RIF2_D1_B, 0, 0, FN_TPU0TO3, - FN_FMIN_C, FN_FMIN_D, 0, 0, - /* IPSR18_3_0 [4] */ - IFN_USB3_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, - FN_RIF2_D0_B, 0, 0, FN_TPU0TO2, - FN_FMCLK_C, FN_FMCLK_D, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 1, 1, 1) { - /* MOD_SEL0 */ - /* sel_msiof3[3](0,1,2,3,4) */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, 0, - 0, 0, - /* sel_msiof2[2](0,1,2,3) */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* sel_msiof1[3](0,1,2,3,4,5,6) */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, 0, - /* sel_lbsc[1](0,1) */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* sel_iebus[1](0,1) */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* sel_i2c2[1](0,1) */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* sel_i2c1[1](0,1) */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* sel_hscif4[1](0,1) */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* sel_hscif3[2](0,1,2,3) */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* sel_hscif1[1](0,1) */ - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* reserved[1] */ - 0, 0, - /* sel_hscif2[2](0,1,2) */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, 0, - /* sel_etheravb[1](0,1) */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* sel_drif3[1](0,1) */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* sel_drif2[1](0,1) */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* sel_drif1[2](0,1,2) */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, 0, - /* sel_drif0[2](0,1,2) */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, 0, - /* sel_canfd0[1](0,1) */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* sel_adg_a[2](0,1,2) */ - FN_SEL_ADG_A_0, FN_SEL_ADG_A_1, - FN_SEL_ADG_A_2, 0, - /* reserved[3]*/ - 0, 0, - 0, 0, - 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32, - 2, 3, 1, 2, - 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* sel_tsif1[2](0,1,2,3) */ - FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, - /* sel_tsif0[3](0,1,2,3,4) */ - FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, 0, - 0, 0, - /* sel_timer_tmu1[1](0,1) */ - FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1, - /* sel_ssp1_1[2](0,1,2,3) */ - FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3, - /* sel_ssp1_0[3](0,1,2,3,4) */ - FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, 0, - 0, 0, - /* sel_ssi1[1](0,1) */ - FN_SEL_SSI_0, FN_SEL_SSI_1, - /* sel_speed_pulse_if[1](0,1) */ - FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, - /* sel_simcard[2](0,1,2,3) */ - FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, - /* sel_sdhi2[1](0,1) */ - FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, - /* sel_scif4[2](0,1,2) */ - FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, 0, - /* sel_scif3[1](0,1) */ - FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, - /* sel_scif2[1](0,1) */ - FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, - /* sel_scif1[1](0,1) */ - FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, - /* sel_scif[1](0,1) */ - FN_SEL_SCIF_0, FN_SEL_SCIF_1, - /* sel_remocon[1](0,1) */ - FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, - /* reserved[8..7] */ - 0, 0, - 0, 0, - /* sel_rcan0[1](0,1) */ - FN_SEL_RCAN_0, FN_SEL_RCAN_1, - /* sel_pwm6[1](0,1) */ - FN_SEL_PWM6_0, FN_SEL_PWM6_1, - /* sel_pwm5[1](0,1) */ - FN_SEL_PWM5_0, FN_SEL_PWM5_1, - /* sel_pwm4[1](0,1) */ - FN_SEL_PWM4_0, FN_SEL_PWM4_1, - /* sel_pwm3[1](0,1) */ - FN_SEL_PWM3_0, FN_SEL_PWM3_1, - /* sel_pwm2[1](0,1) */ - FN_SEL_PWM2_0, FN_SEL_PWM2_1, - /* sel_pwm1[1](0,1) */ - FN_SEL_PWM1_0, FN_SEL_PWM1_1, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* i2c_sel_5[1](0,1) */ - FN_I2C_SEL_5_0, FN_I2C_SEL_5_1, - /* i2c_sel_3[1](0,1) */ - FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, - /* i2c_sel_0[1](0,1) */ - FN_I2C_SEL_0_0, FN_I2C_SEL_0_1, - /* sel_fm[2](0,1,2,3) */ - FN_SEL_FM_0, FN_SEL_FM_1, - FN_SEL_FM_2, FN_SEL_FM_3, - /* sel_scif5[1](0,1) */ - FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - /* sel_i2c6[3](0,1,2) */ - FN_SEL_I2C6_0, FN_SEL_I2C6_1, - FN_SEL_I2C6_2, 0, - /* sel_ndfc[1](0,1) */ - FN_SEL_NDFC_0, FN_SEL_NDFC_1, - /* sel_ssi2[1](0,1) */ - FN_SEL_SSI2_0, FN_SEL_SSI2_1, - /* sel_ssi9[1](0,1) */ - FN_SEL_SSI9_0, FN_SEL_SSI9_1, - /* sel_timer_tmu2[1](0,1) */ - FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1, - /* sel_adg_b[1](0,1) */ - FN_SEL_ADG_B_0, FN_SEL_ADG_B_1, - /* sel_adg_c[1](0,1) */ - FN_SEL_ADG_C_0, FN_SEL_ADG_C_1, - /* reserved[16..16] */ - 0, 0, - /* reserved[15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved[7..1] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* sel_vin4[1](0,1) */ - FN_SEL_VIN4_0, FN_SEL_VIN4_1, - } - }, - { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_IN, GP_0_15_OUT, - GP_0_14_IN, GP_0_14_OUT, - GP_0_13_IN, GP_0_13_OUT, - GP_0_12_IN, GP_0_12_OUT, - GP_0_11_IN, GP_0_11_OUT, - GP_0_10_IN, GP_0_10_OUT, - GP_0_9_IN, GP_0_9_OUT, - GP_0_8_IN, GP_0_8_OUT, - GP_0_7_IN, GP_0_7_OUT, - GP_0_6_IN, GP_0_6_OUT, - GP_0_5_IN, GP_0_5_OUT, - GP_0_4_IN, GP_0_4_OUT, - GP_0_3_IN, GP_0_3_OUT, - GP_0_2_IN, GP_0_2_OUT, - GP_0_1_IN, GP_0_1_OUT, - GP_0_0_IN, GP_0_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_IN, GP_1_28_OUT, - GP_1_27_IN, GP_1_27_OUT, - GP_1_26_IN, GP_1_26_OUT, - GP_1_25_IN, GP_1_25_OUT, - GP_1_24_IN, GP_1_24_OUT, - GP_1_23_IN, GP_1_23_OUT, - GP_1_22_IN, GP_1_22_OUT, - GP_1_21_IN, GP_1_21_OUT, - GP_1_20_IN, GP_1_20_OUT, - GP_1_19_IN, GP_1_19_OUT, - GP_1_18_IN, GP_1_18_OUT, - GP_1_17_IN, GP_1_17_OUT, - GP_1_16_IN, GP_1_16_OUT, - GP_1_15_IN, GP_1_15_OUT, - GP_1_14_IN, GP_1_14_OUT, - GP_1_13_IN, GP_1_13_OUT, - GP_1_12_IN, GP_1_12_OUT, - GP_1_11_IN, GP_1_11_OUT, - GP_1_10_IN, GP_1_10_OUT, - GP_1_9_IN, GP_1_9_OUT, - GP_1_8_IN, GP_1_8_OUT, - GP_1_7_IN, GP_1_7_OUT, - GP_1_6_IN, GP_1_6_OUT, - GP_1_5_IN, GP_1_5_OUT, - GP_1_4_IN, GP_1_4_OUT, - GP_1_3_IN, GP_1_3_OUT, - GP_1_2_IN, GP_1_2_OUT, - GP_1_1_IN, GP_1_1_OUT, - GP_1_0_IN, GP_1_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_IN, GP_2_14_OUT, - GP_2_13_IN, GP_2_13_OUT, - GP_2_12_IN, GP_2_12_OUT, - GP_2_11_IN, GP_2_11_OUT, - GP_2_10_IN, GP_2_10_OUT, - GP_2_9_IN, GP_2_9_OUT, - GP_2_8_IN, GP_2_8_OUT, - GP_2_7_IN, GP_2_7_OUT, - GP_2_6_IN, GP_2_6_OUT, - GP_2_5_IN, GP_2_5_OUT, - GP_2_4_IN, GP_2_4_OUT, - GP_2_3_IN, GP_2_3_OUT, - GP_2_2_IN, GP_2_2_OUT, - GP_2_1_IN, GP_2_1_OUT, - GP_2_0_IN, GP_2_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_IN, GP_3_15_OUT, - GP_3_14_IN, GP_3_14_OUT, - GP_3_13_IN, GP_3_13_OUT, - GP_3_12_IN, GP_3_12_OUT, - GP_3_11_IN, GP_3_11_OUT, - GP_3_10_IN, GP_3_10_OUT, - GP_3_9_IN, GP_3_9_OUT, - GP_3_8_IN, GP_3_8_OUT, - GP_3_7_IN, GP_3_7_OUT, - GP_3_6_IN, GP_3_6_OUT, - GP_3_5_IN, GP_3_5_OUT, - GP_3_4_IN, GP_3_4_OUT, - GP_3_3_IN, GP_3_3_OUT, - GP_3_2_IN, GP_3_2_OUT, - GP_3_1_IN, GP_3_1_OUT, - GP_3_0_IN, GP_3_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_IN, GP_4_17_OUT, - GP_4_16_IN, GP_4_16_OUT, - - GP_4_15_IN, GP_4_15_OUT, - GP_4_14_IN, GP_4_14_OUT, - GP_4_13_IN, GP_4_13_OUT, - GP_4_12_IN, GP_4_12_OUT, - GP_4_11_IN, GP_4_11_OUT, - GP_4_10_IN, GP_4_10_OUT, - GP_4_9_IN, GP_4_9_OUT, - GP_4_8_IN, GP_4_8_OUT, - GP_4_7_IN, GP_4_7_OUT, - GP_4_6_IN, GP_4_6_OUT, - GP_4_5_IN, GP_4_5_OUT, - GP_4_4_IN, GP_4_4_OUT, - GP_4_3_IN, GP_4_3_OUT, - GP_4_2_IN, GP_4_2_OUT, - GP_4_1_IN, GP_4_1_OUT, - GP_4_0_IN, GP_4_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_IN, GP_5_25_OUT, - GP_5_24_IN, GP_5_24_OUT, - - GP_5_23_IN, GP_5_23_OUT, - GP_5_22_IN, GP_5_22_OUT, - GP_5_21_IN, GP_5_21_OUT, - GP_5_20_IN, GP_5_20_OUT, - GP_5_19_IN, GP_5_19_OUT, - GP_5_18_IN, GP_5_18_OUT, - GP_5_17_IN, GP_5_17_OUT, - GP_5_16_IN, GP_5_16_OUT, - - GP_5_15_IN, GP_5_15_OUT, - GP_5_14_IN, GP_5_14_OUT, - GP_5_13_IN, GP_5_13_OUT, - GP_5_12_IN, GP_5_12_OUT, - GP_5_11_IN, GP_5_11_OUT, - GP_5_10_IN, GP_5_10_OUT, - GP_5_9_IN, GP_5_9_OUT, - GP_5_8_IN, GP_5_8_OUT, - GP_5_7_IN, GP_5_7_OUT, - GP_5_6_IN, GP_5_6_OUT, - GP_5_5_IN, GP_5_5_OUT, - GP_5_4_IN, GP_5_4_OUT, - GP_5_3_IN, GP_5_3_OUT, - GP_5_2_IN, GP_5_2_OUT, - GP_5_1_IN, GP_5_1_OUT, - GP_5_0_IN, GP_5_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { - GP_INOUTSEL(6) - } - }, - { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_6_3_IN, GP_6_3_OUT, - GP_6_2_IN, GP_6_2_OUT, - GP_6_1_IN, GP_6_1_OUT, - GP_6_0_IN, GP_6_0_OUT, - } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - /* use OUTDT registers? */ - { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, - GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, - GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, - GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } - }, - { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { - 0, 0, 0, GP_1_28_DATA, - GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, - GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, - GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, - GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, - GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, - GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, - GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } - }, - { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, - GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, - GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, - GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } - }, - { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, - GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, - GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, - GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } - }, - { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA, - GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA, - GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA, - GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA, - GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } - }, - { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { - 0, 0, 0, 0, - 0, 0, GP_5_25_DATA, GP_5_24_DATA, - GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, - GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, - GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, - GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, - GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, - GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } - }, - { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { - GP_INDT(6) } - }, - { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, - GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } - }, - { }, -}; - - -static struct pinmux_info r8a7795_pinmux_info = { - .name = "r8a7795_pfc", - - .unlock_reg = 0xe6060000, /* PMMR */ - - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_FMIN_D, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), -}; - -void r8a7795_pinmux_init(void) -{ - register_pinmux(&r8a7795_pinmux_info); -} diff --git a/arch/arm/mach-rmobile/pfc-r8a7796.c b/arch/arm/mach-rmobile/pfc-r8a7796.c deleted file mode 100644 index f734f96dd08..00000000000 --- a/arch/arm/mach-rmobile/pfc-r8a7796.c +++ /dev/null @@ -1,5253 +0,0 @@ -/* - * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7796.c - * This file is r8a7796 processor support - PFC hardware block. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <sh_pfc.h> -#include <asm/gpio.h> - -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT1(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT2(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT_29(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##28, sfx) - -#define CPU_32_PORT_26(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx) - -#define CPU_32_PORT_18(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##16, sfx), \ - PORT_1(fn, pfx##17, sfx) - -#define CPU_32_PORT_16(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx) - -#define CPU_32_PORT_15(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx) - -#define CPU_32_PORT_4(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), \ - PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##3, sfx) - - -/* --gen3-- */ -/* GP_0_0_DATA -> GP_7_4_DATA */ -/* except for GP0[16] - [31], - GP1[28] - [31], - GP2[15] - [31], - GP3[16] - [31], - GP4[18] - [31], - GP5[26] - [31], - GP7[4] - [31] */ - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_29(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) - -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - GP_ALL(DATA), - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - GP_ALL(IN), - PINMUX_INPUT_END, - - PINMUX_OUTPUT_BEGIN, - GP_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - GP_ALL(FN), - - /* GPSR0 */ - GFN_D15, - GFN_D14, - GFN_D13, - GFN_D12, - GFN_D11, - GFN_D10, - GFN_D9, - GFN_D8, - GFN_D7, - GFN_D6, - GFN_D5, - GFN_D4, - GFN_D3, - GFN_D2, - GFN_D1, - GFN_D0, - - /* GPSR1 */ - GFN_CLKOUT, - GFN_EX_WAIT0_A, - GFN_WE1x, - GFN_WE0x, - GFN_RD_WRx, - GFN_RDx, - GFN_BSx, - GFN_CS1x_A26, - GFN_CS0x, - GFN_A19, - GFN_A18, - GFN_A17, - GFN_A16, - GFN_A15, - GFN_A14, - GFN_A13, - GFN_A12, - GFN_A11, - GFN_A10, - GFN_A9, - GFN_A8, - GFN_A7, - GFN_A6, - GFN_A5, - GFN_A4, - GFN_A3, - GFN_A2, - GFN_A1, - GFN_A0, - - /* GPSR2 */ - GFN_AVB_AVTP_CAPTURE_A, - GFN_AVB_AVTP_MATCH_A, - GFN_AVB_LINK, - GFN_AVB_PHY_INT, - GFN_AVB_MAGIC, - GFN_AVB_MDC, - GFN_PWM2_A, - GFN_PWM1_A, - GFN_PWM0, - GFN_IRQ5, - GFN_IRQ4, - GFN_IRQ3, - GFN_IRQ2, - GFN_IRQ1, - GFN_IRQ0, - - /* GPSR3 */ - GFN_SD1_WP, - GFN_SD1_CD, - GFN_SD0_WP, - GFN_SD0_CD, - GFN_SD1_DAT3, - GFN_SD1_DAT2, - GFN_SD1_DAT1, - GFN_SD1_DAT0, - GFN_SD1_CMD, - GFN_SD1_CLK, - GFN_SD0_DAT3, - GFN_SD0_DAT2, - GFN_SD0_DAT1, - GFN_SD0_DAT0, - GFN_SD0_CMD, - GFN_SD0_CLK, - - /* GPSR4 */ - GFN_SD3_DS, - GFN_SD3_DAT7, - GFN_SD3_DAT6, - GFN_SD3_DAT5, - GFN_SD3_DAT4, - FN_SD3_DAT3, - FN_SD3_DAT2, - FN_SD3_DAT1, - FN_SD3_DAT0, - FN_SD3_CMD, - FN_SD3_CLK, - GFN_SD2_DS, - GFN_SD2_DAT3, - GFN_SD2_DAT2, - GFN_SD2_DAT1, - GFN_SD2_DAT0, - FN_SD2_CMD, - GFN_SD2_CLK, - - /* GPSR5 */ - GFN_MLB_DAT, - GFN_MLB_SIG, - GFN_MLB_CLK, - FN_MSIOF0_RXD, - GFN_MSIOF0_SS2, - FN_MSIOF0_TXD, - GFN_MSIOF0_SS1, - GFN_MSIOF0_SYNC, - FN_MSIOF0_SCK, - GFN_HRTS0x, - GFN_HCTS0x, - GFN_HTX0, - GFN_HRX0, - GFN_HSCK0, - GFN_RX2_A, - GFN_TX2_A, - GFN_SCK2, - GFN_RTS1x_TANS, - GFN_CTS1x, - GFN_TX1_A, - GFN_RX1_A, - GFN_RTS0x_TANS, - GFN_CTS0x, - GFN_TX0, - GFN_RX0, - GFN_SCK0, - - /* GPSR6 */ - GFN_GP6_30, - GFN_GP6_31, - GFN_USB30_OVC, - GFN_USB30_PWEN, - GFN_USB1_OVC, - GFN_USB1_PWEN, - GFN_USB0_OVC, - GFN_USB0_PWEN, - GFN_AUDIO_CLKB_B, - GFN_AUDIO_CLKA_A, - GFN_SSI_SDATA9_A, - GFN_SSI_SDATA8, - GFN_SSI_SDATA7, - GFN_SSI_WS78, - GFN_SSI_SCK78, - GFN_SSI_SDATA6, - GFN_SSI_WS6, - GFN_SSI_SCK6, - FN_SSI_SDATA5, - FN_SSI_WS5, - FN_SSI_SCK5, - GFN_SSI_SDATA4, - GFN_SSI_WS4, - GFN_SSI_SCK4, - GFN_SSI_SDATA3, - GFN_SSI_WS34, - GFN_SSI_SCK34, - GFN_SSI_SDATA2_A, - GFN_SSI_SDATA1_A, - GFN_SSI_SDATA0, - GFN_SSI_WS01239, - GFN_SSI_SCK01239, - - /* GPSR7 */ - FN_HDMI1_CEC, - FN_HDMI0_CEC, - FN_AVS2, - FN_AVS1, - - /* IPSR0 */ - IFN_AVB_MDC, - FN_MSIOF2_SS2_C, - IFN_AVB_MAGIC, - FN_MSIOF2_SS1_C, - FN_SCK4_A, - IFN_AVB_PHY_INT, - FN_MSIOF2_SYNC_C, - FN_RX4_A, - IFN_AVB_LINK, - FN_MSIOF2_SCK_C, - FN_TX4_A, - IFN_AVB_AVTP_MATCH_A, - FN_MSIOF2_RXD_C, - FN_CTS4x_A, - IFN_AVB_AVTP_CAPTURE_A, - FN_MSIOF2_TXD_C, - FN_RTS4x_TANS_A, - IFN_IRQ0, - FN_QPOLB, - FN_DU_CDE, - FN_VI4_DATA0_B, - FN_CAN0_TX_B, - FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - IFN_IRQ1, - FN_QPOLA, - FN_DU_DISP, - FN_VI4_DATA1_B, - FN_CAN0_RX_B, - FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - - /* IPSR1 */ - IFN_IRQ2, - FN_QCPV_QDE, - FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, - FN_MSIOF3_SYNC_E, - FN_PWM3_B, - IFN_IRQ3, - FN_QSTVB_QVE, - FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, - FN_MSIOF3_SCK_E, - FN_PWM4_B, - IFN_IRQ4, - FN_QSTH_QHS, - FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, - FN_MSIOF3_RXD_E, - FN_PWM5_B, - IFN_IRQ5, - FN_QSTB_QHE, - FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, - FN_MSIOF3_TXD_E, - FN_PWM6_B, - IFN_PWM0, - FN_AVB_AVTP_PPS, - FN_VI4_DATA6_B, - FN_IECLK_B, - IFN_PWM1_A, - FN_HRX3_D, - FN_VI4_DATA7_B, - FN_IERX_B, - IFN_PWM2_A, - FN_PWMFSW0, - FN_HTX3_D, - FN_IETX_B, - IFN_A0, - FN_LCDOUT16, - FN_MSIOF3_SYNC_B, - FN_VI4_DATA8, - FN_DU_DB0, - FN_PWM3_A, - - /* IPSR2 */ - IFN_A1, - FN_LCDOUT17, - FN_MSIOF3_TXD_B, - FN_VI4_DATA9, - FN_DU_DB1, - FN_PWM4_A, - IFN_A2, - FN_LCDOUT18, - FN_MSIOF3_SCK_B, - FN_VI4_DATA10, - FN_DU_DB2, - FN_PWM5_A, - IFN_A3, - FN_LCDOUT19, - FN_MSIOF3_RXD_B, - FN_VI4_DATA11, - FN_DU_DB3, - FN_PWM6_A, - IFN_A4, - FN_LCDOUT20, - FN_MSIOF3_SS1_B, - FN_VI4_DATA12, - FN_VI5_DATA12, - FN_DU_DB4, - IFN_A5, - FN_LCDOUT21, - FN_MSIOF3_SS2_B, - FN_SCK4_B, - FN_VI4_DATA13, - FN_VI5_DATA13, - FN_DU_DB5, - IFN_A6, - FN_LCDOUT22, - FN_MSIOF2_SS1_A, - FN_RX4_B, - FN_VI4_DATA14, - FN_VI5_DATA14, - FN_DU_DB6, - IFN_A7, - FN_LCDOUT23, - FN_MSIOF2_SS2_A, - FN_TX4_B, - FN_VI4_DATA15, - FN_V15_DATA15, - FN_DU_DB7, - IFN_A8, - FN_RX3_B, - FN_MSIOF2_SYNC_A, - FN_HRX4_B, - FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, - FN_PWM1_B, - - /* IPSR3 */ - IFN_A9, - FN_MSIOF2_SCK_A, - FN_CTS4x_B, - FN_VI5_VSYNCx, - IFN_A10, - FN_MSIOF2_RXD_A, - FN_RTS4n_TANS_B, - FN_VI5_HSYNCx, - IFN_A11, - FN_TX3_B, - FN_MSIOF2_TXD_A, - FN_HTX4_B, - FN_HSCK4, - FN_VI5_FIELD, - FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, - FN_PWM2_B, - FN_SPV_EVEN, - IFN_A12, - FN_LCDOUT12, - FN_MSIOF3_SCK_C, - FN_HRX4_A, - FN_VI5_DATA8, - FN_DU_DG4, - IFN_A13, - FN_LCDOUT13, - FN_MSIOF3_SYNC_C, - FN_HTX4_A, - FN_VI5_DATA9, - FN_DU_DG5, - IFN_A14, - FN_LCDOUT14, - FN_MSIOF3_RXD_C, - FN_HCTS4x, - FN_VI5_DATA10, - FN_DU_DG6, - IFN_A15, - FN_LCDOUT15, - FN_MSIOF3_TXD_C, - FN_HRTS4x, - FN_VI5_DATA11, - FN_DU_DG7, - IFN_A16, - FN_LCDOUT8, - FN_VI4_FIELD, - FN_DU_DG0, - - /* IPSR4 */ - IFN_A17, - FN_LCDOUT9, - FN_VI4_VSYNCx, - FN_DU_DG1, - IFN_A18, - FN_LCDOUT10, - FN_VI4_HSYNCx, - FN_DU_DG2, - IFN_A19, - FN_LCDOUT11, - FN_VI4_CLKENB, - FN_DU_DG3, - IFN_CS0x, - FN_VI5_CLKENB, - IFN_CS1x_A26, - FN_VI5_CLK, - FN_EX_WAIT0_B, - IFN_BSx, - FN_QSTVA_QVS, - FN_MSIOF3_SCK_D, - FN_SCK3, - FN_HSCK3, - FN_CAN1_TX, - FN_CANFD1_TX, - FN_IETX_A, - IFN_RDx, - FN_MSIOF3_SYNC_D, - FN_RX3_A, - FN_HRX3_A, - FN_CAN0_TX_A, - FN_CANFD0_TX_A, - IFN_RD_WRx, - FN_MSIOF3_RXD_D, - FN_TX3_A, - FN_HTX3_A, - FN_CAN0_RX_A, - FN_CANFD0_RX_A, - - /* IPSR5 */ - IFN_WE0x, - FN_MSIIOF3_TXD_D, - FN_CTS3x, - FN_HCTS3x, - FN_SCL6_B, - FN_CAN_CLK, - FN_IECLK_A, - IFN_WE1x, - FN_MSIOF3_SS1_D, - FN_RTS3x_TANS, - FN_HRTS3x, - FN_SDA6_B, - FN_CAN1_RX, - FN_CANFD1_RX, - FN_IERX_A, - IFN_EX_WAIT0_A, - FN_QCLK, - FN_VI4_CLK, - FN_DU_DOTCLKOUT0, - IFN_D0, - FN_MSIOF2_SS1_B, - FN_MSIOF3_SCK_A, - FN_VI4_DATA16, - FN_VI5_DATA0, - IFN_D1, - FN_MSIOF2_SS2_B, - FN_MSIOF3_SYNC_A, - FN_VI4_DATA17, - FN_VI5_DATA1, - IFN_D2, - FN_MSIOF3_RXD_A, - FN_VI4_DATA18, - FN_VI5_DATA2, - IFN_D3, - FN_MSIOF3_TXD_A, - FN_VI4_DATA19, - FN_VI5_DATA3, - IFN_D4, - FN_MSIOF2_SCK_B, - FN_VI4_DATA20, - FN_VI5_DATA4, - - /* IPSR6 */ - IFN_D5, - FN_MSIOF2_SYNC_B, - FN_VI4_DATA21, - FN_VI5_DATA5, - IFN_D6, - FN_MSIOF2_RXD_B, - FN_VI4_DATA22, - FN_VI5_DATA6, - IFN_D7, - FN_MSIOF2_TXD_B, - FN_VI4_DATA23, - FN_VI5_DATA7, - IFN_D8, - FN_LCDOUT0, - FN_MSIOF2_SCK_D, - FN_SCK4_C, - FN_VI4_DATA0_A, - FN_DU_DR0, - IFN_D9, - FN_LCDOUT1, - FN_MSIOF2_SYNC_D, - FN_VI4_DATA1_A, - FN_DU_DR1, - IFN_D10, - FN_LCDOUT2, - FN_MSIOF2_RXD_D, - FN_HRX3_B, - FN_VI4_DATA2_A, - FN_CTS4x_C, - FN_DU_DR2, - IFN_D11, - FN_LCDOUT3, - FN_MSIOF2_TXD_D, - FN_HTX3_B, - FN_VI4_DATA3_A, - FN_RTS4x_TANS_C, - FN_DU_DR3, - IFN_D12, - FN_LCDOUT4, - FN_MSIOF2_SS1_D, - FN_RX4_C, - FN_VI4_DATA4_A, - FN_DU_DR4, - - /* IPSR7 */ - IFN_D13, - FN_LCDOUT5, - FN_MSIOF2_SS2_D, - FN_TX4_C, - FN_VI4_DATA5_A, - FN_DU_DR5, - IFN_D14, - FN_LCDOUT6, - FN_MSIOF3_SS1_A, - FN_HRX3_C, - FN_VI4_DATA6_A, - FN_DU_DR6, - FN_SCL6_C, - IFN_D15, - FN_LCDOUT7, - FN_MSIOF3_SS2_A, - FN_HTX3_C, - FN_VI4_DATA7_A, - FN_DU_DR7, - FN_SDA6_C, - FN_FSCLKST, - IFN_SD0_CLK, - FN_MSIOF1_SCK_E, - FN_STP_OPWM_0_B, - IFN_SD0_CMD, - FN_MSIOF1_SYNC_E, - FN_STP_IVCXO27_0_B, - IFN_SD0_DAT0, - FN_MSIOF1_RXD_E, - FN_TS_SCK0_B, - FN_STP_ISCLK_0_B, - IFN_SD0_DAT1, - FN_MSIOF1_TXD_E, - FN_TS_SPSYNC0_B, - FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - IFN_SD0_DAT2, - FN_MSIOF1_SS1_E, - FN_TS_SDAT0_B, - FN_STP_ISD_0_B, - - IFN_SD0_DAT3, - FN_MSIOF1_SS2_E, - FN_TS_SDEN0_B, - FN_STP_ISEN_0_B, - - IFN_SD1_CLK, - FN_MSIOF1_SCK_G, - FN_SIM0_CLK_A, - - IFN_SD1_CMD, - FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - FN_SIM0_D_A, - FN_STP_IVCXO27_1_B, - - IFN_SD1_DAT0, - FN_SD2_DAT4, - FN_MSIOF1_RXD_G, - FN_NFWPx_B, - FN_TS_SCK1_B, - FN_STP_ISCLK_1_B, - - IFN_SD1_DAT1, - FN_SD2_DAT5, - FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - FN_TS_SPSYNC1_B, - FN_STP_ISSYNC_1_B, - - IFN_SD1_DAT2, - FN_SD2_DAT6, - FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - FN_TS_SDAT1_B, - FN_STP_IOD_1_B, - - IFN_SD1_DAT3, - FN_SD2_DAT7, - FN_MSIOF1_SS2_G, - FN_NFRBx_B, - FN_TS_SDEN1_B, - FN_STP_ISEN_1_B, - - /* IPSR9 */ - IFN_SD2_CLK, - FN_NFDATA8, - - IFN_SD2_CMD, - FN_NFDATA9, - - IFN_SD2_DAT0, - FN_NFDATA10, - - IFN_SD2_DAT1, - FN_NFDATA11, - - IFN_SD2_DAT2, - FN_NFDATA12, - - IFN_SD2_DAT3, - FN_NFDATA13, - - IFN_SD2_DS, - FN_NFALE, - - IFN_SD3_CLK, - FN_NFWEx, - - /* IPSR10 */ - IFN_SD3_CMD, - FN_NFREx, - - IFN_SD3_DAT0, - FN_NFDATA0, - - IFN_SD3_DAT1, - FN_NFDATA1, - - IFN_SD3_DAT2, - FN_NFDATA2, - - IFN_SD3_DAT3, - FN_NFDATA3, - - IFN_SD3_DAT4, - FN_SD2_CD_A, - FN_NFDATA4, - - IFN_SD3_DAT5, - FN_SD2_WP_A, - FN_NFDATA5, - - IFN_SD3_DAT6, - FN_SD3_CD, - FN_NFDATA6, - - /* IPSR11 */ - IFN_SD3_DAT7, - FN_SD3_WP, - FN_NFDATA7, - - IFN_SD3_DS, - FN_NFCLE, - - IFN_SD0_CD, - FN_NFDATA14_A, - FN_SCL2_B, - FN_SIM0_RST_A, - - IFN_SD0_WP, - FN_NFDATA15_A, - FN_SDA2_B, - - IFN_SD1_CD, - FN_NFRBx_A, - FN_SIM0_CLK_B, - - IFN_SD1_WP, - FN_NFCEx_A, - FN_SIM0_D_B, - - IFN_SCK0, - FN_HSCK1_B, - FN_MSIOF1_SS2_B, - FN_AUDIO_CLKC_B, - FN_SDA2_A, - FN_SIM0_RST_B, - FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - FN_ADICHS2, - FN_SCK5_B, - - IFN_RX0, - FN_HRX1_B, - FN_TS_SCK0_C, - FN_STP_ISCLK_0_C, - FN_RIF0_D0_B, - - /* IPSR12 */ - IFN_TX0, - FN_HTX1_B, - FN_TS_SPSYNC0_C, - FN_STP_ISSYNC_0_C, - FN_RIF0_D1_B, - - IFN_CTS0x, - FN_HCTS1x_B, - FN_MSIOF1_SYNC_B, - FN_TS_SPSYNC1_C, - FN_STP_ISSYNC_1_C, - FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, - FN_ADICS_SAMP, - - IFN_RTS0x_TANS, - FN_HRTS1x_B, - FN_MSIOF1_SS1_B, - FN_AUDIO_CLKA_B, - FN_SCL2_A, - FN_STP_IVCXO27_1_C, - FN_RIF0_SYNC_B, - FN_ADICHS1, - - IFN_RX1_A, - FN_HRX1_A, - FN_TS_SDAT0_C, - FN_STP_ISD_0_C, - FN_RIF1_CLK_C, - - IFN_TX1_A, - FN_HTX1_A, - FN_TS_SDEN0_C, - FN_STP_ISEN_0_C, - FN_RIF1_D0_C, - - IFN_CTS1x, - FN_HCTS1x_A, - FN_MSIOF1_RXD_B, - FN_TS_SDEN1_C, - FN_STP_ISEN_1_C, - FN_RIF1_D0_B, - FN_ADIDATA, - - IFN_RTS1x_TANS, - FN_HRTS1x_A, - FN_MSIOF1_TXD_B, - FN_TS_SDAT1_C, - FN_STP_ISD_1_C, - FN_RIF1_D1_B, - FN_ADICHS0, - - IFN_SCK2, - FN_SCIF_CLK_B, - FN_MSIOF1_SCK_B, - FN_TS_SCK1_C, - FN_STP_ISCLK_1_C, - FN_RIF1_CLK_B, - FN_ADICLK, - - /* IPSR13 */ - IFN_TX2_A, - FN_SD2_CD_B, - FN_SCL1_A, - FN_FMCLK_A, - FN_RIF1_D1_C, - FN_FSO_CFE_0_B, - - IFN_RX2_A, - FN_SD2_WP_B, - FN_SDA1_A, - FN_FMIN_A, - FN_RIF1_SYNC_C, - FN_FSO_CEF_1_B, - - IFN_HSCK0, - FN_MSIOF1_SCK_D, - FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, - FN_TS_SCK0_D, - FN_STP_ISCLK_0_D, - FN_RIF0_CLK_C, - FN_RX5_B, - - IFN_HRX0, - FN_MSIOF1_RXD_D, - FN_SS1_SDATA2_B, - FN_TS_SDEN0_D, - FN_STP_ISEN_0_D, - FN_RIF0_D0_C, - - IFN_HTX0, - FN_MSIOF1_TXD_D, - FN_SSI_SDATA9_B, - FN_TS_SDAT0_D, - FN_STP_ISD_0_D, - FN_RIF0_D1_C, - - IFN_HCTS0x, - FN_RX2_B, - FN_MSIOF1_SYNC_D, - FN_SSI_SCK9_A, - FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, - - IFN_HRTS0x, - FN_TX2_B, - FN_MSIOF1_SS1_D, - FN_SSI_WS9_A, - FN_STP_IVCXO27_0_D, - FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, - - IFN_MSIOF0_SYNC, - FN_AUDIO_CLKOUT_A, - FN_TX5_B, - FN_BPFCLK_D, - - /* IPSR14 */ - IFN_MSIOF0_SS1, - FN_RX5_A, - FN_NFWPx_A, - FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, - FN_STP_IVCXO27_0_C, - FN_AUDIO_CLKOUT3_A, - FN_TCLK1_B, - - IFN_MSIOF0_SS2, - FN_TX5_A, - FN_MSIOF1_SS2_D, - FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, - FN_STP_OPWM_0_D, - FN_AUDIO_CLKOUT_D, - FN_SPEEDIN_B, - - IFN_MLB_CLK, - FN_MSIOF1_SCK_F, - FN_SCL1_B, - - IFN_MLB_SIG, - FN_RX1_B, - FN_MSIOF1_SYNC_F, - FN_SDA1_B, - - IFN_MLB_DAT, - FN_TX1_B, - FN_MSIOF1_RXD_F, - - IFN_SSI_SCK0129, - FN_MSIOF1_TXD_F, - FN_MOUT0, - - IFN_SSI_WS0129, - FN_MSIOF1_SS1_F, - FN_MOUT1, - - IFN_SSI_SDATA0, - FN_MSIOF1_SS2_F, - FN_MOUT2, - - /* IPSR15 */ - IFN_SSI_SDATA1_A, - FN_MOUT5, - - IFN_SSI_SDATA2_A, - FN_SSI_SCK1_B, - FN_MOUT6, - - IFN_SSI_SCK34, - FN_MSIOF1_SS1_A, - FN_STP_OPWM_0_A, - - IFN_SSI_WS34, - FN_HCTS2x_A, - FN_MSIOF1_SS2_A, - FN_STP_IVCXO27_0_A, - - IFN_SSI_SDATA3, - FN_HRTS2x_A, - FN_MSIOF1_TXD_A, - FN_TS_SCK0_A, - FN_STP_ISCLK_0_A, - FN_RIF0_D1_A, - FN_RIF2_D0_A, - - IFN_SSI_SCK4, - FN_HRX2_A, - FN_MSIOF1_SCK_A, - FN_TS_SDAT0_A, - FN_STP_ISD_0_A, - FN_RIF0_CLK_A, - FN_RIF2_CLK_A, - - IFN_SSI_WS4, - FN_HTX2_A, - FN_MSIOF1_SYNC_A, - FN_TS_SDEN0_A, - FN_STP_ISEN_0_A, - FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, - - IFN_SSI_SDATA4, - FN_HSCK2_A, - FN_MSIOF1_RXD_A, - FN_TS_SPSYNC0_A, - FN_STP_ISSYNC_0_A, - FN_RIF0_D0_A, - FN_RIF2_D1_A, - - /* IPSR16 */ - IFN_SSI_SCK6, - FN_SIM0_RST_D, - FN_FSO_TOE_A, - - IFN_SSI_WS6, - FN_SIM0_D_D, - - IFN_SSI_SDATA6, - FN_SIM0_CLK_D, - - IFN_SSI_SCK78, - FN_HRX2_B, - FN_MSIOF1_SCK_C, - FN_TS_SCK1_A, - FN_STP_ISCLK_1_A, - FN_RIF1_CLK_A, - FN_RIF3_CLK_A, - - IFN_SSI_WS78, - FN_HTX2_B, - FN_MSIOF1_SYNC_C, - FN_TS_SDAT1_A, - FN_STP_ISD_1_A, - FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, - - IFN_SSI_SDATA7, - FN_HCTS2x_B, - FN_MSIOF1_RXD_C, - FN_TS_SDEN1_A, - FN_STP_IEN_1_A, - FN_RIF1_D0_A, - FN_RIF3_D0_A, - FN_TCLK2_A, - - IFN_SSI_SDATA8, - FN_HRTS2x_B, - FN_MSIOF1_TXD_C, - FN_TS_SPSYNC1_A, - FN_STP_ISSYNC_1_A, - FN_RIF1_D1_A, - FN_EIF3_D1_A, - - IFN_SSI_SDATA9_A, - FN_HSCK2_B, - FN_MSIOF1_SS1_C, - FN_HSCK1_A, - FN_SSI_WS1_B, - FN_SCK1, - FN_STP_IVCXO27_1_A, - FN_SCK5, - - /* IPSR17 */ - IFN_AUDIO_CLKA_A, - FN_CC5_OSCOUT, - - IFN_AUDIO_CLKB_B, - FN_SCIF_CLK_A, - FN_STP_IVCXO27_1_D, - FN_REMOCON_A, - FN_TCLK1_A, - - IFN_USB0_PWEN, - FN_SIM0_RST_C, - FN_TS_SCK1_D, - FN_STP_ISCLK_1_D, - FN_BPFCLK_B, - FN_RIF3_CLK_B, - FN_FSO_CFE_1_A, - FN_HSCK2_C, - - IFN_USB0_OVC, - FN_SIM0_D_C, - FN_TS_SDAT1_D, - FN_STP_ISD_1_D, - FN_RIF3_SYNC_B, - FN_HRX2_C, - - IFN_USB1_PWEN, - FN_SIM0_CLK_C, - FN_SSI_SCK1_A, - FN_TS_SCK0_E, - FN_STP_ISCLK_0_E, - FN_FMCLK_B, - FN_RIF2_CLK_B, - FN_SPEEDIN_A, - FN_HTX2_C, - - IFN_USB1_OVC, - FN_MSIOF1_SS2_C, - FN_SSI_WS1_A, - FN_TS_SDAT0_E, - FN_STP_ISD_0_E, - FN_FMIN_B, - FN_RIF2_SYNC_B, - FN_REMOCON_B, - FN_HCTS2x_C, - - IFN_USB30_PWEN, - FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, - FN_TS_SDEN1_D, - FN_STP_ISEN_1_D, - FN_STP_OPWM_0_E, - FN_RIF3_D0_B, - FN_TCLK2_B, - FN_TPU0TO0, - FN_BPFCLK_C, - FN_HRTS2x_C, - - IFN_USB30_OVC, - FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, - FN_TS_SPSYNC1_D, - FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, - FN_FSO_TOE_B, - FN_TPU0TO1, - - /* IPSR18 */ - IFN_GP6_30, - FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, - FN_TS_SDEN0_E, - FN_STP_ISEN_0_E, - FN_RIF2_D0_B, - FN_FSO_CFE_0_A, - FN_TPU0TO2, - FN_FMCLK_C, - FN_FMCLK_D, - - IFN_GP6_31, - FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, - FN_TS_SPSYNC0_E, - FN_STP_ISSYNC_0_E, - FN_RIF2_D1_B, - FN_TPU0TO3, - FN_FMIN_C, - FN_FMIN_D, - - /* MOD_SEL0 */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5, - FN_SEL_MSIOF3_6, - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - FN_SEL_FSO_0, FN_SEL_FSO_1, - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_ADG_2, FN_SEL_ADG_3, - - /* MOD_SEL1 */ - FN_SEL_TSIF1_0, - FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, - FN_SEL_TSIF1_3, - FN_SEL_TSIF0_0, - FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, - FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - FN_SEL_TIMER_TMU_0, - FN_SEL_TIMER_TMU_1, - FN_SEL_SSP1_1_0, - FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, - FN_SEL_SSP1_1_3, - FN_SEL_SSP1_0_0, - FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, - FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - FN_SEL_SSI_0, - FN_SEL_SSI_1, - FN_SEL_SPEED_PULSE_IF_0, - FN_SEL_SPEED_PULSE_IF_1, - FN_SEL_SIMCARD_0, - FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, - FN_SEL_SIMCARD_3, - FN_SEL_SDHI2_0, - FN_SEL_SDHI2_1, - FN_SEL_SCIF4_0, - FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - FN_SEL_SCIF3_0, - FN_SEL_SCIF3_1, - FN_SEL_SCIF2_0, - FN_SEL_SCIF2_1, - FN_SEL_SCIF1_0, - FN_SEL_SCIF1_1, - FN_SEL_SCIF_0, - FN_SEL_SCIF_1, - FN_SEL_REMOCON_0, - FN_SEL_REMOCON_1, - FN_SEL_RCAN_0, - FN_SEL_RCAN_1, - FN_SEL_PWM6_0, - FN_SEL_PWM6_1, - FN_SEL_PWM5_0, - FN_SEL_PWM5_1, - FN_SEL_PWM4_0, - FN_SEL_PWM4_1, - FN_SEL_PWM3_0, - FN_SEL_PWM3_1, - FN_SEL_PWM2_0, - FN_SEL_PWM2_1, - FN_SEL_PWM1_0, - FN_SEL_PWM1_1, - - /* MOD_SEL2 */ - FN_I2C_SEL_5_0, - FN_I2C_SEL_5_1, - FN_I2C_SEL_3_0, - FN_I2C_SEL_3_1, - FN_I2C_SEL_0_0, - FN_I2C_SEL_0_1, - FN_SEL_FM_0, - FN_SEL_FM_1, - FN_SEL_FM_2, - FN_SEL_FM_3, - FN_SEL_SCIF5_0, - FN_SEL_SCIF5_1, - FN_SEL_I2C6_0, - FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - FN_SEL_NDF_0, - FN_SEL_NDF_1, - FN_SEL_SSI2_0, - FN_SEL_SSI2_1, - FN_SEL_SSI9_0, - FN_SEL_SSI9_1, - FN_SEL_TIMER_TMU2_0, - FN_SEL_TIMER_TMU2_1, - FN_SEL_ADG_B_0, - FN_SEL_ADG_B_1, - FN_SEL_ADG_C_0, - FN_SEL_ADG_C_1, - FN_SEL_VIN4_0, - FN_SEL_VIN4_1, - - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - /* GPSR0 */ - D15_GMARK, - D14_GMARK, - D13_GMARK, - D12_GMARK, - D11_GMARK, - D10_GMARK, - D9_GMARK, - D8_GMARK, - D7_GMARK, - D6_GMARK, - D5_GMARK, - D4_GMARK, - D3_GMARK, - D2_GMARK, - D1_GMARK, - D0_GMARK, - - /* GPSR1 */ - CLKOUT_GMARK, - EX_WAIT0_A_GMARK, - WE1x_GMARK, - WE0x_GMARK, - RD_WRx_GMARK, - RDx_GMARK, - BSx_GMARK, - CS1x_A26_GMARK, - CS0x_GMARK, - A19_GMARK, - A18_GMARK, - A17_GMARK, - A16_GMARK, - A15_GMARK, - A14_GMARK, - A13_GMARK, - A12_GMARK, - A11_GMARK, - A10_GMARK, - A9_GMARK, - A8_GMARK, - A7_GMARK, - A6_GMARK, - A5_GMARK, - A4_GMARK, - A3_GMARK, - A2_GMARK, - A1_GMARK, - A0_GMARK, - - /* GPSR2 */ - AVB_AVTP_CAPTURE_A_GMARK, - AVB_AVTP_MATCH_A_GMARK, - AVB_LINK_GMARK, - AVB_PHY_INT_GMARK, - AVB_MAGIC_GMARK, - AVB_MDC_GMARK, - PWM2_A_GMARK, - PWM1_A_GMARK, - PWM0_GMARK, - IRQ5_GMARK, - IRQ4_GMARK, - IRQ3_GMARK, - IRQ2_GMARK, - IRQ1_GMARK, - IRQ0_GMARK, - - /* GPSR3 */ - SD1_WP_GMARK, - SD1_CD_GMARK, - SD0_WP_GMARK, - SD0_CD_GMARK, - SD1_DAT3_GMARK, - SD1_DAT2_GMARK, - SD1_DAT1_GMARK, - SD1_DAT0_GMARK, - SD1_CMD_GMARK, - SD1_CLK_GMARK, - SD0_DAT3_GMARK, - SD0_DAT2_GMARK, - SD0_DAT1_GMARK, - SD0_DAT0_GMARK, - SD0_CMD_GMARK, - SD0_CLK_GMARK, - - /* GPSR4 */ - SD3_DS_GMARK, - SD3_DAT7_GMARK, - SD3_DAT6_GMARK, - SD3_DAT5_GMARK, - SD3_DAT4_GMARK, - SD3_DAT3_MARK, - SD3_DAT2_MARK, - SD3_DAT1_MARK, - SD3_DAT0_MARK, - SD3_CMD_MARK, - SD3_CLK_MARK, - SD2_DS_GMARK, - SD2_DAT3_GMARK, - SD2_DAT2_GMARK, - SD2_DAT1_GMARK, - SD2_DAT0_GMARK, - SD2_CMD_MARK, - SD2_CLK_GMARK, - - /* GPSR5 */ - MLB_DAT_GMARK, - MLB_SIG_GMARK, - MLB_CLK_GMARK, - MSIOF0_RXD_MARK, - MSIOF0_SS2_GMARK, - MSIOF0_TXD_MARK, - MSIOF0_SS1_GMARK, - MSIOF0_SYNC_GMARK, - MSIOF0_SCK_MARK, - HRTS0x_GMARK, - HCTS0x_GMARK, - HTX0_GMARK, - HRX0_GMARK, - HSCK0_GMARK, - RX2_A_GMARK, - TX2_A_GMARK, - SCK2_GMARK, - RTS1x_TANS_GMARK, - CTS1x_GMARK, - TX1_A_GMARK, - RX1_A_GMARK, - RTS0x_TANS_GMARK, - CTS0x_GMARK, - TX0_GMARK, - RX0_GMARK, - SCK0_GMARK, - - /* GPSR6 */ - GP6_30_GMARK, - GP6_31_GMARK, - USB30_OVC_GMARK, - USB30_PWEN_GMARK, - USB1_OVC_GMARK, - USB1_PWEN_GMARK, - USB0_OVC_GMARK, - USB0_PWEN_GMARK, - AUDIO_CLKB_B_GMARK, - AUDIO_CLKA_A_GMARK, - SSI_SDATA9_A_GMARK, - SSI_SDATA8_GMARK, - SSI_SDATA7_GMARK, - SSI_WS78_GMARK, - SSI_SCK78_GMARK, - SSI_SDATA6_GMARK, - SSI_WS6_GMARK, - SSI_SCK6_GMARK, - SSI_SDATA5_MARK, - SSI_WS5_MARK, - SSI_SCK5_MARK, - SSI_SDATA4_GMARK, - SSI_WS4_GMARK, - SSI_SCK4_GMARK, - SSI_SDATA3_GMARK, - SSI_WS34_GMARK, - SSI_SCK34_GMARK, - SSI_SDATA2_A_GMARK, - SSI_SDATA1_A_GMARK, - SSI_SDATA0_GMARK, - SSI_WS01239_GMARK, - SSI_SCK01239_GMARK, - - /* GPSR7 */ - HDMI1_CEC_MARK, - HDMI0_CEC_MARK, - AVS2_MARK, - AVS1_MARK, - - /* IPSR0 */ - AVB_MDC_IMARK, - MSIOF2_SS2_C_MARK, - AVB_MAGIC_IMARK, - MSIOF2_SS1_C_MARK, - SCK4_A_MARK, - AVB_PHY_INT_IMARK, - MSIOF2_SYNC_C_MARK, - RX4_A_MARK, - AVB_LINK_IMARK, - MSIOF2_SCK_C_MARK, - TX4_A_MARK, - AVB_AVTP_MATCH_A_IMARK, - MSIOF2_RXD_C_MARK, - CTS4x_A_MARK, - AVB_AVTP_CAPTURE_A_IMARK, - MSIOF2_TXD_C_MARK, - RTS4x_TANS_A_MARK, - IRQ0_IMARK, - QPOLB_MARK, - DU_CDE_MARK, - VI4_DATA0_B_MARK, - CAN0_TX_B_MARK, - CANFD0_TX_B_MARK, - MSIOF3_SS2_E_MARK, - IRQ1_IMARK, - QPOLA_MARK, - DU_DISP_MARK, - VI4_DATA1_B_MARK, - CAN0_RX_B_MARK, - CANFD0_RX_B_MARK, - MSIOF3_SS1_E_MARK, - - /* IPSR1 */ - IRQ2_IMARK, - QCPV_QDE_MARK, - DU_EXODDF_DU_ODDF_DISP_CDE_MARK, - VI4_DATA2_B_MARK, - MSIOF3_SYNC_E_MARK, - PWM3_B_MARK, - IRQ3_IMARK, - QSTVB_QVE_MARK, - DU_DOTCLKOUT1_MARK, - VI4_DATA3_B_MARK, - MSIOF3_SCK_E_MARK, - PWM4_B_MARK, - IRQ4_IMARK, - QSTH_QHS_MARK, - DU_EXHSYNC_DU_HSYNC_MARK, - VI4_DATA4_B_MARK, - MSIOF3_RXD_E_MARK, - PWM5_B_MARK, - IRQ5_IMARK, - QSTB_QHE_MARK, - DU_EXVSYNC_DU_VSYNC_MARK, - VI4_DATA5_B_MARK, - MSIOF3_TXD_E_MARK, - PWM6_B_MARK, - PWM0_IMARK, - AVB_AVTP_PPS_MARK, - VI4_DATA6_B_MARK, - IECLK_B_MARK, - PWM1_A_IMARK, - HRX3_D_MARK, - VI4_DATA7_B_MARK, - IERX_B_MARK, - PWM2_A_IMARK, - PWMFSW0_MARK, - HTX3_D_MARK, - IETX_B_MARK, - A0_IMARK, - LCDOUT16_MARK, - MSIOF3_SYNC_B_MARK, - VI4_DATA8_MARK, - DU_DB0_MARK, - PWM3_A_MARK, - - /* IPSR2 */ - A1_IMARK, - LCDOUT17_MARK, - MSIOF3_TXD_B_MARK, - VI4_DATA9_MARK, - DU_DB1_MARK, - PWM4_A_MARK, - A2_IMARK, - LCDOUT18_MARK, - MSIOF3_SCK_B_MARK, - VI4_DATA10_MARK, - DU_DB2_MARK, - PWM5_A_MARK, - A3_IMARK, - LCDOUT19_MARK, - MSIOF3_RXD_B_MARK, - VI4_DATA11_MARK, - DU_DB3_MARK, - PWM6_A_MARK, - A4_IMARK, - LCDOUT20_MARK, - MSIOF3_SS1_B_MARK, - VI4_DATA12_MARK, - VI5_DATA12_MARK, - DU_DB4_MARK, - A5_IMARK, - LCDOUT21_MARK, - MSIOF3_SS2_B_MARK, - SCK4_B_MARK, - VI4_DATA13_MARK, - VI5_DATA13_MARK, - DU_DB5_MARK, - A6_IMARK, - LCDOUT22_MARK, - MSIOF2_SS1_A_MARK, - RX4_B_MARK, - VI4_DATA14_MARK, - VI5_DATA14_MARK, - DU_DB6_MARK, - A7_IMARK, - LCDOUT23_MARK, - MSIOF2_SS2_A_MARK, - TX4_B_MARK, - VI4_DATA15_MARK, - V15_DATA15_MARK, - DU_DB7_MARK, - A8_IMARK, - RX3_B_MARK, - MSIOF2_SYNC_A_MARK, - HRX4_B_MARK, - SDA6_A_MARK, - AVB_AVTP_MATCH_B_MARK, - PWM1_B_MARK, - - /* IPSR3 */ - A9_IMARK, - MSIOF2_SCK_A_MARK, - CTS4x_B_MARK, - VI5_VSYNCx_MARK, - A10_IMARK, - MSIOF2_RXD_A_MARK, - RTS4n_TANS_B_MARK, - VI5_HSYNCx_MARK, - A11_IMARK, - TX3_B_MARK, - MSIOF2_TXD_A_MARK, - HTX4_B_MARK, - HSCK4_MARK, - VI5_FIELD_MARK, - SCL6_A_MARK, - AVB_AVTP_CAPTURE_B_MARK, - PWM2_B_MARK, - SPV_EVEN_MARK, - A12_IMARK, - LCDOUT12_MARK, - MSIOF3_SCK_C_MARK, - HRX4_A_MARK, - VI5_DATA8_MARK, - DU_DG4_MARK, - A13_IMARK, - LCDOUT13_MARK, - MSIOF3_SYNC_C_MARK, - HTX4_A_MARK, - VI5_DATA9_MARK, - DU_DG5_MARK, - A14_IMARK, - LCDOUT14_MARK, - MSIOF3_RXD_C_MARK, - HCTS4x_MARK, - VI5_DATA10_MARK, - DU_DG6_MARK, - A15_IMARK, - LCDOUT15_MARK, - MSIOF3_TXD_C_MARK, - HRTS4x_MARK, - VI5_DATA11_MARK, - DU_DG7_MARK, - A16_IMARK, - LCDOUT8_MARK, - VI4_FIELD_MARK, - DU_DG0_MARK, - - /* IPSR4 */ - A17_IMARK, - LCDOUT9_MARK, - VI4_VSYNCx_MARK, - DU_DG1_MARK, - A18_IMARK, - LCDOUT10_MARK, - VI4_HSYNCx_MARK, - DU_DG2_MARK, - A19_IMARK, - LCDOUT11_MARK, - VI4_CLKENB_MARK, - DU_DG3_MARK, - CS0x_IMARK, - VI5_CLKENB_MARK, - CS1x_A26_IMARK, - VI5_CLK_MARK, - EX_WAIT0_B_MARK, - BSx_IMARK, - QSTVA_QVS_MARK, - MSIOF3_SCK_D_MARK, - SCK3_MARK, - HSCK3_MARK, - CAN1_TX_MARK, - CANFD1_TX_MARK, - IETX_A_MARK, - RDx_IMARK, - MSIOF3_SYNC_D_MARK, - RX3_A_MARK, - HRX3_A_MARK, - CAN0_TX_A_MARK, - CANFD0_TX_A_MARK, - RD_WRx_IMARK, - MSIOF3_RXD_D_MARK, - TX3_A_MARK, - HTX3_A_MARK, - CAN0_RX_A_MARK, - CANFD0_RX_A_MARK, - - /* IPSR5 */ - WE0x_IMARK, - MSIIOF3_TXD_D_MARK, - CTS3x_MARK, - HCTS3x_MARK, - SCL6_B_MARK, - CAN_CLK_MARK, - IECLK_A_MARK, - WE1x_IMARK, - MSIOF3_SS1_D_MARK, - RTS3x_TANS_MARK, - HRTS3x_MARK, - SDA6_B_MARK, - CAN1_RX_MARK, - CANFD1_RX_MARK, - IERX_A_MARK, - EX_WAIT0_A_IMARK, - QCLK_MARK, - VI4_CLK_MARK, - DU_DOTCLKOUT0_MARK, - D0_IMARK, - MSIOF2_SS1_B_MARK, - MSIOF3_SCK_A_MARK, - VI4_DATA16_MARK, - VI5_DATA0_MARK, - D1_IMARK, - MSIOF2_SS2_B_MARK, - MSIOF3_SYNC_A_MARK, - VI4_DATA17_MARK, - VI5_DATA1_MARK, - D2_IMARK, - MSIOF3_RXD_A_MARK, - VI4_DATA18_MARK, - VI5_DATA2_MARK, - D3_IMARK, - MSIOF3_TXD_A_MARK, - VI4_DATA19_MARK, - VI5_DATA3_MARK, - D4_IMARK, - MSIOF2_SCK_B_MARK, - VI4_DATA20_MARK, - VI5_DATA4_MARK, - - /* IPSR6 */ - D5_IMARK, - MSIOF2_SYNC_B_MARK, - VI4_DATA21_MARK, - VI5_DATA5_MARK, - D6_IMARK, - MSIOF2_RXD_B_MARK, - VI4_DATA22_MARK, - VI5_DATA6_MARK, - D7_IMARK, - MSIOF2_TXD_B_MARK, - VI4_DATA23_MARK, - VI5_DATA7_MARK, - D8_IMARK, - LCDOUT0_MARK, - MSIOF2_SCK_D_MARK, - SCK4_C_MARK, - VI4_DATA0_A_MARK, - DU_DR0_MARK, - D9_IMARK, - LCDOUT1_MARK, - MSIOF2_SYNC_D_MARK, - VI4_DATA1_A_MARK, - DU_DR1_MARK, - D10_IMARK, - LCDOUT2_MARK, - MSIOF2_RXD_D_MARK, - HRX3_B_MARK, - VI4_DATA2_A_MARK, - CTS4x_C_MARK, - DU_DR2_MARK, - D11_IMARK, - LCDOUT3_MARK, - MSIOF2_TXD_D_MARK, - HTX3_B_MARK, - VI4_DATA3_A_MARK, - RTS4x_TANS_C_MARK, - DU_DR3_MARK, - D12_IMARK, - LCDOUT4_MARK, - MSIOF2_SS1_D_MARK, - RX4_C_MARK, - VI4_DATA4_A_MARK, - DU_DR4_MARK, - - /* IPSR7 */ - D13_IMARK, - LCDOUT5_MARK, - MSIOF2_SS2_D_MARK, - TX4_C_MARK, - VI4_DATA5_A_MARK, - DU_DR5_MARK, - D14_IMARK, - LCDOUT6_MARK, - MSIOF3_SS1_A_MARK, - HRX3_C_MARK, - VI4_DATA6_A_MARK, - DU_DR6_MARK, - SCL6_C_MARK, - D15_IMARK, - LCDOUT7_MARK, - MSIOF3_SS2_A_MARK, - HTX3_C_MARK, - VI4_DATA7_A_MARK, - DU_DR7_MARK, - SDA6_C_MARK, - FSCLKST_MARK, - SD0_CLK_IMARK, - MSIOF1_SCK_E_MARK, - STP_OPWM_0_B_MARK, - SD0_CMD_IMARK, - MSIOF1_SYNC_E_MARK, - STP_IVCXO27_0_B_MARK, - SD0_DAT0_IMARK, - MSIOF1_RXD_E_MARK, - TS_SCK0_B_MARK, - STP_ISCLK_0_B_MARK, - SD0_DAT1_IMARK, - MSIOF1_TXD_E_MARK, - TS_SPSYNC0_B_MARK, - STP_ISSYNC_0_B_MARK, - - /* IPSR8 */ - SD0_DAT2_IMARK, - MSIOF1_SS1_E_MARK, - TS_SDAT0_B_MARK, - STP_ISD_0_B_MARK, - - SD0_DAT3_IMARK, - MSIOF1_SS2_E_MARK, - TS_SDEN0_B_MARK, - STP_ISEN_0_B_MARK, - - SD1_CLK_IMARK, - MSIOF1_SCK_G_MARK, - SIM0_CLK_A_MARK, - - SD1_CMD_IMARK, - MSIOF1_SYNC_G_MARK, - NFCEx_B_MARK, - SIM0_D_A_MARK, - STP_IVCXO27_1_B_MARK, - - SD1_DAT0_IMARK, - SD2_DAT4_MARK, - MSIOF1_RXD_G_MARK, - NFWPx_B_MARK, - TS_SCK1_B_MARK, - STP_ISCLK_1_B_MARK, - - SD1_DAT1_IMARK, - SD2_DAT5_MARK, - MSIOF1_TXD_G_MARK, - NFDATA14_B_MARK, - TS_SPSYNC1_B_MARK, - STP_ISSYNC_1_B_MARK, - - SD1_DAT2_IMARK, - SD2_DAT6_MARK, - MSIOF1_SS1_G_MARK, - NFDATA15_B_MARK, - TS_SDAT1_B_MARK, - STP_IOD_1_B_MARK, - - SD1_DAT3_IMARK, - SD2_DAT7_MARK, - MSIOF1_SS2_G_MARK, - NFRBx_B_MARK, - TS_SDEN1_B_MARK, - STP_ISEN_1_B_MARK, - - /* IPSR9 */ - SD2_CLK_IMARK, - NFDATA8_MARK, - - SD2_CMD_IMARK, - NFDATA9_MARK, - - SD2_DAT0_IMARK, - NFDATA10_MARK, - - SD2_DAT1_IMARK, - NFDATA11_MARK, - - SD2_DAT2_IMARK, - NFDATA12_MARK, - - SD2_DAT3_IMARK, - NFDATA13_MARK, - - SD2_DS_IMARK, - NFALE_MARK, - - SD3_CLK_IMARK, - NFWEx_MARK, - - /* IPSR10 */ - SD3_CMD_IMARK, - NFREx_MARK, - - SD3_DAT0_IMARK, - NFDATA0_MARK, - - SD3_DAT1_IMARK, - NFDATA1_MARK, - - SD3_DAT2_IMARK, - NFDATA2_MARK, - - SD3_DAT3_IMARK, - NFDATA3_MARK, - - SD3_DAT4_IMARK, - SD2_CD_A_MARK, - NFDATA4_MARK, - - SD3_DAT5_IMARK, - SD2_WP_A_MARK, - NFDATA5_MARK, - - SD3_DAT6_IMARK, - SD3_CD_MARK, - NFDATA6_MARK, - - /* IPSR11 */ - SD3_DAT7_IMARK, - SD3_WP_MARK, - NFDATA7_MARK, - - SD3_DS_IMARK, - NFCLE_MARK, - - SD0_CD_IMARK, - NFDATA14_A_MARK, - SCL2_B_MARK, - SIM0_RST_A_MARK, - - SD0_WP_IMARK, - NFDATA15_A_MARK, - SDA2_B_MARK, - - SD1_CD_IMARK, - NFRBx_A_MARK, - SIM0_CLK_B_MARK, - - SD1_WP_IMARK, - NFCEx_A_MARK, - SIM0_D_B_MARK, - - SCK0_IMARK, - HSCK1_B_MARK, - MSIOF1_SS2_B_MARK, - AUDIO_CLKC_B_MARK, - SDA2_A_MARK, - SIM0_RST_B_MARK, - STP_OPWM_0_C_MARK, - RIF0_CLK_B_MARK, - ADICHS2_MARK, - SCK5_B_MARK, - - RX0_IMARK, - HRX1_B_MARK, - TS_SCK0_C_MARK, - STP_ISCLK_0_C_MARK, - RIF0_D0_B_MARK, - - /* IPSR12 */ - TX0_IMARK, - HTX1_B_MARK, - TS_SPSYNC0_C_MARK, - STP_ISSYNC_0_C_MARK, - RIF0_D1_B_MARK, - - CTS0x_IMARK, - HCTS1x_B_MARK, - MSIOF1_SYNC_B_MARK, - TS_SPSYNC1_C_MARK, - STP_ISSYNC_1_C_MARK, - RIF1_SYNC_B_MARK, - AUDIO_CLKOUT_C_MARK, - ADICS_SAMP_MARK, - - RTS0x_TANS_IMARK, - HRTS1x_B_MARK, - MSIOF1_SS1_B_MARK, - AUDIO_CLKA_B_MARK, - SCL2_A_MARK, - STP_IVCXO27_1_C_MARK, - RIF0_SYNC_B_MARK, - ADICHS1_MARK, - - RX1_A_IMARK, - HRX1_A_MARK, - TS_SDAT0_C_MARK, - STP_ISD_0_C_MARK, - RIF1_CLK_C_MARK, - - TX1_A_IMARK, - HTX1_A_MARK, - TS_SDEN0_C_MARK, - STP_ISEN_0_C_MARK, - RIF1_D0_C_MARK, - - CTS1x_IMARK, - HCTS1x_A_MARK, - MSIOF1_RXD_B_MARK, - TS_SDEN1_C_MARK, - STP_ISEN_1_C_MARK, - RIF1_D0_B_MARK, - ADIDATA_MARK, - - RTS1x_TANS_IMARK, - HRTS1x_A_MARK, - MSIOF1_TXD_B_MARK, - TS_SDAT1_C_MARK, - STP_ISD_1_C_MARK, - RIF1_D1_B_MARK, - ADICHS0_MARK, - - SCK2_IMARK, - SCIF_CLK_B_MARK, - MSIOF1_SCK_B_MARK, - TS_SCK1_C_MARK, - STP_ISCLK_1_C_MARK, - RIF1_CLK_B_MARK, - ADICLK_MARK, - - /* IPSR13 */ - TX2_A_IMARK, - SD2_CD_B_MARK, - SCL1_A_MARK, - FMCLK_A_MARK, - RIF1_D1_C_MARK, - FSO_CFE_0_B_MARK, - - RX2_A_IMARK, - SD2_WP_B_MARK, - SDA1_A_MARK, - FMIN_A_MARK, - RIF1_SYNC_C_MARK, - FSO_CEF_1_B_MARK, - - HSCK0_IMARK, - MSIOF1_SCK_D_MARK, - AUDIO_CLKB_A_MARK, - SSI_SDATA1_B_MARK, - TS_SCK0_D_MARK, - STP_ISCLK_0_D_MARK, - RIF0_CLK_C_MARK, - RX5_B_MARK, - - HRX0_IMARK, - MSIOF1_RXD_D_MARK, - SS1_SDATA2_B_MARK, - TS_SDEN0_D_MARK, - STP_ISEN_0_D_MARK, - RIF0_D0_C_MARK, - - HTX0_IMARK, - MSIOF1_TXD_D_MARK, - SSI_SDATA9_B_MARK, - TS_SDAT0_D_MARK, - STP_ISD_0_D_MARK, - RIF0_D1_C_MARK, - - HCTS0x_IMARK, - RX2_B_MARK, - MSIOF1_SYNC_D_MARK, - SSI_SCK9_A_MARK, - TS_SPSYNC0_D_MARK, - STP_ISSYNC_0_D_MARK, - RIF0_SYNC_C_MARK, - AUDIO_CLKOUT1_A_MARK, - - HRTS0x_IMARK, - TX2_B_MARK, - MSIOF1_SS1_D_MARK, - SSI_WS9_A_MARK, - STP_IVCXO27_0_D_MARK, - BPFCLK_A_MARK, - AUDIO_CLKOUT2_A_MARK, - - MSIOF0_SYNC_IMARK, - AUDIO_CLKOUT_A_MARK, - TX5_B_MARK, - BPFCLK_D_MARK, - - /* IPSR14 */ - MSIOF0_SS1_IMARK, - RX5_A_MARK, - NFWPx_A_MARK, - AUDIO_CLKA_C_MARK, - SSI_SCK2_A_MARK, - STP_IVCXO27_0_C_MARK, - AUDIO_CLKOUT3_A_MARK, - TCLK1_B_MARK, - - MSIOF0_SS2_IMARK, - TX5_A_MARK, - MSIOF1_SS2_D_MARK, - AUDIO_CLKC_A_MARK, - SSI_WS2_A_MARK, - STP_OPWM_0_D_MARK, - AUDIO_CLKOUT_D_MARK, - SPEEDIN_B_MARK, - - MLB_CLK_IMARK, - MSIOF1_SCK_F_MARK, - SCL1_B_MARK, - - MLB_SIG_IMARK, - RX1_B_MARK, - MSIOF1_SYNC_F_MARK, - SDA1_B_MARK, - - MLB_DAT_IMARK, - TX1_B_MARK, - MSIOF1_RXD_F_MARK, - - SSI_SCK0129_IMARK, - MSIOF1_TXD_F_MARK, - MOUT0_MARK, - - SSI_WS0129_IMARK, - MSIOF1_SS1_F_MARK, - MOUT1_MARK, - - SSI_SDATA0_IMARK, - MSIOF1_SS2_F_MARK, - MOUT2_MARK, - - /* IPSR15 */ - SSI_SDATA1_A_IMARK, - MOUT5_MARK, - - SSI_SDATA2_A_IMARK, - SSI_SCK1_B_MARK, - MOUT6_MARK, - - SSI_SCK34_IMARK, - MSIOF1_SS1_A_MARK, - STP_OPWM_0_A_MARK, - - SSI_WS34_IMARK, - HCTS2x_A_MARK, - MSIOF1_SS2_A_MARK, - STP_IVCXO27_0_A_MARK, - - SSI_SDATA3_IMARK, - HRTS2x_A_MARK, - MSIOF1_TXD_A_MARK, - TS_SCK0_A_MARK, - STP_ISCLK_0_A_MARK, - RIF0_D1_A_MARK, - RIF2_D0_A_MARK, - - SSI_SCK4_IMARK, - HRX2_A_MARK, - MSIOF1_SCK_A_MARK, - TS_SDAT0_A_MARK, - STP_ISD_0_A_MARK, - RIF0_CLK_A_MARK, - RIF2_CLK_A_MARK, - - SSI_WS4_IMARK, - HTX2_A_MARK, - MSIOF1_SYNC_A_MARK, - TS_SDEN0_A_MARK, - STP_ISEN_0_A_MARK, - RIF0_SYNC_A_MARK, - RIF2_SYNC_A_MARK, - - SSI_SDATA4_IMARK, - HSCK2_A_MARK, - MSIOF1_RXD_A_MARK, - TS_SPSYNC0_A_MARK, - STP_ISSYNC_0_A_MARK, - RIF0_D0_A_MARK, - RIF2_D1_A_MARK, - - /* IPSR16 */ - SSI_SCK6_IMARK, - SIM0_RST_D_MARK, - FSO_TOE_A_MARK, - - SSI_WS6_IMARK, - SIM0_D_D_MARK, - - SSI_SDATA6_IMARK, - SIM0_CLK_D_MARK, - - SSI_SCK78_IMARK, - HRX2_B_MARK, - MSIOF1_SCK_C_MARK, - TS_SCK1_A_MARK, - STP_ISCLK_1_A_MARK, - RIF1_CLK_A_MARK, - RIF3_CLK_A_MARK, - - SSI_WS78_IMARK, - HTX2_B_MARK, - MSIOF1_SYNC_C_MARK, - TS_SDAT1_A_MARK, - STP_ISD_1_A_MARK, - RIF1_SYNC_A_MARK, - RIF3_SYNC_A_MARK, - - SSI_SDATA7_IMARK, - HCTS2x_B_MARK, - MSIOF1_RXD_C_MARK, - TS_SDEN1_A_MARK, - STP_IEN_1_A_MARK, - RIF1_D0_A_MARK, - RIF3_D0_A_MARK, - TCLK2_A_MARK, - - SSI_SDATA8_IMARK, - HRTS2x_B_MARK, - MSIOF1_TXD_C_MARK, - TS_SPSYNC1_A_MARK, - STP_ISSYNC_1_A_MARK, - RIF1_D1_A_MARK, - EIF3_D1_A_MARK, - - SSI_SDATA9_A_IMARK, - HSCK2_B_MARK, - MSIOF1_SS1_C_MARK, - HSCK1_A_MARK, - SSI_WS1_B_MARK, - SCK1_MARK, - STP_IVCXO27_1_A_MARK, - SCK5_MARK, - - /* IPSR17 */ - AUDIO_CLKA_A_IMARK, - CC5_OSCOUT_MARK, - - AUDIO_CLKB_B_IMARK, - SCIF_CLK_A_MARK, - STP_IVCXO27_1_D_MARK, - REMOCON_A_MARK, - TCLK1_A_MARK, - - USB0_PWEN_IMARK, - SIM0_RST_C_MARK, - TS_SCK1_D_MARK, - STP_ISCLK_1_D_MARK, - BPFCLK_B_MARK, - RIF3_CLK_B_MARK, - FSO_CFE_1_A_MARK, - HSCK2_C_MARK, - - USB0_OVC_IMARK, - SIM0_D_C_MARK, - TS_SDAT1_D_MARK, - STP_ISD_1_D_MARK, - RIF3_SYNC_B_MARK, - HRX2_C_MARK, - - USB1_PWEN_IMARK, - SIM0_CLK_C_MARK, - SSI_SCK1_A_MARK, - TS_SCK0_E_MARK, - STP_ISCLK_0_E_MARK, - FMCLK_B_MARK, - RIF2_CLK_B_MARK, - SPEEDIN_A_MARK, - HTX2_C_MARK, - - USB1_OVC_IMARK, - MSIOF1_SS2_C_MARK, - SSI_WS1_A_MARK, - TS_SDAT0_E_MARK, - STP_ISD_0_E_MARK, - FMIN_B_MARK, - RIF2_SYNC_B_MARK, - REMOCON_B_MARK, - HCTS2x_C_MARK, - - USB30_PWEN_IMARK, - AUDIO_CLKOUT_B_MARK, - SSI_SCK2_B_MARK, - TS_SDEN1_D_MARK, - STP_ISEN_1_D_MARK, - STP_OPWM_0_E_MARK, - RIF3_D0_B_MARK, - TCLK2_B_MARK, - TPU0TO0_MARK, - BPFCLK_C_MARK, - HRTS2x_C_MARK, - - USB30_OVC_IMARK, - AUDIO_CLKOUT1_B_MARK, - SSI_WS2_B_MARK, - TS_SPSYNC1_D_MARK, - STP_ISSYNC_1_D_MARK, - STP_IVCXO27_0_E_MARK, - RIF3_D1_B_MARK, - FSO_TOE_B_MARK, - TPU0TO1_MARK, - - /* IPSR18 */ - GP6_30_IMARK, - AUDIO_CLKOUT2_B_MARK, - SSI_SCK9_B_MARK, - TS_SDEN0_E_MARK, - STP_ISEN_0_E_MARK, - RIF2_D0_B_MARK, - FSO_CFE_0_A_MARK, - TPU0TO2_MARK, - FMCLK_C_MARK, - FMCLK_D_MARK, - - GP6_31_IMARK, - AUDIO_CLKOUT3_B_MARK, - SSI_WS9_B_MARK, - TS_SPSYNC0_E_MARK, - STP_ISSYNC_0_E_MARK, - RIF2_D1_B_MARK, - TPU0TO3_MARK, - FMIN_C_MARK, - FMIN_D_MARK, - - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - - /* GPSR0 */ - PINMUX_DATA(D15_GMARK, GFN_D15), - PINMUX_DATA(D14_GMARK, GFN_D14), - PINMUX_DATA(D13_GMARK, GFN_D13), - PINMUX_DATA(D12_GMARK, GFN_D12), - PINMUX_DATA(D11_GMARK, GFN_D11), - PINMUX_DATA(D10_GMARK, GFN_D10), - PINMUX_DATA(D9_GMARK, GFN_D9), - PINMUX_DATA(D8_GMARK, GFN_D8), - PINMUX_DATA(D7_GMARK, GFN_D7), - PINMUX_DATA(D6_GMARK, GFN_D6), - PINMUX_DATA(D5_GMARK, GFN_D5), - PINMUX_DATA(D4_GMARK, GFN_D4), - PINMUX_DATA(D3_GMARK, GFN_D3), - PINMUX_DATA(D2_GMARK, GFN_D2), - PINMUX_DATA(D1_GMARK, GFN_D1), - PINMUX_DATA(D0_GMARK, GFN_D0), - - /* GPSR1 */ - PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT), - PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A), - PINMUX_DATA(WE1x_GMARK, GFN_WE1x), - PINMUX_DATA(WE0x_GMARK, GFN_WE0x), - PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx), - PINMUX_DATA(RDx_GMARK, GFN_RDx), - PINMUX_DATA(BSx_GMARK, GFN_BSx), - PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26), - PINMUX_DATA(CS0x_GMARK, GFN_CS0x), - PINMUX_DATA(A19_GMARK, GFN_A19), - PINMUX_DATA(A18_GMARK, GFN_A18), - PINMUX_DATA(A17_GMARK, GFN_A17), - PINMUX_DATA(A16_GMARK, GFN_A16), - PINMUX_DATA(A15_GMARK, GFN_A15), - PINMUX_DATA(A14_GMARK, GFN_A14), - PINMUX_DATA(A13_GMARK, GFN_A13), - PINMUX_DATA(A12_GMARK, GFN_A12), - PINMUX_DATA(A11_GMARK, GFN_A11), - PINMUX_DATA(A10_GMARK, GFN_A10), - PINMUX_DATA(A9_GMARK, GFN_A9), - PINMUX_DATA(A8_GMARK, GFN_A8), - PINMUX_DATA(A7_GMARK, GFN_A7), - PINMUX_DATA(A6_GMARK, GFN_A6), - PINMUX_DATA(A5_GMARK, GFN_A5), - PINMUX_DATA(A4_GMARK, GFN_A4), - PINMUX_DATA(A3_GMARK, GFN_A3), - PINMUX_DATA(A2_GMARK, GFN_A2), - PINMUX_DATA(A1_GMARK, GFN_A1), - PINMUX_DATA(A0_GMARK, GFN_A0), - - /* GPSR2 */ - PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A), - PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A), - PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK), - PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT), - PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC), - PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC), - PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A), - PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A), - PINMUX_DATA(PWM0_GMARK, GFN_PWM0), - PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5), - PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4), - PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3), - PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2), - PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1), - PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), - - /* GPSR3 */ - PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP), - PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD), - PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP), - PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD), - PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3), - PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2), - PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1), - PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0), - PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD), - PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK), - PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3), - PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2), - PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1), - PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0), - PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD), - PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK), - - /* GPSR4 */ - PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS), - PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7), - PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6), - PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5), - PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4), - PINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3), - PINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2), - PINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1), - PINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0), - PINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD), - PINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK), - PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS), - PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3), - PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2), - PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1), - PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0), - PINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD), - PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK), - - /* GPSR5 */ - PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT), - PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG), - PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK), - PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD), - PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2), - PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD), - PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1), - PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC), - PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK), - PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x), - PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x), - PINMUX_DATA(HTX0_GMARK, GFN_HTX0), - PINMUX_DATA(HRX0_GMARK, GFN_HRX0), - PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0), - PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A), - PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A), - PINMUX_DATA(SCK2_GMARK, GFN_SCK2), - PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS), - PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x), - PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A), - PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A), - PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS), - PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x), - PINMUX_DATA(TX0_GMARK, GFN_TX0), - PINMUX_DATA(RX0_GMARK, GFN_RX0), - PINMUX_DATA(SCK0_GMARK, GFN_SCK0), - - /* GPSR6 */ - PINMUX_DATA(GP6_30_GMARK, GFN_GP6_30), - PINMUX_DATA(GP6_31_GMARK, GFN_GP6_31), - PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC), - PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN), - PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC), - PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN), - PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC), - PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN), - PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B), - PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A), - PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A), - PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8), - PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7), - PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78), - PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78), - PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6), - PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6), - PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6), - PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5), - PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5), - PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5), - PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4), - PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4), - PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4), - PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3), - PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34), - PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34), - PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A), - PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A), - PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0), - PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239), - PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239), - - /* GPSR7 */ - PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC), - PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC), - PINMUX_DATA(AVS2_MARK, FN_AVS2), - PINMUX_DATA(AVS1_MARK, FN_AVS1), - - /* ipsr setting .. underconstruction */ -}; - -static struct pinmux_gpio pinmux_gpios[] = { - PINMUX_GPIO_GP_ALL(), - /* GPSR0 */ - GPIO_GFN(D15), - GPIO_GFN(D14), - GPIO_GFN(D13), - GPIO_GFN(D12), - GPIO_GFN(D11), - GPIO_GFN(D10), - GPIO_GFN(D9), - GPIO_GFN(D8), - GPIO_GFN(D7), - GPIO_GFN(D6), - GPIO_GFN(D5), - GPIO_GFN(D4), - GPIO_GFN(D3), - GPIO_GFN(D2), - GPIO_GFN(D1), - GPIO_GFN(D0), - /* GPSR1 */ - GPIO_GFN(CLKOUT), - GPIO_GFN(EX_WAIT0_A), - GPIO_GFN(WE1x), - GPIO_GFN(WE0x), - GPIO_GFN(RD_WRx), - GPIO_GFN(RDx), - GPIO_GFN(BSx), - GPIO_GFN(CS1x_A26), - GPIO_GFN(CS0x), - GPIO_GFN(A19), - GPIO_GFN(A18), - GPIO_GFN(A17), - GPIO_GFN(A16), - GPIO_GFN(A15), - GPIO_GFN(A14), - GPIO_GFN(A13), - GPIO_GFN(A12), - GPIO_GFN(A11), - GPIO_GFN(A10), - GPIO_GFN(A9), - GPIO_GFN(A8), - GPIO_GFN(A7), - GPIO_GFN(A6), - GPIO_GFN(A5), - GPIO_GFN(A4), - GPIO_GFN(A3), - GPIO_GFN(A2), - GPIO_GFN(A1), - GPIO_GFN(A0), - - /* GPSR2 */ - GPIO_GFN(AVB_AVTP_CAPTURE_A), - GPIO_GFN(AVB_AVTP_MATCH_A), - GPIO_GFN(AVB_LINK), - GPIO_GFN(AVB_PHY_INT), - GPIO_GFN(AVB_MAGIC), - GPIO_GFN(AVB_MDC), - GPIO_GFN(PWM2_A), - GPIO_GFN(PWM1_A), - GPIO_GFN(PWM0), - GPIO_GFN(IRQ5), - GPIO_GFN(IRQ4), - GPIO_GFN(IRQ3), - GPIO_GFN(IRQ2), - GPIO_GFN(IRQ1), - GPIO_GFN(IRQ0), - - /* GPSR3 */ - GPIO_GFN(SD1_WP), - GPIO_GFN(SD1_CD), - GPIO_GFN(SD0_WP), - GPIO_GFN(SD0_CD), - GPIO_GFN(SD1_DAT3), - GPIO_GFN(SD1_DAT2), - GPIO_GFN(SD1_DAT1), - GPIO_GFN(SD1_DAT0), - GPIO_GFN(SD1_CMD), - GPIO_GFN(SD1_CLK), - GPIO_GFN(SD0_DAT3), - GPIO_GFN(SD0_DAT2), - GPIO_GFN(SD0_DAT1), - GPIO_GFN(SD0_DAT0), - GPIO_GFN(SD0_CMD), - GPIO_GFN(SD0_CLK), - - /* GPSR4 */ - GPIO_GFN(SD3_DS), - GPIO_GFN(SD3_DAT7), - GPIO_GFN(SD3_DAT6), - GPIO_GFN(SD3_DAT5), - GPIO_GFN(SD3_DAT4), - GPIO_FN(SD3_DAT3), - GPIO_FN(SD3_DAT2), - GPIO_FN(SD3_DAT1), - GPIO_FN(SD3_DAT0), - GPIO_FN(SD3_CMD), - GPIO_FN(SD3_CLK), - GPIO_GFN(SD2_DS), - GPIO_GFN(SD2_DAT3), - GPIO_GFN(SD2_DAT2), - GPIO_GFN(SD2_DAT1), - GPIO_GFN(SD2_DAT0), - GPIO_FN(SD2_CMD), - GPIO_GFN(SD2_CLK), - - /* GPSR5 */ - GPIO_GFN(MLB_DAT), - GPIO_GFN(MLB_SIG), - GPIO_GFN(MLB_CLK), - GPIO_FN(MSIOF0_RXD), - GPIO_GFN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - GPIO_GFN(MSIOF0_SS1), - GPIO_GFN(MSIOF0_SYNC), - GPIO_FN(MSIOF0_SCK), - GPIO_GFN(HRTS0x), - GPIO_GFN(HCTS0x), - GPIO_GFN(HTX0), - GPIO_GFN(HRX0), - GPIO_GFN(HSCK0), - GPIO_GFN(RX2_A), - GPIO_GFN(TX2_A), - GPIO_GFN(SCK2), - GPIO_GFN(RTS1x_TANS), - GPIO_GFN(CTS1x), - GPIO_GFN(TX1_A), - GPIO_GFN(RX1_A), - GPIO_GFN(RTS0x_TANS), - GPIO_GFN(CTS0x), - GPIO_GFN(TX0), - GPIO_GFN(RX0), - GPIO_GFN(SCK0), - - /* GPSR6 */ - GPIO_GFN(GP6_30), - GPIO_GFN(GP6_31), - GPIO_GFN(USB30_OVC), - GPIO_GFN(USB30_PWEN), - GPIO_GFN(USB1_OVC), - GPIO_GFN(USB1_PWEN), - GPIO_GFN(USB0_OVC), - GPIO_GFN(USB0_PWEN), - GPIO_GFN(AUDIO_CLKB_B), - GPIO_GFN(AUDIO_CLKA_A), - GPIO_GFN(SSI_SDATA9_A), - GPIO_GFN(SSI_SDATA8), - GPIO_GFN(SSI_SDATA7), - GPIO_GFN(SSI_WS78), - GPIO_GFN(SSI_SCK78), - GPIO_GFN(SSI_SDATA6), - GPIO_GFN(SSI_WS6), - GPIO_GFN(SSI_SCK6), - GPIO_FN(SSI_SDATA5), - GPIO_FN(SSI_WS5), - GPIO_FN(SSI_SCK5), - GPIO_GFN(SSI_SDATA4), - GPIO_GFN(SSI_WS4), - GPIO_GFN(SSI_SCK4), - GPIO_GFN(SSI_SDATA3), - GPIO_GFN(SSI_WS34), - GPIO_GFN(SSI_SCK34), - GPIO_GFN(SSI_SDATA2_A), - GPIO_GFN(SSI_SDATA1_A), - GPIO_GFN(SSI_SDATA0), - GPIO_GFN(SSI_WS01239), - GPIO_GFN(SSI_SCK01239), - - /* GPSR7 */ - GPIO_FN(HDMI1_CEC), - GPIO_FN(HDMI0_CEC), - GPIO_FN(AVS2), - GPIO_FN(AVS1), - - /* IPSR0 */ - GPIO_IFN(AVB_MDC), - GPIO_FN(MSIOF2_SS2_C), - GPIO_IFN(AVB_MAGIC), - GPIO_FN(MSIOF2_SS1_C), - GPIO_FN(SCK4_A), - GPIO_IFN(AVB_PHY_INT), - GPIO_FN(MSIOF2_SYNC_C), - GPIO_FN(RX4_A), - GPIO_IFN(AVB_LINK), - GPIO_FN(MSIOF2_SCK_C), - GPIO_FN(TX4_A), - GPIO_IFN(AVB_AVTP_MATCH_A), - GPIO_FN(MSIOF2_RXD_C), - GPIO_FN(CTS4x_A), - GPIO_IFN(AVB_AVTP_CAPTURE_A), - GPIO_FN(MSIOF2_TXD_C), - GPIO_FN(RTS4x_TANS_A), - GPIO_IFN(IRQ0), - GPIO_FN(QPOLB), - GPIO_FN(DU_CDE), - GPIO_FN(VI4_DATA0_B), - GPIO_FN(CAN0_TX_B), - GPIO_FN(CANFD0_TX_B), - GPIO_FN(MSIOF3_SS2_E), - GPIO_IFN(IRQ1), - GPIO_FN(QPOLA), - GPIO_FN(DU_DISP), - GPIO_FN(VI4_DATA1_B), - GPIO_FN(CAN0_RX_B), - GPIO_FN(CANFD0_RX_B), - GPIO_FN(MSIOF3_SS1_E), - - /* IPSR1 */ - GPIO_IFN(IRQ2), - GPIO_FN(QCPV_QDE), - GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE), - GPIO_FN(VI4_DATA2_B), - GPIO_FN(MSIOF3_SYNC_E), - GPIO_FN(PWM3_B), - GPIO_IFN(IRQ3), - GPIO_FN(QSTVB_QVE), - GPIO_FN(DU_DOTCLKOUT1), - GPIO_FN(VI4_DATA3_B), - GPIO_FN(MSIOF3_SCK_E), - GPIO_FN(PWM4_B), - GPIO_IFN(IRQ4), - GPIO_FN(QSTH_QHS), - GPIO_FN(DU_EXHSYNC_DU_HSYNC), - GPIO_FN(VI4_DATA4_B), - GPIO_FN(MSIOF3_RXD_E), - GPIO_FN(PWM5_B), - GPIO_IFN(IRQ5), - GPIO_FN(QSTB_QHE), - GPIO_FN(DU_EXVSYNC_DU_VSYNC), - GPIO_FN(VI4_DATA5_B), - GPIO_FN(MSIOF3_TXD_E), - GPIO_FN(PWM6_B), - GPIO_IFN(PWM0), - GPIO_FN(AVB_AVTP_PPS), - GPIO_FN(VI4_DATA6_B), - GPIO_FN(IECLK_B), - GPIO_IFN(PWM1_A), - GPIO_FN(HRX3_D), - GPIO_FN(VI4_DATA7_B), - GPIO_FN(IERX_B), - GPIO_IFN(PWM2_A), - GPIO_FN(PWMFSW0), - GPIO_FN(HTX3_D), - GPIO_FN(IETX_B), - GPIO_IFN(A0), - GPIO_FN(LCDOUT16), - GPIO_FN(MSIOF3_SYNC_B), - GPIO_FN(VI4_DATA8), - GPIO_FN(DU_DB0), - GPIO_FN(PWM3_A), - - /* IPSR2 */ - GPIO_IFN(A1), - GPIO_FN(LCDOUT17), - GPIO_FN(MSIOF3_TXD_B), - GPIO_FN(VI4_DATA9), - GPIO_FN(DU_DB1), - GPIO_FN(PWM4_A), - GPIO_IFN(A2), - GPIO_FN(LCDOUT18), - GPIO_FN(MSIOF3_SCK_B), - GPIO_FN(VI4_DATA10), - GPIO_FN(DU_DB2), - GPIO_FN(PWM5_A), - GPIO_IFN(A3), - GPIO_FN(LCDOUT19), - GPIO_FN(MSIOF3_RXD_B), - GPIO_FN(VI4_DATA11), - GPIO_FN(DU_DB3), - GPIO_FN(PWM6_A), - GPIO_IFN(A4), - GPIO_FN(LCDOUT20), - GPIO_FN(MSIOF3_SS1_B), - GPIO_FN(VI4_DATA12), - GPIO_FN(VI5_DATA12), - GPIO_FN(DU_DB4), - GPIO_IFN(A5), - GPIO_FN(LCDOUT21), - GPIO_FN(MSIOF3_SS2_B), - GPIO_FN(SCK4_B), - GPIO_FN(VI4_DATA13), - GPIO_FN(VI5_DATA13), - GPIO_FN(DU_DB5), - GPIO_IFN(A6), - GPIO_FN(LCDOUT22), - GPIO_FN(MSIOF2_SS1_A), - GPIO_FN(RX4_B), - GPIO_FN(VI4_DATA14), - GPIO_FN(VI5_DATA14), - GPIO_FN(DU_DB6), - GPIO_IFN(A7), - GPIO_FN(LCDOUT23), - GPIO_FN(MSIOF2_SS2_A), - GPIO_FN(TX4_B), - GPIO_FN(VI4_DATA15), - GPIO_FN(V15_DATA15), - GPIO_FN(DU_DB7), - GPIO_IFN(A8), - GPIO_FN(RX3_B), - GPIO_FN(MSIOF2_SYNC_A), - GPIO_FN(HRX4_B), - GPIO_FN(SDA6_A), - GPIO_FN(AVB_AVTP_MATCH_B), - GPIO_FN(PWM1_B), - - /* IPSR3 */ - GPIO_IFN(A9), - GPIO_FN(MSIOF2_SCK_A), - GPIO_FN(CTS4x_B), - GPIO_FN(VI5_VSYNCx), - GPIO_IFN(A10), - GPIO_FN(MSIOF2_RXD_A), - GPIO_FN(RTS4n_TANS_B), - GPIO_FN(VI5_HSYNCx), - GPIO_IFN(A11), - GPIO_FN(TX3_B), - GPIO_FN(MSIOF2_TXD_A), - GPIO_FN(HTX4_B), - GPIO_FN(HSCK4), - GPIO_FN(VI5_FIELD), - GPIO_FN(SCL6_A), - GPIO_FN(AVB_AVTP_CAPTURE_B), - GPIO_FN(PWM2_B), - GPIO_FN(SPV_EVEN), - GPIO_IFN(A12), - GPIO_FN(LCDOUT12), - GPIO_FN(MSIOF3_SCK_C), - GPIO_FN(HRX4_A), - GPIO_FN(VI5_DATA8), - GPIO_FN(DU_DG4), - GPIO_IFN(A13), - GPIO_FN(LCDOUT13), - GPIO_FN(MSIOF3_SYNC_C), - GPIO_FN(HTX4_A), - GPIO_FN(VI5_DATA9), - GPIO_FN(DU_DG5), - GPIO_IFN(A14), - GPIO_FN(LCDOUT14), - GPIO_FN(MSIOF3_RXD_C), - GPIO_FN(HCTS4x), - GPIO_FN(VI5_DATA10), - GPIO_FN(DU_DG6), - GPIO_IFN(A15), - GPIO_FN(LCDOUT15), - GPIO_FN(MSIOF3_TXD_C), - GPIO_FN(HRTS4x), - GPIO_FN(VI5_DATA11), - GPIO_FN(DU_DG7), - GPIO_IFN(A16), - GPIO_FN(LCDOUT8), - GPIO_FN(VI4_FIELD), - GPIO_FN(DU_DG0), - - /* IPSR4 */ - GPIO_IFN(A17), - GPIO_FN(LCDOUT9), - GPIO_FN(VI4_VSYNCx), - GPIO_FN(DU_DG1), - GPIO_IFN(A18), - GPIO_FN(LCDOUT10), - GPIO_FN(VI4_HSYNCx), - GPIO_FN(DU_DG2), - GPIO_IFN(A19), - GPIO_FN(LCDOUT11), - GPIO_FN(VI4_CLKENB), - GPIO_FN(DU_DG3), - GPIO_IFN(CS0x), - GPIO_FN(VI5_CLKENB), - GPIO_IFN(CS1x_A26), - GPIO_FN(VI5_CLK), - GPIO_FN(EX_WAIT0_B), - GPIO_IFN(BSx), - GPIO_FN(QSTVA_QVS), - GPIO_FN(MSIOF3_SCK_D), - GPIO_FN(SCK3), - GPIO_FN(HSCK3), - GPIO_FN(CAN1_TX), - GPIO_FN(CANFD1_TX), - GPIO_FN(IETX_A), - GPIO_IFN(RDx), - GPIO_FN(MSIOF3_SYNC_D), - GPIO_FN(RX3_A), - GPIO_FN(HRX3_A), - GPIO_FN(CAN0_TX_A), - GPIO_FN(CANFD0_TX_A), - GPIO_IFN(RD_WRx), - GPIO_FN(MSIOF3_RXD_D), - GPIO_FN(TX3_A), - GPIO_FN(HTX3_A), - GPIO_FN(CAN0_RX_A), - GPIO_FN(CANFD0_RX_A), - - /* IPSR5 */ - GPIO_IFN(WE0x), - GPIO_FN(MSIIOF3_TXD_D), - GPIO_FN(CTS3x), - GPIO_FN(HCTS3x), - GPIO_FN(SCL6_B), - GPIO_FN(CAN_CLK), - GPIO_FN(IECLK_A), - GPIO_IFN(WE1x), - GPIO_FN(MSIOF3_SS1_D), - GPIO_FN(RTS3x_TANS), - GPIO_FN(HRTS3x), - GPIO_FN(SDA6_B), - GPIO_FN(CAN1_RX), - GPIO_FN(CANFD1_RX), - GPIO_FN(IERX_A), - GPIO_IFN(EX_WAIT0_A), - GPIO_FN(QCLK), - GPIO_FN(VI4_CLK), - GPIO_FN(DU_DOTCLKOUT0), - GPIO_IFN(D0), - GPIO_FN(MSIOF2_SS1_B), - GPIO_FN(MSIOF3_SCK_A), - GPIO_FN(VI4_DATA16), - GPIO_FN(VI5_DATA0), - GPIO_IFN(D1), - GPIO_FN(MSIOF2_SS2_B), - GPIO_FN(MSIOF3_SYNC_A), - GPIO_FN(VI4_DATA17), - GPIO_FN(VI5_DATA1), - GPIO_IFN(D2), - GPIO_FN(MSIOF3_RXD_A), - GPIO_FN(VI4_DATA18), - GPIO_FN(VI5_DATA2), - GPIO_IFN(D3), - GPIO_FN(MSIOF3_TXD_A), - GPIO_FN(VI4_DATA19), - GPIO_FN(VI5_DATA3), - GPIO_IFN(D4), - GPIO_FN(MSIOF2_SCK_B), - GPIO_FN(VI4_DATA20), - GPIO_FN(VI5_DATA4), - - /* IPSR6 */ - GPIO_IFN(D5), - GPIO_FN(MSIOF2_SYNC_B), - GPIO_FN(VI4_DATA21), - GPIO_FN(VI5_DATA5), - GPIO_IFN(D6), - GPIO_FN(MSIOF2_RXD_B), - GPIO_FN(VI4_DATA22), - GPIO_FN(VI5_DATA6), - GPIO_IFN(D7), - GPIO_FN(MSIOF2_TXD_B), - GPIO_FN(VI4_DATA23), - GPIO_FN(VI5_DATA7), - GPIO_IFN(D8), - GPIO_FN(LCDOUT0), - GPIO_FN(MSIOF2_SCK_D), - GPIO_FN(SCK4_C), - GPIO_FN(VI4_DATA0_A), - GPIO_FN(DU_DR0), - GPIO_IFN(D9), - GPIO_FN(LCDOUT1), - GPIO_FN(MSIOF2_SYNC_D), - GPIO_FN(VI4_DATA1_A), - GPIO_FN(DU_DR1), - GPIO_IFN(D10), - GPIO_FN(LCDOUT2), - GPIO_FN(MSIOF2_RXD_D), - GPIO_FN(HRX3_B), - GPIO_FN(VI4_DATA2_A), - GPIO_FN(CTS4x_C), - GPIO_FN(DU_DR2), - GPIO_IFN(D11), - GPIO_FN(LCDOUT3), - GPIO_FN(MSIOF2_TXD_D), - GPIO_FN(HTX3_B), - GPIO_FN(VI4_DATA3_A), - GPIO_FN(RTS4x_TANS_C), - GPIO_FN(DU_DR3), - GPIO_IFN(D12), - GPIO_FN(LCDOUT4), - GPIO_FN(MSIOF2_SS1_D), - GPIO_FN(RX4_C), - GPIO_FN(VI4_DATA4_A), - GPIO_FN(DU_DR4), - - /* IPSR7 */ - GPIO_IFN(D13), - GPIO_FN(LCDOUT5), - GPIO_FN(MSIOF2_SS2_D), - GPIO_FN(TX4_C), - GPIO_FN(VI4_DATA5_A), - GPIO_FN(DU_DR5), - GPIO_IFN(D14), - GPIO_FN(LCDOUT6), - GPIO_FN(MSIOF3_SS1_A), - GPIO_FN(HRX3_C), - GPIO_FN(VI4_DATA6_A), - GPIO_FN(DU_DR6), - GPIO_FN(SCL6_C), - GPIO_IFN(D15), - GPIO_FN(LCDOUT7), - GPIO_FN(MSIOF3_SS2_A), - GPIO_FN(HTX3_C), - GPIO_FN(VI4_DATA7_A), - GPIO_FN(DU_DR7), - GPIO_FN(SDA6_C), - GPIO_FN(FSCLKST), - GPIO_IFN(SD0_CLK), - GPIO_FN(MSIOF1_SCK_E), - GPIO_FN(STP_OPWM_0_B), - GPIO_IFN(SD0_CMD), - GPIO_FN(MSIOF1_SYNC_E), - GPIO_FN(STP_IVCXO27_0_B), - GPIO_IFN(SD0_DAT0), - GPIO_FN(MSIOF1_RXD_E), - GPIO_FN(TS_SCK0_B), - GPIO_FN(STP_ISCLK_0_B), - GPIO_IFN(SD0_DAT1), - GPIO_FN(MSIOF1_TXD_E), - GPIO_FN(TS_SPSYNC0_B), - GPIO_FN(STP_ISSYNC_0_B), - - /* IPSR8 */ - GPIO_IFN(SD0_DAT2), - GPIO_FN(MSIOF1_SS1_E), - GPIO_FN(TS_SDAT0_B), - GPIO_FN(STP_ISD_0_B), - - GPIO_IFN(SD0_DAT3), - GPIO_FN(MSIOF1_SS2_E), - GPIO_FN(TS_SDEN0_B), - GPIO_FN(STP_ISEN_0_B), - - GPIO_IFN(SD1_CLK), - GPIO_FN(MSIOF1_SCK_G), - GPIO_FN(SIM0_CLK_A), - - GPIO_IFN(SD1_CMD), - GPIO_FN(MSIOF1_SYNC_G), - GPIO_FN(NFCEx_B), - GPIO_FN(SIM0_D_A), - GPIO_FN(STP_IVCXO27_1_B), - - GPIO_IFN(SD1_DAT0), - GPIO_FN(SD2_DAT4), - GPIO_FN(MSIOF1_RXD_G), - GPIO_FN(NFWPx_B), - GPIO_FN(TS_SCK1_B), - GPIO_FN(STP_ISCLK_1_B), - - GPIO_IFN(SD1_DAT1), - GPIO_FN(SD2_DAT5), - GPIO_FN(MSIOF1_TXD_G), - GPIO_FN(NFDATA14_B), - GPIO_FN(TS_SPSYNC1_B), - GPIO_FN(STP_ISSYNC_1_B), - - GPIO_IFN(SD1_DAT2), - GPIO_FN(SD2_DAT6), - GPIO_FN(MSIOF1_SS1_G), - GPIO_FN(NFDATA15_B), - GPIO_FN(TS_SDAT1_B), - GPIO_FN(STP_IOD_1_B), - - GPIO_IFN(SD1_DAT3), - GPIO_FN(SD2_DAT7), - GPIO_FN(MSIOF1_SS2_G), - GPIO_FN(NFRBx_B), - GPIO_FN(TS_SDEN1_B), - GPIO_FN(STP_ISEN_1_B), - - /* IPSR9 */ - GPIO_IFN(SD2_CLK), - GPIO_FN(NFDATA8), - - GPIO_IFN(SD2_CMD), - GPIO_FN(NFDATA9), - - GPIO_IFN(SD2_DAT0), - GPIO_FN(NFDATA10), - - GPIO_IFN(SD2_DAT1), - GPIO_FN(NFDATA11), - - GPIO_IFN(SD2_DAT2), - GPIO_FN(NFDATA12), - - GPIO_IFN(SD2_DAT3), - GPIO_FN(NFDATA13), - - GPIO_IFN(SD2_DS), - GPIO_FN(NFALE), - - GPIO_IFN(SD3_CLK), - GPIO_FN(NFWEx), - - /* IPSR10 */ - GPIO_IFN(SD3_CMD), - GPIO_FN(NFREx), - - GPIO_IFN(SD3_DAT0), - GPIO_FN(NFDATA0), - - GPIO_IFN(SD3_DAT1), - GPIO_FN(NFDATA1), - - GPIO_IFN(SD3_DAT2), - GPIO_FN(NFDATA2), - - GPIO_IFN(SD3_DAT3), - GPIO_FN(NFDATA3), - - GPIO_IFN(SD3_DAT4), - GPIO_FN(SD2_CD_A), - GPIO_FN(NFDATA4), - - GPIO_IFN(SD3_DAT5), - GPIO_FN(SD2_WP_A), - GPIO_FN(NFDATA5), - - GPIO_IFN(SD3_DAT6), - GPIO_FN(SD3_CD), - GPIO_FN(NFDATA6), - - /* IPSR11 */ - GPIO_IFN(SD3_DAT7), - GPIO_FN(SD3_WP), - GPIO_FN(NFDATA7), - - GPIO_IFN(SD3_DS), - GPIO_FN(NFCLE), - - GPIO_IFN(SD0_CD), - GPIO_FN(NFDATA14_A), - GPIO_FN(SCL2_B), - GPIO_FN(SIM0_RST_A), - - GPIO_IFN(SD0_WP), - GPIO_FN(NFDATA15_A), - GPIO_FN(SDA2_B), - - GPIO_IFN(SD1_CD), - GPIO_FN(NFRBx_A), - GPIO_FN(SIM0_CLK_B), - - GPIO_IFN(SD1_WP), - GPIO_FN(NFCEx_A), - GPIO_FN(SIM0_D_B), - - GPIO_IFN(SCK0), - GPIO_FN(HSCK1_B), - GPIO_FN(MSIOF1_SS2_B), - GPIO_FN(AUDIO_CLKC_B), - GPIO_FN(SDA2_A), - GPIO_FN(SIM0_RST_B), - GPIO_FN(STP_OPWM_0_C), - GPIO_FN(RIF0_CLK_B), - GPIO_FN(ADICHS2), - GPIO_FN(SCK5_B), - - GPIO_IFN(RX0), - GPIO_FN(HRX1_B), - GPIO_FN(TS_SCK0_C), - GPIO_FN(STP_ISCLK_0_C), - GPIO_FN(RIF0_D0_B), - - /* IPSR12 */ - GPIO_IFN(TX0), - GPIO_FN(HTX1_B), - GPIO_FN(TS_SPSYNC0_C), - GPIO_FN(STP_ISSYNC_0_C), - GPIO_FN(RIF0_D1_B), - - GPIO_IFN(CTS0x), - GPIO_FN(HCTS1x_B), - GPIO_FN(MSIOF1_SYNC_B), - GPIO_FN(TS_SPSYNC1_C), - GPIO_FN(STP_ISSYNC_1_C), - GPIO_FN(RIF1_SYNC_B), - GPIO_FN(AUDIO_CLKOUT_C), - GPIO_FN(ADICS_SAMP), - - GPIO_IFN(RTS0x_TANS), - GPIO_FN(HRTS1x_B), - GPIO_FN(MSIOF1_SS1_B), - GPIO_FN(AUDIO_CLKA_B), - GPIO_FN(SCL2_A), - GPIO_FN(STP_IVCXO27_1_C), - GPIO_FN(RIF0_SYNC_B), - GPIO_FN(ADICHS1), - - GPIO_IFN(RX1_A), - GPIO_FN(HRX1_A), - GPIO_FN(TS_SDAT0_C), - GPIO_FN(STP_ISD_0_C), - GPIO_FN(RIF1_CLK_C), - - GPIO_IFN(TX1_A), - GPIO_FN(HTX1_A), - GPIO_FN(TS_SDEN0_C), - GPIO_FN(STP_ISEN_0_C), - GPIO_FN(RIF1_D0_C), - - GPIO_IFN(CTS1x), - GPIO_FN(HCTS1x_A), - GPIO_FN(MSIOF1_RXD_B), - GPIO_FN(TS_SDEN1_C), - GPIO_FN(STP_ISEN_1_C), - GPIO_FN(RIF1_D0_B), - GPIO_FN(ADIDATA), - - GPIO_IFN(RTS1x_TANS), - GPIO_FN(HRTS1x_A), - GPIO_FN(MSIOF1_TXD_B), - GPIO_FN(TS_SDAT1_C), - GPIO_FN(STP_ISD_1_C), - GPIO_FN(RIF1_D1_B), - GPIO_FN(ADICHS0), - - GPIO_IFN(SCK2), - GPIO_FN(SCIF_CLK_B), - GPIO_FN(MSIOF1_SCK_B), - GPIO_FN(TS_SCK1_C), - GPIO_FN(STP_ISCLK_1_C), - GPIO_FN(RIF1_CLK_B), - GPIO_FN(ADICLK), - - /* IPSR13 */ - GPIO_IFN(TX2_A), - GPIO_FN(SD2_CD_B), - GPIO_FN(SCL1_A), - GPIO_FN(FMCLK_A), - GPIO_FN(RIF1_D1_C), - GPIO_FN(FSO_CFE_0_B), - - GPIO_IFN(RX2_A), - GPIO_FN(SD2_WP_B), - GPIO_FN(SDA1_A), - GPIO_FN(FMIN_A), - GPIO_FN(RIF1_SYNC_C), - GPIO_FN(FSO_CEF_1_B), - - GPIO_IFN(HSCK0), - GPIO_FN(MSIOF1_SCK_D), - GPIO_FN(AUDIO_CLKB_A), - GPIO_FN(SSI_SDATA1_B), - GPIO_FN(TS_SCK0_D), - GPIO_FN(STP_ISCLK_0_D), - GPIO_FN(RIF0_CLK_C), - GPIO_FN(RX5_B), - - GPIO_IFN(HRX0), - GPIO_FN(MSIOF1_RXD_D), - GPIO_FN(SS1_SDATA2_B), - GPIO_FN(TS_SDEN0_D), - GPIO_FN(STP_ISEN_0_D), - GPIO_FN(RIF0_D0_C), - - GPIO_IFN(HTX0), - GPIO_FN(MSIOF1_TXD_D), - GPIO_FN(SSI_SDATA9_B), - GPIO_FN(TS_SDAT0_D), - GPIO_FN(STP_ISD_0_D), - GPIO_FN(RIF0_D1_C), - - GPIO_IFN(HCTS0x), - GPIO_FN(RX2_B), - GPIO_FN(MSIOF1_SYNC_D), - GPIO_FN(SSI_SCK9_A), - GPIO_FN(TS_SPSYNC0_D), - GPIO_FN(STP_ISSYNC_0_D), - GPIO_FN(RIF0_SYNC_C), - GPIO_FN(AUDIO_CLKOUT1_A), - - GPIO_IFN(HRTS0x), - GPIO_FN(TX2_B), - GPIO_FN(MSIOF1_SS1_D), - GPIO_FN(SSI_WS9_A), - GPIO_FN(STP_IVCXO27_0_D), - GPIO_FN(BPFCLK_A), - GPIO_FN(AUDIO_CLKOUT2_A), - - GPIO_IFN(MSIOF0_SYNC), - GPIO_FN(AUDIO_CLKOUT_A), - GPIO_FN(TX5_B), - GPIO_FN(BPFCLK_D), - - /* IPSR14 */ - GPIO_IFN(MSIOF0_SS1), - GPIO_FN(RX5_A), - GPIO_FN(NFWPx_A), - GPIO_FN(AUDIO_CLKA_C), - GPIO_FN(SSI_SCK2_A), - GPIO_FN(STP_IVCXO27_0_C), - GPIO_FN(AUDIO_CLKOUT3_A), - GPIO_FN(TCLK1_B), - - GPIO_IFN(MSIOF0_SS2), - GPIO_FN(TX5_A), - GPIO_FN(MSIOF1_SS2_D), - GPIO_FN(AUDIO_CLKC_A), - GPIO_FN(SSI_WS2_A), - GPIO_FN(STP_OPWM_0_D), - GPIO_FN(AUDIO_CLKOUT_D), - GPIO_FN(SPEEDIN_B), - - GPIO_IFN(MLB_CLK), - GPIO_FN(MSIOF1_SCK_F), - GPIO_FN(SCL1_B), - - GPIO_IFN(MLB_SIG), - GPIO_FN(RX1_B), - GPIO_FN(MSIOF1_SYNC_F), - GPIO_FN(SDA1_B), - - GPIO_IFN(MLB_DAT), - GPIO_FN(TX1_B), - GPIO_FN(MSIOF1_RXD_F), - - GPIO_IFN(SSI_SCK0129), - GPIO_FN(MSIOF1_TXD_F), - GPIO_FN(MOUT0), - - GPIO_IFN(SSI_WS0129), - GPIO_FN(MSIOF1_SS1_F), - GPIO_FN(MOUT1), - - GPIO_IFN(SSI_SDATA0), - GPIO_FN(MSIOF1_SS2_F), - GPIO_FN(MOUT2), - - /* IPSR15 */ - GPIO_IFN(SSI_SDATA1_A), - GPIO_FN(MOUT5), - - GPIO_IFN(SSI_SDATA2_A), - GPIO_FN(SSI_SCK1_B), - GPIO_FN(MOUT6), - - GPIO_IFN(SSI_SCK34), - GPIO_FN(MSIOF1_SS1_A), - GPIO_FN(STP_OPWM_0_A), - - GPIO_IFN(SSI_WS34), - GPIO_FN(HCTS2x_A), - GPIO_FN(MSIOF1_SS2_A), - GPIO_FN(STP_IVCXO27_0_A), - - GPIO_IFN(SSI_SDATA3), - GPIO_FN(HRTS2x_A), - GPIO_FN(MSIOF1_TXD_A), - GPIO_FN(TS_SCK0_A), - GPIO_FN(STP_ISCLK_0_A), - GPIO_FN(RIF0_D1_A), - GPIO_FN(RIF2_D0_A), - - GPIO_IFN(SSI_SCK4), - GPIO_FN(HRX2_A), - GPIO_FN(MSIOF1_SCK_A), - GPIO_FN(TS_SDAT0_A), - GPIO_FN(STP_ISD_0_A), - GPIO_FN(RIF0_CLK_A), - GPIO_FN(RIF2_CLK_A), - - GPIO_IFN(SSI_WS4), - GPIO_FN(HTX2_A), - GPIO_FN(MSIOF1_SYNC_A), - GPIO_FN(TS_SDEN0_A), - GPIO_FN(STP_ISEN_0_A), - GPIO_FN(RIF0_SYNC_A), - GPIO_FN(RIF2_SYNC_A), - - GPIO_IFN(SSI_SDATA4), - GPIO_FN(HSCK2_A), - GPIO_FN(MSIOF1_RXD_A), - GPIO_FN(TS_SPSYNC0_A), - GPIO_FN(STP_ISSYNC_0_A), - GPIO_FN(RIF0_D0_A), - GPIO_FN(RIF2_D1_A), - - /* IPSR16 */ - GPIO_IFN(SSI_SCK6), - GPIO_FN(SIM0_RST_D), - GPIO_FN(FSO_TOE_A), - - GPIO_IFN(SSI_WS6), - GPIO_FN(SIM0_D_D), - - GPIO_IFN(SSI_SDATA6), - GPIO_FN(SIM0_CLK_D), - - GPIO_IFN(SSI_SCK78), - GPIO_FN(HRX2_B), - GPIO_FN(MSIOF1_SCK_C), - GPIO_FN(TS_SCK1_A), - GPIO_FN(STP_ISCLK_1_A), - GPIO_FN(RIF1_CLK_A), - GPIO_FN(RIF3_CLK_A), - - GPIO_IFN(SSI_WS78), - GPIO_FN(HTX2_B), - GPIO_FN(MSIOF1_SYNC_C), - GPIO_FN(TS_SDAT1_A), - GPIO_FN(STP_ISD_1_A), - GPIO_FN(RIF1_SYNC_A), - GPIO_FN(RIF3_SYNC_A), - - GPIO_IFN(SSI_SDATA7), - GPIO_FN(HCTS2x_B), - GPIO_FN(MSIOF1_RXD_C), - GPIO_FN(TS_SDEN1_A), - GPIO_FN(STP_IEN_1_A), - GPIO_FN(RIF1_D0_A), - GPIO_FN(RIF3_D0_A), - GPIO_FN(TCLK2_A), - - GPIO_IFN(SSI_SDATA8), - GPIO_FN(HRTS2x_B), - GPIO_FN(MSIOF1_TXD_C), - GPIO_FN(TS_SPSYNC1_A), - GPIO_FN(STP_ISSYNC_1_A), - GPIO_FN(RIF1_D1_A), - GPIO_FN(EIF3_D1_A), - - GPIO_IFN(SSI_SDATA9_A), - GPIO_FN(HSCK2_B), - GPIO_FN(MSIOF1_SS1_C), - GPIO_FN(HSCK1_A), - GPIO_FN(SSI_WS1_B), - GPIO_FN(SCK1), - GPIO_FN(STP_IVCXO27_1_A), - GPIO_FN(SCK5), - - /* IPSR17 */ - GPIO_IFN(AUDIO_CLKA_A), - GPIO_FN(CC5_OSCOUT), - - GPIO_IFN(AUDIO_CLKB_B), - GPIO_FN(SCIF_CLK_A), - GPIO_FN(STP_IVCXO27_1_D), - GPIO_FN(REMOCON_A), - GPIO_FN(TCLK1_A), - - GPIO_IFN(USB0_PWEN), - GPIO_FN(SIM0_RST_C), - GPIO_FN(TS_SCK1_D), - GPIO_FN(STP_ISCLK_1_D), - GPIO_FN(BPFCLK_B), - GPIO_FN(RIF3_CLK_B), - GPIO_FN(FSO_CFE_1_A), - GPIO_FN(HSCK2_C), - - GPIO_IFN(USB0_OVC), - GPIO_FN(SIM0_D_C), - GPIO_FN(TS_SDAT1_D), - GPIO_FN(STP_ISD_1_D), - GPIO_FN(RIF3_SYNC_B), - GPIO_FN(HRX2_C), - - GPIO_IFN(USB1_PWEN), - GPIO_FN(SIM0_CLK_C), - GPIO_FN(SSI_SCK1_A), - GPIO_FN(TS_SCK0_E), - GPIO_FN(STP_ISCLK_0_E), - GPIO_FN(FMCLK_B), - GPIO_FN(RIF2_CLK_B), - GPIO_FN(SPEEDIN_A), - GPIO_FN(HTX2_C), - - GPIO_IFN(USB1_OVC), - GPIO_FN(MSIOF1_SS2_C), - GPIO_FN(SSI_WS1_A), - GPIO_FN(TS_SDAT0_E), - GPIO_FN(STP_ISD_0_E), - GPIO_FN(FMIN_B), - GPIO_FN(RIF2_SYNC_B), - GPIO_FN(REMOCON_B), - GPIO_FN(HCTS2x_C), - - GPIO_IFN(USB30_PWEN), - GPIO_FN(AUDIO_CLKOUT_B), - GPIO_FN(SSI_SCK2_B), - GPIO_FN(TS_SDEN1_D), - GPIO_FN(STP_ISEN_1_D), - GPIO_FN(STP_OPWM_0_E), - GPIO_FN(RIF3_D0_B), - GPIO_FN(TCLK2_B), - GPIO_FN(TPU0TO0), - GPIO_FN(BPFCLK_C), - GPIO_FN(HRTS2x_C), - - GPIO_IFN(USB30_OVC), - GPIO_FN(AUDIO_CLKOUT1_B), - GPIO_FN(SSI_WS2_B), - GPIO_FN(TS_SPSYNC1_D), - GPIO_FN(STP_ISSYNC_1_D), - GPIO_FN(STP_IVCXO27_0_E), - GPIO_FN(RIF3_D1_B), - GPIO_FN(FSO_TOE_B), - GPIO_FN(TPU0TO1), - - /* IPSR18 */ - GPIO_IFN(GP6_30), - GPIO_FN(AUDIO_CLKOUT2_B), - GPIO_FN(SSI_SCK9_B), - GPIO_FN(TS_SDEN0_E), - GPIO_FN(STP_ISEN_0_E), - GPIO_FN(RIF2_D0_B), - GPIO_FN(FSO_CFE_0_A), - GPIO_FN(TPU0TO2), - GPIO_FN(FMCLK_C), - GPIO_FN(FMCLK_D), - - GPIO_IFN(GP6_31), - GPIO_FN(AUDIO_CLKOUT3_B), - GPIO_FN(SSI_WS9_B), - GPIO_FN(TS_SPSYNC0_E), - GPIO_FN(STP_ISSYNC_0_E), - GPIO_FN(RIF2_D1_B), - GPIO_FN(TPU0TO3), - GPIO_FN(FMIN_C), - GPIO_FN(FMIN_D), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - /* GPSR0(0xE6060100) md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0000FFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_FN, GFN_D15, - GP_0_14_FN, GFN_D14, - GP_0_13_FN, GFN_D13, - GP_0_12_FN, GFN_D12, - GP_0_11_FN, GFN_D11, - GP_0_10_FN, GFN_D10, - GP_0_9_FN, GFN_D9, - GP_0_8_FN, GFN_D8, - GP_0_7_FN, GFN_D7, - GP_0_6_FN, GFN_D6, - GP_0_5_FN, GFN_D5, - GP_0_4_FN, GFN_D4, - GP_0_3_FN, GFN_D3, - GP_0_2_FN, GFN_D2, - GP_0_1_FN, GFN_D1, - GP_0_0_FN, GFN_D0 } - }, - /* GPSR1(0xE6060104) is md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0EFFFFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_FN, GFN_CLKOUT, - GP_1_27_FN, GFN_EX_WAIT0_A, - GP_1_26_FN, GFN_WE1x, - GP_1_25_FN, GFN_WE0x, - GP_1_24_FN, GFN_RD_WRx, - GP_1_23_FN, GFN_RDx, - GP_1_22_FN, GFN_BSx, - GP_1_21_FN, GFN_CS1x_A26, - GP_1_20_FN, GFN_CS0x, - GP_1_19_FN, GFN_A19, - GP_1_18_FN, GFN_A18, - GP_1_17_FN, GFN_A17, - GP_1_16_FN, GFN_A16, - GP_1_15_FN, GFN_A15, - GP_1_14_FN, GFN_A14, - GP_1_13_FN, GFN_A13, - GP_1_12_FN, GFN_A12, - GP_1_11_FN, GFN_A11, - GP_1_10_FN, GFN_A10, - GP_1_9_FN, GFN_A9, - GP_1_8_FN, GFN_A8, - GP_1_7_FN, GFN_A7, - GP_1_6_FN, GFN_A6, - GP_1_5_FN, GFN_A5, - GP_1_4_FN, GFN_A4, - GP_1_3_FN, GFN_A3, - GP_1_2_FN, GFN_A2, - GP_1_1_FN, GFN_A1, - GP_1_0_FN, GFN_A0 } - }, - /* GPSR2(0xE6060108) is md[3:1] controls */ - /* md[3:1] .. 0 : 0x000003C0 */ - /* .. other : 0x00000200 */ - { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A, - GP_2_13_FN, GFN_AVB_AVTP_MATCH_A, - GP_2_12_FN, GFN_AVB_LINK, - GP_2_11_FN, GFN_AVB_PHY_INT, - GP_2_10_FN, GFN_AVB_MAGIC, - GP_2_9_FN, GFN_AVB_MDC, - GP_2_8_FN, GFN_PWM2_A, - GP_2_7_FN, GFN_PWM1_A, - GP_2_6_FN, GFN_PWM0, - GP_2_5_FN, GFN_IRQ5, - GP_2_4_FN, GFN_IRQ4, - GP_2_3_FN, GFN_IRQ3, - GP_2_2_FN, GFN_IRQ2, - GP_2_1_FN, GFN_IRQ1, - GP_2_0_FN, GFN_IRQ0 } - }, - - /* GPSR3 */ - { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_FN, GFN_SD1_WP, - GP_3_14_FN, GFN_SD1_CD, - GP_3_13_FN, GFN_SD0_WP, - GP_3_12_FN, GFN_SD0_CD, - GP_3_11_FN, GFN_SD1_DAT3, - GP_3_10_FN, GFN_SD1_DAT2, - GP_3_9_FN, GFN_SD1_DAT1, - GP_3_8_FN, GFN_SD1_DAT0, - GP_3_7_FN, GFN_SD1_CMD, - GP_3_6_FN, GFN_SD1_CLK, - GP_3_5_FN, GFN_SD0_DAT3, - GP_3_4_FN, GFN_SD0_DAT2, - GP_3_3_FN, GFN_SD0_DAT1, - GP_3_2_FN, GFN_SD0_DAT0, - GP_3_1_FN, GFN_SD0_CMD, - GP_3_0_FN, GFN_SD0_CLK } - }, - /* GPSR4 */ - { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_FN, GFN_SD3_DS, - GP_4_16_FN, GFN_SD3_DAT7, - - GP_4_15_FN, GFN_SD3_DAT6, - GP_4_14_FN, GFN_SD3_DAT5, - GP_4_13_FN, GFN_SD3_DAT4, - GP_4_12_FN, FN_SD3_DAT3, - GP_4_11_FN, FN_SD3_DAT2, - GP_4_10_FN, FN_SD3_DAT1, - GP_4_9_FN, FN_SD3_DAT0, - GP_4_8_FN, FN_SD3_CMD, - GP_4_7_FN, FN_SD3_CLK, - GP_4_6_FN, GFN_SD2_DS, - GP_4_5_FN, GFN_SD2_DAT3, - GP_4_4_FN, GFN_SD2_DAT2, - GP_4_3_FN, GFN_SD2_DAT1, - GP_4_2_FN, GFN_SD2_DAT0, - GP_4_1_FN, FN_SD2_CMD, - GP_4_0_FN, GFN_SD2_CLK } - }, - /* GPSR5 */ - { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_FN, GFN_MLB_DAT, - GP_5_24_FN, GFN_MLB_SIG, - - GP_5_23_FN, GFN_MLB_CLK, - GP_5_22_FN, FN_MSIOF0_RXD, - GP_5_21_FN, GFN_MSIOF0_SS2, - GP_5_20_FN, FN_MSIOF0_TXD, - GP_5_19_FN, GFN_MSIOF0_SS1, - GP_5_18_FN, GFN_MSIOF0_SYNC, - GP_5_17_FN, FN_MSIOF0_SCK, - GP_5_16_FN, GFN_HRTS0x, - GP_5_15_FN, GFN_HCTS0x, - GP_5_14_FN, GFN_HTX0, - GP_5_13_FN, GFN_HRX0, - GP_5_12_FN, GFN_HSCK0, - GP_5_11_FN, GFN_RX2_A, - GP_5_10_FN, GFN_TX2_A, - GP_5_9_FN, GFN_SCK2, - GP_5_8_FN, GFN_RTS1x_TANS, - GP_5_7_FN, GFN_CTS1x, - GP_5_6_FN, GFN_TX1_A, - GP_5_5_FN, GFN_RX1_A, - GP_5_4_FN, GFN_RTS0x_TANS, - GP_5_3_FN, GFN_CTS0x, - GP_5_2_FN, GFN_TX0, - GP_5_1_FN, GFN_RX0, - GP_5_0_FN, GFN_SCK0 } - }, - /* GPSR6 */ - { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) { - GP_6_31_FN, GFN_GP6_31, - GP_6_30_FN, GFN_GP6_30, - GP_6_29_FN, GFN_USB30_OVC, - GP_6_28_FN, GFN_USB30_PWEN, - GP_6_27_FN, GFN_USB1_OVC, - GP_6_26_FN, GFN_USB1_PWEN, - GP_6_25_FN, GFN_USB0_OVC, - GP_6_24_FN, GFN_USB0_PWEN, - GP_6_23_FN, GFN_AUDIO_CLKB_B, - GP_6_22_FN, GFN_AUDIO_CLKA_A, - GP_6_21_FN, GFN_SSI_SDATA9_A, - GP_6_20_FN, GFN_SSI_SDATA8, - GP_6_19_FN, GFN_SSI_SDATA7, - GP_6_18_FN, GFN_SSI_WS78, - GP_6_17_FN, GFN_SSI_SCK78, - GP_6_16_FN, GFN_SSI_SDATA6, - GP_6_15_FN, GFN_SSI_WS6, - GP_6_14_FN, GFN_SSI_SCK6, - GP_6_13_FN, FN_SSI_SDATA5, - GP_6_12_FN, FN_SSI_WS5, - GP_6_11_FN, FN_SSI_SCK5, - GP_6_10_FN, GFN_SSI_SDATA4, - GP_6_9_FN, GFN_SSI_WS4, - GP_6_8_FN, GFN_SSI_SCK4, - GP_6_7_FN, GFN_SSI_SDATA3, - GP_6_6_FN, GFN_SSI_WS34, - GP_6_5_FN, GFN_SSI_SCK34, - GP_6_4_FN, GFN_SSI_SDATA2_A, - GP_6_3_FN, GFN_SSI_SDATA1_A, - GP_6_2_FN, GFN_SSI_SDATA0, - GP_6_1_FN, GFN_SSI_WS01239, - GP_6_0_FN, GFN_SSI_SCK01239 } - }, - /* GPSR7 */ - { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_7_3_FN, FN_HDMI1_CEC, - GP_7_2_FN, FN_HDMI0_CEC, - GP_7_1_FN, FN_AVS2, - GP_7_0_FN, FN_AVS1 } - }, - { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR0_31_28 [4] */ - IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP, - FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_27_24 [4] */ - IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE, - FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_23_20 [4] */ - IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_19_16 [4] */ - IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_15_12 [4] */ - IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_11_8 [4] */ - IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_7_4 [4] */ - IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_3_0 [4] */ - IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR1_31_28 [4] */ - IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0, - FN_VI4_DATA8, 0, FN_DU_DB0, 0, - 0, FN_PWM3_A, 0, 0, - 0, 0, 0, 0, - /* IPSR1_27_24 [4] */ - IFN_PWM2_A, FN_PWMFSW0, 0, FN_HTX3_D, - 0, 0, 0, 0, - 0, FN_IETX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_23_20 [4] */ - IFN_PWM1_A, 0, 0, FN_HRX3_D, - FN_VI4_DATA7_B, 0, 0, 0, - 0, FN_IERX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_19_16 [4] */ - IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0, - FN_VI4_DATA6_B, 0, 0, 0, - 0, FN_IECLK_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_15_12 [4] */ - IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, 0, 0, FN_MSIOF3_TXD_E, - 0, FN_PWM6_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_11_8 [4] */ - IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E, - 0, FN_PWM5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_7_4 [4] */ - IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E, - 0, FN_PWM4_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_3_0 [4] */ - IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E, - 0, FN_PWM3_B, 0, 0, - 0, 0, 0, 0 - } - }, - { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR2_31_28 [4] */ - IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B, - 0, 0, 0, FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR2_27_24 [4] */ - IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B, - FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_23_20 [4] */ - IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B, - FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_19_16 [4] */ - IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B, - FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_15_12 [4] */ - IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0, - FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_11_8 [4] */ - IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0, - FN_VI4_DATA11, 0, FN_DU_DB3, 0, - 0, FN_PWM6_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_7_4 [4] */ - IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0, - FN_VI4_DATA10, 0, FN_DU_DB2, 0, - 0, FN_PWM5_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_3_0 [4] */ - IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0, - FN_VI4_DATA9, 0, FN_DU_DB1, 0, - 0, FN_PWM4_A, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR3_31_28 [4] */ - IFN_A16, FN_LCDOUT8, 0, 0, - FN_VI4_FIELD, 0, FN_DU_DG0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_27_24 [4] */ - IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0, - FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_23_20 [4] */ - IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0, - FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_19_16 [4] */ - IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0, - FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_15_12 [4] */ - IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0, - FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_11_8 [4] */ - IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, - FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0, - 0, 0, 0, 0, - /* IPSR3_7_4 [4] */ - IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B, - 0, FN_VI5_HSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_3_0 [4] */ - IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B, - 0, FN_VI5_VSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR4_31_28 [4] */ - IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A, - FN_HTX3_A, 0, 0, 0, - FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_27_24 [4] */ - IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A, - FN_HRX3_A, 0, 0, 0, - FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_23_20 [4] */ - IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3, - FN_HSCK3, 0, 0, 0, - FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0, - 0, 0, 0, 0, - /* IPSR4_19_16 [4] */ - IFN_CS1x_A26, 0, 0, 0, - 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_15_12 [4] */ - IFN_CS0x, 0, 0, 0, - 0, FN_VI5_CLKENB, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_11_8 [4] */ - IFN_A19, FN_LCDOUT11, 0, 0, - FN_VI4_CLKENB, 0, FN_DU_DG3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_7_4 [4] */ - IFN_A18, FN_LCDOUT10, 0, 0, - FN_VI4_HSYNCx, 0, FN_DU_DG2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_3_0 [4] */ - IFN_A17, FN_LCDOUT9, 0, 0, - FN_VI4_VSYNCx, 0, FN_DU_DG1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR5_31_28 [4] */ - IFN_D4, FN_MSIOF2_SCK_B, 0, 0, - FN_VI4_DATA20, FN_VI5_DATA4, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_27_24 [4] */ - IFN_D3, 0, FN_MSIOF3_TXD_A, 0, - FN_VI4_DATA19, FN_VI5_DATA3, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_23_20 [4] */ - IFN_D2, 0, FN_MSIOF3_RXD_A, 0, - FN_VI4_DATA18, FN_VI5_DATA2, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_19_16 [4] */ - IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0, - FN_VI4_DATA17, FN_VI5_DATA1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_15_12 [4] */ - IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0, - FN_VI4_DATA16, FN_VI5_DATA0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_11_8 [4] */ - IFN_EX_WAIT0_A, FN_QCLK, 0, 0, - FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_7_4 [4] */ - IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS, - FN_HRTS3x, 0, 0, FN_SDA6_B, - FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0, - 0, 0, 0, 0, - /* IPSR5_3_0 [4] */ - IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x, - FN_HCTS3x, 0, 0, FN_SCL6_B, - FN_CAN_CLK, 0, FN_IECLK_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR6_31_28 [4] */ - IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C, - FN_VI4_DATA4_A, 0, FN_DU_DR4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_27_24 [4] */ - IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B, - FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_23_20 [4] */ - IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B, - FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_19_16 [4] */ - IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0, - FN_VI4_DATA1_A, 0, FN_DU_DR1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_15_12 [4] */ - IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C, - FN_VI4_DATA0_A, 0, FN_DU_DR0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_11_8 [4] */ - IFN_D7, FN_MSIOF2_TXD_B, 0, 0, - FN_VI4_DATA23, FN_VI5_DATA7, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_7_4 [4] */ - IFN_D6, FN_MSIOF2_RXD_B, 0, 0, - FN_VI4_DATA22, FN_VI5_DATA6, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_3_0 [4] */ - IFN_D5, FN_MSIOF2_SYNC_B, 0, 0, - FN_VI4_DATA21, FN_VI5_DATA5, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR7_31_28 [4] */ - IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0, - 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_27_24 [4] */ - IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0, - 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_23_20 [4] */ - IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0, - 0, 0, FN_STP_IVCXO27_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_19_16 [4] */ - IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0, - 0, 0, FN_STP_OPWM_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_15_12 [4] */ - FN_FSCLKST, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_11_8 [4] */ - IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C, - FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_7_4 [4] */ - IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C, - FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_3_0 [4] */ - IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C, - FN_VI4_DATA5_A, 0, FN_DU_DR5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR8_31_28 [4] */ - IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, - FN_NFRBx_B, - 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_27_24 [4] */ - IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_23_20 [4] */ - IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_19_16 [4] */ - IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, - FN_NFWPx_B, - 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_15_12 [4] */ - IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_11_8 [4] */ - IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0, - 0, FN_SIM0_CLK_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_7_4 [4] */ - IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0, - 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_3_0 [4] */ - IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0, - 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR9_31_28 [4] */ - IFN_SD3_CLK, 0, FN_NFWEx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_27_24 [4] */ - IFN_SD2_DS, 0, FN_NFALE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_23_20 [4] */ - IFN_SD2_DAT3, 0, FN_NFDATA13, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_19_16 [4] */ - IFN_SD2_DAT2, 0, FN_NFDATA12, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_15_12 [4] */ - IFN_SD2_DAT1, 0, FN_NFDATA11, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_11_8 [4] */ - IFN_SD2_DAT0, 0, FN_NFDATA10, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_7_4 [4] */ - IFN_SD2_CMD, 0, FN_NFDATA9, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_3_0 [4] */ - IFN_SD3_CLK, 0, FN_NFDATA8, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR10_31_28 [4] */ - IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_27_24 [4] */ - IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_23_20 [4] */ - IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_19_16 [4] */ - IFN_SD3_DAT3, 0, FN_NFDATA3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_15_12 [4] */ - IFN_SD3_DAT2, 0, FN_NFDATA2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_11_8 [4] */ - IFN_SD3_DAT1, 0, FN_NFDATA1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_7_4 [4] */ - IFN_SD3_DAT0, 0, FN_NFDATA0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_3_0 [4] */ - IFN_SD3_CMD, 0, FN_NFREx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR11_31_28 [4] */ - IFN_RX0, FN_HRX1_B, 0, 0, - 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_27_24 [4] */ - IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, - FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - 0, FN_ADICHS2, 0, FN_RIF0_CLK_B, - 0, 0, 0, 0, - /* IPSR11_23_20 [4] */ - IFN_SD1_WP, 0, FN_NFCEx_A, 0, - 0, FN_SIM0_D_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_19_16 [4] */ - IFN_SD1_CD, 0, FN_NFRBx_A, 0, - 0, FN_SIM0_CLK_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_15_12 [4] */ - IFN_SD0_WP, 0, FN_NFDATA15_A, 0, - FN_SDA2_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_11_8 [4] */ - IFN_SD0_CD, 0, FN_NFDATA14_A, 0, - FN_SCL2_B, FN_SIM0_RST_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_7_4 [4] */ - IFN_SD3_DS, 0, FN_NFCLE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_3_0 [4] */ - IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR12_31_28 [4] */ - IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, - 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B, - 0, FN_ADICLK, 0, 0, - 0, 0, 0, 0, - /* IPSR12_27_24 [4] */ - IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0, - 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B, - 0, FN_ADICHS0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_23_20 [4] */ - IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0, - 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, - 0, FN_ADIDATA, 0, 0, - /* IPSR12_19_16 [4] */ - IFN_TX1_A, FN_HTX1_A, 0, 0, - 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_15_12 [4] */ - IFN_RX1_A, FN_HRX1_A, 0, 0, - 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_11_8 [4] */ - IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, - FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, - 0, FN_ADICHS1, 0, 0, - 0, 0, 0, 0, - /* IPSR12_7_4 [4] */ - IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0, - 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0, - 0, 0, 0, 0, - /* IPSR12_3_0 [4] */ - IFN_TX0, FN_HTX1_B, 0, 0, - 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR13_31_28 [4] */ - IFN_MSIOF0_SYNC, 0, 0, 0, - 0, 0, 0, 0, - FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0, - 0, FN_BPFCLK_D, 0, 0, - /* IPSR13_27_24 [4] */ - IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0, - FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_23_20 [4] */ - IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0, - FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_19_16 [4] */ - IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0, - FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_15_12 [4] */ - IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0, - FN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_11_8 [4] */ - IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, - 0, 0, FN_RX5_B, 0, - 0, 0, 0, 0, - /* IPSR13_7_4 [4] */ - IFN_RX2_A, 0, 0, FN_SD2_WP_B, - FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C, - 0, FN_FSO_CEF_1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR13_3_0 [4] */ - IFN_TX2_A, 0, 0, FN_SD2_CD_B, - FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C, - 0, FN_FSO_CFE_0_B, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR14_31_28 [4] */ - IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0, - 0, 0, 0, FN_MOUT2, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_27_24 [4] */ - IFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0, - 0, 0, 0, FN_MOUT1, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_23_20 [4] */ - IFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0, - 0, 0, 0, FN_MOUT0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_19_16 [4] */ - IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_15_12 [4] */ - IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0, - FN_SDA1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_11_8 [4] */ - IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0, - FN_SCL1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_7_4 [4] */ - IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0, - FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0, - /* IPSR14_3_0 [4] */ - IFN_MSIOF0_SS1, FN_RX5_A, 0, FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0, - FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR15_31_28 [4] */ - IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0, - 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, - FN_RIF2_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_27_24 [4] */ - IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0, - 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_23_20 [4] */ - IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0, - 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A, - FN_RIF2_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_19_16 [4] */ - IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0, - 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A, - FN_RIF2_D0_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_15_12 [4] */ - IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0, - 0, 0, FN_STP_IVCXO27_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_11_8 [4] */ - IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0, - 0, 0, FN_STP_OPWM_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_7_4 [4] */ - IFN_SSI_SDATA2_A, 0, 0, 0, - FN_SSI_SCK1_B, 0, 0, FN_MOUT6, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_3_0 [4] */ - IFN_SSI_SDATA1_A, 0, 0, 0, - 0, 0, 0, FN_MOUT5, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR16_31_28 [4] */ - IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, - FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_27_24 [4] */ - IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0, - 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, - FN_EIF3_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_23_20 [4] */ - IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0, - 0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A, - FN_RIF3_D0_A, 0, FN_TCLK2_A, 0, - /* IPSR16_19_16 [4] */ - IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0, - 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_15_12 [4] */ - IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0, - 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, - FN_RIF3_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_11_8 [4] */ - IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_7_4 [4] */ - IFN_SSI_WS6, 0, 0, FN_SIM0_D_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_3_0 [4] */ - IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D, - 0, 0, 0, 0, - 0, 0, FN_FSO_TOE_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR17_31_28 [4] */ - IFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0, - FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, 0, FN_FSO_TOE_B, FN_TPU0TO1, - 0, 0, 0, 0, - /* IPSR17_27_24 [4] */ - IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, - FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0, - FN_BPFCLK_C, FN_HRTS2x_C, 0, 0, - /* IPSR17_23_20 [4] */ - IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0, - FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B, - FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0, - 0, FN_HCTS2x_C, 0, 0, - /* IPSR17_19_16 [4] */ - IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C, - FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B, - FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0, - 0, FN_HTX2_C, 0, 0, - /* IPSR17_15_12 [4] */ - IFN_USB0_OVC, 0, 0, FN_SIM0_D_C, - 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0, - FN_RIF3_SYNC_B, 0, 0, 0, - 0, FN_HRX2_C, 0, 0, - /* IPSR17_11_8 [4] */ - IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C, - 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, - FN_RIF3_CLK_B, 0, FN_FSO_CFE_1_A, 0, - 0, FN_HSCK2_C, 0, 0, - /* IPSR17_7_4 [4] */ - IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0, - 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, - 0, 0, FN_TCLK1_A, 0, - 0, 0, 0, 0, - /* IPSR17_3_0 [4] */ - IFN_AUDIO_CLKA_A, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, FN_CC5_OSCOUT, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 4, 4) { - /* reserved [31..24] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [23..16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* IPSR18_7_4 [4] */ - IFN_GP6_31, 0, 0, FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0, - FN_RIF2_D1_B, 0, 0, FN_TPU0TO3, - FN_FMIN_C, FN_FMIN_D, 0, 0, - /* IPSR18_3_0 [4] */ - IFN_GP6_30, 0, 0, FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, - FN_RIF2_D0_B, 0, FN_FSO_CFE_0_A, FN_TPU0TO2, - FN_FMCLK_C, FN_FMCLK_D, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32, - 3, 2, 3, - 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, - 2, 1, 2, 1, 1, 1) { - /* SEL_MSIOF3 [3] */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5, - FN_SEL_MSIOF3_6, 0, - /* SEL_MSIOF2 [2] */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* SEL_MSIOF1 [3] */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, 0, - - /* SEL_LBSC [1] */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* SEL_IEBUS [1] */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* SEL_I2C2 [1] */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* SEL_I2C1 [1] */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* SEL_HSCIF4 [1] */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* SEL_HSCIF3 [2] */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* SEL_HSCIF1 [1] */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - - /* SEL_FSO [1] */ - FN_SEL_FSO_0, FN_SEL_FSO_1, - /* SEL_HSCIF2 [2] */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, 0, - /* SEL_ETHERAVB [1] */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* SEL_DRIF3 [1] */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* SEL_DRIF2 [1] */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* SEL_DRIF1 [2] */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, 0, - - /* SEL_DRIF0 [2] */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, 0, - /* SEL_CANFD0 [1] */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* SEL_ADG [2] */ - FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_ADG_2, FN_SEL_ADG_3, - /* reserved [3] */ - 0, 0, - 0, 0, - 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32, - 2, 3, 1, 2, - 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* SEL_TSIF1 [2] */ - FN_SEL_TSIF1_0, - FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, - FN_SEL_TSIF1_3, - /* SEL_TSIF0 [3] */ - FN_SEL_TSIF0_0, - FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, - FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - 0, - 0, - 0, - /* SEL_TIMER_TMU [1] */ - FN_SEL_TIMER_TMU_0, - FN_SEL_TIMER_TMU_1, - /* SEL_SSP1_1 [2] */ - FN_SEL_SSP1_1_0, - FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, - FN_SEL_SSP1_1_3, - - /* SEL_SSP1_0 [3] */ - FN_SEL_SSP1_0_0, - FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, - FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - 0, - 0, - 0, - /* SEL_SSI [1] */ - FN_SEL_SSI_0, - FN_SEL_SSI_1, - /* SEL_SPEED_PULSE_IF [1] */ - FN_SEL_SPEED_PULSE_IF_0, - FN_SEL_SPEED_PULSE_IF_1, - /* SEL_SIMCARD [2] */ - FN_SEL_SIMCARD_0, - FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, - FN_SEL_SIMCARD_3, - /* SEL_SDHI2 [1] */ - FN_SEL_SDHI2_0, - FN_SEL_SDHI2_1, - - /* SEL_SCIF4 [2] */ - FN_SEL_SCIF4_0, - FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - 0, - /* SEL_SCIF3 [1] */ - FN_SEL_SCIF3_0, - FN_SEL_SCIF3_1, - /* SEL_SCIF2 [1] */ - FN_SEL_SCIF2_0, - FN_SEL_SCIF2_1, - /* SEL_SCIF1 [1] */ - FN_SEL_SCIF1_0, - FN_SEL_SCIF1_1, - /* SEL_SCIF [1] */ - FN_SEL_SCIF_0, - FN_SEL_SCIF_1, - /* SEL_REMOCON [1] */ - FN_SEL_REMOCON_0, - FN_SEL_REMOCON_1, - /* reserved [2] */ - 0, 0, - - 0, 0, - /* SEL_RCAN [1] */ - FN_SEL_RCAN_0, - FN_SEL_RCAN_1, - /* SEL_PWM6 [1] */ - FN_SEL_PWM6_0, - FN_SEL_PWM6_1, - /* SEL_PWM5 [1] */ - FN_SEL_PWM5_0, - FN_SEL_PWM5_1, - /* SEL_PWM4 [1] */ - FN_SEL_PWM4_0, - FN_SEL_PWM4_1, - /* SEL_PWM3 [1] */ - FN_SEL_PWM3_0, - FN_SEL_PWM3_1, - /* SEL_PWM2 [1] */ - FN_SEL_PWM2_0, - FN_SEL_PWM2_1, - /* SEL_PWM1 [1] */ - FN_SEL_PWM1_0, - FN_SEL_PWM1_1, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32, - 1, 1, 1, 2, 1, - 3, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1) { - /* I2C_SEL_5 [1] */ - FN_I2C_SEL_5_0, - FN_I2C_SEL_5_1, - /* I2C_SEL_3 [1] */ - FN_I2C_SEL_3_0, - FN_I2C_SEL_3_1, - /* I2C_SEL_0 [1] */ - FN_I2C_SEL_0_0, - FN_I2C_SEL_0_1, - /* SEL_FM [2] */ - FN_SEL_FM_0, - FN_SEL_FM_1, - FN_SEL_FM_2, - FN_SEL_FM_3, - /* SEL_SCIF5 [1] */ - FN_SEL_SCIF5_0, - FN_SEL_SCIF5_1, - - /* SEL_I2C6 [3] */ - FN_SEL_I2C6_0, - FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - 0, - 0, - 0, - 0, - 0, - /* SEL_NDF [1] */ - FN_SEL_NDF_0, - FN_SEL_NDF_1, - /* SEL_SSI2 [1] */ - FN_SEL_SSI2_0, - FN_SEL_SSI2_1, - /* SEL_SSI9 [1] */ - FN_SEL_SSI9_0, - FN_SEL_SSI9_1, - /* SEL_TIMER_TME2 [1] */ - FN_SEL_TIMER_TMU2_0, - FN_SEL_TIMER_TMU2_1, - /* SEL_ADG_B [1] */ - FN_SEL_ADG_B_0, - FN_SEL_ADG_B_1, - - /* SEL_ADG_C [1] */ - FN_SEL_ADG_C_0, - FN_SEL_ADG_C_1, - /* reserved [16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - /* SEL_VIN4 [1] */ - FN_SEL_VIN4_0, - FN_SEL_VIN4_1, - } - }, - - /* under construction */ - { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_IN, GP_0_15_OUT, - GP_0_14_IN, GP_0_14_OUT, - GP_0_13_IN, GP_0_13_OUT, - GP_0_12_IN, GP_0_12_OUT, - GP_0_11_IN, GP_0_11_OUT, - GP_0_10_IN, GP_0_10_OUT, - GP_0_9_IN, GP_0_9_OUT, - GP_0_8_IN, GP_0_8_OUT, - GP_0_7_IN, GP_0_7_OUT, - GP_0_6_IN, GP_0_6_OUT, - GP_0_5_IN, GP_0_5_OUT, - GP_0_4_IN, GP_0_4_OUT, - GP_0_3_IN, GP_0_3_OUT, - GP_0_2_IN, GP_0_2_OUT, - GP_0_1_IN, GP_0_1_OUT, - GP_0_0_IN, GP_0_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_IN, GP_1_28_OUT, - GP_1_27_IN, GP_1_27_OUT, - GP_1_26_IN, GP_1_26_OUT, - GP_1_25_IN, GP_1_25_OUT, - GP_1_24_IN, GP_1_24_OUT, - GP_1_23_IN, GP_1_23_OUT, - GP_1_22_IN, GP_1_22_OUT, - GP_1_21_IN, GP_1_21_OUT, - GP_1_20_IN, GP_1_20_OUT, - GP_1_19_IN, GP_1_19_OUT, - GP_1_18_IN, GP_1_18_OUT, - GP_1_17_IN, GP_1_17_OUT, - GP_1_16_IN, GP_1_16_OUT, - GP_1_15_IN, GP_1_15_OUT, - GP_1_14_IN, GP_1_14_OUT, - GP_1_13_IN, GP_1_13_OUT, - GP_1_12_IN, GP_1_12_OUT, - GP_1_11_IN, GP_1_11_OUT, - GP_1_10_IN, GP_1_10_OUT, - GP_1_9_IN, GP_1_9_OUT, - GP_1_8_IN, GP_1_8_OUT, - GP_1_7_IN, GP_1_7_OUT, - GP_1_6_IN, GP_1_6_OUT, - GP_1_5_IN, GP_1_5_OUT, - GP_1_4_IN, GP_1_4_OUT, - GP_1_3_IN, GP_1_3_OUT, - GP_1_2_IN, GP_1_2_OUT, - GP_1_1_IN, GP_1_1_OUT, - GP_1_0_IN, GP_1_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_IN, GP_2_14_OUT, - GP_2_13_IN, GP_2_13_OUT, - GP_2_12_IN, GP_2_12_OUT, - GP_2_11_IN, GP_2_11_OUT, - GP_2_10_IN, GP_2_10_OUT, - GP_2_9_IN, GP_2_9_OUT, - GP_2_8_IN, GP_2_8_OUT, - GP_2_7_IN, GP_2_7_OUT, - GP_2_6_IN, GP_2_6_OUT, - GP_2_5_IN, GP_2_5_OUT, - GP_2_4_IN, GP_2_4_OUT, - GP_2_3_IN, GP_2_3_OUT, - GP_2_2_IN, GP_2_2_OUT, - GP_2_1_IN, GP_2_1_OUT, - GP_2_0_IN, GP_2_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_IN, GP_3_15_OUT, - GP_3_14_IN, GP_3_14_OUT, - GP_3_13_IN, GP_3_13_OUT, - GP_3_12_IN, GP_3_12_OUT, - GP_3_11_IN, GP_3_11_OUT, - GP_3_10_IN, GP_3_10_OUT, - GP_3_9_IN, GP_3_9_OUT, - GP_3_8_IN, GP_3_8_OUT, - GP_3_7_IN, GP_3_7_OUT, - GP_3_6_IN, GP_3_6_OUT, - GP_3_5_IN, GP_3_5_OUT, - GP_3_4_IN, GP_3_4_OUT, - GP_3_3_IN, GP_3_3_OUT, - GP_3_2_IN, GP_3_2_OUT, - GP_3_1_IN, GP_3_1_OUT, - GP_3_0_IN, GP_3_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_IN, GP_4_17_OUT, - GP_4_16_IN, GP_4_16_OUT, - - GP_4_15_IN, GP_4_15_OUT, - GP_4_14_IN, GP_4_14_OUT, - GP_4_13_IN, GP_4_13_OUT, - GP_4_12_IN, GP_4_12_OUT, - GP_4_11_IN, GP_4_11_OUT, - GP_4_10_IN, GP_4_10_OUT, - GP_4_9_IN, GP_4_9_OUT, - GP_4_8_IN, GP_4_8_OUT, - GP_4_7_IN, GP_4_7_OUT, - GP_4_6_IN, GP_4_6_OUT, - GP_4_5_IN, GP_4_5_OUT, - GP_4_4_IN, GP_4_4_OUT, - GP_4_3_IN, GP_4_3_OUT, - GP_4_2_IN, GP_4_2_OUT, - GP_4_1_IN, GP_4_1_OUT, - GP_4_0_IN, GP_4_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_IN, GP_5_25_OUT, - GP_5_24_IN, GP_5_24_OUT, - - GP_5_23_IN, GP_5_23_OUT, - GP_5_22_IN, GP_5_22_OUT, - GP_5_21_IN, GP_5_21_OUT, - GP_5_20_IN, GP_5_20_OUT, - GP_5_19_IN, GP_5_19_OUT, - GP_5_18_IN, GP_5_18_OUT, - GP_5_17_IN, GP_5_17_OUT, - GP_5_16_IN, GP_5_16_OUT, - - GP_5_15_IN, GP_5_15_OUT, - GP_5_14_IN, GP_5_14_OUT, - GP_5_13_IN, GP_5_13_OUT, - GP_5_12_IN, GP_5_12_OUT, - GP_5_11_IN, GP_5_11_OUT, - GP_5_10_IN, GP_5_10_OUT, - GP_5_9_IN, GP_5_9_OUT, - GP_5_8_IN, GP_5_8_OUT, - GP_5_7_IN, GP_5_7_OUT, - GP_5_6_IN, GP_5_6_OUT, - GP_5_5_IN, GP_5_5_OUT, - GP_5_4_IN, GP_5_4_OUT, - GP_5_3_IN, GP_5_3_OUT, - GP_5_2_IN, GP_5_2_OUT, - GP_5_1_IN, GP_5_1_OUT, - GP_5_0_IN, GP_5_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { - GP_INOUTSEL(6) - } - }, - { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_6_3_IN, GP_6_3_OUT, - GP_6_2_IN, GP_6_2_OUT, - GP_6_1_IN, GP_6_1_OUT, - GP_6_0_IN, GP_6_0_OUT, - } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - /* use OUTDT registers? */ - { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, - GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, - GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, - GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } - }, - { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { - 0, 0, 0, GP_1_28_DATA, - GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, - GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, - GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, - GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, - GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, - GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, - GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } - }, - { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, - GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, - GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, - GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } - }, - { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, - GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, - GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, - GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } - }, - { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA, - GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA, - GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA, - GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA, - GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } - }, - { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { - 0, 0, 0, 0, - 0, 0, GP_5_25_DATA, GP_5_24_DATA, - GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, - GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, - GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, - GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, - GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, - GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } - }, - { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { - GP_INDT(6) } - }, - { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, - GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } - }, - { }, -}; - -static struct pinmux_info r8a7796_pinmux_info = { - .name = "r8a7796_pfc", - - .unlock_reg = 0xe6060000, /* PMMR */ - - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_FMIN_D, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), -}; - -void r8a7796_pinmux_init(void) -{ - register_pinmux(&r8a7796_pinmux_info); -} diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index a26736a5aca..1e74db36076 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,6 +11,15 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3128 + bool "Support Rockchip RK3128" + select CPU_V7 + help + The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3188 bool "Support Rockchip RK3188" select CPU_V7 @@ -211,6 +220,7 @@ config SPL_MMC_SUPPORT default y if !SPL_ROCKCHIP_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 7e1f864383e..e1b0519b1f4 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -30,6 +30,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-y += boot_mode.o obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o +obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o @@ -43,6 +44,7 @@ obj-y += rk_timer.o endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 460dd6074e6..e5393ec50a8 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -34,10 +34,11 @@ struct rk3036_sdram_priv { struct rk3036_ddr_config ddr_config; }; -/* use integer mode, 396MHz dpll setting +/* + * use integer mode, dpll output 792MHz and ddr get 396MHz * refdiv, fbdiv, postdiv1, postdiv2 */ -const struct pll_div dpll_init_cfg = {1, 50, 3, 1}; +const struct pll_div dpll_init_cfg = {1, 66, 2, 1}; /* 396Mhz ddr timing */ const struct rk3036_ddr_timing ddr_timing = {0x18c, @@ -329,29 +330,26 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv) struct rk3036_pll *pll = &priv->cru->pll[1]; /* pll enter slow-mode */ - rk_clrsetreg(&priv->cru->cru_mode_con, - DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); /* use integer mode */ - rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); rk_clrsetreg(&pll->con0, - PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | dpll_init_cfg.fbdiv); - rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | - PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, - (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | - dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | + dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) rockchip_udelay(1); /* PLL enter normal-mode */ - rk_clrsetreg(&priv->cru->cru_mode_con, - DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_NORM << DPLL_MODE_SHIFT); } diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c new file mode 100644 index 00000000000..2e8393d70a9 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <asm/arch/grf_rk3128.h> +#include <asm/arch/boot_mode.h> +#include <asm/arch/timer.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +__weak int rk_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + setup_boot_mode(); + + return rk_board_late_init(); +} + +int board_init(void) +{ + int ret = 0; + + rockchip_timer_init(); + + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulator\n", __func__); + return ret; + } + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8400000; + /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + + gd->bd->bi_dram[0].size + 0xe00000; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + gd->ram_size - gd->bd->bi_dram[1].start; + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3128_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3128-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3128-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3128_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif + +#if defined(CONFIG_USB_FUNCTION_FASTBOOT) +int fb_set_reboot_flag(void) +{ + struct rk3128_grf *grf; + + printf("Setting reboot to fastboot flag ...\n"); + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + /* Set boot mode to fastboot */ + writel(BOOT_FASTBOOT, &grf->os_reg[0]); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig new file mode 100644 index 00000000000..40655a22b59 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -0,0 +1,24 @@ +if ROCKCHIP_RK3128 + +choice + prompt "RK3128 board select" + +config TARGET_EVB_RK3128 + bool "RK3128 evaluation board" + select BOARD_LATE_INIT + help + RK3128evb is a evaluation board for Rockchip rk3128, + with full function and phisical connectors support like + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... + +endchoice + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +source "board/rockchip/evb_rk3128/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile new file mode 100644 index 00000000000..50e11175423 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2017 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3128.o +obj-y += syscon_rk3128.o +obj-y += clk_rk3128.o diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c new file mode 100644 index 00000000000..7ca5fd34841 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3128.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3128_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3128_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c new file mode 100644 index 00000000000..9d6e3b1ee19 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/rk3128.c @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int arch_cpu_init(void) +{ + /* We do some SoC one time setting here. */ + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c new file mode 100644 index 00000000000..0b636390ac2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3128_syscon_ids[] = { + { .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3128) = { + .name = "rk3128_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3128_syscon_ids, +}; diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile index 0f5ac37168a..c2806af69b0 100644 --- a/arch/arm/mach-stm32/Makefile +++ b/arch/arm/mach-stm32/Makefile @@ -4,7 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # - +obj-y += soc.o obj-$(CONFIG_STM32F4) += stm32f4/ obj-$(CONFIG_STM32F7) += stm32f7/ -obj-$(CONFIG_STM32H7) += stm32h7/ diff --git a/arch/arm/mach-stm32/stm32h7/soc.c b/arch/arm/mach-stm32/soc.c index 692dbcc04a8..df20d547c50 100644 --- a/arch/arm/mach-stm32/stm32h7/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -9,11 +9,6 @@ #include <asm/io.h> #include <asm/armv7m_mpu.h> -u32 get_cpu_rev(void) -{ - return 0; -} - int arch_cpu_init(void) { int i; @@ -30,11 +25,11 @@ int arch_cpu_init(void) { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_4GB }, - /* Code area, executable & strongly ordered */ - { 0xD0000000, REGION_1, XN_EN, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_8MB }, + /* armv7m code area */ + { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_512MB }, - /* Device area in all H7 : Not executable */ + /* Device area : Not executable */ { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, DEVICE_NON_SHARED, REGION_512MB }, @@ -42,8 +37,14 @@ int arch_cpu_init(void) * Armv7m fixed configuration: strongly ordered & not * executable, not cacheable */ - { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, + { 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, STRONG_ORDER, REGION_512MB }, + +#if !defined(CONFIG_STM32H7) + /* Device area : Not executable */ + { 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, + DEVICE_NON_SHARED, REGION_512MB }, +#endif }; disable_mpu(); @@ -53,7 +54,3 @@ int arch_cpu_init(void) return 0; } - -void s_init(void) -{ -} diff --git a/arch/arm/mach-stm32/stm32f4/Makefile b/arch/arm/mach-stm32/stm32f4/Makefile index 020e78370c8..63db8200300 100644 --- a/arch/arm/mach-stm32/stm32f4/Makefile +++ b/arch/arm/mach-stm32/stm32f4/Makefile @@ -8,4 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += soc.o clock.o timer.o +obj-y += clock.o timer.o diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 15fcadbbe6f..774591d6a59 100644 --- a/arch/arm/mach-stm32/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <stm32_rcc.h> #include <asm/io.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_periph.h> @@ -81,32 +82,6 @@ #define RCC_ENR_GPIO_J_EN (1 << 9) #define RCC_ENR_GPIO_K_EN (1 << 10) -struct pll_psc { - u8 pll_m; - u16 pll_n; - u8 pll_p; - u8 pll_q; - u8 ahb_psc; - u8 apb1_psc; - u8 apb2_psc; -}; - -#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF - -#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 - #if !defined(CONFIG_STM32_HSE_HZ) #error "CONFIG_STM32_HSE_HZ not defined!" #else diff --git a/arch/arm/mach-stm32/stm32f4/soc.c b/arch/arm/mach-stm32/stm32f4/soc.c deleted file mode 100644 index 9eb655a681f..00000000000 --- a/arch/arm/mach-stm32/stm32f4/soc.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/armv7m_mpu.h> -#include <asm/arch/stm32.h> - -u32 get_cpu_rev(void) -{ - return 0; -} - -int arch_cpu_init(void) -{ - struct mpu_region_config stm32_region_config[] = { - { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_4GB }, - }; - int i; - - configure_clocks(); - /* - * Configure the memory protection unit (MPU) to allow full access to - * the whole 4GB address space. - */ - disable_mpu(); - for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++) - mpu_config(&stm32_region_config[i]); - enable_mpu(); - - return 0; -} - -void s_init(void) -{ -} diff --git a/arch/arm/mach-stm32/stm32f4/timer.c b/arch/arm/mach-stm32/stm32f4/timer.c index 1dee190766b..163f4616d3f 100644 --- a/arch/arm/mach-stm32/stm32f4/timer.c +++ b/arch/arm/mach-stm32/stm32f4/timer.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <stm32_rcc.h> #include <asm/io.h> #include <asm/armv7m.h> #include <asm/arch/stm32.h> diff --git a/arch/arm/mach-stm32/stm32f7/Makefile b/arch/arm/mach-stm32/stm32f7/Makefile index 6696b267fe4..8132c132340 100644 --- a/arch/arm/mach-stm32/stm32f7/Makefile +++ b/arch/arm/mach-stm32/stm32f7/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += timer.o soc.o +obj-y += timer.o diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c deleted file mode 100644 index a960cc1cbfd..00000000000 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/armv7m_mpu.h> -#include <asm/arch/stm32.h> - -u32 get_cpu_rev(void) -{ - return 0; -} - -int arch_cpu_init(void) -{ - int i; - - struct mpu_region_config stm32_region_config[] = { - { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_4GB }, - - { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_512MB }, - - { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, - DEVICE_NON_SHARED, REGION_512MB }, - - { 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, - DEVICE_NON_SHARED, REGION_512MB }, - - { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_512MB }, - }; - - disable_mpu(); - for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++) - mpu_config(&stm32_region_config[i]); - enable_mpu(); - - return 0; -} - -void s_init(void) -{ -} diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c index 0521c24810b..69d37a7c708 100644 --- a/arch/arm/mach-stm32/stm32f7/timer.c +++ b/arch/arm/mach-stm32/stm32f7/timer.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <stm32_rcc.h> #include <asm/io.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_defs.h> diff --git a/arch/arm/mach-stm32/stm32h7/Makefile b/arch/arm/mach-stm32/stm32h7/Makefile deleted file mode 100644 index cba2e3be1ca..00000000000 --- a/arch/arm/mach-stm32/stm32h7/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2017, STMicroelectronics - All Rights Reserved -# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += soc.o diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts index fbe6d744371..b19ba988dbf 100644 --- a/arch/nds32/dts/ae3xx.dts +++ b/arch/nds32/dts/ae3xx.dts @@ -69,6 +69,14 @@ interrupts = <25 4>; }; + mmc0: mmc@f0e00000 { + compatible = "andestech,atsdc010"; + max-frequency = <100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <17 4>; + }; + nor@0,0 { compatible = "cfi-flash"; reg = <0x88000000 0x1000>; diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts index 99cde2f8b8f..19dc36fa157 100644 --- a/arch/nds32/dts/ag101p.dts +++ b/arch/nds32/dts/ag101p.dts @@ -60,4 +60,12 @@ reg = <0x90900000 0x1000>; interrupts = <25 4>; }; + + mmc0: mmc@98e00000 { + compatible = "andestech,atsdc010"; + max-frequency = <30000000>; + fifo-depth = <0x10>; + reg = <0x98e00000 0x1000>; + interrupts = <5 4>; + }; }; diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 8835dcf36f1..472ada54907 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -34,9 +34,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64) -LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 -LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 - # This is used in the top-level Makefile which does not include # PLATFORM_LDFLAGS LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index e13786efa59..1c42584e76f 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -143,8 +143,8 @@ const char *cpu_vendor_name(int vendor) { const char *name; name = "<invalid cpu vendor>"; - if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && - (x86_vendor_name[vendor] != 0)) + if (vendor < ARRAY_SIZE(x86_vendor_name) && + x86_vendor_name[vendor]) name = x86_vendor_name[vendor]; return name; diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index da378128fec..81444f3d9e1 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -18,7 +18,7 @@ if QEMU config SYS_CAR_ADDR hex - default 0xd0000 + default 0x10000 config SYS_CAR_SIZE hex diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index fe00d7573f5..7d729ea0f7d 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-y += early_cmos.o obj-$(CONFIG_EFI) += efi/ obj-y += e820.o -obj-y += gcc.o obj-y += init_helpers.o obj-y += interrupts.o obj-y += lpc-uclass.o @@ -49,12 +48,7 @@ endif obj-$(CONFIG_HAVE_FSP) += fsp/ obj-$(CONFIG_SPL_BUILD) += spl.o -extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a - -NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name) -OBJCOPYFLAGS := --prefix-symbols=__normal_ -$(obj)/lib.a: $(NORMAL_LIBGCC) FORCE - $(call if_changed,objcopy) +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += div64.o ifeq ($(CONFIG_$(SPL_)X86_64),) obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index ecd4f4e6c61..e548cdbed59 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -109,7 +109,7 @@ static int boot_prep_linux(bootm_headers_t *images) } is_zimage = 1; #if defined(CONFIG_FIT) - } else if (images->fit_uname_os) { + } else if (images->fit_uname_os && is_zimage) { ret = fit_image_get_data(images->fit_hdr_os, images->fit_noffset_os, (const void **)&data, &len); diff --git a/arch/x86/lib/div64.c b/arch/x86/lib/div64.c new file mode 100644 index 00000000000..4efed74037e --- /dev/null +++ b/arch/x86/lib/div64.c @@ -0,0 +1,113 @@ +/* + * This file is copied from the coreboot repository as part of + * the libpayload project: + * + * Copyright 2014 Google Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common.h> + +union overlay64 { + u64 longw; + struct { + u32 lower; + u32 higher; + } words; +}; + +u64 __ashldi3(u64 num, unsigned int shift) +{ + union overlay64 output; + + output.longw = num; + if (shift >= 32) { + output.words.higher = output.words.lower << (shift - 32); + output.words.lower = 0; + } else { + if (!shift) + return num; + output.words.higher = (output.words.higher << shift) | + (output.words.lower >> (32 - shift)); + output.words.lower = output.words.lower << shift; + } + return output.longw; +} + +u64 __lshrdi3(u64 num, unsigned int shift) +{ + union overlay64 output; + + output.longw = num; + if (shift >= 32) { + output.words.lower = output.words.higher >> (shift - 32); + output.words.higher = 0; + } else { + if (!shift) + return num; + output.words.lower = output.words.lower >> shift | + (output.words.higher << (32 - shift)); + output.words.higher = output.words.higher >> shift; + } + return output.longw; +} + +#define MAX_32BIT_UINT ((((u64)1) << 32) - 1) + +static u64 _64bit_divide(u64 dividend, u64 divider, u64 *rem_p) +{ + u64 result = 0; + + /* + * If divider is zero - let the rest of the system care about the + * exception. + */ + if (!divider) + return 1 / (u32)divider; + + /* As an optimization, let's not use 64 bit division unless we must. */ + if (dividend <= MAX_32BIT_UINT) { + if (divider > MAX_32BIT_UINT) { + result = 0; + if (rem_p) + *rem_p = divider; + } else { + result = (u32)dividend / (u32)divider; + if (rem_p) + *rem_p = (u32)dividend % (u32)divider; + } + return result; + } + + while (divider <= dividend) { + u64 locald = divider; + u64 limit = __lshrdi3(dividend, 1); + int shifts = 0; + + while (locald <= limit) { + shifts++; + locald = locald + locald; + } + result |= __ashldi3(1, shifts); + dividend -= locald; + } + + if (rem_p) + *rem_p = dividend; + + return result; +} + +u64 __udivdi3(u64 num, u64 den) +{ + return _64bit_divide(num, den, NULL); +} + +u64 __umoddi3(u64 num, u64 den) +{ + u64 v = 0; + + _64bit_divide(num, den, &v); + return v; +} diff --git a/arch/x86/lib/gcc.c b/arch/x86/lib/gcc.c deleted file mode 100644 index 3c70d790d49..00000000000 --- a/arch/x86/lib/gcc.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifdef __GNUC__ - -/* - * GCC's libgcc handling is quite broken. While the libgcc functions - * are always regparm(0) the code that calls them uses whatever the - * compiler call specifies. Therefore we need a wrapper around those - * functions. See gcc bug PR41055 for more information. - */ -#define WRAP_LIBGCC_CALL(type, name) \ - type __normal_##name(type a, type b) __attribute__((regparm(0))); \ - type __wrap_##name(type a, type b); \ - type __attribute__((no_instrument_function)) \ - __wrap_##name(type a, type b) \ - { return __normal_##name(a, b); } - -WRAP_LIBGCC_CALL(long long, __divdi3) -WRAP_LIBGCC_CALL(unsigned long long, __udivdi3) -WRAP_LIBGCC_CALL(long long, __moddi3) -WRAP_LIBGCC_CALL(unsigned long long, __umoddi3) - -#endif diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c index 79608f4efe8..f918c630c17 100644 --- a/board/AndesTech/adp-ag101p/adp-ag101p.c +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -85,8 +85,10 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) int board_mmc_init(bd_t *bis) { +#ifndef CONFIG_DM_MMC #ifdef CONFIG_FTSDC010 ftsdc010_mmc_init(0); #endif +#endif return 0; } diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index af66837909d..b03c0a3714b 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -212,7 +212,7 @@ static struct hws_topology_map board_topology_map_1g = { BUS_WIDTH_16, /* memory_width */ MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ - 0, 0, /* cas_l cas_wl */ + 0, 0, /* cas_wl cas_l */ HWS_TEMP_NORMAL, /* temperature */ HWS_TIM_2T} }, /* timing (force 2t) */ 5, /* Num Of Bus Per Interface*/ @@ -231,7 +231,7 @@ static struct hws_topology_map board_topology_map_2g = { BUS_WIDTH_16, /* memory_width */ MEM_8G, /* mem_size */ DDR_FREQ_800, /* frequency */ - 0, 0, /* cas_l cas_wl */ + 0, 0, /* cas_wl cas_l */ HWS_TEMP_NORMAL, /* temperature */ HWS_TIM_2T} }, /* timing (force 2t) */ 5, /* Num Of Bus Per Interface*/ diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index ac58f908526..7db0095f75e 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -68,7 +68,7 @@ static struct hws_topology_map board_topology_map = { BUS_WIDTH_8, /* memory_width */ MEM_2G, /* mem_size */ DDR_FREQ_800, /* frequency */ - 0, 0, /* cas_l cas_wl */ + 0, 0, /* cas_wl cas_l */ HWS_TEMP_LOW, /* temperature */ HWS_TIM_DEFAULT} }, /* timing */ 5, /* Num Of Bus Per Interface*/ diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index a1974cb4bd2..b95cd1d4aab 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -89,7 +89,7 @@ static struct hws_topology_map board_topology_map = { BUS_WIDTH_8, /* memory_width */ MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ - 0, 0, /* cas_l cas_wl */ + 0, 0, /* cas_wl cas_l */ HWS_TEMP_LOW, /* temperature */ HWS_TIM_DEFAULT} }, /* timing */ 5, /* Num Of Bus Per Interface*/ diff --git a/board/amlogic/khadas-vim/Kconfig b/board/amlogic/khadas-vim/Kconfig new file mode 100644 index 00000000000..0fa8db97eab --- /dev/null +++ b/board/amlogic/khadas-vim/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KHADAS_VIM + +config SYS_BOARD + default "khadas-vim" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "khadas-vim" + +endif diff --git a/board/amlogic/khadas-vim/MAINTAINERS b/board/amlogic/khadas-vim/MAINTAINERS new file mode 100644 index 00000000000..024220a5261 --- /dev/null +++ b/board/amlogic/khadas-vim/MAINTAINERS @@ -0,0 +1,6 @@ +KHADAS-VIM +M: Neil Armstrong <narmstrong@baylibre.com> +S: Maintained +F: board/amlogic/khadas-vim/ +F: include/configs/khadas-vim.h +F: configs/khadas-vim_defconfig diff --git a/board/amlogic/khadas-vim/Makefile b/board/amlogic/khadas-vim/Makefile new file mode 100644 index 00000000000..eedc1bf3767 --- /dev/null +++ b/board/amlogic/khadas-vim/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := khadas-vim.o diff --git a/board/amlogic/khadas-vim/README b/board/amlogic/khadas-vim/README new file mode 100644 index 00000000000..0478eee3f08 --- /dev/null +++ b/board/amlogic/khadas-vim/README @@ -0,0 +1,96 @@ +U-Boot for Khadas VIM +======================= + +Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Tomato +Technology Co., Ltd with the following specifications: + + - Amlogic S905x ARM Cortex-A53 quad-core SoC @ 2GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG + - 8GB/16GBeMMC + - microSD + - SDIO Wifi Module, Bluetooth + - Two channels IR receiver + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + +U-Boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make khadas-vim_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot + > cd vim-u-boot + > make kvim_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/khadas-vim/khadas-vim.c b/board/amlogic/khadas-vim/khadas-vim.c new file mode 100644 index 00000000000..5e198569db4 --- /dev/null +++ b/board/amlogic/khadas-vim/khadas-vim.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/gxbb.h> +#include <asm/arch/mem.h> +#include <asm/arch/sm.h> +#include <asm/arch/eth.h> + +#define EFUSE_SN_OFFSET 20 +#define EFUSE_SN_SIZE 16 +#define EFUSE_MAC_OFFSET 52 +#define EFUSE_MAC_SIZE 6 + +int board_init(void) +{ + return 0; +} + +int misc_init_r(void) +{ + u8 mac_addr[EFUSE_MAC_SIZE]; + char serial[EFUSE_SN_SIZE]; + ssize_t len; + + meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, + MESON_GXL_USE_INTERNAL_RMII_PHY); + + if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { + len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, + mac_addr, EFUSE_MAC_SIZE); + if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); + } + + if (!env_get("serial#")) { + len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, + EFUSE_SN_SIZE); + if (len == EFUSE_SN_SIZE) + env_set("serial#", serial); + } + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + meson_gx_init_reserved_memory(blob); + + return 0; +} diff --git a/board/amlogic/libretech-cc/Kconfig b/board/amlogic/libretech-cc/Kconfig new file mode 100644 index 00000000000..7a6f9169bdb --- /dev/null +++ b/board/amlogic/libretech-cc/Kconfig @@ -0,0 +1,12 @@ +if TARGET_LIBRETECH_CC + +config SYS_BOARD + default "libretech-cc" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "libretech-cc" + +endif diff --git a/board/amlogic/libretech-cc/MAINTAINERS b/board/amlogic/libretech-cc/MAINTAINERS new file mode 100644 index 00000000000..398ce57db2c --- /dev/null +++ b/board/amlogic/libretech-cc/MAINTAINERS @@ -0,0 +1,6 @@ +LIBRETECH-CC +M: Neil Armstrong <narmstrong@baylibre.com> +S: Maintained +F: board/amlogic/libretech-cc/ +F: include/configs/libretech-cc.h +F: configs/libretech-cc_defconfig diff --git a/board/amlogic/libretech-cc/Makefile b/board/amlogic/libretech-cc/Makefile new file mode 100644 index 00000000000..d0e3bbb9917 --- /dev/null +++ b/board/amlogic/libretech-cc/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := libretech-cc.o diff --git a/board/amlogic/libretech-cc/README b/board/amlogic/libretech-cc/README new file mode 100644 index 00000000000..c06a3924824 --- /dev/null +++ b/board/amlogic/libretech-cc/README @@ -0,0 +1,96 @@ +U-Boot for LibreTech CC +======================= + +LibreTech CC is a single board computer manufactured by Libre Technology +with the following specifications: + + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 2GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the U-Boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + +U-Boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make libretech-cc_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot + > cd amlogic-u-boot + > make libretech_cc_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c new file mode 100644 index 00000000000..6be6e2ae93b --- /dev/null +++ b/board/amlogic/libretech-cc/libretech-cc.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/gxbb.h> +#include <asm/arch/sm.h> +#include <asm/arch/eth.h> +#include <asm/arch/mem.h> + +#define EFUSE_SN_OFFSET 20 +#define EFUSE_SN_SIZE 16 +#define EFUSE_MAC_OFFSET 52 +#define EFUSE_MAC_SIZE 6 + +int board_init(void) +{ + return 0; +} + +int misc_init_r(void) +{ + u8 mac_addr[EFUSE_MAC_SIZE]; + char serial[EFUSE_SN_SIZE]; + ssize_t len; + + meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, + MESON_GXL_USE_INTERNAL_RMII_PHY); + + /* Enable power and clock gate */ + setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); + clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); + + if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { + len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, + mac_addr, EFUSE_MAC_SIZE); + if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); + } + + if (!env_get("serial#")) { + len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, + EFUSE_SN_SIZE); + if (len == EFUSE_SN_SIZE) + env_set("serial#", serial); + } + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + meson_gx_init_reserved_memory(blob); + + return 0; +} diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c index a5ea8dc5af2..0cb571432f0 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -9,7 +9,8 @@ #include <asm/io.h> #include <asm/arch/gxbb.h> #include <asm/arch/sm.h> -#include <phy.h> +#include <asm/arch/eth.h> +#include <asm/arch/mem.h> #define EFUSE_SN_OFFSET 20 #define EFUSE_SN_SIZE 16 @@ -27,17 +28,10 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - /* Set RGMII mode */ - setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | - GXBB_ETH_REG_0_TX_PHASE(1) | - GXBB_ETH_REG_0_TX_RATIO(4) | - GXBB_ETH_REG_0_PHY_CLK_EN | - GXBB_ETH_REG_0_CLK_EN); + meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); /* Enable power and clock gate */ setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C); - setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); - clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); /* Reset PHY on GPIOZ_14 */ clrbits_le32(GXBB_GPIO_EN(3), BIT(14)); @@ -61,3 +55,10 @@ int misc_init_r(void) return 0; } + +int ft_board_setup(void *blob, bd_t *bd) +{ + meson_gx_init_reserved_memory(blob); + + return 0; +} diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index ece8096c5cc..5fde53438ec 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -10,7 +10,8 @@ #include <asm/io.h> #include <asm/arch/gxbb.h> #include <asm/arch/sm.h> -#include <phy.h> +#include <asm/arch/eth.h> +#include <asm/arch/mem.h> #define EFUSE_SN_OFFSET 20 #define EFUSE_SN_SIZE 16 @@ -28,17 +29,7 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - /* Set RMII mode */ - out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK | - GXBB_ETH_REG_0_CLK_EN); - - /* Use Internal PHY */ - out_le32(GXBB_ETH_REG_2, 0x10110181); - out_le32(GXBB_ETH_REG_3, 0xe40908ff); - - /* Enable power and clock gate */ - setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); - clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); + meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, 0); if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, @@ -56,3 +47,10 @@ int misc_init_r(void) return 0; } + +int ft_board_setup(void *blob, bd_t *bd) +{ + meson_gx_init_reserved_memory(blob); + + return 0; +} diff --git a/board/atmel/sama5d2_ptc/MAINTAINERS b/board/atmel/sama5d2_ptc/MAINTAINERS deleted file mode 100644 index 7ab03d6eafa..00000000000 --- a/board/atmel/sama5d2_ptc/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SAMA5D2 PTC Engineering BOARD -M: Wenyou Yang <wenyou.yang@atmel.com> -S: Maintained -F: board/atmel/sama5d2_ptc/ -F: include/configs/sama5d2_ptc.h -F: configs/sama5d2_ptc_spiflash_defconfig -F: configs/sama5d2_ptc_nandflash_defconfig diff --git a/board/atmel/sama5d2_ptc/Makefile b/board/atmel/sama5d2_ptc/Makefile deleted file mode 100644 index 1fe0392da09..00000000000 --- a/board/atmel/sama5d2_ptc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2016 Atmel -# Wenyou Yang <wenyou.yang@atmel.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += sama5d2_ptc.o diff --git a/board/atmel/sama5d2_ptc/sama5d2_ptc.c b/board/atmel/sama5d2_ptc/sama5d2_ptc.c deleted file mode 100644 index c441e69ee42..00000000000 --- a/board/atmel/sama5d2_ptc/sama5d2_ptc.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (C) 2016 Atmel - * Wenyou.Yang <wenyou.yang@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <atmel_hlcdc.h> -#include <lcd.h> -#include <mmc.h> -#include <net.h> -#include <netdev.h> -#include <spi.h> -#include <version.h> -#include <asm/io.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/atmel_pio4.h> -#include <asm/arch/atmel_mpddrc.h> -#include <asm/arch/atmel_usba_udc.h> -#include <asm/arch/atmel_sdhci.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/arch/sama5_sfr.h> -#include <asm/arch/sama5d2.h> -#include <asm/arch/sama5d3_smc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); -} - -static void board_spi0_hw_init(void) -{ - atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); - atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); - atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); - - atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); - - at91_periph_clk_enable(ATMEL_ID_SPI0); -} - -static void board_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; - - at91_periph_clk_enable(ATMEL_ID_HSMC); - - writel(AT91_SFR_EBICFG_DRIVE0_HIGH | - AT91_SFR_EBICFG_PULL0_NONE | - AT91_SFR_EBICFG_DRIVE1_HIGH | - AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg); - - /* Configure SMC CS3 for NAND */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | - AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | - AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) | - AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(3), - &smc->cs[3].mode); - - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */ - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */ -} - -static void board_usb_hw_init(void) -{ - atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1); -} - -static void board_gmac_hw_init(void) -{ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ - - at91_periph_clk_enable(ATMEL_ID_GMAC); -} - -static void board_uart0_hw_init(void) -{ - atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */ - atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ - - at91_periph_clk_enable(CONFIG_USART_ID); -} - -int board_early_init_f(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - - board_uart0_hw_init(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_ATMEL_SPI - board_spi0_hw_init(); -#endif -#ifdef CONFIG_NAND_ATMEL - board_nand_hw_init(); -#endif -#ifdef CONFIG_MACB - board_gmac_hw_init(); -#endif -#ifdef CONFIG_CMD_USB - board_usb_hw_init(); -#endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); - if (rc) - printf("GMAC register failed\n"); -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - -/* SPL */ -#ifdef CONFIG_SPL_BUILD -void spl_board_init(void) -{ -#ifdef CONFIG_SPI_BOOT - board_spi0_hw_init(); -#endif - -#ifdef CONFIG_NAND_BOOT - board_nand_hw_init(); -#endif -} - -static void ddrc_conf(struct atmel_mpddrc_config *ddrc) -{ - ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); - - ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | - ATMEL_MPDDRC_CR_NR_ROW_14 | - ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | - ATMEL_MPDDRC_CR_DIC_DS | - ATMEL_MPDDRC_CR_DIS_DLL | - ATMEL_MPDDRC_CR_NB_8BANKS | - ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | - ATMEL_MPDDRC_CR_UNAL_SUPPORTED); - - ddrc->rtr = 0x511; - - ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | - (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | - (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | - (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | - (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | - (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | - (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | - (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); - - ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | - (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | - (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | - (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); - - ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | - (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | - (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | - (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | - (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); -} - -void mem_init(void) -{ - struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; - struct atmel_mpddrc_config ddrc_config; - u32 reg; - - ddrc_conf(&ddrc_config); - - at91_periph_clk_enable(ATMEL_ID_MPDDRC); - at91_system_clk_enable(AT91_PMC_DDR); - - reg = readl(&mpddrc->io_calibr); - reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; - reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; - reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; - reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); - writel(reg, &mpddrc->io_calibr); - - writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, - &mpddrc->rd_data_path); - - ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); - - writel(0x3, &mpddrc->cal_mr4); - writel(64, &mpddrc->tim_cal); -} - -void at91_pmc_init(void) -{ - at91_plla_init(AT91_PMC_PLLAR_29 | - AT91_PMC_PLLXR_PLLCOUNT(0x3f) | - AT91_PMC_PLLXR_MUL(82) | - AT91_PMC_PLLXR_DIV(1)); - - at91_pllicpr_init(0); - - at91_mck_init(AT91_PMC_MCKR_H32MXDIV | - AT91_PMC_MCKR_PLLADIV_2 | - AT91_PMC_MCKR_MDIV_3 | - AT91_PMC_MCKR_CSS_PLLA); -} -#endif diff --git a/board/atmel/sama5d2_ptc/Kconfig b/board/atmel/sama5d2_ptc_ek/Kconfig index d2661c689a2..8b202d6ccfc 100644 --- a/board/atmel/sama5d2_ptc/Kconfig +++ b/board/atmel/sama5d2_ptc_ek/Kconfig @@ -1,7 +1,7 @@ -if TARGET_SAMA5D2_PTC +if TARGET_SAMA5D2_PTC_EK config SYS_BOARD - default "sama5d2_ptc" + default "sama5d2_ptc_ek" config SYS_VENDOR default "atmel" @@ -10,6 +10,6 @@ config SYS_SOC default "at91" config SYS_CONFIG_NAME - default "sama5d2_ptc" + default "sama5d2_ptc_ek" endif diff --git a/board/atmel/sama5d2_ptc_ek/MAINTAINERS b/board/atmel/sama5d2_ptc_ek/MAINTAINERS new file mode 100644 index 00000000000..3c7b7f51c61 --- /dev/null +++ b/board/atmel/sama5d2_ptc_ek/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D2 PTC EK BOARD +M: Wenyou Yang <wenyou.yang@microchip.com> +M: Ludovic Desroches <ludovic.desroches@microchip.com> +S: Maintained +F: board/atmel/sama5d2_ptc_ek/ +F: include/configs/sama5d2_ptc_ek.h +F: configs/sama5d2_ptc_ek_mmc_defconfig +F: configs/sama5d2_ptc_ek_nandflash_defconfig diff --git a/board/atmel/sama5d2_ptc_ek/Makefile b/board/atmel/sama5d2_ptc_ek/Makefile new file mode 100644 index 00000000000..9fe4b410a1a --- /dev/null +++ b/board/atmel/sama5d2_ptc_ek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Microchip Corporation +# Wenyou Yang <wenyou.yang@microchip.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d2_ptc_ek.o diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c new file mode 100644 index 00000000000..4c2e20977e5 --- /dev/null +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2017 Microchip Corporation + * Wenyou Yang <wenyou.yang@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <i2c.h> +#include <nand.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> +#include <asm/arch/sama5d2_smc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_NAND_ATMEL +static void board_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_HSMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) | + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, 0); /* D0 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, 0); /* D1 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, 0); /* D2 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, 0); /* D3 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, 0); /* D4 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, 0); /* D5 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, 0); /* D6 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, 0); /* D7 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */ + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, 1); /* NCS */ + atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, 1); /* RDY */ + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, 1); /* ALE */ + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, 1); /* CLE */ +} +#endif + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1); +} + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(ATMEL_ID_UART0); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + board_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#define AT24MAC_MAC_OFFSET 0xfa + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(AT24MAC_MAC_OFFSET); +#endif + return 0; +} +#endif diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index 32168d35768..3d74a6dfb89 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -52,7 +52,7 @@ static struct hws_topology_map ddr_topology_map = { BUS_WIDTH_16, /* memory_width */ MEM_4G, /* mem_size */ DDR_FREQ_533, /* frequency */ - 0, 0, /* cas_l cas_wl */ + 0, 0, /* cas_wl cas_l */ HWS_TEMP_LOW, /* temperature */ HWS_TIM_DEFAULT} }, /* timing */ 5, /* Num Of Bus Per Interface*/ diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig new file mode 100644 index 00000000000..2a67337293e --- /dev/null +++ b/board/laird/wb45n/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WB45N + +config SYS_BOARD + default "wb45n" + +config SYS_VENDOR + default "laird" + +config SYS_CONFIG_NAME + default "wb45n" + +endif diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS new file mode 100644 index 00000000000..60bb5632010 --- /dev/null +++ b/board/laird/wb45n/MAINTAINERS @@ -0,0 +1,6 @@ +WB45N CPU MODULE +M: Ben Whitten <ben.whitten@lairdtech.com> +S: Maintained +F: board/laird/wb45n/ +F: include/configs/wb45n.h +F: configs/wb45n_defconfig diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile new file mode 100644 index 00000000000..fc645ddc539 --- /dev/null +++ b/board/laird/wb45n/Makefile @@ -0,0 +1,6 @@ +# +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += wb45n.o diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c new file mode 100644 index 00000000000..59140716475 --- /dev/null +++ b/board/laird/wb45n/wb45n.c @@ -0,0 +1,199 @@ +/* + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <net.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ +static void wb45n_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + csa = readl(&matrix->ebicsa); + /* Enable CS3 */ + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + /* NAND flash on D0 */ + csa &= ~AT91_MATRIX_NFD0_ON_D16; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOCD); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + /* Disable Flash Write Protect Line */ + at91_set_gpio_output(AT91_PIN_PD10, 1); + + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ +} + +static void wb45n_gpio_hw_init(void) +{ + + /* Configure wifi gpio CHIP_PWD_L */ + at91_set_gpio_output(AT91_PIN_PA28, 0); + + /* Setup USB pins */ + at91_set_gpio_input(AT91_PIN_PB11, 0); + at91_set_gpio_output(AT91_PIN_PB12, 0); + + /* IRQ pin, pullup, deglitch */ + at91_set_gpio_input(AT91_PIN_PB18, 1); + at91_set_gpio_deglitch(AT91_PIN_PB18, 1); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + if (has_emac0()) + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); + + return rc; +} + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + wb45n_gpio_hw_init(); + + wb45n_nand_hw_init(); + + at91_macb_hw_init(); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ + /* Setup GPIO first */ + wb45n_gpio_hw_init(); + + /* Bring up NAND */ + wb45n_nand_hw_init(); +} + +void matrix_init(void) +{ + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + csa = readl(&matrix->ebicsa); + /* Pull ups on D0 - D16 */ + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; + csa |= AT91_MATRIX_EBI_DBPD_OFF; + /* Normal drive strength */ + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + /* Multi-port off */ + csa &= ~AT91_MATRIX_MP_ON; + writel(csa, &matrix->ebicsa); +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_DQMS_SHARED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddrc_config ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + at91_system_clk_enable(AT91_PMC_DDR); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + writel(csa, &matrix->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); +} +#endif diff --git a/board/laird/wb50n/Kconfig b/board/laird/wb50n/Kconfig new file mode 100644 index 00000000000..2e7090ec34b --- /dev/null +++ b/board/laird/wb50n/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WB50N + +config SYS_BOARD + default "wb50n" + +config SYS_VENDOR + default "laird" + +config SYS_CONFIG_NAME + default "wb50n" + +endif diff --git a/board/laird/wb50n/MAINTAINERS b/board/laird/wb50n/MAINTAINERS new file mode 100644 index 00000000000..3d38fc4e9fa --- /dev/null +++ b/board/laird/wb50n/MAINTAINERS @@ -0,0 +1,6 @@ +WB50N CPU MODULE +M: Ben Whitten <ben.whitten@lairdtech.com> +S: Maintained +F: board/laird/wb50n/ +F: include/configs/wb50n.h +F: configs/wb50n_defconfig diff --git a/board/laird/wb50n/Makefile b/board/laird/wb50n/Makefile new file mode 100644 index 00000000000..d1b6cfa291f --- /dev/null +++ b/board/laird/wb50n/Makefile @@ -0,0 +1,6 @@ +# +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += wb50n.o diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c new file mode 100644 index 00000000000..8896e620735 --- /dev/null +++ b/board/laird/wb50n/wb50n.c @@ -0,0 +1,206 @@ +/* + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sama5_sfr.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <micrel.h> +#include <net.h> +#include <netdev.h> +#include <spl.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/at91_wdt.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +void wb50n_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | + AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | + AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) | + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); + + /* Disable Flash Write Protect Line */ + at91_set_pio_output(AT91_PIO_PORTE, 14, 1); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + wb50n_nand_hw_init(); + + at91_macb_hw_init(); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); + /* tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); + /* rx/tx clock delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); + + return rc; +} + +#ifdef CONFIG_BOARD_LATE_INIT +#include <linux/ctype.h> +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + const char *LAIRD_NAME = "lrd_name"; + char name[32], *p; + + strcpy(name, get_cpu_name()); + for (p = name; *p != '\0'; *p = tolower(*p), p++) + ; + strcat(name, "-wb50n"); + env_set(LAIRD_NAME, name); + +#endif + + return 0; +} +#endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ + wb50n_nand_hw_init(); +} + +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + struct atmel_mpddrc_config ddr2; + + ddr2_conf(&ddr2); + + writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN, + &sfr->ddrcfg); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + at91_system_clk_enable(AT91_PMC_DDR); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); + + tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 530f1496171..3b7a54f519d 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -105,6 +105,11 @@ static const struct rpi_model rpi_models_new_scheme[] = { DTB_DIR "bcm2835-rpi-zero.dtb", false, }, + [0xC] = { + "Zero W", + DTB_DIR "bcm2835-rpi-zero-w.dtb", + false, + }, }; static const struct rpi_model rpi_models_old_scheme[] = { diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile index 61b0d063e59..5b4dea91c14 100644 --- a/board/renesas/salvator-x/Makefile +++ b/board/renesas/salvator-x/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := salvator-x.o ../rcar-common/common.o +obj-y := salvator-x.o diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index debd1db7214..882a35c1400 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -79,17 +79,19 @@ int board_early_init_f(void) int board_init(void) { + u32 cpu_type = rmobile_get_cpu_type(); + /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; -#if defined(CONFIG_R8A7795) - /* GSX: force power and clock supply */ - writel(0x0000001F, SYSC_PWRONCR2); - while (readl(SYSC_PWRSR2) != 0x000003E0) - mdelay(20); + if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) { + /* GSX: force power and clock supply */ + writel(0x0000001F, SYSC_PWRONCR2); + while (readl(SYSC_PWRSR2) != 0x000003E0) + mdelay(20); - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); -#endif + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); + } /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); @@ -107,43 +109,19 @@ int board_init(void) int dram_init(void) { - gd->ram_size = PHYS_SDRAM_1_SIZE; -#if (CONFIG_NR_DRAM_BANKS >= 2) - gd->ram_size += PHYS_SDRAM_2_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 3) - gd->ram_size += PHYS_SDRAM_3_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 4) - gd->ram_size += PHYS_SDRAM_4_SIZE; -#endif + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#if (CONFIG_NR_DRAM_BANKS >= 2) - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 3) - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 4) - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -#endif + fdtdec_setup_memory_banksize(); + return 0; } -const struct rmobile_sysinfo sysinfo = { - CONFIG_RCAR_BOARD_STRING -}; - #define RST_BASE 0xE6160000 #define RST_CA57RESCNT (RST_BASE + 0x40) #define RST_CA53RESCNT (RST_BASE + 0x44) diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile index 6fe0b480f77..406fdc8fa40 100644 --- a/board/renesas/ulcb/Makefile +++ b/board/renesas/ulcb/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := ulcb.o cpld.o ../rcar-common/common.o +obj-y := ulcb.o cpld.o diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c index a1fecf18e5e..50de56837e6 100644 --- a/board/renesas/ulcb/cpld.c +++ b/board/renesas/ulcb/cpld.c @@ -8,14 +8,12 @@ */ #include <common.h> -#include <spi.h> -#include <asm/io.h> #include <asm/gpio.h> - -#define SCLK (192 + 8) /* GPIO6 8 */ -#define SSTBZ (64 + 3) /* GPIO2 3 */ -#define MOSI (192 + 7) /* GPIO6 8 */ -#define MISO (192 + 10) /* GPIO6 10 */ +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <linux/err.h> +#include <sysreset.h> #define CPLD_ADDR_MODE 0x00 /* RW */ #define CPLD_ADDR_MUX 0x02 /* RW */ @@ -23,111 +21,89 @@ #define CPLD_ADDR_RESET 0x80 /* RW */ #define CPLD_ADDR_VERSION 0xFF /* R */ -static int cpld_initialized; - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* Always valid */ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* Always active */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* Always active */ -} - -void ulcb_softspi_sda(int set) -{ - gpio_set_value(MOSI, set); -} +struct renesas_ulcb_sysreset_priv { + struct gpio_desc miso; + struct gpio_desc mosi; + struct gpio_desc sck; + struct gpio_desc sstbz; +}; -void ulcb_softspi_scl(int set) -{ - gpio_set_value(SCLK, set); -} - -unsigned char ulcb_softspi_read(void) -{ - return !!gpio_get_value(MISO); -} - -static void cpld_rw(u8 write) -{ - gpio_set_value(MOSI, write); - gpio_set_value(SSTBZ, 0); - gpio_set_value(SCLK, 1); - gpio_set_value(SCLK, 0); - gpio_set_value(SSTBZ, 1); -} - -static u32 cpld_read(u8 addr) +static u32 cpld_read(struct udevice *dev, u8 addr) { + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); u32 data = 0; + int i; - spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END); - - cpld_rw(0); - - spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END); - - return swab32(data); -} - -static void cpld_write(u8 addr, u32 data) -{ - data = swab32(data); - - spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + for (i = 0; i < 8; i++) { + dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + addr <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END); + dm_gpio_set_value(&priv->mosi, 0); /* READ */ + dm_gpio_set_value(&priv->sstbz, 0); + dm_gpio_set_value(&priv->sck, 1); + dm_gpio_set_value(&priv->sck, 0); + dm_gpio_set_value(&priv->sstbz, 1); + + for (i = 0; i < 32; i++) { + dm_gpio_set_value(&priv->sck, 1); + data <<= 1; + data |= dm_gpio_get_value(&priv->miso); /* MSB first */ + dm_gpio_set_value(&priv->sck, 0); + } - cpld_rw(1); + return data; } -static void cpld_init(void) +static void cpld_write(struct udevice *dev, u8 addr, u32 data) { - if (cpld_initialized) - return; - - /* PULL-UP on MISO line */ - setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); - - gpio_request(SCLK, NULL); - gpio_request(SSTBZ, NULL); - gpio_request(MOSI, NULL); - gpio_request(MISO, NULL); - - gpio_direction_output(SCLK, 0); - gpio_direction_output(SSTBZ, 1); - gpio_direction_output(MOSI, 0); - gpio_direction_input(MISO); + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < 32; i++) { + dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + data <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - /* Dummy read */ - cpld_read(CPLD_ADDR_VERSION); + for (i = 0; i < 8; i++) { + dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + addr <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - cpld_initialized = 1; + dm_gpio_set_value(&priv->mosi, 1); /* WRITE */ + dm_gpio_set_value(&priv->sstbz, 0); + dm_gpio_set_value(&priv->sck, 1); + dm_gpio_set_value(&priv->sck, 0); + dm_gpio_set_value(&priv->sstbz, 1); } static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; u32 addr, val; + int ret; - cpld_init(); + ret = uclass_get_device_by_driver(UCLASS_SYSRESET, + DM_GET_DRIVER(sysreset_renesas_ulcb), + &dev); + if (ret) + return ret; if (argc == 2 && strcmp(argv[1], "info") == 0) { printf("CPLD version:\t\t\t0x%08x\n", - cpld_read(CPLD_ADDR_VERSION)); + cpld_read(dev, CPLD_ADDR_VERSION)); printf("H3 Mode setting (MD0..28):\t0x%08x\n", - cpld_read(CPLD_ADDR_MODE)); + cpld_read(dev, CPLD_ADDR_MODE)); printf("Multiplexer settings:\t\t0x%08x\n", - cpld_read(CPLD_ADDR_MUX)); + cpld_read(dev, CPLD_ADDR_MUX)); printf("DIPSW (SW6):\t\t\t0x%08x\n", - cpld_read(CPLD_ADDR_DIPSW6)); + cpld_read(dev, CPLD_ADDR_DIPSW6)); return 0; } @@ -143,10 +119,10 @@ static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (argc == 3 && strcmp(argv[1], "read") == 0) { - printf("0x%x\n", cpld_read(addr)); + printf("0x%x\n", cpld_read(dev, addr)); } else if (argc == 4 && strcmp(argv[1], "write") == 0) { val = simple_strtoul(argv[3], NULL, 16); - cpld_write(addr, val); + cpld_write(dev, addr, val); } return 0; @@ -160,8 +136,56 @@ U_BOOT_CMD( "cpld write addr val\n" ); -void reset_cpu(ulong addr) +static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + cpld_write(dev, CPLD_ADDR_RESET, 1); + + return -EINPROGRESS; +} + +static int renesas_ulcb_sysreset_probe(struct udevice *dev) { - cpld_init(); - cpld_write(CPLD_ADDR_RESET, 1); + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); + + if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso, + GPIOD_IS_IN)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck, + GPIOD_IS_OUT)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi, + GPIOD_IS_OUT)) + return -EINVAL; + + /* PULL-UP on MISO line */ + setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); + + /* Dummy read */ + cpld_read(dev, CPLD_ADDR_VERSION); + + return 0; } + +static struct sysreset_ops renesas_ulcb_sysreset = { + .request = renesas_ulcb_sysreset_request, +}; + +static const struct udevice_id renesas_ulcb_sysreset_ids[] = { + { .compatible = "renesas,ulcb-cpld" }, + { } +}; + +U_BOOT_DRIVER(sysreset_renesas_ulcb) = { + .name = "renesas_ulcb_sysreset", + .id = UCLASS_SYSRESET, + .ops = &renesas_ulcb_sysreset, + .probe = renesas_ulcb_sysreset_probe, + .of_match = renesas_ulcb_sysreset_ids, + .priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv), +}; diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index ca1b71975b3..ed891c833c3 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -97,39 +97,15 @@ int board_init(void) int dram_init(void) { - gd->ram_size = PHYS_SDRAM_1_SIZE; -#if (CONFIG_NR_DRAM_BANKS >= 2) - gd->ram_size += PHYS_SDRAM_2_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 3) - gd->ram_size += PHYS_SDRAM_3_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 4) - gd->ram_size += PHYS_SDRAM_4_SIZE; -#endif + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#if (CONFIG_NR_DRAM_BANKS >= 2) - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 3) - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; -#endif -#if (CONFIG_NR_DRAM_BANKS >= 4) - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -#endif + fdtdec_setup_memory_banksize(); + return 0; } - -const struct rmobile_sysinfo sysinfo = { - CONFIG_RCAR_BOARD_STRING -}; diff --git a/board/rockchip/evb_rk3128/Kconfig b/board/rockchip/evb_rk3128/Kconfig new file mode 100644 index 00000000000..5b3095ade99 --- /dev/null +++ b/board/rockchip/evb_rk3128/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3128 + +config SYS_BOARD + default "evb_rk3128" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3128" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3128/MAINTAINERS b/board/rockchip/evb_rk3128/MAINTAINERS new file mode 100644 index 00000000000..f5145d1f041 --- /dev/null +++ b/board/rockchip/evb_rk3128/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3128 +M: Kever Yang <kever.yang@rock-chips.com> +S: Maintained +F: board/rockchip/evb_rk3128 +F: include/configs/evb_rk3128.h +F: configs/evb-rk3128_defconfig diff --git a/board/rockchip/evb_rk3128/Makefile b/board/rockchip/evb_rk3128/Makefile new file mode 100644 index 00000000000..078bb898c68 --- /dev/null +++ b/board/rockchip/evb_rk3128/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evk-rk3128.o diff --git a/board/rockchip/evb_rk3128/evk-rk3128.c b/board/rockchip/evb_rk3128/evk-rk3128.c new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/board/rockchip/evb_rk3128/evk-rk3128.c diff --git a/board/rockchip/evb_rv1108/README b/board/rockchip/evb_rv1108/README index 58895960e98..79a97c31385 100644 --- a/board/rockchip/evb_rv1108/README +++ b/board/rockchip/evb_rv1108/README @@ -3,12 +3,11 @@ Here is the step-by-step to boot U-Boot on rv1108 evb. Get ddr init binary ============================================================================== > git clone https://github.com/rockchip-linux/rkbin.git - > dd if=./rkbin/rv1x/rv1108ddr.bin of=ddr.bin bs=4 skip=1 Compile U-Boot =========================== > make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig all - > ./tools/mkimage -n rv1108 -T rksd -d ddr.bin spl.bin + > ./tools/mkimage -n rv1108 -T rksd -d ../rkbin/rv1x/rv1108ddr_v1.00.bin spl.bin > cat spl.bin u-boot.bin > u-boot.img Flash the image by rkdeveloptool @@ -16,7 +15,7 @@ Flash the image by rkdeveloptool rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: - > rkdeveloptool db ./rkbin/rv1x/RV1108_usb_boot.bin + > rkdeveloptool db ./rkbin/rv1x/rv1108usbboot_v1.00.bin > rkdeveloptool wl 0x40 u-boot.img > rkdeveloptool RD diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 8906636f764..1472e9793e5 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -82,7 +82,7 @@ static struct hws_topology_map board_topology_map = { BUS_WIDTH_16, /* memory_width */ MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ - 0, 0, /* cas_l cas_wl */ + 0, 0, /* cas_wl cas_l */ HWS_TEMP_LOW, /* temperature */ HWS_TIM_DEFAULT} }, /* timing */ 5, /* Num Of Bus Per Interface*/ diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index d6763c306f8..1c34a8efe14 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -13,6 +13,7 @@ #include <common.h> #include <dm.h> +#include <stm32_rcc.h> #include <asm/io.h> #include <asm/armv7m.h> #include <asm/arch/stm32.h> @@ -293,6 +294,8 @@ int board_early_init_f(void) { int res; + configure_clocks(); + res = uart_setup_gpio(); if (res) return res; diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 2b4988e2d22..0ad267cdd07 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -7,12 +7,16 @@ #include <common.h> #include <dm.h> #include <misc.h> +#include <spl.h> +#include <usb.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> +#include <asm/gpio.h> #include <asm/setup.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3399.h> #include <asm/arch/periph.h> #include <power/regulator.h> -#include <spl.h> #include <u-boot/sha256.h> DECLARE_GLOBAL_DATA_PTR; @@ -32,9 +36,50 @@ int board_init(void) return 0; } +static void rk3399_force_power_on_reset(void) +{ + ofnode node; + struct gpio_desc sysreset_gpio; + + debug("%s: trying to force a power-on reset\n", __func__); + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + + if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, + &sysreset_gpio, GPIOD_IS_OUT)) { + debug("%s: could not find a /config/sysreset-gpio\n", __func__); + return; + } + + dm_gpio_set_value(&sysreset_gpio, 1); +} + void spl_board_init(void) { int ret; + struct rk3399_cru *cru = rockchip_get_cru(); + + /* + * The RK3399 resets only 'almost all logic' (see also in the TRM + * "3.9.4 Global software reset"), when issuing a software reset. + * This may cause issues during boot-up for some configurations of + * the application software stack. + * + * To work around this, we test whether the last reset reason was + * a power-on reset and (if not) issue an overtemp-reset to reset + * the entire module. + * + * While this was previously fixed by modifying the various places + * that could generate a software reset (e.g. U-Boot's sysreset + * driver, the ATF or Linux), we now have it here to ensure that + * we no longer have to track this through the various components. + */ + if (cru->glb_rst_st != 0) + rk3399_force_power_on_reset(); /* * Turning the eMMC and SPI back on (if disabled via the Qseven @@ -158,3 +203,70 @@ void get_board_serial(struct tag_serialnr *serialnr) serialnr->low = (u32)(serial & 0xffffffff); } #endif + +/** + * Switch power at an external regulator (for our root hub). + * + * @param ctrl pointer to the xHCI controller + * @param port port number as in the control message (one-based) + * @param enable boolean indicating whether to enable or disable power + * @return returns 0 on success, an error-code on failure + */ +static int board_usb_port_power_set(struct udevice *dev, int port, + bool enable) +{ +#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_REGULATOR) + /* We start counting ports at 0, while USB counts from 1. */ + int index = port - 1; + const char *regname = NULL; + struct udevice *regulator; + const char *prop = "tsd,usb-port-power"; + int ret; + + debug("%s: ctrl '%s' port %d enable %s\n", __func__, + dev_read_name(dev), port, enable ? "true" : "false"); + + ret = dev_read_string_index(dev, prop, index, ®name); + if (ret < 0) { + debug("%s: ctrl '%s' port %d: no entry in '%s'\n", + __func__, dev_read_name(dev), port, prop); + return ret; + } + + ret = regulator_get_by_platname(regname, ®ulator); + if (ret) { + debug("%s: ctrl '%s' port %d: could not get regulator '%s'\n", + __func__, dev_read_name(dev), port, regname); + return ret; + } + + regulator_set_enable(regulator, enable); + return 0; +#else + return -ENOTSUPP; +#endif +} + +void usb_hub_reset_devices(struct usb_hub_device *hub, int port) +{ + struct udevice *dev = hub->pusb_dev->dev; + struct udevice *ctrl; + + /* We are only interested in our root-hubs */ + if (usb_hub_is_root_hub(dev) == false) + return; + + ctrl = usb_get_bus(dev); + if (!ctrl) { + debug("%s: could not retrieve ctrl for hub\n", __func__); + return; + } + + /* + * To work around an incompatibility between the single-threaded + * USB stack in U-Boot and (a strange low-power mode of) the USB + * hub we have on-module, we need to delay powering on the hub + * until the first time the port is probed. + */ + board_usb_port_power_set(ctrl, port, true); +} diff --git a/cmd/blk_common.c b/cmd/blk_common.c index 0c0c23eb370..bf2f626dd65 100644 --- a/cmd/blk_common.c +++ b/cmd/blk_common.c @@ -95,8 +95,6 @@ int blk_common_cmd(int argc, char * const argv[], enum if_type if_type, } else { return CMD_RET_USAGE; } - - return 0; } } #endif diff --git a/common/command.c b/common/command.c index e5d9b9cf959..21a6d409fba 100644 --- a/common/command.c +++ b/common/command.c @@ -318,7 +318,7 @@ static int find_common_prefix(char * const argv[]) return len; } -static char tmp_buf[CONFIG_SYS_CBSIZE]; /* copy of console I/O buffer */ +static char tmp_buf[CONFIG_SYS_CBSIZE + 1]; /* copy of console I/O buffer */ int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp) { diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig index a3a40bf1e9b..600566955a3 100644 --- a/configs/adp-ae3xx_defconfig +++ b/configs/adp-ae3xx_defconfig @@ -27,12 +27,15 @@ CONFIG_CFI_FLASH=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_MMC=y +CONFIG_MMC_NDS32=y +CONFIG_FTSDC010=y CONFIG_DM_ETH=y CONFIG_FTMAC100=y CONFIG_BAUDRATE=38400 CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y -CONFIG_NDS_AE3XX_SPI=y +CONFIG_ATCSPI200_SPI=y CONFIG_TIMER=y -CONFIG_AE3XX_TIMER=y +CONFIG_ATCPIT100_TIMER=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 5cf2d265525..82cf7f2481e 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -18,6 +18,9 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_NDS32=y +CONFIG_FTSDC010=y CONFIG_MTD_NOR_FLASH=y CONFIG_DM_ETH=y CONFIG_FTMAC100=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 59bde05c806..535bfe411d4 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -6,6 +6,7 @@ CONFIG_INTERNAL_UART=y CONFIG_DEBUG_UART=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y +CONFIG_VGA_BIOS_ADDR=0xfffb0000 CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig new file mode 100644 index 00000000000..7c2a607e901 --- /dev/null +++ b/configs/evb-rk3128_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3128=y +CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3128=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_BASE=0x20068000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Rockchip" +CONFIG_G_DNL_VENDOR_NUM=0x2207 +CONFIG_G_DNL_PRODUCT_NUM=0x310c +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig new file mode 100644 index 00000000000..f2a30a83e9b --- /dev/null +++ b/configs/khadas-vim_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_MESON_GXL=y +CONFIG_TARGET_KHADAS_VIM=y +CONFIG_IDENT_STRING=" khadas-vim" +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim" +CONFIG_DEBUG_UART=y +CONFIG_ENV_IS_NOWHERE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY_MESON_GXL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig new file mode 100644 index 00000000000..6583c43c855 --- /dev/null +++ b/configs/libretech-cc_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_MESON_GXL=y +CONFIG_TARGET_LIBRETECH_CC=y +CONFIG_IDENT_STRING=" libretech-cc" +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc" +CONFIG_DEBUG_UART=y +CONFIG_ENV_IS_NOWHERE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY_MESON_GXL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 1afd2fc1113..18d2b6825d5 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -16,6 +16,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_SETUP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index f67bcb18953..0c513664fea 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -6,8 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SYS_MPUCLK=720 CONFIG_TARGET_OMAP3_EVM=y CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/p212_defconfig b/configs/p212_defconfig index d4b534954ee..b6e788b0989 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_SETUP=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index e32aceba549..5a09473efaf 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -13,8 +13,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -26,10 +26,14 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y CONFIG_PHY_MICREL=y @@ -45,6 +49,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index 50d36891cc3..0959bb44c97 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -25,12 +26,18 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y CONFIG_PINCTRL=y @@ -40,8 +47,10 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 8f22645efbd..9055c291bb2 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -14,8 +14,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -27,10 +27,14 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y CONFIG_PHY_MICREL=y @@ -46,6 +50,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index c8edfabc911..fe0b4fc93d3 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -26,12 +27,18 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_UNIPHIER=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y CONFIG_PINCTRL=y @@ -41,8 +48,10 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig new file mode 100644 index 00000000000..092f378f9fa --- /dev/null +++ b/configs/rpi_0_w_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_ARCH_BCM283X=y +CONFIG_TARGET_RPI_0_W=y +CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="U-Boot> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_DM_ETH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_CONSOLE_SCROLL_LINES=10 +CONFIG_PHYS_TO_BUS=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig new file mode 100644 index 00000000000..03dc69b3d84 --- /dev/null +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_PTC_EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_CONSOLE_MUX=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xf801c000 +CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig new file mode 100644 index 00000000000..8340f818d6d --- /dev/null +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_PTC_EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH" +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_CONSOLE_MUX=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xf801c000 +CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig deleted file mode 100644 index cfbdbb00251..00000000000 --- a/configs/sama5d2_ptc_nandflash_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_SAMA5D2_PTC=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_NAND_BOOT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_NAND=y -# CONFIG_MMC is not set -CONFIG_SPI_FLASH=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Atmel SAMA5D2_PTC" -CONFIG_USB_GADGET_ATMEL_USBA=y -CONFIG_USB_ETHER=y diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig deleted file mode 100644 index 25ee07740ec..00000000000 --- a/configs/sama5d2_ptc_spiflash_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_SAMA5D2_PTC=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPI_BOOT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -# CONFIG_MMC is not set -CONFIG_SPI_FLASH=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Atmel SAMA5D2_PTC" -CONFIG_USB_GADGET_ATMEL_USBA=y -CONFIG_USB_ETHER=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 378cf83d1f9..b6617611264 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -30,6 +30,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_CLK=y CONFIG_DM_GPIO=y +CONFIG_MISC=y +CONFIG_STM32_RCC=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -43,6 +45,8 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_STM32=y CONFIG_RAM=y CONFIG_STM32_SDRAM=y +CONFIG_DM_RESET=y +CONFIG_STM32_RESET=y CONFIG_STM32X7_SERIAL=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig new file mode 100644 index 00000000000..6cf41df0e53 --- /dev/null +++ b/configs/wb45n_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_WB45N=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_LZMA=y +CONFIG_OF_LIBFDT=y diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig new file mode 100644 index 00000000000..1f3e41e5c60 --- /dev/null +++ b/configs/wb50n_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_WB50N=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_NETDEVICES=y +CONFIG_LZMA=y +CONFIG_OF_LIBFDT=y diff --git a/disk/part_efi.c b/disk/part_efi.c index f6f5bee8cd8..bea8b20bbd1 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -350,7 +350,7 @@ static int part_test_efi(struct blk_desc *dev_desc) static int set_protective_mbr(struct blk_desc *dev_desc) { /* Setup the Protective MBR */ - ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, p_mbr, 1); + ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, p_mbr, 1, dev_desc->blksz); memset(p_mbr, 0, sizeof(*p_mbr)); if (p_mbr == NULL) { @@ -931,7 +931,7 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, return 0; } - ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr, dev_desc->blksz); + ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, mbr, 1, dev_desc->blksz); /* Read MBR Header from device */ if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1) { diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt index 15e4349c19a..6cdc16da5b5 100644 --- a/doc/device-tree-bindings/config.txt +++ b/doc/device-tree-bindings/config.txt @@ -46,3 +46,9 @@ u-boot,spl-payload-offset If present (and SPL is controlled by the device-tree), this allows to override the CONFIG_SYS_SPI_U_BOOT_OFFS setting using a value from the device-tree. + +sysreset-gpio + If present (and supported by the specific board), indicates a + GPIO that can be set to trigger a system reset. It is assumed + that such a system reset will effect a complete platform reset, + being roughly equivalent to a power-on reset. diff --git a/doc/device-tree-bindings/spi/spi-atcspi200.txt b/doc/device-tree-bindings/spi/spi-atcspi200.txt new file mode 100644 index 00000000000..9c0630b5003 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-atcspi200.txt @@ -0,0 +1,37 @@ +Andestech ATCSPI200 SPI controller Device Tree Bindings +------------------------------------------------------- +ATCSPI200 is a Serial Peripheral Interface (SPI) controller +which serves as a SPI master or a SPI slave. + +It is often be embedded in AE3XX and AE250 platforms. + +Required properties: +- compatible: has to be "andestech,atcspi200". +- reg: Base address and size of the controllers memory area. +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. +- interrupts: Property with a value describing the interrupt number. +- clocks: Clock phandles (see clock bindings for details). +- spi-max-frequency: Maximum SPI clocking speed of device in Hz. + +Optional properties: +- num-cs: Number of chip selects used. + +Example: + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0xf0b00000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <3 4>; + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; diff --git a/doc/device-tree-bindings/timer/atcpit100_timer.txt b/doc/device-tree-bindings/timer/atcpit100_timer.txt new file mode 100644 index 00000000000..620814e948c --- /dev/null +++ b/doc/device-tree-bindings/timer/atcpit100_timer.txt @@ -0,0 +1,31 @@ +Andestech ATCPIT100 timer +------------------------------------------------------------------ +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX, AE250 platforms and other designs. + +This timer is a set of compact multi-function timers, which can be +used as pulse width modulators (PWM) as well as simple timers. + +It supports up to 4 PIT channels. Each PIT channel is a +multi-function timer and provide the following usage scenarios: +One 32-bit timer +Two 16-bit timers +Four 8-bit timers +One 16-bit PWM +One 16-bit timer and one 8-bit PWM +Two 8-bit timer and one 8-bit PWM + +Required properties: +- compatible : Should be "andestech,atcpit100" +- reg : Address and length of the register set +- interrupts : Reference to the timer interrupt +- clock-frequency : The rate in HZ in input of the Andestech ATCPIT100 timer + +Examples: + +timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clock-frequency = <30000000>; +}: diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index baa60a52e68..f6644ee6d16 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -46,6 +46,14 @@ config CLK_BOSTON help Enable this to support the clocks +config CLK_STM32F + bool "Enable clock driver support for STM32F family" + depends on CLK && (STM32F7 || STM32F4) + default y + help + This clock driver adds support for RCC clock management + for STM32F4 and STM32F7 SoCs. + config CLK_ZYNQ bool "Enable clock driver support for Zynq" depends on CLK && ARCH_ZYNQ diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 83fe88ce9f5..bcc8f82fb65 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,5 +21,5 @@ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_ARCH_ASPEED) += aspeed/ -obj-$(CONFIG_STM32F7) += clk_stm32f7.o +obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o obj-$(CONFIG_STM32H7) += clk_stm32h7.o diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig index c6c57618c14..fd56f200b9f 100644 --- a/drivers/clk/at91/Kconfig +++ b/drivers/clk/at91/Kconfig @@ -14,11 +14,11 @@ config CLK_AT91 config AT91_UTMI bool "Support UTMI PLL Clock" - depends on CLK_AT91 && SPL_DM + depends on CLK_AT91 select REGMAP - select SPL_REGMAP + select SPL_REGMAP if SPL_DM select SYSCON - select SPL_SYSCON + select SPL_SYSCON if SPL_DM help This option is used to enable the AT91 UTMI PLL clock driver. It is the clock provider of USB, and UPLLCK is the diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 8c9a3cb053a..2aacbaef0c0 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -53,16 +53,17 @@ static ulong generic_clk_get_rate(struct clk *clk) struct clk parent; ulong clk_rate; u32 tmp, gckdiv; - u8 parent_id; + u8 clock_source, parent_index; int ret; writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); tmp = readl(&pmc->pcr); - parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) & + clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) & AT91_PMC_PCR_GCKCSS_MASK; gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK; - ret = clk_get_by_index(dev_get_parent(clk->dev), parent_id, &parent); + parent_index = clock_source - 1; + ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent); if (ret) return 0; @@ -82,7 +83,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate) ulong tmp_rate, best_rate = rate, parent_rate; int tmp_diff, best_diff = -1; u32 div, best_div = 0; - u8 best_parent_id = 0; + u8 best_parent_index, best_clock_source = 0; u8 i; u32 tmp; int ret; @@ -98,9 +99,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate) for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); - if (rate < tmp_rate) - continue; - tmp_diff = rate - tmp_rate; + tmp_diff = abs(rate - tmp_rate); if (best_diff < 0 || best_diff > tmp_diff) { best_rate = tmp_rate; @@ -108,7 +107,8 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate) best_div = div - 1; best_parent = parent; - best_parent_id = i; + best_parent_index = i; + best_clock_source = best_parent_index + 1; } if (!best_diff || tmp_rate < rate) @@ -129,7 +129,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate) writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); tmp = readl(&pmc->pcr); tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS); - tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) | + tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) | AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_GCKDIV_(best_div) | AT91_PMC_PCR_GCKEN; diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f.c index f1a9e9ca44e..634f0717c68 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f.c @@ -8,10 +8,12 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h> +#include <stm32_rcc.h> + #include <asm/io.h> -#include <asm/arch/rcc.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_periph.h> +#include <asm/arch/stm32_pwr.h> #include <dt-bindings/mfd/stm32f7-rcc.h> @@ -22,6 +24,8 @@ #define RCC_CR_CSSON BIT(19) #define RCC_CR_PLLON BIT(24) #define RCC_CR_PLLRDY BIT(25) +#define RCC_CR_PLLSAION BIT(28) +#define RCC_CR_PLLSAIRDY BIT(29) #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) @@ -52,75 +56,87 @@ #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE2_SHIFT 13 +#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6) +#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) +#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 +#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 +#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17) +#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) +#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) + +#define RCC_DCKCFGRX_CK48MSEL BIT(27) +#define RCC_DCKCFGRX_SDMMC1SEL BIT(28) +#define RCC_DCKCFGR2_SDMMC2SEL BIT(29) + +#define RCC_APB2ENR_SAI1EN BIT(22) + +/* + * RCC AHB1ENR specific definitions + */ +#define RCC_AHB1ENR_ETHMAC_EN BIT(25) +#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) +#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) + /* - * Offsets of some PWR registers + * RCC APB1ENR specific definitions */ -#define PWR_CR1_ODEN BIT(16) -#define PWR_CR1_ODSWEN BIT(17) -#define PWR_CSR1_ODRDY BIT(16) -#define PWR_CSR1_ODSWRDY BIT(17) - -struct pll_psc { - u8 pll_m; - u16 pll_n; - u8 pll_p; - u8 pll_q; - u8 ahb_psc; - u8 apb1_psc; - u8 apb2_psc; +#define RCC_APB1ENR_TIM2EN BIT(0) +#define RCC_APB1ENR_PWREN BIT(28) + +/* + * RCC APB2ENR specific definitions + */ +#define RCC_APB2ENR_SYSCFGEN BIT(14) + +struct stm32_clk_info stm32f4_clk_info = { + /* 180 MHz */ + .sys_pll_psc = { + .pll_m = 8, + .pll_n = 360, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2, + }, + .has_overdrive = false, + .v2 = false, }; -#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF - -#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 +struct stm32_clk_info stm32f7_clk_info = { + /* 200 MHz */ + .sys_pll_psc = { + .pll_m = 25, + .pll_n = 400, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2, + }, + .has_overdrive = true, + .v2 = true, +}; struct stm32_clk { struct stm32_rcc_regs *base; + struct stm32_pwr_regs *pwr_regs; + struct stm32_clk_info *info; }; -#if !defined(CONFIG_STM32_HSE_HZ) -#error "CONFIG_STM32_HSE_HZ not defined!" -#else -#if (CONFIG_STM32_HSE_HZ == 25000000) -#if (CONFIG_SYS_CLK_FREQ == 200000000) -/* 200 MHz */ -struct pll_psc sys_pll_psc = { - .pll_m = 25, - .pll_n = 400, - .pll_p = 2, - .pll_q = 8, - .ahb_psc = AHB_PSC_1, - .apb1_psc = APB_PSC_4, - .apb2_psc = APB_PSC_2 -}; -#endif -#else -#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" -#endif -#endif - static int configure_clocks(struct udevice *dev) { struct stm32_clk *priv = dev_get_priv(dev); struct stm32_rcc_regs *regs = priv->base; + struct stm32_pwr_regs *pwr = priv->pwr_regs; + struct pll_psc sys_pll_psc = priv->info->sys_pll_psc; + u32 pllsaicfgr = 0; /* Reset RCC configuration */ setbits_le32(®s->cr, RCC_CR_HSION); writel(0, ®s->cfgr); /* Reset CFGR */ clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON - | RCC_CR_PLLON)); + | RCC_CR_PLLON | RCC_CR_PLLSAION)); writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ clrbits_le32(®s->cr, RCC_CR_HSEBYP); writel(0, ®s->cir); /* Disable all interrupts */ @@ -146,23 +162,57 @@ static int configure_clocks(struct udevice *dev) clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT); + /* Configure the SAI PLL to get a 48 MHz source */ + pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 | + RCC_PLLSAICFGR_PLLSAIP_4; + pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT; + writel(pllsaicfgr, ®s->pllsaicfgr); + /* Enable the main PLL */ setbits_le32(®s->cr, RCC_CR_PLLON); while (!(readl(®s->cr) & RCC_CR_PLLRDY)) ; - /* Enable high performance mode, System frequency up to 200 MHz */ - setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); - setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN); - /* Infinite wait! */ - while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY)) - ; - /* Enable the Over-drive switch */ - setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN); - /* Infinite wait! */ - while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY)) + if (priv->info->v2) { /*stm32f7 case */ + /* select PLLSAI as 48MHz clock source */ + setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); + + /* select 48MHz as SDMMC1 clock source */ + clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL); + + /* select 48MHz as SDMMC2 clock source */ + clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL); + } else { /* stm32f4 case */ + /* select PLLSAI as 48MHz clock source */ + setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); + + /* select 48MHz as SDMMC1 clock source */ + clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); + } + + /* Enable the SAI PLL */ + setbits_le32(®s->cr, RCC_CR_PLLSAION); + while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) ; + setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); + + if (priv->info->has_overdrive) { + /* + * Enable high performance mode + * System frequency up to 200 MHz + */ + setbits_le32(&pwr->cr1, PWR_CR1_ODEN); + /* Infinite wait! */ + while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) + ; + /* Enable the Over-drive switch */ + setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN); + /* Infinite wait! */ + while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) + ; + } + stm32_flash_latency_cfg(5); clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); @@ -170,16 +220,47 @@ static int configure_clocks(struct udevice *dev) while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) ; + /* gate the SAI clock, needed for MMC 1&2 clocks */ + setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN); return 0; } +static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, + u32 sysclk) +{ + struct stm32_rcc_regs *regs = priv->base; + u16 pllq, pllm, pllsain, pllsaip; + bool pllsai; + + pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) + >> RCC_PLLCFGR_PLLQ_SHIFT; + + if (priv->info->v2) /*stm32f7 case */ + pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; + else + pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; + + if (pllsai) { + /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ + pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); + pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK) + >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); + pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) + >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); + return ((CONFIG_STM32_HSE_HZ / pllm) * pllsain) / pllsaip; + } + /* PLL48CLK is selected from PLLQ */ + return sysclk / pllq; +} + static unsigned long stm32_clk_get_rate(struct clk *clk) { struct stm32_clk *priv = dev_get_priv(clk->dev); struct stm32_rcc_regs *regs = priv->base; u32 sysclk = 0; u32 shift = 0; + u16 pllm, plln, pllp; /* Prescaler table lookups for clock computation */ u8 ahb_psc_table[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 @@ -190,7 +271,6 @@ static unsigned long stm32_clk_get_rate(struct clk *clk) if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL) { - u16 pllm, plln, pllp; pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) >> RCC_PLLCFGR_PLLN_SHIFT); @@ -211,25 +291,43 @@ static unsigned long stm32_clk_get_rate(struct clk *clk) (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) >> RCC_CFGR_HPRE_SHIFT)]; return sysclk >>= shift; - break; /* APB1 CLOCK */ case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): shift = apb_psc_table[( (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) >> RCC_CFGR_PPRE1_SHIFT)]; return sysclk >>= shift; - break; /* APB2 CLOCK */ case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): + /* + * particular case for SDMMC1 and SDMMC2 : + * 48Mhz source clock can be from main PLL or from + * SAI PLL + */ + switch (clk->id) { + case STM32F7_APB2_CLOCK(SDMMC1): + if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL) + /* System clock is selected as SDMMC1 clock */ + return sysclk; + else + return stm32_clk_pll48clk_rate(priv, sysclk); + break; + case STM32F7_APB2_CLOCK(SDMMC2): + if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) + /* System clock is selected as SDMMC2 clock */ + return sysclk; + else + return stm32_clk_pll48clk_rate(priv, sysclk); + break; + } + shift = apb_psc_table[( (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) >> RCC_CFGR_PPRE2_SHIFT)]; return sysclk >>= shift; - break; default: pr_err("clock index %ld out of range\n", clk->id); return -EINVAL; - break; } } @@ -268,17 +366,43 @@ void clock_setup(int peripheral) static int stm32_clk_probe(struct udevice *dev) { - debug("%s: stm32_clk_probe\n", __func__); + struct ofnode_phandle_args args; + int err; + + debug("%s\n", __func__); struct stm32_clk *priv = dev_get_priv(dev); fdt_addr_t addr; - addr = devfdt_get_addr(dev); + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->base = (struct stm32_rcc_regs *)addr; + switch (dev_get_driver_data(dev)) { + case STM32F4: + priv->info = &stm32f4_clk_info; + break; + case STM32F7: + priv->info = &stm32f7_clk_info; + break; + default: + return -EINVAL; + } + + if (priv->info->has_overdrive) { + err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, + &args); + if (err) { + debug("%s: can't find syscon device (%d)\n", __func__, + err); + return err; + } + + priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node); + } + configure_clocks(dev); return 0; @@ -307,15 +431,9 @@ static struct clk_ops stm32_clk_ops = { .get_rate = stm32_clk_get_rate, }; -static const struct udevice_id stm32_clk_ids[] = { - { .compatible = "st,stm32f42xx-rcc"}, - {} -}; - -U_BOOT_DRIVER(stm32f7_clk) = { - .name = "stm32f7_clk", +U_BOOT_DRIVER(stm32fx_clk) = { + .name = "stm32fx_rcc_clock", .id = UCLASS_CLK, - .of_match = stm32_clk_ids, .ops = &stm32_clk_ops, .probe = stm32_clk_probe, .priv_auto_alloc_size = sizeof(struct stm32_clk), diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index c821bddc251..5abb171827e 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -490,6 +490,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1), DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1), + DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), DEF_MOD("rwdt", 402, R8A7796_CLK_R), @@ -1074,6 +1075,64 @@ static int gen3_clk_probe(struct udevice *dev) return 0; } +struct mstp_stop_table { + u32 dis; + u32 en; +}; + +static struct mstp_stop_table r8a7795_mstp_table[] = { + { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 }, + { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 }, + { 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 }, + { 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 }, + { 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 }, + { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 }, +}; + +static struct mstp_stop_table r8a7796_mstp_table[] = { + { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 }, + { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 }, + { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 }, + { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 }, + { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 }, + { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, +}; + +#define TSTR0 0x04 +#define TSTR0_STR0 BIT(0) + +static int gen3_clk_remove(struct udevice *dev) +{ + struct gen3_clk_priv *priv = dev_get_priv(dev); + enum gen3_clk_model model = dev_get_driver_data(dev); + struct mstp_stop_table *tbl; + unsigned int i, tbl_size; + + switch (model) { + case CLK_R8A7795: + tbl = r8a7795_mstp_table; + tbl_size = ARRAY_SIZE(r8a7795_mstp_table); + break; + case CLK_R8A7796: + tbl = r8a7796_mstp_table; + tbl_size = ARRAY_SIZE(r8a7796_mstp_table); + break; + default: + return -EINVAL; + } + + /* Stop TMU0 */ + clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0); + + /* Stop module clock */ + for (i = 0; i < tbl_size; i++) { + clrsetbits_le32(priv->base + SMSTPCR(i), tbl[i].dis, tbl[i].en); + clrsetbits_le32(priv->base + RMSTPCR(i), tbl[i].dis, 0x0); + } + + return 0; +} + static const struct udevice_id gen3_clk_ids[] = { { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 }, { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 }, @@ -1087,4 +1146,5 @@ U_BOOT_DRIVER(clk_gen3) = { .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), .ops = &gen3_clk_ops, .probe = gen3_clk_probe, + .remove = gen3_clk_remove, }; diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index c50aff2e93d..eae0ef6a9fb 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -1,10 +1,11 @@ # -# Copyright (c) 2016 Google, Inc +# Copyright (c) 2017 Rockchip Electronics Co., Ltd # # SPDX-License-Identifier: GPL-2.0+ # obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c new file mode 100644 index 00000000000..132d50dda38 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -0,0 +1,596 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3128.h> +#include <asm/arch/hardware.h> +#include <bitfield.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rk3128-cru.h> +#include <linux/log2.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + VCO_MAX_HZ = 2400U * 1000000, + VCO_MIN_HZ = 600 * 1000000, + OUTPUT_MAX_HZ = 2400U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; + +/* use integer mode*/ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + +static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3128_pll *pll = &cru->pll[pll_id]; + + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n", + pll, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); + + /* use integer mode */ + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + /* Power down */ + rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); + + rk_clrsetreg(&pll->con0, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT)); + + /* Power Up */ + rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); + + /* waiting for pll lock */ + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) + udelay(1); + + return 0; +} + +static int pll_para_config(u32 freq_hz, struct pll_div *div) +{ + u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; + u32 postdiv1, postdiv2 = 1; + u32 fref_khz; + u32 diff_khz, best_diff_khz; + const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; + const u32 max_postdiv1 = 7, max_postdiv2 = 7; + u32 vco_khz; + u32 freq_khz = freq_hz / 1000; + + if (!freq_hz) { + printf("%s: the frequency can't be 0 Hz\n", __func__); + return -1; + } + + postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); + if (postdiv1 > max_postdiv1) { + postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); + postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); + } + + vco_khz = freq_khz * postdiv1 * postdiv2; + + if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || + postdiv2 > max_postdiv2) { + printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", + __func__, freq_hz); + return -1; + } + + div->postdiv1 = postdiv1; + div->postdiv2 = postdiv2; + + best_diff_khz = vco_khz; + for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { + fref_khz = ref_khz / refdiv; + + fbdiv = vco_khz / fref_khz; + if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) + continue; + diff_khz = vco_khz - fbdiv * fref_khz; + if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { + fbdiv++; + diff_khz = fref_khz - diff_khz; + } + + if (diff_khz >= best_diff_khz) + continue; + + best_diff_khz = diff_khz; + div->refdiv = refdiv; + div->fbdiv = fbdiv; + } + + if (best_diff_khz > 4 * (1000)) { + printf("%s: Failed to match output frequency %u bestis %u Hz\n", + __func__, freq_hz, + best_diff_khz * 1000); + return -1; + } + return 0; +} + +static void rkclk_init(struct rk3128_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | APLL_MODE_MASK, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + + /* + * select apll as cpu/core clock pll source and + * set up dependent divisors for PERI and ACLK clocks. + * core hz : apll = 1:1 + */ + aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; + assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); + + pclk_div = APLL_HZ / CORE_PERI_HZ - 1; + assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, + CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | + 0 << CORE_DIV_CON_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, + aclk_div << CORE_ACLK_DIV_SHIFT | + pclk_div << CORE_PERI_DIV_SHIFT); + + /* + * select gpll as pd_bus bus clock source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; + assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); + + pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; + assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7); + + hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; + assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[0], + BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, + BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | + aclk_div << BUS_ACLK_DIV_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, + pclk_div << BUS_PCLK_DIV_SHIFT | + hclk_div << BUS_HCLK_DIV_SHIFT); + + /* + * select gpll as pd_peri bus clock source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && pclk_div < 0x8); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | + PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, + PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK, + GPLL_MODE_NORM << GPLL_MODE_SHIFT | + APLL_MODE_NORM << APLL_MODE_SHIFT | + CPLL_MODE_NORM << CPLL_MODE_SHIFT); + + /*fix NAND controller working clock max to 150Mhz */ + rk_clrsetreg(&cru->cru_clksel_con[2], + NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK, + NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT | + 3 << NANDC_CLK_DIV_SHIFT); +} + +/* Get pll rate by id */ +static u32 rkclk_pll_get_rate(struct rk3128_cru *cru, + enum rk_clk_id clk_id) +{ + u32 refdiv, fbdiv, postdiv1, postdiv2; + u32 con; + int pll_id = rk_pll_id(clk_id); + struct rk3128_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, + GPLL_MODE_SHIFT, 0xff + }; + static u32 clk_mask[CLK_COUNT] = { + 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, + GPLL_MODE_MASK, 0xff + }; + uint shift; + uint mask; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + mask = clk_mask[clk_id]; + + switch ((con & mask) >> shift) { + case GPLL_MODE_SLOW: + return OSC_HZ; + case GPLL_MODE_NORM: + /* normal mode */ + con = readl(&pll->con0); + postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; + fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; + con = readl(&pll->con1); + postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; + refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; + return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + case GPLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate, + int periph) +{ + uint src_rate; + uint div, mux; + u32 con; + + switch (periph) { + case HCLK_EMMC: + case SCLK_EMMC: + case SCLK_EMMC_SAMPLE: + con = readl(&cru->cru_clksel_con[12]); + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; + break; + case HCLK_SDMMC: + case SCLK_SDMMC: + con = readl(&cru->cru_clksel_con[11]); + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; + break; + default: + return -EINVAL; + } + + src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; + return DIV_TO_RATE(src_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate, + int periph, uint freq) +{ + int src_clk_div; + int mux; + + debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); + + /* mmc clock defaulg div 2 internal, need provide double in cru */ + src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); + + if (src_clk_div > 128) { + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); + mux = EMMC_SEL_24M; + } else { + mux = EMMC_SEL_GPLL; + } + + switch (periph) { + case HCLK_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_PLL_MASK | EMMC_DIV_MASK, + mux << EMMC_PLL_SHIFT | + (src_clk_div - 1) << EMMC_DIV_SHIFT); + break; + case HCLK_SDMMC: + case SCLK_SDMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_PLL_MASK | MMC0_DIV_MASK, + mux << MMC0_PLL_SHIFT | + (src_clk_div - 1) << MMC0_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, clk_general_rate, periph); +} + +static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id) +{ + u32 div, con; + + switch (clk_id) { + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_PWM: + con = readl(&cru->cru_clksel_con[10]); + div = con >> 12 & 0x3; + break; + default: + printf("do not support this peripheral bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(PERI_ACLK_HZ, div); +} + +static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz) +{ + int src_clk_div; + + src_clk_div = PERI_ACLK_HZ / hz; + assert(src_clk_div - 1 < 4); + + switch (clk_id) { + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_PWM: + rk_setreg(&cru->cru_clksel_con[10], + ((src_clk_div - 1) << 12)); + break; + default: + printf("do not support this peripheral bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div); +} + +static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru) +{ + u32 div, val; + + val = readl(&cru->cru_clksel_con[24]); + div = bitfield_extract(val, SARADC_DIV_CON_SHIFT, + SARADC_DIV_CON_WIDTH); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->cru_clksel_con[24], + SARADC_DIV_CON_MASK, + src_clk_div << SARADC_DIV_CON_SHIFT); + + return rk3128_saradc_get_clk(cru); +} + +static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) +{ + int src_clk_div; + struct pll_div cpll_config = {0}; + + src_clk_div = GPLL_HZ / hz; + assert(src_clk_div - 1 < 31); + + switch (clk_id) { + case ACLK_VIO0: + rk_clrsetreg(&cru->cru_clksel_con[31], + VIO0_PLL_MASK | VIO0_DIV_MASK, + VIO0_SEL_GPLL << VIO0_PLL_SHIFT | + (src_clk_div - 1) << VIO0_DIV_SHIFT); + break; + case ACLK_VIO1: + rk_clrsetreg(&cru->cru_clksel_con[31], + VIO1_PLL_MASK | VIO1_DIV_MASK, + VIO1_SEL_GPLL << VIO1_PLL_SHIFT | + (src_clk_div - 1) << VIO1_DIV_SHIFT); + break; + case DCLK_LCDC: + if (pll_para_config(hz, &cpll_config)) + return -1; + rkclk_set_pll(cru, CLK_CODEC, &cpll_config); + + rk_clrsetreg(&cru->cru_clksel_con[27], + DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK, + DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT | + (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); + break; + default: + printf("do not support this vop freq\n"); + return -EINVAL; + } + + return hz; +} + +static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id) +{ + u32 div, con, parent; + + switch (clk_id) { + case ACLK_VIO0: + con = readl(&cru->cru_clksel_con[31]); + div = con & 0x1f; + parent = GPLL_HZ; + break; + case ACLK_VIO1: + con = readl(&cru->cru_clksel_con[31]); + div = (con >> 8) & 0x1f; + parent = GPLL_HZ; + break; + case DCLK_LCDC: + con = readl(&cru->cru_clksel_con[27]); + div = (con >> 8) & 0xfff; + parent = rkclk_pll_get_rate(cru, CLK_CODEC); + break; + default: + return -ENOENT; + } + return DIV_TO_RATE(parent, div); +} + +static ulong rk3128_clk_get_rate(struct clk *clk) +{ + struct rk3128_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0 ... 63: + return rkclk_pll_get_rate(priv->cru, clk->id); + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_PWM: + return rk3128_peri_get_pclk(priv->cru, clk->id); + case SCLK_SARADC: + return rk3128_saradc_get_clk(priv->cru); + case DCLK_LCDC: + case ACLK_VIO0: + case ACLK_VIO1: + return rk3128_vop_get_rate(priv->cru, clk->id); + default: + return -ENOENT; + } +} + +static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3128_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case 0 ... 63: + return 0; + case DCLK_LCDC: + case ACLK_VIO0: + case ACLK_VIO1: + new_rate = rk3128_vop_set_clk(priv->cru, + clk->id, rate); + break; + case HCLK_EMMC: + new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, + clk->id, rate); + break; + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_PWM: + new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate); + break; + case SCLK_SARADC: + new_rate = rk3128_saradc_set_clk(priv->cru, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk3128_clk_ops = { + .get_rate = rk3128_clk_get_rate, + .set_rate = rk3128_clk_set_rate, +}; + +static int rk3128_clk_probe(struct udevice *dev) +{ + struct rk3128_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3128_cru *)dev_read_addr(dev); + rkclk_init(priv->cru); + + return 0; +} + +static int rk3128_clk_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3128_cru, + cru_glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk3128_cru, + cru_glb_srst_snd_value); + sys_child->priv = priv; + } + + return 0; +} + +static const struct udevice_id rk3128_clk_ids[] = { + { .compatible = "rockchip,rk3128-cru" }, + { .compatible = "rockchip,rk3126-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3128_cru) = { + .name = "clk_rk3128", + .id = UCLASS_CLK, + .of_match = rk3128_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv), + .ops = &rk3128_clk_ops, + .bind = rk3128_clk_bind, + .probe = rk3128_clk_probe, +}; diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 451fbdebba3..cef8adc8175 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -13,6 +13,7 @@ #include <libfdt.h> #include <linux/arm-smccc.h> #include <linux/errno.h> +#include <linux/printk.h> #include <linux/psci.h> psci_fn *invoke_psci_fn; @@ -48,7 +49,7 @@ static int psci_bind(struct udevice *dev) ret = device_bind_driver(dev, "psci-sysreset", "psci-sysreset", NULL); if (ret) - debug("PSCI System Reset was not bound.\n"); + pr_debug("PSCI System Reset was not bound.\n"); } return 0; @@ -62,7 +63,7 @@ static int psci_probe(struct udevice *dev) method = fdt_stringlist_get(gd->fdt_blob, dev_of_offset(dev), "method", 0, NULL); if (!method) { - printf("missing \"method\" property\n"); + pr_warn("missing \"method\" property\n"); return -ENXIO; } @@ -71,7 +72,7 @@ static int psci_probe(struct udevice *dev) } else if (!strcmp("smc", method)) { invoke_psci_fn = __invoke_psci_fn_smc; } else { - printf("invalid \"method\" property: %s\n", method); + pr_warn("invalid \"method\" property: %s\n", method); return -EINVAL; } diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 8504dceb849..cb9f4258842 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -10,6 +10,7 @@ #include <errno.h> #include <asm/gpio.h> #include <asm/io.h> +#include "../pinctrl/renesas/sh_pfc.h" #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */ @@ -29,7 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; struct rcar_gpio_priv { - void __iomem *regs; + void __iomem *regs; + int pfc_offset; }; static int rcar_gpio_get_value(struct udevice *dev, unsigned offset) @@ -113,7 +115,22 @@ static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) return GPIOF_INPUT; } +static int rcar_gpio_request(struct udevice *dev, unsigned offset, + const char *label) +{ + struct rcar_gpio_priv *priv = dev_get_priv(dev); + struct udevice *pctldev; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pctldev); + if (ret) + return ret; + + return sh_pfc_config_mux_for_gpio(pctldev, priv->pfc_offset + offset); +} + static const struct dm_gpio_ops rcar_gpio_ops = { + .request = rcar_gpio_request, .direction_input = rcar_gpio_direction_input, .direction_output = rcar_gpio_direction_output, .get_value = rcar_gpio_get_value, @@ -135,6 +152,7 @@ static int rcar_gpio_probe(struct udevice *dev) ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", NULL, 3, 0, &args); + priv->pfc_offset = ret == 0 ? args.args[1] : -1; uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; ret = clk_get_by_index(dev, 0, &clk); diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 1989f8eb572..cc370b9c57c 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -157,6 +157,12 @@ config SYS_I2C_OMAP24XX help Add support for the OMAP2+ I2C driver. +config SYS_I2C_RCAR_IIC + bool "Renesas RCar Gen3 IIC driver" + depends on RCAR_GEN3 && DM_I2C + help + Support for Renesas RCar Gen3 IIC controller. + config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 733cd3e92fa..169a2f1d7a9 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o +obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c new file mode 100644 index 00000000000..57ae2f51fca --- /dev/null +++ b/drivers/i2c/rcar_iic.c @@ -0,0 +1,271 @@ +/* + * Renesas RCar IIC driver + * + * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> + * + * Based on + * Copyright (C) 2011, 2013 Renesas Solutions Corp. + * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <i2c.h> +#include <asm/io.h> + +struct rcar_iic_priv { + void __iomem *base; + struct clk clk; + u8 iccl; + u8 icch; +}; + +#define RCAR_IIC_ICDR 0x00 +#define RCAR_IIC_ICCR 0x04 +#define RCAR_IIC_ICSR 0x08 +#define RCAR_IIC_ICIC 0x0c +#define RCAR_IIC_ICCL 0x10 +#define RCAR_IIC_ICCH 0x14 + +/* ICCR */ +#define RCAR_IIC_ICCR_ICE BIT(7) +#define RCAR_IIC_ICCR_RACK BIT(6) +#define RCAR_IIC_ICCR_RTS BIT(4) +#define RCAR_IIC_ICCR_BUSY BIT(2) +#define RCAR_IIC_ICCR_SCP BIT(0) + +/* ICSR / ICIC */ +#define RCAR_IC_BUSY BIT(4) +#define RCAR_IC_TACK BIT(2) +#define RCAR_IC_DTE BIT(0) + +#define IRQ_WAIT 1000 + +static void sh_irq_dte(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < IRQ_WAIT; i++) { + if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) + break; + udelay(10); + } +} + +static int sh_irq_dte_with_tack(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < IRQ_WAIT; i++) { + if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) + break; + if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR)) + return -ETIMEDOUT; + udelay(10); + } + return 0; +} + +static void sh_irq_busy(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < IRQ_WAIT; i++) { + if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR))) + break; + udelay(10); + } +} + +static int rcar_iic_set_addr(struct udevice *dev, u8 chip, u8 read) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + + clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); + setbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); + + writeb(priv->iccl, priv->base + RCAR_IIC_ICCL); + writeb(priv->icch, priv->base + RCAR_IIC_ICCH); + writeb(RCAR_IC_TACK, priv->base + RCAR_IIC_ICIC); + + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS | RCAR_IIC_ICCR_BUSY, + priv->base + RCAR_IIC_ICCR); + sh_irq_dte(dev); + + clrbits_8(priv->base + RCAR_IIC_ICSR, RCAR_IC_TACK); + writeb(chip << 1 | read, priv->base + RCAR_IIC_ICDR); + return sh_irq_dte_with_tack(dev); +} + +static void rcar_iic_finish(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + + writeb(0, priv->base + RCAR_IIC_ICSR); + clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); +} + +static int rcar_iic_read_common(struct udevice *dev, struct i2c_msg *msg) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i, ret = -EREMOTEIO; + + if (rcar_iic_set_addr(dev, msg->addr, 1) != 0) + goto err; + + udelay(10); + + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP, + priv->base + RCAR_IIC_ICCR); + + for (i = 0; i < msg->len; i++) { + if (sh_irq_dte_with_tack(dev) != 0) + goto err; + + msg->buf[i] = readb(priv->base + RCAR_IIC_ICDR) & 0xff; + + if (msg->len - 1 == i) { + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RACK, + priv->base + RCAR_IIC_ICCR); + } + } + + sh_irq_busy(dev); + ret = 0; + +err: + rcar_iic_finish(dev); + return ret; +} + +static int rcar_iic_write_common(struct udevice *dev, struct i2c_msg *msg) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int i, ret = -EREMOTEIO; + + if (rcar_iic_set_addr(dev, msg->addr, 0) != 0) + goto err; + + udelay(10); + + for (i = 0; i < msg->len; i++) { + writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR); + if (sh_irq_dte_with_tack(dev) != 0) + goto err; + } + + if (msg->flags & I2C_M_STOP) { + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS, + priv->base + RCAR_IIC_ICCR); + if (sh_irq_dte_with_tack(dev) != 0) + goto err; + } + + sh_irq_busy(dev); + ret = 0; + +err: + rcar_iic_finish(dev); + return ret; +} + +static int rcar_iic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) +{ + int ret; + + for (; nmsgs > 0; nmsgs--, msg++) { + if (msg->flags & I2C_M_RD) + ret = rcar_iic_read_common(dev, msg); + else + ret = rcar_iic_write_common(dev, msg); + + if (ret) + return -EREMOTEIO; + } + + return ret; +} + +static int rcar_iic_set_speed(struct udevice *dev, uint speed) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + const unsigned int ratio_high = 4; + const unsigned int ratio_low = 5; + int clkrate, denom; + + clkrate = clk_get_rate(&priv->clk); + if (clkrate < 0) + return clkrate; + + /* + * Calculate the value for ICCL and ICCH. From the data sheet: + * iccl = (p-clock / transfer-rate) * (L / (L + H)) + * icch = (p clock / transfer rate) * (H / (L + H)) + * where L and H are the SCL low and high ratio. + */ + denom = speed * (ratio_high + ratio_low); + priv->iccl = DIV_ROUND_CLOSEST(clkrate * ratio_low, denom); + priv->icch = DIV_ROUND_CLOSEST(clkrate * ratio_high, denom); + + return 0; +} + +static int rcar_iic_probe_chip(struct udevice *dev, uint addr, uint flags) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int ret; + + rcar_iic_set_addr(dev, addr, 1); + writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP, + priv->base + RCAR_IIC_ICCR); + ret = sh_irq_dte_with_tack(dev); + rcar_iic_finish(dev); + + return ret; +} + +static int rcar_iic_probe(struct udevice *dev) +{ + struct rcar_iic_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + rcar_iic_finish(dev); + + return rcar_iic_set_speed(dev, 100000); +} + +static const struct dm_i2c_ops rcar_iic_ops = { + .xfer = rcar_iic_xfer, + .probe_chip = rcar_iic_probe_chip, + .set_bus_speed = rcar_iic_set_speed, +}; + +static const struct udevice_id rcar_iic_ids[] = { + { .compatible = "renesas,rmobile-iic" }, + { } +}; + +U_BOOT_DRIVER(iic_rcar) = { + .name = "iic_rcar", + .id = UCLASS_I2C, + .of_match = rcar_iic_ids, + .probe = rcar_iic_probe, + .priv_auto_alloc_size = sizeof(struct rcar_iic_priv), + .ops = &rcar_iic_ops, +}; diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index 32d39719d81..87d9928362b 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -8,31 +8,63 @@ #include <common.h> #include <dm.h> #include <misc.h> +#include <stm32_rcc.h> +#include <dm/device-internal.h> #include <dm/lists.h> +struct stm32_rcc_clk stm32_rcc_clk_f4 = { + .drv_name = "stm32fx_rcc_clock", + .soc = STM32F4, +}; + +struct stm32_rcc_clk stm32_rcc_clk_f7 = { + .drv_name = "stm32fx_rcc_clock", + .soc = STM32F7, +}; + +struct stm32_rcc_clk stm32_rcc_clk_h7 = { + .drv_name = "stm32h7_rcc_clock", +}; + static int stm32_rcc_bind(struct udevice *dev) { - int ret; struct udevice *child; + struct driver *drv; + struct stm32_rcc_clk *rcc_clk = + (struct stm32_rcc_clk *)dev_get_driver_data(dev); + int ret; debug("%s(dev=%p)\n", __func__, dev); - ret = device_bind_driver_to_node(dev, "stm32h7_rcc_clock", - "stm32h7_rcc_clock", - dev_ofnode(dev), &child); + drv = lists_driver_lookup_name(rcc_clk->drv_name); + if (!drv) { + debug("Cannot find driver '%s'\n", rcc_clk->drv_name); + return -ENOENT; + } + + ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name, + rcc_clk->soc, + dev_ofnode(dev), &child); + if (ret) return ret; +#ifdef CONFIG_SPL_BUILD + return 0; +#else return device_bind_driver_to_node(dev, "stm32_rcc_reset", "stm32_rcc_reset", dev_ofnode(dev), &child); +#endif } static const struct misc_ops stm32_rcc_ops = { }; static const struct udevice_id stm32_rcc_ids[] = { - {.compatible = "st,stm32h743-rcc"}, + {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f4 }, + {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 }, + {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 }, { } }; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 62ce0af7d3c..8fbeaa740d6 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -401,6 +401,18 @@ config STM32_SDMMC2 If you have a board based on such a SoC and with a SD/MMC slot, say Y or M here. +config MMC_NDS32 + bool "Andestech SD/MMC controller support" + depends on DM_MMC && OF_CONTROL && BLK && FTSDC010 + help + This enables support for the Andestech SD/MMM controller, which is + based on Faraday IP. + +config FTSDC010 + bool "Ftsdc010 SD/MMC controller Support" + help + This SD/MMC controller is present in Andestech SoCs which is based on Faraday IP. + endif config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index d505f37f019..9af375b044a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o +obj-$(CONFIG_MMC_NDS32) += nds32_mmc.o # SDHCI obj-$(CONFIG_MMC_SDHCI) += sdhci.o diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index c19a1f36b69..9b37e32c8db 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -13,6 +13,7 @@ #include <asm/arch/clk.h> #define ATMEL_SDHC_MIN_FREQ 400000 +#define ATMEL_SDHC_GCK_RATE 240000000 #ifndef CONFIG_DM_MMC int atmel_sdhci_init(void *regbase, u32 id) @@ -57,9 +58,6 @@ static int atmel_sdhci_probe(struct udevice *dev) struct atmel_sdhci_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); u32 max_clk; - u32 caps, caps_1; - u32 clk_base, clk_mul; - ulong gck_rate; struct clk clk; int ret; @@ -78,17 +76,11 @@ static int atmel_sdhci_probe(struct udevice *dev) host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", 4); - caps = sdhci_readl(host, SDHCI_CAPABILITIES); - clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); - clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; - gck_rate = clk_base * 1000000 * (clk_mul + 1); - ret = clk_get_by_index(dev, 1, &clk); if (ret) return ret; - ret = clk_set_rate(&clk, gck_rate); + ret = clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE); if (ret) return ret; diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 652a718467a..6ac4f83bd1c 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -12,24 +12,15 @@ #include <part.h> #include <mmc.h> -#include <asm/io.h> +#include <linux/io.h> #include <linux/errno.h> #include <asm/byteorder.h> #include <faraday/ftsdc010.h> +#include "ftsdc010_mci.h" #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ -struct ftsdc010_chip { - void __iomem *regs; - uint32_t wprot; /* write protected (locked) */ - uint32_t rate; /* actual SD clock in Hz */ - uint32_t sclk; /* FTSDC010 source clock in Hz */ - uint32_t fifo; /* fifo depth in bytes */ - uint32_t acmd; - struct mmc_config cfg; /* mmc configuration */ -}; - static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) { struct ftsdc010_chip *chip = mmc->priv; @@ -127,9 +118,8 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) { int ret = -ETIMEDOUT; - uint32_t st, ts; - - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { + uint32_t st, timeout = 10000000; + while (timeout--) { st = readl(®s->status); if (!(st & mask)) continue; @@ -138,8 +128,9 @@ static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) break; } - if (ret) + if (ret){ debug("ftsdc010: wait st(0x%x) timeout\n", mask); + } return ret; } @@ -147,10 +138,16 @@ static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) /* * u-boot mmc api */ - +#ifdef CONFIG_DM_MMC +static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { +#endif int ret = -EOPNOTSUPP; uint32_t len = 0; struct ftsdc010_chip *chip = mmc->priv; @@ -245,14 +242,20 @@ static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, if (!ret) { ret = ftsdc010_wait(regs, - FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR); + FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK); } return ret; } +#ifdef CONFIG_DM_MMC +static int ftsdc010_set_ios(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static int ftsdc010_set_ios(struct mmc *mmc) { +#endif struct ftsdc010_chip *chip = mmc->priv; struct ftsdc010_mmc __iomem *regs = chip->regs; @@ -274,20 +277,43 @@ static int ftsdc010_set_ios(struct mmc *mmc) return 0; } -static int ftsdc010_init(struct mmc *mmc) +#ifdef CONFIG_DM_MMC +static int ftsdc010_get_cd(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else +static int ftsdc010_get_cd(struct mmc *mmc) { +#endif struct ftsdc010_chip *chip = mmc->priv; struct ftsdc010_mmc __iomem *regs = chip->regs; - uint32_t ts; - - if (readl(®s->status) & FTSDC010_STATUS_CARD_DETECT) - return -ENOMEDIUM; + return !(readl(®s->status) & FTSDC010_STATUS_CARD_DETECT); +} +#ifdef CONFIG_DM_MMC +static int ftsdc010_get_wp(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else +static int ftsdc010_get_wp(struct mmc *mmc) +{ +#endif + struct ftsdc010_chip *chip = mmc->priv; + struct ftsdc010_mmc __iomem *regs = chip->regs; if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) { printf("ftsdc010: write protected\n"); chip->wprot = 1; } + return 0; +} + +static int ftsdc010_init(struct mmc *mmc) +{ + struct ftsdc010_chip *chip = mmc->priv; + struct ftsdc010_mmc __iomem *regs = chip->regs; + uint32_t ts; + chip->fifo = (readl(®s->feature) & 0xff) << 2; /* 1. chip reset */ @@ -311,11 +337,69 @@ static int ftsdc010_init(struct mmc *mmc) return 0; } +#ifdef CONFIG_DM_MMC +int ftsdc010_probe(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + return ftsdc010_init(mmc); +} + +const struct dm_mmc_ops dm_ftsdc010_ops = { + .send_cmd = ftsdc010_request, + .set_ios = ftsdc010_set_ios, + .get_cd = ftsdc010_get_cd, + .get_wp = ftsdc010_get_wp, +}; + +#else static const struct mmc_ops ftsdc010_ops = { .send_cmd = ftsdc010_request, .set_ios = ftsdc010_set_ios, + .getcd = ftsdc010_get_cd, + .getwp = ftsdc010_get_wp, .init = ftsdc010_init, }; +#endif + +void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, + uint caps, u32 max_clk, u32 min_clk) +{ + cfg->name = name; + cfg->f_min = min_clk; + cfg->f_max = max_clk; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->host_caps = caps; + if (buswidth == 8) { + cfg->host_caps |= MMC_MODE_8BIT; + cfg->host_caps &= ~MMC_MODE_4BIT; + } else { + cfg->host_caps |= MMC_MODE_4BIT; + cfg->host_caps &= ~MMC_MODE_8BIT; + } + cfg->part_type = PART_TYPE_DOS; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; +} + +void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg) +{ + switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) { + case FTSDC010_BWR_CAPS_4BIT: + cfg->host_caps |= MMC_MODE_4BIT; + break; + case FTSDC010_BWR_CAPS_8BIT: + cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; + break; + default: + break; + } +} + +#ifdef CONFIG_BLK +int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) +{ + return mmc_bind(dev, mmc, cfg); +} +#else int ftsdc010_mmc_init(int devid) { @@ -345,19 +429,11 @@ int ftsdc010_mmc_init(int devid) #endif chip->cfg.name = "ftsdc010"; +#ifndef CONFIG_DM_MMC chip->cfg.ops = &ftsdc010_ops; +#endif chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; - switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) { - case FTSDC010_BWR_CAPS_4BIT: - chip->cfg.host_caps |= MMC_MODE_4BIT; - break; - case FTSDC010_BWR_CAPS_8BIT: - chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; - break; - default: - break; - } - + set_bus_width(regs , &chip->cfg); chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; chip->cfg.f_max = chip->sclk / 2; chip->cfg.f_min = chip->sclk / 0x100; @@ -373,3 +449,4 @@ int ftsdc010_mmc_init(int devid) return 0; } +#endif diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h new file mode 100644 index 00000000000..31a27fd7728 --- /dev/null +++ b/drivers/mmc/ftsdc010_mci.h @@ -0,0 +1,53 @@ +/* + * Faraday FTSDC010 Secure Digital Memory Card Host Controller + * + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <mmc.h> + +#ifndef __FTSDC010_MCI_H +#define __FTSDC010_MCI_H + +struct ftsdc010_chip { + void __iomem *regs; + uint32_t wprot; /* write protected (locked) */ + uint32_t rate; /* actual SD clock in Hz */ + uint32_t sclk; /* FTSDC010 source clock in Hz */ + uint32_t fifo; /* fifo depth in bytes */ + uint32_t acmd; + struct mmc_config cfg; /* mmc configuration */ + const char *name; + void *ioaddr; + unsigned int caps; + unsigned int version; + unsigned int clock; + unsigned int bus_hz; + unsigned int div; + int dev_index; + int dev_id; + int buswidth; + u32 fifoth_val; + struct mmc *mmc; + void *priv; + bool fifo_mode; +}; + + +#ifdef CONFIG_DM_MMC +/* Export the operations to drivers */ +int ftsdc010_probe(struct udevice *dev); +extern const struct dm_mmc_ops dm_ftsdc010_ops; +#endif +void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, + uint caps, u32 max_clk, u32 min_clk); +void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg); + +#ifdef CONFIG_BLK +int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); +#endif + + +#endif /* __FTSDC010_MCI_H */ diff --git a/drivers/mmc/nds32_mmc.c b/drivers/mmc/nds32_mmc.c new file mode 100644 index 00000000000..6d3c8572e50 --- /dev/null +++ b/drivers/mmc/nds32_mmc.c @@ -0,0 +1,136 @@ +/* + * Andestech ATFSDC010 SD/MMC driver + * + * (C) Copyright 2017 + * Rick Chen, NDS32 Software Engineering, rick@andestech.com + + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-structs.h> +#include <errno.h> +#include <mapmem.h> +#include <mmc.h> +#include <pwrseq.h> +#include <syscon.h> +#include <linux/err.h> +#include <faraday/ftsdc010.h> +#include "ftsdc010_mci.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct nds_mmc { + fdt32_t bus_width; + bool cap_mmc_highspeed; + bool cap_sd_highspeed; + fdt32_t clock_freq_min_max[2]; + struct phandle_2_cell clocks[4]; + fdt32_t fifo_depth; + fdt32_t reg[2]; +}; +#endif + +struct nds_mmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct nds_mmc dtplat; +#endif + struct mmc_config cfg; + struct mmc mmc; +}; + +struct ftsdc_priv { + struct clk clk; + struct ftsdc010_chip chip; + int fifo_depth; + bool fifo_mode; + u32 minmax[2]; +}; + +static int nds32_mmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct ftsdc_priv *priv = dev_get_priv(dev); + struct ftsdc010_chip *chip = &priv->chip; + chip->name = dev->name; + chip->ioaddr = (void *)devfdt_get_addr(dev); + chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "bus-width", 4); + chip->priv = dev; + priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "fifo-depth", 0); + priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "fifo-mode"); + if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), + "clock-freq-min-max", priv->minmax, 2)) { + int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "max-frequency", -EINVAL); + if (val < 0) + return val; + + priv->minmax[0] = 400000; /* 400 kHz */ + priv->minmax[1] = val; + } else { + debug("%s: 'clock-freq-min-max' property was deprecated.\n", + __func__); + } +#endif + chip->sclk = priv->minmax[1]; + chip->regs = chip->ioaddr; + return 0; +} + +static int nds32_mmc_probe(struct udevice *dev) +{ + struct nds_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct ftsdc_priv *priv = dev_get_priv(dev); + struct ftsdc010_chip *chip = &priv->chip; + struct udevice *pwr_dev __maybe_unused; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + int ret; + struct nds_mmc *dtplat = &plat->dtplat; + chip->name = dev->name; + chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); + chip->buswidth = dtplat->bus_width; + chip->priv = dev; + chip->dev_index = 1; + memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); + ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); + if (ret < 0) + return ret; +#endif + ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps, + priv->minmax[1] , priv->minmax[0]); + chip->mmc = &plat->mmc; + chip->mmc->priv = &priv->chip; + chip->mmc->dev = dev; + upriv->mmc = chip->mmc; + return ftsdc010_probe(dev); +} + +static int nds32_mmc_bind(struct udevice *dev) +{ + struct nds_mmc_plat *plat = dev_get_platdata(dev); + return ftsdc010_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id nds32_mmc_ids[] = { + { .compatible = "andestech,atsdc010" }, + { } +}; + +U_BOOT_DRIVER(nds32_mmc_drv) = { + .name = "nds32_mmc", + .id = UCLASS_MMC, + .of_match = nds32_mmc_ids, + .ofdata_to_platdata = nds32_mmc_ofdata_to_platdata, + .ops = &dm_ftsdc010_ops, + .bind = nds32_mmc_bind, + .probe = nds32_mmc_probe, + .priv_auto_alloc_size = sizeof(struct ftsdc_priv), + .platdata_auto_alloc_size = sizeof(struct nds_mmc_plat), +}; diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 6ab3c8a25ad..cedbb239b68 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -233,6 +233,7 @@ static struct pxa3xx_nand_flash builtin_flash_types[] = { { 0xba20, 16, 16, &timing[3] }, }; +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; @@ -255,6 +256,7 @@ static struct nand_bbt_descr bbt_mirror_descr = { .maxblocks = 8, /* Last 8 blocks in each chip */ .pattern = bbt_mirror_pattern }; +#endif static struct nand_ecclayout ecc_layout_2KB_bch4bit = { .eccbytes = 32, diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index dc7a52534e5..26d95f178f7 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -492,8 +492,8 @@ static int ravb_probe(struct udevice *dev) if (ret < 0) goto err_mdio_alloc; - gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0, - ð->reset_gpio, GPIOD_IS_OUT); + gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio, + GPIOD_IS_OUT); mdiodev = mdio_alloc(); if (!mdiodev) { @@ -528,7 +528,8 @@ static int ravb_remove(struct udevice *dev) free(eth->phydev); mdio_unregister(eth->bus); mdio_free(eth->bus); - dm_gpio_free(dev, ð->reset_gpio); + if (dm_gpio_is_valid(ð->reset_gpio)) + dm_gpio_free(dev, ð->reset_gpio); unmap_physmem(eth->iobase, MAP_NOCACHE); return 0; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index afca56dff1f..7e8e4b0b276 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -168,6 +168,16 @@ config PINCTRL_ROCKCHIP_RK3036 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_ROCKCHIP_RK3128 + bool "Rockchip rk3128 pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3128 SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + config PINCTRL_ROCKCHIP_RK3188 bool "Rockchip rk3188 pin control driver" depends on DM diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 1675485d669..66700725045 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -448,6 +448,51 @@ static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, return priv->pfc.info->functions[selector].name; } +int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + struct sh_pfc_pin_config *cfg; + const struct sh_pfc_pin *pin = NULL; + int i, idx; + + for (i = 1; i < pfc->info->nr_pins; i++) { + if (priv->pfc.info->pins[i].pin != pin_selector) + continue; + + pin = &priv->pfc.info->pins[i]; + break; + } + + if (!pin) + return -EINVAL; + + idx = sh_pfc_get_pin_index(pfc, pin->pin); + cfg = &pmx->configs[idx]; + + if (cfg->type != PINMUX_TYPE_NONE) + return -EBUSY; + + return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); +} + +static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, + unsigned func_selector) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector]; + int idx = sh_pfc_get_pin_index(pfc, pin->pin); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + if (cfg->type != PINMUX_TYPE_NONE) + return -EBUSY; + + return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); +} + static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector, unsigned func_selector) { @@ -642,6 +687,19 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, return 0; } +static int sh_pfc_pinconf_pin_set(struct udevice *dev, + unsigned int pin_selector, + unsigned int param, unsigned int arg) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector]; + + sh_pfc_pinconf_set(pmx, pin->pin, param, arg); + + return 0; +} static int sh_pfc_pinconf_group_set(struct udevice *dev, unsigned int group_selector, @@ -671,8 +729,10 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = { #if CONFIG_IS_ENABLED(PINCONF) .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), .pinconf_params = sh_pfc_pinconf_params, + .pinconf_set = sh_pfc_pinconf_pin_set, .pinconf_group_set = sh_pfc_pinconf_group_set, #endif + .pinmux_set = sh_pfc_pinctrl_pin_set, .pinmux_group_set = sh_pfc_pinctrl_group_set, .set_state = pinctrl_generic_set_state, }; diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 7aef2d360b2..f82417b1a34 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -243,6 +243,7 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) const struct sh_pfc_bias_info * sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, unsigned int num, unsigned int pin); +int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector); extern const struct sh_pfc_soc_info r8a7795_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 5251771a106..f09c6e17b4b 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -1,11 +1,11 @@ # -# Copyright (c) 2015 Google, Inc -# Written by Simon Glass <sjg@chromium.org> +# Copyright (c) 2017 Rockchip Electronics Co., Ltd # # SPDX-License-Identifier: GPL-2.0+ # obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o +obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3128) += pinctrl_rk3128.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3128.c b/drivers/pinctrl/rockchip/pinctrl_rk3128.c new file mode 100644 index 00000000000..b1c32ac592a --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3128.c @@ -0,0 +1,187 @@ +/* + * Pinctrl driver for Rockchip 3128 SoCs + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3128.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3128_pinctrl_priv { + struct rk3128_grf *grf; +}; + +static void pinctrl_rk3128_i2c_config(struct rk3128_grf *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A1_MASK | GPIO0A0_MASK, + GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | + GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); + + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A3_MASK | GPIO0A2_MASK, + GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | + GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2c_iomux2, + GPIO2C5_MASK | GPIO2C4_MASK, + GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | + GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A7_MASK | GPIO0A6_MASK, + GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT | + GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT); + + break; + } +} + +static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, + GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | + GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | + GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | + GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | + GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | + GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | + GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | + GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A5_MASK | GPIO2A7_MASK, + GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT | + GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio1c_iomux, 0x0fff, + GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT | + GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT | + GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT | + GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT | + GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT | + GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT); + break; + } +} + +static int rk3128_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3128_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + pinctrl_rk3128_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3128_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3128_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 14: + return PERIPH_ID_SDCARD; + case 16: + return PERIPH_ID_EMMC; + case 20: + return PERIPH_ID_UART0; + case 21: + return PERIPH_ID_UART1; + case 22: + return PERIPH_ID_UART2; + case 23: + return PERIPH_ID_SPI0; + case 24: + return PERIPH_ID_I2C0; + case 25: + return PERIPH_ID_I2C1; + case 26: + return PERIPH_ID_I2C2; + case 27: + return PERIPH_ID_I2C3; + case 30: + return PERIPH_ID_PWM0; + } + return -ENOENT; +} + +static int rk3128_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3128_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk3128_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3128_pinctrl_ops = { + .set_state_simple = rk3128_pinctrl_set_state_simple, + .request = rk3128_pinctrl_request, + .get_periph_id = rk3128_pinctrl_get_periph_id, +}; + +static int rk3128_pinctrl_probe(struct udevice *dev) +{ + struct rk3128_pinctrl_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + return 0; +} + +static const struct udevice_id rk3128_pinctrl_ids[] = { + { .compatible = "rockchip,rk3128-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3128) = { + .name = "pinctrl_rk3128", + .id = UCLASS_PINCTRL, + .of_match = rk3128_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3128_pinctrl_priv), + .ops = &rk3128_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = rk3128_pinctrl_probe, +}; diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index 45b5fe72471..1a1e5578ca4 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -5,6 +5,7 @@ # obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o +obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c new file mode 100644 index 00000000000..a33127f4b05 --- /dev/null +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3128.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR; +struct dram_info { + struct ram_info info; + struct rk3128_grf *grf; +}; + +static int rk3128_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->grf->os_reg[1]); + + return 0; +} + +static int rk3128_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3128_dmc_ops = { + .get_info = rk3128_dmc_get_info, +}; + +static const struct udevice_id rk3128_dmc_ids[] = { + { .compatible = "rockchip,rk3128-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3128) = { + .name = "rockchip_rk3128_dmc", + .id = UCLASS_RAM, + .of_match = rk3128_dmc_ids, + .ops = &rk3128_dmc_ops, + .probe = rk3128_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +}; diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 4d271222434..1b8d742f1cf 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -226,8 +226,7 @@ struct uart_port { # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \ - defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795) || \ - defined(CONFIG_R8A7796) + defined(CONFIG_R8A7794) || defined(CONFIG_RCAR_GEN3) # if defined(CONFIG_SCIF_A) # define SCIF_ORER 0x0200 # else diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 88da9a4c8e7..494639fb019 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -210,12 +210,12 @@ config FSL_QSPI used to access the SPI NOR flash on platforms embedding this Freescale IP core. -config NDS_AE3XX_SPI - bool "Andestech AE3XX SPI driver" +config ATCSPI200_SPI + bool "Andestech ATCSPI200 SPI driver" help - Enable the Andestech AE3XX SPI driver. This driver can be - used to access the SPI flash on platforms embedding this - Andestech IP core. + Enable the Andestech ATCSPI200 SPI driver. This driver can be + used to access the SPI flash on AE3XX and AE250 platforms embedding + this Andestech IP core. config TI_QSPI bool "TI QSPI driver" diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ad56203cd6f..e3184db67f5 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o -obj-$(CONFIG_NDS_AE3XX_SPI) += nds_ae3xx_spi.o +obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o obj-$(CONFIG_PIC32_SPI) += pic32_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o diff --git a/drivers/spi/nds_ae3xx_spi.c b/drivers/spi/atcspi200_spi.c index f5bd99a605b..3e29df03a4d 100644 --- a/drivers/spi/nds_ae3xx_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -1,5 +1,5 @@ /* - * NDS SPI controller driver. + * Andestech ATCSPI200 SPI controller driver. * * Copyright 2017 Andes Technology, Inc. * Author: Rick Chen (rick@andestech.com) @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI1_BASE 0xf0f00000 #define NSPI_MAX_CS_NUM 1 -struct ae3xx_spi_regs { +struct atcspi200_spi_regs { u32 rev; u32 reserve1[3]; u32 format; /* 0x10 */ @@ -78,7 +78,7 @@ struct nds_spi_slave { #ifndef CONFIG_DM_SPI struct spi_slave slave; #endif - volatile struct ae3xx_spi_regs *regs; + volatile struct atcspi200_spi_regs *regs; int to; unsigned int freq; ulong clock; @@ -94,7 +94,7 @@ struct nds_spi_slave { unsigned int max_transfer_length; }; -static int __ae3xx_spi_set_speed(struct nds_spi_slave *ns) +static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns) { u32 tm; u8 div; @@ -117,7 +117,7 @@ static int __ae3xx_spi_set_speed(struct nds_spi_slave *ns) } -static int __ae3xx_spi_claim_bus(struct nds_spi_slave *ns) +static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns) { unsigned int format=0; ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST); @@ -128,18 +128,18 @@ static int __ae3xx_spi_claim_bus(struct nds_spi_slave *ns) ns->cmd_len = 0; format = ns->mode|DATA_LENGTH(8); ns->regs->format = format; - __ae3xx_spi_set_speed(ns); + __atcspi200_spi_set_speed(ns); return 0; } -static int __ae3xx_spi_release_bus(struct nds_spi_slave *ns) +static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns) { /* do nothing */ return 0; } -static int __ae3xx_spi_start(struct nds_spi_slave *ns) +static int __atcspi200_spi_start(struct nds_spi_slave *ns) { int i,olen=0; int tc = ns->regs->tctrl; @@ -168,7 +168,7 @@ static int __ae3xx_spi_start(struct nds_spi_slave *ns) return 0; } -static int __ae3xx_spi_stop(struct nds_spi_slave *ns) +static int __atcspi200_spi_stop(struct nds_spi_slave *ns) { ns->regs->timing = ns->mtiming; while ((ns->regs->status & SPIBSY)&&(ns->to--)) @@ -190,7 +190,7 @@ static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int byte } -static int __ae3xx_spi_xfer(struct nds_spi_slave *ns, +static int __atcspi200_spi_xfer(struct nds_spi_slave *ns, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { @@ -230,7 +230,7 @@ static int __ae3xx_spi_xfer(struct nds_spi_slave *ns, memcpy(cmd_buf, data_out, cmd_len); data_out = 0; data_len = 0; - __ae3xx_spi_start(ns); + __atcspi200_spi_start(ns); break; } debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %u\n", @@ -245,7 +245,7 @@ static int __ae3xx_spi_xfer(struct nds_spi_slave *ns, num_bytes = (tran_len) % CHUNK_SIZE; if(num_bytes == 0) num_bytes = CHUNK_SIZE; - __ae3xx_spi_start(ns); + __atcspi200_spi_start(ns); while (num_blks) { event = in_le32(&ns->regs->status); @@ -279,9 +279,9 @@ static int __ae3xx_spi_xfer(struct nds_spi_slave *ns, ns->cmd_buf[3] += ((tran_len)&0xff); ns->data_len = data_len; } - ret = __ae3xx_spi_stop(ns); + ret = __atcspi200_spi_stop(ns); } - ret = __ae3xx_spi_stop(ns); + ret = __atcspi200_spi_stop(ns); return ret; } @@ -300,11 +300,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, switch (bus) { case SPI0_BUS: - ns->regs = (struct ae3xx_spi_regs *)SPI0_BASE; + ns->regs = (struct atcspi200_spi_regs *)SPI0_BASE; break; case SPI1_BUS: - ns->regs = (struct ae3xx_spi_regs *)SPI1_BASE; + ns->regs = (struct atcspi200_spi_regs *)SPI1_BASE; break; default: @@ -336,20 +336,20 @@ void spi_init(void) int spi_claim_bus(struct spi_slave *slave) { struct nds_spi_slave *ns = to_nds_spi_slave(slave); - return __ae3xx_spi_claim_bus(ns); + return __atcspi200_spi_claim_bus(ns); } void spi_release_bus(struct spi_slave *slave) { struct nds_spi_slave *ns = to_nds_spi_slave(slave); - __ae3xx_spi_release_bus(ns); + __atcspi200_spi_release_bus(ns); } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { struct nds_spi_slave *ns = to_nds_spi_slave(slave); - return __ae3xx_spi_xfer(ns, bitlen, data_out, data_in, flags); + return __atcspi200_spi_xfer(ns, bitlen, data_out, data_in, flags); } int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -360,28 +360,28 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { struct nds_spi_slave *ns = to_nds_spi_slave(slave); - __ae3xx_spi_start(ns); + __atcspi200_spi_start(ns); } void spi_cs_deactivate(struct spi_slave *slave) { struct nds_spi_slave *ns = to_nds_spi_slave(slave); - __ae3xx_spi_stop(ns); + __atcspi200_spi_stop(ns); } #else -static int ae3xx_spi_set_speed(struct udevice *bus, uint max_hz) +static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz) { struct nds_spi_slave *ns = dev_get_priv(bus); debug("%s speed %u\n", __func__, max_hz); ns->freq = max_hz; - __ae3xx_spi_set_speed(ns); + __atcspi200_spi_set_speed(ns); return 0; } -static int ae3xx_spi_set_mode(struct udevice *bus, uint mode) +static int atcspi200_spi_set_mode(struct udevice *bus, uint mode) { struct nds_spi_slave *ns = dev_get_priv(bus); @@ -391,7 +391,7 @@ static int ae3xx_spi_set_mode(struct udevice *bus, uint mode) return 0; } -static int ae3xx_spi_claim_bus(struct udevice *dev) +static int atcspi200_spi_claim_bus(struct udevice *dev) { struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); @@ -403,27 +403,27 @@ static int ae3xx_spi_claim_bus(struct udevice *dev) return -EINVAL; } - return __ae3xx_spi_claim_bus(ns); + return __atcspi200_spi_claim_bus(ns); } -static int ae3xx_spi_release_bus(struct udevice *dev) +static int atcspi200_spi_release_bus(struct udevice *dev) { struct nds_spi_slave *ns = dev_get_priv(dev->parent); - return __ae3xx_spi_release_bus(ns); + return __atcspi200_spi_release_bus(ns); } -static int ae3xx_spi_xfer(struct udevice *dev, unsigned int bitlen, +static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev->parent; struct nds_spi_slave *ns = dev_get_priv(bus); - return __ae3xx_spi_xfer(ns, bitlen, dout, din, flags); + return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags); } -static int ae3xx_spi_get_clk(struct udevice *bus) +static int atcspi200_spi_get_clk(struct udevice *bus) { struct nds_spi_slave *ns = dev_get_priv(bus); struct clk clk; @@ -444,26 +444,26 @@ static int ae3xx_spi_get_clk(struct udevice *bus) return 0; } -static int ae3xx_spi_probe(struct udevice *bus) +static int atcspi200_spi_probe(struct udevice *bus) { struct nds_spi_slave *ns = dev_get_priv(bus); ns->to = SPI_TIMEOUT; ns->max_transfer_length = MAX_TRANSFER_LEN; ns->mtiming = ns->regs->timing; - ae3xx_spi_get_clk(bus); + atcspi200_spi_get_clk(bus); return 0; } -static int ae3xx_ofdata_to_platadata(struct udevice *bus) +static int atcspi200_ofdata_to_platadata(struct udevice *bus) { struct nds_spi_slave *ns = dev_get_priv(bus); const void *blob = gd->fdt_blob; int node = dev_of_offset(bus); ns->regs = map_physmem(devfdt_get_addr(bus), - sizeof(struct ae3xx_spi_regs), + sizeof(struct atcspi200_spi_regs), MAP_NOCACHE); if (!ns->regs) { printf("%s: could not map device address\n", __func__); @@ -474,26 +474,26 @@ static int ae3xx_ofdata_to_platadata(struct udevice *bus) return 0; } -static const struct dm_spi_ops ae3xx_spi_ops = { - .claim_bus = ae3xx_spi_claim_bus, - .release_bus = ae3xx_spi_release_bus, - .xfer = ae3xx_spi_xfer, - .set_speed = ae3xx_spi_set_speed, - .set_mode = ae3xx_spi_set_mode, +static const struct dm_spi_ops atcspi200_spi_ops = { + .claim_bus = atcspi200_spi_claim_bus, + .release_bus = atcspi200_spi_release_bus, + .xfer = atcspi200_spi_xfer, + .set_speed = atcspi200_spi_set_speed, + .set_mode = atcspi200_spi_set_mode, }; -static const struct udevice_id ae3xx_spi_ids[] = { +static const struct udevice_id atcspi200_spi_ids[] = { { .compatible = "andestech,atcspi200" }, { } }; -U_BOOT_DRIVER(ae3xx_spi) = { - .name = "ae3xx_spi", +U_BOOT_DRIVER(atcspi200_spi) = { + .name = "atcspi200_spi", .id = UCLASS_SPI, - .of_match = ae3xx_spi_ids, - .ops = &ae3xx_spi_ops, - .ofdata_to_platdata = ae3xx_ofdata_to_platadata, + .of_match = atcspi200_spi_ids, + .ops = &atcspi200_spi_ops, + .ofdata_to_platdata = atcspi200_ofdata_to_platadata, .priv_auto_alloc_size = sizeof(struct nds_spi_slave), - .probe = ae3xx_spi_probe, + .probe = atcspi200_spi_probe, }; #endif diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6305bbf01cd..3a1f8311c12 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -105,11 +105,12 @@ config AG101P_TIMER help Select this to enable a timer for AG01P devices. -config AE3XX_TIMER - bool "AE3XX timer support" - depends on TIMER && NDS32 +config ATCPIT100_TIMER + bool "ATCPIT100 timer support" + depends on TIMER help - Select this to enable a timer for AE3XX devices. + Select this to enable a ATCPIT100 timer which will be embeded + in AE3XX, AE250 boards. config ROCKCHIP_TIMER bool "Rockchip timer support" diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 69e8961a7ba..15e515407e3 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -13,6 +13,6 @@ obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o -obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o +obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o diff --git a/drivers/timer/ae3xx_timer.c b/drivers/timer/atcpit100_timer.c index bcc07a0c864..963f978d206 100644 --- a/drivers/timer/ae3xx_timer.c +++ b/drivers/timer/atcpit100_timer.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; -#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2))) +#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2))) /* * Definition of register offsets @@ -67,51 +67,51 @@ struct atctmr_timer_regs { u32 int_mask; /* 0x38 */ }; -struct atftmr_timer_platdata { - unsigned long *regs; +struct atcpit_timer_platdata { + u32 *regs; }; -static int atftmr_timer_get_count(struct udevice *dev, u64 *count) +static int atcpit_timer_get_count(struct udevice *dev, u64 *count) { - struct atftmr_timer_platdata *plat = dev->platdata; + struct atcpit_timer_platdata *plat = dev_get_platdata(dev); u32 val; val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); *count = timer_conv_64(val); return 0; } -static int atctmr_timer_probe(struct udevice *dev) +static int atcpit_timer_probe(struct udevice *dev) { - struct atftmr_timer_platdata *plat = dev->platdata; + struct atcpit_timer_platdata *plat = dev_get_platdata(dev); REG32_TMR(CH_REL(1)) = 0xffffffff; REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); return 0; } -static int atctme_timer_ofdata_to_platdata(struct udevice *dev) +static int atcpit_timer_ofdata_to_platdata(struct udevice *dev) { - struct atftmr_timer_platdata *plat = dev_get_platdata(dev); + struct atcpit_timer_platdata *plat = dev_get_platdata(dev); plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE); return 0; } -static const struct timer_ops ag101p_timer_ops = { - .get_count = atftmr_timer_get_count, +static const struct timer_ops atcpit_timer_ops = { + .get_count = atcpit_timer_get_count, }; -static const struct udevice_id ag101p_timer_ids[] = { +static const struct udevice_id atcpit_timer_ids[] = { { .compatible = "andestech,atcpit100" }, {} }; -U_BOOT_DRIVER(altera_timer) = { - .name = "ae3xx_timer", +U_BOOT_DRIVER(atcpit100_timer) = { + .name = "atcpit100_timer", .id = UCLASS_TIMER, - .of_match = ag101p_timer_ids, - .ofdata_to_platdata = atctme_timer_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), - .probe = atctmr_timer_probe, - .ops = &ag101p_timer_ops, + .of_match = atcpit_timer_ids, + .ofdata_to_platdata = atcpit_timer_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata), + .probe = atcpit_timer_probe, + .ops = &atcpit_timer_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/dts/Makefile b/dts/Makefile index 3a93dafb516..c9b2a894418 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -22,10 +22,29 @@ DTB := $(ARCH_PATH)/$(DEVICE_TREE).dtb dtb_depends += $(DTB:.dtb=.dts) endif +# Pass the original device tree file through fdtgrep twice. The first pass +# removes any unwanted nodes (i.e. those which don't have the +# 'u-boot,dm-pre-reloc' property and thus are not needed by SPL. The second +# pass removes various unused properties from the remaining nodes. +# The output is typically a much smaller device tree file. +ifeq ($(CONFIG_TPL_BUILD),y) +fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-tpl +else +fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-spl +endif +quiet_cmd_fdtgrep = FDTGREP $@ + cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \ + -n /chosen -n /config -O dtb | \ + $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ + $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) + +$(obj)/dt-spl.dtb: $(DTB) $(objtree)/tools/fdtgrep FORCE + $(call if_changed,fdtgrep) + $(obj)/dt.dtb: $(DTB) FORCE $(call if_changed,shipped) -targets += dt.dtb +targets += dt.dtb dt-spl.dtb $(DTB): $(dtb_depends) ifeq ($(EXT_DTB),) @@ -42,14 +61,22 @@ endif arch-dtbs: $(Q)$(MAKE) $(build)=$(ARCH_PATH) dtbs -.SECONDARY: $(obj)/dt.dtb.S +.SECONDARY: $(obj)/dt.dtb.S $(obj)/dt-spl.dtb.S + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-$(CONFIG_OF_EMBED) := dt-spl.dtb.o +# support "out-of-tree" build for dtb-spl +$(obj)/dt-spl.dtb.o: $(obj)/dt-spl.dtb.S FORCE + $(call if_changed_dep,as_o_S) +else obj-$(CONFIG_OF_EMBED) := dt.dtb.o +endif -dtbs: $(obj)/dt.dtb +dtbs: $(obj)/dt.dtb $(obj)/dt-spl.dtb @: -clean-files := dt.dtb.S +clean-files := dt.dtb.S dt-spl.dtb.S # Let clean descend into dts directories subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts diff --git a/env/mmc.c b/env/mmc.c index 3343f9e9f6c..ed7bcf16ae0 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -73,7 +73,7 @@ static inline s64 mmc_offset(int copy) .partition = "u-boot,mmc-env-partition", .offset = "u-boot,mmc-env-offset", }; - s64 val, defvalue; + s64 val = 0, defvalue; const char *propname; const char *str; int err; diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 7fe78439cf1..d16883fa10d 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -1149,11 +1149,13 @@ typedef struct { int fat_opendir(const char *filename, struct fs_dir_stream **dirsp) { - fat_dir *dir = calloc(1, sizeof(*dir)); + fat_dir *dir; int ret; + dir = malloc_cache_aligned(sizeof(*dir)); if (!dir) return -ENOMEM; + memset(dir, 0, sizeof(*dir)); ret = fat_itr_root(&dir->itr, &dir->fsdata); if (ret) diff --git a/fs/fs_internal.c b/fs/fs_internal.c index 58b441030c8..5cdd272c9de 100644 --- a/fs/fs_internal.c +++ b/fs/fs_internal.c @@ -15,12 +15,13 @@ int fs_devread(struct blk_desc *blk, disk_partition_t *partition, lbaint_t sector, int byte_offset, int byte_len, char *buf) { unsigned block_len; - int log2blksz = blk->log2blksz; + int log2blksz; ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, (blk ? blk->blksz : 0)); if (blk == NULL) { printf("** Invalid Block Device Descriptor (NULL)\n"); return 0; } + log2blksz = blk->log2blksz; /* Check partition boundaries */ if ((sector + ((byte_offset + byte_len - 1) >> log2blksz)) diff --git a/include/common.h b/include/common.h index e14e1daa88b..6e245451789 100644 --- a/include/common.h +++ b/include/common.h @@ -201,6 +201,7 @@ int last_stage_init(void); extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ +extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ int set_cpu_clk_info(void); int mdm_init(void); int print_cpuinfo(void); diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index e0d0034ed34..5c469a23fa7 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -91,6 +91,10 @@ #define BOOTEFI_NAME "bootaa64.efi" #elif defined(CONFIG_ARM) #define BOOTEFI_NAME "bootarm.efi" +#elif defined(CONFIG_X86_RUN_32BIT) +#define BOOTEFI_NAME "bootia32.efi" +#elif defined(CONFIG_X86_RUN_64BIT) +#define BOOTEFI_NAME "bootx64.efi" #endif #endif diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h index 69460293330..5644a6153bc 100644 --- a/include/configs/adp-ae3xx.h +++ b/include/configs/adp-ae3xx.h @@ -91,7 +91,6 @@ /* * SD (MMC) controller */ -#define CONFIG_FTSDC010 #define CONFIG_FTSDC010_NUMBER 1 #define CONFIG_FTSDC010_SDIO diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index fad4d308e03..f2de3846313 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -97,7 +97,6 @@ /* * SD (MMC) controller */ -#define CONFIG_FTSDC010 #define CONFIG_FTSDC010_NUMBER 1 #define CONFIG_FTSDC010_SDIO diff --git a/include/configs/evb_rk3128.h b/include/configs/evb_rk3128.h new file mode 100644 index 00000000000..a34153aac5a --- /dev/null +++ b/include/configs/evb_rk3128.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EVB_RK3128_H +#define __EVB_RK3128_H + +#include <configs/rk3128_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h new file mode 100644 index 00000000000..9d99bc5dc7c --- /dev/null +++ b/include/configs/khadas-vim.h @@ -0,0 +1,21 @@ +/* + * Configuration for Khadas VIM + * + * Copyright (C) 2017 Baylibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MISC_INIT_R + +#define CONFIG_PHY_ADDR 8 + +#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0" + +#include <configs/meson-gxbb-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h new file mode 100644 index 00000000000..ffaca2648b8 --- /dev/null +++ b/include/configs/libretech-cc.h @@ -0,0 +1,21 @@ +/* + * Configuration for LibreTech CC + * + * Copyright (C) 2017 Baylibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MISC_INIT_R + +#define CONFIG_PHY_ADDR 8 + +#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0" + +#include <configs/meson-gxbb-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index d88d42de9ac..c2b306ad2e6 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -10,7 +10,7 @@ #define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF -#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 32 #define CONFIG_SYS_MALLOC_LEN (32 << 20) diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index fd60a9bfd48..d85527434a0 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -73,11 +73,6 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE -/* Environment in SPI NOR flash */ -#ifdef CONFIG_MVEBU_SPI_BOOT -/* Environment in NAND flash */ -#endif - #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index df50325ab66..42f21536379 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -86,8 +86,49 @@ /* Environment */ #define CONFIG_PREBOOT "usb start" +#if !defined(CONFIG_SPL_BUILD) + +#include <config_distro_defaults.h> + +#define MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV + +#if defined(CONFIG_NAND) +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "run nandboot\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " +#endif /* CONFIG_NAND */ + +#define BOOTENV_DEV_UIMAGE_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; " \ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_UIMAGE_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_ZIMAGE_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; " \ + "run mmcbootz\0" + +#define BOOTENV_DEV_NAME_ZIMAGE_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(ZIMAGE_MMC, zimage_mmc, 0) \ + func(UIMAGE_MMC, uimage_mmc, 0) \ + func(NAND, nand, 0) + +#include <config_distro_bootcmd.h> + #define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "bootenv=uEnv.txt\0" \ @@ -107,40 +148,39 @@ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t ${loadaddr} ${filesize}\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ + "mmcbootenv=" \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan && run loadbootenv; then " \ + "run importbootenv; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi\0" \ "loaduimage=setenv bootfile uImage; " \ "fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "loadzimage=setenv bootfile zImage; " \ "fatload mmc ${mmcdev} ${loadaddr} zImage\0" \ - "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} " CONFIG_DEFAULT_FDT_FILE "\0" \ - "mmcboot=echo Booting ${bootfile} from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "mmcbootz=echo Booting ${bootfile} from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ + "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "mmcboot=run mmcbootenv; " \ + "if run loaduimage && run loaddtb; then " \ + "echo Booting ${bootfile} from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "fi\0" \ + "mmcbootz=run mmcbootenv; " \ + "if run loadzimage && run loaddtb; then " \ + "echo Booting ${bootfile} from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr};" \ + "fi\0" \ "nandboot=echo Booting uImage from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} kernel; " \ "nand read ${fdtaddr} dtb; " \ - "bootm ${loadaddr} - ${fdtaddr}\0" + "bootm ${loadaddr} - ${fdtaddr}\0" \ + BOOTENV -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootenv; then " \ - "run importbootenv; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "else " \ - "if run loadzimage && run loaddtb; then " \ - "run mmcbootz; fi; " \ - "if run loaduimage && run loaddtb; then " \ - "run mmcboot; fi; " \ - "run nandboot; " \ - "fi; " \ - "else run nandboot; fi" +#endif /* !CONFIG_SPL_BUILD */ #endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 6deed0dcd70..2815e241dec 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -31,6 +31,11 @@ #define CONFIG_ARCH_CPU_INIT +/* Generic Interrupt Controller Definitions */ +#define CONFIG_GICV2 +#define GICD_BASE 0xF1010000 +#define GICC_BASE 0xF1020000 + /* console */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE @@ -43,30 +48,12 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define DRAM_RSV_SIZE 0x08000000 -#if defined(CONFIG_R8A7795) #define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) -#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2 0x500000000 -#define PHYS_SDRAM_2_SIZE 0x40000000u -#define PHYS_SDRAM_3 0x600000000 -#define PHYS_SDRAM_3_SIZE 0x40000000u -#define PHYS_SDRAM_4 0x700000000 -#define PHYS_SDRAM_4_SIZE 0x40000000u -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE -#elif defined(CONFIG_R8A7796) -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) -#define PHYS_SDRAM_1_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2 0x0600000000 -#define PHYS_SDRAM_2_SIZE 0x80000000u -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE -#endif +#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_LOAD_ADDR 0x48080000 #define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_SDRAM_SIZE +#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h new file mode 100644 index 00000000000..e915a562b92 --- /dev/null +++ b/include/configs/rk3128_common.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3128_COMMON_H +#define __CONFIG_RK3128_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_EXT4 + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 2 +#define SDRAM_MAX_SIZE 0x80000000 + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +#ifndef CONFIG_SPL_BUILD + +/* usb mass storage */ +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60500000\0" \ + "pxefile_addr_r=0x60600000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/rpi.h b/include/configs/rpi.h index c499b45b320..cab8661779e 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -76,7 +76,7 @@ #endif /* Console UART */ -#ifdef CONFIG_BCM2837 +#if defined (CONFIG_BCM2837) || defined(CONFIG_TARGET_RPI_0_W) #define CONFIG_BCM283X_MU_SERIAL #else #define CONFIG_PL01X_SERIAL diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 77a12de963d..33624e6c4ea 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -12,74 +12,22 @@ #undef DEBUG -#define CONFIG_RCAR_BOARD_STRING "Salvator-X" - #include "rcar-gen3-common.h" -/* SCIF */ -#define CONFIG_CONS_SCIF2 -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ - -/* [A] Hyper Flash */ -/* use to RPC(SPI Multi I/O Bus Controller) */ - /* Ethernet RAVB */ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI /* Board Clock */ /* XTAL_CLK : 33.33MHz */ -#define RCAR_XTAL_CLK 33333333u -#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK -/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ -/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ -#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) -#define CONFIG_S3D2_CLK_FREQ (266666666u/2) -#define CONFIG_S3D4_CLK_FREQ (266666666u/4) +#define CONFIG_SYS_CLK_FREQ 33333333u /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x60 -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 - -/* USB */ -#ifdef CONFIG_R8A7795 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#else -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 200000000 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 -/* Module stop status bits */ -/* MFIS, SCIF1 */ -#define CONFIG_SMSTP2_ENA 0x00002040 -/* SCIF2 */ -#define CONFIG_SMSTP3_ENA 0x00000400 -/* INTC-AP, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 - #endif /* __SALVATOR_X_H */ diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h deleted file mode 100644 index c52dcd4e8fd..00000000000 --- a/include/configs/sama5d2_ptc.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Configuration settings for the SAMA5D2 PTC Engineering board. - * - * Copyright (C) 2016 Atmel - * Wenyou Yang <wenyou.yang@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE 0xf801c000 -#define CONFIG_USART_ID 24 - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_TIMER_COUNTER 0xf804803c - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x210000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#undef CONFIG_AT91_GPIO -#define CONFIG_ATMEL_PIO4 - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 - -/* SerialFlash */ -#ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#endif - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x80000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION -/* PMECC & PMERRLOC */ -#define CONFIG_ATMEL_NAND_HWECC -#define CONFIG_ATMEL_NAND_HW_PMECC -#endif - -/* USB device */ - -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY - -#ifdef CONFIG_NAND_BOOT -#undef CONFIG_ENV_OFFSET -#undef CONFIG_ENV_OFFSET_REDUND -#undef CONFIG_BOOTCOMMAND -/* u-boot env in nand flash */ -#define CONFIG_ENV_OFFSET 0x200000 -#define CONFIG_ENV_OFFSET_REDUND 0x400000 -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \ - "nand read 0x22000000 0x600000 0x600000;" \ - "bootz 0x22000000 - 0x21000000" -#endif - -/* SPL */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 - -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#endif -#define CONFIG_PMECC_CAP 8 -#define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 224 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 -#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER - -#endif diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h new file mode 100644 index 00000000000..d99eaee18fd --- /dev/null +++ b/include/configs/sama5d2_ptc_ek.h @@ -0,0 +1,46 @@ +/* + * Configuration file for the SAMA5D2 PTC EK Board. + * + * Copyright (C) 2017 Microchip Technology Inc. + * Wenyou Yang <wenyou.yang@microchip.com> + * Ludovic Desroches <ludovic.desroches@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +#define CONFIG_MISC_INIT_R + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND Flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index b54e63c2a2f..dfd6436b3ca 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -12,96 +12,22 @@ #undef DEBUG -#define CONFIG_RCAR_BOARD_STRING "ULCB" - #include "rcar-gen3-common.h" -/* M3 ULCB has 2 banks, each with 1 GiB of RAM */ -#if defined(CONFIG_R8A7796) -#undef PHYS_SDRAM_1_SIZE -#undef PHYS_SDRAM_2_SIZE -#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2_SIZE 0x40000000u -#endif - -/* SCIF */ -#define CONFIG_CONS_SCIF2 -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ - -/* [A] Hyper Flash */ -/* use to RPC(SPI Multi I/O Bus Controller) */ - /* Ethernet RAVB */ -#define CONFIG_PHY_MICREL #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI /* Board Clock */ /* XTAL_CLK : 33.33MHz */ -#define RCAR_XTAL_CLK 33333333u -#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK -/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ -/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ -#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) -#define CONFIG_S3D2_CLK_FREQ (266666666u/2) -#define CONFIG_S3D4_CLK_FREQ (266666666u/4) +#define CONFIG_SYS_CLK_FREQ 33333333u /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - -/* CPLD SPI */ -#define CONFIG_CMD_SPI -#define CONFIG_SOFT_SPI -#define SPI_DELAY udelay(0) -#define SPI_SDA(val) ulcb_softspi_sda(val) -#define SPI_SCL(val) ulcb_softspi_scl(val) -#define SPI_READ ulcb_softspi_read() -#ifndef __ASSEMBLY__ -void ulcb_softspi_sda(int); -void ulcb_softspi_scl(int); -unsigned char ulcb_softspi_read(void); -#endif - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x60 -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 - -/* USB */ -#ifdef CONFIG_R8A7795 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#else -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 200000000 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 -/* Module stop status bits */ -/* MFIS, SCIF1 */ -#define CONFIG_SMSTP2_ENA 0x00002040 -/* SCIF2 */ -#define CONFIG_SMSTP3_ENA 0x00000400 -/* INTC-AP, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 - #endif /* __ULCB_H */ diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h new file mode 100644 index 00000000000..8989d55f53b --- /dev/null +++ b/include/configs/wb45n.h @@ -0,0 +1,161 @@ +/* + * Configuation settings for the WB45N CPU Module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC 1 +#define CONFIG_ATMEL_NAND_HW_PMECC 1 +#define CONFIG_PMECC_CAP 4 +#define CONFIG_PMECC_SECTOR_SIZE 512 + +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_ETHADDR C0:EE:40:00:00:00 +#define CONFIG_ENV_OVERWRITE 1 + +/* System */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#ifdef CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_OFFSET 0xa0000 +#define CONFIG_ENV_OFFSET_REDUND 0xc0000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */ + +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ + "run _mtd; bootm" + +#define MTDIDS_DEFAULT "nand0=atmel_nand" +#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ + "128K(at91bs)," \ + "512K(u-boot)," \ + "128K(u-boot-env)," \ + "128K(redund-env)," \ + "2560K(kernel-a)," \ + "2560K(kernel-b)," \ + "38912K(rootfs-a)," \ + "38912K(rootfs-b)," \ + "46208K(user)," \ + "512K(logs)" + +#else +#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' +#endif + +#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \ + "rw noinitrd mem=64M " \ + "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ + "autoload=no\0" \ + "autostart=no\0" \ + "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ + "\0" + +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x6000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#endif /* __CONFIG_H__ */ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h new file mode 100644 index 00000000000..4ab81c864b4 --- /dev/null +++ b/include/configs/wb50n.h @@ -0,0 +1,139 @@ +/* + * Configuation settings for the WB50N CPU Module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_IMAGE_FORMAT_LEGACY + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_DBGU + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x310000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_MEMTEST_START 0x21000000 +#define CONFIG_SYS_MEMTEST_END 0x22000000 +#define CONFIG_SYS_ALT_MEMTEST + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RGMII +#define CONFIG_ETHADDR C0:EE:40:00:00:00 +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "autostart=no\0" + +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_OFFSET 0xA0000 +#define CONFIG_ENV_OFFSET_REDUND 0xC0000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND \ + "nand read 0x22000000 0x000e0000 0x500000; " \ + "bootm" + +#define CONFIG_BOOTARGS \ + "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#endif diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h new file mode 100644 index 00000000000..476268a78b4 --- /dev/null +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_SARADC 91 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_VIO0 197 +#define ACLK_VIO1 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_SARADC 318 +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index e36cc69959c..44c09144938 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -90,6 +90,7 @@ #define STM32F7_RCC_APB2_TIM8 1 #define STM32F7_RCC_APB2_USART1 4 #define STM32F7_RCC_APB2_USART6 5 +#define STM32F7_RCC_APB2_SDMMC2 7 #define STM32F7_RCC_APB2_ADC1 8 #define STM32F7_RCC_APB2_ADC2 9 #define STM32F7_RCC_APB2_ADC3 10 diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h new file mode 100644 index 00000000000..063177bc987 --- /dev/null +++ b/include/stm32_rcc.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_RCC_H_ +#define __STM32_RCC_H_ + +#define AHB_PSC_1 0 +#define AHB_PSC_2 0x8 +#define AHB_PSC_4 0x9 +#define AHB_PSC_8 0xA +#define AHB_PSC_16 0xB +#define AHB_PSC_64 0xC +#define AHB_PSC_128 0xD +#define AHB_PSC_256 0xE +#define AHB_PSC_512 0xF + +#define APB_PSC_1 0 +#define APB_PSC_2 0x4 +#define APB_PSC_4 0x5 +#define APB_PSC_8 0x6 +#define APB_PSC_16 0x7 + +struct pll_psc { + u8 pll_m; + u16 pll_n; + u8 pll_p; + u8 pll_q; + u8 ahb_psc; + u8 apb1_psc; + u8 apb2_psc; +}; + +struct stm32_clk_info { + struct pll_psc sys_pll_psc; + bool has_overdrive; + bool v2; +}; + +enum soc_family { + STM32F4, + STM32F7, +}; + +struct stm32_rcc_clk { + char *drv_name; + enum soc_family soc; +}; + +struct stm32_rcc_regs { + u32 cr; /* RCC clock control */ + u32 pllcfgr; /* RCC PLL configuration */ + u32 cfgr; /* RCC clock configuration */ + u32 cir; /* RCC clock interrupt */ + u32 ahb1rstr; /* RCC AHB1 peripheral reset */ + u32 ahb2rstr; /* RCC AHB2 peripheral reset */ + u32 ahb3rstr; /* RCC AHB3 peripheral reset */ + u32 rsv0; + u32 apb1rstr; /* RCC APB1 peripheral reset */ + u32 apb2rstr; /* RCC APB2 peripheral reset */ + u32 rsv1[2]; + u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ + u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ + u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ + u32 rsv2; + u32 apb1enr; /* RCC APB1 peripheral clock enable */ + u32 apb2enr; /* RCC APB2 peripheral clock enable */ + u32 rsv3[2]; + u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ + u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ + u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ + u32 rsv4; + u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ + u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ + u32 rsv5[2]; + u32 bdcr; /* RCC Backup domain control */ + u32 csr; /* RCC clock control & status */ + u32 rsv6[2]; + u32 sscgr; /* RCC spread spectrum clock generation */ + u32 plli2scfgr; /* RCC PLLI2S configuration */ + /* below registers are only available on STM32F46x and STM32F7 SoCs*/ + u32 pllsaicfgr; /* PLLSAI configuration */ + u32 dckcfgr; /* dedicated clocks configuration register */ + /* Below registers are only available on STM32F7 SoCs */ + u32 dckcfgr2; /* dedicated clocks configuration register */ +}; + +#endif /* __STM32_RCC_H_ */ diff --git a/include/test/compression.h b/include/test/compression.h new file mode 100644 index 00000000000..646f117ed81 --- /dev/null +++ b/include/test/compression.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TEST_COMPRESSION_H__ +#define __TEST_COMPRESSION_H__ + +#include <test/test.h> + +/* Declare a new compression test */ +#define COMPRESSION_TEST(_name, _flags) \ + UNIT_TEST(_name, _flags, compression_test) + +#endif /* __TEST_ENV_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h index 0e94feb07a7..5f2e519084f 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -8,9 +8,26 @@ #ifndef __TEST_SUITES_H__ #define __TEST_SUITES_H__ +struct unit_test; + +/** + * cmd_ut_category() - Run a category of unit tests + * + * @name: Category name + * @tests: List of tests to run + * @n_ents: Number of tests in @tests + * @argc: Argument count provided. Must be <= 1. If this is 1 then all + * tests are run, otherwise only the one named @argv[1] is run. + * @argv: Arguments: argv[1] is the test to run (if @argc >= 2) + * @return 0 if OK, CMD_RET_FAILURE on failure + */ +int cmd_ut_category(const char *name, struct unit_test *tests, int n_ents, + int argc, char * const argv[]); + int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); #endif /* __TEST_SUITES_H__ */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index c4582eaccae..30ec6b92b27 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1176,21 +1176,33 @@ int fdtdec_setup_memory_size(void) #if defined(CONFIG_NR_DRAM_BANKS) int fdtdec_setup_memory_banksize(void) { - int bank, ret, mem; + int bank, ret, mem, reg = 0; struct fdt_resource res; - mem = fdt_path_offset(gd->fdt_blob, "/memory"); + mem = fdt_node_offset_by_prop_value(gd->fdt_blob, -1, "device_type", + "memory", 7); if (mem < 0) { debug("%s: Missing /memory node\n", __func__); return -EINVAL; } for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, &res); - if (ret == -FDT_ERR_NOTFOUND) - break; - if (ret != 0) + ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res); + if (ret == -FDT_ERR_NOTFOUND) { + reg = 0; + mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem, + "device_type", + "memory", 7); + if (mem == -FDT_ERR_NOTFOUND) + break; + + ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res); + if (ret == -FDT_ERR_NOTFOUND) + break; + } + if (ret != 0) { return -EINVAL; + } gd->bd->bi_dram[bank].start = (phys_addr_t)res.start; gd->bd->bi_dram[bank].size = @@ -1268,7 +1280,11 @@ int fdtdec_setup(void) # endif # ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ +# ifdef CONFIG_SPL_BUILD + gd->fdt_blob = __dtb_dt_spl_begin; +# else gd->fdt_blob = __dtb_dt_begin; +# endif # elif defined CONFIG_OF_SEPARATE # ifdef CONFIG_SPL_BUILD /* FDT is at end of BSS unless it is in a different memory region */ diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile index 369bbf9ba36..be42e946b79 100644 --- a/lib/libfdt/Makefile +++ b/lib/libfdt/Makefile @@ -8,6 +8,7 @@ # Use upstream code. obj-y += \ fdt.o \ + fdt_wip.o \ fdt_strerror.o \ fdt_sw.o \ fdt_empty_tree.o \ @@ -19,8 +20,7 @@ obj-$(CONFIG_OF_LIBFDT_OVERLAY) += fdt_overlay.o # TODO: split out the local modifiction. obj-y += \ fdt_ro.o \ - fdt_rw.o \ - fdt_wip.o \ + fdt_rw.o # U-Boot own file obj-y += fdt_region.o diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c index 63099f1d969..5bfc4da3707 100644 --- a/lib/libfdt/fdt_region.c +++ b/lib/libfdt/fdt_region.c @@ -16,6 +16,135 @@ #include "libfdt_internal.h" +#define FDT_MAX_DEPTH 32 + +static int str_in_list(const char *str, char * const list[], int count) +{ + int i; + + for (i = 0; i < count; i++) + if (!strcmp(list[i], str)) + return 1; + + return 0; +} + +int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, + char * const exc_prop[], int exc_prop_count, + struct fdt_region region[], int max_regions, + char *path, int path_len, int add_string_tab) +{ + int stack[FDT_MAX_DEPTH] = { 0 }; + char *end; + int nextoffset = 0; + uint32_t tag; + int count = 0; + int start = -1; + int depth = -1; + int want = 0; + int base = fdt_off_dt_struct(fdt); + + end = path; + *end = '\0'; + do { + const struct fdt_property *prop; + const char *name; + const char *str; + int include = 0; + int stop_at = 0; + int offset; + int len; + + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + stop_at = nextoffset; + + switch (tag) { + case FDT_PROP: + include = want >= 2; + stop_at = offset; + prop = fdt_get_property_by_offset(fdt, offset, NULL); + str = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); + if (str_in_list(str, exc_prop, exc_prop_count)) + include = 0; + break; + + case FDT_NOP: + include = want >= 2; + stop_at = offset; + break; + + case FDT_BEGIN_NODE: + depth++; + if (depth == FDT_MAX_DEPTH) + return -FDT_ERR_BADSTRUCTURE; + name = fdt_get_name(fdt, offset, &len); + if (end - path + 2 + len >= path_len) + return -FDT_ERR_NOSPACE; + if (end != path + 1) + *end++ = '/'; + strcpy(end, name); + end += len; + stack[depth] = want; + if (want == 1) + stop_at = offset; + if (str_in_list(path, inc, inc_count)) + want = 2; + else if (want) + want--; + else + stop_at = offset; + include = want; + break; + + case FDT_END_NODE: + include = want; + want = stack[depth--]; + while (end > path && *--end != '/') + ; + *end = '\0'; + break; + + case FDT_END: + include = 1; + break; + } + + if (include && start == -1) { + /* Should we merge with previous? */ + if (count && count <= max_regions && + offset == region[count - 1].offset + + region[count - 1].size - base) + start = region[--count].offset - base; + else + start = offset; + } + + if (!include && start != -1) { + if (count < max_regions) { + region[count].offset = base + start; + region[count].size = stop_at - start; + } + count++; + start = -1; + } + } while (tag != FDT_END); + + if (nextoffset != fdt_size_dt_struct(fdt)) + return -FDT_ERR_BADLAYOUT; + + /* Add a region for the END tag and the string table */ + if (count < max_regions) { + region[count].offset = base + start; + region[count].size = nextoffset - start; + if (add_string_tab) + region[count].size += fdt_size_dt_strings(fdt); + } + count++; + + return count; +} + /** * fdt_add_region() - Add a new region to our list * @info: State information diff --git a/lib/libfdt/fdt_wip.c b/lib/libfdt/fdt_wip.c index 01adad0ee97..6a771d06603 100644 --- a/lib/libfdt/fdt_wip.c +++ b/lib/libfdt/fdt_wip.c @@ -1,227 +1,2 @@ -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause - */ -#include <libfdt_env.h> - -#ifndef USE_HOSTCC -#include <fdt.h> -#include <libfdt.h> -#else -#include "fdt_host.h" -#endif - -#include "libfdt_internal.h" - -int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, - const char *name, int namelen, - uint32_t idx, const void *val, - int len) -{ - void *propval; - int proplen; - - propval = fdt_getprop_namelen_w(fdt, nodeoffset, name, namelen, - &proplen); - if (!propval) - return proplen; - - if (proplen < (len + idx)) - return -FDT_ERR_NOSPACE; - - memcpy((char *)propval + idx, val, len); - return 0; -} - -int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, - const void *val, int len) -{ - const void *propval; - int proplen; - - propval = fdt_getprop(fdt, nodeoffset, name, &proplen); - if (!propval) - return proplen; - - if (proplen != len) - return -FDT_ERR_NOSPACE; - - return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, - strlen(name), 0, - val, len); -} - -static void _fdt_nop_region(void *start, int len) -{ - fdt32_t *p; - - for (p = start; (char *)p < ((char *)start + len); p++) - *p = cpu_to_fdt32(FDT_NOP); -} - -int fdt_nop_property(void *fdt, int nodeoffset, const char *name) -{ - struct fdt_property *prop; - int len; - - prop = fdt_get_property_w(fdt, nodeoffset, name, &len); - if (!prop) - return len; - - _fdt_nop_region(prop, len + sizeof(*prop)); - - return 0; -} - -int _fdt_node_end_offset(void *fdt, int offset) -{ - int depth = 0; - - while ((offset >= 0) && (depth >= 0)) - offset = fdt_next_node(fdt, offset, &depth); - - return offset; -} - -int fdt_nop_node(void *fdt, int nodeoffset) -{ - int endoffset; - - endoffset = _fdt_node_end_offset(fdt, nodeoffset); - if (endoffset < 0) - return endoffset; - - _fdt_nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0), - endoffset - nodeoffset); - return 0; -} - -#define FDT_MAX_DEPTH 32 - -static int str_in_list(const char *str, char * const list[], int count) -{ - int i; - - for (i = 0; i < count; i++) - if (!strcmp(list[i], str)) - return 1; - - return 0; -} - -int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, - char * const exc_prop[], int exc_prop_count, - struct fdt_region region[], int max_regions, - char *path, int path_len, int add_string_tab) -{ - int stack[FDT_MAX_DEPTH] = { 0 }; - char *end; - int nextoffset = 0; - uint32_t tag; - int count = 0; - int start = -1; - int depth = -1; - int want = 0; - int base = fdt_off_dt_struct(fdt); - - end = path; - *end = '\0'; - do { - const struct fdt_property *prop; - const char *name; - const char *str; - int include = 0; - int stop_at = 0; - int offset; - int len; - - offset = nextoffset; - tag = fdt_next_tag(fdt, offset, &nextoffset); - stop_at = nextoffset; - - switch (tag) { - case FDT_PROP: - include = want >= 2; - stop_at = offset; - prop = fdt_get_property_by_offset(fdt, offset, NULL); - str = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); - if (str_in_list(str, exc_prop, exc_prop_count)) - include = 0; - break; - - case FDT_NOP: - include = want >= 2; - stop_at = offset; - break; - - case FDT_BEGIN_NODE: - depth++; - if (depth == FDT_MAX_DEPTH) - return -FDT_ERR_BADSTRUCTURE; - name = fdt_get_name(fdt, offset, &len); - if (end - path + 2 + len >= path_len) - return -FDT_ERR_NOSPACE; - if (end != path + 1) - *end++ = '/'; - strcpy(end, name); - end += len; - stack[depth] = want; - if (want == 1) - stop_at = offset; - if (str_in_list(path, inc, inc_count)) - want = 2; - else if (want) - want--; - else - stop_at = offset; - include = want; - break; - - case FDT_END_NODE: - include = want; - want = stack[depth--]; - while (end > path && *--end != '/') - ; - *end = '\0'; - break; - - case FDT_END: - include = 1; - break; - } - - if (include && start == -1) { - /* Should we merge with previous? */ - if (count && count <= max_regions && - offset == region[count - 1].offset + - region[count - 1].size - base) - start = region[--count].offset - base; - else - start = offset; - } - - if (!include && start != -1) { - if (count < max_regions) { - region[count].offset = base + start; - region[count].size = stop_at - start; - } - count++; - start = -1; - } - } while (tag != FDT_END); - - if (nextoffset != fdt_size_dt_struct(fdt)) - return -FDT_ERR_BADLAYOUT; - - /* Add a region for the END tag and the string table */ - if (count < max_regions) { - region[count].offset = base + start; - region[count].size = nextoffset - start; - if (add_string_tab) - region[count].size += fdt_size_dt_strings(fdt); - } - count++; - - return count; -} +#include <linux/libfdt_env.h> +#include "../../scripts/dtc/libfdt/fdt_wip.c" diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index b5e7019ea36..64390e57859 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -239,24 +239,8 @@ $(obj)/$(SPL_BIN)-pad.bin: $(obj)/$(SPL_BIN) @bss_size_str=$(shell $(NM) $< | awk 'BEGIN {size = 0} /__bss_size/ {size = $$1} END {print "ibase=16; " toupper(size)}' | bc); \ dd if=/dev/zero of=$@ bs=1 count=$${bss_size_str} 2>/dev/null; -# Pass the original device tree file through fdtgrep twice. The first pass -# removes any unwanted nodes (i.e. those which don't have the -# 'u-boot,dm-pre-reloc' property and thus are not needed by SPL. The second -# pass removes various unused properties from the remaining nodes. -# The output is typically a much smaller device tree file. -ifeq ($(CONFIG_TPL_BUILD),y) -fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-tpl -else -fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-spl -endif -quiet_cmd_fdtgrep = FDTGREP $@ - cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \ - -n /chosen -n /config -O dtb | \ - $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ - $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) - -$(obj)/$(SPL_BIN).dtb: dts/dt.dtb $(objtree)/tools/fdtgrep FORCE - $(call if_changed,fdtgrep) +$(obj)/$(SPL_BIN).dtb: dts/dt-spl.dtb FORCE + $(call if_changed,copy) pythonpath = PYTHONPATH=scripts/dtc/pylibfdt diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl index 15d0836b49a..b3994110dc7 100644 --- a/scripts/Makefile.uncmd_spl +++ b/scripts/Makefile.uncmd_spl @@ -9,7 +9,7 @@ ifdef CONFIG_SPL_BUILD ifndef CONFIG_SPL_DM CONFIG_DM_SERIAL= CONFIG_DM_GPIO= -CONIFG_DM_I2C= +CONFIG_DM_I2C= CONFIG_DM_SPI= CONFIG_DM_SPI_FLASH= endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4ce87484c34..c2fe81e5520 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -346,7 +346,6 @@ CONFIG_CPU_SH7785 CONFIG_CPU_SH_TYPE_R CONFIG_CPU_TYPE_R CONFIG_CPU_VR41XX -CONFIG_CP_CLK_FREQ CONFIG_CQSPI_DECODER CONFIG_CQSPI_REF_CLK CONFIG_CRC32 @@ -1886,8 +1885,6 @@ CONFIG_RUN_FROM_DDR1 CONFIG_RUN_FROM_IRAM_ONLY CONFIG_RX_DESCR_NUM CONFIG_S32V234 -CONFIG_S3D2_CLK_FREQ -CONFIG_S3D4_CLK_FREQ CONFIG_S5P CONFIG_S5PC100 CONFIG_S5PC110 diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 14333423a17..6b24f463f33 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -8,9 +8,34 @@ #include <common.h> #include <command.h> #include <test/suites.h> +#include <test/test.h> static int do_ut_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int cmd_ut_category(const char *name, struct unit_test *tests, int n_ents, + int argc, char * const argv[]) +{ + struct unit_test_state uts = { .fail_count = 0 }; + struct unit_test *test; + + if (argc == 1) + printf("Running %d %s tests\n", n_ents, name); + + for (test = tests; test < tests + n_ents; test++) { + if (argc > 1 && strcmp(argv[1], test->name)) + continue; + printf("Test: %s\n", test->name); + + uts.start = mallinfo(); + + test->func(&uts); + } + + printf("Failures: %d\n", uts.fail_count); + + return uts.fail_count ? CMD_RET_FAILURE : 0; +} + static cmd_tbl_t cmd_ut_sub[] = { U_BOOT_CMD_MKENT(all, CONFIG_SYS_MAXARGS, 1, do_ut_all, "", ""), #if defined(CONFIG_UT_DM) @@ -25,6 +50,10 @@ static cmd_tbl_t cmd_ut_sub[] = { #ifdef CONFIG_UT_TIME U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""), #endif +#ifdef CONFIG_SANDBOX + U_BOOT_CMD_MKENT(compression, CONFIG_SYS_MAXARGS, 1, do_ut_compression, + "", ""), +#endif }; static int do_ut_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -77,6 +106,9 @@ static char ut_help_text[] = #ifdef CONFIG_UT_TIME "ut time - Very basic test of time functions\n" #endif +#ifdef CONFIG_SANDBOX + "ut compression - Test compressors and bootm decompression\n" +#endif ; #endif diff --git a/test/compression.c b/test/compression.c index be4e04e6cc0..fe27ad66ea4 100644 --- a/test/compression.c +++ b/test/compression.c @@ -4,8 +4,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#define DEBUG - #include <common.h> #include <bootm.h> #include <command.h> @@ -21,6 +19,9 @@ #include <lzma/LzmaTools.h> #include <linux/lzo.h> +#include <test/compression.h> +#include <test/suites.h> +#include <test/ut.h> static const char plain[] = "I am a highly compressable bit of text.\n" @@ -120,10 +121,11 @@ static const unsigned long lz4_compressed_size = 276; #define TEST_BUFFER_SIZE 512 -typedef int (*mutate_func)(void *, unsigned long, void *, unsigned long, - unsigned long *); +typedef int (*mutate_func)(struct unit_test_state *uts, void *, unsigned long, + void *, unsigned long, unsigned long *); -static int compress_using_gzip(void *in, unsigned long in_size, +static int compress_using_gzip(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { @@ -137,7 +139,8 @@ static int compress_using_gzip(void *in, unsigned long in_size, return ret; } -static int uncompress_using_gzip(void *in, unsigned long in_size, +static int uncompress_using_gzip(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { @@ -151,13 +154,14 @@ static int uncompress_using_gzip(void *in, unsigned long in_size, return ret; } -static int compress_using_bzip2(void *in, unsigned long in_size, +static int compress_using_bzip2(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { /* There is no bzip2 compression in u-boot, so fake it. */ - assert(in_size == strlen(plain)); - assert(memcmp(plain, in, in_size) == 0); + ut_asserteq(in_size, strlen(plain)); + ut_asserteq(0, memcmp(plain, in, in_size)); if (bzip2_compressed_size > out_max) return -1; @@ -169,7 +173,8 @@ static int compress_using_bzip2(void *in, unsigned long in_size, return 0; } -static int uncompress_using_bzip2(void *in, unsigned long in_size, +static int uncompress_using_bzip2(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { @@ -184,13 +189,14 @@ static int uncompress_using_bzip2(void *in, unsigned long in_size, return (ret != BZ_OK); } -static int compress_using_lzma(void *in, unsigned long in_size, +static int compress_using_lzma(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { /* There is no lzma compression in u-boot, so fake it. */ - assert(in_size == strlen(plain)); - assert(memcmp(plain, in, in_size) == 0); + ut_asserteq(in_size, strlen(plain)); + ut_asserteq(0, memcmp(plain, in, in_size)); if (lzma_compressed_size > out_max) return -1; @@ -202,7 +208,8 @@ static int compress_using_lzma(void *in, unsigned long in_size, return 0; } -static int uncompress_using_lzma(void *in, unsigned long in_size, +static int uncompress_using_lzma(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { @@ -216,13 +223,14 @@ static int uncompress_using_lzma(void *in, unsigned long in_size, return (ret != SZ_OK); } -static int compress_using_lzo(void *in, unsigned long in_size, +static int compress_using_lzo(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { /* There is no lzo compression in u-boot, so fake it. */ - assert(in_size == strlen(plain)); - assert(memcmp(plain, in, in_size) == 0); + ut_asserteq(in_size, strlen(plain)); + ut_asserteq(0, memcmp(plain, in, in_size)); if (lzo_compressed_size > out_max) return -1; @@ -234,7 +242,8 @@ static int compress_using_lzo(void *in, unsigned long in_size, return 0; } -static int uncompress_using_lzo(void *in, unsigned long in_size, +static int uncompress_using_lzo(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { @@ -249,13 +258,14 @@ static int uncompress_using_lzo(void *in, unsigned long in_size, return (ret != LZO_E_OK); } -static int compress_using_lz4(void *in, unsigned long in_size, +static int compress_using_lz4(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { /* There is no lz4 compression in u-boot, so fake it. */ - assert(in_size == strlen(plain)); - assert(memcmp(plain, in, in_size) == 0); + ut_asserteq(in_size, strlen(plain)); + ut_asserteq(0, memcmp(plain, in, in_size)); if (lz4_compressed_size > out_max) return -1; @@ -267,7 +277,8 @@ static int compress_using_lz4(void *in, unsigned long in_size, return 0; } -static int uncompress_using_lz4(void *in, unsigned long in_size, +static int uncompress_using_lz4(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { @@ -288,73 +299,69 @@ static int uncompress_using_lz4(void *in, unsigned long in_size, goto out; \ } -static int run_test(char *name, mutate_func compress, mutate_func uncompress) -{ - ulong orig_size, compressed_size, uncompressed_size; +struct buf_state { + ulong orig_size; + ulong compressed_size; + ulong uncompressed_size; void *orig_buf; - void *compressed_buf = NULL; - void *uncompressed_buf = NULL; - void *compare_buf = NULL; + void *compressed_buf; + void *uncompressed_buf; + void *compare_buf; +}; + +static int run_test_internal(struct unit_test_state *uts, char *name, + mutate_func compress, mutate_func uncompress, + struct buf_state *buf) +{ int ret; - printf(" testing %s ...\n", name); - - orig_buf = (void *)plain; - orig_size = strlen(orig_buf); /* Trailing NULL not included. */ - errcheck(orig_size > 0); - - compressed_size = uncompressed_size = TEST_BUFFER_SIZE; - compressed_buf = malloc(compressed_size); - errcheck(compressed_buf != NULL); - uncompressed_buf = malloc(uncompressed_size); - errcheck(uncompressed_buf != NULL); - compare_buf = malloc(uncompressed_size); - errcheck(compare_buf != NULL); - /* Compress works as expected. */ - printf("\torig_size:%lu\n", orig_size); - memset(compressed_buf, 'A', TEST_BUFFER_SIZE); - errcheck(compress(orig_buf, orig_size, - compressed_buf, compressed_size, - &compressed_size) == 0); - printf("\tcompressed_size:%lu\n", compressed_size); - errcheck(compressed_size > 0); - errcheck(compressed_size < orig_size); - errcheck(((char *)compressed_buf)[compressed_size-1] != 'A'); - errcheck(((char *)compressed_buf)[compressed_size] == 'A'); + printf("\torig_size:%lu\n", buf->orig_size); + memset(buf->compressed_buf, 'A', TEST_BUFFER_SIZE); + errcheck(compress(uts, buf->orig_buf, buf->orig_size, + buf->compressed_buf, buf->compressed_size, + &buf->compressed_size) == 0); + printf("\tcompressed_size:%lu\n", buf->compressed_size); + errcheck(buf->compressed_size > 0); + errcheck(buf->compressed_size < buf->orig_size); + errcheck(((char *)buf->compressed_buf)[buf->compressed_size - 1] != + 'A'); + errcheck(((char *)buf->compressed_buf)[buf->compressed_size] == 'A'); /* Uncompresses with space remaining. */ - errcheck(uncompress(compressed_buf, compressed_size, - uncompressed_buf, uncompressed_size, - &uncompressed_size) == 0); - printf("\tuncompressed_size:%lu\n", uncompressed_size); - errcheck(uncompressed_size == orig_size); - errcheck(memcmp(orig_buf, uncompressed_buf, orig_size) == 0); + errcheck(uncompress(uts, buf->compressed_buf, buf->compressed_size, + buf->uncompressed_buf, buf->uncompressed_size, + &buf->uncompressed_size) == 0); + printf("\tuncompressed_size:%lu\n", buf->uncompressed_size); + errcheck(buf->uncompressed_size == buf->orig_size); + errcheck(memcmp(buf->orig_buf, buf->uncompressed_buf, + buf->orig_size) == 0); /* Uncompresses with exactly the right size output buffer. */ - memset(uncompressed_buf, 'A', TEST_BUFFER_SIZE); - errcheck(uncompress(compressed_buf, compressed_size, - uncompressed_buf, orig_size, - &uncompressed_size) == 0); - errcheck(uncompressed_size == orig_size); - errcheck(memcmp(orig_buf, uncompressed_buf, orig_size) == 0); - errcheck(((char *)uncompressed_buf)[orig_size] == 'A'); + memset(buf->uncompressed_buf, 'A', TEST_BUFFER_SIZE); + errcheck(uncompress(uts, buf->compressed_buf, buf->compressed_size, + buf->uncompressed_buf, buf->orig_size, + &buf->uncompressed_size) == 0); + errcheck(buf->uncompressed_size == buf->orig_size); + errcheck(memcmp(buf->orig_buf, buf->uncompressed_buf, + buf->orig_size) == 0); + errcheck(((char *)buf->uncompressed_buf)[buf->orig_size] == 'A'); /* Make sure compression does not over-run. */ - memset(compare_buf, 'A', TEST_BUFFER_SIZE); - ret = compress(orig_buf, orig_size, - compare_buf, compressed_size - 1, + memset(buf->compare_buf, 'A', TEST_BUFFER_SIZE); + ret = compress(uts, buf->orig_buf, buf->orig_size, + buf->compare_buf, buf->compressed_size - 1, NULL); - errcheck(((char *)compare_buf)[compressed_size] == 'A'); + errcheck(((char *)buf->compare_buf)[buf->compressed_size] == 'A'); errcheck(ret != 0); printf("\tcompress does not overrun\n"); /* Make sure decompression does not over-run. */ - memset(compare_buf, 'A', TEST_BUFFER_SIZE); - ret = uncompress(compressed_buf, compressed_size, - compare_buf, uncompressed_size - 1, + memset(buf->compare_buf, 'A', TEST_BUFFER_SIZE); + ret = uncompress(uts, buf->compressed_buf, buf->compressed_size, + buf->compare_buf, buf->uncompressed_size - 1, NULL); - errcheck(((char *)compare_buf)[uncompressed_size - 1] == 'A'); + errcheck(((char *)buf->compare_buf)[buf->uncompressed_size - 1] == 'A'); errcheck(ret != 0); printf("\tuncompress does not overrun\n"); @@ -362,32 +369,76 @@ static int run_test(char *name, mutate_func compress, mutate_func uncompress) ret = 0; out: + return ret; +} + +static int run_test(struct unit_test_state *uts, char *name, + mutate_func compress, mutate_func uncompress) +{ + struct buf_state sbuf, *buf = &sbuf; + int ret; + + printf(" testing %s ...\n", name); + + buf->orig_buf = (void *)plain; + buf->orig_size = strlen(buf->orig_buf); /* Trailing NUL not included */ + errcheck(buf->orig_size > 0); + + buf->compressed_size = TEST_BUFFER_SIZE; + buf->uncompressed_size = TEST_BUFFER_SIZE; + buf->compressed_buf = malloc(buf->compressed_size); + errcheck(buf->compressed_buf); + buf->uncompressed_buf = malloc(buf->uncompressed_size); + errcheck(buf->uncompressed_buf); + buf->compare_buf = malloc(buf->uncompressed_size); + errcheck(buf->compare_buf); + + ret = run_test_internal(uts, name, compress, uncompress, buf); +out: printf(" %s: %s\n", name, ret == 0 ? "ok" : "FAILED"); - free(compare_buf); - free(uncompressed_buf); - free(compressed_buf); + free(buf->compare_buf); + free(buf->uncompressed_buf); + free(buf->compressed_buf); return ret; } -static int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) +static int compression_test_gzip(struct unit_test_state *uts) { - int err = 0; + return run_test(uts, "gzip", compress_using_gzip, + uncompress_using_gzip); +} +COMPRESSION_TEST(compression_test_gzip, 0); + +static int compression_test_bzip2(struct unit_test_state *uts) +{ + return run_test(uts, "bzip2", compress_using_bzip2, + uncompress_using_bzip2); +} +COMPRESSION_TEST(compression_test_bzip2, 0); - err += run_test("gzip", compress_using_gzip, uncompress_using_gzip); - err += run_test("bzip2", compress_using_bzip2, uncompress_using_bzip2); - err += run_test("lzma", compress_using_lzma, uncompress_using_lzma); - err += run_test("lzo", compress_using_lzo, uncompress_using_lzo); - err += run_test("lz4", compress_using_lz4, uncompress_using_lz4); +static int compression_test_lzma(struct unit_test_state *uts) +{ + return run_test(uts, "lzma", compress_using_lzma, + uncompress_using_lzma); +} +COMPRESSION_TEST(compression_test_lzma, 0); - printf("ut_compression %s\n", err == 0 ? "ok" : "FAILED"); +static int compression_test_lzo(struct unit_test_state *uts) +{ + return run_test(uts, "lzo", compress_using_lzo, uncompress_using_lzo); +} +COMPRESSION_TEST(compression_test_lzo, 0); - return err; +static int compression_test_lz4(struct unit_test_state *uts) +{ + return run_test(uts, "lz4", compress_using_lz4, uncompress_using_lz4); } +COMPRESSION_TEST(compression_test_lz4, 0); -static int compress_using_none(void *in, unsigned long in_size, +static int compress_using_none(struct unit_test_state *uts, + void *in, unsigned long in_size, void *out, unsigned long out_max, unsigned long *out_size) { @@ -405,7 +456,8 @@ static int compress_using_none(void *in, unsigned long in_size, * @compress: Our function to compress data * @return 0 if OK, non-zero on failure */ -static int run_bootm_test(int comp_type, mutate_func compress) +static int run_bootm_test(struct unit_test_state *uts, int comp_type, + mutate_func compress) { ulong compress_size = 1024; void *compress_buff; @@ -418,20 +470,18 @@ static int run_bootm_test(int comp_type, mutate_func compress) printf("Testing: %s\n", genimg_get_comp_name(comp_type)); compress_buff = map_sysmem(image_start, 0); unc_len = strlen(plain); - compress((void *)plain, unc_len, compress_buff, compress_size, + compress(uts, (void *)plain, unc_len, compress_buff, compress_size, &compress_size); err = bootm_decomp_image(comp_type, load_addr, image_start, IH_TYPE_KERNEL, map_sysmem(load_addr, 0), compress_buff, compress_size, unc_len, &load_end); - if (err) - return err; + ut_assertok(err); err = bootm_decomp_image(comp_type, load_addr, image_start, IH_TYPE_KERNEL, map_sysmem(load_addr, 0), compress_buff, compress_size, unc_len - 1, &load_end); - if (!err) - return -EINVAL; + ut_assert(err); /* We can't detect corruption when not decompressing */ if (comp_type == IH_COMP_NONE) @@ -442,35 +492,52 @@ static int run_bootm_test(int comp_type, mutate_func compress) IH_TYPE_KERNEL, map_sysmem(load_addr, 0), compress_buff, compress_size, 0x10000, &load_end); - if (!err) - return -EINVAL; + ut_assert(err); return 0; } -static int do_ut_image_decomp(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) +static int compression_test_bootm_gzip(struct unit_test_state *uts) { - int err = 0; + return run_bootm_test(uts, IH_COMP_GZIP, compress_using_gzip); +} +COMPRESSION_TEST(compression_test_bootm_gzip, 0); + +static int compression_test_bootm_bzip2(struct unit_test_state *uts) +{ + return run_bootm_test(uts, IH_COMP_BZIP2, compress_using_bzip2); +} +COMPRESSION_TEST(compression_test_bootm_bzip2, 0); - err = run_bootm_test(IH_COMP_GZIP, compress_using_gzip); - err |= run_bootm_test(IH_COMP_BZIP2, compress_using_bzip2); - err |= run_bootm_test(IH_COMP_LZMA, compress_using_lzma); - err |= run_bootm_test(IH_COMP_LZO, compress_using_lzo); - err |= run_bootm_test(IH_COMP_LZ4, compress_using_lz4); - err |= run_bootm_test(IH_COMP_NONE, compress_using_none); +static int compression_test_bootm_lzma(struct unit_test_state *uts) +{ + return run_bootm_test(uts, IH_COMP_LZMA, compress_using_lzma); +} +COMPRESSION_TEST(compression_test_bootm_lzma, 0); - printf("ut_image_decomp %s\n", err == 0 ? "ok" : "FAILED"); +static int compression_test_bootm_lzo(struct unit_test_state *uts) +{ + return run_bootm_test(uts, IH_COMP_LZO, compress_using_lzo); +} +COMPRESSION_TEST(compression_test_bootm_lzo, 0); - return 0; +static int compression_test_bootm_lz4(struct unit_test_state *uts) +{ + return run_bootm_test(uts, IH_COMP_LZ4, compress_using_lz4); } +COMPRESSION_TEST(compression_test_bootm_lz4, 0); -U_BOOT_CMD( - ut_compression, 5, 1, do_ut_compression, - "Basic test of compressors: gzip bzip2 lzma lzo", "" -); +static int compression_test_bootm_none(struct unit_test_state *uts) +{ + return run_bootm_test(uts, IH_COMP_NONE, compress_using_none); +} +COMPRESSION_TEST(compression_test_bootm_none, 0); -U_BOOT_CMD( - ut_image_decomp, 5, 1, do_ut_image_decomp, - "Basic test of bootm decompression", "" -); +int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct unit_test *tests = ll_entry_start(struct unit_test, + compression_test); + const int n_ents = ll_entry_count(struct unit_test, compression_test); + + return cmd_ut_category("compression", tests, n_ents, argc, argv); +} diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c index 893e5e6a6d6..096afa83dde 100644 --- a/test/env/cmd_ut_env.c +++ b/test/env/cmd_ut_env.c @@ -15,23 +15,6 @@ int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct unit_test *tests = ll_entry_start(struct unit_test, env_test); const int n_ents = ll_entry_count(struct unit_test, env_test); - struct unit_test_state uts = { .fail_count = 0 }; - struct unit_test *test; - if (argc == 1) - printf("Running %d environment tests\n", n_ents); - - for (test = tests; test < tests + n_ents; test++) { - if (argc > 1 && strcmp(argv[1], test->name)) - continue; - printf("Test: %s\n", test->name); - - uts.start = mallinfo(); - - test->func(&uts); - } - - printf("Failures: %d\n", uts.fail_count); - - return uts.fail_count ? CMD_RET_FAILURE : 0; + return cmd_ut_category("environment", tests, n_ents, argc, argv); } diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c index c730a11f518..6279e6d0c20 100644 --- a/test/overlay/cmd_ut_overlay.c +++ b/test/overlay/cmd_ut_overlay.c @@ -14,6 +14,7 @@ #include <test/ut.h> #include <test/overlay.h> +#include <test/suites.h> /* 4k ought to be enough for anybody */ #define FDT_COPY_SIZE (4 * SZ_1K) @@ -221,7 +222,6 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) overlay_test); const int n_ents = ll_entry_count(struct unit_test, overlay_test); struct unit_test_state *uts; - struct unit_test *test; void *fdt_base = &__dtb_test_fdt_base_begin; void *fdt_overlay = &__dtb_test_fdt_overlay_begin; void *fdt_overlay_stacked = &__dtb_test_fdt_overlay_stacked_begin; @@ -280,24 +280,7 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Apply the stacked overlay */ ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_stacked_copy)); - if (argc == 1) - printf("Running %d environment tests\n", n_ents); - - for (test = tests; test < tests + n_ents; test++) { - if (argc > 1 && strcmp(argv[1], test->name)) - continue; - printf("Test: %s\n", test->name); - - uts->start = mallinfo(); - - test->func(uts); - } - - printf("Failures: %d\n", uts->fail_count); - if (!uts->fail_count) - ret = 0; - else - ret = CMD_RET_FAILURE; + ret = cmd_ut_category("overlay", tests, n_ents, argc, argv); free(fdt_overlay_stacked_copy); err3: diff --git a/test/py/conftest.py b/test/py/conftest.py index 6e66a48c15f..3fe91e87460 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -200,7 +200,7 @@ def pytest_configure(config): import u_boot_console_exec_attach console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig) -re_ut_test_list = re.compile(r'_u_boot_list_2_(dm|env)_test_2_\1_test_(.*)\s*$') +re_ut_test_list = re.compile(r'_u_boot_list_2_(.*)_test_2_\1_test_(.*)\s*$') def generate_ut_subtest(metafunc, fixture_name): """Provide parametrization for a ut_subtest fixture. diff --git a/tools/Makefile b/tools/Makefile index acbcd87af28..4d32fe5910f 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -61,11 +61,11 @@ FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o # The following files are synced with upstream DTC. # Use synced versions from scripts/dtc/libfdt/. -LIBFDT_SRCS_SYNCED := fdt.c fdt_sw.c fdt_strerror.c fdt_empty_tree.c \ +LIBFDT_SRCS_SYNCED := fdt.c fdt_wip.c fdt_sw.c fdt_strerror.c fdt_empty_tree.c \ fdt_addresses.c fdt_overlay.c # The following files are locally modified for U-Boot (unfotunately). # Use U-Boot own versions from lib/libfdt/. -LIBFDT_SRCS_UNSYNCED := fdt_ro.c fdt_wip.c fdt_rw.c fdt_region.c +LIBFDT_SRCS_UNSYNCED := fdt_ro.c fdt_rw.c fdt_region.c LIBFDT_OBJS := $(addprefix libfdt/, $(patsubst %.c, %.o, $(LIBFDT_SRCS_SYNCED))) \ $(addprefix lib/libfdt/, $(patsubst %.c, %.o, $(LIBFDT_SRCS_UNSYNCED))) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 963a6152a50..18c2324d2fc 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -25,6 +25,7 @@ #include <sys/ioctl.h> #include <sys/stat.h> #include <unistd.h> +#include <dirent.h> #ifdef MTD_OLD # include <stdint.h> @@ -34,6 +35,8 @@ # include <mtd/mtd-user.h> #endif +#include <mtd/ubi-user.h> + #include "fw_env_private.h" #include "fw_env.h" @@ -58,6 +61,7 @@ struct envdev_s { ulong erase_size; /* device erase size */ ulong env_sectors; /* number of environment sectors */ uint8_t mtd_type; /* type of the MTD device */ + int is_ubi; /* set if we use UBI volume */ }; static struct envdev_s envdevices[2] = @@ -76,6 +80,7 @@ static int dev_current; #define DEVESIZE(i) envdevices[(i)].erase_size #define ENVSECTORS(i) envdevices[(i)].env_sectors #define DEVTYPE(i) envdevices[(i)].mtd_type +#define IS_UBI(i) envdevices[(i)].is_ubi #define CUR_ENVSIZE ENVSIZE(dev_current) @@ -120,6 +125,228 @@ static unsigned char obsolete_flag = 0; #define DEFAULT_ENV_INSTANCE_STATIC #include <env_default.h> +#define UBI_DEV_START "/dev/ubi" +#define UBI_SYSFS "/sys/class/ubi" +#define UBI_VOL_NAME_PATT "ubi%d_%d" + +static int is_ubi_devname(const char *devname) +{ + return !strncmp(devname, UBI_DEV_START, sizeof(UBI_DEV_START) - 1); +} + +static int ubi_check_volume_sysfs_name(const char *volume_sysfs_name, + const char *volname) +{ + char path[256]; + FILE *file; + char *name; + int ret; + + strcpy(path, UBI_SYSFS "/"); + strcat(path, volume_sysfs_name); + strcat(path, "/name"); + + file = fopen(path, "r"); + if (!file) + return -1; + + ret = fscanf(file, "%ms", &name); + fclose(file); + if (ret <= 0 || !name) { + fprintf(stderr, + "Failed to read from file %s, ret = %d, name = %s\n", + path, ret, name); + return -1; + } + + if (!strcmp(name, volname)) { + free(name); + return 0; + } + free(name); + + return -1; +} + +static int ubi_get_volnum_by_name(int devnum, const char *volname) +{ + DIR *sysfs_ubi; + struct dirent *dirent; + int ret; + int tmp_devnum; + int volnum; + + sysfs_ubi = opendir(UBI_SYSFS); + if (!sysfs_ubi) + return -1; + +#ifdef DEBUG + fprintf(stderr, "Looking for volume name \"%s\"\n", volname); +#endif + + while (1) { + dirent = readdir(sysfs_ubi); + if (!dirent) + return -1; + + ret = sscanf(dirent->d_name, UBI_VOL_NAME_PATT, + &tmp_devnum, &volnum); + if (ret == 2 && devnum == tmp_devnum) { + if (ubi_check_volume_sysfs_name(dirent->d_name, + volname) == 0) + return volnum; + } + } + + return -1; +} + +static int ubi_get_devnum_by_devname(const char *devname) +{ + int devnum; + int ret; + + ret = sscanf(devname + sizeof(UBI_DEV_START) - 1, "%d", &devnum); + if (ret != 1) + return -1; + + return devnum; +} + +static const char *ubi_get_volume_devname(const char *devname, + const char *volname) +{ + char *volume_devname; + int volnum; + int devnum; + int ret; + + devnum = ubi_get_devnum_by_devname(devname); + if (devnum < 0) + return NULL; + + volnum = ubi_get_volnum_by_name(devnum, volname); + if (volnum < 0) + return NULL; + + ret = asprintf(&volume_devname, "%s_%d", devname, volnum); + if (ret < 0) + return NULL; + +#ifdef DEBUG + fprintf(stderr, "Found ubi volume \"%s:%s\" -> %s\n", + devname, volname, volume_devname); +#endif + + return volume_devname; +} + +static void ubi_check_dev(unsigned int dev_id) +{ + char *devname = (char *)DEVNAME(dev_id); + char *pname; + const char *volname = NULL; + const char *volume_devname; + + if (!is_ubi_devname(DEVNAME(dev_id))) + return; + + IS_UBI(dev_id) = 1; + + for (pname = devname; *pname != '\0'; pname++) { + if (*pname == ':') { + *pname = '\0'; + volname = pname + 1; + break; + } + } + + if (volname) { + /* Let's find real volume device name */ + volume_devname = ubi_get_volume_devname(devname, volname); + if (!volume_devname) { + fprintf(stderr, "Didn't found ubi volume \"%s\"\n", + volname); + return; + } + + free(devname); + DEVNAME(dev_id) = volume_devname; + } +} + +static int ubi_update_start(int fd, int64_t bytes) +{ + if (ioctl(fd, UBI_IOCVOLUP, &bytes)) + return -1; + return 0; +} + +static int ubi_read(int fd, void *buf, size_t count) +{ + ssize_t ret; + + while (count > 0) { + ret = read(fd, buf, count); + if (ret > 0) { + count -= ret; + buf += ret; + + continue; + } + + if (ret == 0) { + /* + * Happens in case of too short volume data size. If we + * return error status we will fail it will be treated + * as UBI device error. + * + * Leave catching this error to CRC check. + */ + fprintf(stderr, "Warning: end of data on ubi volume\n"); + return 0; + } else if (errno == EBADF) { + /* + * Happens in case of corrupted volume. The same as + * above, we cannot return error now, as we will still + * be able to successfully write environment later. + */ + fprintf(stderr, "Warning: corrupted volume?\n"); + return 0; + } else if (errno == EINTR) { + continue; + } + + fprintf(stderr, "Cannot read %u bytes from ubi volume, %s\n", + (unsigned int)count, strerror(errno)); + return -1; + } + + return 0; +} + +static int ubi_write(int fd, const void *buf, size_t count) +{ + ssize_t ret; + + while (count > 0) { + ret = write(fd, buf, count); + if (ret <= 0) { + if (ret < 0 && errno == EINTR) + continue; + + fprintf(stderr, "Cannot write %u bytes to ubi volume\n", + (unsigned int)count); + return -1; + } + + count -= ret; + buf += ret; + } + + return 0; +} + static int flash_io (int mode); static int parse_config(struct env_opts *opts); @@ -960,6 +1187,12 @@ static int flash_write (int fd_current, int fd_target, int dev_target) DEVOFFSET (dev_target), DEVNAME (dev_target)); #endif + if (IS_UBI(dev_target)) { + if (ubi_update_start(fd_target, CUR_ENVSIZE) < 0) + return 0; + return ubi_write(fd_target, environment.image, CUR_ENVSIZE); + } + rc = flash_write_buf(dev_target, fd_target, environment.image, CUR_ENVSIZE); if (rc < 0) @@ -984,6 +1217,12 @@ static int flash_read (int fd) { int rc; + if (IS_UBI(dev_current)) { + DEVTYPE(dev_current) = MTD_ABSENT; + + return ubi_read(fd, environment.image, CUR_ENVSIZE); + } + rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE, DEVOFFSET(dev_current)); if (rc != CUR_ENVSIZE) @@ -1165,7 +1404,8 @@ int fw_env_open(struct env_opts *opts) DEVTYPE(!dev_current) == MTD_UBIVOLUME) { environment.flag_scheme = FLAG_INCREMENTAL; } else if (DEVTYPE(dev_current) == MTD_ABSENT && - DEVTYPE(!dev_current) == MTD_ABSENT) { + DEVTYPE(!dev_current) == MTD_ABSENT && + IS_UBI(dev_current) == IS_UBI(!dev_current)) { environment.flag_scheme = FLAG_INCREMENTAL; } else { fprintf (stderr, "Incompatible flash types!\n"); @@ -1271,8 +1511,12 @@ int fw_env_close(struct env_opts *opts) static int check_device_config(int dev) { struct stat st; + int32_t lnum = 0; int fd, rc = 0; + /* Fills in IS_UBI(), converts DEVNAME() with ubi volume name */ + ubi_check_dev(dev); + fd = open(DEVNAME(dev), O_RDONLY); if (fd < 0) { fprintf(stderr, @@ -1288,7 +1532,14 @@ static int check_device_config(int dev) goto err; } - if (S_ISCHR(st.st_mode)) { + if (IS_UBI(dev)) { + rc = ioctl(fd, UBI_IOCEBISMAP, &lnum); + if (rc < 0) { + fprintf(stderr, "Cannot get UBI information for %s\n", + DEVNAME(dev)); + goto err; + } + } else if (S_ISCHR(st.st_mode)) { struct mtd_info_user mtdinfo; rc = ioctl(fd, MEMGETINFO, &mtdinfo); if (rc < 0) { diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index 7916ebdb1f6..053895a2c07 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -28,3 +28,11 @@ # VFAT example #/boot/uboot.env 0x0000 0x4000 + +# UBI volume +#/dev/ubi0_0 0x0 0x1f000 0x1f000 +#/dev/ubi0_1 0x0 0x1f000 0x1f000 + +# UBI volume by name +#/dev/ubi0:env 0x0 0x1f000 0x1f000 +#/dev/ubi0:env-redund 0x0 0x1f000 0x1f000 diff --git a/tools/libfdt/fdt_wip.c b/tools/libfdt/fdt_wip.c new file mode 100644 index 00000000000..bad73ed9e76 --- /dev/null +++ b/tools/libfdt/fdt_wip.c @@ -0,0 +1,2 @@ +#include "fdt_host.h" +#include "../scripts/dtc/libfdt/fdt_wip.c" |