diff options
49 files changed, 1128 insertions, 1183 deletions
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt new file mode 100644 index 00000000000..cfc376bc977 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ethernet.txt @@ -0,0 +1,66 @@ +The following properties are common to the Ethernet controllers: + +NOTE: All 'phy*' properties documented below are Ethernet specific. For the +generic PHY 'phys' property, see +Documentation/devicetree/bindings/phy/phy-bindings.txt. + +- local-mac-address: array of 6 bytes, specifies the MAC address that was + assigned to the network device; +- mac-address: array of 6 bytes, specifies the MAC address that was last used by + the boot program; should be used in cases where the MAC address assigned to + the device by the boot program is different from the "local-mac-address" + property; +- nvmem-cells: phandle, reference to an nvmem node for the MAC address; +- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used; +- max-speed: number, specifies maximum speed in Mbit/s supported by the device; +- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than + the maximum frame size (there's contradiction in the Devicetree + Specification). +- phy-mode: string, operation mode of the PHY interface. This is now a de-facto + standard property; supported values are: + * "internal" + * "mii" + * "gmii" + * "sgmii" + * "qsgmii" + * "tbi" + * "rev-mii" + * "rmii" + * "rgmii" (RX and TX delays are added by the MAC when required) + * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the + MAC should not add the RX or TX delays in this case) + * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC + should not add an RX delay in this case) + * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC + should not add an TX delay in this case) + * "rtbi" + * "smii" + * "xgmii" + * "trgmii" + * "2000base-x", + * "2500base-x", + * "rxaui" + * "xaui" + * "10gbase-kr" (10GBASE-KR, XFI, SFI) +- phy-connection-type: the same as "phy-mode" property but described in the + Devicetree Specification; +- phy-handle: phandle, specifies a reference to a node representing a PHY + device; this property is described in the Devicetree Specification and so + preferred; +- phy: the same as "phy-handle" property, not recommended for new bindings. +- phy-device: the same as "phy-handle" property, not recommended for new + bindings. +- rx-fifo-depth: the size of the controller's receive fifo in bytes. This + is used for components that can have configurable receive fifo sizes, + and is useful for determining certain configuration settings such as + flow control thresholds. +- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This + is used for components that can have configurable fifo sizes. +- managed: string, specifies the PHY management type. Supported values are: + "auto", "in-band-status". "auto" is the default, it usess MDIO for + management if fixed-link is not specified. + +Child nodes of the Ethernet controller are typically the individual PHY devices +connected via the MDIO bus (sometimes the MDIO bus controller is separate). +They are described in the phy.txt file in this same directory. +For non-MDIO PHY management see fixed-link.txt. diff --git a/arch/arm/dts/armada-388-helios4-u-boot.dtsi b/arch/arm/dts/armada-388-helios4-u-boot.dtsi index 4b20610d831..f0da9f42de2 100644 --- a/arch/arm/dts/armada-388-helios4-u-boot.dtsi +++ b/arch/arm/dts/armada-388-helios4-u-boot.dtsi @@ -20,3 +20,7 @@ status = "okay"; u-boot,dm-spl; }; + +&sdhci { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/dts/imx6-logicpd-baseboard.dtsi index 303c09334ba..c40a7af6ebe 100644 --- a/arch/arm/dts/imx6-logicpd-baseboard.dtsi +++ b/arch/arm/dts/imx6-logicpd-baseboard.dtsi @@ -1,45 +1,6 @@ -/* - * Copyright 2018 Logic PD, Inc. - * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. / { keyboard { @@ -68,6 +29,7 @@ debounce-interval = <10>; wakeup-source; }; + btn3 { gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; label = "btn3"; @@ -81,7 +43,7 @@ leds { compatible = "gpio-leds"; - gen_led0 { + gen-led0 { label = "led0"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led0>; @@ -89,25 +51,27 @@ linux,default-trigger = "cpu0"; }; - gen_led1 { + gen-led1 { label = "led1"; gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; }; - gen_led2 { + gen-led2 { label = "led2"; gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - gen_led3 { + gen-led3 { label = "led3"; gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; }; - reg_usb_otg_vbus: regulator-otg-vbus@0 { + reg_usb_otg_vbus: regulator-otg-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg>; compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; @@ -116,14 +80,19 @@ enable-active-high; }; - reg_usb_h1_vbus: regulator-usbh1vbus@1 { + reg_usb_h1_vbus: regulator-usb-h1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; compatible = "regulator-fixed"; regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; }; - reg_3v3: regulator-3v3@2 { + reg_3v3: regulator-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_3v3>; compatible = "regulator-fixed"; @@ -131,13 +100,14 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; enable-active-high; regulator-always-on; }; - reg_enet: regulator-ethernet@3 { + reg_enet: regulator-ethernet { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_pwr>; + pinctrl-0 = <&pinctrl_reg_enet>; compatible = "regulator-fixed"; regulator-name = "ethernet-supply"; regulator-min-microvolt = <3300000>; @@ -148,7 +118,7 @@ vin-supply = <&sw4_reg>; }; - reg_audio: regulator-audio@4 { + reg_audio: regulator-audio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_audio>; compatible = "regulator-fixed"; @@ -157,11 +127,10 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; vin-supply = <®_3v3>; }; - reg_hdmi: regulator-hdmi@5 { + reg_hdmi: regulator-hdmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_hdmi>; compatible = "regulator-fixed"; @@ -173,7 +142,7 @@ vin-supply = <®_3v3>; }; - reg_uart3: regulator-uart3@6 { + reg_uart3: regulator-uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_uart3>; compatible = "regulator-fixed"; @@ -184,7 +153,7 @@ vin-supply = <®_3v3>; }; - reg_1v8: regulator-1v8@7 { + reg_1v8: regulator-1v8 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_1v8>; compatible = "regulator-fixed"; @@ -195,21 +164,21 @@ vin-supply = <®_3v3>; }; - reg_pcie: regulator@8 { + reg_pcie: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; + pinctrl-0 = <&pinctrl_reg_pcie>; + regulator-name = "mpcie_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; enable-active-high; }; - mipi_pwr: regulator@9 { + reg_mipi: regulator-mipi { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi_pwr>; + pinctrl-0 = <&pinctrl_reg_mipi>; regulator-name = "mipi_pwr_en"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -221,7 +190,7 @@ compatible = "fsl,imx-audio-wm8962"; model = "wm8962-audio"; ssi-controller = <&ssi2>; - audio-codec = <&codec>; + audio-codec = <&wm8962>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", @@ -246,34 +215,10 @@ status = "disabled"; }; -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-reset-duration = <10>; phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; phy-supply = <®_enet>; @@ -282,23 +227,13 @@ status = "okay"; }; -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; - &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clock-frequency = <400000>; status = "okay"; - codec: wm8962@1a { + wm8962: audio-codec@1a { compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -330,9 +265,9 @@ reg = <0x10>; clocks = <&clks IMX6QDL_CLK_CKO>; clock-names = "xclk"; - DOVDD-supply = <&mipi_pwr>; - AVDD-supply = <&mipi_pwr>; - DVDD-supply = <&mipi_pwr>; + DOVDD-supply = <®_mipi>; + AVDD-supply = <®_mipi>; + DVDD-supply = <®_mipi>; reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; @@ -361,6 +296,11 @@ }; }; +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; + &mipi_csi { status = "okay"; @@ -379,17 +319,52 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - status = "okay"; vpcie-supply = <®_pcie>; - /* fsl,max-link-speed = <2>; */ + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; }; &ssi2 { status = "okay"; }; -&iomuxc { +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_3v3>; + no-1-8-v; + keep-power-in-suspend; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 @@ -399,21 +374,49 @@ >; }; - pinctrl_i2c1: i2c1 { + pinctrl_ecspi1: ecspi1grp { fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 >; }; - pinctrl_enet_pwr: enet_pwr { + pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ >; }; - pinctrl_mipi_pwr: pwr_mipi { - fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_led0: led0grp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; }; pinctrl_ov5640: ov5640grp { @@ -423,174 +426,132 @@ >; }; - pinctrl_reg_hdmi: reg_hdmi { + pinctrl_pcf8574: pcf8575grp { fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 >; }; - pinctrl_uart3: uart3grp { + pinctrl_pcie: pciegrp { fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 >; }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 - MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0 - >; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; }; - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 - >; + pinctrl_reg_1v8: reg1v8grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; }; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 - >; - }; - - pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; + pinctrl_reg_3v3: reg3v3grp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 + >; }; - pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { + pinctrl_reg_audio: reg-audiogrp { fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 >; }; - pinctrl_enet: enetgrp { + pinctrl_reg_enet: reg-enetgrp { fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 >; }; - pinctrl_reg_audio: audio-reg { + pinctrl_reg_hdmi: reg-hdmigrp { fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 >; }; - pinctrl_pcie: pcie { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; + pinctrl_reg_mipi: reg-mipigrp { + fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>; }; - pinctrl_pcie_reg: pciereggrp { + pinctrl_reg_pcie: reg-pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 >; }; - pinctrl_pcf8574: pcf8575-pins { + pinctrl_reg_uart3: reguart3grp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_reg_usb_h1_vbus: usbh1grp { fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 >; }; - pinctrl_lcd: lcdgrp { + pinctrl_reg_usb_otg: reg-usb-otggrp { fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */ - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */ - MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */ - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 >; }; - pinctrl_pwm3: pwm3grp { + pinctrl_uart3: uart3grp { fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; }; - pinctrl_reg_uart3: uart3reg { + pinctrl_usbotg: usbotggrp { fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 >; }; - pinctrl_reg_3v3: reg-3v3 { + pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 >; }; - pinctrl_reg_1v8: reg-1v8 { + pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 >; }; - pinctrl_led0: led0 { + pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 >; }; + }; diff --git a/arch/arm/dts/imx6-logicpd-som.dtsi b/arch/arm/dts/imx6-logicpd-som.dtsi index 3fc50babf09..7ceae357324 100644 --- a/arch/arm/dts/imx6-logicpd-som.dtsi +++ b/arch/arm/dts/imx6-logicpd-som.dtsi @@ -1,16 +1,6 @@ -/* - * Copyright 2018 Logic PD - * This file is adapted from imx6qdl-sabresd.dtsi. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -20,7 +10,8 @@ stdout-path = &uart1; }; - memory { + memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; @@ -35,17 +26,6 @@ }; }; -/* Reroute power feeding the CPU to come from the external PMIC */ -®_arm -{ - vin-supply = <&sw1a_reg>; -}; - -®_soc -{ - vin-supply = <&sw1c_reg>; -}; - &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; @@ -56,8 +36,8 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; nand-on-flash-bbt; + status = "okay"; }; &i2c3 { @@ -66,7 +46,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - pmic: pfuze100@08 { + pfuze100: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -94,20 +74,19 @@ regulator-max-microvolt = <3300000>; regulator-name = "gen_3v3"; regulator-boot-on; - /* regulator-always-on; */ }; sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-name = "sw3a_vddr"; regulator-boot-on; regulator-always-on; }; sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-name = "sw3b_vddr"; regulator-boot-on; regulator-always-on; @@ -152,8 +131,8 @@ vgen3_reg: vgen3 { regulator-name = "gen_vadj_0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; vgen4_reg: vgen4 { @@ -164,8 +143,8 @@ }; vgen5_reg: vgen5 { - regulator-name = "gen_adj_1"; - regulator-min-microvolt = <3300000>; + regulator-name = "gen_vadj_1"; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -185,44 +164,75 @@ }; }; - temp_sense0: tmp102@4a { + temperature-sensor@49 { compatible = "ti,tmp102"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tempsense>; + reg = <0x49>; interrupt-parent = <&gpio6>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; #thermal-sensor-cells = <1>; }; - temp_sense1: tmp102@49 { + temperature-sensor@4a { compatible = "ti,tmp102"; - reg = <0x49>; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; interrupt-parent = <&gpio6>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; #thermal-sensor-cells = <1>; }; - mfg_eeprom: at24@51 { + eeprom@51 { compatible = "atmel,24c64"; pagesize = <32>; - read-only; + read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x51>; }; - user_eeprom: at24@52 { + eeprom@52 { compatible = "atmel,24c64"; pagesize = <32>; reg = <0x52>; }; }; +/* Reroute power feeding the CPU to come from the external PMIC */ +®_arm +{ + vin-supply = <&sw1a_reg>; +}; + +®_soc +{ + vin-supply = <&sw1c_reg>; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - pinctrl_hog: hoggrp { + pinctrl_gpmi_nand: gpmi-nandgrp { fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < /* Enable ARM Debugger */ MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 @@ -246,30 +256,16 @@ >; }; - pinctrl_gpmi_nand: gpminandgrp { + pinctrl_i2c3: i2c3grp { fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 >; }; - pinctrl_i2c3: i2c3grp { + pinctrl_tempsense: tempsensegrp { fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 >; }; @@ -282,7 +278,7 @@ pinctrl_uart2: uart2grp { fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 @@ -313,12 +309,6 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ >; }; - - pinctrl_tempsense: tempsensegrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */ - >; - }; }; &snvs_poweroff { @@ -334,8 +324,9 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; uart-has-rtscts; + status = "okay"; + bluetooth { compatible = "ti,wl1837-st"; enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; @@ -347,9 +338,9 @@ pinctrl-0 = <&pinctrl_usdhc1>; non-removable; keep-power-in-suspend; - enable-sdio-wakeup; - status = "okay"; + wakeup-source; vmmc-supply = <&sw2_reg>; + status = "okay"; }; &usdhc3 { @@ -360,9 +351,10 @@ keep-power-in-suspend; wakeup-source; vmmc-supply = <®_wl18xx_vmmc>; - status = "okay"; #address-cells = <1>; #size-cells = <0>; + status = "okay"; + wlcore: wlcore@2 { compatible = "ti,wl1837"; reg = <2>; diff --git a/arch/arm/dts/imx6q-logicpd.dts b/arch/arm/dts/imx6q-logicpd.dts index dcea784477b..45eb0b7f75f 100644 --- a/arch/arm/dts/imx6q-logicpd.dts +++ b/arch/arm/dts/imx6q-logicpd.dts @@ -1,45 +1,6 @@ -/* - * Copyright 2018 Logic PD, Inc. - * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. /dts-v1/; #include "imx6q.dtsi" @@ -47,10 +8,10 @@ #include "imx6-logicpd-baseboard.dtsi" / { - model = "Logic PD i.MX6QD SOM-M3 (HDMI)"; + model = "Logic PD i.MX6QD SOM-M3"; compatible = "fsl,imx6q"; - backlight: backlight_lvds { + backlight: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm3 0 20000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -58,6 +19,16 @@ power-supply = <®_lcd>; }; + panel-lvds0 { + compatible = "okaya,rs800480t-7x0gp"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + reg_lcd: regulator-lcd { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd_reg>; @@ -72,7 +43,7 @@ startup-delay-us = <500000>; }; - lcd_reset: lcd_reset { + reg_lcd_reset: regulator-lcd-reset { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd_reset>; compatible = "regulator-fixed"; @@ -84,17 +55,17 @@ regulator-always-on; vin-supply = <®_lcd>; }; +}; - panel-lvds0 { - compatible = "ampire,am800480b3tmqw"; - backlight = <&backlight>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; }; &hdmi { @@ -102,22 +73,6 @@ status = "okay"; }; -&i2c1 { - ili_touch: ilitouch@26 { - compatible = "ili,ili2117a"; - reg = <0x26>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>; - ili2117a,poll-period = <10>; - ili2117a,max-touch = <2>; - }; -}; - -®_hdmi { - regulator-always-on; -}; - &ldb { status = "okay"; @@ -128,7 +83,6 @@ port@4 { reg = <4>; - lvds0_out: endpoint { remote-endpoint = <&panel_in_lvds0>; }; @@ -137,23 +91,12 @@ }; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; -}; - &pwm3 { status = "okay"; }; -&usdhc2 { - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +®_hdmi { + regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */ }; &iomuxc { @@ -165,7 +108,7 @@ pinctrl_lcd_reset: lcdreset { fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ >; }; @@ -175,4 +118,3 @@ >; }; }; - diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 61e84e51299..adc50922c8f 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -134,7 +134,6 @@ source "board/davinci/da8xxevm/Kconfig" source "board/lego/ev3/Kconfig" config SPL_LDSCRIPT - default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390 default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 6887fe05dd8..ed882740720 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -18,7 +18,3 @@ obj-$(CONFIG_SPL_FRAMEWORK) += spl.o obj-$(CONFIG_SOC_DM365) += dm365_lowlevel.o obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o endif - -ifndef CONFIG_SKIP_LOWLEVEL_INIT -obj-y += lowlevel_init.o -endif diff --git a/arch/arm/mach-davinci/lowlevel_init.S b/arch/arm/mach-davinci/lowlevel_init.S deleted file mode 100644 index b82dafad2bb..00000000000 --- a/arch/arm/mach-davinci/lowlevel_init.S +++ /dev/null @@ -1,692 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Low-level board setup code for TI DaVinci SoC based boards. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Partially based on TI sources, original copyrights follow: - */ - -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 - * - * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005 - * - * Modified for DV-EVM board by Swaminathan S, Nov 2005 - */ - -#include <config.h> - -#define MDSTAT_STATE 0x3f - -.globl lowlevel_init -lowlevel_init: -#ifdef CONFIG_SOC_DM644X - - /*-------------------------------------------------------* - * Mask all IRQs by setting all bits in the EINT default * - *-------------------------------------------------------*/ - mov r1, $0 - ldr r0, =EINT_ENABLE0 - str r1, [r0] - ldr r0, =EINT_ENABLE1 - str r1, [r0] - - /*------------------------------------------------------* - * Put the GEM in reset * - *------------------------------------------------------*/ - - /* Put the GEM in reset */ - ldr r8, PSC_GEM_FLAG_CLEAR - ldr r6, MDCTL_GEM - ldr r7, [r6] - and r7, r7, r8 - str r7, [r6] - - /* Enable the Power Domain Transition Command */ - ldr r6, PTCMD - ldr r7, [r6] - orr r7, r7, $0x02 - str r7, [r6] - - /* Check for Transition Complete(PTSTAT) */ -checkStatClkStopGem: - ldr r6, PTSTAT - ldr r7, [r6] - ands r7, r7, $0x02 - bne checkStatClkStopGem - - /* Check for GEM Reset Completion */ -checkGemStatClkStop: - ldr r6, MDSTAT_GEM - ldr r7, [r6] - ands r7, r7, $0x100 - bne checkGemStatClkStop - - /* Do this for enabling a WDT initiated reset this is a workaround - for a chip bug. Not required under normal situations */ - ldr r6, P1394 - mov r10, $0 - str r10, [r6] - - /*------------------------------------------------------* - * Enable L1 & L2 Memories in Fast mode * - *------------------------------------------------------*/ - ldr r6, DFT_ENABLE - mov r10, $0x01 - str r10, [r6] - - ldr r6, MMARG_BRF0 - ldr r10, MMARG_BRF0_VAL - str r10, [r6] - - ldr r6, DFT_ENABLE - mov r10, $0 - str r10, [r6] - - /*------------------------------------------------------* - * DDR2 PLL Initialization * - *------------------------------------------------------*/ - - /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ - mov r10, $0 - ldr r6, PLL2_CTL - ldr r7, PLL_CLKSRC_MASK - ldr r8, [r6] - and r8, r8, r7 - mov r9, r10, lsl $8 - orr r8, r8, r9 - str r8, [r6] - - /* Select the PLLEN source */ - ldr r7, PLL_ENSRC_MASK - and r8, r8, r7 - str r8, [r6] - - /* Bypass the PLL */ - ldr r7, PLL_BYPASS_MASK - and r8, r8, r7 - str r8, [r6] - - /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ - mov r10, $0x20 -WaitPPL2Loop: - subs r10, r10, $1 - bne WaitPPL2Loop - - /* Reset the PLL */ - ldr r7, PLL_RESET_MASK - and r8, r8, r7 - str r8, [r6] - - /* Power up the PLL */ - ldr r7, PLL_PWRUP_MASK - and r8, r8, r7 - str r8, [r6] - - /* Enable the PLL from Disable Mode */ - ldr r7, PLL_DISABLE_ENABLE_MASK - and r8, r8, r7 - str r8, [r6] - - /* Program the PLL Multiplier */ - ldr r6, PLL2_PLLM - mov r2, $0x17 /* 162 MHz */ - str r2, [r6] - - /* Program the PLL2 Divisor Value */ - ldr r6, PLL2_DIV2 - mov r3, $0x01 - str r3, [r6] - - /* Program the PLL2 Divisor Value */ - ldr r6, PLL2_DIV1 - mov r4, $0x0b /* 54 MHz */ - str r4, [r6] - - /* PLL2 DIV2 MMR */ - ldr r8, PLL2_DIV_MASK - ldr r6, PLL2_DIV2 - ldr r9, [r6] - and r8, r8, r9 - mov r9, $0x01 - mov r9, r9, lsl $15 - orr r8, r8, r9 - str r8, [r6] - - /* Program the GOSET bit to take new divider values */ - ldr r6, PLL2_PLLCMD - ldr r7, [r6] - orr r7, r7, $0x01 - str r7, [r6] - - /* Wait for Done */ - ldr r6, PLL2_PLLSTAT -doneLoop_0: - ldr r7, [r6] - ands r7, r7, $0x01 - bne doneLoop_0 - - /* PLL2 DIV1 MMR */ - ldr r8, PLL2_DIV_MASK - ldr r6, PLL2_DIV1 - ldr r9, [r6] - and r8, r8, r9 - mov r9, $0x01 - mov r9, r9, lsl $15 - orr r8, r8, r9 - str r8, [r6] - - /* Program the GOSET bit to take new divider values */ - ldr r6, PLL2_PLLCMD - ldr r7, [r6] - orr r7, r7, $0x01 - str r7, [r6] - - /* Wait for Done */ - ldr r6, PLL2_PLLSTAT -doneLoop: - ldr r7, [r6] - ands r7, r7, $0x01 - bne doneLoop - - /* Wait for PLL to Reset Properly */ - mov r10, $0x218 -ResetPPL2Loop: - subs r10, r10, $1 - bne ResetPPL2Loop - - /* Bring PLL out of Reset */ - ldr r6, PLL2_CTL - ldr r8, [r6] - orr r8, r8, $0x08 - str r8, [r6] - - /* Wait for PLL to Lock */ - ldr r10, PLL_LOCK_COUNT -PLL2Lock: - subs r10, r10, $1 - bne PLL2Lock - - /* Enable the PLL */ - ldr r6, PLL2_CTL - ldr r8, [r6] - orr r8, r8, $0x01 - str r8, [r6] - - /*------------------------------------------------------* - * Issue Soft Reset to DDR Module * - *------------------------------------------------------*/ - - /* Shut down the DDR2 LPSC Module */ - ldr r8, PSC_FLAG_CLEAR - ldr r6, MDCTL_DDR2 - ldr r7, [r6] - and r7, r7, r8 - orr r7, r7, $0x03 - str r7, [r6] - - /* Enable the Power Domain Transition Command */ - ldr r6, PTCMD - ldr r7, [r6] - orr r7, r7, $0x01 - str r7, [r6] - - /* Check for Transition Complete(PTSTAT) */ -checkStatClkStop: - ldr r6, PTSTAT - ldr r7, [r6] - ands r7, r7, $0x01 - bne checkStatClkStop - - /* Check for DDR2 Controller Enable Completion */ -checkDDRStatClkStop: - ldr r6, MDSTAT_DDR2 - ldr r7, [r6] - and r7, r7, $MDSTAT_STATE - cmp r7, $0x03 - bne checkDDRStatClkStop - - /*------------------------------------------------------* - * Program DDR2 MMRs for 162MHz Setting * - *------------------------------------------------------*/ - - /* Program PHY Control Register */ - ldr r6, DDRCTL - ldr r7, DDRCTL_VAL - str r7, [r6] - - /* Program SDRAM Bank Config Register */ - ldr r6, SDCFG - ldr r7, SDCFG_VAL - str r7, [r6] - - /* Program SDRAM TIM-0 Config Register */ - ldr r6, SDTIM0 - ldr r7, SDTIM0_VAL_162MHz - str r7, [r6] - - /* Program SDRAM TIM-1 Config Register */ - ldr r6, SDTIM1 - ldr r7, SDTIM1_VAL_162MHz - str r7, [r6] - - /* Program the SDRAM Bank Config Control Register */ - ldr r10, MASK_VAL - ldr r8, SDCFG - ldr r9, SDCFG_VAL - and r9, r9, r10 - str r9, [r8] - - /* Program SDRAM SDREF Config Register */ - ldr r6, SDREF - ldr r7, SDREF_VAL - str r7, [r6] - - /*------------------------------------------------------* - * Issue Soft Reset to DDR Module * - *------------------------------------------------------*/ - - /* Issue a Dummy DDR2 read/write */ - ldr r8, DDR2_START_ADDR - ldr r7, DUMMY_VAL - str r7, [r8] - ldr r7, [r8] - - /* Shut down the DDR2 LPSC Module */ - ldr r8, PSC_FLAG_CLEAR - ldr r6, MDCTL_DDR2 - ldr r7, [r6] - and r7, r7, r8 - orr r7, r7, $0x01 - str r7, [r6] - - /* Enable the Power Domain Transition Command */ - ldr r6, PTCMD - ldr r7, [r6] - orr r7, r7, $0x01 - str r7, [r6] - - /* Check for Transition Complete(PTSTAT) */ -checkStatClkStop2: - ldr r6, PTSTAT - ldr r7, [r6] - ands r7, r7, $0x01 - bne checkStatClkStop2 - - /* Check for DDR2 Controller Enable Completion */ -checkDDRStatClkStop2: - ldr r6, MDSTAT_DDR2 - ldr r7, [r6] - and r7, r7, $MDSTAT_STATE - cmp r7, $0x01 - bne checkDDRStatClkStop2 - - /*------------------------------------------------------* - * Turn DDR2 Controller Clocks On * - *------------------------------------------------------*/ - - /* Enable the DDR2 LPSC Module */ - ldr r6, MDCTL_DDR2 - ldr r7, [r6] - orr r7, r7, $0x03 - str r7, [r6] - - /* Enable the Power Domain Transition Command */ - ldr r6, PTCMD - ldr r7, [r6] - orr r7, r7, $0x01 - str r7, [r6] - - /* Check for Transition Complete(PTSTAT) */ -checkStatClkEn2: - ldr r6, PTSTAT - ldr r7, [r6] - ands r7, r7, $0x01 - bne checkStatClkEn2 - - /* Check for DDR2 Controller Enable Completion */ -checkDDRStatClkEn2: - ldr r6, MDSTAT_DDR2 - ldr r7, [r6] - and r7, r7, $MDSTAT_STATE - cmp r7, $0x03 - bne checkDDRStatClkEn2 - - /* DDR Writes and Reads */ - ldr r6, CFGTEST - mov r3, $0x01 - str r3, [r6] - - /*------------------------------------------------------* - * System PLL Initialization * - *------------------------------------------------------*/ - - /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ - mov r2, $0 - ldr r6, PLL1_CTL - ldr r7, PLL_CLKSRC_MASK - ldr r8, [r6] - and r8, r8, r7 - mov r9, r2, lsl $8 - orr r8, r8, r9 - str r8, [r6] - - /* Select the PLLEN source */ - ldr r7, PLL_ENSRC_MASK - and r8, r8, r7 - str r8, [r6] - - /* Bypass the PLL */ - ldr r7, PLL_BYPASS_MASK - and r8, r8, r7 - str r8, [r6] - - /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ - mov r10, $0x20 - -WaitLoop: - subs r10, r10, $1 - bne WaitLoop - - /* Reset the PLL */ - ldr r7, PLL_RESET_MASK - and r8, r8, r7 - str r8, [r6] - - /* Disable the PLL */ - orr r8, r8, $0x10 - str r8, [r6] - - /* Power up the PLL */ - ldr r7, PLL_PWRUP_MASK - and r8, r8, r7 - str r8, [r6] - - /* Enable the PLL from Disable Mode */ - ldr r7, PLL_DISABLE_ENABLE_MASK - and r8, r8, r7 - str r8, [r6] - - /* Program the PLL Multiplier */ - ldr r6, PLL1_PLLM - mov r3, $0x15 /* For 594MHz */ - str r3, [r6] - - /* Wait for PLL to Reset Properly */ - mov r10, $0xff - -ResetLoop: - subs r10, r10, $1 - bne ResetLoop - - /* Bring PLL out of Reset */ - ldr r6, PLL1_CTL - orr r8, r8, $0x08 - str r8, [r6] - - /* Wait for PLL to Lock */ - ldr r10, PLL_LOCK_COUNT - -PLL1Lock: - subs r10, r10, $1 - bne PLL1Lock - - /* Enable the PLL */ - orr r8, r8, $0x01 - str r8, [r6] - - nop - nop - nop - nop - - /*------------------------------------------------------* - * AEMIF configuration for NOR Flash (double check) * - *------------------------------------------------------*/ - ldr r0, _PINMUX0 - ldr r1, _DEV_SETTING - str r1, [r0] - - ldr r0, WAITCFG - ldr r1, WAITCFG_VAL - ldr r2, [r0] - orr r2, r2, r1 - str r2, [r0] - - ldr r0, ACFG3 - ldr r1, ACFG3_VAL - ldr r2, [r0] - and r1, r2, r1 - str r1, [r0] - - ldr r0, ACFG4 - ldr r1, ACFG4_VAL - ldr r2, [r0] - and r1, r2, r1 - str r1, [r0] - - ldr r0, ACFG5 - ldr r1, ACFG5_VAL - ldr r2, [r0] - and r1, r2, r1 - str r1, [r0] - - /*--------------------------------------* - * VTP manual Calibration * - *--------------------------------------*/ - ldr r0, VTPIOCR - ldr r1, VTP_MMR0 - str r1, [r0] - - ldr r0, VTPIOCR - ldr r1, VTP_MMR1 - str r1, [r0] - - /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ - ldr r10, VTP_LOCK_COUNT -VTPLock: - subs r10, r10, $1 - bne VTPLock - - ldr r6, DFT_ENABLE - mov r10, $0x01 - str r10, [r6] - - ldr r6, DDRVTPR - ldr r7, [r6] - mov r8, r7, LSL #32-10 - mov r8, r8, LSR #32-10 /* grab low 10 bits */ - ldr r7, VTP_RECAL - orr r8, r7, r8 - ldr r7, VTP_EN - orr r8, r7, r8 - str r8, [r0] - - - /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ - ldr r10, VTP_LOCK_COUNT -VTP1Lock: - subs r10, r10, $1 - bne VTP1Lock - - ldr r1, [r0] - ldr r2, VTP_MASK - and r2, r1, r2 - str r2, [r0] - - ldr r6, DFT_ENABLE - mov r10, $0 - str r10, [r6] - - /* - * Call board-specific lowlevel init. - * That MUST be present and THAT returns - * back to arch calling code with "mov pc, lr." - */ - b dv_board_init - -.ltorg - -_PINMUX0: - .word 0x01c40000 /* Device Configuration Registers */ -_PINMUX1: - .word 0x01c40004 /* Device Configuration Registers */ - -_DEV_SETTING: - .word 0x00000c1f - -WAITCFG: - .word 0x01e00004 -WAITCFG_VAL: - .word 0 -ACFG3: - .word 0x01e00014 -ACFG3_VAL: - .word 0x3ffffffd -ACFG4: - .word 0x01e00018 -ACFG4_VAL: - .word 0x3ffffffd -ACFG5: - .word 0x01e0001c -ACFG5_VAL: - .word 0x3ffffffd - -MDCTL_DDR2: - .word 0x01c41a34 -MDSTAT_DDR2: - .word 0x01c41834 - -PTCMD: - .word 0x01c41120 -PTSTAT: - .word 0x01c41128 - -EINT_ENABLE0: - .word 0x01c48018 -EINT_ENABLE1: - .word 0x01c4801c - -PSC_FLAG_CLEAR: - .word 0xffffffe0 -PSC_GEM_FLAG_CLEAR: - .word 0xfffffeff - -/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */ -DDRCTL: - .word 0x200000e4 -DDRCTL_VAL: - .word 0x50006405 -SDREF: - .word 0x2000000c -SDREF_VAL: - .word 0x000005c3 -SDCFG: - .word 0x20000008 -SDCFG_VAL: -#ifdef DDR_4BANKS - .word 0x00178622 -#elif defined DDR_8BANKS - .word 0x00178632 -#else -#error "Unknown DDR configuration!!!" -#endif -SDTIM0: - .word 0x20000010 -SDTIM0_VAL_162MHz: - .word 0x28923211 -SDTIM1: - .word 0x20000014 -SDTIM1_VAL_162MHz: - .word 0x0016c722 -VTPIOCR: - .word 0x200000f0 /* VTP IO Control register */ -DDRVTPR: - .word 0x01c42030 /* DDR VPTR MMR */ -VTP_MMR0: - .word 0x201f -VTP_MMR1: - .word 0xa01f -DFT_ENABLE: - .word 0x01c4004c -VTP_LOCK_COUNT: - .word 0x5b0 -VTP_MASK: - .word 0xffffdfff -VTP_RECAL: - .word 0x08000 -VTP_EN: - .word 0x02000 -CFGTEST: - .word 0x80010000 -MASK_VAL: - .word 0x00000fff - -/* GEM Power Up & LPSC Control Register */ -MDCTL_GEM: - .word 0x01c41a9c -MDSTAT_GEM: - .word 0x01c4189c - -/* For WDT reset chip bug */ -P1394: - .word 0x01c41a20 - -PLL_CLKSRC_MASK: - .word 0xfffffeff /* Mask the Clock Mode bit */ -PLL_ENSRC_MASK: - .word 0xffffffdf /* Select the PLLEN source */ -PLL_BYPASS_MASK: - .word 0xfffffffe /* Put the PLL in BYPASS */ -PLL_RESET_MASK: - .word 0xfffffff7 /* Put the PLL in Reset Mode */ -PLL_PWRUP_MASK: - .word 0xfffffffd /* PLL Power up Mask Bit */ -PLL_DISABLE_ENABLE_MASK: - .word 0xffffffef /* Enable the PLL from Disable */ -PLL_LOCK_COUNT: - .word 0x2000 - -/* PLL1-SYSTEM PLL MMRs */ -PLL1_CTL: - .word 0x01c40900 -PLL1_PLLM: - .word 0x01c40910 - -/* PLL2-SYSTEM PLL MMRs */ -PLL2_CTL: - .word 0x01c40d00 -PLL2_PLLM: - .word 0x01c40d10 -PLL2_DIV1: - .word 0x01c40d18 -PLL2_DIV2: - .word 0x01c40d1c -PLL2_PLLCMD: - .word 0x01c40d38 -PLL2_PLLSTAT: - .word 0x01c40d3c -PLL2_DIV_MASK: - .word 0xffff7fff - -MMARG_BRF0: - .word 0x01c42010 /* BRF margin mode 0 (R/W)*/ -MMARG_BRF0_VAL: - .word 0x00444400 - -DDR2_START_ADDR: - .word 0x80000000 -DUMMY_VAL: - .word 0xa55aa55a -#else /* CONFIG_SOC_DM644X */ - mov pc, lr -#endif diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 103639e3475..be3daa9bc02 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -31,9 +31,12 @@ void putc(char c) } #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ -void spl_board_init(void) +void board_init_f(ulong dummy) { arch_cpu_init(); + + spl_early_init(); + preloader_console_init(); } diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 2d25fc60a0e..658ef8c1f11 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -34,6 +34,8 @@ static void omap3_invalidate_l2_cache_secure(void); #endif #ifdef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(OF_CONTROL) +/* Manually initialize GPIO banks when OF_CONTROL doesn't */ static const struct omap_gpio_platdata omap34xx_gpio[] = { { 0, OMAP34XX_GPIO1_BASE }, { 1, OMAP34XX_GPIO2_BASE }, @@ -51,7 +53,7 @@ U_BOOT_DEVICES(omap34xx_gpios) = { { "gpio_omap", &omap34xx_gpio[4] }, { "gpio_omap", &omap34xx_gpio[5] }, }; - +#endif #else static const struct gpio_bank gpio_bank_34xx[6] = { diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0d04d91ad49..8cfc7d0faaa 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_AX25_AE350 bool "Support ax25-ae350" +config TARGET_MICROCHIP_ICICLE + bool "Support Microchip PolarFire-SoC Icicle Board" + config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" @@ -48,6 +51,7 @@ config SPL_SYS_DCACHE_OFF # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" +source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/fu540/Kconfig" # platform-specific options below diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c index 190f141091f..c8cc73ab141 100644 --- a/board/BuR/common/br_resetc.c +++ b/board/BuR/common/br_resetc.c @@ -64,6 +64,7 @@ static int resetc_init(void) return -1; } + resetc.is_psoc = 1; rc = dm_i2c_probe(i2cbus, RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev); if (rc) { diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 1bc26828bfa..a90b7a35383 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -62,7 +62,7 @@ static int get_mac_addr(u8 *addr) return -1; } - ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET) + 1, 7, addr); + ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr); if (ret) { printf("Error - unable to read MAC address from SPI flash.\n"); return -1; diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index 2c2f885d43e..fe1bf441014 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -353,7 +353,7 @@ int misc_init_r(void) return 0; } -#ifndef CONFIG_DM_MMC +#if !CONFIG_IS_ENABLED(DM_MMC) #ifdef CONFIG_MMC_DAVINCI static struct davinci_mmc mmc_sd0 = { .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 20ea6dc59b7..7f9a74dd48e 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -36,5 +36,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply OF_BOARD_SETUP imply SIFIVE_SERIAL imply SMP + imply PCI + imply DM_PCI + imply PCIE_ECAM_GENERIC + imply CMD_PCI + imply E1000 + imply NVME endif diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index 63b06517ac3..94e0d572e22 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -1,5 +1,5 @@ KM83XX BOARD -M: Holger Brunck <holger.brunck@keymile.com> +M: Holger Brunck <holger.brunck@ch.abb.com> S: Maintained F: board/keymile/km83xx/ F: include/configs/km8360.h diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS index 079c8036772..d156e8574bd 100644 --- a/board/keymile/km_arm/MAINTAINERS +++ b/board/keymile/km_arm/MAINTAINERS @@ -1,5 +1,5 @@ KM_ARM BOARD -M: Valentin Longchamp <valentin.longchamp@keymile.com> +M: Valentin Longchamp <valentin.longchamp@ch.abb.com> S: Maintained F: board/keymile/km_arm/ F: include/configs/km_kirkwood.h diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS index 93b6bad0a8b..c5170c97e71 100644 --- a/board/keymile/kmp204x/MAINTAINERS +++ b/board/keymile/kmp204x/MAINTAINERS @@ -1,5 +1,5 @@ KMP204X BOARD -M: Valentin Longchamp <valentin.longchamp@keymile.com> +M: Valentin Longchamp <valentin.longchamp@ch.abb.com> S: Maintained F: board/keymile/kmp204x/ F: include/configs/kmp204x.h diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig new file mode 100644 index 00000000000..bf8e1a13ece --- /dev/null +++ b/board/microchip/mpfs_icicle/Kconfig @@ -0,0 +1,26 @@ +if TARGET_MICROCHIP_ICICLE + +config SYS_BOARD + default "mpfs_icicle" + +config SYS_VENDOR + default "microchip" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "microchip_mpfs_icicle" + +config SYS_TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + select BOARD_EARLY_INIT_F + imply SMP + imply SYS_NS16550 + +endif diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS new file mode 100644 index 00000000000..22f3b97d8b1 --- /dev/null +++ b/board/microchip/mpfs_icicle/MAINTAINERS @@ -0,0 +1,7 @@ +Microchip MPFS icicle +M: Padmarao Begari <padmarao.begari@microchip.com> +M: Cyril Jean <cyril.jean@microchip.com> +S: Maintained +F: board/microchip/mpfs_icicle/ +F: include/configs/microchip_mpfs_icicle.h +F: configs/microchip_mpfs_icicle_defconfig diff --git a/board/microchip/mpfs_icicle/Makefile b/board/microchip/mpfs_icicle/Makefile new file mode 100644 index 00000000000..72b0410dda8 --- /dev/null +++ b/board/microchip/mpfs_icicle/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. +# Padmarao Begari <padmarao.begari@microchip.com> +# + +obj-y += mpfs_icicle.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c new file mode 100644 index 00000000000..0ef243186d4 --- /dev/null +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(1u << 5u)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index f46437901d1..8eb5e304ab2 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_PING imply CLK_SIFIVE imply CLK_SIFIVE_FU540_PRCI + imply CLK_SIFIVE_GEMGXL_MGMT imply DOS_PARTITION imply EFI_PARTITION imply IP_DYN diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 37a599768b1..6e1ede39339 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -93,6 +93,10 @@ static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { }; static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ diff --git a/cmd/led.c b/cmd/led.c index fc07ca95a31..403abbc6bcf 100644 --- a/cmd/led.c +++ b/cmd/led.c @@ -85,7 +85,7 @@ int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc < 2) return CMD_RET_USAGE; led_label = argv[1]; - if (*led_label == 'l') + if (strncmp(led_label, "list", 4) == 0) return list_leds(); cmd = argc > 2 ? get_led_cmd(argv[2]) : LEDST_COUNT; @@ -137,6 +137,6 @@ U_BOOT_CMD( led, 4, 1, do_led, "manage LEDs", "<led_label> on|off|toggle" BLINK "\tChange LED state\n" - "led [<led_label>\tGet LED state\n" + "led [<led_label>]\tGet LED state\n" "led list\t\tshow a list of LEDs" ); diff --git a/cmd/mdio.c b/cmd/mdio.c index efe8c9ef095..5e219f699d8 100644 --- a/cmd/mdio.c +++ b/cmd/mdio.c @@ -54,7 +54,10 @@ static int mdio_write_ranges(struct mii_dev *bus, for (devad = devadlo; devad <= devadhi; devad++) { for (reg = reglo; reg <= reghi; reg++) { - if (!extended) + if (!phydev) + err = bus->write(bus, addr, devad, + reg, data); + else if (!extended) err = phy_write_mmd(phydev, devad, reg, data); else @@ -88,7 +91,9 @@ static int mdio_read_ranges(struct mii_dev *bus, for (reg = reglo; reg <= reghi; reg++) { int val; - if (!extended) + if (!phydev) + val = bus->read(bus, addr, devad, reg); + else if (!extended) val = phy_read_mmd(phydev, devad, reg); else val = phydev->drv->readext(phydev, addr, diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index f0982221131..7ecdc361ce8 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -20,7 +20,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 8c16d5c4f5a..c0950582825 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -21,7 +21,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index b8eac0e6599..72710163467 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -19,7 +19,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_NAND_SUPPORT=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig new file mode 100644 index 00000000000..a375546a751 --- /dev/null +++ b/configs/microchip_mpfs_icicle_defconfig @@ -0,0 +1,8 @@ +CONFIG_RISCV=y +CONFIG_ARCH_RV64I=y +CONFIG_NR_CPUS=5 +CONFIG_TARGET_MICROCHIP_ICICLE=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_FIT=y +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index e43141844a1..48f251ebb80 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -18,7 +18,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5 CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 81fc9f8fdae..644881b9487 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -17,3 +17,10 @@ config CLK_SIFIVE_FU540_PRCI Supports the Power Reset Clock interface (PRCI) IP block found in FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, enable this driver. + +config CLK_SIFIVE_GEMGXL_MGMT + bool "GEMGXL management for SiFive FU540 SoCs" + depends on CLK_SIFIVE + help + Supports the GEMGXL management IP block found in FU540 SoCs to + control GEM TX clock operation mode for 10/100/1000 Mbps. diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index 1155e07e370..f8263e79b70 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o + +obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT) += gemgxl-mgmt.o diff --git a/drivers/clk/sifive/gemgxl-mgmt.c b/drivers/clk/sifive/gemgxl-mgmt.c new file mode 100644 index 00000000000..eb37416b5e0 --- /dev/null +++ b/drivers/clk/sifive/gemgxl-mgmt.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> + +struct gemgxl_mgmt_regs { + __u32 tx_clk_sel; +}; + +struct gemgxl_mgmt_platdata { + struct gemgxl_mgmt_regs *regs; +}; + +static int gemgxl_mgmt_ofdata_to_platdata(struct udevice *dev) +{ + struct gemgxl_mgmt_platdata *plat = dev_get_platdata(dev); + + plat->regs = (struct gemgxl_mgmt_regs *)dev_read_addr(dev); + + return 0; +} + +static ulong gemgxl_mgmt_set_rate(struct clk *clk, ulong rate) +{ + struct gemgxl_mgmt_platdata *plat = dev_get_platdata(clk->dev); + + /* + * GEMGXL TX clock operation mode: + * + * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic + * and output clock on GMII output signal GTX_CLK + * 1 = MII mode. Use MII input signal TX_CLK in TX logic + */ + writel(rate != 125000000, &plat->regs->tx_clk_sel); + + return 0; +} + +const struct clk_ops gemgxl_mgmt_ops = { + .set_rate = gemgxl_mgmt_set_rate, +}; + +static const struct udevice_id gemgxl_mgmt_match[] = { + { .compatible = "sifive,cadencegemgxlmgmt0", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sifive_gemgxl_mgmt) = { + .name = "sifive-gemgxl-mgmt", + .id = UCLASS_CLK, + .of_match = gemgxl_mgmt_match, + .ofdata_to_platdata = gemgxl_mgmt_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct gemgxl_mgmt_platdata), + .ops = &gemgxl_mgmt_ops, +}; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 72614164e9c..c5560a71114 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -488,15 +488,58 @@ static int macb_phy_find(struct macb_device *macb, const char *name) /** * macb_linkspd_cb - Linkspeed change callback function - * @regs: Base Register of MACB devices + * @dev/@regs: MACB udevice (DM version) or + * Base Register of MACB devices (non-DM version) * @speed: Linkspeed * Returns 0 when operation success and negative errno number * when operation failed. */ +#ifdef CONFIG_DM_ETH +int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed) +{ +#ifdef CONFIG_CLK + struct clk tx_clk; + ulong rate; + int ret; + + /* + * "tx_clk" is an optional clock source for MACB. + * Ignore if it does not exist in DT. + */ + ret = clk_get_by_name(dev, "tx_clk", &tx_clk); + if (ret) + return 0; + + switch (speed) { + case _10BASET: + rate = 2500000; /* 2.5 MHz */ + break; + case _100BASET: + rate = 25000000; /* 25 MHz */ + break; + case _1000BASET: + rate = 125000000; /* 125 MHz */ + break; + default: + /* does not change anything */ + return 0; + } + + if (tx_clk.dev) { + ret = clk_set_rate(&tx_clk, rate); + if (ret) + return ret; + } +#endif + + return 0; +} +#else int __weak macb_linkspd_cb(void *regs, unsigned int speed) { return 0; } +#endif #ifdef CONFIG_DM_ETH static int macb_phy_init(struct udevice *dev, const char *name) @@ -589,7 +632,11 @@ static int macb_phy_init(struct macb_device *macb, const char *name) macb_writel(macb, NCFGR, ncfgr); +#ifdef CONFIG_DM_ETH + ret = macb_linkspd_cb(dev, _1000BASET); +#else ret = macb_linkspd_cb(macb->regs, _1000BASET); +#endif if (ret) return ret; @@ -614,9 +661,17 @@ static int macb_phy_init(struct macb_device *macb, const char *name) ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); if (speed) { ncfgr |= MACB_BIT(SPD); +#ifdef CONFIG_DM_ETH + ret = macb_linkspd_cb(dev, _100BASET); +#else ret = macb_linkspd_cb(macb->regs, _100BASET); +#endif } else { +#ifdef CONFIG_DM_ETH + ret = macb_linkspd_cb(dev, _10BASET); +#else ret = macb_linkspd_cb(macb->regs, _10BASET); +#endif } if (ret) diff --git a/drivers/rtc/rtc-lib.c b/drivers/rtc/rtc-lib.c index 6528ddfebb4..1f7bdade298 100644 --- a/drivers/rtc/rtc-lib.c +++ b/drivers/rtc/rtc-lib.c @@ -23,7 +23,7 @@ static const unsigned char rtc_days_in_month[] = { /* * The number of days in the month. */ -static int rtc_month_days(unsigned int month, unsigned int year) +int rtc_month_days(unsigned int month, unsigned int year) { return rtc_days_in_month[month] + (is_leap_year(year) && month == 1); } diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 1e239ecadd0..36ca3b201ed 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -22,6 +22,7 @@ #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SKIP_LOWLEVEL_INIT /* * Memory Info diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h new file mode 100644 index 00000000000..82c7fbbdf22 --- /dev/null +++ b/include/configs/microchip_mpfs_icicle.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* + * Print Buffer Size + */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * max number of command args + */ +#define CONFIG_SYS_MAXARGS 16 + +/* + * Boot Argument Buffer Size + */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Size of malloc() pool + * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough + */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 + +/* Init Stack Pointer */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000) + +#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* SDRAM */ + +/* + * memtest works on DRAM + */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) + +/* When we use RAM as ENV */ +#define CONFIG_ENV_SIZE 0x2000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index b7110edebcb..df22f780b09 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -20,7 +20,7 @@ #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ -#define CONFIG_ENV_SIZE SZ_4K +#define CONFIG_ENV_SIZE SZ_128K #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ diff --git a/include/efi_loader.h b/include/efi_loader.h index 43d3a084282..23ce7322676 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -287,19 +287,37 @@ extern struct list_head efi_obj_list; extern struct list_head efi_events; /** + * struct efi_protocol_notification - handle for notified protocol + * + * When a protocol interface is installed for which an event was registered with + * the RegisterProtocolNotify() service this structure is used to hold the + * handle on which the protocol interface was installed. + * + * @link: link to list of all handles notified for this event + * @handle: handle on which the notified protocol interface was installed + */ +struct efi_protocol_notification { + struct list_head link; + efi_handle_t handle; +}; + +/** * efi_register_notify_event - event registered by RegisterProtocolNotify() * * The address of this structure serves as registration value. * - * @link: link to list of all registered events - * @event: registered event. The same event may registered for - * multiple GUIDs. - * @protocol: protocol for which the event is registered + * @link: link to list of all registered events + * @event: registered event. The same event may registered for multiple + * GUIDs. + * @protocol: protocol for which the event is registered + * @handles: linked list of all handles on which the notified protocol was + * installed */ struct efi_register_notify_event { struct list_head link; struct efi_event *event; efi_guid_t protocol; + struct list_head handles; }; /* List of all events registered by RegisterProtocolNotify() */ @@ -576,6 +594,8 @@ efi_status_t __efi_runtime EFIAPI efi_get_time( struct efi_time *time, struct efi_time_cap *capabilities); +efi_status_t __efi_runtime EFIAPI efi_set_time(struct efi_time *time); + #ifdef CONFIG_CMD_BOOTEFI_SELFTEST /* * Entry point for the tests of the EFI API. diff --git a/include/rtc.h b/include/rtc.h index 2c3a5743e30..b255bdc7a33 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -258,4 +258,12 @@ void rtc_to_tm(u64 time_t, struct rtc_time *time); */ unsigned long rtc_mktime(const struct rtc_time *time); +/** + * rtc_month_days() - The number of days in the month + * + * @month: month (January = 0) + * @year: year (4 digits) + */ +int rtc_month_days(unsigned int month, unsigned int year); + #endif /* _RTC_H_ */ diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index fc04ea39d0a..cd5436c576b 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -18,6 +18,22 @@ config EFI_LOADER if EFI_LOADER +config EFI_GET_TIME + bool "GetTime() runtime service" + depends on DM_RTC + default y + help + Provide the GetTime() runtime service at boottime. This service + can be used by an EFI application to read the real time clock. + +config EFI_SET_TIME + bool "SetTime() runtime service" + depends on EFI_GET_TIME + default n + help + Provide the SetTime() runtime service at boottime. This service + can be used by an EFI application to adjust the real time clock. + config EFI_DEVICE_PATH_TO_TEXT bool "Device path to text protocol" default y diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 78c6076e28c..7d1d6e92138 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -921,6 +921,14 @@ static efi_status_t EFIAPI efi_close_event(struct efi_event *event) list_for_each_entry_safe(item, next, &efi_register_notify_events, link) { if (event == item->event) { + struct efi_protocol_notification *hitem, *hnext; + + /* Remove signaled handles */ + list_for_each_entry_safe(hitem, hnext, &item->handles, + link) { + list_del(&hitem->link); + free(hitem); + } list_del(&item->link); free(item); } @@ -1049,8 +1057,19 @@ efi_status_t efi_add_protocol(const efi_handle_t handle, /* Notify registered events */ list_for_each_entry(event, &efi_register_notify_events, link) { - if (!guidcmp(protocol, &event->protocol)) + if (!guidcmp(protocol, &event->protocol)) { + struct efi_protocol_notification *notif; + + notif = calloc(1, sizeof(*notif)); + if (!notif) { + list_del(&handler->link); + free(handler); + return EFI_OUT_OF_RESOURCES; + } + notif->handle = handle; + list_add_tail(¬if->link, &event->handles); efi_signal_event(event->event, true); + } } if (!guidcmp(&efi_guid_device_path, protocol)) @@ -1246,10 +1265,6 @@ static efi_status_t efi_uninstall_protocol goto out; /* Disconnect controllers */ efi_disconnect_all_drivers(efiobj, protocol, NULL); - if (!list_empty(&handler->open_infos)) { - r = EFI_ACCESS_DENIED; - goto out; - } /* Close protocol */ list_for_each_entry_safe(item, pos, &handler->open_infos, link) { if (item->info.attributes == @@ -1337,6 +1352,7 @@ static efi_status_t EFIAPI efi_register_protocol_notify( item->event = event; memcpy(&item->protocol, protocol, sizeof(efi_guid_t)); + INIT_LIST_HEAD(&item->handles); list_add_tail(&item->link, &efi_register_notify_events); @@ -1364,7 +1380,6 @@ static int efi_search(enum efi_locate_search_type search_type, switch (search_type) { case ALL_HANDLES: return 0; - case BY_REGISTER_NOTIFY: case BY_PROTOCOL: ret = efi_search_protocol(handle, protocol, NULL); return (ret != EFI_SUCCESS); @@ -1375,6 +1390,27 @@ static int efi_search(enum efi_locate_search_type search_type, } /** + * efi_check_register_notify_event() - check if registration key is valid + * + * Check that a pointer is a valid registration key as returned by + * RegisterProtocolNotify(). + * + * @key: registration key + * Return: valid registration key or NULL + */ +static struct efi_register_notify_event *efi_check_register_notify_event + (void *key) +{ + struct efi_register_notify_event *event; + + list_for_each_entry(event, &efi_register_notify_events, link) { + if (event == (struct efi_register_notify_event *)key) + return event; + } + return NULL; +} + +/** * efi_locate_handle() - locate handles implementing a protocol * * @search_type: selection criterion @@ -1395,7 +1431,8 @@ static efi_status_t efi_locate_handle( { struct efi_object *efiobj; efi_uintn_t size = 0; - struct efi_register_notify_event *item, *event = NULL; + struct efi_register_notify_event *event; + struct efi_protocol_notification *handle = NULL; /* Check parameters */ switch (search_type) { @@ -1405,17 +1442,9 @@ static efi_status_t efi_locate_handle( if (!search_key) return EFI_INVALID_PARAMETER; /* Check that the registration key is valid */ - list_for_each_entry(item, &efi_register_notify_events, link) { - if (item == - (struct efi_register_notify_event *)search_key) { - event = item; - break; - } - } + event = efi_check_register_notify_event(search_key); if (!event) return EFI_INVALID_PARAMETER; - - protocol = &event->protocol; break; case BY_PROTOCOL: if (!protocol) @@ -1426,14 +1455,23 @@ static efi_status_t efi_locate_handle( } /* Count how much space we need */ - list_for_each_entry(efiobj, &efi_obj_list, link) { - if (!efi_search(search_type, protocol, efiobj)) - size += sizeof(void *); + if (search_type == BY_REGISTER_NOTIFY) { + if (list_empty(&event->handles)) + return EFI_NOT_FOUND; + handle = list_first_entry(&event->handles, + struct efi_protocol_notification, + link); + efiobj = handle->handle; + size += sizeof(void *); + } else { + list_for_each_entry(efiobj, &efi_obj_list, link) { + if (!efi_search(search_type, protocol, efiobj)) + size += sizeof(void *); + } + if (size == 0) + return EFI_NOT_FOUND; } - if (size == 0) - return EFI_NOT_FOUND; - if (!buffer_size) return EFI_INVALID_PARAMETER; @@ -1449,9 +1487,14 @@ static efi_status_t efi_locate_handle( return EFI_INVALID_PARAMETER; /* Then fill the array */ - list_for_each_entry(efiobj, &efi_obj_list, link) { - if (!efi_search(search_type, protocol, efiobj)) - *buffer++ = efiobj; + if (search_type == BY_REGISTER_NOTIFY) { + *buffer = efiobj; + list_del(&handle->link); + } else { + list_for_each_entry(efiobj, &efi_obj_list, link) { + if (!efi_search(search_type, protocol, efiobj)) + *buffer++ = efiobj; + } } return EFI_SUCCESS; @@ -2024,7 +2067,6 @@ static efi_status_t EFIAPI efi_close_protocol(efi_handle_t handle, item->info.controller_handle == controller_handle) { efi_delete_open_info(item); r = EFI_SUCCESS; - break; } } out: @@ -2223,29 +2265,58 @@ static efi_status_t EFIAPI efi_locate_protocol(const efi_guid_t *protocol, void *registration, void **protocol_interface) { - struct list_head *lhandle; + struct efi_handler *handler; efi_status_t ret; + struct efi_object *efiobj; EFI_ENTRY("%pUl, %p, %p", protocol, registration, protocol_interface); + /* + * The UEFI spec explicitly requires a protocol even if a registration + * key is provided. This differs from the logic in LocateHandle(). + */ if (!protocol || !protocol_interface) return EFI_EXIT(EFI_INVALID_PARAMETER); - list_for_each(lhandle, &efi_obj_list) { - struct efi_object *efiobj; - struct efi_handler *handler; - - efiobj = list_entry(lhandle, struct efi_object, link); + if (registration) { + struct efi_register_notify_event *event; + struct efi_protocol_notification *handle; + event = efi_check_register_notify_event(registration); + if (!event) + return EFI_EXIT(EFI_INVALID_PARAMETER); + /* + * The UEFI spec requires to return EFI_NOT_FOUND if no + * protocol instance matches protocol and registration. + * So let's do the same for a mismatch between protocol and + * registration. + */ + if (guidcmp(&event->protocol, protocol)) + goto not_found; + if (list_empty(&event->handles)) + goto not_found; + handle = list_first_entry(&event->handles, + struct efi_protocol_notification, + link); + efiobj = handle->handle; + list_del(&handle->link); + free(handle); ret = efi_search_protocol(efiobj, protocol, &handler); - if (ret == EFI_SUCCESS) { - *protocol_interface = handler->protocol_interface; - return EFI_EXIT(EFI_SUCCESS); + if (ret == EFI_SUCCESS) + goto found; + } else { + list_for_each_entry(efiobj, &efi_obj_list, link) { + ret = efi_search_protocol(efiobj, protocol, &handler); + if (ret == EFI_SUCCESS) + goto found; } } +not_found: *protocol_interface = NULL; - return EFI_EXIT(EFI_NOT_FOUND); +found: + *protocol_interface = handler->protocol_interface; + return EFI_EXIT(EFI_SUCCESS); } /** @@ -2572,34 +2643,50 @@ static efi_status_t efi_protocol_open( if ((attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) && (item->info.attributes == attributes)) return EFI_ALREADY_STARTED; + } else { + if (item->info.attributes & + EFI_OPEN_PROTOCOL_BY_DRIVER) + opened_by_driver = true; } if (item->info.attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE) opened_exclusive = true; } /* Only one controller can open the protocol exclusively */ - if (opened_exclusive && attributes & - (EFI_OPEN_PROTOCOL_EXCLUSIVE | EFI_OPEN_PROTOCOL_BY_DRIVER)) - return EFI_ACCESS_DENIED; + if (attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE) { + if (opened_exclusive) + return EFI_ACCESS_DENIED; + } else if (attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) { + if (opened_exclusive || opened_by_driver) + return EFI_ACCESS_DENIED; + } /* Prepare exclusive opening */ if (attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE) { /* Try to disconnect controllers */ +disconnect_next: + opened_by_driver = false; list_for_each_entry(item, &handler->open_infos, link) { + efi_status_t ret; + if (item->info.attributes == - EFI_OPEN_PROTOCOL_BY_DRIVER) - EFI_CALL(efi_disconnect_controller( + EFI_OPEN_PROTOCOL_BY_DRIVER) { + ret = EFI_CALL(efi_disconnect_controller( item->info.controller_handle, item->info.agent_handle, NULL)); + if (ret == EFI_SUCCESS) + /* + * Child controllers may have been + * removed from the open_infos list. So + * let's restart the loop. + */ + goto disconnect_next; + else + opened_by_driver = true; + } } - opened_by_driver = false; - /* Check if all controllers are disconnected */ - list_for_each_entry(item, &handler->open_infos, link) { - if (item->info.attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) - opened_by_driver = true; - } - /* Only one controller can be connected */ + /* Only one driver can be connected */ if (opened_by_driver) return EFI_ACCESS_DENIED; } @@ -2607,7 +2694,8 @@ static efi_status_t efi_protocol_open( /* Find existing entry */ list_for_each_entry(item, &handler->open_infos, link) { if (item->info.agent_handle == agent_handle && - item->info.controller_handle == controller_handle) + item->info.controller_handle == controller_handle && + item->info.attributes == attributes) match = &item->info; } /* None found, create one */ @@ -3030,7 +3118,7 @@ static efi_status_t EFIAPI efi_handle_protocol(efi_handle_t handle, const efi_guid_t *protocol, void **protocol_interface) { - return efi_open_protocol(handle, protocol, protocol_interface, NULL, + return efi_open_protocol(handle, protocol, protocol_interface, efi_root, NULL, EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); } diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 058b40a8876..9c50955c9bd 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -167,7 +167,7 @@ static efi_status_t EFIAPI efi_get_time_boottime( struct efi_time *time, struct efi_time_cap *capabilities) { -#ifdef CONFIG_DM_RTC +#ifdef CONFIG_EFI_GET_TIME efi_status_t ret = EFI_SUCCESS; struct rtc_time tm; struct udevice *dev; @@ -195,9 +195,9 @@ static efi_status_t EFIAPI efi_get_time_boottime( time->hour = tm.tm_hour; time->minute = tm.tm_min; time->second = tm.tm_sec; - time->daylight = EFI_TIME_ADJUST_DAYLIGHT; - if (tm.tm_isdst > 0) - time->daylight |= EFI_TIME_IN_DAYLIGHT; + if (tm.tm_isdst) + time->daylight = + EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT; time->timezone = EFI_UNSPECIFIED_TIMEZONE; if (capabilities) { @@ -214,6 +214,30 @@ out: #endif } +#ifdef CONFIG_EFI_SET_TIME + +/** + * efi_validate_time() - checks if timestamp is valid + * + * @time: timestamp to validate + * Returns: 0 if timestamp is valid, 1 otherwise + */ +static int efi_validate_time(struct efi_time *time) +{ + return (!time || + time->year < 1900 || time->year > 9999 || + !time->month || time->month > 12 || !time->day || + time->day > rtc_month_days(time->month - 1, time->year) || + time->hour > 23 || time->minute > 59 || time->second > 59 || + time->nanosecond > 999999999 || + time->daylight & + ~(EFI_TIME_IN_DAYLIGHT | EFI_TIME_ADJUST_DAYLIGHT) || + ((time->timezone < -1440 || time->timezone > 1440) && + time->timezone != EFI_UNSPECIFIED_TIMEZONE)); +} + +#endif + /** * efi_set_time_boottime() - set current time * @@ -228,14 +252,14 @@ out: */ static efi_status_t EFIAPI efi_set_time_boottime(struct efi_time *time) { -#ifdef CONFIG_DM_RTC +#ifdef CONFIG_EFI_SET_TIME efi_status_t ret = EFI_SUCCESS; struct rtc_time tm; struct udevice *dev; EFI_ENTRY("%p", time); - if (!time) { + if (efi_validate_time(time)) { ret = EFI_INVALID_PARAMETER; goto out; } @@ -252,7 +276,8 @@ static efi_status_t EFIAPI efi_set_time_boottime(struct efi_time *time) tm.tm_hour = time->hour; tm.tm_min = time->minute; tm.tm_sec = time->second; - tm.tm_isdst = time->daylight == EFI_TIME_IN_DAYLIGHT; + tm.tm_isdst = time->daylight == + (EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT); /* Calculate day of week */ rtc_calc_weekday(&tm); diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index cfbb40c8910..3bebd0f5737 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -26,8 +26,8 @@ efi_selftest_gop.o \ efi_selftest_loaded_image.o \ efi_selftest_manageprotocols.o \ efi_selftest_memory.o \ +efi_selftest_open_protocol.o \ efi_selftest_register_notify.o \ -efi_selftest_rtc.o \ efi_selftest_snp.o \ efi_selftest_textinput.o \ efi_selftest_textinputex.o \ @@ -43,6 +43,7 @@ efi_selftest_unicode_collation.o obj-$(CONFIG_CPU_V7) += efi_selftest_unaligned.o obj-$(CONFIG_EFI_LOADER_HII) += efi_selftest_hii.o +obj-$(CONFIG_EFI_GET_TIME) += efi_selftest_rtc.o ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) obj-y += efi_selftest_fdt.o diff --git a/lib/efi_selftest/efi_selftest_open_protocol.c b/lib/efi_selftest/efi_selftest_open_protocol.c new file mode 100644 index 00000000000..e3f351df723 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_open_protocol.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * efi_selftest_open_protocol + * + * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * This unit test checks that open protocol information is correctly updated + * when calling: + * HandleProtocol, OpenProtocol, OpenProtocolInformation, CloseProtocol. + */ + +#include <efi_selftest.h> + +/* + * The test currently does not actually call the interface function. + * So this is just a dummy structure. + */ +struct interface { + void (EFIAPI *inc)(void); +}; + +static struct efi_boot_services *boottime; +static efi_guid_t guid1 = + EFI_GUID(0x492a0e38, 0x1442, 0xf819, + 0x14, 0xaa, 0x4b, 0x8d, 0x09, 0xfe, 0x5a, 0xb9); +static efi_handle_t handle1; +static struct interface interface1; + +/* + * Setup unit test. + * + * Create a handle and install a protocol interface on it. + * + * @handle: handle of the loaded image + * @systable: system table + */ +static int setup(const efi_handle_t img_handle, + const struct efi_system_table *systable) +{ + efi_status_t ret; + + boottime = systable->boottime; + + ret = boottime->install_protocol_interface(&handle1, &guid1, + EFI_NATIVE_INTERFACE, + &interface1); + if (ret != EFI_SUCCESS) { + efi_st_error("InstallProtocolInterface failed\n"); + return EFI_ST_FAILURE; + } + if (!handle1) { + efi_st_error + ("InstallProtocolInterface failed to create handle\n"); + return EFI_ST_FAILURE; + } + return EFI_ST_SUCCESS; +} + +/* + * Tear down unit test. + * + */ +static int teardown(void) +{ + efi_status_t ret; + + if (handle1) { + ret = boottime->uninstall_protocol_interface(handle1, &guid1, + &interface1); + if (ret != EFI_SUCCESS) { + efi_st_error("UninstallProtocolInterface failed\n"); + return EFI_ST_FAILURE; + } + } + return EFI_ST_SUCCESS; +} + +/* + * Execute unit test. + * + * Open the installed protocol twice via HandleProtocol() and once via + * OpenProtocol(EFI_OPEN_PROTOCOL_GET_PROTOCOL). Read the open protocol + * information and check the open counts. Finally close the protocol and + * check again. + */ +static int execute(void) +{ + void *interface; + struct efi_open_protocol_info_entry *entry_buffer; + efi_uintn_t entry_count; + efi_handle_t firmware_handle; + efi_status_t ret; + + ret = boottime->handle_protocol(handle1, &guid1, &interface); + if (ret != EFI_SUCCESS) { + efi_st_error("HandleProtocol failed\n"); + return EFI_ST_FAILURE; + } + if (interface != &interface1) { + efi_st_error("HandleProtocol returned wrong interface\n"); + return EFI_ST_FAILURE; + } + ret = boottime->open_protocol_information(handle1, &guid1, + &entry_buffer, &entry_count); + if (ret != EFI_SUCCESS) { + efi_st_error("OpenProtocolInformation failed\n"); + return EFI_ST_FAILURE; + } + if (entry_count != 1) { + efi_st_error("Incorrect OpenProtocolInformation count\n"); + efi_st_printf("Expected 1, got %u\n", + (unsigned int)entry_count); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(entry_buffer); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->handle_protocol(handle1, &guid1, &interface); + if (ret != EFI_SUCCESS) { + efi_st_error("HandleProtocol failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->open_protocol_information(handle1, &guid1, + &entry_buffer, &entry_count); + if (ret != EFI_SUCCESS) { + efi_st_error("OpenProtocolInformation failed\n"); + return EFI_ST_FAILURE; + } + if (entry_count != 1) { + efi_st_error("Incorrect OpenProtocolInformation count\n"); + efi_st_printf("Expected 1, got %u\n", + (unsigned int)entry_count); + return EFI_ST_FAILURE; + } + if (entry_buffer[0].open_count != 2) { + efi_st_error("Incorrect open count: expected 2 got %u\n", + entry_buffer[0].open_count); + return EFI_ST_FAILURE; + } + firmware_handle = entry_buffer[0].agent_handle; + ret = boottime->free_pool(entry_buffer); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->open_protocol(handle1, &guid1, &interface, + firmware_handle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS) { + efi_st_error("OpenProtocol failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->open_protocol_information(handle1, &guid1, + &entry_buffer, &entry_count); + if (ret != EFI_SUCCESS) { + efi_st_error("OpenProtocolInformation failed\n"); + return EFI_ST_FAILURE; + } + if (entry_count != 2) { + efi_st_error("Incorrect OpenProtocolInformation count\n"); + efi_st_printf("Expected 2, got %u\n", + (unsigned int)entry_count); + return EFI_ST_FAILURE; + } + if (entry_buffer[0].open_count + entry_buffer[1].open_count != 3) { + efi_st_error("Incorrect open count: expected 3 got %u\n", + entry_buffer[0].open_count + + entry_buffer[1].open_count); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(entry_buffer); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->close_protocol(handle1, &guid1, firmware_handle, NULL); + if (ret != EFI_SUCCESS) { + efi_st_error("CloseProtocol failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->open_protocol_information(handle1, &guid1, + &entry_buffer, &entry_count); + if (ret != EFI_SUCCESS) { + efi_st_error("OpenProtocolInformation failed\n"); + return EFI_ST_FAILURE; + } + if (entry_count) { + efi_st_error("Incorrect OpenProtocolInformation count\n"); + efi_st_printf("Expected 0, got %u\n", + (unsigned int)entry_count); + return EFI_ST_FAILURE; + } + + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(openprot) = { + .name = "open protocol", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, + .teardown = teardown, +}; diff --git a/lib/efi_selftest/efi_selftest_register_notify.c b/lib/efi_selftest/efi_selftest_register_notify.c index ee0ef395de4..ad763dd6cb8 100644 --- a/lib/efi_selftest/efi_selftest_register_notify.c +++ b/lib/efi_selftest/efi_selftest_register_notify.c @@ -47,15 +47,20 @@ static void EFIAPI notify(struct efi_event *event, void *context) { struct context *cp = context; efi_status_t ret; + efi_uintn_t handle_count; + efi_handle_t *handles; cp->notify_count++; - ret = boottime->locate_handle_buffer(BY_REGISTER_NOTIFY, NULL, - cp->registration_key, - &cp->handle_count, - &cp->handles); - if (ret != EFI_SUCCESS) - cp->handle_count = 0; + for (;;) { + ret = boottime->locate_handle_buffer(BY_REGISTER_NOTIFY, NULL, + cp->registration_key, + &handle_count, &handles); + if (ret != EFI_SUCCESS) + break; + cp->handle_count += handle_count; + cp->handles = handles; + } } /* @@ -170,7 +175,7 @@ static int execute(void) efi_st_error("reinstall was notified too often\n"); return EFI_ST_FAILURE; } - if (context.handle_count != 1) { + if (context.handle_count != 2) { efi_st_error("LocateHandle failed\n"); return EFI_ST_FAILURE; } @@ -195,7 +200,7 @@ static int execute(void) efi_st_error("install was notified too often\n"); return EFI_ST_FAILURE; } - if (context.handle_count != 2) { + if (context.handle_count != 3) { efi_st_error("LocateHandle failed\n"); return EFI_ST_FAILURE; } diff --git a/lib/efi_selftest/efi_selftest_rtc.c b/lib/efi_selftest/efi_selftest_rtc.c index 9eb29add3b0..6f7035dee61 100644 --- a/lib/efi_selftest/efi_selftest_rtc.c +++ b/lib/efi_selftest/efi_selftest_rtc.c @@ -40,7 +40,9 @@ static int setup(const efi_handle_t handle, static int execute(void) { efi_status_t ret; - struct efi_time tm, tm_old, tm_new = { + struct efi_time tm_old; +#ifdef CONFIG_EFI_SET_TIME + struct efi_time tm, tm_new = { .year = 2017, .month = 5, .day = 19, @@ -48,31 +50,23 @@ static int execute(void) .minute = 47, .second = 53, }; +#endif /* Display current time */ ret = runtime->get_time(&tm_old, NULL); if (ret != EFI_SUCCESS) { -#ifdef CONFIG_CMD_DATE efi_st_error(EFI_ST_NO_RTC); return EFI_ST_FAILURE; -#else - efi_st_todo(EFI_ST_NO_RTC); - return EFI_ST_SUCCESS; -#endif } efi_st_printf("Time according to real time clock: " "%.4u-%.2u-%.2u %.2u:%.2u:%.2u\n", tm_old.year, tm_old.month, tm_old.day, tm_old.hour, tm_old.minute, tm_old.second); +#ifdef CONFIG_EFI_SET_TIME ret = runtime->set_time(&tm_new); if (ret != EFI_SUCCESS) { -#ifdef CONFIG_CMD_DATE efi_st_error(EFI_ST_NO_RTC_SET); return EFI_ST_FAILURE; -#else - efi_st_todo(EFI_ST_NO_RTC_SET); - return EFI_ST_SUCCESS; -#endif } ret = runtime->get_time(&tm, NULL); if (ret != EFI_SUCCESS) { @@ -95,6 +89,7 @@ static int execute(void) efi_st_error(EFI_ST_NO_RTC_SET); return EFI_ST_FAILURE; } +#endif return EFI_ST_SUCCESS; } diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 2ef20df1920..031d5586258 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -455,6 +455,26 @@ static int eth_pre_unbind(struct udevice *dev) return 0; } +static bool eth_dev_get_mac_address(struct udevice *dev, u8 mac[ARP_HLEN]) +{ +#if IS_ENABLED(CONFIG_OF_CONTROL) + const uint8_t *p; + + p = dev_read_u8_array_ptr(dev, "mac-address", ARP_HLEN); + if (!p) + p = dev_read_u8_array_ptr(dev, "local-mac-address", ARP_HLEN); + + if (!p) + return false; + + memcpy(mac, p, ARP_HLEN); + + return true; +#else + return false; +#endif +} + static int eth_post_probe(struct udevice *dev) { struct eth_device_priv *priv = dev->uclass_priv; @@ -489,9 +509,13 @@ static int eth_post_probe(struct udevice *dev) priv->state = ETH_STATE_INIT; - /* Check if the device has a MAC address in ROM */ - if (eth_get_ops(dev)->read_rom_hwaddr) - eth_get_ops(dev)->read_rom_hwaddr(dev); + /* Check if the device has a valid MAC address in device tree */ + if (!eth_dev_get_mac_address(dev, pdata->enetaddr) || + !is_valid_ethaddr(pdata->enetaddr)) { + /* Check if the device has a MAC address in ROM */ + if (eth_get_ops(dev)->read_rom_hwaddr) + eth_get_ops(dev)->read_rom_hwaddr(dev); + } eth_env_get_enetaddr_by_index("eth", dev->seq, env_enetaddr); if (!is_zero_ethaddr(env_enetaddr)) { @@ -524,6 +548,8 @@ static int eth_post_probe(struct udevice *dev) #endif } + eth_write_hwaddr(dev); + return 0; } |