diff options
24 files changed, 647 insertions, 369 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 32b698a7f41..976dbda48c3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -918,8 +918,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_IMX9) += \ - imx93-var-som-symphony.dtb \ - imx93-phyboard-segin.dtb + imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ diff --git a/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi b/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi index 7730bb60dd0..faf596255f1 100644 --- a/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi +++ b/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi @@ -5,8 +5,12 @@ * Author: Michael Trimarchi <michael@amarulasolutions.com> */ -&{/soc} { - bootph-all; +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &aips2 { diff --git a/arch/arm/dts/imx93-phyboard-segin.dts b/arch/arm/dts/imx93-phyboard-segin.dts deleted file mode 100644 index 85fb188b057..00000000000 --- a/arch/arm/dts/imx93-phyboard-segin.dts +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> - * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> - * - * Product homepage: - * phyBOARD-Segin carrier board is reused for the i.MX93 design. - * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ - */ -/dts-v1/; - -#include "imx93-phycore-som.dtsi" - -/{ - model = "PHYTEC phyBOARD-Segin-i.MX93"; - compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", - "fsl,imx93"; - - chosen { - stdout-path = &lpuart1; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "VCC_SD"; - }; -}; - -/* Console */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* eMMC */ -&usdhc1 { - no-1-8-v; -}; - -/* SD-Card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; - bus-width = <4>; - cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - no-mmc; - no-sdio; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x30e - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e - >; - }; - - pinctrl_usdhc2_cd: usdhc2cdgrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; - - pinctrl_usdhc2_default: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; -}; diff --git a/arch/arm/dts/imx93-phycore-som.dtsi b/arch/arm/dts/imx93-phycore-som.dtsi deleted file mode 100644 index 88c2657b50e..00000000000 --- a/arch/arm/dts/imx93-phycore-som.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> - * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> - * - * Product homepage: - * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ - */ - -#include <dt-bindings/leds/common.h> - -#include "imx93.dtsi" - -/{ - model = "PHYTEC phyCORE-i.MX93"; - compatible = "phytec,imx93-phycore-som", "fsl,imx93"; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - alloc-ranges = <0 0x80000000 0 0x40000000>; - size = <0 0x10000000>; - linux,cma-default; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -/* Ethernet */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - fsl,magic-packet; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <100000000>, <50000000>, <50000000>; - status = "okay"; - - mdio: mdio { - clock-frequency = <5000000>; - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -/* Watchdog */ -&wdog3 { - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e - MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 567e8e9e81a..3cdb71a2528 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_IMX_HAB) +#if IS_ENABLED(CONFIG_IMX_HAB) struct imx_fuse const imx_sec_config_fuse = { .bank = 1, .word = 3, @@ -52,7 +52,7 @@ struct imx_fuse const imx_field_return_fuse = { int timer_init(void) { -#ifdef CONFIG_XPL_BUILD +#if IS_ENABLED(CONFIG_XPL_BUILD) struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); @@ -110,7 +110,7 @@ void set_wdog_reset(struct wdog_regs *wdog) setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); } -#ifdef CONFIG_ARMV8_PSCI +#if IS_ENABLED(CONFIG_ARMV8_PSCI) #define PTE_MAP_NS PTE_BLOCK_NS #else #define PTE_MAP_NS 0 @@ -700,11 +700,11 @@ int arch_cpu_init(void) return 0; } -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) struct rom_api *g_rom_api = (struct rom_api *)0x980; #endif -#if defined(CONFIG_IMX8M) +#if IS_ENABLED(CONFIG_IMX8M) #include <spl.h> int imx8m_detect_secondary_image_boot(void) { @@ -790,8 +790,8 @@ int boot_mode_getprisec(void) } #endif -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) -#ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) #define IMG_CNTN_SET1_OFFSET GENMASK(22, 19) unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) @@ -826,7 +826,7 @@ unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, return raw_sect; } -#endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */ +#endif /* CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */ #endif bool is_usb_boot(void) @@ -834,7 +834,7 @@ bool is_usb_boot(void) return get_boot_device() == USB_BOOT; } -#ifdef CONFIG_OF_SYSTEM_SETUP +#if IS_ENABLED(CONFIG_OF_SYSTEM_SETUP) bool check_fdt_new_path(void *blob) { const char *soc_path = "/soc@0"; @@ -880,7 +880,7 @@ add_status: return 0; } -#ifdef CONFIG_IMX8MQ +#if IS_ENABLED(CONFIG_IMX8MQ) bool check_dcss_fused(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -1026,7 +1026,7 @@ int disable_vpu_nodes(void *blob) return -EPERM; } -#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +#if IS_ENABLED(CONFIG_IMX8MN_LOW_DRIVE_MODE) static int low_drive_gpu_freq(void *blob) { static const char *nodes_path_8mn[] = { @@ -1311,7 +1311,7 @@ int ft_system_setup(void *blob, struct bd_info *bd) "/cpus/cpu@3", }; -#ifdef CONFIG_IMX8MQ +#if IS_ENABLED(CONFIG_IMX8MQ) int i = 0; int rc; int nodeoff; @@ -1387,7 +1387,7 @@ usb_modify_speed: if (is_imx8md()) disable_cpu_nodes(blob, nodes_path, 2, 4); -#elif defined(CONFIG_IMX8MM) +#elif IS_ENABLED(CONFIG_IMX8MM) if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl()) disable_vpu_nodes(blob); @@ -1396,10 +1396,10 @@ usb_modify_speed: else if (is_imx8mms() || is_imx8mmsl()) disable_cpu_nodes(blob, nodes_path, 3, 4); -#elif defined(CONFIG_IMX8MN) +#elif IS_ENABLED(CONFIG_IMX8MN) if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl()) disable_gpu_nodes(blob); -#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +#if IS_ENABLED(CONFIG_IMX8MN_LOW_DRIVE_MODE) else { int ldm_gpu = low_drive_gpu_freq(blob); @@ -1415,7 +1415,7 @@ usb_modify_speed: else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) disable_cpu_nodes(blob, nodes_path, 3, 4); -#elif defined(CONFIG_IMX8MP) +#elif IS_ENABLED(CONFIG_IMX8MP) if (is_imx8mpul()) { /* Disable GPU */ disable_gpu_nodes(blob); @@ -1471,7 +1471,7 @@ void reset_cpu(void) } #endif -#if defined(CONFIG_ARCH_MISC_INIT) +#if IS_ENABLED(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { @@ -1487,8 +1487,8 @@ int arch_misc_init(void) } #endif -#if defined(CONFIG_XPL_BUILD) -#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) +#if IS_ENABLED(CONFIG_XPL_BUILD) +#if IS_ENABLED(CONFIG_IMX8MQ) || IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) bool serror_need_skip = true; void do_error(struct pt_regs *pt_regs) @@ -1523,7 +1523,7 @@ void do_error(struct pt_regs *pt_regs) #endif #endif -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) enum env_location arch_env_get_location(enum env_operation op, int prio) { enum boot_device dev = get_boot_device(); @@ -1571,7 +1571,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio) #endif -#ifdef CONFIG_IMX_BOOTAUX +#if IS_ENABLED(CONFIG_IMX_BOOTAUX) const struct rproc_att hostmap[] = { /* aux core , host core, size */ { 0x00000000, 0x007e0000, 0x00020000 }, diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 0fd82dc0811..e6cafdcd813 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -73,6 +73,7 @@ config TARGET_PHYCORE_IMX93 bool "phycore_imx93" select IMX93 select IMX9_LPDDR4X + imply OF_UPSTREAM select OF_BOARD_FIXUP select OF_BOARD_SETUP diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 3982f4cca18..b7008df8e35 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -35,12 +35,10 @@ ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev) { u32 sector = 0; - /* - * Some boards use this value even though MMC is not enabled in SPL, for - * example imx8mn_bsh_smm_s2 - */ -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR) sector = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; +#elif IS_ENABLED(CONFIG_SPL_NAND_RAW_U_BOOT_USE_SECTOR) + sector = CONFIG_SPL_NAND_RAW_U_BOOT_SECTOR; #endif return image_offset + sector * 512 - 0x8000; diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile index 59870419bdd..4f4d67f659d 100644 --- a/board/bsh/imx6ulz_smm_m2/Makefile +++ b/board/bsh/imx6ulz_smm_m2/Makefile @@ -2,5 +2,4 @@ # (C) Copyright 2021 Amarula Solutions B.V. obj-y := imx6ulz_smm_m2.o -obj-$(CONFIG_XPL_BUILD) += spl.o - +obj-$(CONFIG_XPL_BUILD) += spl.o ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c new file mode 100644 index 00000000000..66c3483adbf --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ + + /* Address: */ + {0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured + * using Group Control Register IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ + {0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ + {0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:ISSI + * Device Part Number:IS43TR16640BL-125JBLI + * Clock Freq.: 400MHz + * Density per CS in Gb: 1 + * Chip Selects used:1 + * Number of Banks:8 + * Row address: 13 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit + * during MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration. + */ + + /* + * For target board, may need to run write leveling calibration to fine tune + * these settings. + */ + {0x021b080c, 0x00000000}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x41480148}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */ + + /* Write calibration */ + {0x021b0850, 0x4040362E}, /* MPWRDLCTL PHY0 */ + + /* + * Read data bit delay: 3 is the recommended default value, although out of reset + * value is 0. + */ + {0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + /* Write data bit delay: */ + {0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */ + + /* DQS&CLK Duty Cycle */ + {0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */ + + /* Complete calibration by forced measurement: */ + {0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* + * ============================================================================= + * Calibration setup end + * ============================================================================= + */ + + /* MMDC init: */ + {0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB66D0B63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + + /* + * MDMISC: RALAT kept to the high level of 5. + * MDMISC: consider reducing RALAT if your 528MHz board design allow that. + * Lower RALAT benefits: + * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 + * b. Small performance improvement + */ + {0x021b0018, 0x00211740}, /* MMDC0_MDMISC */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit during + * MMDC set up + */ + {0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x002F1023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000043}, /* Chan0 CS0_END */ + {0x021b0000, 0x82180000}, /* MMDC0_MDCTL */ + + {0x021b0890, 0x00400000}, /* MPPDCMPR2 */ + + /* Mode register writes */ + {0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */ + {0x021b001c, 0x04008040}, /* + * MMDC0_MDSCR, ZQ calibration command sent to device + * on CS0 + */ + + {0x021b0020, 0x00007800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + + {0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */ + + {0x021b0404, 0x00011006}, /* + * MMDC0_MAPSR ADOPT power down enabled, + * MMDC will enter automatically to self-refresh + * while the number of idle cycle reached. + */ + + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially the + * configuration bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_128mb = { + .ddrc_cfg = ddr_ddrc_cfg_128mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb), +}; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c new file mode 100644 index 00000000000..0fe5b90a673 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ + + /* Address: */ + {0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured + * using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ + {0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ + {0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:ISSI + * Device Part Number:IS43TR16640BL-125JBLI + * Clock Freq.: 400MHz + * Density per CS in Gb: 2 + * Chip Selects used:1 + * Number of Banks:8 + * Row address: 14 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit during + * MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration + */ + + /* + * For target board, may need to run write leveling calibration to fine tune these settings + */ + {0x021b080c, 0x00050005}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x01480144}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x4040363A}, /* MPRDDLCTL PHY0 */ + + /* Write calibration */ + {0x021b0850, 0x40402E2C}, /* MPWRDLCTL PHY0 */ + + /* + * Read data bit delay: 3 is the reccommended default value, although out of reset value + * is 0 + */ + {0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + /* Write data bit delay: */ + {0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */ + + /* DQS&CLK Duty Cycle */ + {0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */ + + /* Complete calibration by forced measurement: */ + {0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* + * ============================================================================= + * Calibration setup end + * ============================================================================= + */ + + /* MMDC init: */ + {0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x3F435333}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB68E0B63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + + /* + * MDMISC: RALAT kept to the high level of 5. + * MDMISC: consider reducing RALAT if your 528MHz board design allow that. + * Lower RALAT benefits: + * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 + * b. Small performence improvment + */ + {0x021b0018, 0x00211740}, /* MMDC0_MDMISC */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit during + * MMDC set up + */ + {0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x00431023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000047}, /* Chan0 CS0_END */ + {0x021b0000, 0x83180000}, /* MMDC0_MDCTL */ + + {0x021b0890, 0x00400000}, /* MPPDCMPR2 */ + + /* Mode register writes */ + {0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */ + {0x021b001c, 0x04008040}, /* + * MMDC0_MDSCR, ZQ calibration command sent to device + * on CS0 + */ + + {0x021b0020, 0x00007800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + + {0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */ + + {0x021b0404, 0x00011006}, /* + * MMDC0_MAPSR ADOPT power down enabled, MMDC will enter + * automatically to self-refresh while the number of idle + * cycle reached + */ + + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially the + * configuration bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_256mb = { + .ddrc_cfg = ddr_ddrc_cfg_256mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb), +}; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c new file mode 100644 index 00000000000..f5989382f5a --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { + /* + * ============================================================================= + * IOMUX + * ============================================================================= + */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ + + /* Address: */ + {0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using + * Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + {0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ + {0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ + {0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:ISSI + * Device Part Number:IS43TR16640BL-125JBLI + * Clock Freq.: 400MHz + * Density per CS in Gb: 2 + * Chip Selects used:1 + * Number of Banks:8 + * Row address: 14 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit during + * MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration + */ + + /* + * For target board may need to run write leveling calibration to fine tune these settings + */ + {0x021b080c, 0x00000000}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x01440140}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */ + + /* Write calibration */ + {0x021b0850, 0x4040322A}, /* MPWRDLCTL PHY0 */ + + /* + * Read data bit delay: 3 is the reccommended default value, although out of reset value + * is 0 + */ + {0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + /* Write data bit delay: */ + {0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */ + + /* DQS&CLK Duty Cycle */ + {0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */ + + /* Complete calibration by forced measurement: */ + {0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* + * ============================================================================= + * Calibration setup end + * ============================================================================= + */ + + /* MMDC init: */ + {0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x3F435333}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB68E0B63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + + /* + * MDMISC: RALAT kept to the high level of 5. + * MDMISC: consider reducing RALAT if your 528MHz board design allow that. + * Lower RALAT benefits: + * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 + * b. Small performence improvment + */ + {0x021b0018, 0x00211740}, /* MMDC0_MDMISC */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR set the Configuration request bit during + * MMDC set up + */ + {0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x00431023}, /* MMDC0_MDOR */ + {0x021b0040, 0x0000004F}, /* Chan0 CS0_END */ + {0x021b0000, 0x84180000}, /* MMDC0_MDCTL */ + + {0x021b0890, 0x00400000}, /* MPPDCMPR2 */ + + /* Mode register writes */ + {0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */ + {0x021b001c, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */ + + {0x021b0020, 0x00007800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + + {0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */ + + {0x021b0404, 0x00011006}, /* + * MMDC0_MAPSR ADOPT power down enabled, MMDC will enter + * automatically to self-refresh while the number of idle + * cycle reached + */ + + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially the configuration + * bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_512mb = { + .ddrc_cfg = ddr_ddrc_cfg_512mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb), +}; diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c index 724841b5745..c330e4d6d39 100644 --- a/board/bsh/imx6ulz_smm_m2/spl.c +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -13,10 +13,13 @@ #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/boot_mode.h> +#include <linux/delay.h> #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/mx6-ddr.h> +#include "spl_mtypes.h" + #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -31,69 +34,48 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); } -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000028, - .grp_ddrmode_ctl = 0x00020000, - .grp_b0ds = 0x00000028, - .grp_ctlds = 0x00000028, - .grp_b1ds = 0x00000028, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ddr_type = 0x000c0000, -}; +static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info) +{ + int i; + const struct dram_cfg_param *ddrc_cfg = dram_timing_info->ddrc_cfg; + const int ddrc_cfg_num = dram_timing_info->ddrc_cfg_num; + struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000028, - .dram_dqm1 = 0x00000028, - .dram_ras = 0x00000028, - .dram_cas = 0x00000028, - .dram_odt0 = 0x00000028, - .dram_odt1 = 0x00000028, - .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000028, - .dram_sdqs0 = 0x00000028, - .dram_sdqs1 = 0x00000028, - .dram_reset = 0x000c0028, -}; + clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */ + clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */ -static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00000000, - .p0_mpwldectrl1 = 0x00100010, - .p0_mpdgctrl0 = 0x414c014c, - .p0_mpdgctrl1 = 0x00000000, - .p0_mprddlctl = 0x40403a42, - .p0_mpwrdlctl = 0x4040342e, -}; + for (i = 0; i < ddrc_cfg_num; i++) { + debug("Writing 0x%x to register 0x%x\n", ddrc_cfg->val, + ddrc_cfg->reg); + writel(ddrc_cfg->val, ddrc_cfg->reg); + ddrc_cfg++; + } +} -static struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 0, - .cs1_mirror = 0, - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 0, - .ralat = 5, - .walat = 1, - .mif3_mode = 3, - .rst_to_cke = 0x23, /* 33 cycles (JEDEC value for DDR3) - total of 500 us */ - .sde_to_rst = 0x10, /* 14 cycles (JEDEC value for DDR3) - total of 200 us */ - .refsel = 1, - .refr = 3, -}; +static void spl_dram_init(void) +{ + /* Configure memory to maximum supported size for detection */ + ddr_cfg_write(&bsh_dram_timing_512mb); -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 1333, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1350, - .trcmin = 4950, - .trasmin = 3600, -}; + /* Detect memory physically present */ + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); + + /* Reconfigure memory for actual detected size */ + switch (gd->ram_size) { + case SZ_512M: + /* Already configured, nothing to do */ + break; + case SZ_256M: + udelay(1); + ddr_cfg_write(&bsh_dram_timing_256mb); + break; + case SZ_128M: + default: + udelay(1); + ddr_cfg_write(&bsh_dram_timing_128mb); + break; + } +} static void ccgr_init(void) { @@ -108,20 +90,17 @@ static void ccgr_init(void) writel(0xFFFFFFFF, &ccm->CCGR6); } -static void imx6ul_spl_dram_cfg(void) -{ - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - void board_init_f(ulong dummy) { ccgr_init(); + + /* DDR initialization */ + spl_dram_init(); + arch_cpu_init(); timer_init(); setup_iomux_uart(); preloader_console_init(); - imx6ul_spl_dram_cfg(); } void reset_cpu(void) diff --git a/board/bsh/imx6ulz_smm_m2/spl_mtypes.h b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h new file mode 100644 index 00000000000..8da59881c83 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 BSH Hausgeraete GmbH + * + * Written by: Simon Holesch <simon.holesch@bshg.com> + */ + +#ifndef SPL_MTYPES_H +#define SPL_MTYPES_H + +#include <spl.h> + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_timing_info { + const struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; +}; + +extern struct dram_timing_info bsh_dram_timing_128mb; +extern struct dram_timing_info bsh_dram_timing_256mb; +extern struct dram_timing_info bsh_dram_timing_512mb; + +#endif /* SPL_MTYPES_H */ diff --git a/board/bsh/imx8mn_smm_s2/spl.c b/board/bsh/imx8mn_smm_s2/spl.c index 5a77d28cb7e..d36ddd24c63 100644 --- a/board/bsh/imx8mn_smm_s2/spl.c +++ b/board/bsh/imx8mn_smm_s2/spl.c @@ -43,8 +43,6 @@ void spl_board_init(void) int board_early_init_f(void) { - init_uart_clk(3); - if (IS_ENABLED(CONFIG_NAND_MXS)) { init_nand_clk(); } diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 231b9289eea..f96f5c45789 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -115,8 +115,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - init_uart_clk(1); - timer_init(); /* Clear the BSS. */ diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS index 718f89a084a..7393061707d 100644 --- a/board/phytec/phycore_imx93/MAINTAINERS +++ b/board/phytec/phycore_imx93/MAINTAINERS @@ -3,8 +3,6 @@ M: Mathieu Othacehe <m.othacehe@gmail.com> R: Christoph Stoidner <c.stoidner@phytec.de> W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ S: Maintained -F: arch/arm/dts/imx93-phyboard-segin.dts -F: arch/arm/dts/imx93-phycore-som.dtsi F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi F: board/phytec/phycore_imx93/ F: board/phytec/common/imx93_som_detection.c diff --git a/common/spl/Kconfig b/common/spl/Kconfig index aa3a85eea54..77cf04d38ed 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -974,6 +974,21 @@ config SPL_NAND_SUPPORT This enables the drivers in drivers/mtd/nand/raw as part of an SPL build. +config SPL_NAND_RAW_U_BOOT_USE_SECTOR + bool "NAND raw mode: by sector" + depends on SPL_NAND_SUPPORT + select SPL_LOAD_BLOCK + help + Use sector number for specifying U-Boot location on NAND in + raw mode. + +config SPL_NAND_RAW_U_BOOT_SECTOR + hex "Address on the NAND to load U-Boot from" + depends on SPL_NAND_RAW_U_BOOT_USE_SECTOR + help + Address on the NAND to load U-Boot from, when the NAND is being used + in raw mode. Units: NAND disk sectors (1 sector = 512 bytes). + config SPL_NAND_RAW_ONLY bool "Support to boot only raw u-boot.bin images" depends on SPL_NAND_SUPPORT diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig index 15a3ec5c627..436bfb78cc2 100644 --- a/configs/imx6ulz_smm_m2_defconfig +++ b/configs/imx6ulz_smm_m2_defconfig @@ -64,6 +64,8 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -75,3 +77,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x877fffc0 CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 9ffcd3b221c..206d216394d 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -15,7 +15,6 @@ CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x950000 @@ -47,6 +46,8 @@ CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_RAW_U_BOOT_USE_SECTOR=y +CONFIG_SPL_NAND_RAW_U_BOOT_SECTOR=0x300 CONFIG_SPL_NAND_BASE=y CONFIG_SPL_NAND_IDENT=y CONFIG_SPL_POWER=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index d2010d13b8c..ef486f51eee 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x980000 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x950000 diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 7187fd70833..66a431244b0 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -12,7 +12,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x700000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx93-phyboard-segin" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-phyboard-segin" CONFIG_AHAB_BOOT=y CONFIG_TARGET_PHYCORE_IMX93=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 8f7a821ebf3..1d95d2bff27 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -217,13 +217,6 @@ static int jr_enqueue(uint32_t *desc_addr, jr->head = (head + 1) & (jr->size - 1); - /* Invalidate output ring */ - start = (unsigned long)jr->output_ring & - ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN((unsigned long)jr->output_ring + jr->op_size, - ARCH_DMA_MINALIGN); - invalidate_dcache_range(start, end); - sec_out32(®s->irja, 1); return 0; @@ -243,6 +236,7 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam) #else uint32_t *addr; #endif + unsigned long start, end; while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail, jr->size)) { @@ -250,6 +244,11 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam) found = 0; caam_dma_addr_t op_desc; + + /* Invalidate output ring */ + start = (unsigned long)jr->output_ring & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)jr->output_ring + jr->op_size, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); #ifdef CONFIG_CAAM_64BIT /* Read the 64 bit Descriptor address from Output Ring. * The 32 bit hign and low part of the address will @@ -283,8 +282,13 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam) } /* Error condition if match not found */ - if (!found) + if (!found) { + int slots_full = sec_in32(®s->orsf); + + jr->tail = (jr->tail + slots_full) & (jr->size - 1); + sec_out32(®s->orjr, slots_full); return -1; + } jr->info[idx].op_done = 1; callback = (void *)jr->info[idx].callback; @@ -296,14 +300,14 @@ static int jr_dequeue(int sec_idx, struct caam_regs *caam) */ if (idx == tail) do { + jr->info[tail].op_done = 0; tail = (tail + 1) & (jr->size - 1); } while (jr->info[tail].op_done); jr->tail = tail; - jr->read_idx = (jr->read_idx + 1) & (jr->size - 1); + sec_out32(®s->orjr, 1); - jr->info[idx].op_done = 0; callback(status, arg); } @@ -378,7 +382,6 @@ static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) jr->head = 0; jr->tail = 0; - jr->read_idx = 0; jr->write_idx = 0; memset(jr->info, 0, sizeof(jr->info)); memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t)); diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index b136cd8d05a..8d5ca03e501 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -83,10 +83,6 @@ struct jobring { * in-order job completion */ int tail; - /* Read index of the output ring. It may not match with tail in case - * of out of order completetion - */ - int read_idx; /* Write index to input ring. Would be always equal to head */ int write_idx; /* Size of the rings. */ diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 44a3fc02e8a..87aede218d1 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -60,10 +60,8 @@ BOOTENV /* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_128M - -#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE |