diff options
55 files changed, 387 insertions, 2149 deletions
@@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -VERSION = 2024 -PATCHLEVEL = 10 +VERSION = 2025 +PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = # *DOCUMENTATION* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 03ed3cbeb79..aeccfa93fc5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1165,14 +1165,6 @@ dtb-$(CONFIG_STM32MP25X) += \ dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ k3-am654-r5-base-board.dtb \ - k3-am65-iot2050-spl.dtb \ - k3-am6528-iot2050-basic.dtb \ - k3-am6528-iot2050-basic-pg2.dtb \ - k3-am6548-iot2050-advanced.dtb \ - k3-am6548-iot2050-advanced-pg2.dtb \ - k3-am6548-iot2050-advanced-m2.dtb \ - k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \ - k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \ k3-am654-icssg2.dtbo dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \ diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi index 3a6db91e132..f49d6f262f2 100644 --- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi @@ -84,12 +84,12 @@ }; fdt-0 { - description = "k3-am65-iot2050-spl.dtb"; + description = "ti/k3-am6528-iot2050-basic.dtb"; type = "flat_dt"; arch = "arm"; compression = "none"; blob-ext { - filename = "spl/dts/k3-am65-iot2050-spl.dtb"; + filename = "spl/dts/ti/k3-am6528-iot2050-basic.dtb"; }; }; }; @@ -205,10 +205,10 @@ }; fit@380000 { - fit,fdt-list-val = "k3-am6528-iot2050-basic", "k3-am6548-iot2050-advanced"; + fit,fdt-list-val = "ti/k3-am6528-iot2050-basic", "ti/k3-am6548-iot2050-advanced"; configurations { - default = "k3-am6528-iot2050-basic"; + default = "ti/k3-am6528-iot2050-basic"; @config-SEQ { loadables = #ifdef CONFIG_WDT_K3_RTI_FW_FILE @@ -229,7 +229,10 @@ }; fit@380000 { - fit,fdt-list-val = "k3-am6528-iot2050-basic-pg2", "k3-am6548-iot2050-advanced-pg2", "k3-am6548-iot2050-advanced-m2"; + fit,fdt-list-val = "ti/k3-am6528-iot2050-basic-pg2", + "ti/k3-am6548-iot2050-advanced-pg2", + "ti/k3-am6548-iot2050-advanced-m2", + "ti/k3-am6548-iot2050-advanced-sm"; images { bkey-usb3-overlay { @@ -239,7 +242,7 @@ arch = "arm64"; compression = "none"; blob-ext { - filename = "k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo"; + filename = "ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo"; }; hash { algo = "sha256"; @@ -253,7 +256,7 @@ arch = "arm64"; compression = "none"; blob-ext { - filename = "k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo"; + filename = "ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtbo"; }; hash { algo = "sha256"; @@ -262,7 +265,7 @@ }; configurations { - default = "k3-am6528-iot2050-basic-pg2"; + default = "ti/k3-am6528-iot2050-basic-pg2"; @config-SEQ { loadables = #ifdef CONFIG_WDT_K3_RTI_FW_FILE diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi deleted file mode 100644 index 51f902fa35a..00000000000 --- a/arch/arm/dts/k3-am65-iot2050-common-pg1.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2021 - * - * Authors: - * Jan Kiszka <jan.kiszka@siemens.com> - * - * Common bits of the IOT2050 Basic and Advanced variants, PG1 - */ - -&dss { - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; -}; - -&serdes0 { - status = "disabled"; -}; - -&sdhci1 { - no-1-8-v; -}; - -&tx_pru0_0 { - status = "disabled"; -}; - -&tx_pru0_1 { - status = "disabled"; -}; - -&tx_pru1_0 { - status = "disabled"; -}; - -&tx_pru1_1 { - status = "disabled"; -}; - -&tx_pru2_0 { - status = "disabled"; -}; - -&tx_pru2_1 { - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi deleted file mode 100644 index e9419c4fe60..00000000000 --- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2021 - * - * Authors: - * Chao Zeng <chao.zeng@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * Common bits of the IOT2050 Basic and Advanced variants, PG2 - */ - -&main_pmx0 { - cp2102n_reset_pin_default: cp2102n-reset-default-pins { - pinctrl-single,pins = < - /* (AF12) GPIO1_24, used as cp2102 reset */ - AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) - >; - }; -}; - -&main_gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp2102n_reset_pin_default>; - gpio-line-names = - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "CP2102N-RESET"; -}; - -&dss { - /* Workaround needed to get DP clock of 154Mhz */ - assigned-clocks = <&k3_clks 67 0>; -}; - -&serdes0 { - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; -}; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ - phys = <&serdes0 PHY_TYPE_USB3 0>; - phy-names = "usb3-phy"; -}; - -&usb0 { - maximum-speed = "super-speed"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; -}; diff --git a/arch/arm/dts/k3-am65-iot2050-common.dtsi b/arch/arm/dts/k3-am65-iot2050-common.dtsi deleted file mode 100644 index fa7178144b8..00000000000 --- a/arch/arm/dts/k3-am65-iot2050-common.dtsi +++ /dev/null @@ -1,738 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2021 - * - * Authors: - * Le Jin <le.jin@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2 - */ - -#include "k3-am654.dtsi" -#include <dt-bindings/phy/phy.h> - -/ { - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &main_i2c0; - i2c3 = &main_i2c1; - i2c4 = &main_i2c2; - i2c5 = &main_i2c3; - spi0 = &mcu_spi0; - mmc0 = &sdhci1; - mmc1 = &sdhci0; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: secure-ddr@9e800000 { - reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0 0xa0000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0 0xa0100000 0 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a2000000 { - reg = <0x00 0xa2000000 0x00 0x00200000>; - alignment = <0x1000>; - no-map; - }; - - /* To reserve the power-on(PON) reason for watchdog reset */ - wdt_reset_memory_region: wdt-memory@a2200000 { - reg = <0x00 0xa2200000 0x00 0x00001000>; - no-map; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default>; - - status-led-red { - gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>; - panic-indicator; - }; - - status-led-green { - gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>; - }; - - user-led1-red { - gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>; - }; - - user-led1-green { - gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>; - }; - - user-led2-red { - gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - user-led2-green { - gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>; - }; - }; - - dp_refclk: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; -}; - -&wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - /* (AC7) WKUP_I2C0_SCL */ - AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) - /* (AD6) WKUP_I2C0_SDA */ - AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) - >; - }; - - mcu_i2c0_pins_default: mcu-i2c0-default-pins { - pinctrl-single,pins = < - /* (AD8) MCU_I2C0_SCL */ - AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) - /* (AD7) MCU_I2C0_SDA */ - AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) - >; - }; - - arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { - pinctrl-single,pins = < - /* (R2) WKUP_GPIO0_21 */ - AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) - >; - }; - - push_button_pins_default: push-button-default-pins { - pinctrl-single,pins = < - /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ - AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) - >; - }; - - arduino_uart_pins_default: arduino-uart-default-pins { - pinctrl-single,pins = < - /* (P4) MCU_UART0_RXD */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) - /* (P5) MCU_UART0_TXD */ - AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) - >; - }; - - arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins { - pinctrl-single,pins = < - /* (P1) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7) - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7) - >; - }; - - arduino_io_oe_pins_default: arduino-io-oe-default-pins { - pinctrl-single,pins = < - /* (N4) WKUP_GPIO0_34 */ - AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) - /* (M2) WKUP_GPIO0_36 */ - AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) - /* (M3) WKUP_GPIO0_37 */ - AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) - /* (M4) WKUP_GPIO0_38 */ - AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) - /* (M1) WKUP_GPIO0_41 */ - AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - /* (V1) MCU_OSPI0_CLK */ - AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) - /* (U2) MCU_OSPI0_DQS */ - AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) - /* (U4) MCU_OSPI0_D0 */ - AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) - /* (U5) MCU_OSPI0_D1 */ - AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) - /* (R4) MCU_OSPI0_CSn0 */ - AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) - >; - }; - - db9_com_mode_pins_default: db9-com-mode-default-pins { - pinctrl-single,pins = < - /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */ - AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7) - /* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */ - AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7) - /* (AC1) WKUP_GPIO0_7, used as uart0 term */ - AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7) - /* (AC2) WKUP_GPIO0_6, used as uart0 en */ - AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7) - >; - }; - - leds_pins_default: leds-default-pins { - pinctrl-single,pins = < - /* (T2) WKUP_GPIO0_17, used as user led1 red */ - AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7) - /* (R3) WKUP_GPIO0_22, used as user led1 green */ - AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7) - /* (R5) WKUP_GPIO0_24, used as status led red */ - AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7) - /* (N2) WKUP_GPIO0_32, used as status led green */ - AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7) - >; - }; - - mcu_spi0_pins_default: mcu-spi0-default-pins { - pinctrl-single,pins = < - /* (Y1) MCU_SPI0_CLK */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) - /* (Y3) MCU_SPI0_D0 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) - /* (Y2) MCU_SPI0_D1 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) - /* (Y4) MCU_SPI0_CS0 */ - AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) - >; - }; - - minipcie_pins_default: minipcie-default-pins { - pinctrl-single,pins = < - /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ - AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) - >; - }; -}; - -&main_pmx0 { - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ - AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */ - AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */ - AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */ - AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ - AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ - AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ - AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ - AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ - AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ - AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ - AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */ - >; - }; - - usb0_pins_default: usb0-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ - >; - }; - - usb1_pins_default: usb1-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ - >; - }; - - arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */ - >; - }; - - dss_vout1_pins_default: dss-vout1-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ - AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ - AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ - AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ - AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ - AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ - AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ - AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ - AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ - AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ - AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ - AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ - AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ - AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ - AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ - AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ - AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ - AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ - AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ - AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ - AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ - AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ - AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ - AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ - AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ - AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ - AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ - AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ - >; - }; - - dp_pins_default: dp-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ - >; - }; - - main_i2c2_pins_default: main-i2c2-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ - AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ - >; - }; -}; - -&main_pmx1 { - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ - AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ - AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ - >; - }; - - ecap0_pins_default: ecap0-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; -}; - -&main_uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&arduino_uart_pins_default>; -}; - -&main_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>; - gpio-line-names = - "main_gpio0-base", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "IO4", "", "IO5", "", "", "IO6", "", - "", "", "", "IO7", "", "", "", "", "IO8", "", - "", "IO9"; -}; - -&wkup_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = - <&arduino_io_d2_to_d3_pins_default>, - <&arduino_i2c_aio_switch_pins_default>, - <&arduino_io_oe_pins_default>, - <&push_button_pins_default>, - <&db9_com_mode_pins_default>; - gpio-line-names = - /* 0..9 */ - "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", - "UART0-enable", "UART0-terminate", "", "WIFI-disable", - /* 10..19 */ - "", "", "", "", "", "", "", "", "", "", - /* 20..29 */ - "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", - /* 30..39 */ - "IO1", "IO2", "", "IO3", "IO17-direction", "A5", - "IO16-direction", "IO15-direction", "IO14-direction", "A3", - /* 40..49 */ - "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", - "IO11", - /* 50..51 */ - "IO12", "IO10"; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; -}; - -&mcu_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_i2c0_pins_default>; - clock-frequency = <400000>; - - psu: regulator@60 { - compatible = "ti,tps62363"; - reg = <0x60>; - regulator-name = "tps62363-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - ti,enable-vout-discharge; - }; - - /* D4200 */ - pcal9535_1: gpio@20 { - compatible = "nxp,pcal9535"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", - "A5-pull", "", "", - "IO14-enable", "IO15-enable", "IO16-enable", - "IO17-enable", "IO18-enable", "IO19-enable"; - }; - - /* D4201 */ - pcal9535_2: gpio@21 { - compatible = "nxp,pcal9535"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "IO0-direction", "IO1-direction", "IO2-direction", - "IO3-direction", "IO4-direction", "IO5-direction", - "IO6-direction", "IO7-direction", - "IO8-direction", "IO9-direction", "IO10-direction", - "IO11-direction", "IO12-direction", "IO13-direction", - "IO19-direction"; - }; - - /* D4202 */ - pcal9535_3: gpio@25 { - compatible = "nxp,pcal9535"; - reg = <0x25>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", - "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", - "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", - "IO12-pull", "IO13-pull"; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - eeprom: eeprom@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - pagesize = <16>; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; -}; - -&main_i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c2_pins_default>; - clock-frequency = <400000>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - #address-cells = <1>; - #size-cells = <0>; - - edp-bridge@f { - compatible = "toshiba,tc358767"; - reg = <0x0f>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_pins_default>; - reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; - - clock-names = "ref"; - clocks = <&dp_refclk>; - - toshiba,hpd-pin = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; -}; - -&mcu_cpsw { - status = "disabled"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins_default>; -}; - -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_default>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_default>; - dr_mode = "host"; -}; - -&mcu_spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_spi0_pins_default>; - - #address-cells = <1>; - #size-cells = <0>; - ti,pindir-d0-out-d1-in; -}; - -&tscadc1 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5>; - }; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - spi-max-frequency = <50000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - seboot@0 { - label = "seboot"; - reg = <0x0 0x180000>; /* 1.5M */ - }; - - tispl@180000 { - label = "tispl"; - reg = <0x180000 0x200000>; /* 2M */ - }; - - u-boot@380000 { - label = "u-boot"; - reg = <0x380000 0x300000>; /* 3M */ - }; - - env@680000 { - label = "env"; - reg = <0x680000 0x20000>; /* 128K */ - }; - - env-backup@6a0000 { - label = "env.backup"; - reg = <0x6a0000 0x20000>; /* 128K */ - }; - - otpcmd@6c0000 { - label = "otpcmd"; - reg = <0x6c0000 0x10000>; /* 64K */ - }; - - unused@6d0000 { - label = "unused"; - reg = <0x6d0000 0x7b0000>; /* 7872K */ - }; - - seboot-backup@e80000 { - label = "seboot.backup"; - reg = <0xe80000 0x180000>; /* 1.5M */ - }; - }; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout1_pins_default>; - - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - - dpi_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; -}; - -&pcie1_rc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_pins_default>; - - num-lanes = <1>; - phys = <&serdes1 PHY_TYPE_PCIE 0>; - phy-names = "pcie-phy0"; - reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; -}; - -&mcu_r5fss0_core1 { - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; -}; - -&mcu_rti1 { - memory-region = <&wdt_reset_memory_region>; -}; diff --git a/arch/arm/dts/k3-am65-iot2050-spl.dts b/arch/arm/dts/k3-am65-iot2050-spl.dts deleted file mode 100644 index 4e668fa3e03..00000000000 --- a/arch/arm/dts/k3-am65-iot2050-spl.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2021 - * - * Authors: - * Jan Kiszka <jan.kiszka@siemens.com> - */ - -/dts-v1/; - -#include "k3-am65-iot2050-common.dtsi" -#include "k3-am65-iot2050-common-u-boot.dtsi" - -/ { - compatible = "siemens,iot2050", "ti,am654"; - model = "Siemens IOT2050"; -}; diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi deleted file mode 100644 index 5ab434c02ab..00000000000 --- a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2021 - * - * Authors: - * Le Jin <le.jin@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * Common bits of the IOT2050 Basic variant, PG1 and PG2 - */ - -#include "k3-am65-iot2050-common.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 1G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; - }; - - cpus { - cpu-map { - /delete-node/ cluster1; - }; - /delete-node/ cpu@100; - /delete-node/ cpu@101; - }; - - /delete-node/ l2-cache1; -}; - -/* eMMC */ -&sdhci0 { - status = "disabled"; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ - AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ - AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ - AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ - AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */ - AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */ - AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */ - AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */ - >; - }; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -&mcu_r5fss0 { - /* lock-step mode not supported on Basic boards */ - ti,cluster-mode = <0>; -}; diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts b/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts deleted file mode 100644 index c62549a4b43..00000000000 --- a/arch/arm/dts/k3-am6528-iot2050-basic-pg2.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2021 - * - * Authors: - * Le Jin <le.jin@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2 - * 1 GB RAM, no eMMC, main_uart0 on connector X30 - * - * Product homepage: - * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html - */ - -/dts-v1/; - -#include "k3-am6528-iot2050-basic-common.dtsi" -#include "k3-am65-iot2050-common-pg2.dtsi" - -/ { - compatible = "siemens,iot2050-basic-pg2", "ti,am654"; - model = "SIMATIC IOT2050 Basic PG2"; -}; diff --git a/arch/arm/dts/k3-am6528-iot2050-basic.dts b/arch/arm/dts/k3-am6528-iot2050-basic.dts deleted file mode 100644 index 87928ff2821..00000000000 --- a/arch/arm/dts/k3-am6528-iot2050-basic.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2021 - * - * Authors: - * Le Jin <le.jin@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1 - * 1 GB RAM, no eMMC, main_uart0 on connector X30 - * - * Product homepage: - * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html - */ - -/dts-v1/; - -#include "k3-am6528-iot2050-basic-common.dtsi" -#include "k3-am65-iot2050-common-pg1.dtsi" - -/ { - compatible = "siemens,iot2050-basic", "ti,am654"; - model = "SIMATIC IOT2050 Basic"; -}; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi deleted file mode 100644 index be55494b1f3..00000000000 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2021 - * - * Authors: - * Le Jin <le.jin@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * Common bits of the IOT2050 Advanced variant, PG1 and PG2 - */ - -/dts-v1/; - -#include "k3-am65-iot2050-common.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; -}; - -&main_pmx0 { - main_mmc0_pins_default: main-mmc0-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ - AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ - AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ - AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ - AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ - AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ - AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ - AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ - AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ - AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ - AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */ - AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ - AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ - >; - }; -}; - -/* eMMC */ -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - bus-width = <8>; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts deleted file mode 100644 index 774eb14ac90..00000000000 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2.dts +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2023 - * - * Authors: - * Chao Zeng <chao.zeng@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product - * Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 - * - * Product homepage: - * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html - */ - -#include "k3-am6548-iot2050-advanced-common.dtsi" -#include "k3-am65-iot2050-common-pg2.dtsi" - -/ { - compatible = "siemens,iot2050-advanced-m2", "ti,am654"; - model = "SIMATIC IOT2050 Advanced M2"; -}; - -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; - -&main_pmx0 { - main_m2_enable_pins_default: main-m2-enable-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ - >; - }; - - main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ - >; - }; - - main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */ - AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */ - >; - }; - - main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */ - AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */ - AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */ - >; - }; -}; - -&main_pmx1 { - main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */ - AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */ - >; - }; -}; - -&main_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = - <&main_m2_pcie_mux_control>, - <&arduino_io_d4_to_d9_pins_default>; -}; - -&main_gpio1 { - pinctrl-names = "default"; - pinctrl-0 = - <&main_m2_enable_pins_default>, - <&main_pmx0_m2_config_pins_default>, - <&main_pmx1_m2_config_pins_default>, - <&cp2102n_reset_pin_default>; -}; - -/* - * Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only. - * Firmware switches to other modes via device tree overlays. - */ - -&serdes0 { - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; -}; - -&pcie0_rc { - pinctrl-names = "default"; - pinctrl-0 = <&main_bkey_pcie_reset>; - - num-lanes = <2>; - phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; - phy-names = "pcie-phy0","pcie-phy1"; - reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie1_rc { - status = "disabled"; -}; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ - /delete-property/ phys; - /delete-property/ phy-names; -}; - -&usb0 { - maximum-speed = "high-speed"; - /delete-property/ snps,dis-u1-entry-quirk; - /delete-property/ snps,dis-u2-entry-quirk; -}; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts deleted file mode 100644 index f00dc86d01b..00000000000 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2021 - * - * Authors: - * Le Jin <le.jin@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2 - * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 - * - * Product homepage: - * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html - */ - -/dts-v1/; - -#include "k3-am6548-iot2050-advanced-common.dtsi" -#include "k3-am65-iot2050-common-pg2.dtsi" - -/ { - compatible = "siemens,iot2050-advanced-pg2", "ti,am654"; - model = "SIMATIC IOT2050 Advanced PG2"; -}; - -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi new file mode 120000 index 00000000000..859776d3ffe --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-sm-u-boot.dtsi @@ -0,0 +1 @@ +k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced.dts b/arch/arm/dts/k3-am6548-iot2050-advanced.dts deleted file mode 100644 index 077f165bdc6..00000000000 --- a/arch/arm/dts/k3-am6548-iot2050-advanced.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) Siemens AG, 2018-2021 - * - * Authors: - * Le Jin <le.jin@siemens.com> - * Jan Kiszka <jan.kiszka@siemens.com> - * - * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1 - * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 - * - * Product homepage: - * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html - */ - -/dts-v1/; - -#include "k3-am6548-iot2050-advanced-common.dtsi" -#include "k3-am65-iot2050-common-pg1.dtsi" - -/ { - compatible = "siemens,iot2050-advanced", "ti,am654"; - model = "SIMATIC IOT2050 Advanced"; -}; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa371027d45..043d963f634 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -21,7 +21,7 @@ config TARGET_OPENPITON_RISCV64 bool "Support RISC-V cores on OpenPiton SoC" config TARGET_QEMU_VIRT - bool "Support QEMU Virt Board" + bool "Support QEMU Virt & RVVM Boards" select BOARD_LATE_INIT config TARGET_SIFIVE_UNLEASHED @@ -319,6 +319,10 @@ config RISCV_ISA_A help Adds "A" to the ISA string passed to the compiler. +config RISCV_ISA_ZICBOM + bool "Zicbom support" + depends on !SYS_DISABLE_DCACHE_OPS + config DMA_ADDR_T_64BIT bool default y if 64BIT diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f3dfd751cb4..bf32ead01b0 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb -dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi deleted file mode 100644 index 1069134f2e1..00000000000 --- a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -/ { - compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", - "microchip,mpfs"; - - core_pwm0: pwm@40000000 { - compatible = "microchip,corepwm-rtl-v4"; - reg = <0x0 0x40000000 0x0 0xF0>; - microchip,sync-update-mask = /bits/ 32 <0>; - #pwm-cells = <3>; - clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; - status = "disabled"; - }; - - i2c2: i2c@40000200 { - compatible = "microchip,corei2c-rtl-v7"; - reg = <0x0 0x40000200 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; - interrupt-parent = <&plic>; - interrupts = <122>; - clock-frequency = <100000>; - status = "disabled"; - }; - - pcie: pcie@3000000000 { - compatible = "microchip,pcie-host-1.0"; - #address-cells = <0x3>; - #interrupt-cells = <0x1>; - #size-cells = <0x2>; - device_type = "pci"; - reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; - bus-range = <0x0 0x7f>; - interrupt-parent = <&plic>; - interrupts = <119>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask = <0 0 0 7>; - clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; - clock-names = "fic1", "fic3"; - ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; - dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; - msi-parent = <&pcie>; - msi-controller; - status = "disabled"; - pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - refclk_ccc: cccrefclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; -}; - -&ccc_nw { - clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, - <&refclk_ccc>, <&refclk_ccc>; - clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", - "dll0_ref", "dll1_ref"; - status = "okay"; -}; diff --git a/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi deleted file mode 100644 index f60283fb6b3..00000000000 --- a/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2020 Microchip Technology Inc. - * Padmarao Begari <padmarao.begari@microchip.com> - */ - -/ { - aliases { - cpu1 = &cpu1; - cpu2 = &cpu2; - cpu3 = &cpu3; - cpu4 = &cpu4; - }; -}; diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts deleted file mode 100644 index 8aa5fb17d64..00000000000 --- a/arch/riscv/dts/mpfs-icicle-kit.dts +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021-2022 Microchip Technology Inc. - * Padmarao Begari <padmarao.begari@microchip.com> - */ - -/dts-v1/; - -#include "mpfs.dtsi" -#include "mpfs-icicle-kit-fabric.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> - -/* Clock frequency (in Hz) of the rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", - "microchip,mpfs"; - - aliases { - ethernet0 = &mac1; - serial0 = &mmuart0; - serial1 = &mmuart1; - serial2 = &mmuart2; - serial3 = &mmuart3; - serial4 = &mmuart4; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - cpus { - timebase-frequency = <RTCCLK_FREQ>; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_RED>; - label = "led1"; - }; - - led-2 { - gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_RED>; - label = "led2"; - }; - - led-3 { - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_AMBER>; - label = "led3"; - }; - - led-4 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_AMBER>; - label = "led4"; - }; - }; - - ddrc_cache_lo: memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - status = "okay"; - }; - - ddrc_cache_hi: memory@1040000000 { - device_type = "memory"; - reg = <0x10 0x40000000 0x0 0x40000000>; - status = "okay"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hss_payload: region@BFC00000 { - reg = <0x0 0xBFC00000 0x0 0x400000>; - no-map; - }; - }; -}; - -&core_pwm0 { - status = "okay"; -}; - -&gpio2 { - interrupts = <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mac0 { - phy-mode = "sgmii"; - phy-handle = <&phy0>; - status = "enabled"; -}; - -&mac1 { - phy-mode = "sgmii"; - phy-handle = <&phy1>; - status = "okay"; - - phy1: ethernet-phy@9 { - reg = <9>; - }; - - phy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -&mbox { - status = "okay"; -}; - -&mmc { - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&mmuart1 { - status = "okay"; -}; - -&mmuart2 { - status = "okay"; -}; - -&mmuart3 { - status = "okay"; -}; - -&mmuart4 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&qspi { - status = "okay"; -}; - -&refclk { - clock-frequency = <125000000>; -}; - -&refclk_ccc { - clock-frequency = <50000000>; -}; - -&rtc { - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; - -&syscontroller { - status = "okay"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/riscv/dts/mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi deleted file mode 100644 index 6012a285070..00000000000 --- a/arch/riscv/dts/mpfs.dtsi +++ /dev/null @@ -1,511 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#include "dt-bindings/clock/microchip-mpfs-clock.h" - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "Microchip PolarFire SoC"; - compatible = "microchip,mpfs"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "sifive,e51", "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; - clocks = <&clkcfg CLK_CPU>; - status = "disabled"; - - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu1: cpu@1 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <1>; - riscv,isa = "rv64imafdc"; - clocks = <&clkcfg CLK_CPU>; - tlb-split; - next-level-cache = <&cctrllr>; - status = "okay"; - - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu2: cpu@2 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <2>; - riscv,isa = "rv64imafdc"; - clocks = <&clkcfg CLK_CPU>; - tlb-split; - next-level-cache = <&cctrllr>; - status = "okay"; - - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu3: cpu@3 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <3>; - riscv,isa = "rv64imafdc"; - clocks = <&clkcfg CLK_CPU>; - tlb-split; - next-level-cache = <&cctrllr>; - status = "okay"; - - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu4: cpu@4 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <4>; - riscv,isa = "rv64imafdc"; - clocks = <&clkcfg CLK_CPU>; - tlb-split; - next-level-cache = <&cctrllr>; - status = "okay"; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - - core2 { - cpu = <&cpu2>; - }; - - core3 { - cpu = <&cpu3>; - }; - - core4 { - cpu = <&cpu4>; - }; - }; - }; - }; - - refclk: mssrefclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - syscontroller: syscontroller { - compatible = "microchip,mpfs-sys-controller"; - mboxes = <&mbox 0>; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - cctrllr: cache-controller@2010000 { - compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; - reg = <0x0 0x2010000 0x0 0x1000>; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic>; - interrupts = <1>, <3>, <4>, <2>; - }; - - clint: clint@2000000 { - compatible = "sifive,fu540-c000-clint", "sifive,clint0"; - reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>; - }; - - plic: interrupt-controller@c000000 { - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts-extended = <&cpu0_intc 11>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>; - riscv,ndev = <186>; - }; - - pdma: dma-controller@3000000 { - compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic>; - interrupts = <5 6>, <7 8>, <9 10>, <11 12>; - dma-channels = <4>; - #dma-cells = <1>; - }; - - clkcfg: clkcfg@20002000 { - compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks = <&refclk>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - ccc_se: clock-controller@38010000 { - compatible = "microchip,mpfs-ccc"; - reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, - <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; - #clock-cells = <1>; - status = "disabled"; - }; - - ccc_ne: clock-controller@38040000 { - compatible = "microchip,mpfs-ccc"; - reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, - <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; - #clock-cells = <1>; - status = "disabled"; - }; - - ccc_nw: clock-controller@38100000 { - compatible = "microchip,mpfs-ccc"; - reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, - <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; - #clock-cells = <1>; - status = "disabled"; - }; - - ccc_sw: clock-controller@38400000 { - compatible = "microchip,mpfs-ccc"; - reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, - <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; - #clock-cells = <1>; - status = "disabled"; - }; - - mmuart0: serial@20000000 { - compatible = "ns16550a"; - reg = <0x0 0x20000000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <90>; - current-speed = <115200>; - clocks = <&clkcfg CLK_MMUART0>; - status = "disabled"; /* Reserved for the HSS */ - }; - - mmuart1: serial@20100000 { - compatible = "ns16550a"; - reg = <0x0 0x20100000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <91>; - current-speed = <115200>; - clocks = <&clkcfg CLK_MMUART1>; - status = "disabled"; - }; - - mmuart2: serial@20102000 { - compatible = "ns16550a"; - reg = <0x0 0x20102000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <92>; - current-speed = <115200>; - clocks = <&clkcfg CLK_MMUART2>; - status = "disabled"; - }; - - mmuart3: serial@20104000 { - compatible = "ns16550a"; - reg = <0x0 0x20104000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <93>; - current-speed = <115200>; - clocks = <&clkcfg CLK_MMUART3>; - status = "disabled"; - }; - - mmuart4: serial@20106000 { - compatible = "ns16550a"; - reg = <0x0 0x20106000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <94>; - clocks = <&clkcfg CLK_MMUART4>; - current-speed = <115200>; - status = "disabled"; - }; - - /* Common node entry for emmc/sd */ - mmc: mmc@20008000 { - compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; - reg = <0x0 0x20008000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <88>; - clocks = <&clkcfg CLK_MMC>; - max-frequency = <200000000>; - status = "disabled"; - }; - - spi0: spi@20108000 { - compatible = "microchip,mpfs-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20108000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <54>; - clocks = <&clkcfg CLK_SPI0>; - status = "disabled"; - }; - - spi1: spi@20109000 { - compatible = "microchip,mpfs-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20109000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <55>; - clocks = <&clkcfg CLK_SPI1>; - status = "disabled"; - }; - - qspi: spi@21000000 { - compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21000000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <85>; - clocks = <&clkcfg CLK_QSPI>; - status = "disabled"; - }; - - i2c0: i2c@2010a000 { - compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; - reg = <0x0 0x2010a000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&plic>; - interrupts = <58>; - clocks = <&clkcfg CLK_I2C0>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c1: i2c@2010b000 { - compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; - reg = <0x0 0x2010b000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&plic>; - interrupts = <61>; - clocks = <&clkcfg CLK_I2C1>; - clock-frequency = <100000>; - status = "disabled"; - }; - - can0: can@2010c000 { - compatible = "microchip,mpfs-can"; - reg = <0x0 0x2010c000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN0>; - interrupt-parent = <&plic>; - interrupts = <56>; - status = "disabled"; - }; - - can1: can@2010d000 { - compatible = "microchip,mpfs-can"; - reg = <0x0 0x2010d000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN1>; - interrupt-parent = <&plic>; - interrupts = <57>; - status = "disabled"; - }; - - mac0: ethernet@20110000 { - compatible = "microchip,mpfs-macb", "cdns,macb"; - reg = <0x0 0x20110000 0x0 0x2000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&plic>; - interrupts = <64>, <65>, <66>, <67>, <68>, <69>; - local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; - resets = <&clkcfg CLK_MAC0>; - status = "disabled"; - }; - - mac1: ethernet@20112000 { - compatible = "microchip,mpfs-macb", "cdns,macb"; - reg = <0x0 0x20112000 0x0 0x2000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&plic>; - interrupts = <70>, <71>, <72>, <73>, <74>, <75>; - local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; - resets = <&clkcfg CLK_MAC1>; - status = "disabled"; - }; - - gpio0: gpio@20120000 { - compatible = "microchip,mpfs-gpio"; - reg = <0x0 0x20120000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupt-controller; - #interrupt-cells = <1>; - clocks = <&clkcfg CLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@20121000 { - compatible = "microchip,mpfs-gpio"; - reg = <0x0 0x20121000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupt-controller; - #interrupt-cells = <1>; - clocks = <&clkcfg CLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - gpio2: gpio@20122000 { - compatible = "microchip,mpfs-gpio"; - reg = <0x0 0x20122000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupt-controller; - #interrupt-cells = <1>; - clocks = <&clkcfg CLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - rtc: rtc@20124000 { - compatible = "microchip,mpfs-rtc"; - reg = <0x0 0x20124000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <80>, <81>; - clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; - clock-names = "rtc", "rtcref"; - status = "disabled"; - }; - - usb: usb@20201000 { - compatible = "microchip,mpfs-musb"; - reg = <0x0 0x20201000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <86>, <87>; - clocks = <&clkcfg CLK_USB>; - interrupt-names = "dma","mc"; - status = "disabled"; - }; - - mbox: mailbox@37020000 { - compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; - interrupt-parent = <&plic>; - interrupts = <96>; - #mbox-cells = <1>; - status = "disabled"; - }; - }; -}; diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 48ee1154956..4050ce2f051 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -20,7 +20,7 @@ cpus: cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <102000000>; + timebase-frequency = <100000000>; cpu_0: cpu@0 { compatible = "amd,mbv32", "riscv"; device_type = "cpu"; @@ -28,7 +28,7 @@ riscv,isa = "rv32imafdc"; i-cache-size = <32768>; d-cache-size = <32768>; - clock-frequency = <102000000>; + clock-frequency = <100000000>; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; @@ -46,15 +46,15 @@ stdout-path = "serial0:115200n8"; }; - memory@20000000 { + memory@80000000 { device_type = "memory"; - reg = <0x20000000 0x20000000>; + reg = <0x80000000 0x40000000>; }; - clk102: clock { + clk100: clock { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <102000000>; + clock-frequency = <100000000>; }; axi: axi { @@ -77,30 +77,20 @@ compatible = "xlnx,xps-timer-1.00.a"; reg = <0x41c00000 0x1000>; interrupt-parent = <&axi_intc>; - interrupts = <1 2>; - bootph-all; - xlnx,one-timer-only = <0>; - clock-names = "s_axi_aclk"; - clocks = <&clk102>; - }; - - xlnx_timer1: timer@41c20000 { - compatible = "xlnx,xps-timer-1.00.a"; - reg = <0x41c20000 0x1000>; - interrupt-parent = <&axi_intc>; interrupts = <0 2>; + bootph-all; xlnx,one-timer-only = <0>; clock-names = "s_axi_aclk"; - clocks = <&clk102>; + clocks = <&clk100>; }; uart0: serial@40600000 { compatible = "xlnx,xps-uartlite-1.00.a"; reg = <0x40600000 0x1000>; interrupt-parent = <&axi_intc>; - interrupts = <2 2>; + interrupts = <1 2>; bootph-all; - clocks = <&clk102>; + clocks = <&clk100>; current-speed = <115200>; xlnx,data-bits = <8>; xlnx,use-parity = <0>; diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 593d9276d35..d356752a56a 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -42,6 +42,7 @@ struct arch_global_data { #ifdef CONFIG_SMBIOS ulong smbios_start; /* Start address of SMBIOS table */ #endif + struct resume_data *resume; }; #include <asm-generic/global_data.h> diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h new file mode 100644 index 00000000000..19a10cad84c --- /dev/null +++ b/arch/riscv/include/asm/insn-def.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Ventana Micro Systems Ltd. + * + * Ported from linux insn-def.h. + */ + +#ifndef _ASM_RISCV_BARRIER_H +#define _ASM_RISCV_BARRIER_H + +#define INSN_I_SIMM12_SHIFT 20 +#define INSN_I_RS1_SHIFT 15 +#define INSN_I_FUNC3_SHIFT 12 +#define INSN_I_RD_SHIFT 7 +#define INSN_I_OPCODE_SHIFT 0 + +#define RV_OPCODE(v) __ASM_STR(v) +#define RV_FUNC3(v) __ASM_STR(v) +#define RV_FUNC7(v) __ASM_STR(v) +#define RV_SIMM12(v) __ASM_STR(v) +#define RV_RD(v) __ASM_STR(v) +#define RV_RS1(v) __ASM_STR(v) +#define RV_RS2(v) __ASM_STR(v) +#define __RV_REG(v) __ASM_STR(x ## v) +#define RV___RD(v) __RV_REG(v) +#define RV___RS1(v) __RV_REG(v) +#define RV___RS2(v) __RV_REG(v) + +#define RV_OPCODE_MISC_MEM RV_OPCODE(15) +#define RV_OPCODE_SYSTEM RV_OPCODE(115) + +#define __INSN_I(opcode, func3, rd, rs1, simm12) \ + ".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" + +#define INSN_I(opcode, func3, rd, rs1, simm12) \ + __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \ + RV_##rs1, RV_##simm12) + +#endif /* _ASM_RISCV_BARRIER_H */ diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ad32dedb589..47124dbaac8 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -33,8 +33,10 @@ enum sbi_ext_id { SBI_EXT_CPPC = 0x43505043, SBI_EXT_NACL = 0x4E41434C, SBI_EXT_STA = 0x535441, - SBI_EXT_DBTR = 0x44425452, SBI_EXT_SSE = 0x535345, + SBI_EXT_FWFT = 0x46574654, + SBI_EXT_DBTR = 0x44425452, + SBI_EXT_MPXY = 0x4D505859, }; enum sbi_ext_base_fid { diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index afad7e117f3..e184d5e2059 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -5,6 +5,98 @@ */ #include <cpu_func.h> +#include <dm.h> +#include <asm/insn-def.h> +#include <linux/const.h> + +#define CBO_INVAL(base) \ + INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ + RS1(base), SIMM12(0)) +#define CBO_CLEAN(base) \ + INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ + RS1(base), SIMM12(1)) +#define CBO_FLUSH(base) \ + INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ + RS1(base), SIMM12(2)) +enum { + CBO_CLEAN, + CBO_FLUSH, + CBO_INVAL +} riscv_cbo_ops; +static int zicbom_block_size; + +static inline void do_cbo_clean(unsigned long base) +{ + asm volatile ("add a0, %0, zero\n" CBO_CLEAN(%0) :: + "r"(base) : "memory"); +} + +static inline void do_cbo_flush(unsigned long base) +{ + asm volatile ("add a0, %0, zero\n" CBO_FLUSH(%0) :: + "r"(base) : "memory"); +} + +static inline void do_cbo_inval(unsigned long base) +{ + asm volatile ("add a0, %0, zero\n" CBO_INVAL(%0) :: + "r"(base) : "memory"); +} + +static void cbo_op(int op_type, unsigned long start, + unsigned long end) +{ + unsigned long op_size = end - start, size = 0; + void (*fn)(unsigned long base); + + switch (op_type) { + case CBO_CLEAN: + fn = do_cbo_clean; + break; + case CBO_FLUSH: + fn = do_cbo_flush; + break; + case CBO_INVAL: + fn = do_cbo_inval; + break; + } + start &= ~(UL(zicbom_block_size - 1)); + while (size < op_size) { + fn(start + size); + size += zicbom_block_size; + } +} + +void cbo_flush(unsigned long start, unsigned long end) +{ + if (zicbom_block_size) + cbo_op(CBO_FLUSH, start, end); +} + +void cbo_inval(unsigned long start, unsigned long end) +{ + if (zicbom_block_size) + cbo_op(CBO_INVAL, start, end); +} + +static int riscv_zicbom_init(void) +{ + struct udevice *dev; + + if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM) || zicbom_block_size) + return 1; + + uclass_first_device(UCLASS_CPU, &dev); + if (!dev) { + log_debug("Failed to get cpu device!\n"); + return 0; + } + + if (dev_read_u32(dev, "riscv,cbom-block-size", &zicbom_block_size)) + log_debug("riscv,cbom-block-size DT property not present\n"); + + return zicbom_block_size; +} void invalidate_icache_all(void) { @@ -17,6 +109,7 @@ __weak void flush_dcache_all(void) __weak void flush_dcache_range(unsigned long start, unsigned long end) { + cbo_flush(start, end); } __weak void invalidate_icache_range(unsigned long start, unsigned long end) @@ -30,6 +123,7 @@ __weak void invalidate_icache_range(unsigned long start, unsigned long end) __weak void invalidate_dcache_range(unsigned long start, unsigned long end) { + cbo_inval(start, end); } void cache_flush(void) @@ -72,4 +166,6 @@ __weak int dcache_status(void) __weak void enable_caches(void) { + if (!riscv_zicbom_init()) + log_info("Zicbom not initialized.\n"); } diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index c658e72bd39..6dfd1a2d5b8 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -142,7 +142,7 @@ int arch_fixup_fdt(void *blob) size = fdt_totalsize(blob); err = fdt_open_into(blob, blob, size + 32); if (err < 0) { - log_err("Device Tree can't be expanded to accommodate new node"); + log_err("Device-tree can't be expanded to accommodate new node\n"); return err; } chosen_offset = fdt_path_offset(blob, "/chosen"); diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 714cc92d03e..ef1056eeb6f 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -22,11 +22,9 @@ DECLARE_GLOBAL_DATA_PTR; -static struct resume_data *resume; - void set_resume(struct resume_data *data) { - resume = data; + gd->arch.resume = data; } static void show_efi_loaded_images(uintptr_t epc) @@ -138,9 +136,9 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) "Store/AMO page fault", }; - if (resume) { - resume->code = code; - longjmp(resume->jump, 1); + if (gd->arch.resume) { + gd->arch.resume->code = code; + longjmp(gd->arch.resume->jump, 1); } if (code < ARRAY_SIZE(exception_code)) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 9538c66e8be..012ac14a123 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -58,6 +58,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply E1000 imply PCI imply NVME_PCI + imply VIDEO + imply VIDEO_SIMPLE imply PCIE_ECAM_GENERIC imply DM_RNG imply DM_RTC diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index 4309f7528bb..6e8c479e955 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -24,6 +24,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SMP imply CLK_CCF imply CLK_MPFS + imply REGMAP + imply SYSCON imply SYS_NS16550 imply CMD_DHCP imply CMD_EXT2 diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index ed292c364a5..e6bedc38917 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -38,6 +38,8 @@ struct iot2050_info { u8 mac_addr_cnt; u8 mac_addr[8][ARP_HLEN]; char seboot_version[40 + 1]; + u8 padding[3]; + u32 ddr_size_mb; } __packed; /* @@ -172,6 +174,14 @@ static bool board_is_m2(void) strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0; } +static bool board_is_sm(void) +{ + struct iot2050_info *info = IOT2050_INFO_DATA; + + return info->magic == IOT2050_INFO_MAGIC && + strcmp((char *)info->name, "IOT2050-ADVANCED-SM") == 0; +} + static void remove_mmc1_target(void) { char *boot_targets = strdup(env_get("boot_targets")); @@ -185,6 +195,15 @@ static void remove_mmc1_target(void) free(boot_targets); } +static void enable_pcie_connector_power(void) +{ + if (board_is_sm()) + set_pinvalue("gpio@601000_22", "P3V3_PCIE_CON_EN", 1); + else + set_pinvalue("gpio@601000_17", "P3V3_PCIE_CON_EN", 1); + udelay(4 * 100); +} + void set_board_info_env(void) { struct iot2050_info *info = IOT2050_INFO_DATA; @@ -220,8 +239,10 @@ void set_board_info_env(void) if (board_is_advanced()) { if (board_is_pg1()) fdtfile = "ti/k3-am6548-iot2050-advanced.dtb"; - else if(board_is_m2()) + else if (board_is_m2()) fdtfile = "ti/k3-am6548-iot2050-advanced-m2.dtb"; + else if (board_is_sm()) + fdtfile = "ti/k3-am6548-iot2050-advanced-sm.dtb"; else fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb"; } else { @@ -237,23 +258,14 @@ void set_board_info_env(void) env_save(); } -static void m2_overlay_prepare(void) +static void do_overlay_prepare(const char *overlay_path) { #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) - const char *overlay_path; void *overlay; u64 loadaddr; ofnode node; int ret; - if (connector_mode == BKEY_PCIEX2) - return; - - if (connector_mode == BKEY_PCIE_EKEY_PCIE) - overlay_path = "/fit-images/bkey-ekey-pcie-overlay"; - else - overlay_path = "/fit-images/bkey-usb3-overlay"; - node = ofnode_path(overlay_path); if (!ofnode_valid(node)) goto fit_error; @@ -280,6 +292,21 @@ fit_error: #endif } +static void m2_overlay_prepare(void) +{ + const char *overlay_path; + + if (connector_mode == BKEY_PCIEX2) + return; + + if (connector_mode == BKEY_PCIE_EKEY_PCIE) + overlay_path = "/fit-images/bkey-ekey-pcie-overlay"; + else + overlay_path = "/fit-images/bkey-usb3-overlay"; + + do_overlay_prepare(overlay_path); +} + static void m2_connector_setup(void) { ulong m2_manual_config = env_get_ulong("m2_manual_config", 10, @@ -288,10 +315,6 @@ static void m2_connector_setup(void) struct m2_config_pins config_pins; unsigned int n; - /* enable M.2 connector power */ - set_pinvalue("gpio@601000_17", "P3V3_M2_EN", 1); - udelay(4 * 100); - if (m2_manual_config < CONNECTOR_MODE_INVALID) { mode_info = " [manual mode]"; connector_mode = m2_manual_config; @@ -339,25 +362,42 @@ int board_init(void) int dram_init(void) { - if (board_is_advanced()) - gd->ram_size = SZ_2G; - else - gd->ram_size = SZ_1G; + struct iot2050_info *info = IOT2050_INFO_DATA; + gd->ram_size = ((phys_size_t)(info->ddr_size_mb)) << 20; return 0; } +ulong board_get_usable_ram_top(ulong total_size) +{ + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; + + return gd->ram_top; +} + int dram_init_banksize(void) { dram_init(); - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + if (gd->ram_size > SZ_2G) { + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = SZ_2G; - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + /* Bank 1 declares the memory available in the DDR high region */ + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + } else { + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + /* Bank 1 declares the memory available in the DDR high region */ + gd->bd->bi_dram[1].start = 0; + gd->bd->bi_dram[1].size = 0; + } return 0; } @@ -368,8 +408,8 @@ int board_fit_config_name_match(const char *name) struct iot2050_info *info = IOT2050_INFO_DATA; char upper_name[32]; - /* skip the prefix "k3-am65x8-" */ - name += 10; + /* skip the prefix "ti/k3-am65x8-" */ + name += 13; if (info->magic != IOT2050_INFO_MAGIC || strlen(name) >= sizeof(upper_name)) @@ -429,6 +469,8 @@ int board_late_init(void) /* change CTRL_MMR register to let serdes0 not output USB3.0 signals. */ writel(0x3, SERDES0_LANE_SELECT); + enable_pcie_connector_power(); + if (board_is_m2()) m2_connector_setup(); @@ -443,7 +485,7 @@ int board_late_init(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -static void m2_fdt_fixup(void *blob) +static void variants_fdt_fixup(void *blob) { void *overlay_copy = NULL; void *fdt_copy = NULL; @@ -483,14 +525,14 @@ cleanup: return; fixup_error: - pr_err("Could not apply M.2 device tree overlay\n"); + pr_err("Could not apply device tree overlay\n"); goto cleanup; } int ft_board_setup(void *blob, struct bd_info *bd) { if (board_is_m2()) - m2_fdt_fixup(blob); + variants_fdt_fixup(blob); return 0; } diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index f55c6b5d34c..3fd535e7cfc 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -41,7 +41,7 @@ static const struct starfive_vf2_pro milk_v_mars[] = { {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "motorcomm,rx-data-drv-microamp", "2910"}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "rx-internal-delay-ps", "1900"}, + "rx-internal-delay-ps", "1500"}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps", "1500"}, }; @@ -68,9 +68,7 @@ static const struct starfive_vf2_pro starfive_verb[] = { {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "motorcomm,rx-data-drv-microamp", "2910"}, {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "rx-internal-delay-ps", "1900"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "tx-internal-delay-ps", "1500"}, + "rx-internal-delay-ps", "1500"}, {"/soc/ethernet@16040000/mdio/ethernet-phy@1", "motorcomm,tx-clk-adj-enabled", NULL}, diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index a3a6f212577..c52ba1870b0 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -10,14 +10,14 @@ config SYS_CPU default "generic" config TEXT_BASE - default 0x21200000 + default 0x81200000 config SPL_TEXT_BASE - default 0x20000000 + default 0x80000000 config SPL_OPENSBI_LOAD_ADDR hex - default 0x20200000 + default 0x80200000 config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index a231604e492..5ecf56781c1 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -54,8 +54,10 @@ static struct sbi_ext extensions[] = { { SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" }, { SBI_EXT_NACL, "Nested Acceleration Extension" }, { SBI_EXT_STA, "Steal-time Accounting Extension" }, - { SBI_EXT_DBTR, "Debug Trigger Extension" }, { SBI_EXT_SSE, "Supervisor Software Events" }, + { SBI_EXT_FWFT, "Firmware Features Extension" }, + { SBI_EXT_DBTR, "Debug Triggers Extension" }, + { SBI_EXT_MPXY, "Message Proxy Extension" }, }; static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 401e57adeca..2624f0cb573 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -17,7 +17,7 @@ CONFIG_ENV_OFFSET=0x680000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am6528-iot2050-basic" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -79,8 +79,11 @@ CONFIG_CMD_TIME=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y +CONFIG_OF_LIST="ti/k3-am6528-iot2050-basic ti/k3-am6528-iot2050-basic-pg2 ti/k3-am6548-iot2050-advanced ti/k3-am6548-iot2050-advanced-pg2 ti/k3-am6548-iot2050-advanced-m2 ti/k3-am6548-iot2050-advanced-sm" +CONFIG_OF_OVERLAY_LIST="ti/k3-am6548-iot2050-advanced-m2-bkey-usb3 ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie" CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl" +CONFIG_SPL_OF_LIST="ti/k3-am6528-iot2050-basic" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 94952a96762..a35721a8a89 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -4,8 +4,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit" -CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" +CONFIG_OF_UPSTREAM=y CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SYS_MEM_TOP_HIDE=0x400000 CONFIG_TARGET_MICROCHIP_ICICLE=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 511645cebef..c3508926d6c 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -62,6 +62,7 @@ CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="StarFive # " +CONFIG_CMD_ERASEENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_SIZE=512 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index a57cedbfd11..3b6ff62ee12 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 @@ -50,6 +51,7 @@ CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNLZ4 is not set # CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_ITEST is not set @@ -61,7 +63,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NO_NET=y # CONFIG_BLOCK_CACHE is not set -# CONFIG_GPIO is not set +CONFIG_DWAPB_GPIO=y # CONFIG_I2C is not set # CONFIG_INPUT is not set # CONFIG_DM_MMC is not set diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 3983b20c2d8..7333413267e 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -2,17 +2,17 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" -CONFIG_SPL_STACK=0x20200000 -CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_STACK=0x80200000 +CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SYS_LOAD_ADDR=0x20200000 +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 -CONFIG_DEBUG_UART_CLOCK=1000000 +CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_DEBUG_UART=y @@ -20,7 +20,7 @@ CONFIG_TARGET_XILINX_MBV=y # CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst index ee3c5c95846..37b23f6146b 100644 --- a/doc/board/siemens/iot2050.rst +++ b/doc/board/siemens/iot2050.rst @@ -8,7 +8,9 @@ The SIMATIC IOT2050 is an open industrial IoT gateway that is using the TI AM6528 GP (Basic variant) or the AM6548 HS (Advanced variant). The Advanced variant is prepared for secure boot. M.2 Variant also uses the AM6548 HS. Instead of a MiniPCI connector, it comes with two M.2 connectors and can -support 5G/WIFI/BT applications or connect an SSD. +support 5G/WIFI/BT applications or connect an SSD. Compared with the AM6548 +Advanced variant, SM variant removes the Arduino interface, and adds a new +ASIC for communicating with the PLC 1200 signal modules. The IOT2050 starts only from OSPI. It loads a Siemens-provided bootloader called SE-Boot for the MCU domain (R5F cores), then hands over to ATF and @@ -29,6 +31,9 @@ The following binaries from that source need to be present in the build folder: - seboot_pg1.bin - seboot_pg2.bin +Note that SE-Boot D/V01.04.01.02 or greater is required, otherwise the DDR size +will not be picked up correctly by U-Boot. + When using the watchdog, a related firmware for the R5 core(s) is needed, e.g. https://github.com/siemens/k3-rti-wdt. The name and location of the image is configured via CONFIG_WDT_K3_RTI_FW_FILE. diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 9340e9c4311..faec644249e 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -51,10 +51,9 @@ Examples:: Current Status -------------- -* U-Boot v2024.10 was released on Mon 07 October 2024. +* U-Boot v2025.01-rc1 was released on Mon 28 October 2024. -* The Merge Window for the next release (v2025.01) is **open** until the -rc1 - release on Mon 28 October 2024. +* The Merge Window for the next release (v2025.01) is **closed**. * The next branch is now **closed**. @@ -66,9 +65,9 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -.. For the next scheduled release, release candidates were made on:: +For the next scheduled release, release candidates were made on:: -.. * U-Boot v2025.01-rc1 was released on Mon 28 October 2024. +* U-Boot v2025.01-rc1 was released on Mon 28 October 2024. .. * U-Boot v2025.01-rc2 was released on Mon 11 November 2024. diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index b70241559db..62072e100b1 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -1,5 +1,7 @@ config CLK_MPFS bool "Clock support for Microchip PolarFire SoC" depends on CLK && CLK_CCF + depends on SYSCON + depends on REGMAP help This enables support clock driver for Microchip PolarFire SoC platform. diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c index 0a82777ff74..2c6694f0035 100644 --- a/drivers/clk/microchip/mpfs_clk.c +++ b/drivers/clk/microchip/mpfs_clk.c @@ -9,25 +9,39 @@ #include <log.h> #include <dm/device.h> #include <dm/devres.h> +#include <dm/ofnode.h> #include <dm/uclass.h> +#include <regmap.h> +#include <syscon.h> #include <dt-bindings/clock/microchip-mpfs-clock.h> #include <linux/err.h> #include "mpfs_clk.h" -static int mpfs_clk_probe(struct udevice *dev) +static int mpfs_clk_syscon_probe(struct udevice *dev, void __iomem **msspll_base, + struct regmap **regmap) { - struct clk *parent_clk = dev_get_priv(dev); - struct clk clk_msspll = { .id = CLK_MSSPLL }; - void __iomem *base; - void __iomem *msspll_base; - int ret; + ofnode node; - base = dev_read_addr_index_ptr(dev, 0); - if (!base) - return -EINVAL; + node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-mss-top-sysreg"); + if (!ofnode_valid(node)) + return -ENODEV; - ret = clk_get_by_index(dev, 0, parent_clk); + *regmap = syscon_node_to_regmap(node); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + *msspll_base = dev_read_addr_index_ptr(dev, 0); + + return 0; +} + +static int mpfs_clk_old_format_probe(struct udevice *dev, void __iomem **msspll_base, + struct regmap **regmap) +{ + int ret; + + ret = regmap_init_mem_index(dev_ofnode(dev), regmap, 0); if (ret) return ret; @@ -40,7 +54,30 @@ static int mpfs_clk_probe(struct udevice *dev) * Otherwise, skip registering it & pass the reference clock directly * to the cfg clock registration function. */ - msspll_base = dev_read_addr_index_ptr(dev, 1); + *msspll_base = dev_read_addr_index_ptr(dev, 1); + + return 0; +} + +static int mpfs_clk_probe(struct udevice *dev) +{ + struct clk *parent_clk = dev_get_priv(dev); + struct clk clk_msspll = { .id = CLK_MSSPLL }; + struct regmap *regmap; + void __iomem *msspll_base; + int ret; + + ret = clk_get_by_index(dev, 0, parent_clk); + if (ret) + return ret; + + ret = mpfs_clk_syscon_probe(dev, &msspll_base, ®map); + if (ret) { + ret = mpfs_clk_old_format_probe(dev, &msspll_base, ®map); + if (ret) + return ret; + } + if (msspll_base) { ret = mpfs_clk_register_msspll(msspll_base, parent_clk); if (ret) @@ -50,11 +87,11 @@ static int mpfs_clk_probe(struct udevice *dev) parent_clk = &clk_msspll; } - ret = mpfs_clk_register_cfgs(base, parent_clk); + ret = mpfs_clk_register_cfgs(parent_clk, regmap); if (ret) return ret; - ret = mpfs_clk_register_periphs(base, dev); + ret = mpfs_clk_register_periphs(dev, regmap); return ret; } diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h index 72288cc971b..b8ad3ea7616 100644 --- a/drivers/clk/microchip/mpfs_clk.h +++ b/drivers/clk/microchip/mpfs_clk.h @@ -7,6 +7,7 @@ #define __MICROCHIP_MPFS_CLK_H #include <linux/clk-provider.h> +#include <regmap.h> /** * mpfs_clk_register_cfgs() - register configuration clocks * @@ -14,7 +15,7 @@ * @parent: a pointer to parent clock. * Return: zero on success, or a negative error code. */ -int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent); +int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap); /** * mpfs_clk_register_msspll() - register the mss pll * @@ -30,7 +31,7 @@ int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent); * @dev: udevice representing the clock controller. * Return: zero on success, or a negative error code. */ -int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev); +int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap); /** * divider_get_val() - get the clock divider value * diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c index 5e8fb995289..7da1fc77120 100644 --- a/drivers/clk/microchip/mpfs_clk_cfg.c +++ b/drivers/clk/microchip/mpfs_clk_cfg.c @@ -9,6 +9,7 @@ #include <dm/device.h> #include <dm/devres.h> #include <dm/uclass.h> +#include <regmap.h> #include <dt-bindings/clock/microchip-mpfs-clock.h> #include <linux/err.h> @@ -57,7 +58,7 @@ struct mpfs_cfg_clock { */ struct mpfs_cfg_hw_clock { struct mpfs_cfg_clock cfg; - void __iomem *sys_base; + struct regmap *regmap; u32 prate; struct clk hw; }; @@ -68,11 +69,11 @@ static ulong mpfs_cfg_clk_recalc_rate(struct clk *hw) { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; unsigned long rate; u32 val; - val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift; + regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val); + val >>= cfg->shift; val &= clk_div_mask(cfg->width); rate = cfg_hw->prate / (1u << val); hw->rate = rate; @@ -84,7 +85,6 @@ static ulong mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate) { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; u32 val; int divider_setting; @@ -93,10 +93,10 @@ static ulong mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate) if (divider_setting < 0) return divider_setting; - val = readl(base_addr + REG_CLOCK_CONFIG_CR); + regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val); val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); val |= divider_setting << cfg->shift; - writel(val, base_addr + REG_CLOCK_CONFIG_CR); + regmap_write(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, val); return clk_get_rate(hw); } @@ -116,7 +116,7 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0), }; -int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent) +int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap) { int ret; int i, id, num_clks; @@ -126,7 +126,7 @@ int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent) num_clks = ARRAY_SIZE(mpfs_cfg_clks); for (i = 0; i < num_clks; i++) { hw = &mpfs_cfg_clks[i].hw; - mpfs_cfg_clks[i].sys_base = base; + mpfs_cfg_clks[i].regmap = regmap; mpfs_cfg_clks[i].prate = clk_get_rate(parent); name = mpfs_cfg_clks[i].cfg.name; ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent->dev->name); diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c index 41c6df4fb97..b734f49d81a 100644 --- a/drivers/clk/microchip/mpfs_clk_periph.c +++ b/drivers/clk/microchip/mpfs_clk_periph.c @@ -9,6 +9,7 @@ #include <dm/device.h> #include <dm/devres.h> #include <dm/uclass.h> +#include <regmap.h> #include <dt-bindings/clock/microchip-mpfs-clock.h> #include <linux/err.h> @@ -50,7 +51,7 @@ struct mpfs_periph_clock { */ struct mpfs_periph_hw_clock { struct mpfs_periph_clock periph; - void __iomem *sys_base; + struct regmap *regmap; u32 prate; struct clk hw; }; @@ -61,17 +62,16 @@ static int mpfs_periph_clk_enable(struct clk *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; - u32 reg, val; + u32 reg; if (periph->flags != CLK_IS_CRITICAL) { - reg = readl(base_addr + REG_SUBBLK_RESET_CR); - val = reg & ~(1u << periph->shift); - writel(val, base_addr + REG_SUBBLK_RESET_CR); + regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, ®); + reg &= ~(1u << periph->shift); + regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg); - reg = readl(base_addr + REG_SUBBLK_CLOCK_CR); - val = reg | (1u << periph->shift); - writel(val, base_addr + REG_SUBBLK_CLOCK_CR); + regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, ®); + reg |= (1u << periph->shift); + regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg); } return 0; @@ -81,17 +81,16 @@ static int mpfs_periph_clk_disable(struct clk *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; - u32 reg, val; + u32 reg; if (periph->flags != CLK_IS_CRITICAL) { - reg = readl(base_addr + REG_SUBBLK_RESET_CR); - val = reg | (1u << periph->shift); - writel(val, base_addr + REG_SUBBLK_RESET_CR); + regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, ®); + reg |= (1u << periph->shift); + regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg); - reg = readl(base_addr + REG_SUBBLK_CLOCK_CR); - val = reg & ~(1u << periph->shift); - writel(val, base_addr + REG_SUBBLK_CLOCK_CR); + regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, ®); + reg &= ~(1u << periph->shift); + regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg); } return 0; @@ -159,7 +158,7 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0), }; -int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev) +int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap) { int ret; int i, id, num_clks; @@ -172,7 +171,7 @@ int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev) clk_request(dev, &parent); hw = &mpfs_periph_clks[i].hw; - mpfs_periph_clks[i].sys_base = base; + mpfs_periph_clks[i].regmap = regmap; mpfs_periph_clks[i].prate = clk_get_rate(&parent); name = mpfs_periph_clks[i].periph.name; ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent.dev->name); diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index 7a6eae9ba18..04639a4cb68 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -177,7 +177,9 @@ static int gpio_dwapb_bind(struct udevice *dev) plat->base = (void *)base; plat->bank = bank; - plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0); + + if (ofnode_read_u32(node, "ngpios", &plat->pins)) + plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0); if (ofnode_read_string_index(node, "bank-name", 0, &plat->name)) { diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi index e2584a5efe3..b3c4c0eec3d 100644 --- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi @@ -9,11 +9,6 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG2 */ -&mcu_r5fss0 { - /* lock-step mode not supported on PG2 boards */ - ti,cluster-mode = <0>; -}; - &main_pmx0 { cp2102n_reset_pin_default: cp2102n-reset-default-pins { pinctrl-single,pins = < diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi index ef34b851e17..e76828ccf21 100644 --- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi @@ -635,3 +635,8 @@ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; }; + +&mcu_r5fss0 { + /* lock-step mode not supported on iot2050 boards */ + ti,cluster-mode = <0>; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts b/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts index 29a31891b3d..4968a47f31e 100644 --- a/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts +++ b/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic.dts @@ -22,8 +22,3 @@ compatible = "siemens,iot2050-basic", "ti,am654"; model = "SIMATIC IOT2050 Basic"; }; - -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso index c9e736098f9..666237f6d79 100644 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso +++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0 - * Copyright (c) Siemens AG, 2022 + * Copyright (c) Siemens AG, 2022-2024 * * Authors: * Chao Zeng <chao.zeng@siemens.com> diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso index 72fc011bd54..0f86235c977 100644 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso +++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0 - * Copyright (c) Siemens AG, 2022 + * Copyright (c) Siemens AG, 2022-2024 * * Authors: * Chao Zeng <chao.zeng@siemens.com> diff --git a/dts/upstream/src/riscv/Makefile b/dts/upstream/src/riscv/Makefile new file mode 100644 index 00000000000..980617e6de3 --- /dev/null +++ b/dts/upstream/src/riscv/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/scripts/Makefile.dts + +DTC_FLAGS += -R 4 -p 0x1000 + diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 94a9c767882..5c58c7bbaab 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -24,6 +24,9 @@ func(USB, usb, 2) #endif +/* DDR Configuration */ +#define CFG_SYS_SDRAM_BASE1 0x880000000 + /* * This defines all MMC devices, even if the basic variant has no mmc1. * The non-supported device will be removed from the boot targets during @@ -39,7 +42,7 @@ #define CFG_ENV_FLAGS_LIST_STATIC \ "board_uuid:sw,board_name:sw,board_serial:sw,board_a5e:sw," \ "mlfb:sw,fw_version:sw,seboot_version:sw," \ - "m2_manuel_config:sw," \ + "m2_manual_config:sw," \ "eth1addr:mw,eth2addr:mw,watchdog_timeout_ms:dw,boot_targets:sw" #endif diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 2f594bfcfd6..cf4fcb90b04 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -22,6 +22,7 @@ "stderr=serial,vidconsole\0" #define BOOT_TARGET_DEVICES(func) \ + func(NVME, nvme, 0) \ func(VIRTIO, virtio, 0) \ func(VIRTIO, virtio, 1) \ func(SCSI, scsi, 0) \ |