diff options
211 files changed, 6329 insertions, 425 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce472aa9bd5..c6a39aa3412 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -316,6 +316,8 @@ int arch_cpu_init(void) struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; u32 state; + icache_enable(); + /* * The RCPM FSM state may not be reset after power-on. * So, reset them. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 858b79ac97e..af2842a0f8b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -438,6 +438,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1012a-frdm.dtb \ fsl-ls1012a-frwy.dtb dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ + fsl-ls1028a-kontron-sl28-var1.dtb \ + fsl-ls1028a-kontron-sl28-var2.dtb \ fsl-ls1028a-kontron-sl28-var3.dtb \ fsl-ls1028a-kontron-sl28-var4.dtb \ @@ -809,6 +811,8 @@ dtb-$(CONFIG_RCAR_GEN2) += \ dtb-$(CONFIG_RCAR_GEN3) += \ r8a774a1-beacon-rzg2m-kit.dtb \ + r8a774b1-beacon-rzg2n-kit.dtb \ + r8a774e1-beacon-rzg2h-kit.dtb \ r8a77950-ulcb-u-boot.dtb \ r8a77950-salvator-x-u-boot.dtb \ r8a77960-ulcb-u-boot.dtb \ diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi b/arch/arm/dts/beacon-renesom-baseboard.dtsi index 8a472c057a9..5f998d47064 100644 --- a/arch/arm/dts/beacon-renesom-baseboard.dtsi +++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi @@ -5,35 +5,27 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/clk/versaclock.h> / { - aliases { - serial0 = &scif2; - serial1 = &hscif0; - serial2 = &hscif1; - serial3 = &scif0; - serial4 = &hscif2; - serial5 = &scif5; - spi0 = &msiof0; - spi1 = &msiof1; - spi2 = &msiof2; - spi3 = &msiof3; - ethernet0 = &avb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; power-supply = <®_lcd>; enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>; - pwms = <&pwm0 0 50000>; + pwms = <&pwm2 0 25000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; + backlight_dpi: backlight-dpi { + compatible = "pwm-backlight"; + power-supply = <®_lcd>; + enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 0 25000>; + brightness-levels = <0 25 33 50 63 75 88 100>; + default-brightness-level = <6>; + }; + hdmi0-out { compatible = "hdmi-connector"; type = "a"; @@ -48,38 +40,38 @@ keys { compatible = "gpio-keys"; - key-1 { + key-1 { /* S19 */ gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - linux,code = <KEY_1>; - label = "Switch-1"; + linux,code = <KEY_UP>; + label = "Up"; wakeup-source; debounce-interval = <20>; }; - key-2 { + key-2 { /*S20 */ gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - linux,code = <KEY_2>; - label = "Switch-2"; + linux,code = <KEY_LEFT>; + label = "Left"; wakeup-source; debounce-interval = <20>; }; - key-3 { + key-3 { /* S21 */ gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - linux,code = <KEY_3>; - label = "Switch-3"; + linux,code = <KEY_DOWN>; + label = "Down"; wakeup-source; debounce-interval = <20>; }; - key-4 { + key-4 { /* S22 */ gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - linux,code = <KEY_4>; - label = "Switch-4"; + linux,code = <KEY_RIGHT>; + label = "Right"; wakeup-source; debounce-interval = <20>; }; - key-5 { + key-5 { /* S23 */ gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - linux,code = <KEY_5>; - label = "Switch-4"; + linux,code = <KEY_ENTER>; + label = "Center"; wakeup-source; debounce-interval = <20>; }; @@ -98,17 +90,59 @@ led1 { gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; label = "LED1"; - linux,default-trigger = "heartbeat"; }; led2 { gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; label = "LED2"; - linux,default-trigger = "heartbeat"; }; led3 { gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; label = "LED3"; - linux,default-trigger = "heartbeat"; + }; + }; + + lvds { + compatible = "panel-lvds"; + power-supply = <®_lcd_reset>; + width-mm = <223>; + height-mm = <125>; + backlight = <&backlight_lvds>; + data-mapping = "vesa-24"; + + panel-timing { + /* 800x480@60Hz */ + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hsync-len = <48>; + hfront-porch = <40>; + hback-porch = <40>; + vfront-porch = <13>; + vback-porch = <29>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <3>; + de-active = <1>; + pixelclk-active = <0>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + rgb { + /* Different LCD with compatible timings */ + compatible = "rocktech,rk070er9427"; + backlight = <&backlight_dpi>; + enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + power-supply = <®_lcd>; + port { + rgb_panel: endpoint { + remote-endpoint = <&du_out_rgb>; + }; }; }; @@ -117,7 +151,7 @@ regulator-name = "audio-1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>; + gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -167,15 +201,12 @@ vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; - regulator-name = "SDHI0 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1>, <1800000 0>; - regulator-always-on; }; /* External DU dot clocks */ @@ -190,10 +221,29 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; -}; -&audio_clk_a { - clock-frequency = <22579200>; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; }; &audio_clk_b { @@ -214,30 +264,19 @@ status = "okay"; }; -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; +&du_out_rgb { + remote-endpoint = <&rgb_panel>; }; &ehci0 { dr_mode = "otg"; status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>, <&versaclock6_bb 4>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>; }; &ehci1 { status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 4>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; }; &hdmi0 { @@ -258,7 +297,6 @@ }; }; port@2 { - /* HDMI sound */ reg = <2>; dw_hdmi0_snd_in: endpoint { remote-endpoint = <&rsnd_endpoint1>; @@ -281,7 +319,7 @@ &i2c2 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -299,18 +337,49 @@ #gpio-cells = <2>; }; - versaclock6_bb: versaclock6_bb@6a { + gpio_exp4: gpio@23 { + compatible = "onnn,pca9654"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + versaclock6_bb: clock-controller@6a { compatible = "idt,5p49v6965"; reg = <0x6a>; #clock-cells = <1>; clocks = <&x304_clk>; clock-names = "xin"; - /* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */ + assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, <&versaclock6_bb 3>, <&versaclock6_bb 4>; - assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24000000>; + assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>; + + OUT1 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT2 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT3 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; + + OUT4 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; }; }; @@ -324,13 +393,14 @@ &i2c5 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-0 = <&i2c5_pins>; pinctrl-names = "default"; codec: wm8962@1a { compatible = "wlf,wm8962"; reg = <0x1a>; + clocks = <&versaclock6_bb 3>; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; @@ -375,6 +445,49 @@ interrupts = <9 IRQ_TYPE_EDGE_RISING>; wakeup-source; }; + + hd3ss3220@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + interrupt-parent = <&gpio6>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&msiof1 { + pinctrl-0 = <&msiof1_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; }; &ohci0 { @@ -440,6 +553,11 @@ function = "pwm0"; }; + pwm2_pins: pwm2 { + groups = "pwm2_a"; + function = "pwm2"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -458,7 +576,7 @@ }; sound_clk_pins: sound_clk { - groups = "audio_clk_a_a"; + groups = "audio_clk_a_a", "audio_clk_b_a"; function = "audio_clk"; }; @@ -490,6 +608,12 @@ status = "okay"; }; +&pwm2 { + pinctrl-0 = <&pwm2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &rcar_sound { pinctrl-0 = <&sound_pins &sound_clk_pins>; pinctrl-names = "default"; @@ -503,23 +627,6 @@ status = "okay"; - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; - ports { #address-cells = <1>; #size-cells = <0>; @@ -551,6 +658,11 @@ }; }; +&rwdt { + status = "okay"; + timeout-sec = <60>; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; @@ -584,6 +696,26 @@ shared-pin; }; +&tmu0 { + status = "okay"; +}; + +&tmu1 { + status = "okay"; +}; + +&tmu2 { + status = "okay"; +}; + +&tmu3 { + status = "okay"; +}; + +&tmu4 { + status = "okay"; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; @@ -595,3 +727,62 @@ pinctrl-names = "default"; status = "okay"; }; + +&usb3_peri0 { + companion = <&xhci0>; + status = "okay"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&vin0 { + status = "okay"; +}; +&vin1 { + status = "okay"; +}; +&vin2 { + status = "okay"; +}; +&vin3 { + status = "okay"; +}; +&vin4 { + status = "okay"; +}; +&vin5 { + status = "okay"; +}; +&vin6 { + status = "okay"; +}; +&vin7 { + status = "okay"; +}; + +&xhci0 +{ + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi index 6c16a2732a8..9565495b495 100644 --- a/arch/arm/dts/beacon-renesom-som.dtsi +++ b/arch/arm/dts/beacon-renesom-som.dtsi @@ -4,17 +4,18 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clk/versaclock.h> / { memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; + reg = <0x0 0x48000000 0x0 0xc000000>; }; - memory@600000000 { + memory@57000000 { device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; + reg = <0x0 0x57000000 0x0 0x29000000>; }; osc_32k: osc_32k { @@ -55,7 +56,8 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { @@ -88,7 +90,6 @@ pinctrl-names = "default"; uart-has-rtscts; status = "okay"; - max-speed = <4000000>; bluetooth { compatible = "brcm,bcm43438-bt"; @@ -97,6 +98,7 @@ device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>; clocks = <&osc_32k>; clock-names = "extclk"; + max-speed = <4000000>; }; }; @@ -108,7 +110,7 @@ &i2c4 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; pca9654: gpio@20 { compatible = "onnn,pca9654"; @@ -147,7 +149,7 @@ }; eeprom@50 { - compatible = "microchip, at24c64", "atmel,24c64"; + compatible = "microchip,at24c64", "atmel,24c64"; pagesize = <32>; read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x50>; @@ -169,7 +171,32 @@ <&versaclock5 2>, <&versaclock5 3>, <&versaclock5 4>; + assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>; + + OUT1 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT2 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT3 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT4 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; }; }; @@ -295,18 +322,14 @@ status = "okay"; }; -&usb_extal_clk { - clock-frequency = <50000000>; +&usb2_clksel { + status = "okay"; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&versaclock5 3>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; }; &usb3s0_clk { clock-frequency = <100000000>; }; - -&vspb { - status = "okay"; -}; - -&vspi0 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index c401ba33ac5..2894842cf25 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -71,6 +71,26 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 9b4e0298a75..240178ab4e7 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -10,8 +10,6 @@ i2c1 = &i2c3; i2c2 = &i2c4; rtc0 = &rtc; - ethernet0 = &enetc0; - ethernet1 = &enetc1; ethernet2 = &enetc2; ethernet3 = &enetc6; }; @@ -52,6 +50,28 @@ }; fdt-2 { + description = "fsl-ls1028a-kontron-sl28-var1"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dtb"; + }; + }; + + fdt-3 { + description = "fsl-ls1028a-kontron-sl28-var2"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dtb"; + }; + }; + + fdt-4 { description = "fsl-ls1028a-kontron-sl28-var3"; type = "flat_dt"; arch = "arm"; @@ -62,7 +82,7 @@ }; }; - fdt-3 { + fdt-5 { description = "fsl-ls1028a-kontron-sl28-var4"; type = "flat_dt"; arch = "arm"; @@ -84,16 +104,30 @@ }; conf-2 { - description = "fsl-ls1028a-kontron-sl28-var3"; + description = "fsl-ls1028a-kontron-sl28-var1"; firmware = "uboot"; fdt = "fdt-2"; }; conf-3 { - description = "fsl-ls1028a-kontron-sl28-var4"; + description = "fsl-ls1028a-kontron-sl28-var2"; firmware = "uboot"; fdt = "fdt-3"; }; + + conf-4 { + description = "fsl-ls1028a-kontron-sl28-var3"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-4"; + }; + + conf-5 { + description = "fsl-ls1028a-kontron-sl28-var4"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-5"; + }; }; }; }; @@ -133,6 +167,16 @@ firmware = "bl31"; loadables = "uboot"; }; + + conf-4 { + firmware = "bl31"; + loadables = "uboot"; + }; + + conf-5 { + firmware = "bl31"; + loadables = "uboot"; + }; }; }; }; @@ -169,6 +213,14 @@ conf-3 { loadables = "uboot", "bl32"; }; + + conf-4 { + loadables = "uboot", "bl32"; + }; + + conf-5 { + loadables = "uboot", "bl32"; + }; }; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi new file mode 100644 index 00000000000..98e89393692 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &enetc1; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts new file mode 100644 index 00000000000..fe708bdbfa0 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 1 which has one ethernet port. It is + * different than the base variant, which also has one port, but here the + * port is connected via RGMII. This port is not TSN aware. + * None of the four SerDes lanes are used by the module, instead they are + * all led out to the carrier for customer use. + * + * Copyright (C) 2020 Michael Walle <michael@walle.cc> + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" +#include <dt-bindings/net/qca-ar803x.h> + +/ { + model = "Kontron SMARC-sAL28 (4 Lanes)"; + compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; +}; + +&enetc0 { + status = "disabled"; + /delete-property/ phy-handle; +}; + +&enetc1 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +/delete-node/ &phy0; +&mdio0 { + phy0: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = <AR803X_STRENGTH_FULL>; + + vddio-supply = <&vddh>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi new file mode 100644 index 00000000000..79b771e0746 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts new file mode 100644 index 00000000000..1ea1265bcf5 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 2 which has no ethernet support in the + * bootloader. + * + * Copyright (C) 2020 Michael Walle <michael@walle.cc> + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" + +/ { + model = "Kontron SMARC-sAL28 (TSN-on-module)"; + compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; +}; + +&enetc0 { + status = "disabled"; + /delete-property/ phy-handle; +}; + +/delete-node/ &phy0; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi index 79b771e0746..879a76415ba 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi @@ -1,2 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ #include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &enetc0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi index 79b771e0746..fce46946828 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi @@ -1,2 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ #include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &enetc0; + ethernet1 = &enetc1; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts index 9561a585628..ea77a83d2fe 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts @@ -172,6 +172,10 @@ }; }; +&sata { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index d0850237c79..5171bf28c79 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -380,6 +380,39 @@ status = "disabled"; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; + sata: sata@3200000 { compatible = "fsl,ls1028a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 8ca57ea7b96..d8171bd03b4 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -79,6 +79,46 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 134 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 155455d591e..9df419a87d8 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -78,6 +78,46 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 66 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 67 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 68 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 134 4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 7b4ac6d3ded..64caa600ad7 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -2,9 +2,10 @@ /* * NXP ls1088a SOC common device tree source * - * Copyright 2017, 2020 NXP + * Copyright 2017, 2020-2021 NXP */ +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "fsl,ls1088a"; interrupt-parent = <&gic>; @@ -115,6 +116,50 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x2240000 0x0 0x20000>; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index f0f4a82c146..7374d580e07 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -2,7 +2,7 @@ /* * NXP ls2080a SOC common device tree source * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * Copyright 2013-2015 Freescale Semiconductor, Inc. */ @@ -120,6 +120,50 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 0x4>; /* Level high type */ + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 0x4>; /* Level high type */ + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index b16526503d9..341610ccf4a 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -15,20 +15,123 @@ compatible = "fsl,lx2162aqds", "fsl,lx2160a"; aliases { - pcie@3500000 { - status = "disabled"; - }; - - pcie@3800000 { - status = "disabled"; - }; - - pcie@3900000 { - status = "disabled"; - }; + spi1 = &dspi0; + spi2 = &dspi1; + spi3 = &dspi2; }; }; &usb1 { status = "disabled"; }; + +&pcie2 { + status = "disabled"; +}; + +&pcie5 { + status = "disabled"; +}; + +&pcie6 { + status = "disabled"; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dflash3: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash4: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash5: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&dspi2 { + bus-num = <0>; + status = "okay"; + + dflash6: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash7: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash8: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 0eeec43cccc..7b99ce02b35 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -98,6 +98,46 @@ bus-width = <4>; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + scfg: scfg@1570000 { compatible = "fsl,ls1021a-scfg", "syscon"; reg = <0x1570000 0x10000>; diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts index e7ed5d48061..501cb05da22 100644 --- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts +++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts @@ -10,6 +10,61 @@ #include "beacon-renesom-baseboard.dtsi" / { - model = "Beacon Embedded Works RZ/G2M Development Kit"; - compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; + model = "Beacon EmbeddedWorks RZ/G2M Development Kit"; + compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; + + aliases { + serial0 = &scif2; + serial1 = &hscif0; + serial2 = &hscif1; + serial3 = &scif0; + serial4 = &hscif2; + serial5 = &scif5; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; + +/* Reference versaclock instead of audio_clk_a */ +&rcar_sound { + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774A1_CLK_S0D4>; }; diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi index 8e80f50132a..d64fb8b1b86 100644 --- a/arch/arm/dts/r8a774a1.dtsi +++ b/arch/arm/dts/r8a774a1.dtsi @@ -408,7 +408,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774a1"; reg = <0 0xe6060000 0 0x50c>; }; @@ -835,6 +835,21 @@ status = "disabled"; }; + usb2_clksel: clock-controller@e6590630 { + compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", + "renesas,rcar-gen3-usb2-clock-sel"; + reg = <0 0xe6590630 0 0x02>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal_clk>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; + #clock-cells = <0>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; + status = "disabled"; + }; + usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a774a1-usb-dmac", "renesas,usb-dmac"; @@ -1115,6 +1130,8 @@ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; @@ -2300,6 +2317,23 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a774a1-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x4000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + clock-names = "rpc"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -2371,6 +2405,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774a1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a774a1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi new file mode 100644 index 00000000000..a0c0a7f35c4 --- /dev/null +++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&cpg { + u-boot,dm-pre-reloc; +}; + +&extal_clk { + u-boot,dm-pre-reloc; +}; + +&prr { + u-boot,dm-pre-reloc; +}; + +&extalr_clk { + u-boot,dm-pre-reloc; +}; + +&sdhi0 { + /delete-property/ cd-gpios; +}; + +&sdhi2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts new file mode 100644 index 00000000000..71763f4402a --- /dev/null +++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "r8a774b1.dtsi" +#include "beacon-renesom-som.dtsi" +#include "beacon-renesom-baseboard.dtsi" + +/ { + model = "Beacon Embedded Works RZ/G2N Development Kit"; + compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; + + aliases { + serial0 = &scif2; + serial1 = &hscif0; + serial2 = &hscif1; + serial3 = &scif0; + serial4 = &hscif2; + serial5 = &scif5; + serial6 = &scif4; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +/* Reference versaclock instead of audio_clk_a */ +&rcar_sound { + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774B1_CLK_S0D4>; +}; diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi index 23119c0ae7b..5b05474dc27 100644 --- a/arch/arm/dts/r8a774b1.dtsi +++ b/arch/arm/dts/r8a774b1.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the r8a774b1 SoC * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2019 Renesas Electronics Corp. */ #include <dt-bindings/interrupt-controller/irq.h> @@ -282,7 +282,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774b1"; reg = <0 0xe6060000 0 0x50c>; }; @@ -709,6 +709,21 @@ status = "disabled"; }; + usb2_clksel: clock-controller@e6590630 { + compatible = "renesas,r8a774b1-rcar-usb2-clock-sel", + "renesas,rcar-gen3-usb2-clock-sel"; + reg = <0 0xe6590630 0 0x02>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal_clk>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; + #clock-cells = <0>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; + status = "disabled"; + }; + usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a774b1-usb-dmac", "renesas,usb-dmac"; @@ -989,6 +1004,8 @@ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; @@ -2158,6 +2175,23 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a774b1-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x4000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + clock-names = "rpc"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a774b1", "renesas,rcar-gen3-sata"; @@ -2240,6 +2274,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774b1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a774b1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi new file mode 100644 index 00000000000..eef200af2d1 --- /dev/null +++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&cpg { + u-boot,dm-pre-reloc; +}; + +&extal_clk { + u-boot,dm-pre-reloc; +}; + +&prr { + u-boot,dm-pre-reloc; +}; + +&extalr_clk { + u-boot,dm-pre-reloc; +}; + +&sdhi0 { + /delete-property/ cd-gpios; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + status = "disabled"; +}; + +&sdhi3 { + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts new file mode 100644 index 00000000000..273f062f290 --- /dev/null +++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "r8a774e1.dtsi" +#include "beacon-renesom-som.dtsi" +#include "beacon-renesom-baseboard.dtsi" + +/ { + model = "Beacon Embedded Works RZ/G2H Development Kit"; + compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; + + aliases { + serial0 = &scif2; + serial1 = &hscif0; + serial2 = &hscif1; + serial3 = &scif0; + serial4 = &hscif2; + serial5 = &scif5; + serial6 = &scif4; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x80000000>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +/* Reference versaclock instead of audio_clk_a */ +&rcar_sound { + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774E1_CLK_S0D4>; +}; diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi index 0f86cfd5242..8eb006cbd9a 100644 --- a/arch/arm/dts/r8a774e1.dtsi +++ b/arch/arm/dts/r8a774e1.dtsi @@ -28,6 +28,12 @@ clock-frequency = <0>; }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; @@ -127,6 +133,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; @@ -141,6 +148,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -154,6 +162,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -167,6 +176,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -180,6 +190,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; #cooling-cells = <2>; dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; @@ -194,6 +205,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -206,6 +218,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -218,6 +231,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -236,6 +250,28 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <700>; + exit-latency-us = <700>; + min-residency-us = <5000>; + }; + }; }; extal_clk: extal { @@ -427,7 +463,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774e1"; reg = <0 0xe6060000 0 0x50c>; }; @@ -838,18 +874,76 @@ }; hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a774e1", + "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; status = "disabled"; + }; - /* placeholder */ + usb2_clksel: clock-controller@e6590630 { + compatible = "renesas,r8a774e1-rcar-usb2-clock-sel", + "renesas,rcar-gen3-usb2-clock-sel"; + reg = <0 0xe6590630 0 0x02>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal_clk>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; + #clock-cells = <0>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a774e1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a774e1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; }; usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a774e1-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; #phy-cells = <0>; status = "disabled"; - - /* placeholder */ }; dmac0: dma-controller@e6700000 { @@ -1139,6 +1233,8 @@ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; @@ -1203,11 +1299,73 @@ }; pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; #pwm-cells = <2>; status = "disabled"; + }; - /* placeholder */ + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; }; scif0: serial@e6e60000 { @@ -1372,7 +1530,260 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin7>; + }; + }; + }; + }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -1380,71 +1791,569 @@ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774E1_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; status = "disabled"; - /* placeholder */ + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; + }; ssi2: ssi-2 { - /* placeholder */ + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; + }; + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a774e1", + "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; status = "disabled"; - - /* placeholder */ }; usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a774e1-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; status = "disabled"; - - /* placeholder */ }; ohci0: usb@ee080000 { + compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; - - /* placeholder */ }; ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; reg = <0 0xee0a0000 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; status = "disabled"; - - /* placeholder */ }; ehci0: usb@ee080100 { + compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; - - /* placeholder */ }; ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; status = "disabled"; - - /* placeholder */ }; usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a774e1", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; status = "disabled"; - - /* placeholder */ }; usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a774e1", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; status = "disabled"; - - /* placeholder */ }; sdhi0: mmc@ee100000 { @@ -1499,6 +2408,35 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a774e1-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x4000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + clock-names = "rpc"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a774e1", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 815>; + iommus = <&ipmmu_hc 2>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1517,53 +2455,435 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; + }; - /* placeholder */ + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774e1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a774e1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 615>; + }; + + fcpf1: fcp@fe951000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe951000 0 0x200>; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 614>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 607>; + }; + + fcpvb1: fcp@fe92f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 606>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 611>; + }; + + fcpvi1: fcp@fe9bf000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 610>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + + csi20: csi2@fea80000 { + compatible = "renesas,r8a774e1-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774e1-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; }; hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a774e1-hdmi", + "renesas,rcar-gen3-hdmi"; reg = <0 0xfead0000 0 0x10000>; + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A774E1_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 729>; status = "disabled"; - /* placeholder */ - ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; }; port@1 { reg = <1>; }; port@2 { + /* HDMI sound */ reg = <2>; }; }; }; du: display@feb00000 { + compatible = "renesas,du-r8a774e1"; reg = <0 0xfeb00000 0 0x80000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.3"; status = "disabled"; - /* placeholder */ + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; + ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; + du_out_rgb: endpoint { + }; }; port@1 { reg = <1>; + du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; }; port@2 { reg = <2>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a774e1-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; }; }; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index b61666ed4b7..b64d7fbc1b3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -589,5 +589,15 @@ struct ccsr_serdes { u8 res5[0x19fc - 0xa00]; }; +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + #endif /*__ASSEMBLY__ */ #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index b24f38cac90..bd41df1be44 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2021 NXP * Copyright 2015 Freescale Semiconductor */ @@ -16,6 +16,7 @@ #include <asm/arch/immap_lsch3.h> #endif #endif +#include <asm/arch/svr.h> #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE #define gur_in32(a) in_le32(a) @@ -77,46 +78,17 @@ enum boot_src get_boot_src(void); #endif #endif #define SVR_WO_E 0xFFFFFE -#define SVR_LS1012A 0x870400 -#define SVR_LS1043A 0x879200 -#define SVR_LS1023A 0x879208 -/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ -#define SVR_LS1043A_P23 0x879202 -#define SVR_LS1023A_P23 0x87920A -#define SVR_LS1017A 0x870B24 -#define SVR_LS1018A 0x870B20 -#define SVR_LS1027A 0x870B04 -#define SVR_LS1028A 0x870B00 -#define SVR_LS1046A 0x870700 -#define SVR_LS1026A 0x870708 -#define SVR_LS1048A 0x870320 -#define SVR_LS1084A 0x870302 -#define SVR_LS1088A 0x870300 -#define SVR_LS1044A 0x870322 -#define SVR_LS2045A 0x870120 -#define SVR_LS2080A 0x870110 -#define SVR_LS2085A 0x870100 -#define SVR_LS2040A 0x870130 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 -#define SVR_LX2160A 0x873600 -#define SVR_LX2120A 0x873620 -#define SVR_LX2080A 0x873602 -#define SVR_LX2162A 0x873608 -#define SVR_LX2122A 0x873628 -#define SVR_LX2082A 0x87360A #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#define SVR_WO_CE 0xFFFFEE +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE) +#else +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #endif #ifdef CONFIG_ARCH_LS1028A #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 36f36699a7c..b36b6d3889f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015-2020 NXP + * Copyright 2015-2021 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -103,7 +103,7 @@ #define FSL_DPAA2_STREAM_ID_END 63 /* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */ -#define FSL_ECAM_STREAM_ID_START 32 +#define FSL_ECAM_STREAM_ID_START 41 #define FSL_ECAM_STREAM_ID_END 63 #define FSL_SEC_STREAM_ID 64 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/svr.h b/arch/arm/include/asm/arch-fsl-layerscape/svr.h new file mode 100644 index 00000000000..e37c4a88b54 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/svr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ + +#define SVR_LS1012A 0x870400 +#define SVR_LS1043A 0x879200 +#define SVR_LS1023A 0x879208 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ +#define SVR_LS1043A_P23 0x879202 +#define SVR_LS1023A_P23 0x87920A +#define SVR_LS1017A 0x870B24 +#define SVR_LS1018A 0x870B20 +#define SVR_LS1027A 0x870B04 +#define SVR_LS1028A 0x870B00 +#define SVR_LS1046A 0x870700 +#define SVR_LS1026A 0x870708 +#define SVR_LS1048A 0x870320 +#define SVR_LS1084A 0x870302 +#define SVR_LS1088A 0x870300 +#define SVR_LS1044A 0x870322 +#define SVR_LS2045A 0x870120 +#define SVR_LS2080A 0x870110 +#define SVR_LS2085A 0x870100 +#define SVR_LS2040A 0x870130 +#define SVR_LS2088A 0x870900 +#define SVR_LS2084A 0x870910 +#define SVR_LS2048A 0x870920 +#define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870918 +#define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873600 +#define SVR_LX2120A 0x873620 +#define SVR_LX2080A 0x873602 +#define SVR_LX2162A 0x873608 +#define SVR_LX2122A 0x873628 +#define SVR_LX2082A 0x87360A + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h index dad181e7abd..517652b5d0f 100644 --- a/arch/arm/include/asm/arch-ls102xa/gpio.h +++ b/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -13,4 +13,20 @@ #ifndef __ASM_ARCH_LS102XA_GPIO_H_ #define __ASM_ARCH_LS102XA_GPIO_H_ +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + +struct mpc8xxx_gpio_plat { + ulong addr; + ulong size; + uint ngpios; +}; + #endif diff --git a/arch/arm/include/asm/arch-ls102xa/svr.h b/arch/arm/include/asm/arch-ls102xa/svr.h new file mode 100644 index 00000000000..52b27e2d67e --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/svr.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_LS102X_SVR_H_ +#define _ASM_LS102X_SVR_H_ + +#define SVR_LS102XA 0 +#define SVR_VAR_PER_SHIFT 8 +#define SVR_LS102XA_MASK 0x700 + +#endif /* _ASM_LS102X_SVR_H_ */ diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 0ef6cf619b4..b95c8e8d29e 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -60,11 +60,21 @@ choice prompt "Renesas ARM64 SoCs board select" optional +config TARGET_BEACON_RZG2H + bool "Beacon EmbeddedWorks RZ/G2H Dev Kit" + select R8A774E1 + select PINCTRL_PFC_R8A774E1 + config TARGET_BEACON_RZG2M bool "Beacon EmbeddedWorks RZ/G2M Dev Kit" select R8A774A1 select PINCTRL_PFC_R8A774A1 +config TARGET_BEACON_RZG2N + bool "Beacon EmbeddedWorks RZ/G2N Dev Kit" + select R8A774B1 + select PINCTRL_PFC_R8A774B1 + config TARGET_CONDOR bool "Condor board" imply R8A77980 diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 54c7fd9522a..c1a37706710 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -256,6 +256,10 @@ config TARGET_KMP204X bool "Support kmp204x" select VENDOR_KM +config TARGET_KMCENT2 + bool "Support kmcent2" + select VENDOR_KM + config TARGET_XPEDITE520X bool "Support xpedite520x" select ARCH_MPC8548 diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 2c378b76158..52299499519 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -390,7 +390,7 @@ int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn) return -1; sizebit = __ilog2_roundup_64(size); - size = 1 << sizebit; + size = 1ull << sizebit; debug("min start_addr is %llx\n", min_addr); debug("max end_addr is %llx\n", max_addr); debug("size found is %llx\n", size); diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 266d345f720..3ecda365387 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_KMCENT2) += kmcent2.dtb dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb diff --git a/arch/powerpc/dts/elo3-dma-0.dtsi b/arch/powerpc/dts/elo3-dma-0.dtsi new file mode 100644 index 00000000000..c3f77372562 --- /dev/null +++ b/arch/powerpc/dts/elo3-dma-0.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + */ + +dma0: dma@100300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,elo3-dma"; + reg = <0x100300 0x4>, + <0x100600 0x4>; + ranges = <0x0 0x100100 0x500>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <28 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <29 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <30 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <31 2 0 0>; + }; + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <76 2 0 0>; + }; + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <77 2 0 0>; + }; + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <78 2 0 0>; + }; + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <79 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/elo3-dma-1.dtsi b/arch/powerpc/dts/elo3-dma-1.dtsi new file mode 100644 index 00000000000..a61c88649ca --- /dev/null +++ b/arch/powerpc/dts/elo3-dma-1.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ] + * + * Copyright 2013 Freescale Semiconductor Inc. + */ + +dma1: dma@101300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,elo3-dma"; + reg = <0x101300 0x4>, + <0x101600 0x4>; + ranges = <0x0 0x101100 0x500>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <32 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <33 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <34 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <35 2 0 0>; + }; + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <80 2 0 0>; + }; + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <81 2 0 0>; + }; + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <82 2 0 0>; + }; + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <83 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi new file mode 100644 index 00000000000..ab76a9f1226 --- /dev/null +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2021 Niel Fourie <lusus@denx.de> + */ + +#include <config.h> + +/ { + + aliases { + spi0 = "/soc@ffe000000/spi@110000"; + i2c0 = "/soc@ffe000000/i2c@118000"; + i2c1 = "/soc@ffe000000/i2c@118000/mux@70/i2c@0"; + i2c2 = "/soc@ffe000000/i2c@118000/mux@70/i2c@1"; + i2c3 = "/soc@ffe000000/i2c@118000/mux@70/i2c@7"; + i2c4 = "/soc@ffe000000/i2c@118100"; + /delete-property/ pci1; + /delete-property/ pci2; + /delete-property/ pci3; + }; + + chosen { + stdout-path = "/soc@ffe000000/serial@11c500"; + }; + + soc@ffe000000 { + u-boot,dm-pre-reloc; + spi@110000 { + /* This documents where km_fpgacfg should be appear */ + fpga@0 { + compatible = "keymile,fpga-conf"; + reg = <0>; + spi-max-frequency = <25000000>; + }; + }; + + sdhc@114000 { + status = "okay"; + }; + + i2c@118000 { + u-boot,dm-pre-reloc; + mux@70 { + i2c@1 { /* IVM bus */ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + serial@11c500 { + u-boot,dm-pre-reloc; + clock-frequency = <200000000>; + }; + + fman@400000 { + ethernet@e0000 { + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-connection-type = "sgmii"; + }; + + ethernet@e8000 { + phy-connection-type = "rgmii-id"; + }; + }; + + }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t104x"; + law_trgt_if = <0>; + }; + + binman { + filename = "u-boot-with-dtb.bin"; + skip-at-start = <CONFIG_SYS_TEXT_BASE>; + sort-by-offset; + pad-byte = <0xff>; + size = <CONFIG_SYS_MONITOR_LEN>; + + u-boot-with-ucode-ptr { + offset = <CONFIG_SYS_TEXT_BASE>; + optional-ucode; + }; + + u-boot-dtb-with-ucode { + align = <256>; + }; + powerpc-mpc85xx-bootpg-resetvec { + offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmcent2.dts b/arch/powerpc/dts/kmcent2.dts new file mode 100644 index 00000000000..5d23ecb34bf --- /dev/null +++ b/arch/powerpc/dts/kmcent2.dts @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS + * + * (C) Copyright 2016 + * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com + * + * Copyright 2014 - 2015 Freescale Semiconductor Inc. + */ + +/include/ "t104xsi-pre.dtsi" + +/ { + model = "keymile,kmcent2"; + compatible = "keymile,kmcent2"; + + aliases { + front_phy = &front_phy; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + bman_fbpr: bman-fbpr { + size = <0 0x1000000>; + alignment = <0 0x1000000>; + }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; + }; + + ifc: localbus@ffe124000 { + reg = <0xf 0xfe124000 0 0x2000>; + ranges = <0 0 0xf 0xe8000000 0x04000000 + 1 0 0xf 0xfa000000 0x00010000 + 2 0 0xf 0xfb000000 0x00010000 + 4 0 0xf 0xc0000000 0x08000000 + 6 0 0xf 0xd0000000 0x08000000 + 7 0 0xf 0xd8000000 0x08000000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x04000000>; + bank-width = <2>; + device-width = <2>; + }; + + nand@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x1 0x0 0x10000>; + }; + + board-control@2,0 { + compatible = "keymile,qriox"; + reg = <0x2 0x0 0x80>; + }; + + chassis-mgmt@6,0 { + compatible = "keymile,bfticu"; + reg = <6 0 0x100>; + interrupt-controller; + interrupt-parent = <&mpic>; + interrupts = <11 1 0 0>; + #interrupt-cells = <1>; + }; + + }; + + memory { + device_type = "memory"; + }; + + dcsr: dcsr@f00000000 { + ranges = <0x00000000 0xf 0x00000000 0x01072000>; + }; + + bportals: bman-portals@ff4000000 { + ranges = <0x0 0xf 0xf4000000 0x2000000>; + }; + + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + + spi@110000 { + network-clock@1 { + compatible = "zarlink,zl30364"; + reg = <1>; + spi-max-frequency = <1000000>; + }; + }; + + sdhc@114000 { + status = "disabled"; + }; + + i2c@118000 { + clock-frequency = <100000>; + + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@54 { + compatible = "atmel,24c02"; + reg = <0x54>; + pagesize = <2>; + read-only; + label = "ddr3-spd"; + }; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + temp-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + label = "SENSOR_0"; + }; + temp-sensor@4a { + compatible = "national,lm75"; + reg = <0x4a>; + label = "SENSOR_2"; + }; + temp-sensor@4b { + compatible = "national,lm75"; + reg = <0x4b>; + label = "SENSOR_3"; + }; + }; + }; + }; + + i2c@118100 { + clock-frequency = <100000>; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; + }; + + i2c@119000 { + status = "disabled"; + }; + + i2c@119100 { + status = "disabled"; + }; + + serial2: serial@11d500 { + status = "disabled"; + }; + + serial3: serial@11d600 { + status = "disabled"; + }; + + usb0: usb@210000 { + status = "disabled"; + }; + usb1: usb@211000 { + status = "disabled"; + }; + + display@180000 { + status = "disabled"; + }; + + sata@220000 { + status = "disabled"; + }; + sata@221000 { + status = "disabled"; + }; + + fman@400000 { + ethernet@e0000 { + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@e2000 { + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@e4000 { + status = "disabled"; + }; + + ethernet@e6000 { + status = "disabled"; + }; + + ethernet@e8000 { + phy-handle = <&front_phy>; + phy-mode = "rgmii-id"; + }; + + mdio0: mdio@fc000 { + front_phy: ethernet-phy@11 { + reg = <0x11>; + }; + }; + }; + }; + + pci0: pcie@ffe240000 { + reg = <0xf 0xfe240000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 + 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci1: pcie@ffe250000 { + status = "disabled"; + reg = <0xf 0xfe250000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 + 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe260000 { + status = "disabled"; + reg = <0xf 0xfe260000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci3: pcie@ffe270000 { + status = "disabled"; + reg = <0xf 0xfe270000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + qe: qe@ffe140000 { + ranges = <0x0 0xf 0xfe140000 0x40000>; + reg = <0xf 0xfe140000 0 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + + si1: si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram1: siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + ucc_hdlc: ucc@2000 { + device_type = "hdlc"; + compatible = "fsl,ucc-hdlc"; + rx-clock-name = "clk9"; + tx-clock-name = "clk9"; + fsl,hdlc-bus; + }; + }; +}; + +#include "t1040si-post.dtsi" diff --git a/arch/powerpc/dts/qoriq-bman1.dtsi b/arch/powerpc/dts/qoriq-bman1.dtsi new file mode 100644 index 00000000000..d6164bac8ac --- /dev/null +++ b/arch/powerpc/dts/qoriq-bman1.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ BMan device tree stub [ controller @ offset 0x31a000 ] + * + * Copyright 2011 - 2014 Freescale Semiconductor Inc. + */ + +bman: bman@31a000 { + compatible = "fsl,bman"; + reg = <0x31a000 0x1000>; + interrupts = <16 2 1 2>; + fsl,bman-portals = <&bportals>; + memory-region = <&bman_fbpr>; +}; diff --git a/arch/powerpc/dts/qoriq-duart-0.dtsi b/arch/powerpc/dts/qoriq-duart-0.dtsi new file mode 100644 index 00000000000..0ac48438408 --- /dev/null +++ b/arch/powerpc/dts/qoriq-duart-0.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +serial0: serial@11c500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x11c500 0x100>; + clock-frequency = <0>; + interrupts = <36 2 0 0>; +}; + +serial1: serial@11c600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x11c600 0x100>; + clock-frequency = <0>; + interrupts = <36 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-duart-1.dtsi b/arch/powerpc/dts/qoriq-duart-1.dtsi new file mode 100644 index 00000000000..c712146aa6f --- /dev/null +++ b/arch/powerpc/dts/qoriq-duart-1.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +serial2: serial@11d500 { + cell-index = <2>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x11d500 0x100>; + clock-frequency = <0>; + interrupts = <37 2 0 0>; +}; + +serial3: serial@11d600 { + cell-index = <3>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x11d600 0x100>; + clock-frequency = <0>; + interrupts = <37 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-esdhc-0.dtsi b/arch/powerpc/dts/qoriq-esdhc-0.dtsi new file mode 100644 index 00000000000..dd24a49095f --- /dev/null +++ b/arch/powerpc/dts/qoriq-esdhc-0.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +sdhc: sdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + interrupts = <48 2 0 0>; + clock-frequency = <0>; +}; diff --git a/arch/powerpc/dts/qoriq-espi-0.dtsi b/arch/powerpc/dts/qoriq-espi-0.dtsi new file mode 100644 index 00000000000..e87e6dd49b7 --- /dev/null +++ b/arch/powerpc/dts/qoriq-espi-0.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +spi@110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8536-espi"; + reg = <0x110000 0x1000>; + interrupts = <53 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-mpic.dtsi b/arch/powerpc/dts/qoriq-mpic.dtsi new file mode 100644 index 00000000000..bec7c04e69b --- /dev/null +++ b/arch/powerpc/dts/qoriq-mpic.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; +}; + +timer@41100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x41100 0x100 0x41300 4>; + interrupts = <0 0 3 0 + 1 0 3 0 + 2 0 3 0 + 3 0 3 0>; +}; + +msi0: msi@41600 { + compatible = "fsl,mpic-msi"; + reg = <0x41600 0x200 0x44140 4>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 0 0 + 0xe1 0 0 0 + 0xe2 0 0 0 + 0xe3 0 0 0 + 0xe4 0 0 0 + 0xe5 0 0 0 + 0xe6 0 0 0 + 0xe7 0 0 0>; +}; + +msi1: msi@41800 { + compatible = "fsl,mpic-msi"; + reg = <0x41800 0x200 0x45140 4>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe8 0 0 0 + 0xe9 0 0 0 + 0xea 0 0 0 + 0xeb 0 0 0 + 0xec 0 0 0 + 0xed 0 0 0 + 0xee 0 0 0 + 0xef 0 0 0>; +}; + +msi2: msi@41a00 { + compatible = "fsl,mpic-msi"; + reg = <0x41a00 0x200 0x46140 4>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xf0 0 0 0 + 0xf1 0 0 0 + 0xf2 0 0 0 + 0xf3 0 0 0 + 0xf4 0 0 0 + 0xf5 0 0 0 + 0xf6 0 0 0 + 0xf7 0 0 0>; +}; + +timer@42100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x42100 0x100 0x42300 4>; + interrupts = <4 0 3 0 + 5 0 3 0 + 6 0 3 0 + 7 0 3 0>; +}; diff --git a/arch/powerpc/dts/qoriq-qman3.dtsi b/arch/powerpc/dts/qoriq-qman3.dtsi new file mode 100644 index 00000000000..b1f8a777a2c --- /dev/null +++ b/arch/powerpc/dts/qoriq-qman3.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ QMan rev3 device tree stub [ controller @ offset 0x318000 ] + * + * Copyright 2014 Freescale Semiconductor Inc. + */ + +qman: qman@318000 { + compatible = "fsl,qman"; + reg = <0x318000 0x2000>; + interrupts = <16 2 1 3>; + fsl,qman-portals = <&qportals>; + memory-region = <&qman_fqd &qman_pfdr>; +}; diff --git a/arch/powerpc/dts/qoriq-sata2-0.dtsi b/arch/powerpc/dts/qoriq-sata2-0.dtsi new file mode 100644 index 00000000000..385b91784d2 --- /dev/null +++ b/arch/powerpc/dts/qoriq-sata2-0.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +sata@220000 { + compatible = "fsl,pq-sata-v2"; + reg = <0x220000 0x1000>; + interrupts = <68 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-sata2-1.dtsi b/arch/powerpc/dts/qoriq-sata2-1.dtsi new file mode 100644 index 00000000000..d72dd39e02d --- /dev/null +++ b/arch/powerpc/dts/qoriq-sata2-1.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +sata@221000 { + compatible = "fsl,pq-sata-v2"; + reg = <0x221000 0x1000>; + interrupts = <69 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-sec5.0-0.dtsi b/arch/powerpc/dts/qoriq-sec5.0-0.dtsi new file mode 100644 index 00000000000..af0bb9dd6ed --- /dev/null +++ b/arch/powerpc/dts/qoriq-sec5.0-0.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ] + * + * Copyright 2012 Freescale Semiconductor Inc. + */ + +crypto: crypto@300000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <5>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x300000 0x10000>; + ranges = <0 0x300000 0x10000>; + interrupts = <92 2 0 0>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <88 2 0 0>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <89 2 0 0>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <90 2 0 0>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = <91 2 0 0>; + }; + + rtic@6000 { + compatible = "fsl,sec-v5.0-rtic", + "fsl,sec-v4.0-rtic"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x6000 0x100>; + ranges = <0x0 0x6100 0xe00>; + + rtic_a: rtic-a@0 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x00 0x20 0x100 0x80>; + }; + + rtic_b: rtic-b@20 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x20 0x20 0x200 0x80>; + }; + + rtic_c: rtic-c@40 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x40 0x20 0x300 0x80>; + }; + + rtic_d: rtic-d@60 { + compatible = "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x60 0x20 0x500 0x80>; + }; + }; +}; + +sec_mon: sec_mon@314000 { + compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; + reg = <0x314000 0x1000>; + interrupts = <93 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi b/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi new file mode 100644 index 00000000000..ee135c67ca2 --- /dev/null +++ b/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +usb@211000 { + compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; + reg = <0x211000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <45 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi b/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi new file mode 100644 index 00000000000..8579cc1e061 --- /dev/null +++ b/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +usb@210000 { + compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; + reg = <0x210000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <44 0x2 0 0>; +}; diff --git a/arch/powerpc/dts/t1040si-post.dtsi b/arch/powerpc/dts/t1040si-post.dtsi new file mode 100644 index 00000000000..c71cf33f8a9 --- /dev/null +++ b/arch/powerpc/dts/t1040si-post.dtsi @@ -0,0 +1,727 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * T1040 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 - 2014 Freescale Semiconductor Inc. + */ + +#include <dt-bindings/thermal/thermal.h> + +&bman_fbpr { + compatible = "fsl,bman-fbpr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,ifc", "simple-bus"; + interrupts = <25 2 0 0>; +}; + +&pci0 { + compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + interrupts = <20 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <20 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 40 1 0 0 + 0000 0 0 2 &mpic 1 1 0 0 + 0000 0 0 3 &mpic 2 1 0 0 + 0000 0 0 4 &mpic 3 1 0 0 + >; + }; +}; + +&pci1 { + compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0 0xff>; + interrupts = <21 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <21 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 41 1 0 0 + 0000 0 0 2 &mpic 5 1 0 0 + 0000 0 0 3 &mpic 6 1 0 0 + 0000 0 0 4 &mpic 7 1 0 0 + >; + }; +}; + +&pci2 { + compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + interrupts = <22 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <22 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 42 1 0 0 + 0000 0 0 2 &mpic 9 1 0 0 + 0000 0 0 3 &mpic 10 1 0 0 + 0000 0 0 4 &mpic 11 1 0 0 + >; + }; +}; + +&pci3 { + compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + interrupts = <23 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <23 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 43 1 0 0 + 0000 0 0 2 &mpic 0 1 0 0 + 0000 0 0 3 &mpic 4 1 0 0 + 0000 0 0 4 &mpic 8 1 0 0 + >; + }; +}; + +&dcsr { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,dcsr", "simple-bus"; + + dcsr-epu@0 { + compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu"; + interrupts = <52 2 0 0 + 84 2 0 0 + 85 2 0 0>; + reg = <0x0 0x1000>; + }; + dcsr-npc { + compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc"; + reg = <0x1000 0x1000 0x1002000 0x10000>; + }; + dcsr-nxc@2000 { + compatible = "fsl,dcsr-nxc"; + reg = <0x2000 0x1000>; + }; + dcsr-corenet { + compatible = "fsl,dcsr-corenet"; + reg = <0x8000 0x1000 0x1A000 0x1000>; + }; + dcsr-dpaa@9000 { + compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa"; + reg = <0x9000 0x1000>; + }; + dcsr-ocn@11000 { + compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn"; + reg = <0x11000 0x1000>; + }; + dcsr-ddr@12000 { + compatible = "fsl,dcsr-ddr"; + dev-handle = <&ddr1>; + reg = <0x12000 0x1000>; + }; + dcsr-nal@18000 { + compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal"; + reg = <0x18000 0x1000>; + }; + dcsr-rcpm@22000 { + compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm"; + reg = <0x22000 0x1000>; + }; + dcsr-snpc@30000 { + compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; + reg = <0x30000 0x1000 0x1022000 0x10000>; + }; + dcsr-snpc@31000 { + compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; + reg = <0x31000 0x1000 0x1042000 0x10000>; + }; + dcsr-cpu-sb-proxy@100000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu0>; + reg = <0x100000 0x1000 0x101000 0x1000>; + }; + dcsr-cpu-sb-proxy@108000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu1>; + reg = <0x108000 0x1000 0x109000 0x1000>; + }; + dcsr-cpu-sb-proxy@110000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu2>; + reg = <0x110000 0x1000 0x111000 0x1000>; + }; + dcsr-cpu-sb-proxy@118000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu3>; + reg = <0x118000 0x1000 0x119000 0x1000>; + }; +}; + +&bportals { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + + bman-portal@0 { + compatible = "fsl,bman-portal"; + reg = <0x0 0x4000>, <0x1000000 0x1000>; + interrupts = <105 2 0 0>; + }; + bman-portal@4000 { + compatible = "fsl,bman-portal"; + reg = <0x4000 0x4000>, <0x1001000 0x1000>; + interrupts = <107 2 0 0>; + }; + bman-portal@8000 { + compatible = "fsl,bman-portal"; + reg = <0x8000 0x4000>, <0x1002000 0x1000>; + interrupts = <109 2 0 0>; + }; + bman-portal@c000 { + compatible = "fsl,bman-portal"; + reg = <0xc000 0x4000>, <0x1003000 0x1000>; + interrupts = <111 2 0 0>; + }; + bman-portal@10000 { + compatible = "fsl,bman-portal"; + reg = <0x10000 0x4000>, <0x1004000 0x1000>; + interrupts = <113 2 0 0>; + }; + bman-portal@14000 { + compatible = "fsl,bman-portal"; + reg = <0x14000 0x4000>, <0x1005000 0x1000>; + interrupts = <115 2 0 0>; + }; + bman-portal@18000 { + compatible = "fsl,bman-portal"; + reg = <0x18000 0x4000>, <0x1006000 0x1000>; + interrupts = <117 2 0 0>; + }; + bman-portal@1c000 { + compatible = "fsl,bman-portal"; + reg = <0x1c000 0x4000>, <0x1007000 0x1000>; + interrupts = <119 2 0 0>; + }; + bman-portal@20000 { + compatible = "fsl,bman-portal"; + reg = <0x20000 0x4000>, <0x1008000 0x1000>; + interrupts = <121 2 0 0>; + }; + bman-portal@24000 { + compatible = "fsl,bman-portal"; + reg = <0x24000 0x4000>, <0x1009000 0x1000>; + interrupts = <123 2 0 0>; + }; +}; + +&qportals { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + + qportal0: qman-portal@0 { + compatible = "fsl,qman-portal"; + reg = <0x0 0x4000>, <0x1000000 0x1000>; + interrupts = <104 0x2 0 0>; + cell-index = <0x0>; + }; + qportal1: qman-portal@4000 { + compatible = "fsl,qman-portal"; + reg = <0x4000 0x4000>, <0x1001000 0x1000>; + interrupts = <106 0x2 0 0>; + cell-index = <0x1>; + }; + qportal2: qman-portal@8000 { + compatible = "fsl,qman-portal"; + reg = <0x8000 0x4000>, <0x1002000 0x1000>; + interrupts = <108 0x2 0 0>; + cell-index = <0x2>; + }; + qportal3: qman-portal@c000 { + compatible = "fsl,qman-portal"; + reg = <0xc000 0x4000>, <0x1003000 0x1000>; + interrupts = <110 0x2 0 0>; + cell-index = <0x3>; + }; + qportal4: qman-portal@10000 { + compatible = "fsl,qman-portal"; + reg = <0x10000 0x4000>, <0x1004000 0x1000>; + interrupts = <112 0x2 0 0>; + cell-index = <0x4>; + }; + qportal5: qman-portal@14000 { + compatible = "fsl,qman-portal"; + reg = <0x14000 0x4000>, <0x1005000 0x1000>; + interrupts = <114 0x2 0 0>; + cell-index = <0x5>; + }; + qportal6: qman-portal@18000 { + compatible = "fsl,qman-portal"; + reg = <0x18000 0x4000>, <0x1006000 0x1000>; + interrupts = <116 0x2 0 0>; + cell-index = <0x6>; + }; + qportal7: qman-portal@1c000 { + compatible = "fsl,qman-portal"; + reg = <0x1c000 0x4000>, <0x1007000 0x1000>; + interrupts = <118 0x2 0 0>; + cell-index = <0x7>; + }; + qportal8: qman-portal@20000 { + compatible = "fsl,qman-portal"; + reg = <0x20000 0x4000>, <0x1008000 0x1000>; + interrupts = <120 0x2 0 0>; + cell-index = <0x8>; + }; + qportal9: qman-portal@24000 { + compatible = "fsl,qman-portal"; + reg = <0x24000 0x4000>, <0x1009000 0x1000>; + interrupts = <122 0x2 0 0>; + cell-index = <0x9>; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + soc-sram-error { + compatible = "fsl,soc-sram-error"; + interrupts = <16 2 1 29>; + }; + + corenet-law@0 { + compatible = "fsl,corenet-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <16>; + }; + + ddr1: memory-controller@8000 { + compatible = "fsl,qoriq-memory-controller-v5.0", + "fsl,qoriq-memory-controller"; + reg = <0x8000 0x1000>; + interrupts = <16 2 1 23>; + }; + + cpc: l3-cache-controller@10000 { + compatible = "fsl,t1040-l3-cache-controller", "cache"; + reg = <0x10000 0x1000>; + interrupts = <16 2 1 27>; + }; + + corenet-cf@18000 { + compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; + reg = <0x18000 0x1000>; + interrupts = <16 2 1 31>; + fsl,ccf-num-csdids = <32>; + fsl,ccf-num-snoopids = <32>; + }; + + iommu@20000 { + compatible = "fsl,pamu-v1.0", "fsl,pamu"; + reg = <0x20000 0x1000>; + ranges = <0 0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = < + 24 2 0 0 + 16 2 1 30>; + pamu0: pamu@0 { + reg = <0 0x1000>; + fsl,primary-cache-geometry = <128 1>; + fsl,secondary-cache-geometry = <16 2>; + }; + }; + +/include/ "qoriq-mpic.dtsi" + + guts: global-utilities@e0000 { + compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0"; + reg = <0xe0000 0xe00>; + fsl,has-rstcr; + fsl,liodn-bits = <12>; + }; + +/include/ "qoriq-clockgen2.dtsi" + global-utilities@e1000 { + compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; + }; + + rcpm: global-utilities@e2000 { + compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1"; + reg = <0xe2000 0x1000>; + }; + + sfp: sfp@e8000 { + compatible = "fsl,t1040-sfp"; + reg = <0xe8000 0x1000>; + }; + + serdes: serdes@ea000 { + compatible = "fsl,t1040-serdes"; + reg = <0xea000 0x4000>; + }; + + tmu: tmu@f0000 { + compatible = "fsl,qoriq-tmu"; + reg = <0xf0000 0x1000>; + interrupts = <18 2 0 0>; + fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>; + fsl,tmu-calibration = <0x00000000 0x00000025 + 0x00000001 0x00000028 + 0x00000002 0x0000002d + 0x00000003 0x00000031 + 0x00000004 0x00000036 + 0x00000005 0x0000003a + 0x00000006 0x00000040 + 0x00000007 0x00000044 + 0x00000008 0x0000004a + 0x00000009 0x0000004f + 0x0000000a 0x00000054 + + 0x00010000 0x0000000d + 0x00010001 0x00000013 + 0x00010002 0x00000019 + 0x00010003 0x0000001f + 0x00010004 0x00000025 + 0x00010005 0x0000002d + 0x00010006 0x00000033 + 0x00010007 0x00000043 + 0x00010008 0x0000004b + 0x00010009 0x00000053 + + 0x00020000 0x00000010 + 0x00020001 0x00000017 + 0x00020002 0x0000001f + 0x00020003 0x00000029 + 0x00020004 0x00000031 + 0x00020005 0x0000003c + 0x00020006 0x00000042 + 0x00020007 0x0000004d + 0x00020008 0x00000056 + + 0x00030000 0x00000012 + 0x00030001 0x0000001d>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&tmu 2>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert>; + cooling-device = + <&cpu1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map2 { + trip = <&cpu_alert>; + cooling-device = + <&cpu2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map3 { + trip = <&cpu_alert>; + cooling-device = + <&cpu3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + scfg: global-utilities@fc000 { + compatible = "fsl,t1040-scfg"; + reg = <0xfc000 0x1000>; + }; + +/include/ "elo3-dma-0.dtsi" +/include/ "elo3-dma-1.dtsi" +/include/ "qoriq-espi-0.dtsi" + spi@110000 { + fsl,espi-num-chipselects = <4>; + }; + +/include/ "qoriq-esdhc-0.dtsi" + sdhc@114000 { + compatible = "fsl,t1040-esdhc", "fsl,esdhc"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ + sdhci,auto-cmd12; + }; +/include/ "qoriq-i2c-0.dtsi" +/include/ "qoriq-i2c-1.dtsi" +/include/ "qoriq-duart-0.dtsi" +/include/ "qoriq-duart-1.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" +/include/ "qoriq-usb2-mph-0.dtsi" + usb0: usb@210000 { + compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ + phy_type = "utmi"; + port0; + }; +/include/ "qoriq-usb2-dr-0.dtsi" + usb1: usb@211000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ + dr_mode = "host"; + phy_type = "utmi"; + }; + + display@180000 { + compatible = "fsl,t1040-diu", "fsl,diu"; + reg = <0x180000 1000>; + interrupts = <74 2 0 0>; + }; + +/include/ "qoriq-sata2-0.dtsi" + sata@220000 { + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ + }; +/include/ "qoriq-sata2-1.dtsi" + sata@221000 { + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ + }; +/include/ "qoriq-sec5.0-0.dtsi" +/include/ "qoriq-qman3.dtsi" +/include/ "qoriq-bman1.dtsi" + +/include/ "qoriq-fman3l-0.dtsi" +/include/ "qoriq-fman3-0-1g-0.dtsi" +/include/ "qoriq-fman3-0-1g-1.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-1g-4.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + mdio@fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@fd000 { + status = "disabled"; + }; + }; + + seville_switch: ethernet-switch@800000 { + compatible = "mscc,vsc9953-switch"; + reg = <0x800000 0x290000>; + interrupts = <26 2 0 0>; + interrupt-names = "xtr"; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + seville_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + seville_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + seville_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + seville_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + seville_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + + seville_port5: port@5 { + reg = <5>; + status = "disabled"; + }; + + seville_port6: port@6 { + reg = <6>; + status = "disabled"; + }; + + seville_port7: port@7 { + reg = <7>; + status = "disabled"; + }; + + seville_port8: port@8 { + reg = <8>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + seville_port9: port@9 { + reg = <9>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + }; + }; +}; + +&qe { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78 + }; + + ucc@2000 { + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + }; + + ucc@2200 { + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x6000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x6000>; + }; + }; +}; diff --git a/arch/powerpc/dts/t104xsi-pre.dtsi b/arch/powerpc/dts/t104xsi-pre.dtsi new file mode 100644 index 00000000000..025872cfea1 --- /dev/null +++ b/arch/powerpc/dts/t104xsi-pre.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * T1040/T1042 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013-2014 Freescale Semiconductor Inc. + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + aliases { + ccsr = &soc; + dcsr = &dcsr; + + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + pci3 = &pci3; + usb0 = &usb0; + usb1 = &usb1; + sdhc = &sdhc; + + crypto = &crypto; + + fman0 = &fman0; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + ethernet4 = &enet4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + clocks = <&clockgen 1 0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + next-level-cache = <&cpc>; + }; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + clocks = <&clockgen 1 1>; + next-level-cache = <&L2_2>; + #cooling-cells = <2>; + L2_2: l2-cache { + next-level-cache = <&cpc>; + }; + }; + cpu2: PowerPC,e5500@2 { + device_type = "cpu"; + reg = <2>; + clocks = <&clockgen 1 2>; + next-level-cache = <&L2_3>; + #cooling-cells = <2>; + L2_3: l2-cache { + next-level-cache = <&cpc>; + }; + }; + cpu3: PowerPC,e5500@3 { + device_type = "cpu"; + reg = <3>; + clocks = <&clockgen 1 3>; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + L2_4: l2-cache { + next-level-cache = <&cpc>; + }; + }; + }; +}; diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 609869c7154..a03f938d9f4 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -966,6 +966,19 @@ typedef struct immap { } immap_t; #endif +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + union { + u32 gpibe; + u8 res0[0xE8]; + }; +}; + #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) #define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) diff --git a/board/beacon/beacon-rzg2m/Kconfig b/board/beacon/beacon-rzg2m/Kconfig index c03857cf2fe..99c23a3d148 100644 --- a/board/beacon/beacon-rzg2m/Kconfig +++ b/board/beacon/beacon-rzg2m/Kconfig @@ -1,4 +1,4 @@ -if TARGET_BEACON_RZG2M +if TARGET_BEACON_RZG2H || TARGET_BEACON_RZG2M || TARGET_BEACON_RZG2N config SYS_SOC default "rmobile" diff --git a/board/beacon/beacon-rzg2m/MAINTAINERS b/board/beacon/beacon-rzg2m/MAINTAINERS index 3383a689368..45c269da723 100644 --- a/board/beacon/beacon-rzg2m/MAINTAINERS +++ b/board/beacon/beacon-rzg2m/MAINTAINERS @@ -4,3 +4,5 @@ S: Maintained F: board/beacon/beacon-rzg2m/ F: include/configs/beacon-rzg2m.h F: configs/r8a774a1_beacon_defconfig +F: configs/r8a774b1_beacon_defconfig +F: configs/r8a774e1_beacon_defconfig diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index e5906906f3a..6b7377c2007 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -114,6 +114,7 @@ config SYS_IVM_EEPROM_PAGE_LEN Page size of inventory in EEPROM. source "board/keymile/km83xx/Kconfig" +source "board/keymile/kmcent2/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/keymile/km_arm/Kconfig" diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index df507e27907..9c482d8454e 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; */ int set_km_env(void) { - uchar buf[32]; unsigned int pnvramaddr; unsigned int pram; unsigned int varaddr; @@ -49,10 +48,9 @@ int set_km_env(void) char *p; unsigned long rootfssize = 0; - pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - - CONFIG_KM_PNVRAM; - sprintf((char *)buf, "0x%x", pnvramaddr); - env_set("pnvramaddr", (char *)buf); + pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; + env_set_hex("pnvramaddr", pnvramaddr); /* try to read rootfssize (ram image) from environment */ p = env_get("rootfssize"); @@ -60,16 +58,14 @@ int set_km_env(void) strict_strtoul(p, 16, &rootfssize); pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + CONFIG_KM_PNVRAM) / 0x400; - sprintf((char *)buf, "0x%x", pram); - env_set("pram", (char *)buf); + env_set_ulong("pram", pram); - varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; - sprintf((char *)buf, "0x%x", varaddr); - env_set("varaddr", (char *)buf); + varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; + env_set_hex("varaddr", varaddr); kernelmem = gd->ram_size - 0x400 * pram; - sprintf((char *)buf, "0x%x", kernelmem); - env_set("kernelmem", (char *)buf); + env_set_hex("kernelmem", kernelmem); return 0; } @@ -243,7 +239,6 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc, p = env_get("hwkey"); if (p) rc = strict_strtoul(p, 16, &envhwkey); - if (rc != 0) { printf("strict_strtoul returns error: %d", rc); return rc; @@ -305,15 +300,11 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc, * set the values in environment variables. */ if (bid == ivmbid && hwkey == ivmhwkey) { - char buf[10]; - found = 1; envbid = bid; envhwkey = hwkey; - sprintf(buf, "%lx", bid); - env_set("boardid", buf); - sprintf(buf, "%lx", hwkey); - env_set("hwkey", buf); + env_set_hex("boardid", bid); + env_set_hex("hwkey", hwkey); } } /* end while( ! found ) */ } diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index 8251de4db8f..15a3c3797d1 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -136,6 +136,11 @@ int set_km_env(void); #define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); + int i2c_soft_read_pin(void); int i2c_make_abort(void); #endif /* __KEYMILE_COMMON_H */ diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index e989bf609fe..bc8ffd56e1c 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -321,6 +321,11 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset) process_mac(valbuf, page2, mac_address_offset, true); env_set((char *)"eth1addr", (char *)valbuf); } + if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) { + /* 3rd ethernet interface */ + process_mac(valbuf, page2, 2, true); + env_set((char *)"eth4addr", (char *)valbuf); + } return 0; } diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index 06a4e67881f..25937ee362f 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -5,15 +5,28 @@ */ #include <common.h> +#include <asm/io.h> #include <linux/bitops.h> #include "common.h" #include "qrio.h" +/* QRIO ID register offset */ +#define ID_REV_OFF 0x00 + /* QRIO GPIO register offsets */ #define DIRECT_OFF 0x18 #define GPRT_OFF 0x1c +void show_qrio(void) +{ + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + u16 id_rev = in_be16(qrio_base + ID_REV_OFF); + + printf("QRIO: id = %u, revision = %u\n", + (id_rev >> 8) & 0xff, id_rev & 0xff); +} + int qrio_get_gpio(u8 port_off, u8 gpio_nr) { u32 gprt; @@ -129,7 +142,7 @@ void qrio_prst(u8 bit, bool en, bool wden) void qrio_prstcfg(u8 bit, u8 mode) { - u32 prstcfg; + unsigned long prstcfg; u8 i; void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; @@ -137,9 +150,9 @@ void qrio_prstcfg(u8 bit, u8 mode) for (i = 0; i < 2; i++) { if (mode & (1 << i)) - set_bit(2 * bit + i, &prstcfg); + __set_bit(2 * bit + i, &prstcfg); else - clear_bit(2 * bit + i, &prstcfg); + __clear_bit(2 * bit + i, &prstcfg); } out_be32(qrio_base + PRSTCFG_OFF, prstcfg); diff --git a/board/keymile/common/qrio.h b/board/keymile/common/qrio.h index a04a73266fb..757bcbf2f3d 100644 --- a/board/keymile/common/qrio.h +++ b/board/keymile/common/qrio.h @@ -11,6 +11,7 @@ #define QRIO_GPIO_A 0x40 #define QRIO_GPIO_B 0x60 +void show_qrio(void); int qrio_get_gpio(u8 port_off, u8 gpio_nr); void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val); void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value); diff --git a/board/keymile/kmcent2/Kconfig b/board/keymile/kmcent2/Kconfig new file mode 100644 index 00000000000..848d230fbd5 --- /dev/null +++ b/board/keymile/kmcent2/Kconfig @@ -0,0 +1,17 @@ +if TARGET_KMCENT2 + +config SYS_BOARD + default "kmcent2" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmcent2" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_T1040 + select PHYS_64BIT + +endif diff --git a/board/keymile/kmcent2/MAINTAINERS b/board/keymile/kmcent2/MAINTAINERS new file mode 100644 index 00000000000..1426475556c --- /dev/null +++ b/board/keymile/kmcent2/MAINTAINERS @@ -0,0 +1,8 @@ +KMCENT2 BOARD +M: Niel Fourie <lusus@denx.de> +S: Maintained +F: board/keymile/kmcent2/ +F: include/configs/kmcent2.h +F: configs/kmcent2_defconfig +F: arch/powerpc/dts/kmcent2.dts +F: arch/powerpc/dts/kmcent2-u-boot.dtsi diff --git a/board/keymile/kmcent2/Makefile b/board/keymile/kmcent2/Makefile new file mode 100644 index 00000000000..6b26e861f67 --- /dev/null +++ b/board/keymile/kmcent2/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2016 Keymile AG +# Rainer Boschung <rainer.boschung@keymile.com> +# +# Copyright 2013 Freescale Semiconductor, Inc. +# + +obj-y += kmcent2.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +obj-y += ../common/common.o +obj-y += ../common/ivm.o +obj-y += ../common/qrio.o diff --git a/board/keymile/kmcent2/ddr.c b/board/keymile/kmcent2/ddr.c new file mode 100644 index 00000000000..4f778206fe9 --- /dev/null +++ b/board/keymile/kmcent2/ddr.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung <rainer.boschung@keymile.com> + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include <asm/fsl_law.h> +#include <asm/mmu.h> +#include <asm/mpc85xx_gpio.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <hwconfig.h> +#include <i2c.h> +#include <init.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8 +#define DQSn_START(n, start) ((start) << DQSn_POS(n)) + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + + /* 1/2 clk delay between wr command and data strobe */ + popts->write_data_delay = 4; + /* clk lauched 1/2 applied cylcle after address command */ + popts->clk_adjust = 4; + /* 1T timing: command/address held for only 1 cycle */ + popts->twot_en = 0; + popts->threet_en = 0; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x3b; + + /* we have only one module, half str should be OK */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + /* set for DDR3-1600 */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x7; + /* DQS write leveling start time according layout */ + popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) | + DQSn_START(2, 0x06) | + DQSn_START(3, 0x07) | + DQSn_START(4, 0x07)); + popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) | + DQSn_START(6, 0x08) | + DQSn_START(7, 0x08) | + DQSn_START(8, 0x08)); + + /* + * rtt and wtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +int dram_init(void) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c new file mode 100644 index 00000000000..4f5164e63ca --- /dev/null +++ b/board/keymile/kmcent2/kmcent2.c @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung <rainer.boschung@keymile.com> + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include <asm/cache.h> +#include <asm/fsl_fdt.h> +#include <asm/fsl_law.h> +#include <asm/fsl_liodn.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_serdes.h> +#include <asm/immap_85xx.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <fdt_support.h> +#include <fm_eth.h> +#include <hwconfig.h> +#include <image.h> +#include <linux/compiler.h> +#include <net.h> +#include <netdev.h> +#include <vsc9953.h> + +#include "../common/common.h" +#include "../common/qrio.h" + +DECLARE_GLOBAL_DATA_PTR; + +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + +int checkboard(void) +{ + printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME); + + return 0; +} + +#define RSTRQSR1_WDT_RR 0x00200000 +#define RSTRQSR1_SW_RR 0x00100000 + +int board_early_init_f(void) +{ + struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + bool cpuwd_flag = false; + + /* board specific IFC configuration: increased bus turnaround time */ + setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + + /* configure mode for uP reset request */ + qrio_uprstreq(UPREQ_CORE_RST); + + /* board only uses the DDR_MCK0, so disable the DDR_MCK1 */ + setbits_be32(&gur->ddrclkdr, 0x40000000); + + /* set reset reason according CPU register */ + if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) == + RSTRQSR1_WDT_RR) + cpuwd_flag = true; + + qrio_cpuwd_flag(cpuwd_flag); + /* clear CPU bits by writing 1 */ + setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR); + + /* configure PRST lines for the application: */ + /* + * ETHSW_DDR_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_ETHSW_DDR_RST, true); + /* + * XES_PHY_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_XES_PHY_RST, true); + /* + * ES_PHY_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_ES_PHY_RST, true); + /* + * EFE_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_EFE_RST, true); + /* + * BFTIC4_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_BFTIC4_RST, true); + /* + * DPAXE_RST: + * reset at power-up and unit reset only and enable WD on it + */ + qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_DPAXE_RST, true); + /* + * PEXSW_RST: + * reset at power-up and unit reset only, deassert reset w/o WD + */ + qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(KM_PEXSW_RST, false, false); + /* + * PEXSW_NT_RST: + * reset at power-up and unit reset only, deassert reset w/o WD + */ + qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(KM_PEXSW_NT_RST, false, false); + /* + * BOBCAT_RST: + * reset at power-up and unit reset only, deassert reset w/o WD + */ + qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(KM_BOBCAT_RST, false, false); + /* + * FEMT_RST: + * reset at power-up and unit reset only and enable WD + */ + qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_FEMT_RST, true); + /* + * FOAM_RST: + * reset at power-up and unit reset only and enable WD + */ + qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_FOAM_RST, true); + + return 0; +} + +int board_early_init_r(void) +{ + int ret = 0; + + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); + setup_qbman_portals(); + + qrio_set_leds(); + + /* enable Application Buffer */ + qrio_enable_app_buffer(); + + return ret; +} + +unsigned long get_serial_clock(unsigned long dummy) +{ + return (gd->bus_clk / 2); +} + +unsigned long get_board_sys_clk(unsigned long dummy) +{ + return 66666666; +} + +int misc_init_f(void) +{ + /* configure QRIO pis for i2c deblocking */ + i2c_deblock_gpio_cfg(); + + /* + * CFE_RST (front phy): + * reset at power-up, unit and core reset, deasset reset w/o WD + */ + qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + qrio_prst(KM_CFE_RST, false, false); + + /* + * ZL30158_RST (PTP clock generator): + * reset at power-up only, deassert reset and enable WD on it + */ + qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST); + qrio_prst(KM_ZL30158_RST, false, false); + + /* + * ZL30364_RST (EEC generator): + * reset at power-up only, deassert reset and enable WD on it + */ + qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST); + qrio_prst(KM_ZL30364_RST, false, false); + + return 0; +} + +#define USED_SRDS_BANK 0 +#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100 + +#define BRG01_IOCLK12 0x02000000 +#define EC2_GTX_CLK125 0x08000000 + +int misc_init_r(void) +{ + serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG; + ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* check SERDES bank 0 reference clock */ + u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0); + + if (actual & SRDS_PLLCR0_POFF) + printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK); + if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) { + printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n", + USED_SRDS_BANK, + serdes_clock_to_string(EXPECTED_SRDS_RFCK), + serdes_clock_to_string(actual)); + } + + /* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */ + out_be32(&scfg->qeioclkcr, + in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12); + + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, + CONFIG_PIGGY_MAC_ADDRESS_OFFSET); + + /* Fix polarity of Card Detect and Write Protect */ + out_be32(&gur->sdhcpcr, 0xFFFFFFFF); + + /* + * EC1 is disabled in our design, so we must explicitly set GTXCLKSEL + * to EC2 + */ + out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125); + + return 0; +} + +int hush_init_var(void) +{ + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return 0; +} + +int last_stage_init(void) +{ + const char *kmem; + /* DIP switch support on BFTIC */ + struct bfticu_iomap *bftic4 = + (struct bfticu_iomap *)SYS_BFTIC_BASE; + u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK; + + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + env_set("actual_bank", "0"); + } + + set_km_env(); + + /* + * bootm_size is used to fixup the FDT memory node + * set it to kernelmem that has the same value + */ + kmem = env_get("kernelmem"); + if (kmem) + env_set("bootm_size", kmem); + + return 0; +} + +void fdt_fixup_fman_mac_addresses(void *blob) +{ + int node, ret; + char path[24]; + unsigned char mac_addr[6]; + + /* + * Just the fm1-mac5 must be set by us, u-boot handle the 2 others, + * get the mac addr from env + */ + if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) { + printf("eth4addr env variable not defined\n"); + return; + } + + /* local management port */ + strcpy(path, "/soc/fman/ethernet@e8000"); + node = fdt_path_offset(blob, path); + if (node < 0) { + printf("no %s\n", path); + return; + } + + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("%s\n\terror setting local-mac-address property\n", + path); + } +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_liodn(blob); + + fdt_fixup_fman_mac_addresses(blob); + + if (hwconfig("qe-tdm")) + fdt_del_diu(blob); + return 0; +} + +/* DIC26_SELFTEST GPIO used to start factory test sw */ +#define SELFTEST_PORT QRIO_GPIO_A +#define SELFTEST_PIN 0 + +int post_hotkeys_pressed(void) +{ + qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN); + return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN); +} diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c new file mode 100644 index 00000000000..aa0f29f44fc --- /dev/null +++ b/board/keymile/kmcent2/law.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung <rainer.boschung@keymile.com> + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include <config.h> +#include <asm/fsl_law.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC), +/* other application LAW are not used in u-boot */ +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c new file mode 100644 index 00000000000..dbd3b9b064c --- /dev/null +++ b/board/keymile/kmcent2/tlb.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung <rainer.boschung@keymile.com> + * + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include <asm/mmu.h> +#include <asm/u-boot.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, + 0, 2, BOOKE_PAGESZ_128M, 1), + + /* *I*G* - PCI1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI1 I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), + /* QRIO */ + SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, + MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 11, BOOKE_PAGESZ_64K, 1), + /* MRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, + MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 12, BOOKE_PAGESZ_128M, 1), + /* BFTIC */ + SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS, + MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 13, BOOKE_PAGESZ_128M, 1), + /* + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so do not use them here!!. + */ + /* PAXE */ + SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, + MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 16, BOOKE_PAGESZ_128M, 1) +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile index 5d220f07447..147ef9872b8 100644 --- a/board/kontron/sl28/Makefile +++ b/board/kontron/sl28/Makefile @@ -4,7 +4,7 @@ ifndef CONFIG_SPL_BUILD obj-y += sl28.o cmds.o endif -obj-y += common.o ddr.o +obj-y += ddr.o ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c deleted file mode 100644 index 14704f70514..00000000000 --- a/board/kontron/sl28/common.c +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <common.h> -#include <asm/arch-fsl-layerscape/soc.h> - -int board_early_init_f(void) -{ - fsl_lsch3_early_init_f(); - return 0; -} diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 34f17b486bd..28e8c4c9543 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -19,6 +19,12 @@ DECLARE_GLOBAL_DATA_PTR; +int board_early_init_f(void) +{ + fsl_lsch3_early_init_f(); + return 0; +} + int board_init(void) { if (CONFIG_IS_ENABLED(FSL_CAAM)) diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index fa5829eee0b..0e6ad5f37e1 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -3,10 +3,36 @@ #include <common.h> #include <asm/io.h> #include <asm/spl.h> +#include <asm/arch-fsl-layerscape/fsl_serdes.h> +#include <asm/arch-fsl-layerscape/soc.h> #define DCFG_RCWSR25 0x160 #define GPINFO_HW_VARIANT_MASK 0xff +#define SERDES_LNDGCR0 0x1ea08c0 +#define LNDGCR0_PROTS_MASK GENMASK(11, 7) +#define LNDGCR0_PROTS_SATA (0x2 << 7) +#define SERDES_LNDGCR1 0x1ea08c4 +#define LNDGCR1_RDAT_INV BIT(31) + +/* + * On this board the SMARC PCIe lane D might be switched to SATA mode. This + * makes sense if this lane is connected to a Mini PCI slot and a mSATA card + * is plugged in. In this case, the RX pair is swapped and we need to invert + * the received data. + */ +static void fixup_sata_rx_polarity(void) +{ + u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK; + u32 tmp; + + if (prot == LNDGCR0_PROTS_SATA) { + tmp = in_le32(SERDES_LNDGCR1); + tmp |= LNDGCR1_RDAT_INV; + out_le32(SERDES_LNDGCR1, tmp); + } +} + int sl28_variant(void) { return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK; @@ -17,6 +43,10 @@ int board_fit_config_name_match(const char *name) int variant = sl28_variant(); switch (variant) { + case 1: + return strcmp(name, "fsl-ls1028a-kontron-sl28-var1"); + case 2: + return strcmp(name, "fsl-ls1028a-kontron-sl28-var2"); case 3: return strcmp(name, "fsl-ls1028a-kontron-sl28-var3"); case 4: @@ -30,3 +60,11 @@ void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = BOOT_DEVICE_SPI; } + +int board_early_init_f(void) +{ + fixup_sata_rx_polarity(); + fsl_lsch3_early_init_f(); + + return 0; +} diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 855b00ad534..ee7b6faa424 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -84,7 +84,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index b43998a9a7c..c64ad0b1fdd 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -81,7 +81,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index b3ad98a9577..5ce39120c54 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -57,7 +57,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 91f29c6ceb7..46eaf5e9795 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -83,7 +83,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 444c797f2e2..3ac43772aeb 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -69,7 +69,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig index f93ca9c5734..ebe361b5a55 100644 --- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig @@ -78,7 +78,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index 5a8a35f8ad0..f0329297dfd 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -76,7 +76,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index 70cd3e7fa01..04fda7b2ccb 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -73,7 +73,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index 3b4e2a4fbfd..2bd9b8ce885 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -75,7 +75,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index b1daa41b238..07bf31fd185 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -60,7 +60,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig new file mode 100644 index 00000000000..a34bb08432a --- /dev/null +++ b/configs/kmcent2_defconfig @@ -0,0 +1,92 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xebf40000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_KM_DEF_NETDEV="eth2" +CONFIG_KM_IVM_BUS=2 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020 +CONFIG_DEFAULT_DEVICE_TREE="kmcent2" +CONFIG_MPC85xx=y +CONFIG_TARGET_KMCENT2=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_SATA is not set +CONFIG_CMD_SPI=y +CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y +CONFIG_MP=y +CONFIG_CMD_CRAMFS=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=ffa000000.flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:128k(RCW),128k(fman),128k(QE),128k(zarlink),512k(res),62m(ubi0),128k(envred),128k(env),768k(u-boot);ffa000000.flash:-(ubi1);" +CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_ADDR=0xebf20000 +CONFIG_ENV_ADDR_REDUND=0xebf00000 +CONFIG_DM=y +# CONFIG_FSL_SATA is not set +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_FSL_CAAM=y +CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_FSL=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHYLIB=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_FMAN_ENET=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y +CONFIG_PCIE_FSL=y +CONFIG_U_QE=y +CONFIG_SYS_QE_FMAN_FW_IN_NOR=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_MEM=y +CONFIG_FSL_ESPI=y +CONFIG_WATCHDOG=y +CONFIG_FS_CRAMFS=y +CONFIG_BCH=y +CONFIG_PANIC_HANG=y +CONFIG_LZO=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index c1a096799c2..1759d5e1b92 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -62,6 +62,7 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y @@ -73,6 +74,7 @@ CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC=y CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y CONFIG_DM_SPI_FLASH=y +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index a0217fdd852..2cc4cd3fb86 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 6b8212c76d1..9def6655b5f 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index b85513115f1..3d5407d9283 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index b773738a6b1..30a7ed889db 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index be59d29dc2c..ade297a0a16 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index e6742ecb219..2967877da31 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index fdf4703d207..168d4f759fd 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 42bfa9b1884..d38272d0510 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index a581f9bdc05..4053a4e406d 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 1bba6f52500..095bc0e3f50 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index c32f5e19482..d8abdb917b2 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index ea490708ccc..7e1ed5c5913 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 7ba5d2d07c7..216d0fc470e 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 13ce8588d31..7bb003142db 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index dcf0dbb4a60..a606e2ac7cf 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 5e6f531ee8a..1b2d0169018 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 5477d702b25..3f08c28034c 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index f13428d4f02..59c537ad7a0 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index a17b66ea4c4..8108d160f74 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 10ce0454459..91767e0a9fe 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index bd9dc934a05..e08f77f06f0 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 41b16758f5b..e51dab07888 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 5a40bb213a6..60e907a2b41 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 957790288d5..3365d7399c7 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 14c49cd0d6f..7e75a2f121f 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 09a69237087..886556b6002 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index a3749b56273..1ec187d2600 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index b034580aeff..1f53f436dff 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 4bed352420a..eb501be0912 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index b24a316e49e..b4e100dfa7e 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 805e69d8b26..647cf311fb8 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 6b8c77b6144..a7aad4a19f2 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 5c07c912cda..6f303fbed46 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 6188ac5e431..32e894760e2 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index a6e77fc4f6c..65aa811757a 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index b426569aab4..ddd6b1b1f6c 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 1e3ac53070c..faf0142effa 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 43ac60e18b0..ecb0b8daf02 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 22277a8eb36..c1cede2c599 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -17,6 +17,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index f32573d98e0..c45dc20d721 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -17,6 +17,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 84b2950bd61..cfa4ea161d6 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index bb0e2bf419a..0fab89c5f0c 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 34cbd24d0b6..849f0d7938a 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ff2e6699057..f5004203388 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 93f9b9a981b..e8976304c1c 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index a74f1241075..4b1f679acbc 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -20,6 +20,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index ff0f1ccfc42..da63214b55c 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 10a23af7b67..13310e5d3a4 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 6b07708caed..7ed38abd098 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 03be431622a..9e54ed03927 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index deb6ac19a7f..1e77ac9d3cf 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 4ea81422658..ffe3c6b3141 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index b031fce4e10..808625197e8 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 49f9cb4b10b..d1ce22aca20 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 547848ffeba..95aabde52bf 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index efb88d034f3..49b26c1d26b 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 50356dca88e..8be734b8a44 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index ac1d5abf363..d494c650af4 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index b1ac6e0a89f..91319c6f0d4 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_SPL=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 525caa6881f..0a2c71f9197 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 069b2282b82..a10262e0b44 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index a4b67a5ca92..a7c68feca97 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 4ed33170186..f8572ccd79a 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_MISC_INIT_R=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index e95e8714452..f777fc64df3 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -20,9 +20,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index a053ea86a7a..bd6f364bd9d 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -22,9 +22,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 2b0d21d208a..c03a9648ec0 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -23,9 +23,11 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 725f6bb0bb6..e3ef9340a92 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -31,9 +31,11 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index e775e490b18..549e8242a57 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -33,9 +33,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 019d8995edb..9c65c49f3bf 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -29,6 +29,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index b4fdc00aa50..2c461816bc5 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -23,6 +23,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -39,6 +40,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 40fe7c4520e..f474119d59a 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -24,6 +24,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -42,6 +43,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20300000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 9c7a85fe62b..83b99e1236b 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -52,6 +53,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SPL_DM=y CONFIG_SCSI_AHCI=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index d409ef3f945..7f49253f53e 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -52,6 +53,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 6a075770154..095a85bb597 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -41,6 +41,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index d9b11eba717..49a49cd6d9d 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -46,6 +46,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_CMD_GPIO=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_DM_I2C=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 9e6e9f63ad9..f5e8cfbeb40 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 4dbdc1fcb13..7d7443e6f4c 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -17,9 +17,11 @@ CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index f81e2ae6def..58757f2db7b 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -20,9 +20,11 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_MISC_INIT_R=y +CONFIG_DM_GPIO=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index ccf79c1e642..bd7b4dfdaec 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 4277f9cb72e..2c60c85cba6 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index cf4bf8a19a6..13f817eedc3 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index f0e8dca8f92..2bc023f7803 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 0551ef07930..a57ed79c118 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 52ac1264aee..bd2e839ee3d 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_OPTEE_RPMB=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index d9c16740266..5afb2d055b8 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index c6b3ee484b2..d8e0e86c103 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -28,7 +28,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x56000000 CONFIG_FASTBOOT_BUF_SIZE=0x1e00000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_DM_MMC=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index b95d2c683aa..2c760c15917 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -24,7 +24,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x56000000 CONFIG_FASTBOOT_BUF_SIZE=0x1E00000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_DM_MMC=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y diff --git a/configs/pumpkin_defconfig b/configs/pumpkin_defconfig index cd77889eeae..5270ec28cbd 100644 --- a/configs/pumpkin_defconfig +++ b/configs/pumpkin_defconfig @@ -52,7 +52,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x4d000000 CONFIG_FASTBOOT_BUF_SIZE=0x4000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y # CONFIG_INPUT is not set CONFIG_DM_MMC=y # CONFIG_MMC_QUIRKS is not set diff --git a/configs/r8a774b1_beacon_defconfig b/configs/r8a774b1_beacon_defconfig new file mode 100644 index 00000000000..e12ca4d4338 --- /dev/null +++ b/configs/r8a774b1_beacon_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DM_GPIO=y +CONFIG_RCAR_GEN3=y +CONFIG_R8A774B1=y +CONFIG_TARGET_BEACON_RZG2N=y +# CONFIG_SPL is not set +CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit" +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_DEFAULT_FDT_FILE="r8a774b1-beacon-rzg2n-kit.dtb" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_BITBANGMII=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/r8a774e1_beacon_defconfig b/configs/r8a774e1_beacon_defconfig new file mode 100644 index 00000000000..1c2e86ea2a2 --- /dev/null +++ b/configs/r8a774e1_beacon_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DM_GPIO=y +CONFIG_RCAR_GEN3=y +CONFIG_R8A774E1=y +CONFIG_TARGET_BEACON_RZG2H=y +# CONFIG_SPL is not set +CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit" +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_DEFAULT_FDT_FILE="r8a774e1-beacon-rzg2h-kit.dtb" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_BITBANGMII=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y +CONFIG_PINCTRL_PFC_R8A774E1=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_SCIF_CONSOLE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst index 2877c3cbaaa..16b11399b30 100644 --- a/doc/android/fastboot.rst +++ b/doc/android/fastboot.rst @@ -23,6 +23,9 @@ The current implementation supports the following standard commands: The following OEM commands are supported (if enabled): - ``oem format`` - this executes ``gpt write mmc %x $partitions`` +- ``oem partconf`` - this executes ``mmc partconf %x <arg> 0`` to configure eMMC + with <arg> = boot_ack boot_partition +- ``oem bootbus`` - this executes ``mmc bootbus %x %s`` to configure eMMC Support for both eMMC and NAND devices is included. diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c index 318e43c179b..76b629a334f 100644 --- a/drivers/dfu/dfu_sf.c +++ b/drivers/dfu/dfu_sf.c @@ -131,7 +131,7 @@ static struct spi_flash *parse_dev(char *devstr) dev = spi_flash_probe(bus, cs, speed, mode); if (!dev) { - printf("Failed to create SPI flash at %d:%d:%d:%d\n", + printf("Failed to create SPI flash at %u:%u:%u:%u\n", bus, cs, speed, mode); return NULL; } diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 4352ba67a71..a17e488714d 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -104,18 +104,19 @@ config FASTBOOT_FLASH_NAND_TRIMFFS When flashing NAND enable the DROP_FFS flag to drop trailing all-0xff pages. -config FASTBOOT_MMC_BOOT1_SUPPORT - bool "Enable EMMC_BOOT1 flash/erase" - depends on FASTBOOT_FLASH_MMC && EFI_PARTITION && ARCH_MEDIATEK +config FASTBOOT_MMC_BOOT_SUPPORT + bool "Enable EMMC_BOOT flash/erase" + depends on FASTBOOT_FLASH_MMC help The fastboot "flash" and "erase" commands normally does operations - on EMMC userdata. Define this to enable the special commands to - flash/erase EMMC_BOOT1. - The default target name for updating EMMC_BOOT1 is "mmc0boot0". + on eMMC userdata. Define this to enable the special commands to + flash/erase eMMC boot partition. + The default target name for updating eMMC boot partition 1/2 is + CONFIG_FASTBOOT_MMC_BOOT1_NAME/CONFIG_FASTBOOT_MMC_BOOT2_NAME. config FASTBOOT_MMC_BOOT1_NAME string "Target name for updating EMMC_BOOT1" - depends on FASTBOOT_MMC_BOOT1_SUPPORT + depends on FASTBOOT_MMC_BOOT_SUPPORT default "mmc0boot0" help The fastboot "flash" and "erase" commands support operations on @@ -124,14 +125,37 @@ config FASTBOOT_MMC_BOOT1_NAME defined here. The default target name for updating EMMC_BOOT1 is "mmc0boot0". +config FASTBOOT_MMC_BOOT2_NAME + string "Target name for updating EMMC_BOOT2" + depends on FASTBOOT_MMC_BOOT_SUPPORT + default "mmc0boot1" + help + The fastboot "flash" and "erase" commands support operations on + EMMC_BOOT2. This occurs when the specified "EMMC_BOOT2 name" on + the "fastboot flash" and "fastboot erase" commands match the value + defined here. + The default target name for updating EMMC_BOOT2 is "mmc0boot1". + +config FASTBOOT_MMC_USER_SUPPORT + bool "Enable eMMC userdata partition flash/erase" + depends on FASTBOOT_FLASH_MMC + help + Define this to enable the support "flash" and "erase" command on + eMMC userdata. The "flash" command only update the MBR and GPT + header when CONFIG_EFI_PARTITION is supported. + The "erase" command erase all the userdata. + This occurs when the specified "partition name" on the + fastboot command line matches the value CONFIG_FASTBOOT_MMC_USER_NAME. + config FASTBOOT_MMC_USER_NAME - string "Target name for erasing EMMC_USER" - depends on FASTBOOT_FLASH_MMC && EFI_PARTITION && ARCH_MEDIATEK + string "Target name for updating EMMC_USER" + depends on FASTBOOT_MMC_USER_SUPPORT default "mmc0" help - The fastboot "erase" command supports erasing EMMC_USER. This occurs - when the specified "EMMC_USER name" on the "fastboot erase" commands - match the value defined here. + The fastboot "flash" and "erase" command supports EMMC_USER. + This occurs when the specified "EMMC_USER name" on the + "fastboot flash" and the "fastboot erase" commands match the value + defined here. The default target name for erasing EMMC_USER is "mmc0". config FASTBOOT_GPT_NAME @@ -165,17 +189,19 @@ config FASTBOOT_CMD_OEM_FORMAT relies on the env variable partitions to contain the list of partitions as required by the gpt command. -config FASTBOOT_USE_BCB_SET_REBOOT_FLAG - bool "Use BCB by fastboot to set boot reason" - depends on CMD_BCB && !ARCH_MESON && !ARCH_ROCKCHIP && !TARGET_KC1 && \ - !TARGET_SNIPER && !TARGET_AM57XX_EVM && !TARGET_DRA7XX_EVM - default y - help - Fastboot could implement setting of reboot reason in a generic fashion - via BCB commands. BCB commands are able to write reboot reason into - command field of boot control block. In general case it is sufficient - implementation if your platform supports BCB commands and doesn't - require any specific reboot reason handling. +config FASTBOOT_CMD_OEM_PARTCONF + bool "Enable the 'oem partconf' command" + depends on FASTBOOT_FLASH_MMC && SUPPORT_EMMC_BOOT + help + Add support for the "oem partconf" command from a client. This set + the mmc boot-partition for the selecting eMMC device. + +config FASTBOOT_CMD_OEM_BOOTBUS + bool "Enable the 'oem bootbus' command" + depends on FASTBOOT_FLASH_MMC && SUPPORT_EMMC_BOOT + help + Add support for the "oem bootbus" command from a client. This set + the mmc boot configuration for the selecting eMMC device. endif # FASTBOOT diff --git a/drivers/fastboot/Makefile b/drivers/fastboot/Makefile index 2b2c390fe4d..048af5aa823 100644 --- a/drivers/fastboot/Makefile +++ b/drivers/fastboot/Makefile @@ -5,4 +5,3 @@ obj-y += fb_getvar.o obj-y += fb_command.o obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o -obj-$(CONFIG_FASTBOOT_USE_BCB_SET_REBOOT_FLAG) += fb_bcb_impl.o diff --git a/drivers/fastboot/fb_bcb_impl.c b/drivers/fastboot/fb_bcb_impl.c deleted file mode 100644 index 89ec3601b6f..00000000000 --- a/drivers/fastboot/fb_bcb_impl.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 GlobalLogic. - * Roman Kovalivskyi <roman.kovalivskyi@globallogic.com> - */ - -#include <common.h> -#include <fastboot.h> - -/** - * fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader - * - * Set flag which indicates that we should reboot into the bootloader - * following the reboot that fastboot executes after this function. - * - * This function should be overridden in your board file with one - * which sets whatever flag your board specific Android bootloader flow - * requires in order to re-enter the bootloader. - */ -int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) -{ - char cmd[64]; - - if (reason >= FASTBOOT_REBOOT_REASONS_COUNT) - return -EINVAL; - - snprintf(cmd, sizeof(cmd), "bcb load %d misc", - CONFIG_FASTBOOT_FLASH_MMC_DEV); - - if (run_command(cmd, 0)) - return -ENODEV; - - snprintf(cmd, sizeof(cmd), "bcb set command %s", - fastboot_boot_cmds[reason]); - - if (run_command(cmd, 0)) - return -ENOEXEC; - - if (run_command("bcb store", 0)) - return -EIO; - - return 0; -} diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index d3c578672dc..41fc8d7904d 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -42,6 +42,12 @@ static void reboot_recovery(char *, char *); #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) static void oem_format(char *, char *); #endif +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) +static void oem_partconf(char *, char *); +#endif +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) +static void oem_bootbus(char *, char *); +#endif static const struct { const char *command; @@ -99,6 +105,18 @@ static const struct { .dispatch = oem_format, }, #endif +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) + [FASTBOOT_COMMAND_OEM_PARTCONF] = { + .command = "oem partconf", + .dispatch = oem_partconf, + }, +#endif +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) + [FASTBOOT_COMMAND_OEM_BOOTBUS] = { + .command = "oem bootbus", + .dispatch = oem_bootbus, + }, +#endif }; /** @@ -374,3 +392,57 @@ static void oem_format(char *cmd_parameter, char *response) } } #endif + +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) +/** + * oem_partconf() - Execute the OEM partconf command + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void oem_partconf(char *cmd_parameter, char *response) +{ + char cmdbuf[32]; + + if (!cmd_parameter) { + fastboot_fail("Expected command parameter", response); + return; + } + + /* execute 'mmc partconfg' command with cmd_parameter arguments*/ + snprintf(cmdbuf, sizeof(cmdbuf), "mmc partconf %x %s 0", + CONFIG_FASTBOOT_FLASH_MMC_DEV, cmd_parameter); + printf("Execute: %s\n", cmdbuf); + if (run_command(cmdbuf, 0)) + fastboot_fail("Cannot set oem partconf", response); + else + fastboot_okay(NULL, response); +} +#endif + +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) +/** + * oem_bootbus() - Execute the OEM bootbus command + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void oem_bootbus(char *cmd_parameter, char *response) +{ + char cmdbuf[32]; + + if (!cmd_parameter) { + fastboot_fail("Expected command parameter", response); + return; + } + + /* execute 'mmc bootbus' command with cmd_parameter arguments*/ + snprintf(cmdbuf, sizeof(cmdbuf), "mmc bootbus %x %s", + CONFIG_FASTBOOT_FLASH_MMC_DEV, cmd_parameter); + printf("Execute: %s\n", cmdbuf); + if (run_command(cmdbuf, 0)) + fastboot_fail("Cannot set oem bootbus", response); + else + fastboot_okay(NULL, response); +} +#endif diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 736ce1cd024..cbcc3683c47 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -10,6 +10,7 @@ * Rob Herring <robh@kernel.org> */ +#include <bcb.h> #include <common.h> #include <command.h> #include <env.h> @@ -90,7 +91,20 @@ void fastboot_okay(const char *reason, char *response) */ int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) { - return -ENOSYS; +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC_DEV) + static const char * const boot_cmds[] = { + [FASTBOOT_REBOOT_REASON_BOOTLOADER] = "bootonce-bootloader", + [FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot", + [FASTBOOT_REBOOT_REASON_RECOVERY] = "boot-recovery" + }; + + if (reason >= FASTBOOT_REBOOT_REASONS_COUNT) + return -EINVAL; + + return bcb_write_reboot_reason(CONFIG_FASTBOOT_FLASH_MMC_DEV, "misc", boot_cmds[reason]); +#else + return -EINVAL; +#endif } /** diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 4e26cef9417..50532acb847 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -174,7 +174,8 @@ static void write_raw_image(struct blk_desc *dev_desc, fastboot_okay(NULL, response); } -#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT +#if defined(CONFIG_FASTBOOT_MMC_BOOT_SUPPORT) || \ + defined(CONFIG_FASTBOOT_MMC_USER_SUPPORT) static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc) { lbaint_t blks; @@ -193,16 +194,18 @@ static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc) return 0; } +#endif -static void fb_mmc_boot1_ops(struct blk_desc *dev_desc, void *buffer, - u32 buff_sz, char *response) +#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT +static void fb_mmc_boot_ops(struct blk_desc *dev_desc, void *buffer, + int hwpart, u32 buff_sz, char *response) { lbaint_t blkcnt; lbaint_t blks; unsigned long blksz; - // To operate on EMMC_BOOT1 (mmc0boot0), we first change the hwpart - if (blk_dselect_hwpart(dev_desc, 1)) { + // To operate on EMMC_BOOT1/2 (mmc0boot0/1) we first change the hwpart + if (blk_dselect_hwpart(dev_desc, hwpart)) { pr_err("Failed to select hwpart\n"); fastboot_fail("Failed to select hwpart", response); return; @@ -221,21 +224,24 @@ static void fb_mmc_boot1_ops(struct blk_desc *dev_desc, void *buffer, return; } - debug("Start Flashing Image to EMMC_BOOT1...\n"); + debug("Start Flashing Image to EMMC_BOOT%d...\n", hwpart); blks = fb_mmc_blk_write(dev_desc, 0, blkcnt, buffer); if (blks != blkcnt) { - pr_err("Failed to write EMMC_BOOT1\n"); - fastboot_fail("Failed to write EMMC_BOOT1", response); + pr_err("Failed to write EMMC_BOOT%d\n", hwpart); + fastboot_fail("Failed to write EMMC_BOOT part", + response); return; } - printf("........ wrote %lu bytes to EMMC_BOOT1\n", - blkcnt * blksz); + printf("........ wrote %lu bytes to EMMC_BOOT%d\n", + blkcnt * blksz, hwpart); } else { /* erase */ if (fb_mmc_erase_mmc_hwpart(dev_desc)) { - fastboot_fail("Failed to erase EMMC_BOOT1", response); + pr_err("Failed to erase EMMC_BOOT%d\n", hwpart); + fastboot_fail("Failed to erase EMMC_BOOT part", + response); return; } } @@ -464,16 +470,21 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, return; } -#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT +#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) { - fb_mmc_boot1_ops(dev_desc, download_buffer, - download_bytes, response); + fb_mmc_boot_ops(dev_desc, download_buffer, 1, + download_bytes, response); + return; + } + if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) { + fb_mmc_boot_ops(dev_desc, download_buffer, 2, + download_bytes, response); return; } #endif #if CONFIG_IS_ENABLED(EFI_PARTITION) -#ifndef CONFIG_FASTBOOT_MMC_USER_NAME +#ifndef CONFIG_FASTBOOT_MMC_USER_SUPPORT if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) { #else if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0 || @@ -493,6 +504,7 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, response); return; } + part_init(dev_desc); printf("........ success\n"); fastboot_okay(NULL, response); return; @@ -514,6 +526,7 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, response); return; } + part_init(dev_desc); printf("........ success\n"); fastboot_okay(NULL, response); return; @@ -595,15 +608,20 @@ void fastboot_mmc_erase(const char *cmd, char *response) return; } -#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT +#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) { /* erase EMMC boot1 */ - fb_mmc_boot1_ops(dev_desc, NULL, 0, response); + fb_mmc_boot_ops(dev_desc, NULL, 1, 0, response); + return; + } + if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) { + /* erase EMMC boot2 */ + fb_mmc_boot_ops(dev_desc, NULL, 2, 0, response); return; } #endif -#ifdef CONFIG_FASTBOOT_MMC_USER_NAME +#ifdef CONFIG_FASTBOOT_MMC_USER_SUPPORT if (strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) { /* erase EMMC userdata */ if (fb_mmc_erase_mmc_hwpart(dev_desc)) diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index a964347fa32..c7336032894 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -6,7 +6,7 @@ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is * * Copyright 2010 eXMeritus, A Boeing Company - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #include <common.h> @@ -16,16 +16,6 @@ #include <asm/io.h> #include <dm/of_access.h> -struct ccsr_gpio { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr; - u32 gpibe; -}; - struct mpc8xxx_gpio_data { /* The bank's register base in memory */ struct ccsr_gpio __iomem *base; @@ -187,32 +177,11 @@ static int mpc8xxx_gpio_of_to_plat(struct udevice *dev) { struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev); struct mpc8xxx_gpio_data *data = dev_get_priv(dev); - fdt_addr_t addr; - u32 i; - u32 reg[4]; - if (ofnode_read_bool(dev_ofnode(dev), "little-endian")) + if (dev_read_bool(dev, "little-endian")) data->little_endian = true; - if (data->little_endian) - dev_read_u32_array(dev, "reg", reg, 4); - else - dev_read_u32_array(dev, "reg", reg, 2); - - if (data->little_endian) { - for (i = 0; i < 2; i++) - reg[i] = be32_to_cpu(reg[i]); - } - - addr = dev_translate_address(dev, reg); - - plat->addr = addr; - - if (data->little_endian) - plat->size = reg[3]; - else - plat->size = reg[1]; - + plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size); plat->ngpios = dev_read_u32_default(dev, "ngpios", 32); return 0; @@ -257,11 +226,11 @@ static int mpc8xxx_gpio_probe(struct udevice *dev) if (!str) return -ENOMEM; - if (ofnode_device_is_compatible(dev_ofnode(dev), "fsl,qoriq-gpio")) { - unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio) - - sizeof(u32); - - out_be32((unsigned int *)gpibe, 0xffffffff); + if (device_is_compatible(dev, "fsl,qoriq-gpio")) { + if (data->little_endian) + out_le32(&data->base->gpibe, 0xffffffff); + else + out_be32(&data->base->gpibe, 0xffffffff); } uc_priv->bank_name = str; diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index ea444436ad4..f8db8e5213a 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -95,6 +95,16 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_UNLOCK_ALL + bool "Unlock the entire SPI flash on u-boot startup" + default y + help + Some flashes tend to power up with the software write protection + bits set. If this option is set, the whole flash will be unlocked. + + For legacy reasons, this option default to y. But if you intend to + actually use the software protection bits you should say n here. + config SF_DUAL_FLASH bool "SPI DUAL flash memory support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e16b0e1462d..ef426dac02b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2443,10 +2443,11 @@ static int spi_nor_init(struct spi_nor *nor) * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set */ - if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || - JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || - JEDEC_MFR(nor->info) == SNOR_MFR_SST || - nor->info->flags & SPI_NOR_HAS_LOCK) { + if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) && + (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || + JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || + JEDEC_MFR(nor->info) == SNOR_MFR_SST || + nor->info->flags & SPI_NOR_HAS_LOCK)) { write_enable(nor); write_sr(nor, 0); spi_nor_wait_till_ready(nor); diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 944412958d6..e8242ca4e1b 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -2127,7 +2127,7 @@ static struct eqos_ops eqos_imx_ops = { struct eqos_config __maybe_unused eqos_imx_config = { .reg_access_always_ok = false, - .mdio_wait = 10000, + .mdio_wait = 10, .swr_wait = 50, .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 8bd32b0ab75..72b500a6d14 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -28,6 +28,8 @@ struct fm_mdio_priv { }; #endif +#define MAX_NUM_RETRIES 1000 + static u32 memac_in_32(u32 *reg) { #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -38,6 +40,42 @@ static u32 memac_in_32(u32 *reg) } /* + * Wait until the MDIO bus is free + */ +static int memac_wait_until_free(struct memac_mdio_controller *regs) +{ + unsigned int timeout = MAX_NUM_RETRIES; + + while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--) + ; + + if (!timeout) { + printf("timeout waiting for MDIO bus to be free\n"); + return -ETIMEDOUT; + } + + return 0; +} + +/* + * Wait till the MDIO read or write operation is complete + */ +static int memac_wait_until_done(struct memac_mdio_controller *regs) +{ + unsigned int timeout = MAX_NUM_RETRIES; + + while ((memac_in_32(®s->mdio_data) & MDIO_DATA_BSY) && timeout--) + ; + + if (!timeout) { + printf("timeout waiting for MDIO operation to complete\n"); + return -ETIMEDOUT; + } + + return 0; +} + +/* * Write value to the PHY for this device to the register at regnum, waiting * until the write is done before it returns. All PHY configuration has to be * done through the TSEC1 MIIM regs @@ -48,6 +86,7 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, struct memac_mdio_controller *regs; u32 mdio_ctl; u32 c45 = 1; /* Default to 10G interface */ + int err; #ifndef CONFIG_DM_ETH regs = bus->priv; @@ -69,9 +108,9 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, } else memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Set the port and dev addr */ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); @@ -81,16 +120,16 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, if (c45) memac_out_32(®s->mdio_addr, regnum & 0xffff); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Write the value to the register */ memac_out_32(®s->mdio_data, MDIO_DATA(value)); - /* Wait till the MDIO write is complete */ - while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) - ; + err = memac_wait_until_done(regs); + if (err) + return err; return 0; } @@ -106,6 +145,7 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, struct memac_mdio_controller *regs; u32 mdio_ctl; u32 c45 = 1; + int err; #ifndef CONFIG_DM_ETH regs = bus->priv; @@ -129,9 +169,9 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, } else memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Set the Port and Device Addrs */ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); @@ -141,17 +181,17 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, if (c45) memac_out_32(®s->mdio_addr, regnum & 0xffff); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Initiate the read */ mdio_ctl |= MDIO_CTL_READ; memac_out_32(®s->mdio_ctl, mdio_ctl); - /* Wait till the MDIO write is complete */ - while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) - ; + err = memac_wait_until_done(regs); + if (err) + return err; /* Return all Fs if nothing was there */ if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b1de38f7662..ba41787f64d 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -219,7 +219,8 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A - default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie" if ARCH_LX2160A + default "fsl,ls2088a-pcie" if ARCH_LX2162A default "fsl,ls1021a-pcie" if ARCH_LS1021A help This compatible is used to find pci controller node in Kernel DT @@ -228,7 +229,7 @@ config FSL_PCIE_COMPAT config FSL_PCIE_EP_COMPAT string "PCIe EP compatible of Kernel DT" depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 - default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A default "fsl,ls-pcie-ep" help This compatible is used to find pci controller ep node in Kernel DT diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 0124e8e0518..8cdf516d9fa 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,8 @@ #include <pci.h> #include <linux/sizes.h> +#include <asm/arch-fsl-layerscape/svr.h> +#include <asm/arch-ls102xa/svr.h> #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -121,16 +123,6 @@ /* CS2 */ #define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ -#define SVR_LS102XA 0 -#define SVR_VAR_PER_SHIFT 8 -#define SVR_LS102XA_MASK 0x700 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 - /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL #define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 8bc7038a82a..f965301d6ac 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -259,14 +259,6 @@ static const struct fsl_qspi_devtype_data ls1021a_data = { .little_endian = false, }; -static const struct fsl_qspi_devtype_data ls1088a_data = { - .rxfifo = SZ_128, - .txfifo = SZ_128, - .ahb_buf_size = SZ_1K, - .quirks = QUADSPI_QUIRK_TKT253890, - .little_endian = true, -}; - static const struct fsl_qspi_devtype_data ls2080a_data = { .rxfifo = SZ_128, .txfifo = SZ_64, @@ -409,7 +401,7 @@ static bool fsl_qspi_supports_op(struct spi_slave *slave, op->data.nbytes > q->devtype_data->txfifo) return false; - return true; + return spi_mem_default_supports_op(slave, op); } static void fsl_qspi_prepare_lut(struct fsl_qspi *q, @@ -877,7 +869,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, - { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, + { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, { } }; diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 29060fa96b3..4115906c5d7 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -110,10 +110,6 @@ #include <linux/delay.h> #include <linux/stringify.h> extern void __set_direction(unsigned pin, int high); -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); #define KM_KIRKWOOD_SDA_PIN 8 #define KM_KIRKWOOD_SCL_PIN 9 #define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h new file mode 100644 index 00000000000..51a01d860f0 --- /dev/null +++ b/include/configs/kmcent2.h @@ -0,0 +1,513 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Keymile AG + * Rainer Boschung <rainer.boschung@keymile.com> + * + */ + +#ifndef __KMCENT2_H +#define __KMCENT2_H + +#define CONFIG_HOSTNAME "kmcent2" +#define KM_BOARD_NAME CONFIG_HOSTNAME + +/* + * The Linux fsl_fman driver needs to be able to process frames with more + * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot + * parameters + */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558" + +#include "km/keymile-common.h" + +/* Application IFC chip selects */ +#define SYS_LAWAPP_BASE 0xc0000000 +#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) + +/* Application IFC CS4 MRAM */ +#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE +#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS +#define SYS_MRAM_CSPR_EXT (0x0f) +#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \ + CSPR_PORT_SIZE_8 | /* 8 bit */ \ + CSPR_MSEL_GPCM | /* msel = gpcm */ \ + CSPR_V /* bank is valid */) +#define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */ +#define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40 +/* MRAM Timing parameters for IFC CS4 */ +#define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0xe)) +#define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \ + FTIM2_GPCM_TCH(0x2) | \ + FTIM2_GPCM_TWP(0x8)) +#define SYS_MRAM_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT +#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR +#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK +#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR +#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 +#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 +#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 +#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 + +/* Application IFC CS6: BFTIC */ +#define SYS_BFTIC_BASE 0xd0000000 +#define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE) +#define SYS_BFTIC_CSPR_EXT (0x0f) +#define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40 +/* BFTIC Timing parameters for IFC CS6 */ +#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define SYS_BFTIC_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT +#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR +#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK +#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR +#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 +#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 +#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 +#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 + +/* Application IFC CS7 PAXE */ +#define CONFIG_SYS_PAXE_BASE 0xd8000000 +#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE) +#define SYS_PAXE_CSPR_EXT (0x0f) +#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40 +/* PAXE Timing parameters for IFC CS7 */ +#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define SYS_PAXE_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT +#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR +#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK +#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR +#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 +#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 +#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 +#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 + +/* PRST */ +#define KM_BFTIC4_RST 0 +#define KM_DPAXE_RST 1 +#define KM_FEMT_RST 3 +#define KM_FOAM_RST 4 +#define KM_EFE_RST 5 +#define KM_ES_PHY_RST 6 +#define KM_XES_PHY_RST 7 +#define KM_ZL30158_RST 8 +#define KM_ZL30364_RST 9 +#define KM_BOBCAT_RST 10 +#define KM_ETHSW_DDR_RST 12 +#define KM_CFE_RST 13 +#define KM_PEXSW_RST 14 +#define KM_PEXSW_NT_RST 15 + +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +/* High Level Configuration Options */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ + +#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +/* Environment in parallel NOR-Flash */ +#define CONFIG_ENV_TOTAL_SIZE 0x040000 +#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/ + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +/* POST memory regions test */ +#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/****************************************************************************** + * (PRAM usage) + * ... ------------------------------------------------------- + * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |<------------------- pram -------------------------->| + * ... ------------------------------------------------------- + * @END_OF_RAM: + * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose + * @CONFIG_KM_PHRAM: address for /var + * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) + * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM + */ + +/* size of rootfs in RAM */ +#define CONFIG_KM_ROOTFSSIZE 0x0 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM + */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) + +/* + * IFC Definitions + */ +/* NOR flash on IFC CS0 */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ + CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR_CSPR_EXT (0x0f) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ + CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_NOR | /* MSEL = NOR */\ + CSPR_V) /* valid */ +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ + CSOR_NOR_TRHZ_20 | \ + CSOR_NOR_BCTLD) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x7) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x21) | \ + FTIM1_NOR_TSEQRAD_NOR(0x21)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ + FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TWP(0xb) | \ + FTIM2_NOR_TWPH(0x6)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* More NOR Flash params */ +#define CONFIG_SYS_FLASH_QUIET_TEST + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* NAND Flash on IFC CS1*/ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xfa000000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0f) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_NAND | /* MSEL = NAND */\ + CSPR_V) /* valid */ +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ + CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \ + CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ + CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \ + CSOR_NAND_PGS_2K | /* Page size = 2K */ \ + CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \ + CSOR_NAND_PB(64) | /* 64 Pages/Block */ \ + CSOR_NAND_TRHZ_40 | /**/ \ + CSOR_NAND_BCTLD) /**/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ + FTIM0_NAND_TWP(0x8) | \ + FTIM0_NAND_TWCHT(0x3) | \ + FTIM0_NAND_TWH(0x5)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ + FTIM1_NAND_TWBE(0x1e) | \ + FTIM1_NAND_TRR(0x6) | \ + FTIM1_NAND_TRP(0x8)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ + FTIM2_NAND_TREH(0x5) | \ + FTIM2_NAND_TWHRE(0x3c)) +#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* More NAND Flash Params */ +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* QRIO on IFC CS2 */ +#define CONFIG_SYS_QRIO_BASE 0xfb000000 +#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE) +#define SYS_QRIO_CSPR_EXT (0x0f) +#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ + CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ + 0x00000010 | /* drive TE high */\ + CSPR_MSEL_GPCM | /* MSEL = GPCM */\ + CSPR_V) /* valid */ +#define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\ + CSOR_GPCM_BCTLD) +/* QRIO Timing parameters for IFC CS2 */ +#define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x6)) +#define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x7)) +#define SYS_QRIO_FTIM3 0x04000000 +#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT +#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR +#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK +#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR +#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 + +#define CONFIG_MISC_INIT_F +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ + +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + * Retain non-DM serial port for debug purposes. + */ +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#endif + +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull + +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +/* Default address of microcode for the Linux Fman driver */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000 +#define CONFIG_SYS_QE_FW_ADDR 0xE8040000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) + +/* Qman / Bman */ +/* RGMII (FM1@DTESC5) is local managemant interface */ +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 +#define CONFIG_ETHPRIME "fm1-mac5" + +/* + * Hardware Watchdog + */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV +#endif + +#define __USB_PHY_TYPE utmi + +#define CONFIG_KM_DEF_ENV_CPU \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ + "set_fdthigh=true\0" \ + "checkfdt=true\0" \ + "fpgacfg=true\0" \ + "" + +#define CONFIG_HW_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ + "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" + +#define CONFIG_KM_NEW_ENV \ + "newenv=protect off " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "erase " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "protect on " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" + +/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + CONFIG_KM_NEW_ENV \ + CONFIG_HW_ENV_SETTINGS \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +#endif /* __KMCENT2_H */ diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index d1eb7b574b4..90e3702bd80 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -237,12 +237,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ } -#ifndef __ASSEMBLY__ -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); -#endif #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 442fb58b979..5d818a708d0 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -93,6 +93,7 @@ func(MMC, mmc, 1) \ func(NVME, nvme, 0) \ func(USB, usb, 0) \ + func(SCSI, scsi, 0) \ func(DHCP, dhcp, 0) \ func(PXE, pxe, 0) #include <config_distro_bootcmd.h> diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 6cf6a31d767..f6b5d47c255 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -62,6 +62,13 @@ #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 #endif +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index eb6f1c1e5be..b4c70333def 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -341,6 +341,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3e85bb3850b..dfb56437d97 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -219,6 +219,13 @@ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 8345cd7acfc..1c4af7d1760 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -36,6 +36,13 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 6584e391993..4e3e1a946b6 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -119,6 +119,13 @@ #endif +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* IFC */ #ifndef SPL_NO_IFC #if defined(CONFIG_TFABOOT) || \ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index d44a7f105e6..32658cf641f 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -126,6 +126,13 @@ #define CONFIG_SYS_MONITOR_LEN 0xa0000 #endif +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index f9e349871c8..b9a956b90b5 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -53,6 +53,13 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index b92ec14c691..1626e65056b 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -371,10 +371,18 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) +#define COMMON_ENV \ + "kernelheader_addr_r=0x80200000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" + /* Initial environment variables */ #ifdef CONFIG_NXP_ESBC #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -406,6 +414,7 @@ unsigned long get_board_ddr_clk(void); #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -467,6 +476,7 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_QSPI_BOOT) #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -484,6 +494,7 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SD_BOOT) #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x800\0" \ @@ -501,6 +512,7 @@ unsigned long get_board_ddr_clk(void); #else /* NOR BOOT */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 444bb8c3b5c..1042555a8cf 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -66,6 +66,13 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 4bd0ddbdad2..466484c1997 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -160,6 +160,13 @@ #define NXP_FSPI_FLASH_NUM 1 #endif +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif + #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); diff --git a/include/dt-bindings/clk/versaclock.h b/include/dt-bindings/clk/versaclock.h new file mode 100644 index 00000000000..c6a6a094656 --- /dev/null +++ b/include/dt-bindings/clk/versaclock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* This file defines field values used by the versaclock 6 family + * for defining output type + */ + +#define VC5_LVPECL 0 +#define VC5_CMOS 1 +#define VC5_HCSL33 2 +#define VC5_LVDS 3 +#define VC5_CMOS2 4 +#define VC5_CMOSD 5 +#define VC5_HCSL25 6 diff --git a/include/fastboot.h b/include/fastboot.h index 8e9ee80907d..797d7dfd529 100644 --- a/include/fastboot.h +++ b/include/fastboot.h @@ -38,6 +38,12 @@ enum { #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) FASTBOOT_COMMAND_OEM_FORMAT, #endif +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_PARTCONF) + FASTBOOT_COMMAND_OEM_PARTCONF, +#endif +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS) + FASTBOOT_COMMAND_OEM_BOOTBUS, +#endif FASTBOOT_COMMAND_COUNT }; @@ -53,15 +59,6 @@ enum fastboot_reboot_reason { }; /** - * BCB boot commands - */ -static const char * const fastboot_boot_cmds[] = { - [FASTBOOT_REBOOT_REASON_BOOTLOADER] = "bootonce-bootloader", - [FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot", - [FASTBOOT_REBOOT_REASON_RECOVERY] = "boot-recovery" -}; - -/** * fastboot_response() - Writes a response of the form "$tag$reason". * * @tag: The first part of the response diff --git a/include/spi-mem.h b/include/spi-mem.h index ca0f55c8fdf..8be3e2bf6b5 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -240,6 +240,9 @@ bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op); int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op); +bool spi_mem_default_supports_op(struct spi_slave *mem, + const struct spi_mem_op *op); + #ifndef __UBOOT__ int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv, struct module *owner); |