diff options
481 files changed, 19123 insertions, 1531 deletions
@@ -500,13 +500,14 @@ config BUILD_TARGET config HAS_BOARD_SIZE_LIMIT bool "Define a maximum size for the U-Boot image" - default y if RCAR_64 + default y if RCAR_32 || RCAR_64 help In some cases, we need to enforce a hard limit on how big the U-Boot image itself can be. config BOARD_SIZE_LIMIT int "Maximum size of the U-Boot image in bytes" + default 524288 if RCAR_32 default 1048576 if RCAR_64 depends on HAS_BOARD_SIZE_LIMIT help diff --git a/MAINTAINERS b/MAINTAINERS index da477a4e6ad..0b08ca19239 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -59,8 +59,10 @@ F: lib/acpi/ ANDROID AB M: Igor Opaniuk <igor.opaniuk@gmail.com> +M: Mattijs Korpershoek <mkorpershoek@baylibre.com> R: Sam Protsenko <semen.protsenko@linaro.org> S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git F: boot/android_ab.c F: cmd/ab_select.c F: doc/android/ab.rst @@ -69,7 +71,9 @@ F: test/py/tests/test_android/test_ab.py ANDROID AVB M: Igor Opaniuk <igor.opaniuk@gmail.com> +M: Mattijs Korpershoek <mkorpershoek@baylibre.com> S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git F: cmd/avb.c F: common/avb_verify.c F: doc/android/avb2.rst @@ -451,7 +455,7 @@ F: drivers/timer/mchp-pit64b-timer.c ARM MSC SM2S IMX8MP SOM M: Martyn Welch <martyn.welch@collabora.com> -M: Ian Ray <ian.ray@ge.com> +M: Ian Ray <ian.ray@gehealthcare.com> S: Maintained F: arch/arm/dts/imx8mp-msc-sm2s* F: board/msc/sm2s_imx8mp/ @@ -563,6 +567,31 @@ F: arch/arm/mach-exynos/ F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ +ARM SAMSUNG CLOCK +M: Sam Protsenko <semen.protsenko@linaro.org> +S: Maintained +F: drivers/clk/exynos/clk-pll.c +F: drivers/clk/exynos/clk-pll.h +F: drivers/clk/exynos/clk.c +F: drivers/clk/exynos/clk.h + +ARM SAMSUNG EXYNOS850 SOC +M: Sam Protsenko <semen.protsenko@linaro.org> +S: Maintained +F: arch/arm/dts/exynos850-pinctrl.dtsi +F: arch/arm/dts/exynos850.dtsi +F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml +F: drivers/clk/exynos/clk-exynos850.c +F: drivers/pinctrl/exynos/pinctrl-exynos850.c +F: include/dt-bindings/clock/exynos850.h + +ARM SAMSUNG SOC DRIVERS +M: Sam Protsenko <semen.protsenko@linaro.org> +S: Maintained +F: doc/device-tree-bindings/soc/samsung/* +F: drivers/soc/samsung/* +F: include/dt-bindings/soc/samsung,*.h + ARM SANCLOUD M: Paul Barker <paul.barker@sancloud.com> R: Marc Murphy <marc.murphy@sancloud.com> @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* diff --git a/arch/Kconfig b/arch/Kconfig index b6fb9e92733..0d3cce919f8 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -361,7 +361,16 @@ config SYS_BOARD leave this option empty. config SYS_CONFIG_NAME - string + string "Board header file" if ARCH_MESON || ARCH_VERSAL || \ + ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \ + ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2 + default "meson64" if ARCH_MESON + default "microblaze-generic" if MICROBLAZE + default "xilinx_versal" if ARCH_VERSAL + default "xilinx_versal_net" if ARCH_VERSAL_NET + default "xilinx_zynqmp" if ARCH_ZYNQMP + default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5 + default "zynq-common" if ARCH_ZYNQ help This option should contain the base name of board header file. The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 59e4d4d949a..fde85dc0d53 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -678,7 +678,7 @@ config ARCH_BCMBCA config TARGET_VEXPRESS_CA9X4 bool "Support vexpress_ca9x4" select CPU_V7A - select PL011_SERIAL + select PL01X_SERIAL config TARGET_BCMNS bool "Support Broadcom Northstar" @@ -785,15 +785,21 @@ config ARCH_IPQ40XX config ARCH_KEYSTONE bool "TI Keystone" + select CMD_DDR3 select CMD_POWEROFF select CPU_V7A select DDR_SPD + select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SYS_ARCH_TIMER select SYS_THUMB_BUILD imply CMD_MTDPARTS + imply CMD_NFS imply CMD_SAVES + imply DM_I2C imply FIT + imply SOC_TI + imply TI_KEYSTONE_SERDES config ARCH_K3 bool "Texas Instruments' K3 Architecture" @@ -1070,6 +1076,7 @@ config ARCH_RMOBILE select DM select DM_SERIAL select GPIO_EXTRA_HEADER + select LTO imply BOARD_EARLY_INIT_F imply CMD_DM imply FAT_WRITE diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 3bfdc3f7743..4c61d28c20f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -811,6 +811,8 @@ __weak int fsl_setenv_bootcmd(void) enum boot_src src = get_boot_src(); char bootcmd_str[MAX_BOOTCMD_SIZE]; + bootcmd_str[0] = 0; + switch (src) { #ifdef IFC_NOR_BOOTCOMMAND case BOOT_SOURCE_IFC_NOR: @@ -859,6 +861,9 @@ __weak int fsl_setenv_bootcmd(void) break; } + if (!bootcmd_str[0]) + return 0; + ret = env_set("bootcmd", bootcmd_str); if (ret) { printf("Failed to set bootcmd: ret = %d\n", ret); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 50f35e3db3f..d9725030d5a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb dtb-$(CONFIG_ARCH_APPLE) += \ t8103-j274.dtb \ @@ -181,6 +182,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-soquartz-model-a.dtb \ rk3568-bpi-r2-pro.dtb \ rk3568-evb.dtb \ + rk3568-generic.dtb \ rk3568-lubancat-2.dtb \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ @@ -929,6 +931,7 @@ dtb-y += \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ + imx6dl-sielaff.dtb \ imx6dl-wandboard-revd1.dtb \ imx6s-dhcom-drc02.dtb @@ -1130,7 +1133,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ dtb-$(CONFIG_ARCH_IMX9) += \ imx93-11x11-evk.dtb \ - imx93-var-som-symphony.dtb + imx93-var-som-symphony.dtb \ + imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb \ @@ -1170,7 +1174,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \ dtb-$(CONFIG_RCAR_GEN4) += \ r8a779a0-falcon-u-boot.dtb \ r8a779f0-spider-u-boot.dtb \ - r8a779g0-white-hawk-u-boot.dtb + r8a779g0-white-hawk-u-boot.dtb \ + r8a779h0-gray-hawk-u-boot.dtb dtb-$(CONFIG_TARGET_RZG2L) += \ r9a07g044l2-smarc.dts diff --git a/arch/arm/dts/exynos-pinctrl.h b/arch/arm/dts/exynos-pinctrl.h new file mode 100644 index 00000000000..7dd94a9b365 --- /dev/null +++ b/arch/arm/dts/exynos-pinctrl.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ +#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850 + * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1) + */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5433 */ +#define EXYNOS5433_PIN_DRV_FAST_SR1 0 +#define EXYNOS5433_PIN_DRV_FAST_SR2 1 +#define EXYNOS5433_PIN_DRV_FAST_SR3 2 +#define EXYNOS5433_PIN_DRV_FAST_SR4 3 +#define EXYNOS5433_PIN_DRV_FAST_SR5 4 +#define EXYNOS5433_PIN_DRV_FAST_SR6 5 +#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 +#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 +#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa +#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb +#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc +#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf + +/* Drive strengths for Exynos7 (except FSYS1) */ +#define EXYNOS7_PIN_DRV_LV1 0 +#define EXYNOS7_PIN_DRV_LV2 2 +#define EXYNOS7_PIN_DRV_LV3 1 +#define EXYNOS7_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos7 FSYS1 block */ +#define EXYNOS7_FSYS1_PIN_DRV_LV1 0 +#define EXYNOS7_FSYS1_PIN_DRV_LV2 4 +#define EXYNOS7_FSYS1_PIN_DRV_LV3 2 +#define EXYNOS7_FSYS1_PIN_DRV_LV4 6 +#define EXYNOS7_FSYS1_PIN_DRV_LV5 1 +#define EXYNOS7_FSYS1_PIN_DRV_LV6 5 + +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_EINT 0xf +#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT + +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi new file mode 100644 index 00000000000..7ad11e9faab --- /dev/null +++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + */ + +&cmu_top { + bootph-all; +}; + +&cmu_peri { + bootph-all; +}; + +&oscclk { + bootph-all; +}; + +&pinctrl_alive { + bootph-all; +}; + +&pmu_system_controller { + bootph-all; + samsung,uart-debug-1; +}; + +&serial_0 { + bootph-all; +}; + +&uart1_pins { + bootph-all; +}; + +&usi_uart { + bootph-all; +}; diff --git a/arch/arm/dts/exynos850-e850-96.dts b/arch/arm/dts/exynos850-e850-96.dts new file mode 100644 index 00000000000..f074df8982b --- /dev/null +++ b/arch/arm/dts/exynos850-e850-96.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * WinLink E850-96 board device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device tree source file for WinLink's E850-96 board which is based on + * Samsung Exynos850 SoC. + */ + +/dts-v1/; + +#include "exynos850.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "WinLink E850-96 board"; + compatible = "winlink,e850-96", "samsung,exynos850"; + + aliases { + mmc0 = &mmc_0; + serial0 = &serial_0; + }; + + chosen { + stdout-path = &serial_0; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-supply = <®_usb_host_vbus>; + id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <µ_usb_det_pins>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + /* + * RAM: 4 GiB (eMCP): + * - 2 GiB at 0x80000000 + * - 2 GiB at 0x880000000 + * + * 0xbab00000..0xbfffffff: secure memory (85 MiB). + */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x3ab00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown_pins &key_volup_pins>; + + volume-down-key { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&gpa1 0 GPIO_ACTIVE_LOW>; + }; + + volume-up-key { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&gpa0 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* HEART_BEAT_LED */ + user_led1: led-1 { + label = "yellow:user1"; + gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + /* eMMC_LED */ + user_led2: led-2 { + label = "yellow:user2"; + gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_YELLOW>; + linux,default-trigger = "mmc0"; + }; + + /* SD_LED */ + user_led3: led-3 { + label = "white:user3"; + gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_SD; + linux,default-trigger = "mmc2"; + }; + + /* WIFI_LED */ + wlan_active_led: led-4 { + label = "yellow:wlan"; + gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_WLAN; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + /* BLUETOOTH_LED */ + bt_active_led: led-5 { + label = "blue:bt"; + gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_BLUETOOTH; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; + + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + + reg_usb_host_vbus: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpa3 5 GPIO_ACTIVE_LOW>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + ramoops@f0000000 { + compatible = "ramoops"; + reg = <0x0 0xf0000000 0x200000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x100000>; + pmsg-size = <0x20000>; + }; + }; + + /* + * RTC clock (XrtcXTI); external, must be 32.768 kHz. + * + * TODO: Remove this once RTC clock is implemented properly as part of + * PMIC driver. + */ + rtcclk: clock-rtcclk { + compatible = "fixed-clock"; + clock-output-names = "rtcclk"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; +}; + +&cmu_hsi { + clocks = <&oscclk>, <&rtcclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "rtcclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; +}; + +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins + &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + key_voldown_pins: key-voldown-pins { + samsung,pins = "gpa1-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + key_volup_pins: key-volup-pins { + samsung,pins = "gpa0-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + micro_usb_det_pins: micro-usb-det-pins { + samsung,pins = "gpa0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&rtc { + status = "okay"; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>; + clock-names = "rtc", "rtc_src"; +}; + +&serial_0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usbdrd_phy { + status = "okay"; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&watchdog_cl0 { + status = "okay"; +}; + +&watchdog_cl1 { + status = "okay"; +}; diff --git a/arch/arm/dts/exynos850-pinctrl.dtsi b/arch/arm/dts/exynos850-pinctrl.dtsi new file mode 100644 index 00000000000..424bc80bde6 --- /dev/null +++ b/arch/arm/dts/exynos850-pinctrl.dtsi @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "exynos-pinctrl.h" + +&pinctrl_alive { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpa3: gpa3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpa4: gpa4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ + i2c5_pins: i2c5-pins { + samsung,pins = "gpa3-5", "gpa3-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + /* I2C6 (also called MOTOR_I2C in TRM) */ + i2c6_pins: i2c6-pins { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + /* USI: UART_DEBUG_0 pins */ + uart0_pins: uart0-pins { + samsung,pins = "gpq0-0", "gpq0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + /* USI: UART_DEBUG_1 pins */ + uart1_pins: uart1-pins { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpm1: gpm1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpm2: gpm2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpm3: gpm3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpm4: gpm4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpm5: gpm5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpm6: gpm6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpm7: gpm7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* USI_CMGP0: HSI2C function */ + hsi2c3_pins: hsi2c3-pins { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */ + uart1_single_pins: uart1-single-pins { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */ + uart1_dual_pins: uart1-dual-pins { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + /* USI_CMGP0: SPI function */ + spi1_pins: spi1-pins { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + /* USI_CMGP1: HSI2C function */ + hsi2c4_pins: hsi2c4-pins { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */ + uart2_single_pins: uart2-single-pins { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */ + uart2_dual_pins: uart2-dual-pins { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + /* USI_CMGP1: SPI function */ + spi2_pins: spi2-pins { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; +}; + +&pinctrl_aud { + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk_pins: aud-codec-mclk-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + aud_i2s0_pins: aud-i2s0-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + aud_i2s0_idle_pins: aud-i2s0-idle-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + aud_i2s1_pins: aud-i2s1-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + aud_i2s1_idle_pins: aud-i2s1-idle-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + aud_fm_pins: aud-fm-pins { + samsung,pins = "gpb1-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + aud_fm_idle_pins: aud-fm-idle-pins { + samsung,pins = "gpb1-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&pinctrl_hsi { + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk_pins: sd2-clk-pins { + samsung,pins = "gpf2-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>; + }; + + sd2_cmd_pins: sd2-cmd-pins { + samsung,pins = "gpf2-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>; + }; + + sd2_bus1_pins: sd2-bus1-pins { + samsung,pins = "gpf2-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>; + }; + + sd2_bus4_pins: sd2-bus4-pins { + samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>; + }; + + sd2_pdn_pins: sd2-pdn-pins { + samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&pinctrl_core { + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk_pins: sd0-clk-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; + }; + + sd0_cmd_pins: sd0-cmd-pins { + samsung,pins = "gpf0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; + }; + + sd0_rdqs_pins: sd0-rdqs-pins { + samsung,pins = "gpf0-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; + }; + + sd0_nreset_pins: sd0-nreset-pins { + samsung,pins = "gpf0-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; + }; + + sd0_bus1_pins: sd0-bus1-pins { + samsung,pins = "gpf1-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; + }; + + sd0_bus4_pins: sd0-bus4-pins { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; + }; + + sd0_bus8_pins: sd0-bus8-pins { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; + }; +}; + +&pinctrl_peri { + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sensor_mclk0_in_pins: sensor-mclk0-in-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + sensor_mclk0_out_pins: sensor-mclk0-out-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + sensor_mclk0_fn_pins: sensor-mclk0-fn-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + sensor_mclk1_in_pins: sensor-mclk1-in-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + sensor_mclk1_out_pins: sensor-mclk1-out-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + sensor_mclk1_fn_pins: sensor-mclk1-fn-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + sensor_mclk2_in_pins: sensor-mclk2-in-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + sensor_mclk2_out_pins: sensor-mclk2-out-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + sensor_mclk2_fn_pins: sensor-mclk2-fn-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; + }; + + /* USI: HSI2C0 */ + hsi2c0_pins: hsi2c0-pins { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + /* USI: HSI2C1 */ + hsi2c1_pins: hsi2c1-pins { + samsung,pins = "gpc1-2", "gpc1-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + /* USI: HSI2C2 */ + hsi2c2_pins: hsi2c2-pins { + samsung,pins = "gpc1-4", "gpc1-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + /* USI: SPI */ + spi0_pins: spi0-pins { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + i2c0_pins: i2c0-pins { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + i2c1_pins: i2c1-pins { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + i2c2_pins: i2c2-pins { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + i2c3_pins: i2c3-pins { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + i2c4_pins: i2c4-pins { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + xclkout_pins: xclkout-pins { + samsung,pins = "gpq0-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; +}; diff --git a/arch/arm/dts/exynos850.dtsi b/arch/arm/dts/exynos850.dtsi new file mode 100644 index 00000000000..53104e65b9c --- /dev/null +++ b/arch/arm/dts/exynos850.dtsi @@ -0,0 +1,809 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos850 based board files can include this file and provide + * values for board specific bindings. + */ + +#include <dt-bindings/clock/exynos850.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/samsung,exynos-usi.h> + +/ { + /* Also known under engineering name Exynos3830 */ + compatible = "samsung,exynos850"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_cmgp; + pinctrl2 = &pinctrl_aud; + pinctrl3 = &pinctrl_hsi; + pinctrl4 = &pinctrl_core; + pinctrl5 = &pinctrl_peri; + }; + + arm-pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* Main system clock (XTCXO); external, must be 26 MHz */ + oscclk: clock-oscclk { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x3>; + enable-method = "psci"; + }; + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x101>; + enable-method = "psci"; + }; + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x102>; + enable-method = "psci"; + }; + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x103>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + chipid@10000000 { + compatible = "samsung,exynos850-chipid"; + reg = <0x10000000 0x100>; + }; + + timer@10040000 { + compatible = "samsung,exynos850-mct", + "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + + gic: interrupt-controller@12a01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x12a01000 0x1000>, + <0x12a02000 0x2000>, + <0x12a04000 0x2000>, + <0x12a06000 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + pmu_system_controller: system-controller@11860000 { + compatible = "samsung,exynos850-pmu", "syscon"; + reg = <0x11860000 0x10000>; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ + mask = <0x2>; /* SWRESET_SYSTEM */ + value = <0x2>; /* reset value */ + }; + }; + + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynos850-wdt"; + reg = <0x10050000 0x100>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + status = "disabled"; + }; + + watchdog_cl1: watchdog@10060000 { + compatible = "samsung,exynos850-wdt"; + reg = <0x10060000 0x100>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <1>; + status = "disabled"; + }; + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos850-cmu-peri"; + reg = <0x10030000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names = "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + + cmu_g3d: clock-controller@11400000 { + compatible = "samsung,exynos850-cmu-g3d"; + reg = <0x11400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; + clock-names = "oscclk", "dout_g3d_switch"; + }; + + cmu_apm: clock-controller@11800000 { + compatible = "samsung,exynos850-cmu-apm"; + reg = <0x11800000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; + clock-names = "oscclk", "dout_clkcmu_apm_bus"; + }; + + cmu_cmgp: clock-controller@11c00000 { + compatible = "samsung,exynos850-cmu-cmgp"; + reg = <0x11c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; + clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; + }; + + cmu_core: clock-controller@12000000 { + compatible = "samsung,exynos850-cmu-core"; + reg = <0x12000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, + <&cmu_top CLK_DOUT_CORE_CCI>, + <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, + <&cmu_top CLK_DOUT_CORE_SSS>; + clock-names = "oscclk", "dout_core_bus", + "dout_core_cci", "dout_core_mmc_embd", + "dout_core_sss"; + }; + + cmu_top: clock-controller@120e0000 { + compatible = "samsung,exynos850-cmu-top"; + reg = <0x120e0000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + + cmu_mfcmscl: clock-controller@12c00000 { + compatible = "samsung,exynos850-cmu-mfcmscl"; + reg = <0x12c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_MFCMSCL_MFC>, + <&cmu_top CLK_DOUT_MFCMSCL_M2M>, + <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, + <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; + clock-names = "oscclk", "dout_mfcmscl_mfc", + "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", + "dout_mfcmscl_jpeg"; + }; + + cmu_dpu: clock-controller@13000000 { + compatible = "samsung,exynos850-cmu-dpu"; + reg = <0x13000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; + clock-names = "oscclk", "dout_dpu"; + }; + + cmu_hsi: clock-controller@13400000 { + compatible = "samsung,exynos850-cmu-hsi"; + reg = <0x13400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; + }; + + cmu_is: clock-controller@14500000 { + compatible = "samsung,exynos850-cmu-is"; + reg = <0x14500000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_IS_BUS>, + <&cmu_top CLK_DOUT_IS_ITP>, + <&cmu_top CLK_DOUT_IS_VRA>, + <&cmu_top CLK_DOUT_IS_GDC>; + clock-names = "oscclk", "dout_is_bus", "dout_is_itp", + "dout_is_vra", "dout_is_gdc"; + }; + + cmu_aud: clock-controller@14a00000 { + compatible = "samsung,exynos850-cmu-aud"; + reg = <0x14a00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; + clock-names = "oscclk", "dout_aud"; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11850000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos850-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@11c30000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11c30000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos850-wakeup-eint"; + }; + }; + + pinctrl_core: pinctrl@12070000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x12070000 0x1000>; + interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_hsi: pinctrl@13430000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_peri: pinctrl@139b0000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_aud: pinctrl@14a60000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x14a60000 0x1000>; + }; + + rtc: rtc@11a30000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x11a30000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; + clock-names = "rtc"; + status = "disabled"; + }; + + mmc_0: mmc@12100000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + reg = <0x12100000 0x2000>; + interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + i2c_0: i2c@13830000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13830000 0x100>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_1: i2c@13840000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13840000 0x100>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_2: i2c@13850000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13850000 0x100>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_3: i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_4: i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ + i2c_5: i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + /* I2C_6 (also called MOTOR_I2C in TRM) */ + i2c_6: i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + sysmmu_mfcmscl: sysmmu@12c50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12c50000 0x9000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "sysmmu"; + clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_dpu: sysmmu@130c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x130c0000 0x9000>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "sysmmu"; + clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_is0: sysmmu@14550000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14550000 0x9000>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "sysmmu"; + clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_is1: sysmmu@14570000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14570000 0x9000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "sysmmu"; + clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_aud: sysmmu@14850000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14850000 0x9000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "sysmmu"; + clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; + #iommu-cells = <0>; + }; + + sysreg_peri: syscon@10020000 { + compatible = "samsung,exynos850-peri-sysreg", + "samsung,exynos850-sysreg", "syscon"; + reg = <0x10020000 0x10000>; + clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; + }; + + sysreg_cmgp: syscon@11c20000 { + compatible = "samsung,exynos850-cmgp-sysreg", + "samsung,exynos850-sysreg", "syscon"; + reg = <0x11c20000 0x10000>; + clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; + }; + + usbdrd: usb@13600000 { + compatible = "samsung,exynos850-dwusb3"; + ranges = <0x0 0x13600000 0x10000>; + clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>, + <&cmu_hsi CLK_GOUT_USB_REF_CLK>; + clock-names = "bus_early", "ref"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbdrd_phy 0>; + phy-names = "usb2-phy"; + }; + }; + + usbdrd_phy: phy@135d0000 { + compatible = "samsung,exynos850-usbdrd-phy"; + reg = <0x135d0000 0x100>; + clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>, + <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + + usi_uart: usi@138200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138200c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1010>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_0: serial@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0xc0>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + + usi_hsi2c_0: usi@138a00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138a00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1020>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_0: i2c@138a0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138a0000 0xc0>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c0_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_hsi2c_1: usi@138b00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138b00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1030>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_1: i2c@138b0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138b0000 0xc0>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_hsi2c_2: usi@138c00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138c00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1040>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_2: i2c@138c0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138c0000 0xc0>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c2_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_spi_0: usi@139400c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x139400c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1050>; + samsung,mode = <USI_V2_SPI>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + }; + + usi_cmgp0: usi@11d000c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x11d000c0 0x20>; + samsung,sysreg = <&sysreg_cmgp 0x2000>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_3: i2c@11d00000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x11d00000 0xc0>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + + serial_1: serial@11d00000 { + compatible = "samsung,exynos850-uart"; + reg = <0x11d00000 0xc0>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_single_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + + usi_cmgp1: usi@11d200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x11d200c0 0x20>; + samsung,sysreg = <&sysreg_cmgp 0x2010>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_4: i2c@11d20000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x11d20000 0xc0>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c4_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + + serial_2: serial@11d20000 { + compatible = "samsung,exynos850-uart"; + reg = <0x11d20000 0xc0>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_single_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + }; +}; + +#include "exynos850-pinctrl.dtsi" diff --git a/arch/arm/dts/imx53-qsb-u-boot.dtsi b/arch/arm/dts/imx53-qsb-u-boot.dtsi new file mode 100644 index 00000000000..18cf7085cca --- /dev/null +++ b/arch/arm/dts/imx53-qsb-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi b/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi new file mode 100644 index 00000000000..8f5a70ccb85 --- /dev/null +++ b/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +#include "imx6qdl-u-boot.dtsi" + +/ { + binman: binman { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + offset = <0x0>; + filename = "SPL"; + }; + + uboot: blob-ext@2 { + offset = <0x11000>; + filename = "u-boot.img"; + }; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&fec { + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; +}; + +&gpmi { + fsl,legacy-bch-geometry; +}; diff --git a/arch/arm/dts/imx6dl-sielaff.dts b/arch/arm/dts/imx6dl-sielaff.dts new file mode 100644 index 00000000000..7de8d5f2651 --- /dev/null +++ b/arch/arm/dts/imx6dl-sielaff.dts @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include <dt-bindings/clock/imx6qdl-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Sielaff i.MX6 Solo"; + compatible = "sielaff,imx6dl-board", "fsl,imx6dl"; + + chosen { + stdout-path = &uart2; + }; + + backlight: pwm-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm3 0 50000 0>; + brightness-levels = <0 0 64 88 112 136 184 232 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + power-supply = <®_backlight>; + }; + + cec { + compatible = "cec-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + hdmi-phandle = <&hdmi>; + }; + + enet_ref: clock-enet-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet-ref"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-0 { + gpios = <&gpio2 16 0>; + debounce-interval = <10>; + linux,code = <1>; + }; + + key-1 { + gpios = <&gpio3 27 0>; + debounce-interval = <10>; + linux,code = <2>; + }; + + key-2 { + gpios = <&gpio5 4 0>; + debounce-interval = <10>; + linux,code = <3>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-debug { + label = "debug-led"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + device_type = "memory"; + }; + + osc_eth_phy: clock-osc-eth-phy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc-eth-phy"; + }; + + panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_backlight>; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + regulator-name = "backlight"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + /* + * Set PTP clock to external instead of internal reference, as the + * REF_CLK from the PHY is fed back into the i.MX6 and the GPR + * register needs to be set accordingly (see mach-imx6q.c). + */ + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&enet_ref>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + clocks = <&osc_eth_phy>; + clock-names = "rmii-ref"; + micrel,led-mode = <1>; + reset-assert-us = <500>; + reset-deassert-us = <100>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "key-out", "key-in", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "lan9500a-rst", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c4>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + touchscreen@55 { + compatible = "sitronix,st1633"; + reg = <0x55>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio5>; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <100000>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + usb1@1 { + compatible = "usb4b4,6570"; + reg = <1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <12000000 0>; + }; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "host"; + over-current-active-low; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_backlight: regbacklightgrp { + fsl,pins = < + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: regusbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1 + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi index 5c4101b76da..9e9c4422f00 100644 --- a/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi @@ -9,6 +9,11 @@ aliases { mmc1 = &usdhc3; }; + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog2>; + bootph-pre-ram; + }; }; &usdhc3 { @@ -18,3 +23,7 @@ &pinctrl_usdhc3 { bootph-pre-ram; }; + +&wdog2 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi index ebfb95dcdf4..e65eeb8d8ce 100644 --- a/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi @@ -9,6 +9,12 @@ soc { bootph-pre-ram; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &aips2 { @@ -26,3 +32,7 @@ &usdhc1 { bootph-pre-ram; }; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi index cb6ea356fd7..805b5f57955 100644 --- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi @@ -45,6 +45,9 @@ }; &ecspi1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; bootph-pre-ram; flash@0 { bootph-pre-ram; diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi index c398a743f7b..ce61ca6671e 100644 --- a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi @@ -9,6 +9,11 @@ model = "MSC SM2S-IMX8MPLUS"; compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp"; + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -63,3 +68,11 @@ &pmic { bootph-pre-ram; }; + +&uart2 { + bootph-pre-ram; +}; + +&pinctrl_uart2 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 1c7b2505499..b4efff27a70 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -70,6 +70,10 @@ bootph-pre-ram; }; +&usb_dwc3_0 { + dr_mode = "peripheral"; +}; + &usdhc2 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts index 6aa720bafe2..c8640cac3ed 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts @@ -19,6 +19,36 @@ stdout-path = &uart1; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb1_host_vbus"; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -57,6 +87,21 @@ }; }; +/* CAN FD */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -76,15 +121,15 @@ compatible = "nxp,pca9533"; reg = <0x62>; - led1 { + led-1 { type = <PCA9532_TYPE_LED>; }; - led2 { + led-2 { type = <PCA9532_TYPE_LED>; }; - led3 { + led-3 { type = <PCA9532_TYPE_LED>; }; }; @@ -101,8 +146,51 @@ status = "okay"; }; +/* USB1 Host mode Type-A */ +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB */ +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* RS232/RS485 */ +&uart2 { + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + /* SD-Card */ &usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <200000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; @@ -113,6 +201,33 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "", "", "X_PMIC_WDOG_B", "", + "PMIC_SD_VSEL", "", "", "", "", "", + "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "X_SD2_CD_B", "", "", "", + "", "", "", "SD2_RESET_B"; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "nCAN1_EN", "nCAN2_EN"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "", "", + "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN"; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -134,6 +249,32 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 @@ -161,6 +302,21 @@ >; }; + pinctrl_usb1_vbus: usb1vbusgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 + MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 + >; + }; + pinctrl_usdhc2_pins: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi new file mode 100644 index 00000000000..8bf28c2de87 --- /dev/null +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner <c.stoidner@phytec.de> + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX93 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ + */ + +#include "imx93-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_cd { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_default { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&wdog3 { + bootph-all; + bootph-pre-ram; +}; + +/* + * The two nodes below won't be needed once nxp,pca9451a + * support is added to the Linux kernel. + */ +&iomuxc { + pinctrl_lpi2c3: lpi2c3grp { + bootph-pre-ram; + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pmic: pmicgrp { + bootph-pre-ram; + fsl,pins = < + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e + >; + }; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + regulators { + bootph-pre-ram; + bootph-some-ram; + buck1: BUCK1 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3_BUCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "VDD_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "PMIC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx93-phyboard-segin.dts b/arch/arm/dts/imx93-phyboard-segin.dts new file mode 100644 index 00000000000..85fb188b057 --- /dev/null +++ b/arch/arm/dts/imx93-phyboard-segin.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX93 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ + */ +/dts-v1/; + +#include "imx93-phycore-som.dtsi" + +/{ + model = "PHYTEC phyBOARD-Segin-i.MX93"; + compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", + "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SD"; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + no-1-8-v; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/arch/arm/dts/imx93-phycore-som.dtsi b/arch/arm/dts/imx93-phycore-som.dtsi new file mode 100644 index 00000000000..88c2657b50e --- /dev/null +++ b/arch/arm/dts/imx93-phycore-som.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + * + * Product homepage: + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ + */ + +#include <dt-bindings/leds/common.h> + +#include "imx93.dtsi" + +/{ + model = "PHYTEC phyCORE-i.MX93"; + compatible = "phytec,imx93-phycore-som", "fsl,imx93"; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* Ethernet */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>, <50000000>; + status = "okay"; + + mdio: mdio { + clock-frequency = <5000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e + MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; +}; diff --git a/arch/arm/dts/imx93-var-som-symphony.dts b/arch/arm/dts/imx93-var-som-symphony.dts index a67bd005e54..1bc61942716 100644 --- a/arch/arm/dts/imx93-var-som-symphony.dts +++ b/arch/arm/dts/imx93-var-som-symphony.dts @@ -285,6 +285,24 @@ status = "okay"; }; +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + hnp-disable; + srp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + /* SD */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi index 90de635481f..d6964714ea0 100644 --- a/arch/arm/dts/imx93.dtsi +++ b/arch/arm/dts/imx93.dtsi @@ -149,6 +149,20 @@ }; }; + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -844,5 +858,49 @@ #power-domain-cells = <1>; status = "disabled"; }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c100000 0x200>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root_clk", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c100200 0x200>; + #index-cells = <1>; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c200000 0x200>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root_clk", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c200200 0x200>; + #index-cells = <1>; + }; }; }; diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi index 46928c07e97..e246de0299f 100644 --- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi @@ -5,6 +5,10 @@ */ / { + binman: binman { + multiple-images; + }; + chosen { bootph-pre-ram; }; diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi index a9095e736bf..3f54411b7b3 100644 --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi @@ -8,6 +8,10 @@ #include "imxrt1050-pinfunc.h" / { + binman: binman { + multiple-images; + }; + aliases { display0 = &lcdif; usbphy0 = &usbphy1; @@ -113,6 +117,33 @@ }; }; +&binman { +#ifdef CONFIG_FSPI_CONF_HEADER + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + fspi_conf_block { + filename = CONFIG_FSPI_CONF_FILE; + type = "blob-ext"; + offset = <0x0>; + }; + + spl { + filename = "SPL"; + offset = <0x1000>; + type = "blob-ext"; + }; + + binman_uboot: uboot { + filename = "u-boot.img"; + offset = <0x10000>; + type = "blob-ext"; + }; + }; +#endif +}; + &osc { bootph-pre-ram; }; diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi index f923a143014..6e892c1af76 100644 --- a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi @@ -6,6 +6,10 @@ */ / { + binman: binman { + multiple-images; + }; + chosen { bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index 2eb227c1d00..ea200a1ee1c 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -185,7 +185,7 @@ }; &serdes_ln_ctrl { - u-boot,mux-autoprobe; + bootph-all; }; &usbss0 { diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi index 017a5a722e0..f83caf79988 100644 --- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -165,7 +165,6 @@ &serdes_ln_ctrl { bootph-all; - u-boot,mux-autoprobe; }; &serdes2_usb_link { @@ -174,7 +173,6 @@ &usb_serdes_mux { bootph-all; - u-boot,mux-autoprobe; }; &serdes_wiz2 { diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 7ae7cf3d4c9..9433f3bafae 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -94,11 +94,11 @@ }; &serdes_ln_ctrl { - u-boot,mux-autoprobe; + bootph-all; }; &usb_serdes_mux { - u-boot,mux-autoprobe; + bootph-all; }; &main_usbss0_pins_default { diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 479b7bcd6f8..fff447094ae 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -90,11 +90,11 @@ }; &serdes_ln_ctrl { - u-boot,mux-autoprobe; + bootph-all; }; &usb_serdes_mux { - u-boot,mux-autoprobe; + bootph-all; }; &main_usbss0_pins_default { diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi index 1694ef88495..db7517cc9ba 100644 --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h> / { #address-cells = <2>; @@ -152,6 +153,7 @@ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_APB5>; clock-names = "clk_apb5"; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_PSPI2>; status = "disabled"; }; diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi index 4c6d5bed447..bc047d4b443 100644 --- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi @@ -20,34 +20,7 @@ compatible = "nuvoton,npcm845-reset", "syscon", "simple-mfd"; reg = <0x0 0xf0801000 0x0 0xC4>; - rstc1: reset-controller1 { - compatible = "syscon-reset"; - #reset-cells = <1>; - regmap = <&rstc>; - offset = <NPCM8XX_RESET_IPSRST1>; - mask = <0xFFFFFFFF>; - }; - rstc2: reset-controller2 { - compatible = "syscon-reset"; - #reset-cells = <1>; - regmap = <&rstc>; - offset = <NPCM8XX_RESET_IPSRST2>; - mask = <0xFFFFFFFF>; - }; - rstc3: reset-controller3 { - compatible = "syscon-reset"; - #reset-cells = <1>; - regmap = <&rstc>; - offset = <NPCM8XX_RESET_IPSRST3>; - mask = <0xFFFFFFFF>; - }; - rstc4: reset-controller4 { - compatible = "syscon-reset"; - #reset-cells = <1>; - regmap = <&rstc>; - offset = <NPCM8XX_RESET_IPSRST4>; - mask = <0xFFFFFFFF>; - }; + #reset-cells = <2>; }; clk: clock-controller@f0801000 { @@ -70,7 +43,7 @@ clock-names = "stmmaceth"; pinctrl-names = "default"; pinctrl-0 = <&rg1mdio_pins>; - resets = <&rstc2 NPCM8XX_RESET_GMAC1>; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC1>; status = "disabled"; }; @@ -85,7 +58,7 @@ pinctrl-names = "default"; pinctrl-0 = <&rg2_pins &rg2mdio_pins>; - resets = <&rstc2 NPCM8XX_RESET_GMAC2>; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC2>; status = "disabled"; }; @@ -101,7 +74,7 @@ pinctrl-0 = <&r1_pins &r1err_pins &r1md_pins>; - resets = <&rstc1 NPCM8XX_RESET_GMAC3>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC3>; status = "disabled"; }; @@ -117,7 +90,7 @@ pinctrl-0 = <&r2_pins &r2err_pins &r2md_pins>; - resets = <&rstc1 NPCM8XX_RESET_GMAC4>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC4>; status = "disabled"; }; @@ -125,7 +98,7 @@ compatible = "nuvoton,npcm845-ehci"; reg = <0x0 0xf0828100 0x0 0x1000>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstc2 NPCM8XX_RESET_USBH1>; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>; status = "disabled"; }; @@ -133,21 +106,21 @@ compatible = "nuvoton,npcm845-ehci"; reg = <0x0 0xf082a100 0x0 0x1000>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstc4 NPCM8XX_RESET_USBH2>; + resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>; status = "disabled"; }; ohci1: usb@f0829000 { compatible = "nuvoton,npcm845-ohci"; reg = <0x0 0xF0829000 0x0 0x1000>; - resets = <&rstc2 NPCM8XX_RESET_USBH1>; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>; status = "disabled"; }; ohci2: usb@f082b000 { compatible = "nuvoton,npcm845-ohci"; reg = <0x0 0xF082B000 0x0 0x1000>; - resets = <&rstc4 NPCM8XX_RESET_USBH2>; + resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>; status = "disabled"; }; @@ -160,21 +133,21 @@ compatible = "nuvoton,npcm845-usb-phy"; #phy-cells = <1>; reg = <1>; - resets = <&rstc3 NPCM8XX_RESET_USBPHY1>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY1>; status = "disabled"; }; usbphy2: usbphy@2 { compatible = "nuvoton,npcm845-usb-phy"; #phy-cells = <1>; reg = <2>; - resets = <&rstc3 NPCM8XX_RESET_USBPHY2>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY2>; status = "disabled"; }; usbphy3: usbphy@3 { compatible = "nuvoton,npcm845-usb-phy"; #phy-cells = <1>; reg = <3>; - resets = <&rstc4 NPCM8XX_RESET_USBPHY3>; + resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBPHY3>; status = "disabled"; }; }; @@ -186,7 +159,7 @@ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc3 NPCM8XX_RESET_UDC0>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC0>; status = "disable"; }; @@ -197,7 +170,7 @@ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC1>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC1>; status = "disable"; }; @@ -208,7 +181,7 @@ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC2>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC2>; status = "disable"; }; @@ -219,7 +192,7 @@ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC3>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC3>; status = "disable"; }; @@ -230,7 +203,7 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC4>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC4>; status = "disable"; }; @@ -241,7 +214,7 @@ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC5>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC5>; status = "disable"; }; @@ -252,7 +225,7 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC6>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC6>; status = "disable"; }; @@ -263,7 +236,7 @@ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc3 NPCM8XX_RESET_UDC7>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC7>; status = "disable"; }; @@ -274,7 +247,7 @@ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc3 NPCM8XX_RESET_UDC8>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC8>; status = "disable"; }; @@ -285,7 +258,7 @@ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc3 NPCM8XX_RESET_UDC9>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC9>; status = "disable"; }; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi new file mode 100644 index 00000000000..c8a46219826 --- /dev/null +++ b/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Gray Hawk CPU board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +#include "r8a779h0.dtsi" + +/ { + model = "Renesas Gray Hawk CPU board"; + compatible = "renesas,grayhawk-cpu", "renesas,r8a779h0"; + + aliases { + ethernet0 = &avb0; + serial0 = &hscif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:921600n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x1 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi new file mode 100644 index 00000000000..fcdd8eb8d54 --- /dev/null +++ b/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M Gray Hawk CSI/DSI sub-board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +&i2c0 { + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "csi-dsi-sub-board-id"; + reg = <0x52>; + pagesize = <8>; + }; +}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi new file mode 100644 index 00000000000..5a8e598c986 --- /dev/null +++ b/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M Gray Hawk Ethernet sub-board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +&i2c0 { + eeprom@53 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board-id"; + reg = <0x53>; + pagesize = <8>; + }; +}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts new file mode 100644 index 00000000000..935ba9465dc --- /dev/null +++ b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Gray Hawk board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include "r8a779h0-gray-hawk.dts" +#include "r8a779h0-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&pfc { + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk.dts b/arch/arm/dts/r8a779h0-gray-hawk.dts new file mode 100644 index 00000000000..59e5e493ad1 --- /dev/null +++ b/arch/arm/dts/r8a779h0-gray-hawk.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Gray Hawk CPU and BreakOut boards + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779h0-gray-hawk-cpu.dtsi" +#include "r8a779h0-gray-hawk-csi-dsi.dtsi" +#include "r8a779h0-gray-hawk-ethernet.dtsi" + +/ { + model = "Renesas Gray Hawk CPU and Breakout boards based on r8a779h0"; + compatible = "renesas,gray-hawk-breakout", "renesas,gray-hawk-cpu", "renesas,r8a779h0"; +}; + +&i2c0 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi b/arch/arm/dts/r8a779h0-u-boot.dtsi new file mode 100644 index 00000000000..b2f7e054eef --- /dev/null +++ b/arch/arm/dts/r8a779h0-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include "r8a779x-u-boot.dtsi" +/ { + soc { + rpc: spi@ee200000 { + compatible = "renesas,r8a779h0-rpc-if", "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + bank-width = <2>; + num-cs = <1>; + status = "disabled"; + }; + }; +}; + +&extalr_clk { + bootph-all; +}; diff --git a/arch/arm/dts/r8a779h0.dtsi b/arch/arm/dts/r8a779h0.dtsi new file mode 100644 index 00000000000..a896bc27f5a --- /dev/null +++ b/arch/arm/dts/r8a779h0.dtsi @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M (R8A779H0) SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/renesas,r8a779h0-sysc.h> + +/ { + compatible = "renesas,r8a779h0"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; + }; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a779h0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, + <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, + <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; + }; + + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 19>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + }; + + gpio2: gpio@e6058180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058180 0 0x54>; + interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 20>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; + + gpio3: gpio@e6058980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058980 0 0x54>; + interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; + + gpio4: gpio@e6060180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060180 0 0x54>; + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 25>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio5: gpio@e6060980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060980 0 0x54>; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio6: gpio@e6061180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061180 0 0x54>; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio7: gpio@e6061980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061980 0 0x54>; + interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779h0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779h0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779h0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + avb0: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6800000 0 0x800>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 211>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 211>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb1: ethernet@e6810000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6810000 0 0x800>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 212>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 212>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb2: ethernet@e6820000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6820000 0 0x1000>; + interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 213>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 213>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779h0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 706>, + <&cpg CPG_CORE R8A779H0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 732727d9b03..089732524a7 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -9,6 +9,28 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci; }; + + smbios { + compatible = "u-boot,sysinfo-smbios"; + smbios { + system { + manufacturer = "Pine64"; + product = "RockPro64"; + }; + + baseboard { + manufacturer = "Pine64"; + product = "RockPro64"; + }; + + chassis { + manufacturer = "Pine64"; + product = "RockPro64"; + }; + }; + }; + + }; &sdhci { diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index f986e1941e7..fa3df73c33d 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -4,7 +4,6 @@ / { chosen { - stdout-path = &uart2; u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0; }; @@ -88,9 +87,3 @@ vqmmc-supply = <&vcc_1v8>; status = "okay"; }; - -&uart2 { - clock-frequency = <24000000>; - bootph-all; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi index ad43fa199ca..8cbf3d9a4f2 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi @@ -191,30 +191,30 @@ }; }; - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; + leds: pwm-leds { + compatible = "pwm-leds"; green_led: led-0 { color = <LED_COLOR_ID_GREEN>; default-state = "on"; function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; }; amber_led: led-1 { color = <LED_COLOR_ID_AMBER>; function = LED_FUNCTION_CHARGING; - gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - retain-state-suspended; + max-brightness = <255>; + pwms = <&pwm7 0 25000 0>; }; red_led: led-2 { color = <LED_COLOR_ID_RED>; default-state = "off"; function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + max-brightness = <255>; + pwms = <&pwm0 0 25000 0>; }; }; @@ -356,7 +356,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -371,7 +370,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_gpu"; @@ -533,7 +531,6 @@ regulator-boot-on; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1390000>; - regulator-init-microvolt = <900000>; regulator-name = "vdd_cpu"; regulator-ramp-delay = <2300>; vin-supply = <&vcc_sys>; @@ -597,15 +594,6 @@ }; }; - gpio-led { - led_pins: led-pins { - rockchip,pins = - <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - joy-mux { joy_mux_en: joy-mux-en { rockchip,pins = @@ -654,10 +642,24 @@ vccio7-supply = <&vcc_3v3>; }; +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pwm5 { status = "okay"; }; +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8>; status = "okay"; diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi index 06cc15ed21b..930d660868b 100644 --- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi +++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -2,19 +2,12 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &gpio0 { bootph-all; }; &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; @@ -28,12 +21,6 @@ }; }; -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - /* * U-Boot does not support multiple regulators using the same gpio, * use vcc5v0_usb20_host to fix use of USB 2.0 port diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts index 25a8c781f4e..59843a7a199 100644 --- a/arch/arm/dts/rk3566-quartz64-a.dts +++ b/arch/arm/dts/rk3566-quartz64-a.dts @@ -31,8 +31,9 @@ fan: gpio_fan { compatible = "gpio-fan"; gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 4500 1>; + gpio-fan,speed-map = + < 0 0>, + <4500 1>; pinctrl-names = "default"; pinctrl-0 = <&fan_en_h>; #cooling-cells = <2>; @@ -366,7 +367,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -381,7 +381,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_gpu"; diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi index 3c2c54e9418..c235b4357f7 100644 --- a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi +++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi @@ -2,15 +2,8 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; @@ -24,12 +17,6 @@ }; }; -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3566-quartz64-b.dts b/arch/arm/dts/rk3566-quartz64-b.dts index b276eb0810c..2d92713be2a 100644 --- a/arch/arm/dts/rk3566-quartz64-b.dts +++ b/arch/arm/dts/rk3566-quartz64-b.dts @@ -277,7 +277,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-state-mem { @@ -292,7 +291,6 @@ regulator-boot-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-state-mem { diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index c925439f71c..e0e501deccf 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -5,19 +5,6 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; -}; - -&uart2 { - clock-frequency = <24000000>; - bootph-all; - status = "okay"; }; diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts index 5e4236af4fc..3ae24e39450 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io.dts +++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts @@ -14,6 +14,7 @@ compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; aliases { + ethernet0 = &gmac1; mmc1 = &sdmmc0; }; @@ -137,8 +138,8 @@ &mdio1 { rgmii_phy1: ethernet-phy@0 { - compatible="ethernet-phy-ieee802.3-c22"; - reg= <0x0>; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; }; }; diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts index 4e49bebf548..fdbf1c78324 100644 --- a/arch/arm/dts/rk3566-soquartz-blade.dts +++ b/arch/arm/dts/rk3566-soquartz-blade.dts @@ -13,6 +13,10 @@ model = "PINE64 RK3566 SOQuartz on Blade carrier board"; compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; + aliases { + ethernet0 = &gmac1; + }; + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ vcc3v0_sd: vcc3v0-sd-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts b/arch/arm/dts/rk3566-soquartz-cm4.dts index cddf6cd2fec..6ed3fa4aee3 100644 --- a/arch/arm/dts/rk3566-soquartz-cm4.dts +++ b/arch/arm/dts/rk3566-soquartz-cm4.dts @@ -8,6 +8,10 @@ model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566"; + aliases { + ethernet0 = &gmac1; + }; + /* labeled +12v in schematic */ vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts b/arch/arm/dts/rk3566-soquartz-model-a.dts index 2208dbfb7f0..f2095dfa4ea 100644 --- a/arch/arm/dts/rk3566-soquartz-model-a.dts +++ b/arch/arm/dts/rk3566-soquartz-model-a.dts @@ -8,6 +8,10 @@ model = "PINE64 RK3566 SOQuartz on Model A carrier board"; compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; + aliases { + ethernet0 = &gmac1; + }; + /* labeled DCIN_12V in schematic */ vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi index 793cca2ceac..5e46a2422d6 100644 --- a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi +++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi @@ -2,25 +2,12 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3566-soquartz.dtsi b/arch/arm/dts/rk3566-soquartz.dtsi index 31aa2b8efe3..bfb7b952f4c 100644 --- a/arch/arm/dts/rk3566-soquartz.dtsi +++ b/arch/arm/dts/rk3566-soquartz.dtsi @@ -12,7 +12,6 @@ compatible = "pine64,soquartz", "rockchip,rk3566"; aliases { - ethernet0 = &gmac1; mmc0 = &sdmmc0; mmc1 = &sdhci; mmc2 = &sdmmc1; @@ -234,7 +233,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-state-mem { @@ -249,7 +247,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-state-mem { @@ -272,7 +269,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-name = "vdd_npu"; regulator-state-mem { diff --git a/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi index 60a3b21f2d4..5f4f14b3bda 100644 --- a/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi @@ -4,16 +4,3 @@ */ #include "rk356x-u-boot.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; -}; - -&uart2 { - clock-frequency = <24000000>; - bootph-pre-ram; - status = "okay"; -}; - diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb-u-boot.dtsi index 382a52a28b1..5f4f14b3bda 100644 --- a/arch/arm/dts/rk3568-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi @@ -4,20 +4,3 @@ */ #include "rk356x-u-boot.dtsi" - -/ { - chosen { - stdout-path = &uart2; - u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; - }; -}; - -&sdmmc0 { - status = "okay"; -}; - -&uart2 { - clock-frequency = <24000000>; - bootph-pre-ram; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts index 674792567fa..19f8fc369b1 100644 --- a/arch/arm/dts/rk3568-evb.dts +++ b/arch/arm/dts/rk3568-evb.dts @@ -293,7 +293,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -307,7 +306,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -331,7 +329,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; diff --git a/arch/arm/dts/rk3568-generic-u-boot.dtsi b/arch/arm/dts/rk3568-generic-u-boot.dtsi index 90022580a13..6e8307e3bdf 100644 --- a/arch/arm/dts/rk3568-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3568-generic-u-boot.dtsi @@ -1,14 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk356x-u-boot.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; -}; - -&uart2 { - bootph-pre-ram; - clock-frequency = <24000000>; -}; diff --git a/arch/arm/dts/rk3568-generic.dts b/arch/arm/dts/rk3568-generic.dts index 1006ea55bb9..88eb1bfd2aa 100644 --- a/arch/arm/dts/rk3568-generic.dts +++ b/arch/arm/dts/rk3568-generic.dts @@ -10,7 +10,12 @@ model = "Generic RK3566/RK3568"; compatible = "rockchip,rk3568"; - chosen: chosen { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { stdout-path = "serial2:1500000n8"; }; }; @@ -18,6 +23,9 @@ &sdhci { bus-width = <8>; cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; @@ -28,6 +36,8 @@ bus-width = <4>; cap-sd-highspeed; disable-wp; + no-mmc; + no-sdio; pinctrl-names = "default"; pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; status = "okay"; diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi index 27c62775233..1597473017e 100644 --- a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi +++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi @@ -6,22 +6,9 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; - -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts index e653b067aa5..a8a4cc190eb 100644 --- a/arch/arm/dts/rk3568-lubancat-2.dts +++ b/arch/arm/dts/rk3568-lubancat-2.dts @@ -243,7 +243,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; @@ -258,7 +257,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; @@ -284,7 +282,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi index 880f8ff91fc..64c43374c04 100644 --- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -8,31 +8,18 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &pcie3x1 { /delete-property/ vpcie3v3-supply; }; &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; -&uart2 { - clock-frequency = <24000000>; - bootph-all; - status = "okay"; -}; - &vcc5v0_usb_host { /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dtsi b/arch/arm/dts/rk3568-nanopi-r5s.dtsi index 58ba328ea78..93189f83064 100644 --- a/arch/arm/dts/rk3568-nanopi-r5s.dtsi +++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi @@ -232,7 +232,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -246,7 +245,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -270,7 +268,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi index 0fc360b06df..1fc71faa9e0 100644 --- a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi +++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi @@ -2,19 +2,12 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &fspi_dual_io_pins { bootph-all; }; &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; @@ -29,9 +22,3 @@ bootph-pre-ram; }; }; - -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-odroid-m1.dts b/arch/arm/dts/rk3568-odroid-m1.dts index 59ecf868dbd..a337f547caf 100644 --- a/arch/arm/dts/rk3568-odroid-m1.dts +++ b/arch/arm/dts/rk3568-odroid-m1.dts @@ -291,7 +291,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -305,7 +304,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -329,7 +327,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi index c50fbdd4868..45b03dcbbad 100644 --- a/arch/arm/dts/rk3568-radxa-cm3i.dtsi +++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi @@ -163,7 +163,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -177,7 +176,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -201,7 +199,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi index 1136f0bb3b8..74755a44eae 100644 --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -2,12 +2,6 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &pcie3x1 { pinctrl-0 = <&pcie30x1_reset_h>; }; @@ -22,18 +16,11 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; }; -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index b05b7151e6c..5b823fcca5f 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &pcie3x2 { pinctrl-0 = <&pcie3x2_reset_h>; }; @@ -26,7 +20,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; @@ -48,9 +41,3 @@ spi-tx-bus-width = <1>; }; }; - -&uart2 { - clock-frequency = <24000000>; - bootph-all; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts index 917f5b2b8aa..a5e974ea659 100644 --- a/arch/arm/dts/rk3568-rock-3a.dts +++ b/arch/arm/dts/rk3568-rock-3a.dts @@ -15,6 +15,7 @@ ethernet0 = &gmac1; mmc0 = &sdhci; mmc1 = &sdmmc0; + mmc2 = &sdmmc2; }; chosen: chosen { @@ -350,7 +351,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -364,7 +364,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -388,7 +387,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -750,6 +748,9 @@ non-removable; pinctrl-names = "default"; pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; sd-uhs-sdr104; vmmc-supply = <&vcc3v3_sys>; vqmmc-supply = <&vcc_1v8>; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 354b6958e57..d347080577d 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -19,7 +19,6 @@ dmc: dmc { compatible = "rockchip,rk3568-dmc"; bootph-all; - status = "okay"; }; otp: nvmem@fe38c000 { @@ -27,7 +26,6 @@ reg = <0x0 0xfe38c000 0x0 0x4000>; #address-cells = <1>; #size-cells = <1>; - status = "okay"; cpu_id: id@a { reg = <0x0a 0x10>; @@ -37,27 +35,22 @@ &xin24m { bootph-all; - status = "okay"; }; &cru { bootph-all; - status = "okay"; }; &pmucru { bootph-all; - status = "okay"; }; &grf { bootph-all; - status = "okay"; }; &pmugrf { bootph-all; - status = "okay"; }; &pinctrl { @@ -141,6 +134,11 @@ bootph-pre-ram; }; +&uart2 { + bootph-pre-ram; + clock-frequency = <24000000>; +}; + #ifdef CONFIG_ROCKCHIP_SPI_IMAGE &binman { simple-bin-spi { diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi index 61680c7ac48..c19c0f1b377 100644 --- a/arch/arm/dts/rk356x.dtsi +++ b/arch/arm/dts/rk356x.dtsi @@ -613,6 +613,17 @@ #iommu-cells = <0>; }; + rga: rga@fdeb0000 { + compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; + reg = <0x0 0xfdeb0000 0x0 0x180>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3568_PD_RGA>; + }; + vepu: video-codec@fdee0000 { compatible = "rockchip,rk3568-vepu"; reg = <0x0 0xfdee0000 0x0 0x800>; @@ -948,6 +959,13 @@ reg = <0x0 0xfe1a8100 0x0 0x20>; }; + dfi: dfi@fe230000 { + compatible = "rockchip,rk3568-dfi"; + reg = <0x00 0xfe230000 0x00 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + rockchip,pmu = <&pmugrf>; + }; + pcie2x1: pcie@fe260000 { compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0000000 0x0 0x00400000>, @@ -959,7 +977,7 @@ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "sys", "pmc", "msi", "legacy", "err"; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; bus-range = <0x0 0xf>; clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts index b5154389207..be6a4f4f90f 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts @@ -12,10 +12,6 @@ compatible = "edgeble,neural-compute-module-6a-io", "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - aliases { - serial2 = &uart2; - }; - chosen { stdout-path = "serial2:1500000n8"; }; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts index 9933765e409..070baeb6343 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts @@ -9,13 +9,9 @@ / { model = "Edgeble Neu6B IO Board"; - compatible = "edgeble,neural-compute-module-6b-io", + compatible = "edgeble,neural-compute-module-6a-io", "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - aliases { - serial2 = &uart2; - }; - chosen { stdout-path = "serial2:1500000n8"; }; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts index b9d789d5786..ac7c677b0fb 100644 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -16,8 +16,8 @@ compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588"; aliases { + ethernet0 = &gmac0; mmc0 = &sdhci; - serial2 = &uart2; }; chosen { @@ -56,6 +56,63 @@ }; }; + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,name = "RK3588 EVB1 Audio"; + simple-audio-card,aux-devs = <&_headphone>, <&_speaker>; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&masterdai>; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,pin-switches = "Headphones", "Speaker"; + simple-audio-card,routing = + "Speaker Amplifier INL", "LOUT2", + "Speaker Amplifier INR", "ROUT2", + "Speaker", "Speaker Amplifier OUTL", + "Speaker", "Speaker Amplifier OUTR", + "Headphones Amplifier INL", "LOUT1", + "Headphones Amplifier INR", "ROUT1", + "Headphones", "Headphones Amplifier OUTL", + "Headphones", "Headphones Amplifier OUTR", + "LINPUT1", "Onboard Microphone", + "RINPUT1", "Onboard Microphone", + "LINPUT2", "Microphone Jack", + "RINPUT2", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + amp_headphone: headphone-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&headphone_amplifier_en>; + sound-name-prefix = "Headphones Amplifier"; + }; + + amp_speaker: speaker-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&speaker_amplifier_en>; + sound-name-prefix = "Speaker Amplifier"; + }; + backlight: backlight { compatible = "pwm-backlight"; power-supply = <&vcc12v_dcin>; @@ -240,6 +297,32 @@ }; }; +&i2c7 { + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + AVDD-supply = <&avcc_1v8_codec_s0>; + DVDD-supply = <&avcc_1v8_codec_s0>; + HPVDD-supply = <&vcc_3v3_s0>; + PVDD-supply = <&vcc_3v3_s0>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + &mdio0 { rgmii_phy: ethernet-phy@1 { /* RTL8211F */ @@ -273,6 +356,20 @@ }; &pinctrl { + audio { + hp_detect: headphone-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + headphone_amplifier_en: headphone-amplifier-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + speaker_amplifier_en: speaker-amplifier-en { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + rtl8111 { rtl8111_isolate: rtl8111-isolate { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi index 87831c9d432..60494bb8485 100644 --- a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi +++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3588-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; - &fspim1_pins { bootph-all; }; diff --git a/arch/arm/dts/rk3588-nanopc-t6.dts b/arch/arm/dts/rk3588-nanopc-t6.dts index 97af4f91282..d7722772ecd 100644 --- a/arch/arm/dts/rk3588-nanopc-t6.dts +++ b/arch/arm/dts/rk3588-nanopc-t6.dts @@ -19,7 +19,6 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc; - serial2 = &uart2; }; chosen { @@ -537,13 +536,12 @@ }; &sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; disable-wp; + no-mmc; + no-sdio; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vccio_sd_s0>; @@ -570,6 +568,8 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc4v0_sys>; vcc2-supply = <&vcc4v0_sys>; vcc3-supply = <&vcc4v0_sys>; @@ -590,7 +590,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi index b0f5c667197..5d5fa6ffb21 100644 --- a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi @@ -2,12 +2,6 @@ #include "rk3588-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; - &fspim1_pins { bootph-all; }; diff --git a/arch/arm/dts/rk3588-orangepi-5-plus.dts b/arch/arm/dts/rk3588-orangepi-5-plus.dts index 298c183d6f4..3e660ff6cd5 100644 --- a/arch/arm/dts/rk3588-orangepi-5-plus.dts +++ b/arch/arm/dts/rk3588-orangepi-5-plus.dts @@ -19,7 +19,6 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc; - serial2 = &uart2; }; chosen { diff --git a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi index 191ec988c45..7b937943a53 100644 --- a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi @@ -4,9 +4,3 @@ */ #include "rk3588-u-boot.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; diff --git a/arch/arm/dts/rk3588-quartzpro64.dts b/arch/arm/dts/rk3588-quartzpro64.dts index 5c59f9571dc..87a0abf95f7 100644 --- a/arch/arm/dts/rk3588-quartzpro64.dts +++ b/arch/arm/dts/rk3588-quartzpro64.dts @@ -17,9 +17,9 @@ compatible = "pine64,quartzpro64", "rockchip,rk3588"; aliases { + ethernet0 = &gmac0; mmc0 = &sdhci; mmc1 = &sdmmc; - serial2 = &uart2; }; chosen { diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index b595ddef702..9ee9dd051e3 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -7,10 +7,6 @@ #include <dt-bindings/usb/pd.h> / { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; - vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -21,10 +17,6 @@ }; }; -&combphy2_psu { - status = "okay"; -}; - &fspim2_pins { bootph-all; }; @@ -39,7 +31,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; @@ -129,10 +120,6 @@ status = "okay"; }; -&usb_host2_xhci { - status = "okay"; -}; - &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4m1_xfer>; diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 741f631db34..a0e303c3a1d 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -14,7 +14,6 @@ mmc0 = &sdhci; mmc1 = &sdmmc; mmc2 = &sdio; - serial2 = &uart2; }; chosen { @@ -138,6 +137,10 @@ status = "okay"; }; +&combphy2_psu { + status = "okay"; +}; + &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; }; @@ -423,6 +426,8 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; vcc3-supply = <&vcc5v0_sys>; @@ -443,7 +448,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; @@ -765,3 +770,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi index 06c6f327c14..ca2a684f354 100644 --- a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi +++ b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi @@ -6,20 +6,12 @@ #include "rk3588-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; &uart9 { bootph-pre-ram; clock-frequency = <24000000>; - status = "okay"; }; diff --git a/arch/arm/dts/rk3588-turing-rk1.dtsi b/arch/arm/dts/rk3588-turing-rk1.dtsi index 9570b34aca2..dc08da518a7 100644 --- a/arch/arm/dts/rk3588-turing-rk1.dtsi +++ b/arch/arm/dts/rk3588-turing-rk1.dtsi @@ -19,8 +19,6 @@ aliases { ethernet0 = &gmac1; mmc0 = &sdhci; - serial2 = &uart2; - serial9 = &uart9; }; fan: pwm-fan { @@ -235,13 +233,13 @@ &pinctrl { fan { fan_int: fan-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; hym8563 { hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 31046fc7feb..992f7b5d663 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -7,7 +7,7 @@ / { usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, diff --git a/arch/arm/dts/rk3588s-orangepi-5.dts b/arch/arm/dts/rk3588s-orangepi-5.dts index 8f399c4317b..25de4362af3 100644 --- a/arch/arm/dts/rk3588s-orangepi-5.dts +++ b/arch/arm/dts/rk3588s-orangepi-5.dts @@ -13,8 +13,8 @@ compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; aliases { + ethernet0 = &gmac1; mmc0 = &sdmmc; - serial2 = &uart2; }; chosen { @@ -38,7 +38,7 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 =<&leds_gpio>; + pinctrl-0 = <&leds_gpio>; led-1 { gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; @@ -314,6 +314,7 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; spi-max-frequency = <1000000>; + system-power-controller; vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; @@ -660,3 +661,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi index 63151d9d237..30db12c4fc8 100644 --- a/arch/arm/dts/rk3588s-pinctrl.dtsi +++ b/arch/arm/dts/rk3588s-pinctrl.dtsi @@ -369,7 +369,7 @@ emmc_data_strobe: emmc-data-strobe { rockchip,pins = /* emmc_data_strobe */ - <2 RK_PA2 1 &pcfg_pull_none>; + <2 RK_PA2 1 &pcfg_pull_down>; }; }; diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index 584476f77b1..efba0c359ba 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -5,14 +5,7 @@ #include "rk3588s-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts index 8347adcbd00..2002fd0221f 100644 --- a/arch/arm/dts/rk3588s-rock-5a.dts +++ b/arch/arm/dts/rk3588s-rock-5a.dts @@ -12,9 +12,9 @@ compatible = "radxa,rock-5a", "rockchip,rk3588s"; aliases { + ethernet0 = &gmac1; mmc0 = &sdhci; mmc1 = &sdmmc; - serial2 = &uart2; }; analog-sound { @@ -114,6 +114,10 @@ }; }; +&combphy2_psu { + status = "okay"; +}; + &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; }; @@ -734,3 +738,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index c0fd16c4022..bf3b1ea8a3c 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -7,22 +7,20 @@ / { aliases { - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; spi5 = &sfc; }; + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; + dmc { compatible = "rockchip,rk3588-dmc"; bootph-all; - status = "okay"; }; usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc000000 0x0 0x400000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, @@ -43,33 +41,6 @@ status = "disabled"; }; - usb_host2_xhci: usb@fcd00000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfcd00000 0x0 0x400000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, - <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, - <&cru CLK_PIPEPHY2_PIPE_U3_G>; - clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; - dr_mode = "host"; - phys = <&combphy2_psu PHY_TYPE_USB3>; - phy-names = "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_A_USB3OTG2>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - pmu1_grf: syscon@fd58a000 { - bootph-all; - compatible = "rockchip,rk3588-pmu1-grf", "syscon"; - reg = <0x0 0xfd58a000 0x0 0x2000>; - }; - usbdpphy0_grf: syscon@fd5c8000 { compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; reg = <0x0 0xfd5c8000 0x0 0x4000>; @@ -193,17 +164,18 @@ &xin24m { bootph-all; - status = "okay"; }; &cru { bootph-pre-ram; - status = "okay"; }; &sys_grf { bootph-pre-ram; - status = "okay"; +}; + +&pmu1grf { + bootph-all; }; &scmi { @@ -241,9 +213,8 @@ }; &uart2 { - clock-frequency = <24000000>; bootph-pre-ram; - status = "okay"; + clock-frequency = <24000000>; }; &uart2m0_xfer { diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 61a9a11c3bb..36b1b7acfe6 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -18,6 +18,38 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -362,6 +394,11 @@ #clock-cells = <0>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, @@ -443,11 +480,47 @@ status = "disabled"; }; + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; }; + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + }; + php_grf: syscon@fd5b0000 { compatible = "rockchip,rk3588-php-grf", "syscon"; reg = <0x0 0xfd5b0000 0x0 0x1000>; @@ -567,6 +640,74 @@ status = "disabled"; }; + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + uart0: serial@fd890000 { compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; reg = <0x0 0xfd890000 0x0 0x100>; @@ -890,6 +1031,7 @@ reg = <RK3588_PD_USB>; clocks = <&cru PCLK_PHP_ROOT>, <&cru ACLK_USB_ROOT>, + <&cru ACLK_USB>, <&cru HCLK_USB_ROOT>, <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, @@ -1329,6 +1471,16 @@ }; }; + dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; + rockchip,pmu = <&pmu1grf>; + }; + gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts index dded0a12f0c..0c2396b8f8d 100644 --- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts @@ -20,6 +20,76 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + v3v3_sys: v3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_ETHERNET_OUT>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; + assigned-clock-rates = <125000000>, <0>, <25000000>; + clock_in_out = "input"; + phy-handle = <&phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>; + tx_delay = <0x2a>; + rx_delay = <0x1a>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm11 { + status = "okay"; }; &sdmmc { diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/dts/rv1126-edgeble-neu2.dtsi index cc64ba4be34..7ea8d7d16f5 100644 --- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi +++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi @@ -11,15 +11,6 @@ mmc0 = &emmc; }; - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - vccio_flash: vccio-flash-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -52,7 +43,7 @@ bus-width = <8>; non-removable; pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>; rockchip,default-sample-phase = <90>; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&vccio_flash>; @@ -301,6 +292,22 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &sdio { bus-width = <4>; cap-sd-highspeed; diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi index 28d8d29942f..f84f5f2d961 100644 --- a/arch/arm/dts/rv1126-pinctrl.dtsi +++ b/arch/arm/dts/rv1126-pinctrl.dtsi @@ -11,6 +11,14 @@ * by adding changes at end of this file. */ &pinctrl { + clk_out_ethernet { + /omit-if-no-ref/ + clk_out_ethernetm1_pins: clk-out-ethernetm1-pins { + rockchip,pins = + /* clk_out_ethernet_m1 */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + }; emmc { /omit-if-no-ref/ emmc_rstnout: emmc-rstnout { @@ -51,6 +59,24 @@ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; }; }; + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PA3 3 &pcfg_pull_down>, + /* fspi_cs0n */ + <0 RK_PD4 3 &pcfg_pull_up>, + /* fspi_d0 */ + <1 RK_PA0 3 &pcfg_pull_up>, + /* fspi_d1 */ + <1 RK_PA1 3 &pcfg_pull_up>, + /* fspi_d2 */ + <0 RK_PD6 3 &pcfg_pull_up>, + /* fspi_d3 */ + <1 RK_PA2 3 &pcfg_pull_up>; + }; + }; i2c0 { /omit-if-no-ref/ i2c0_xfer: i2c0-xfer { @@ -61,6 +87,86 @@ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; }; }; + i2c2 { + /omit-if-no-ref/ + i2c2_xfer: i2c2-xfer { + rockchip,pins = + /* i2c2_scl */ + <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c2_sda */ + <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_pin_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_pin_m0 */ + <3 RK_PA7 6 &pcfg_pull_none>; + }; + }; + rgmii { + /omit-if-no-ref/ + rgmiim1_miim: rgmiim1-miim { + rockchip,pins = + /* rgmii_mdc_m1 */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_rxer: rgmiim1-rxer { + rockchip,pins = + /* rgmii_rxer_m1 */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_bus2: rgmiim1-bus2 { + rockchip,pins = + /* rgmii_rxd0_m1 */ + <2 RK_PB5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <2 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <2 RK_PB4 2 &pcfg_pull_none>, + /* rgmii_txd0_m1 */ + <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd1_m1 */ + <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_bus4: rgmiim1-bus4 { + rockchip,pins = + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd2_m1 */ + <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd3_m1 */ + <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_mclkinout: rgmiim1-mclkinout { + rockchip,pins = + /* rgmii_clk_m1 */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + }; sdmmc0 { /omit-if-no-ref/ sdmmc0_bus4: sdmmc0-bus4 { @@ -187,6 +293,14 @@ /* uart3_tx_m0 */ <3 RK_PC6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <3 RK_PA1 4 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <3 RK_PA0 4 &pcfg_pull_up>; + }; }; uart4 { /omit-if-no-ref/ @@ -197,6 +311,14 @@ /* uart4_tx_m0 */ <3 RK_PA4 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PD4 3 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; }; uart5 { /omit-if-no-ref/ @@ -207,5 +329,13 @@ /* uart5_tx_m0 */ <3 RK_PA6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PA0 3 &pcfg_pull_up>; + }; }; }; diff --git a/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi new file mode 100644 index 00000000000..a625660d583 --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rv1126-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&sdio { + status = "disabled"; +}; diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dts b/arch/arm/dts/rv1126-sonoff-ihost.dts new file mode 100644 index 00000000000..77386a48d81 --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-sonoff-ihost.dtsi" + +/ { + model = "Sonoff iHost 4G"; + compatible = "itead,sonoff-ihost", "rockchip,rv1126"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dtsi b/arch/arm/dts/rv1126-sonoff-ihost.dtsi new file mode 100644 index 00000000000..32b329e87a0 --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost.dtsi @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-name = "vdd_npu_vepu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-name = "vcc_0v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-name = "vcc0v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-name = "vcc_dovdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-name = "vcc_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-name = "vcc_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "xin32k"; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>, + <&cru CLK_GMAC_TX_RX>; + assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>, + <&cru RMII_MODE_CLK>; + assigned-clock-rates = <0>, <50000000>; + clock_in_out = "output"; + phy-handle = <&phy>; + phy-mode = "rmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-active-low; + reset-assert-us = <50000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + bt { + bt_enable: bt-enable { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc1v8_pmu>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vcc_1v8>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_dovdd>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_dovdd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723ds-bt"; + device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */ + enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */ + host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */ + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi index 1cb43147e90..bb603cae13d 100644 --- a/arch/arm/dts/rv1126.dtsi +++ b/arch/arm/dts/rv1126.dtsi @@ -21,6 +21,13 @@ aliases { i2c0 = &i2c0; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; }; cpus { @@ -83,6 +90,11 @@ clock-frequency = <24000000>; }; + display_subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -125,6 +137,26 @@ reg = <0xfe86c000 0x20>; }; + qos_iep: qos@fe8a0000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0000 0x20>; + }; + + qos_rga_rd: qos@fe8a0080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0080 0x20>; + }; + + qos_rga_wr: qos@fe8a0100 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0100 0x20>; + }; + + qos_vop: qos@fe8a0180 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0180 0x20>; + }; + gic: interrupt-controller@feff0000 { compatible = "arm,gic-400"; interrupt-controller; @@ -170,6 +202,25 @@ pm_qos = <&qos_sdio>; #power-domain-cells = <0>; }; + + power-domain@RV1126_PD_VO { + reg = <RV1126_PD_VO>; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru CLK_RGA_CORE>, + <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP>, + <&cru PCLK_DSIHOST>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru CLK_IEP_CORE>; + pm_qos = <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_vop>, + <&qos_iep>; + #power-domain-cells = <0>; + }; }; }; @@ -187,6 +238,20 @@ status = "disabled"; }; + i2c2: i2c@ff400000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff400000 0x1000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@ff410000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff410000 0x100>; @@ -203,6 +268,17 @@ status = "disabled"; }; + pwm2: pwm@ff430020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430020 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + pmucru: clock-controller@ff480000 { compatible = "rockchip,rv1126-pmucru"; reg = <0xff480000 0x1000>; @@ -232,6 +308,17 @@ clock-names = "apb_pclk"; }; + pwm11: pwm@ff550030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550030 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@ff560000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff560000 0x100>; @@ -332,6 +419,92 @@ clock-names = "pclk", "timer"; }; + vop: vop@ffb00000 { + compatible = "rockchip,rv1126-vop"; + reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + reset-names = "axi", "ahb", "dclk"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + iommus = <&vop_mmu>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + }; + }; + }; + + vop_mmu: iommu@ffb00f00 { + compatible = "rockchip,iommu"; + reg = <0xffb00f00 0x100>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + #iommu-cells = <0>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + }; + + gmac: ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x4000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_GMAC_A>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + emmc: mmc@ffc50000 { compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0xffc50000 0x4000>; @@ -370,6 +543,18 @@ status = "disabled"; }; + sfc: spi@ffc90000 { + compatible = "rockchip,sfc"; + reg = <0xffc90000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <80000000>; + clock-names = "clk_sfc", "hclk_sfc"; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rv1126-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/dts/vexpress-v2p-ca9.dts b/arch/arm/dts/vexpress-v2p-ca9.dts index bf00c62bcf6..e5b86c0d673 100644 --- a/arch/arm/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/dts/vexpress-v2p-ca9.dts @@ -20,7 +20,9 @@ #address-cells = <1>; #size-cells = <1>; - chosen { }; + chosen { + stdout-path = &v2m_serial0; + }; aliases { serial0 = &v2m_serial0; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index f8c786ab0b7..75dfd2f069d 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -44,7 +44,7 @@ }; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index f1b0a4aa65d..0b97fa3f28a 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -449,6 +449,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; + silabs,skip-recall; }; }; i2c@6 { /* USER_SI570_1 */ @@ -463,6 +464,7 @@ factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; + silabs,skip-recall; }; }; @@ -560,6 +562,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; + silabs,skip-recall; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ @@ -574,6 +577,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; + silabs,skip-recall; }; }; i2c@6 { /* HSDP_SI570 */ @@ -588,6 +592,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; + silabs,skip-recall; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 766f78303ee..5202b7c4819 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -32,6 +32,18 @@ #clock-cells = <0>; clock-frequency = <26000000>; }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; &can0 { @@ -354,3 +366,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; + +&zynqmp_dpsub { + status = "disabled"; +}; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 7717abf7bd8..ce7c5eb6d34 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -25,37 +25,43 @@ io-channels = <&u14 0>, <&u14 1>, <&u14 2>; }; - si5332_0: si5332-0 { /* u17 - GEM0/1 */ + clk_27: clock0 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_125: si5332-0 { /* u17 - GEM0/1 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; - si5332_1: si5332-1 { /* u17 - DP */ + clk_74: si5332-5 { /* u17 - SLVC-EC */ compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <27000000>; + clock-frequency = <74250000>; }; - si5332_2: si5332-2 { /* u17 - USB */ + clk_26: si5332-2 { /* u17 - USB */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5332_3: si5332-3 { /* u17 - SFP+ */ + clk_156: si5332-3 { /* u17 - SFP+ */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <156250000>; }; - si5332_4: si5332-4 { /* u17 - GEM2 */ + clk_25_0: si5332-1 { /* u17 - GEM2 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - si5332_5: si5332-5 { /* u17 - GEM3 */ + clk_25_1: si5332-4 { /* u17 - GEM3 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -115,7 +121,7 @@ &psgtr { status = "okay"; /* gem0/1, dp, usb */ - clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>; + clocks = <&clk_125>, <&clk_27>, <&clk_26>; clock-names = "ref0", "ref1", "ref2"; }; @@ -168,12 +174,13 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - +#if 0 usbhub1: usb-hub { /* u84 */ i2c-bus = <&usbhub_i2c1>; compatible = "microchip,usb5744"; reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_1 { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 21187396326..6c29f657413 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -60,6 +60,12 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + + clk_74: clock6 { /* u88 - SLVC-EC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -169,11 +175,13 @@ reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; +#if 0 usbhub1: usb-hub { /* u84 */ i2c-bus = <&usbhub_i2c1>; compatible = "microchip,usb5744"; reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_1 { diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 63238c08780..b50b83b7723 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -207,68 +207,71 @@ mbox-names = "tx", "rx"; }; - nvmem-firmware { + soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - soc_revision: soc-revision@0 { - reg = <0x0 0x4>; - }; - /* efuse access */ - efuse_dna: efuse-dna@c { - reg = <0xc 0xc>; - }; - efuse_usr0: efuse-usr0@20 { - reg = <0x20 0x4>; - }; - efuse_usr1: efuse-usr1@24 { - reg = <0x24 0x4>; - }; - efuse_usr2: efuse-usr2@28 { - reg = <0x28 0x4>; - }; - efuse_usr3: efuse-usr3@2c { - reg = <0x2c 0x4>; - }; - efuse_usr4: efuse-usr4@30 { - reg = <0x30 0x4>; - }; - efuse_usr5: efuse-usr5@34 { - reg = <0x34 0x4>; - }; - efuse_usr6: efuse-usr6@38 { - reg = <0x38 0x4>; - }; - efuse_usr7: efuse-usr7@3c { - reg = <0x3c 0x4>; - }; - efuse_miscusr: efuse-miscusr@40 { - reg = <0x40 0x4>; - }; - efuse_chash: efuse-chash@50 { - reg = <0x50 0x4>; - }; - efuse_pufmisc: efuse-pufmisc@54 { - reg = <0x54 0x4>; - }; - efuse_sec: efuse-sec@58 { - reg = <0x58 0x4>; - }; - efuse_spkid: efuse-spkid@5c { - reg = <0x5c 0x4>; - }; - efuse_aeskey: efuse-aeskey@60 { - reg = <0x60 0x20>; - }; - efuse_ppk0hash: efuse-ppk0hash@a0 { - reg = <0xa0 0x30>; - }; - efuse_ppk1hash: efuse-ppk1hash@d0 { - reg = <0xd0 0x30>; - }; - efuse_pufuser: efuse-pufuser@100 { - reg = <0x100 0x7F>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; + /* efuse access */ + efuse_dna: efuse-dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse-usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse-usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse-usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse-usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse-usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse-usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse-usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse-usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse-miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse-chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse-pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse-sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse-spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_aeskey: efuse-aeskey@60 { + reg = <0x60 0x20>; + }; + efuse_ppk0hash: efuse-ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse-ppk1hash@d0 { + reg = <0xd0 0x30>; + }; + efuse_pufuser: efuse-pufuser@100 { + reg = <0x100 0x7F>; + }; }; }; @@ -303,11 +306,7 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; - edac { - compatible = "arm,cortex-a53-edac"; - }; - - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; diff --git a/arch/arm/include/asm/arch-imx9/mu.h b/arch/arm/include/asm/arch-imx9/mu.h new file mode 100644 index 00000000000..b8604992914 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/mu.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + */ + +#ifndef __ARCH_IMX9_MU_H +#define __ARCH_IMX9_MU_H + +#include <event.h> + +int imx9_probe_mu(void *ctx, struct event *event); + +#endif diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S index 3c2cef6ec73..fe6eca576ec 100644 --- a/arch/arm/lib/crt0_aarch64_efi.S +++ b/arch/arm/lib/crt0_aarch64_efi.S @@ -66,7 +66,11 @@ extra_header_fields: .long _start - ImageBase /* SizeOfHeaders */ .long 0 /* CheckSum */ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ +#if CONFIG_VENDOR_EFI .short 0 /* DllCharacteristics */ +#else + .short IMAGE_DLLCHARACTERISTICS_NX_COMPAT +#endif .quad 0 /* SizeOfStackReserve */ .quad 0 /* SizeOfStackCommit */ .quad 0 /* SizeOfHeapReserve */ diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S index 75ee37b7d31..b5dfd4e3819 100644 --- a/arch/arm/lib/crt0_arm_efi.S +++ b/arch/arm/lib/crt0_arm_efi.S @@ -23,7 +23,7 @@ pe_header: .long IMAGE_NT_SIGNATURE /* 'PE' */ coff_header: .short IMAGE_FILE_MACHINE_THUMB /* Mixed ARM/Thumb */ - .short 2 /* nr_sections */ + .short 3 /* nr_sections */ .long 0 /* TimeDateStamp */ .long 0 /* PointerToSymbolTable */ .long 0 /* NumberOfSymbols */ @@ -65,7 +65,11 @@ extra_header_fields: .long _start - image_base /* SizeOfHeaders */ .long 0 /* CheckSum */ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ +#if CONFIG_VENDOR_EFI .short 0 /* DllCharacteristics */ +#else + .short IMAGE_DLLCHARACTERISTICS_NX_COMPAT +#endif .long 0 /* SizeOfStackReserve */ .long 0 /* SizeOfStackCommit */ .long 0 /* SizeOfHeapReserve */ @@ -98,31 +102,53 @@ section_table: .long 0 /* PointerToLineNumbers */ .short 0 /* NumberOfRelocations */ .short 0 /* NumberOfLineNumbers */ - .long 0x42100040 /* Characteristics (section flags) */ + /* Characteristics (section flags) */ + .long (IMAGE_SCN_MEM_READ | \ + IMAGE_SCN_MEM_DISCARDABLE | \ + IMAGE_SCN_CNT_INITIALIZED_DATA) .ascii ".text" .byte 0 .byte 0 .byte 0 /* end of 0 padding of section name */ - .long _edata - _start /* VirtualSize */ + .long _text_size /* VirtualSize */ .long _start - image_base /* VirtualAddress */ - .long _edata - _start /* SizeOfRawData */ + .long _text_size /* SizeOfRawData */ .long _start - image_base /* PointerToRawData */ + .long 0 /* PointerToRelocations */ + .long 0 /* PointerToLineNumbers */ + .short 0 /* NumberOfRelocations */ + .short 0 /* NumberOfLineNumbers */ + /* Characteristics (section flags) */ + .long (IMAGE_SCN_MEM_READ | \ + IMAGE_SCN_MEM_EXECUTE | \ + IMAGE_SCN_CNT_CODE) - .long 0 /* PointerToRelocations (0 for executables) */ - .long 0 /* PointerToLineNumbers (0 for executables) */ - .short 0 /* NumberOfRelocations (0 for executables) */ - .short 0 /* NumberOfLineNumbers (0 for executables) */ - .long 0xe0500020 /* Characteristics (section flags) */ + .ascii ".data" + .byte 0 + .byte 0 + .byte 0 /* end of 0 padding of section name */ + .long _data_size /* VirtualSize */ + .long _data - image_base /* VirtualAddress */ + .long _data_size /* SizeOfRawData */ + .long _data - image_base /* PointerToRawData */ + .long 0 /* PointerToRelocations */ + .long 0 /* PointerToLineNumbers */ + .short 0 /* NumberOfRelocations */ + .short 0 /* NumberOfLineNumbers */ + /* Characteristics (section flags) */ + .long (IMAGE_SCN_MEM_WRITE | \ + IMAGE_SCN_MEM_READ | \ + IMAGE_SCN_CNT_INITIALIZED_DATA) - .align 9 + .align 12 _start: stmfd sp!, {r0-r2, lr} adr r1, .L_DYNAMIC ldr r0, [r1] add r1, r0, r1 - adr r0, image_base + adrl r0, image_base bl _relocate teq r0, #0 bne 0f diff --git a/arch/arm/lib/elf_arm_efi.lds b/arch/arm/lib/elf_arm_efi.lds index 767ebda6351..41440594aa6 100644 --- a/arch/arm/lib/elf_arm_efi.lds +++ b/arch/arm/lib/elf_arm_efi.lds @@ -7,6 +7,12 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) + +PHDRS +{ + data PT_LOAD FLAGS(3); /* PF_W | PF_X */ +} + ENTRY(_start) SECTIONS { @@ -18,11 +24,13 @@ SECTIONS *(.gnu.linkonce.t.*) *(.srodata) *(.rodata*) + . = ALIGN(16); + *(.dynamic); . = ALIGN(512); } _etext = .; _text_size = . - _text; - .dynamic : { *(.dynamic) } + . = ALIGN(4096); .data : { _data = .; *(.sdata) @@ -47,14 +55,20 @@ SECTIONS . = ALIGN(512); _bss_end = .; _edata = .; - } - .rel.dyn : { *(.rel.dyn) } - .rel.plt : { *(.rel.plt) } - .rel.got : { *(.rel.got) } - .rel.data : { *(.rel.data) *(.rel.data*) } - _data_size = . - _etext; + } :data + _data_size = . - _data; /DISCARD/ : { + /* + * We don't support relocations. These would have to be + * translated from ELF to PE format and added to the .reloc + * section. + */ + *(.rel.dyn) + *(.rel.plt) + *(.rel.got) + *(.rel.data) + *(.rel.data*) *(.rel.reloc) *(.eh_frame) *(.note.GNU-stack) diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index 4ccaf69693d..6de99e7ea12 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -6,7 +6,10 @@ #ifndef _BCM283x_BASE_H_ #define _BCM283x_BASE_H_ -extern unsigned long rpi_bcm283x_base; +extern unsigned long rpi_mbox_base; +extern unsigned long rpi_timer_base; +extern unsigned long rpi_sdhci_base; +extern unsigned long rpi_wdog_base; #ifdef CONFIG_ARMV7_LPAE #ifdef CONFIG_TARGET_RPI_4_32B diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 490664f878f..35d4e2f0754 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -38,8 +38,7 @@ /* Raw mailbox HW */ -#define BCM2835_MBOX_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \ - rpi_bcm283x_base + 0x0000b880; }) +#define BCM2835_MBOX_PHYSADDR rpi_mbox_base struct bcm2835_mbox_regs { u32 read; diff --git a/arch/arm/mach-bcm283x/include/mach/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h index 73236906870..e837c679c46 100644 --- a/arch/arm/mach-bcm283x/include/mach/sdhci.h +++ b/arch/arm/mach-bcm283x/include/mach/sdhci.h @@ -8,8 +8,7 @@ #include <asm/arch/base.h> -#define BCM2835_SDHCI_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \ - rpi_bcm283x_base + 0x00300000; }) +#define BCM2835_SDHCI_PHYSADDR rpi_sdhci_base int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq); diff --git a/arch/arm/mach-bcm283x/include/mach/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h index 5567dbd7f3d..60500a256d0 100644 --- a/arch/arm/mach-bcm283x/include/mach/timer.h +++ b/arch/arm/mach-bcm283x/include/mach/timer.h @@ -11,8 +11,7 @@ #include <linux/bug.h> #endif -#define BCM2835_TIMER_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \ - rpi_bcm283x_base + 0x00003000; }) +#define BCM2835_TIMER_PHYSADDR rpi_timer_base #define BCM2835_TIMER_CS_M3 (1 << 3) #define BCM2835_TIMER_CS_M2 (1 << 2) diff --git a/arch/arm/mach-bcm283x/include/mach/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h index 99426667205..b9505606749 100644 --- a/arch/arm/mach-bcm283x/include/mach/wdog.h +++ b/arch/arm/mach-bcm283x/include/mach/wdog.h @@ -8,8 +8,7 @@ #include <asm/arch/base.h> -#define BCM2835_WDOG_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \ - rpi_bcm283x_base + 0x00100000; }) +#define BCM2835_WDOG_PHYSADDR rpi_wdog_base struct bcm2835_wdog_regs { u32 unknown0[7]; diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 7265faf6cec..016bc1eb412 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -68,6 +68,36 @@ static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = { } }; +static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = { + { + /* First 1GB of DRAM */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Beginning of AXI bus where uSD controller lives */ + .virt = 0x1000000000UL, + .phys = 0x1000000000UL, + .size = 0x0002000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* SoC bus */ + .virt = 0x107c000000UL, + .phys = 0x107c000000UL, + .size = 0x0004000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map = bcm283x_mem_map; /* @@ -78,6 +108,7 @@ static const struct udevice_id board_ids[] = { { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map}, { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map}, { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map}, + { .compatible = "brcm,bcm2712", .data = (ulong)&bcm2712_mem_map}, { }, }; @@ -115,7 +146,11 @@ static void rpi_update_mem_map(void) static void rpi_update_mem_map(void) {} #endif -unsigned long rpi_bcm283x_base = 0x3f000000; +/* Default bcm283x devices addresses */ +unsigned long rpi_mbox_base = 0x3f00b880; +unsigned long rpi_sdhci_base = 0x3f300000; +unsigned long rpi_wdog_base = 0x3f100000; +unsigned long rpi_timer_base = 0x3f003000; int arch_cpu_init(void) { @@ -126,22 +161,45 @@ int arch_cpu_init(void) int mach_cpu_init(void) { - int ret, soc_offset; + int ret, soc, offset; u64 io_base, size; rpi_update_mem_map(); /* Get IO base from device tree */ - soc_offset = fdt_path_offset(gd->fdt_blob, "/soc"); - if (soc_offset < 0) - return soc_offset; + soc = fdt_path_offset(gd->fdt_blob, "/soc"); + if (soc < 0) + return soc; - ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL, - &io_base, &size); + ret = fdt_read_range((void *)gd->fdt_blob, soc, 0, NULL, + &io_base, &size); if (ret) return ret; - rpi_bcm283x_base = io_base; + rpi_mbox_base = io_base + 0x00b880; + rpi_sdhci_base = io_base + 0x300000; + rpi_wdog_base = io_base + 0x100000; + rpi_timer_base = io_base + 0x003000; + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc, + "brcm,bcm2835-mbox"); + if (offset > soc) + rpi_mbox_base = fdt_get_base_address(gd->fdt_blob, offset); + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc, + "brcm,bcm2835-sdhci"); + if (offset > soc) + rpi_sdhci_base = fdt_get_base_address(gd->fdt_blob, offset); + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc, + "brcm,bcm2835-system-timer"); + if (offset > soc) + rpi_timer_base = fdt_get_base_address(gd->fdt_blob, offset); + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc, + "brcm,bcm2712-pm"); + if (offset > soc) + rpi_wdog_base = fdt_get_base_address(gd->fdt_blob, offset); return 0; } diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8f3aee052c8..af00ee1db07 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -2,7 +2,7 @@ if ARCH_EXYNOS config BOARD_COMMON def_bool y - depends on !TARGET_SMDKV310 && !TARGET_ARNDALE + depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_E850_96 config SPI_BOOTING bool @@ -58,6 +58,15 @@ config ARCH_EXYNOS7 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are multiple SoCs in this family including Exynos7420. +config ARCH_EXYNOS9 + bool "Exynos9 SoC family" + select ARM64 + select BLK + select DM_MMC + help + Samsung Exynos9 SoC family are based on ARMv8 Cortex CPU. There are + multiple SoCs in this family including Exynos850. + endchoice if ARCH_EXYNOS4 @@ -228,6 +237,22 @@ config TARGET_A3Y17LTE endchoice endif +if ARCH_EXYNOS9 + +choice + prompt "EXYNOS9 board select" + +config TARGET_E850_96 + bool "WinLink E850-96 board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS850 + +endchoice +endif + config SYS_SOC default "exynos" @@ -252,5 +277,6 @@ source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" source "board/samsung/axy17lte/Kconfig" +source "board/samsung/e850-96/Kconfig" endif diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c index 8d8c64e8f8f..30e522804fb 100644 --- a/arch/arm/mach-exynos/mmu-arm64.c +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/armv8/mmu.h> +#include <linux/sizes.h> #if IS_ENABLED(CONFIG_EXYNOS7420) @@ -95,4 +96,37 @@ static struct mm_region exynos7880_mem_map[] = { }; struct mm_region *mem_map = exynos7880_mem_map; + +#elif IS_ENABLED(CONFIG_EXYNOS850) + +static struct mm_region exynos850_mem_map[] = { + { + /* Peripheral block */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = SZ_256M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DDR, 32-bit area */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* DDR, 64-bit area */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + } +}; + +struct mm_region *mem_map = exynos850_mem_map; + #endif diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 39ac0bc4140..0b91e448a5d 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -45,6 +45,45 @@ struct pass_over_info_t *get_pass_over_info(void) return p; } +static char *get_reset_cause(void) +{ + sc_pm_reset_reason_t reason; + + if (sc_pm_reset_reason(-1, &reason) != SC_ERR_NONE) + return "Unknown reset"; + + switch (reason) { + case SC_PM_RESET_REASON_POR: + return "POR"; + case SC_PM_RESET_REASON_JTAG: + return "JTAG reset "; + case SC_PM_RESET_REASON_SW: + return "Software reset"; + case SC_PM_RESET_REASON_WDOG: + return "Watchdog reset"; + case SC_PM_RESET_REASON_LOCKUP: + return "SCU lockup reset"; + case SC_PM_RESET_REASON_SNVS: + return "SNVS reset"; + case SC_PM_RESET_REASON_TEMP: + return "Temp panic reset"; + case SC_PM_RESET_REASON_MSI: + return "MSI reset"; + case SC_PM_RESET_REASON_UECC: + return "ECC reset"; + case SC_PM_RESET_REASON_SCFW_WDOG: + return "SCFW watchdog reset"; + case SC_PM_RESET_REASON_ROM_WDOG: + return "SCU ROM watchdog reset"; + case SC_PM_RESET_REASON_SECO: + return "SECO reset"; + case SC_PM_RESET_REASON_SCFW_FAULT: + return "SCFW fault reset"; + default: + return "Unknown reset"; + } +} + int arch_cpu_init(void) { #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) @@ -322,6 +361,8 @@ int print_bootinfo(void) break; } + printf("Reset cause: %s\n", get_reset_cause()); + return 0; } diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 961d6f527ab..b79485f1f75 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -37,9 +37,15 @@ config TARGET_IMX93_VAR_SOM select IMX93 select IMX9_LPDDR4X +config TARGET_PHYCORE_IMX93 + bool "phycore_imx93" + select IMX93 + select IMX9_LPDDR4X + endchoice source "board/freescale/imx93_evk/Kconfig" +source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 92c41e9a67b..75d92af036a 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -882,6 +882,11 @@ int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type device_is_compatible(dev, "nxp,imx93-dwmac-eqos")) return imx93_eqos_interface_init(dev, interface_type); + if (IS_ENABLED(CONFIG_IMX93) && + IS_ENABLED(CONFIG_FEC_MXC) && + device_is_compatible(dev, "fsl,imx93-fec")) + return 0; + return -EINVAL; } diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index c1d6b09e775..ccccf702f67 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -2,6 +2,7 @@ if ARCH_IMXRT config IMXRT bool + select BINMAN select SYS_FSL_ERRATUM_ESDHC135 config IMXRT1020 diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 114cce4d9b9..15ee2b933f6 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -356,6 +356,15 @@ config TARGET_MX6Q_ACC select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6S_SIELAFF + bool "Sielaff i.MX6 Solo Board" + depends on MX6S + select BINMAN + select DM + select DM_THERMAL + select SUPPORT_SPL + imply CMD_DM + config TARGET_MX6SABREAUTO bool "mx6sabreauto" depends on MX6QDL @@ -708,6 +717,7 @@ source "board/softing/vining_2000/Kconfig" source "board/liebherr/display5/Kconfig" source "board/liebherr/mccmon6/Kconfig" source "board/logicpd/imx6/Kconfig" +source "board/sielaff/imx6dl-sielaff/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/somlabs/visionsom-6ull/Kconfig" source "board/technexion/pico-imx6/Kconfig" diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index fb0708bae16..3374889558a 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -228,7 +228,7 @@ void k3_mem_init(void) panic("DRAM 0 init failed: %d\n", ret); ret = uclass_next_device_err(&dev); - if (ret) + if (ret && ret != -ENODEV) panic("DRAM 1 init failed: %d\n", ret); } spl_enable_cache(); diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 94e6fe1f228..9bf71a9b453 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -7,40 +7,20 @@ choice config TARGET_K2HK_EVM bool "TI Keystone 2 Kepler/Hawking EVM" select SOC_K2HK - select SPL_BOARD_INIT if SPL - select CMD_DDR3 - imply DM_I2C - imply SOC_TI - imply TI_KEYSTONE_SERDES config TARGET_K2E_EVM bool "TI Keystone 2 Edison EVM" select SOC_K2E - select SPL_BOARD_INIT if SPL - select CMD_DDR3 - imply DM_I2C - imply SOC_TI - imply TI_KEYSTONE_SERDES config TARGET_K2L_EVM bool "TI Keystone 2 Lamar EVM" select SOC_K2L - select SPL_BOARD_INIT if SPL - select CMD_DDR3 - imply DM_I2C - imply SOC_TI - imply TI_KEYSTONE_SERDES config TARGET_K2G_EVM bool "TI Keystone 2 Galileo EVM" select BOARD_LATE_INIT select SOC_K2G - select SPL_BOARD_INIT if SPL select TI_I2C_BOARD_DETECT - select CMD_DDR3 - imply DM_I2C - imply SOC_TI - imply TI_KEYSTONE_SERDES endchoice diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index c3872f42869..82018bd9d3e 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -133,7 +133,6 @@ config SYS_BOARD be used. config SYS_CONFIG_NAME - string "Board configuration name" default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -145,11 +144,6 @@ config SYS_CONFIG_NAME default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518 - default "" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. config MTK_BROM_HEADER_INFO string diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index d6c89058061..6e6f9c13f17 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -88,12 +88,4 @@ config SYS_BOARD Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will be used. -config SYS_CONFIG_NAME - string "Board configuration name" - default "meson64" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - endif diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 b/arch/arm/mach-rmobile/Kconfig.rcar4 index d4f93c89cac..e80dce11f54 100644 --- a/arch/arm/mach-rmobile/Kconfig.rcar4 +++ b/arch/arm/mach-rmobile/Kconfig.rcar4 @@ -20,6 +20,12 @@ config R8A779G0 imply CLK_R8A779G0 imply PINCTRL_PFC_R8A779G0 +config R8A779H0 + bool "Renesas SoC R8A779H0" + select GICV3 + imply CLK_R8A779H0 + imply PINCTRL_PFC_R8A779H0 + endmenu choice @@ -44,10 +50,17 @@ config TARGET_WHITEHAWK help Support for Renesas R-Car Gen4 White Hawk platform +config TARGET_GRAYHAWK + bool "Gray Hawk board" + imply R8A779H0 + help + Support for Renesas R-Car Gen4 Gray Hawk platform + endchoice source "board/renesas/falcon/Kconfig" source "board/renesas/spider/Kconfig" source "board/renesas/whitehawk/Kconfig" +source "board/renesas/grayhawk/Kconfig" endif diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 895c0f5336b..3d5d5ba79a9 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -78,6 +78,7 @@ static const struct { { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" }, { RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" }, { RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" }, + { RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 88b8b78671b..f0216210ba9 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -43,6 +43,7 @@ #define RMOBILE_CPU_TYPE_R8A779A0 0x59 #define RMOBILE_CPU_TYPE_R8A779F0 0x5A #define RMOBILE_CPU_TYPE_R8A779G0 0x5C +#define RMOBILE_CPU_TYPE_R8A779H0 0x5D #define RMOBILE_CPU_TYPE_R9A07G044L 0x9A070440 #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6ff0aa6911e..1bc7ee90427 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -265,6 +265,7 @@ config ROCKCHIP_RK3399 imply TPL_TINY_MEMSET imply TPL_ROCKCHIP_COMMON_BOARD imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 @@ -292,6 +293,8 @@ config ROCKCHIP_RK3568 imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT help The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, including NEON and GPU, 512K L3 cache, Mali-G52 based graphics, @@ -317,8 +320,11 @@ config ROCKCHIP_RK3588 imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT imply CLK_SCMI imply SCMI_FIRMWARE + imply BOOTSTD_FULL help The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4, @@ -359,6 +365,7 @@ config ROCKCHIP_RV1126 select PMIC_RK8XX select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c index e8772d3a382..7b2cf37d9da 100644 --- a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c @@ -10,7 +10,7 @@ static const struct udevice_id rk3588_syscon_ids[] = { { .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF }, - { .compatible = "rockchip,rk3588-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { .compatible = "rockchip,rk3588-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, { .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF }, { .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF }, { .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF }, diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index a6e2b5903c6..55b11121203 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -14,6 +14,13 @@ config TARGET_RV1126_NEU2 IO board and Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. +config TARGET_RV1126_SONOFF_IHOST + bool "Sonoff iHost smart home hub" + help + Sonoff iHost is a smart home gateway based on Rockchip RV1126 SoC. + It features Wifi, Bluetooth and Zigbee radios that are used by many + smart home devices. + config SOC_SPECIFIC_OPTIONS # dummy def_bool y select HAS_CUSTOM_SYS_INIT_SP_ADDR @@ -58,5 +65,6 @@ config TEXT_BASE default 0x600000 source board/edgeble/neural-compute-module-2/Kconfig +source board/itead/sonoff-ihost/Kconfig endif diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 99ecbdc3412..0d9a0aef6f5 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -109,7 +109,14 @@ size_t rockchip_sdram_size(phys_addr_t reg) cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); cs1_col = cs0_col; - bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + if (dram_type == LPDDR5) + /* LPDDR5: 0:8bank(bk=3), 1:16bank(bk=4) */ + bk = 3 + ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & + SYS_REG_BK_MASK); + else + /* Other: 0:8bank(bk=3), 1:4bank(bk=2) */ + bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & + SYS_REG_BK_MASK); if (version >= 2) { cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) & SYS_REG_CS1_COL_MASK); diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index edff5b039e9..1b5339993f8 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -13,14 +13,6 @@ config SYS_VENDOR config SYS_SOC default "versal-net" -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_versal_net" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config COUNTER_FREQUENCY int "Timer clock frequency" default 0 diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 645f06add44..629a14129d5 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -13,14 +13,6 @@ config SYS_VENDOR config SYS_SOC default "versal" -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_versal" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config SYS_MALLOC_LEN default 0x2000000 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index b4c439b4cd6..265e9ce588a 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -43,14 +43,6 @@ config SYS_VENDOR config SYS_SOC default "zynq" -config SYS_CONFIG_NAME - string "Board configuration name" - default "zynq-common" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config SYS_MALLOC_F_LEN default 0x800 diff --git a/arch/arm/mach-zynqmp-r5/Kconfig b/arch/arm/mach-zynqmp-r5/Kconfig index f14514b3c7c..b2ba896e9b4 100644 --- a/arch/arm/mach-zynqmp-r5/Kconfig +++ b/arch/arm/mach-zynqmp-r5/Kconfig @@ -13,14 +13,6 @@ config SYS_VENDOR config SYS_SOC default "zynqmp-r5" -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_zynqmp_r5" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config CPU_FREQ_HZ int "CPU frequency" default 800000000 diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 7e7c87d16fa..6a7be0b4271 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -35,14 +35,6 @@ config SYS_VENDOR config SYS_SOC default "zynqmp" -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_zynqmp" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config SYS_MEM_RSVD_FOR_MMU bool "Reserve memory for MMU Table" help diff --git a/arch/mips/mach-mtmips/mt7620/Kconfig b/arch/mips/mach-mtmips/mt7620/Kconfig index 3ca711ad0f3..398c7c6a948 100644 --- a/arch/mips/mach-mtmips/mt7620/Kconfig +++ b/arch/mips/mach-mtmips/mt7620/Kconfig @@ -67,7 +67,6 @@ config CPU_FREQ_MULTI default 7 if CPU_FREQ_620MHZ config SYS_CONFIG_NAME - string "Board configuration name" default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB config SYS_BOARD diff --git a/arch/mips/mach-mtmips/mt7621/Kconfig b/arch/mips/mach-mtmips/mt7621/Kconfig index 008a28f991c..8fe6e0a2d9a 100644 --- a/arch/mips/mach-mtmips/mt7621/Kconfig +++ b/arch/mips/mach-mtmips/mt7621/Kconfig @@ -102,7 +102,6 @@ config BOARD_MT7621_NAND_RFB endchoice config SYS_CONFIG_NAME - string "Board configuration name" default "mt7621" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB config SYS_BOARD diff --git a/arch/mips/mach-mtmips/mt7628/Kconfig b/arch/mips/mach-mtmips/mt7628/Kconfig index e7273591bca..79b2ddc6692 100644 --- a/arch/mips/mach-mtmips/mt7628/Kconfig +++ b/arch/mips/mach-mtmips/mt7628/Kconfig @@ -49,7 +49,6 @@ config SYS_BOARD default "mt7628" if BOARD_MT7628_RFB config SYS_CONFIG_NAME - string "Board configuration name" default "mt7628" if BOARD_MT7628_RFB source "board/gardena/smart-gateway-mt7688/Kconfig" diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index bb4fb2ac3a5..b06b3efcf56 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -4,11 +4,4 @@ menu "Nios II architecture" config SYS_ARCH default "nios2" -config SYS_CONFIG_NAME - string "Board header file" - help - This option should contain the base name of board header file. - The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h - should be included from include/config.h. - endmenu diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 46b08552371..c7a4559eac8 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -96,7 +96,11 @@ extra_header_fields: .long _start - ImageBase /* SizeOfHeaders */ .long 0 /* CheckSum */ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ +#if CONFIG_VENDOR_EFI .short 0 /* DllCharacteristics */ +#else + .short IMAGE_DLLCHARACTERISTICS_NX_COMPAT +#endif #if __riscv_xlen == 32 .long 0 /* SizeOfStackReserve */ .long 0 /* SizeOfStackCommit */ diff --git a/board/Marvell/octeon_ebb7304/Kconfig b/board/Marvell/octeon_ebb7304/Kconfig index ab54e6dbbc3..b3244f751b1 100644 --- a/board/Marvell/octeon_ebb7304/Kconfig +++ b/board/Marvell/octeon_ebb7304/Kconfig @@ -9,7 +9,6 @@ config SYS_VENDOR default "Marvell" config SYS_CONFIG_NAME - string default "octeon_ebb7304" config DEFAULT_DEVICE_TREE diff --git a/board/Marvell/octeon_nic23/Kconfig b/board/Marvell/octeon_nic23/Kconfig index 3c42e8acdad..468bbb756e6 100644 --- a/board/Marvell/octeon_nic23/Kconfig +++ b/board/Marvell/octeon_nic23/Kconfig @@ -9,7 +9,6 @@ config SYS_VENDOR default "Marvell" config SYS_CONFIG_NAME - string default "octeon_nic23" config DEFAULT_DEVICE_TREE diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c index c8c1c78ae5a..c5b4ff7df47 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.c +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -28,3 +28,17 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + char fdtfile[50]; + + snprintf(fdtfile, sizeof(fdtfile), "%s/%s.dtb", + CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_DEVICE_TREE); + + env_set("fdtfile", fdtfile); + + return 0; +} +#endif diff --git a/board/beagle/beagleboneai64/beagleboneai64.env b/board/beagle/beagleboneai64/beagleboneai64.env index 4f0a94a8113..647b25d14c8 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.env +++ b/board/beagle/beagleboneai64/beagleboneai64.env @@ -1,5 +1,4 @@ #include <env/ti/ti_common.env> -#include <env/ti/default_findfdt.env> #include <env/ti/mmc.env> name_kern=Image diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 1c376dea372..20819ecf45b 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -27,3 +27,17 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + char fdtfile[50]; + + snprintf(fdtfile, sizeof(fdtfile), "%s/%s.dtb", + CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_DEVICE_TREE); + + env_set("fdtfile", fdtfile); + + return 0; +} +#endif diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env index 4f0a94a8113..647b25d14c8 100644 --- a/board/beagle/beagleplay/beagleplay.env +++ b/board/beagle/beagleplay/beagleplay.env @@ -1,5 +1,4 @@ #include <env/ti/ti_common.env> -#include <env/ti/default_findfdt.env> #include <env/ti/mmc.env> name_kern=Image diff --git a/board/cadence/xtfpga/Kconfig b/board/cadence/xtfpga/Kconfig index 69296be49c7..a64961e6d6a 100644 --- a/board/cadence/xtfpga/Kconfig +++ b/board/cadence/xtfpga/Kconfig @@ -25,7 +25,6 @@ config SYS_VENDOR default "cadence" config SYS_CONFIG_NAME - string default "xtfpga" config BOARD_SDRAM_SIZE diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig index 927d8765d67..3d4b260ea29 100644 --- a/board/cavium/thunderx/Kconfig +++ b/board/cavium/thunderx/Kconfig @@ -13,7 +13,6 @@ config SYS_VENDOR default "cavium" config SYS_CONFIG_NAME - string default "thunderx_88xx" config CMD_ATF diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 4f41ce1abf1..abbf08ac695 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -29,10 +29,3 @@ config SYS_CAR_SIZE This option specifies the board specific Cache-As-RAM (CAR) size. endif # CONFIG_VENDOR_COREBOOT - -if TARGET_COREBOOT - -config SYS_CONFIG_NAME - default "coreboot" - -endif diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index f7773658000..d97383c030c 100644 --- a/board/coreboot/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -2,7 +2,6 @@ COREBOOT BOARD M: Simon Glass <sjg@chromium.org> S: Maintained F: board/coreboot/ -F: include/configs/coreboot.h F: configs/coreboot_defconfig COREBOOT64 BOARD diff --git a/board/efi/efi-x86_app/Kconfig b/board/efi/efi-x86_app/Kconfig index ecd08d73146..f9cbef0a864 100644 --- a/board/efi/efi-x86_app/Kconfig +++ b/board/efi/efi-x86_app/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "efi" -config SYS_CONFIG_NAME - default "efi-x86_app" - config BOARD_SPECIFIC_OPTIONS # dummy def_bool y imply VIDEO_EFI diff --git a/board/efi/efi-x86_app/MAINTAINERS b/board/efi/efi-x86_app/MAINTAINERS index 584619c51df..693f367311b 100644 --- a/board/efi/efi-x86_app/MAINTAINERS +++ b/board/efi/efi-x86_app/MAINTAINERS @@ -3,7 +3,6 @@ M: Simon Glass <sjg@chromium.org> S: Maintained F: board/efi/Kconfig F: board/efi/efi-x86_app/ -F: include/configs/efi-x86_app.h F: configs/efi-x86_app32_defconfig EFI-X86_APP64 BOARD @@ -11,5 +10,4 @@ M: Simon Glass <sjg@chromium.org> S: Maintained F: board/efi/Kconfig F: board/efi/efi-x86_app/ -F: include/configs/efi-x86_app.h F: configs/efi-x86_app64_defconfig diff --git a/board/efi/efi-x86_payload/Kconfig b/board/efi/efi-x86_payload/Kconfig index 6d062499346..c500ca02ebf 100644 --- a/board/efi/efi-x86_payload/Kconfig +++ b/board/efi/efi-x86_payload/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "efi" -config SYS_CONFIG_NAME - default "efi-x86_payload" - config TEXT_BASE default 0x00200000 diff --git a/board/efi/efi-x86_payload/MAINTAINERS b/board/efi/efi-x86_payload/MAINTAINERS index d795d60e09e..3c5d48aa84c 100644 --- a/board/efi/efi-x86_payload/MAINTAINERS +++ b/board/efi/efi-x86_payload/MAINTAINERS @@ -3,6 +3,5 @@ M: Bin Meng <bmeng.cn@gmail.com> S: Maintained F: board/efi/Kconfig F: board/efi/efi-x86_payload/ -F: include/configs/efi-x86_payload.h F: configs/efi-x86_payload32_defconfig F: configs/efi-x86_payload64_defconfig diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig index 01dc1d497ae..9a0611820ce 100644 --- a/board/emulation/qemu-x86/Kconfig +++ b/board/emulation/qemu-x86/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "qemu" -config SYS_CONFIG_NAME - default "qemu-x86" - config TEXT_BASE default 0xfff00000 if !SUPPORT_SPL default 0x01110000 if SUPPORT_SPL diff --git a/board/emulation/qemu-x86/MAINTAINERS b/board/emulation/qemu-x86/MAINTAINERS index e62585a65d7..efb8b46daaf 100644 --- a/board/emulation/qemu-x86/MAINTAINERS +++ b/board/emulation/qemu-x86/MAINTAINERS @@ -3,7 +3,6 @@ M: Bin Meng <bmeng.cn@gmail.com> S: Maintained F: board/emulation/qemu-x86/ F: board/emulation/common/ -F: include/configs/qemu-x86.h F: configs/qemu-x86_defconfig QEMU X86 64-bit BOARD @@ -11,5 +10,4 @@ M: Bin Meng <bmeng.cn@gmail.com> S: Maintained F: board/emulation/qemu-x86/ F: board/emulation/common/ -F: include/configs/qemu-x86.h F: configs/qemu-x86_64_defconfig diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index be9c24fc0d9..a98ed69db88 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -14,6 +14,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/imx93_pins.h> +#include <asm/arch/mu.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> @@ -91,7 +92,6 @@ int power_init_board(void) } #endif -extern int imx9_probe_mu(void *ctx, struct event *event); void board_init_f(ulong dummy) { int ret; diff --git a/board/freescale/imxrt1020-evk/Kconfig b/board/freescale/imxrt1020-evk/Kconfig index d00cbff094b..3cb8fb1e6e9 100644 --- a/board/freescale/imxrt1020-evk/Kconfig +++ b/board/freescale/imxrt1020-evk/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "imxrt1020" config SYS_CONFIG_NAME - string default "imxrt1020-evk" config IMX_CONFIG diff --git a/board/freescale/imxrt1050-evk/Kconfig b/board/freescale/imxrt1050-evk/Kconfig index 79e6e4524ad..068130beca9 100644 --- a/board/freescale/imxrt1050-evk/Kconfig +++ b/board/freescale/imxrt1050-evk/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "imxrt1050" config SYS_CONFIG_NAME - string default "imxrt1050-evk" config IMX_CONFIG diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS b/board/freescale/imxrt1050-evk/MAINTAINERS index a8728554525..890825b39ae 100644 --- a/board/freescale/imxrt1050-evk/MAINTAINERS +++ b/board/freescale/imxrt1050-evk/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/imxrt1050-evk F: include/configs/imxrt1050-evk.h F: configs/imxrt1050-evk_defconfig +F: configs/imxrt1050-evk_fspi_defconfig diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg b/board/freescale/imxrt1050-evk/imximage-nor.cfg new file mode 100644 index 00000000000..829be6cbe2b --- /dev/null +++ b/board/freescale/imxrt1050-evk/imximage-nor.cfg @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 + * Author(s): Jesse Taube <Mr.Bossman075@gmail.com> + */ + +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM nor + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * 0x400AC044 is used to configure the flexram. + * Unfortunately setting all to OCRAM only works for MMC + * and setting all to DTCM only works for FLEXSPI NOR. + * This configuration fortunately works for both SPI and MMC. +*/ +/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */ +DATA 4 0x400AC044 0x55aaaaaa +/* Use FLEXRAM_BANK_CFG to config FlexRAM */ +SET_BIT 4 0x400AC040 0x4 diff --git a/board/freescale/imxrt1050-evk/imximage.cfg b/board/freescale/imxrt1050-evk/imximage.cfg index f1f09fd7ebb..b30d8521947 100644 --- a/board/freescale/imxrt1050-evk/imximage.cfg +++ b/board/freescale/imxrt1050-evk/imximage.cfg @@ -29,7 +29,13 @@ BOOT_FROM sd * value value to be stored in the register */ -/* Set all FlexRAM as OCRAM(01b) */ -DATA 4 0x400AC044 0x55555555 +/* + * 0x400AC044 is used to configure the flexram. + * Unfortunately setting all to OCRAM only works for MMC + * and setting all to DTCM only works for FLEXSPI NOR. + * This configuration fortunately works for both SPI and MMC. +*/ +/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */ +DATA 4 0x400AC044 0x55aaaaaa /* Use FLEXRAM_BANK_CFG to config FlexRAM */ SET_BIT 4 0x400AC040 0x4 diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c index 4b82ee5e9ce..4cc3defc882 100644 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c @@ -68,7 +68,12 @@ void spl_board_init(void) u32 spl_boot_device(void) { - return BOOT_DEVICE_MMC1; + /* There is no way to find the boot device so look if there is a valid IVT in RAM for MMC */ + u32 nor_ivt = *(u32 *)(CONFIG_SYS_LOAD_ADDR - 0xC00); + + if (nor_ivt == 0x402000d1) + return BOOT_DEVICE_MMC1; + return BOOT_DEVICE_NOR; } #endif diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig index c61fc579713..b433d6e5df0 100644 --- a/board/freescale/imxrt1170-evk/Kconfig +++ b/board/freescale/imxrt1170-evk/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "imxrt1170" config SYS_CONFIG_NAME - string default "imxrt1170-evk" config IMX_CONFIG diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index b558a596dff..bb066a5d36c 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -7,7 +7,6 @@ #include <image.h> #include <init.h> -#include <net.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> @@ -254,39 +253,6 @@ int board_mmc_init(struct bd_info *bis) } #endif -static int ar8031_phy_fixup(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - ar8031_phy_fixup(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - #if defined(CONFIG_VIDEO_IPUV3) static void disable_lvds(struct display_info_t const *dev) { diff --git a/board/ge/b1x5v2/MAINTAINERS b/board/ge/b1x5v2/MAINTAINERS index 3196ddbb51b..7312f4be1aa 100644 --- a/board/ge/b1x5v2/MAINTAINERS +++ b/board/ge/b1x5v2/MAINTAINERS @@ -1,6 +1,6 @@ GE B1X5V2 BOARD -M: Huan 'Kitty' Wang <HuanWang@ge.com> -M: Ian Ray <ian.ray@ge.com> +M: Huan 'Kitty' Wang <HuanWang@gehealthcare.com> +M: Ian Ray <ian.ray@gehealthcare.com> M: Martyn Welch <martyn.welch@collabora.com> S: Maintained F: arch/arm/dts/imx6dl-b1x5v2.dts diff --git a/board/ge/bx50v3/MAINTAINERS b/board/ge/bx50v3/MAINTAINERS index c1650483360..53a8d88a904 100644 --- a/board/ge/bx50v3/MAINTAINERS +++ b/board/ge/bx50v3/MAINTAINERS @@ -1,5 +1,5 @@ GE BX50V3 BOARD -M: Ian Ray <ian.ray@ge.com> +M: Ian Ray <ian.ray@gehealthcare.com> M: Martyn Welch <martyn.welch@collabora.com> S: Maintained F: arch/arm/dts/imx6q-b450v3.dts diff --git a/board/ge/mx53ppd/MAINTAINERS b/board/ge/mx53ppd/MAINTAINERS index 146a460e7e6..19e4ea75933 100644 --- a/board/ge/mx53ppd/MAINTAINERS +++ b/board/ge/mx53ppd/MAINTAINERS @@ -1,6 +1,5 @@ GE PPD BOARD -M: Antti Mäentausta <antti.maentausta@ge.com> -M: Ian Ray <ian.ray@ge.com> +M: Ian Ray <ian.ray@gehealthcare.com> M: Martyn Welch <martyn.welch@collabora.com> S: Maintained F: arch/arm/dts/imx53-ppd* diff --git a/board/hisilicon/poplar/MAINTAINERS b/board/hisilicon/poplar/MAINTAINERS index bfd4a9be66b..01efc96b0d3 100644 --- a/board/hisilicon/poplar/MAINTAINERS +++ b/board/hisilicon/poplar/MAINTAINERS @@ -1,6 +1,7 @@ Poplar BOARD M: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> M: Shawn Guo <shawn.guo@linaro.org> +M: Igor Opaniuk <igor.opaniuk@gmail.com> S: Maintained F: board/hisilicon/poplar F: doc/board/hisilicon/poplar.rst diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig index 97228d63087..af08566014d 100644 --- a/board/intel/bayleybay/Kconfig +++ b/board/intel/bayleybay/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "baytrail" -config SYS_CONFIG_NAME - default "bayleybay" - config TEXT_BASE default 0xfff00000 diff --git a/board/intel/bayleybay/MAINTAINERS b/board/intel/bayleybay/MAINTAINERS index 85fa51626af..5ab5d73f59e 100644 --- a/board/intel/bayleybay/MAINTAINERS +++ b/board/intel/bayleybay/MAINTAINERS @@ -2,5 +2,4 @@ Intel Bayley Bay M: Bin Meng <bmeng.cn@gmail.com> S: Maintained F: board/intel/bayleybay -F: include/configs/bayleybay.h F: configs/bayleybay_defconfig diff --git a/board/intel/cherryhill/Kconfig b/board/intel/cherryhill/Kconfig index 009cd93b6d4..28e4735e4d6 100644 --- a/board/intel/cherryhill/Kconfig +++ b/board/intel/cherryhill/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "braswell" -config SYS_CONFIG_NAME - default "cherryhill" - config TEXT_BASE default 0xffe00000 diff --git a/board/intel/cherryhill/MAINTAINERS b/board/intel/cherryhill/MAINTAINERS index 6e90f642125..7c1b311990c 100644 --- a/board/intel/cherryhill/MAINTAINERS +++ b/board/intel/cherryhill/MAINTAINERS @@ -2,5 +2,4 @@ INTEL CHERRYHILL BOARD M: Bin Meng <bmeng.cn@gmail.com> S: Maintained F: board/intel/cherryhill/ -F: include/configs/cherryhill.h F: configs/cherryhill_defconfig diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig index 32407025bc1..841e041167e 100644 --- a/board/intel/cougarcanyon2/Kconfig +++ b/board/intel/cougarcanyon2/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "ivybridge" -config SYS_CONFIG_NAME - default "cougarcanyon2" - config TEXT_BASE default 0xffe00000 diff --git a/board/intel/cougarcanyon2/MAINTAINERS b/board/intel/cougarcanyon2/MAINTAINERS index a486739b5ee..a4f465cf5df 100644 --- a/board/intel/cougarcanyon2/MAINTAINERS +++ b/board/intel/cougarcanyon2/MAINTAINERS @@ -2,5 +2,4 @@ INTEL COUGAR CANYON 2 BOARD M: Bin Meng <bmeng.cn@gmail.com> S: Maintained F: board/intel/cougarcanyon2/ -F: include/configs/cougarcanyon2.h F: configs/cougarcanyon2_defconfig diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig index eb2290cfafb..09614ab8d15 100644 --- a/board/intel/crownbay/Kconfig +++ b/board/intel/crownbay/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "queensbay" -config SYS_CONFIG_NAME - default "crownbay" - config TEXT_BASE default 0xfff00000 diff --git a/board/intel/crownbay/MAINTAINERS b/board/intel/crownbay/MAINTAINERS index 1eb68693df3..e2d8e6bc1d0 100644 --- a/board/intel/crownbay/MAINTAINERS +++ b/board/intel/crownbay/MAINTAINERS @@ -2,5 +2,4 @@ INTEL CROWNBAY BOARD M: Bin Meng <bmeng.cn@gmail.com> S: Maintained F: board/intel/crownbay/ -F: include/configs/crownbay.h F: configs/crownbay_defconfig diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig index 5efda4b3a55..daa8d2035cd 100644 --- a/board/intel/edison/Kconfig +++ b/board/intel/edison/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "tangier" -config SYS_CONFIG_NAME - default "edison" - config SYS_MALLOC_LEN default 0x08000000 diff --git a/board/intel/edison/MAINTAINERS b/board/intel/edison/MAINTAINERS index 4bc4a00c8ad..26b27c5dfe1 100644 --- a/board/intel/edison/MAINTAINERS +++ b/board/intel/edison/MAINTAINERS @@ -2,5 +2,4 @@ Intel Edison Board M: Andy Shevchenko <andriy.shevchenko@linux.intel.com> S: Maintained F: board/intel/edison -F: include/configs/edison.h F: configs/edison_defconfig diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig index 4c0451da48d..15c8d125408 100644 --- a/board/intel/galileo/Kconfig +++ b/board/intel/galileo/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "quark" -config SYS_CONFIG_NAME - default "galileo" - config TEXT_BASE default 0xfff10000 diff --git a/board/intel/galileo/MAINTAINERS b/board/intel/galileo/MAINTAINERS index dbbc82e8a1d..a5dcde7ad09 100644 --- a/board/intel/galileo/MAINTAINERS +++ b/board/intel/galileo/MAINTAINERS @@ -2,5 +2,4 @@ INTEL GALILEO BOARD M: Bin Meng <bmeng.cn@gmail.com> S: Maintained F: board/intel/galileo/ -F: include/configs/galileo.h F: configs/galileo_defconfig diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig index a03ef867801..abb1d45ff61 100644 --- a/board/intel/minnowmax/Kconfig +++ b/board/intel/minnowmax/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "baytrail" -config SYS_CONFIG_NAME - default "minnowmax" - config TEXT_BASE default 0xfff00000 diff --git a/board/intel/minnowmax/MAINTAINERS b/board/intel/minnowmax/MAINTAINERS index d655761d578..5cb94b0f36c 100644 --- a/board/intel/minnowmax/MAINTAINERS +++ b/board/intel/minnowmax/MAINTAINERS @@ -2,5 +2,4 @@ CircuitCo Minnowboard Max M: Simon Glass <sjg@chromium.org> S: Maintained F: board/intel/minnowmax -F: include/configs/minnowmax.h F: configs/minnowmax_defconfig diff --git a/board/intel/slimbootloader/Kconfig b/board/intel/slimbootloader/Kconfig index 015ed51dc89..11e6cb37bd8 100644 --- a/board/intel/slimbootloader/Kconfig +++ b/board/intel/slimbootloader/Kconfig @@ -13,9 +13,6 @@ config SYS_VENDOR config SYS_SOC default "slimbootloader" -config SYS_CONFIG_NAME - default "slimbootloader" - config TEXT_BASE default 0x00100000 diff --git a/board/intel/slimbootloader/MAINTAINERS b/board/intel/slimbootloader/MAINTAINERS index e6935517e01..0208a382ac6 100644 --- a/board/intel/slimbootloader/MAINTAINERS +++ b/board/intel/slimbootloader/MAINTAINERS @@ -2,5 +2,4 @@ Intel Slim Bootloader Payload M: Aiden Park <aiden.park@intel.com> S: Maintained F: board/intel/slimbootloader -F: include/configs/slimbootloader.h F: configs/slimbootloader_defconfig diff --git a/board/itead/sonoff-ihost/Kconfig b/board/itead/sonoff-ihost/Kconfig new file mode 100644 index 00000000000..30d9a6b3e6c --- /dev/null +++ b/board/itead/sonoff-ihost/Kconfig @@ -0,0 +1,16 @@ +if TARGET_RV1126_SONOFF_IHOST + +config SYS_BOARD + default "sonoff-ihost" + +config SYS_VENDOR + default "itead" + +config SYS_CONFIG_NAME + default "sonoff-ihost" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RAM_ROCKCHIP_DDR4 + +endif diff --git a/board/itead/sonoff-ihost/MAINTAINERS b/board/itead/sonoff-ihost/MAINTAINERS new file mode 100644 index 00000000000..eff9274bea8 --- /dev/null +++ b/board/itead/sonoff-ihost/MAINTAINERS @@ -0,0 +1,6 @@ +RV1126-SONOFF-IHOST +M: Tim Lunn <tim@feathertop.org> +S: Maintained +F: board/itead/sonoff-ihost +F: include/configs/sonoff-ihost.h +F: configs/sonoff-ihost-rv1126_defconfig diff --git a/board/kontron/sl-mx6ul/Kconfig b/board/kontron/sl-mx6ul/Kconfig index 4e58de20947..782e099cec2 100644 --- a/board/kontron/sl-mx6ul/Kconfig +++ b/board/kontron/sl-mx6ul/Kconfig @@ -9,7 +9,6 @@ config SYS_VENDOR default "kontron" config SYS_CONFIG_NAME - string default "kontron-sl-mx6ul" endif diff --git a/board/kontron/sl-mx8mm/Kconfig b/board/kontron/sl-mx8mm/Kconfig index 9dcf407c867..1cfe9ee64bd 100644 --- a/board/kontron/sl-mx8mm/Kconfig +++ b/board/kontron/sl-mx8mm/Kconfig @@ -9,7 +9,6 @@ config SYS_VENDOR default "kontron" config SYS_CONFIG_NAME - string default "kontron-sl-mx8mm" endif diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c index fed0fbcba1e..ed7a1b7d3d0 100644 --- a/board/msc/sm2s_imx8mp/spl.c +++ b/board/msc/sm2s_imx8mp/spl.c @@ -168,13 +168,6 @@ static const iomux_v3_cfg_t wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) - -static const iomux_v3_cfg_t ser0_pads[] = { - MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; @@ -182,8 +175,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads)); - return 0; } diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index a8f08214376..dbdd6bb7937 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -46,6 +46,10 @@ int board_late_init(void) case MMC3_BOOT: env_set_ulong("mmcdev", 2); break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + env_set_ulong("dofastboot", 1); + break; default: break; } diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig new file mode 100644 index 00000000000..a70104cb798 --- /dev/null +++ b/board/phytec/phycore_imx93/Kconfig @@ -0,0 +1,13 @@ + +if TARGET_PHYCORE_IMX93 + +config SYS_BOARD + default "phycore_imx93" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_imx93" + +endif diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS new file mode 100644 index 00000000000..9e91a29dc31 --- /dev/null +++ b/board/phytec/phycore_imx93/MAINTAINERS @@ -0,0 +1,10 @@ +phyCORE-i.MX93 +M: Mathieu Othacehe <m.othacehe@gmail.com> +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ +S: Maintained +F: arch/arm/dts/imx93-phyboard-segin.dts +F: arch/arm/dts/imx93-phycore-som.dtsi +F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +F: board/phytec/phycore_imx93/ +F: configs/imx93-phyboard-segin_defconfig +F: include/configs/phycore_imx93.h diff --git a/board/phytec/phycore_imx93/Makefile b/board/phytec/phycore_imx93/Makefile new file mode 100644 index 00000000000..ce35326a156 --- /dev/null +++ b/board/phytec/phycore_imx93/Makefile @@ -0,0 +1,14 @@ +# +# Copyright 2022 NXP +# Copyright (C) 2023 PHYTEC Messtechnik GmbH +# Christoph Stoidner <c.stoidner@phytec.de> +# Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += phycore-imx93.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o lpddr4_timing.o +endif diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx93/lpddr4_timing.c new file mode 100644 index 00000000000..2111972a40e --- /dev/null +++ b/board/phytec/phycore_imx93/lpddr4_timing.c @@ -0,0 +1,1546 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner <c.stoidner@phytec.de> + * + * Code generated with DDR Tool v1.0.0. + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x4080}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, + +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24A0421B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F263233}, + {0x4e30010C, 0x0005E18B}, + {0x4e300124, 0x1C770000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x00FE00FE}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2215}, + {0x4e300304, 0x00FE2213}, + {0x4e300308, 0x0A3C0E3C}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0xF2}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x2}, + {0x110a3, 0x3}, + {0x110a4, 0x4}, + {0x110a5, 0x5}, + {0x110a6, 0x6}, + {0x110a7, 0x7}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x2002e, 0x2}, + {0x90204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x20056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x200fa, 0x2}, + {0x20019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x1}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, + +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x2002e, 0x0}, + {0x90204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x20056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x200fa, 0x0}, + {0x20019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 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+ {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, + +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0xf2}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0xf2}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0xf236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0xf236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0xf2}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0xf2}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0xf236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0xf236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x75}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, + +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + + }, + + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, + +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c new file mode 100644 index 00000000000..085c8e195a6 --- /dev/null +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner <c.stoidner@phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + */ + +#include <asm/arch-imx9/ccm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-imx9/imx93_pins.h> +#include <asm/arch/clock.h> +#include <asm/global_data.h> +#include <asm/mach-imx/boot_mode.h> +#include <env.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + switch (get_boot_device()) { + case SD2_BOOT: + env_set_ulong("mmcdev", 1); + break; + case MMC1_BOOT: + env_set_ulong("mmcdev", 0); + break; + default: + break; + } + + return 0; +} diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx93/phycore_imx93.env new file mode 100644 index 00000000000..27bfadfa140 --- /dev/null +++ b/board/phytec/phycore_imx93/phycore_imx93.env @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +image=Image +console=ttyLP0 +fdt_addr=0x83000000 +fdto_addr=0x830c0000 +bootenv_addr=0x83500000 +fdt_file=CONFIG_DEFAULT_FDT_FILE +ip_dyn=yes +bootenv=bootenv.txt +mmc_load_bootenv=fatload mmc ${mmcdev}:${mmcpart} ${bootenv_addr} ${bootenv} +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcpart=1 +mmcroot=2 +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} earlycon + root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmc_load_overlay=fatload mmc ${mmcdev}:${mmcpart} ${fdto_addr} ${overlay} +mmc_apply_overlays= + fdt address ${fdt_addr}; + for overlay in ${overlays}; + do; + if run mmc_load_overlay; then + fdt resize ${filesize}; + fdt apply ${fdto_addr}; + fi; + done; +mmcboot= + echo Booting from mmc ...; + if run mmc_load_bootenv; then + env import -t ${bootenv_addr} ${filesize}; + fi; + run mmcargs; + if run loadfdt; then + run mmc_apply_overlays; + booti ${loadaddr} - ${fdt_addr}; + else + echo WARN: Cannot load the DT; + fi; +nfsroot=/nfs +netargs=setenv bootargs console=${console},${baudrate} earlycon + root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +net_load_bootenv=${get_cmd} ${bootenv_addr} ${bootenv} +net_load_overlay=${get_cmd} ${fdto_addr} ${overlay} +net_apply_overlays= + fdt address ${fdt_addr}; + for overlay in ${overlays}; + do; + if run net_load_overlay; then + fdt resize ${filesize}; + fdt apply ${fdto_addr}; + fi; + done; +netboot= + echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if run net_load_bootenv; then + env import -t ${bootenv_addr} ${filesize}; + fi; + ${get_cmd} ${loadaddr} ${image}; + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + run net_apply_overlays; + booti ${loadaddr} - ${fdt_addr}; + else + echo WARN: Cannot load the DT; + fi; diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c new file mode 100644 index 00000000000..dabc5316f33 --- /dev/null +++ b/board/phytec/phycore_imx93/spl.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner <c.stoidner@phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + */ + +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/trdc.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/sections.h> +#include <hang.h> +#include <init.h> +#include <log.h> +#include <power/pmic.h> +#include <power/pca9450.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Will be part of drivers/power/regulator/pca9450.c + * when pca9451a support is added. + */ +#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5) + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + val = ret; + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) { + /* 0.8v for Low drive mode */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x10); + } + } else { + /* 0.9v for Over drive mode */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x14); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + } + } + + /* set standby voltage to 0.65v */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(NULL, NULL); + if (ret) { + printf("Fail to init ELE API\n"); + } else { + printf("SOC: 0x%x\n", gd->arch.soc_rev); + printf("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init(); + + power_init_board(); + + if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + set_arm_core_max_clk(); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index cd823ad7465..2851ebc9853 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -171,6 +171,11 @@ static const struct rpi_model rpi_models_new_scheme[] = { DTB_DIR "bcm2711-rpi-cm4.dtb", true, }, + [0x17] = { + "5 Model B", + DTB_DIR "bcm2712-rpi-5-b.dtb", + true, + }, }; static const struct rpi_model rpi_models_old_scheme[] = { @@ -429,15 +434,27 @@ static void get_board_revision(void) int ret; const struct rpi_model *models; uint32_t models_count; + ofnode node; BCM2835_MBOX_INIT_HDR(msg); BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV); ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); if (ret) { - printf("bcm2835: Could not query board revision\n"); /* Ignore error; not critical */ - return; + node = ofnode_path("/system"); + if (!ofnode_valid(node)) { + printf("bcm2835: Could not find /system node\n"); + return; + } + + ret = ofnode_read_u32(node, "linux,revision", &revision); + if (ret) { + printf("bcm2835: Could not find linux,revision\n"); + return; + } + } else { + revision = msg->get_board_rev.body.resp.rev; } /* @@ -451,7 +468,6 @@ static void get_board_revision(void) * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250 * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594 */ - revision = msg->get_board_rev.body.resp.rev; if (revision & 0x800000) { rev_scheme = 1; rev_type = (revision >> 4) & 0xff; diff --git a/board/renesas/grayhawk/Kconfig b/board/renesas/grayhawk/Kconfig new file mode 100644 index 00000000000..97621a30ad0 --- /dev/null +++ b/board/renesas/grayhawk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GRAYHAWK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "grayhawk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "grayhawk" + +endif diff --git a/board/renesas/grayhawk/MAINTAINERS b/board/renesas/grayhawk/MAINTAINERS new file mode 100644 index 00000000000..1d5de580a7c --- /dev/null +++ b/board/renesas/grayhawk/MAINTAINERS @@ -0,0 +1,5 @@ +GRAYHAWK BOARD +M: Marek Vasut <marek.vasut+renesas@mailbox.org> +S: Maintained +N: grayhawk +N: r8a779h0 diff --git a/board/renesas/grayhawk/Makefile b/board/renesas/grayhawk/Makefile new file mode 100644 index 00000000000..9c5b8c9a12f --- /dev/null +++ b/board/renesas/grayhawk/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/grayhawk/Makefile +# +# Copyright (C) 2023 Renesas Electronics Corp. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := grayhawk.o ../rcar-common/common.o diff --git a/board/renesas/grayhawk/grayhawk.c b/board/renesas/grayhawk/grayhawk.c new file mode 100644 index 00000000000..6f2e73f7d38 --- /dev/null +++ b/board/renesas/grayhawk/grayhawk.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board/renesas/grayhawk/grayhawk.c + * This file is Gray Hawk board support. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <asm/arch/rmobile.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/processor.h> +#include <linux/errno.h> +#include <asm/system.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void init_generic_timer(void) +{ + const u32 freq = CONFIG_SYS_CLK_FREQ; + + /* Update memory mapped and register based freqency */ + asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); + writel(freq, CNTFID0); + + /* Enable counter */ + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + +static void init_gic_v3(void) +{ + /* GIC v3 power on */ + writel(BIT(1), GICR_LPI_PWRR); + + /* Wait till the WAKER_CA_BIT changes to 0 */ + clrbits_le32(GICR_LPI_WAKER, BIT(1)); + while (readl(GICR_LPI_WAKER) & BIT(2)) + ; + + writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); +} + +void s_init(void) +{ + if (current_el() == 3) + init_generic_timer(); +} + +int board_early_init_f(void) +{ + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + + return 0; +} + +int board_init(void) +{ + if (current_el() == 3) + init_gic_v3(); + + return 0; +} diff --git a/board/samsung/e850-96/Kconfig b/board/samsung/e850-96/Kconfig new file mode 100644 index 00000000000..f891a906959 --- /dev/null +++ b/board/samsung/e850-96/Kconfig @@ -0,0 +1,16 @@ +if TARGET_E850_96 + +config EXYNOS850 + bool "Exynos850 SoC support" + default y + +config SYS_BOARD + default "e850-96" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "e850-96" + +endif diff --git a/board/samsung/e850-96/MAINTAINERS b/board/samsung/e850-96/MAINTAINERS new file mode 100644 index 00000000000..e8b9365eea8 --- /dev/null +++ b/board/samsung/e850-96/MAINTAINERS @@ -0,0 +1,9 @@ +WINLINK E850-96 BOARD +M: Sam Protsenko <semen.protsenko@linaro.org> +S: Maintained +F: arch/arm/dts/exynos850-e850-96-u-boot.dtsi +F: arch/arm/dts/exynos850-e850-96.dts +F: board/samsung/e850-96/ +F: configs/e850-96_defconfig +F: doc/board/samsung/e850-96.rst +F: include/configs/e850-96.h diff --git a/board/samsung/e850-96/Makefile b/board/samsung/e850-96/Makefile new file mode 100644 index 00000000000..301c2233711 --- /dev/null +++ b/board/samsung/e850-96/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020, Linaro Limited +# Sam Protsenko <semen.protsenko@linaro.org> + +obj-y := e850-96.o diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c new file mode 100644 index 00000000000..a00d81b5d4c --- /dev/null +++ b/board/samsung/e850-96/e850-96.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Linaro Limited + * Sam Protsenko <semen.protsenko@linaro.org> + */ + +#include <init.h> + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int board_init(void) +{ + return 0; +} diff --git a/board/samsung/starqltechn/Kconfig b/board/samsung/starqltechn/Kconfig index 0eea666d035..e928cb0ea89 100644 --- a/board/samsung/starqltechn/Kconfig +++ b/board/samsung/starqltechn/Kconfig @@ -6,17 +6,9 @@ config SYS_BOARD starqltechn is a production board for S9 and S9+ phones(SM-G96x0) phones based on SDM845 SoC. config SYS_CONFIG_NAME - string "Board configuration name" default "sdm845" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. config SYS_VENDOR default "samsung" -config SYS_CONFIG_NAME - default "starqltechn" - endif diff --git a/board/sielaff/imx6dl-sielaff/Kconfig b/board/sielaff/imx6dl-sielaff/Kconfig new file mode 100644 index 00000000000..7876ab14c07 --- /dev/null +++ b/board/sielaff/imx6dl-sielaff/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MX6S_SIELAFF + +config SYS_BOARD + string + default "imx6dl-sielaff" + +config SYS_VENDOR + string + default "sielaff" + +config SYS_CONFIG_NAME + default "imx6dl-sielaff" + +endif diff --git a/board/sielaff/imx6dl-sielaff/MAINTAINERS b/board/sielaff/imx6dl-sielaff/MAINTAINERS new file mode 100644 index 00000000000..c0d3a09c95f --- /dev/null +++ b/board/sielaff/imx6dl-sielaff/MAINTAINERS @@ -0,0 +1,9 @@ +Sielaff i.MX6 Solo Board +M: Frieder Schrempf <frieder.schrempf@kontron.de> +S: Maintained +F: arch/arm/dts/imx6dl-sielaff* +F: board/sielaff/imx6dl-sielaff/ +F: configs/imx6dl_sielaff_defconfig +F: doc/board/sielaff/imx6dl-sielaff.rst +F: include/configs/imx6dl-sielaff.h +F: include/configs/kontron-sl-mx6ul.h diff --git a/board/sielaff/imx6dl-sielaff/Makefile b/board/sielaff/imx6dl-sielaff/Makefile new file mode 100644 index 00000000000..65cecfe6f6c --- /dev/null +++ b/board/sielaff/imx6dl-sielaff/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2022 Kontron Electronics GmbH + +ifdef CONFIG_SPL_BUILD +obj-y := spl.o +else +obj-y := imx6dl-sielaff.o +endif diff --git a/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c new file mode 100644 index 00000000000..4da084ed91c --- /dev/null +++ b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +#include <compiler.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/io.h> +#include <init.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + return 0; +} + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable ENFC_CLK_ROOT clock */ + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +int board_init(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + setup_gpmi_nand(); + + /* Enable SPI2 clock */ + enable_spi_clk(true, 1); + + /* + * Configure clock output for USB hub + * 1. Disabling CLK01 and CLK02 + */ + clrbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKOL_EN); + clrbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKO2_EN_OFFSET); + + /* + * 2. Setting ccm timer - osc_clk (24 MHz) divide by 2 -> 12 Mhz + * CLK02_DIV: 001b CLK02_SEL: 01110b -> 0010 1110b -> 0x2e + */ + reg = readl(&mxc_ccm->ccosr); + reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK; + reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK; + reg |= (0x2e << MXC_CCM_CCOSR_CKO2_SEL_OFFSET); + writel(reg, &mxc_ccm->ccosr); + + /* 3. Enabling CLK02 on output CCM_CLK01 */ + setbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CLK_OUT_SEL); + setbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKO2_EN_OFFSET); + + return 0; +} diff --git a/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env new file mode 100644 index 00000000000..9aafa3c9984 --- /dev/null +++ b/board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env @@ -0,0 +1,114 @@ +blkloadfdt=fatload ${device} ${devnum}:${partnum} ${fdt_addr} ${load_fdt_file} +blkloadimage=fatload ${device} ${devnum}:${partnum} ${loadaddr} ${load_image} +boot_devices=usb mmc ubi +bootargs_base=vt.global_cursor_default=0 consoleblank=0 cma=200M fbcon=rotate:1 +bootdelay=3 +bootdir= +console=ttymxc1,115200 +ethact=FEC0 +fdt_addr=0x18000000 +fdt_file_legacy=imx6dl_sielaff.dtb +fdt_file=imx6dl-sielaff.dtb +fdt_high=0xffffffff +image_legacy=zImage +image=fitImage +initrd_high=0xffffffff +ip_dyn=no +loadaddr=0x12000000 +mmcargs=setenv bootargs ${bootargs_base} console=${console} root=${mmcroot} +mmcroot=/dev/mmcblk2p2 rootwait rw +ramdisk_addr=0x18C00000 +script=boot.scr +touch_rst_gpio=2 +touch_irq_gpio=146 +ubiargs=setenv bootargs ${bootargs_base} console=${console} rootfstype=ubifs ubi.mtd=0 root=ubi0_0 rw +ubiloadfdt=ubifsload ${fdt_addr} /boot/${load_fdt_file} +ubiloadimage=ubifsload ${loadaddr} /boot/${load_image} +usb_pgood_delay=2000 +usbargs=setenv bootargs ${bootargs_base} console=${console} root=${usbroot} +usbroot=/dev/sda2 rootwait rw + +bootcmd= + for b in ${boot_devices}; do + if test ${b} = mmc; then + run mmcboot; + fi; + if test ${b} = net; then + run netboot; + fi; + if test ${b} = ubi; then + run ubiboot; + fi; + if test ${b} = usb; then + run usbboot; + fi; + done; + +boot= + load_image=${image}; + run loadimagecmd; + if test $? = 0; then + imxtract ${loadaddr} fdt-${fdt_file} ${fdt_addr}; + run detect_touch; + bootm ${loadaddr} - ${fdt_addr}; + else + load_image=${image_legacy}; + load_fdt_file=${fdt_file_legacy}; + run loadimagecmd; + run loadfdtcmd; + if test $? = 0; then + run detect_touch; + bootz ${loadaddr} - ${fdt_addr}; + fi; + fi; + +detect_touch= + gpio clear ${touch_irq_gpio}; + gpio clear ${touch_rst_gpio}; + sleep 0.02; + gpio set ${touch_rst_gpio}; + sleep 0.1; + gpio input ${touch_irq_gpio}; + i2c dev 2; + fdt addr ${fdt_addr}; + if i2c probe 0x55; then + echo 'Detected Sitronix Touch'; + fdt set /soc/bus@2100000/i2c@21a8000/touchscreen@55 status okay; + else + if i2c probe 0x5d; then + echo 'Detected Goodix Touch'; + fdt set /soc/bus@2100000/i2c@21a8000/touchscreen@5d status okay; + fi; + fi; + gpio clear ${touch_rst_gpio}; + +mmcboot= + echo Booting from MMC ...; + run mmcargs; + device=mmc; + devnum=2; + partnum=1; + setenv loadimagecmd ${blkloadimage}; + setenv loadfdtcmd ${blkloadfdt}; + run boot; + +ubiboot= + echo Booting from NAND (UBI); + run ubiargs; + ubi part rootfs; + ubifsmount ubi0; + setenv loadimagecmd ${ubiloadimage}; + setenv loadfdtcmd ${ubiloadfdt}; + load_image=${image}; + run boot; + +usbboot= + echo Booting from USB Storage ...; + run usbargs; + usb start; + device=usb; + devnum=0; + partnum=1; + setenv loadimagecmd ${blkloadimage}; + setenv loadfdtcmd ${blkloadfdt}; + run boot; diff --git a/board/sielaff/imx6dl-sielaff/spl.c b/board/sielaff/imx6dl-sielaff/spl.c new file mode 100644 index 00000000000..6815952c0fb --- /dev/null +++ b/board/sielaff/imx6dl-sielaff/spl.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +#include <asm/arch/clock.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/sections.h> +#include <init.h> +#include <spl.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static const iomux_v3_cfg_t ecspi2_pads[] = { + MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static const iomux_v3_cfg_t uart2_pads[] = { + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static const iomux_v3_cfg_t usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 4) +#define SPI2_CS_GPIO IMX_GPIO_NR(5, 29) + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", + i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + return 0; +} + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static int mx6ssielaff_dcd_table[] = { + 0x020e0774, 0x000C0000, + 0x020e0754, 0x00000000, + 0x020e04ac, 0x00000030, + 0x020e04b0, 0x00000030, + 0x020e0464, 0x00000030, + 0x020e0490, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e0494, 0x00000030, + 0x020e04a0, 0x00000000, + 0x020e04b4, 0x00000030, + 0x020e04b8, 0x00000030, + 0x020e076c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e04bc, 0x00000030, + 0x020e04c0, 0x00000030, + 0x020e04c4, 0x00000030, + 0x020e04c8, 0x00000030, + 0x020e0760, 0x00020000, + 0x020e0764, 0x00000030, + 0x020e0770, 0x00000030, + 0x020e0778, 0x00000030, + 0x020e077c, 0x00000030, + 0x020e0470, 0x00000030, + 0x020e0474, 0x00000030, + 0x020e0478, 0x00000030, + 0x020e047c, 0x00000030, + 0x021b001c, 0x00008000, + 0x021b0800, 0xA1390003, + 0x021b080c, 0x00350035, + 0x021b0810, 0x002A0032, + 0x021b083c, 0x02340234, + 0x021b0840, 0x02200220, + 0x021b0848, 0x4650504E, + 0x021b0850, 0x3A342E34, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b0004, 0x0002002D, + 0x021b0008, 0x00333040, + 0x021b000c, 0x676B52F3, + 0x021b0010, 0xB66D8B63, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00011740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026D2, + 0x021b0030, 0x006B1023, + 0x021b0040, 0x00000027, + 0x021b0000, 0x84190000, + 0x021b001c, 0x02008032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x15208030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00007800, + 0x021b0818, 0x00022227, + 0x021b0004, 0x0002556D, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, + 0x020c4068, 0x00C03F3F, + 0x020c406c, 0x0030FC03, + 0x020c4070, 0x0FFFC000, + 0x020c4074, 0x3FF00000, + 0x020c4078, 0xFFFFF300, + 0x020c407c, 0x0F0000C3, + 0x020c4080, 0x000003FF, + 0x020e0010, 0xF00000CF, + 0x020e0018, 0x007F007F, + 0x020e001c, 0x007F007F, +}; + +static void ddr_init(int *table, int size) +{ + int i; + + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + ddr_init(mx6ssielaff_dcd_table, ARRAY_SIZE(mx6ssielaff_dcd_table)); +} + +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) +{ + return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) + ? SPI2_CS_GPIO : -1; +} + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + gpio_request(SPI2_CS_GPIO, "spi2_cs0"); + gpio_direction_output(SPI2_CS_GPIO, 1); + enable_spi_clk(true, 1); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* IOMUX UART */ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* SPI */ + setup_spi(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ + u32 bootdev = spl_boot_device(); + + /* + * The default boot fuse settings use the SD card (MMC1) as primary + * boot device, but allow SPI NOR as a fallback boot device. + * We can't detect the fallback case and spl_boot_device() will return + * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR. + * Therefore we try to load U-Boot proper vom SPI NOR after loading + * from MMC has failed. + */ + spl_boot_list[0] = bootdev; + + switch (bootdev) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + spl_boot_list[1] = BOOT_DEVICE_SPI; + break; + } +} diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile index d5846cc8e3c..4dafac10829 100644 --- a/board/siemens/capricorn/Makefile +++ b/board/siemens/capricorn/Makefile @@ -4,6 +4,7 @@ # obj-y += board.o +obj-y += ../common/eeprom.o ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 924c88e8fab..0d66a75bbfa 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -22,12 +22,12 @@ #include <asm/gpio.h> #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> -#include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> #ifndef CONFIG_SPL #include <asm/arch-imx8/clock.h> #endif #include <linux/delay.h> +#include "../common/eeprom.h" #include "../common/factoryset.h" #define GPIO_PAD_CTRL \ @@ -337,13 +337,11 @@ void board_late_mmc_env_init(void) } #ifndef CONFIG_SPL_BUILD -int factoryset_read_eeprom(int i2c_addr); - static int load_parameters_from_factoryset(void) { int ret; - ret = factoryset_read_eeprom(EEPROM_I2C_ADDR); + ret = factoryset_read_eeprom(SIEMENS_EE_I2C_ADDR); if (ret) return ret; diff --git a/board/siemens/common/board.c b/board/siemens/common/board_am335x.c index d077751cbe1..445af9ddbf6 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board_am335x.c @@ -9,35 +9,20 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> #include <command.h> -#include <env.h> -#include <errno.h> -#include <init.h> -#include <malloc.h> #include <serial.h> -#include <spl.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/ddr_defs.h> +#include <watchdog.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/emif.h> #include <asm/gpio.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include <watchdog.h> #include <asm/mach-types.h> -#include "../common/factoryset.h" +#include "board_am335x.h" +#include "eeprom.h" +#include "factoryset.h" DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_SPL_BUILD void set_uart_mux_conf(void) { @@ -48,13 +33,14 @@ void set_mux_conf_regs(void) { /* Initalize the board header */ enable_i2c0_pin_mux(); - i2c_set_bus_num(0); /* enable early the console */ gd->baudrate = CONFIG_BAUDRATE; serial_init(); gd->have_console = 1; - if (read_eeprom() < 0) + + siemens_ee_setup(); + if (draco_read_eeprom() < 0) puts("Could not get board ID.\n"); enable_board_pin_mux(); @@ -62,15 +48,14 @@ void set_mux_conf_regs(void) void sdram_init(void) { - spl_siemens_board_init(); - board_init_ddr(); + spl_draco_board_init(); + draco_init_ddr(); return; } #endif /* #ifdef CONFIG_SPL_BUILD */ #ifndef CONFIG_SPL_BUILD -#define FACTORYSET_EEPROM_ADDR 0x50 /* * Basic board specific setup. Pinmux has been handled already. */ @@ -79,8 +64,7 @@ int board_init(void) #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif /* defined(CONFIG_HW_WATCHDOG) */ - i2c_set_bus_num(0); - if (read_eeprom() < 0) + if (siemens_ee_setup() < 0) puts("Could not get board ID.\n"); #ifdef CONFIG_MACH_TYPE gd->bd->bi_arch_number = CONFIG_MACH_TYPE; @@ -88,15 +72,11 @@ int board_init(void) gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FACTORYSET - factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR); + factoryset_read_eeprom(SIEMENS_EE_I2C_ADDR); #endif gpmc_init(); -#if CONFIG_IS_ENABLED(NAND_CS_INIT) - board_nand_cs_init(); -#endif - return 0; } #endif /* #ifndef CONFIG_SPL_BUILD */ diff --git a/board/siemens/common/board_am335x.h b/board/siemens/common/board_am335x.h new file mode 100644 index 00000000000..3a20352d457 --- /dev/null +++ b/board/siemens/common/board_am335x.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board definitions for draco products + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_AM335X_H_ +#define _BOARD_AM335X_H_ + +#include "eeprom.h" + +/* Common functions with product specific implementation */ +void spl_draco_board_init(void); +void draco_init_ddr(void); +int draco_read_eeprom(void); + +#ifdef CONFIG_SPL_BUILD +/* Mux for init: uart?, i2c0 to read the main EEPROM */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); + +/* Main mux function to enable other pinmux required on the board */ +void enable_board_pin_mux(void); +#endif /* CONFIG_SPL_BUILD */ + +#endif /* _BOARD_AM335X_H_ */ diff --git a/board/siemens/common/eeprom.c b/board/siemens/common/eeprom.c new file mode 100644 index 00000000000..fc93df91d52 --- /dev/null +++ b/board/siemens/common/eeprom.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Read EEPROM data + * (C) Copyright 2024 Siemens AG + */ + +#include <dm/uclass.h> +#include <i2c.h> +#include "eeprom.h" + +#if CONFIG_IS_ENABLED(DM_I2C) +static struct udevice *i2c_dev; +#endif + +/* Probe I2C and set-up EEPROM */ +int siemens_ee_setup(void) +{ +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *bus; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, SIEMENS_EE_I2C_BUS, &bus); + if (ret) + goto err; + + ret = dm_i2c_probe(bus, SIEMENS_EE_I2C_ADDR, 0, &i2c_dev); + if (ret) + goto err; + if (i2c_set_chip_offset_len(i2c_dev, 2)) + goto err; +#else + i2c_set_bus_num(SIEMENS_EE_I2C_BUS); + if (i2c_probe(SIEMENS_EE_I2C_ADDR)) + goto err; +#endif + return 0; + +err: + printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; +} + +/* Read data from EEPROM */ +int siemens_ee_read_data(uint address, uchar *buffer, int len) +{ +#if CONFIG_IS_ENABLED(DM_I2C) + return dm_i2c_read(i2c_dev, address, buffer, len); +#else + return i2c_read(SIEMENS_EE_I2C_ADDR, address, 2, buffer, len); +#endif +} diff --git a/board/siemens/common/eeprom.h b/board/siemens/common/eeprom.h new file mode 100644 index 00000000000..a5ef5abbafd --- /dev/null +++ b/board/siemens/common/eeprom.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright Siemens AG 2023 + * + * Common board definitions for siemens boards + */ + +#ifndef _COMMON_EEPROM_H_ +#define _COMMON_EEPROM_H_ + +/* EEPROM @ I2C */ +#define SIEMENS_EE_I2C_BUS 0 +#define SIEMENS_EE_I2C_ADDR 0x50 + +/* EEPROM mapping */ +#define SIEMENS_EE_ADDR_NAND_GEO 0x80 +#define SIEMENS_EE_ADDR_DDR3 0x90 +#define SIEMENS_EE_ADDR_CHIP 0x120 +#define SIEMENS_EE_ADDR_FACTORYSET 0x400 + +int siemens_ee_setup(void); +int siemens_ee_read_data(uint address, uchar *buffer, int len); + +#endif /* _COMMON_EEPROM_H_ */ diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c index 4e36a6f3199..a250ccfe252 100644 --- a/board/siemens/common/factoryset.c +++ b/board/siemens/common/factoryset.c @@ -7,26 +7,18 @@ #if !defined(CONFIG_SPL_BUILD) -#include <common.h> #include <env.h> -#include <dm.h> -#include <env_internal.h> -#include <i2c.h> -#include <log.h> +#include <g_dnl.h> +#include <net.h> #include <asm/io.h> -#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB) +#if CONFIG_IS_ENABLED(AM33XX) #include <asm/arch/cpu.h> #endif -#include <asm/arch/sys_proto.h> -#include <asm/unaligned.h> -#include <net.h> -#include <errno.h> -#include <g_dnl.h> +#include "eeprom.h" #include "factoryset.h" -#define EEPR_PG_SZ 0x80 -#define EEPROM_FATORYSET_OFFSET 0x400 -#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ +#define EEPR_PG_SZ 0x80 +#define OFF_PG (SIEMENS_EE_ADDR_FACTORYSET / EEPR_PG_SZ) /* Global variable that contains necessary information from FactorySet */ struct factorysetcontainer factory_dat; @@ -148,39 +140,14 @@ int factoryset_read_eeprom(int i2c_addr) int i, pages = 0, size = 0; unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH]; unsigned char *cp, *cp1; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *bus, *dev; - int ret; -#endif #if defined(CONFIG_DFU_OVER_USB) factory_dat.usb_vendor_id = CONFIG_USB_GADGET_VENDOR_NUM; factory_dat.usb_product_id = CONFIG_USB_GADGET_PRODUCT_NUM; #endif -#if CONFIG_IS_ENABLED(DM_I2C) - ret = uclass_get_device_by_seq(UCLASS_I2C, EEPROM_I2C_BUS, &bus); - if (ret) - goto err; - - ret = dm_i2c_probe(bus, i2c_addr, 0, &dev); - if (ret) - goto err; - - ret = i2c_set_chip_offset_len(dev, 2); - if (ret) - goto err; - - ret = dm_i2c_read(dev, EEPROM_FATORYSET_OFFSET, hdr, sizeof(hdr)); - if (ret) - goto err; -#else - if (i2c_probe(i2c_addr)) - goto err; - - if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr))) + if (siemens_ee_read_data(SIEMENS_EE_ADDR_FACTORYSET, hdr, sizeof(hdr))) goto err; -#endif if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) { printf("FactorySet is not right in eeprom.\n"); @@ -201,33 +168,16 @@ int factoryset_read_eeprom(int i2c_addr) * data after every time we got a record from eeprom */ debug("Read eeprom page :\n"); - for (i = 0; i < pages; i++) { -#if CONFIG_IS_ENABLED(DM_I2C) - ret = dm_i2c_read(dev, (OFF_PG + i) * EEPR_PG_SZ, - eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ); - if (ret) - goto err; -#else - if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2, - eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ)) + for (i = 0; i < pages; i++) + if (siemens_ee_read_data((OFF_PG + i) * EEPR_PG_SZ, + eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ)) goto err; -#endif - } - if (size % EEPR_PG_SZ) { -#if CONFIG_IS_ENABLED(DM_I2C) - ret = dm_i2c_read(dev, (OFF_PG + pages) * EEPR_PG_SZ, - eeprom_buf + (pages * EEPR_PG_SZ), - size % EEPR_PG_SZ); - if (ret) - goto err; -#else - if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2, - eeprom_buf + (pages * EEPR_PG_SZ), - (size % EEPR_PG_SZ))) + if (size % EEPR_PG_SZ) + if (siemens_ee_read_data((OFF_PG + pages) * EEPR_PG_SZ, + eeprom_buf + (pages * EEPR_PG_SZ), + size % EEPR_PG_SZ)) goto err; -#endif - } /* we do below just for eeprom align */ for (i = 0; i < size; i++) @@ -247,11 +197,10 @@ int factoryset_read_eeprom(int i2c_addr) cp1 += 3; } -#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB) +#if CONFIG_IS_ENABLED(IMX8) /* get mac address for WLAN */ - ret = get_factory_record_val(cp, size, (uchar *)"WLAN1", (uchar *)"mac", - buf, MAX_STRING_LENGTH); - if (ret > 0) { + if (get_factory_record_val(cp, size, (uchar *)"WLAN1", (uchar *)"mac", + buf, MAX_STRING_LENGTH) > 0) { cp1 = buf; for (i = 0; i < 6; i++) { factory_dat.mac_wlan[i] = hextoul((char *)cp1, NULL); @@ -355,7 +304,7 @@ static int factoryset_mac_env_set(void) eth_env_set_enetaddr("ethaddr", mac_addr); -#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB) +#if CONFIG_IS_ENABLED(IMX8) eth_env_set_enetaddr("eth1addr", mac_addr); /* wlan mac */ diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h index 8fa6c3b3d3b..ee8bcd0f20d 100644 --- a/board/siemens/common/factoryset.h +++ b/board/siemens/common/factoryset.h @@ -11,7 +11,7 @@ struct factorysetcontainer { uchar mac[6]; -#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB) +#if CONFIG_IS_ENABLED(IMX8) uchar mac_wlan[6]; #endif int usb_vendor_id; diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index 0cdf5bc9812..9d45c4239be 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -44,6 +44,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "draco-etamin" -config NAND_CS_INIT - def_bool y endif diff --git a/board/siemens/draco/Makefile b/board/siemens/draco/Makefile index e94456ab1c3..aae536472c5 100644 --- a/board/siemens/draco/Makefile +++ b/board/siemens/draco/Makefile @@ -14,6 +14,8 @@ obj-y := mux.o endif obj-y += board.o +obj-y += ../common/board_am335x.o +obj-y += ../common/eeprom.o ifndef CONFIG_SPL_BUILD obj-y += ../common/factoryset.o endif diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index 8b13d23aca7..fc3eb06ccf2 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -12,33 +12,21 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> #include <command.h> +#include <cpsw.h> #include <env.h> -#include <errno.h> #include <init.h> -#include <net.h> -#include <spl.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/ddr_defs.h> +#include <linux/delay.h> +#include <nand.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> +#include <asm/arch/ddr_defs.h> #include <asm/arch/mem.h> -#include <asm/io.h> -#include <asm/emif.h> +#include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include <watchdog.h> -#include <linux/delay.h> +#include <asm/io.h> #include "board.h" +#include "../common/eeprom.h" #include "../common/factoryset.h" -#include <nand.h> #ifdef CONFIG_SPL_BUILD static struct draco_baseboard_id __section(".data") settings; @@ -132,17 +120,13 @@ struct am335x_nand_geometry { u8 nand_bus; }; -#define EEPROM_ADDR 0x50 -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - static int draco_read_nand_geometry(void) { struct am335x_nand_geometry geo; /* Read NAND geometry */ - if (i2c_read(EEPROM_ADDR, 0x80, 2, - (uchar *)&geo, sizeof(struct am335x_nand_geometry))) { + if (siemens_ee_read_data(SIEMENS_EE_ADDR_NAND_GEO, (uchar *)&geo, + sizeof(struct am335x_nand_geometry))) { printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n"); return -EIO; } @@ -158,27 +142,21 @@ static int draco_read_nand_geometry(void) return 0; } +#ifdef CONFIG_SPL_BUILD /* * Read header information from EEPROM into global structure. */ -static int read_eeprom(void) +int draco_read_eeprom(void) { - /* Check if baseboard eeprom is available */ - if (i2c_probe(EEPROM_ADDR)) { - printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); - return 1; - } - -#ifdef CONFIG_SPL_BUILD /* Read Siemens eeprom data (DDR3) */ - if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, - (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { + if (siemens_ee_read_data(SIEMENS_EE_ADDR_DDR3, (uchar *)&settings.ddr3, + sizeof(struct ddr3_data))) { printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); set_default_ddr3_timings(); } /* Read Siemens eeprom data (CHIP) */ - if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, - (uchar *)&settings.chip, sizeof(settings.chip))) + if (siemens_ee_read_data(SIEMENS_EE_ADDR_CHIP, (uchar *)&settings.chip, + sizeof(settings.chip))) printf("Could not read chip settings\n"); if (ddr3_default.magic == settings.ddr3.magic && @@ -202,12 +180,9 @@ static int read_eeprom(void) print_ddr3_timings(); return draco_read_nand_geometry(); -#endif - return 0; } -#ifdef CONFIG_SPL_BUILD -static void board_init_ddr(void) +void draco_init_ddr(void) { struct emif_regs draco_ddr3_emif_reg_data = { .zq_config = 0x50074BE4, @@ -254,7 +229,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = { &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); } -static void spl_siemens_board_init(void) +void spl_draco_board_init(void) { return; } @@ -369,31 +344,3 @@ U_BOOT_CMD( ); #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ - -#if CONFIG_IS_ENABLED(NAND_CS_INIT) -#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800 -#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00 -#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00 -#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 -#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e -#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 - -/* GPMC definitions for second nand cs1 */ -static const u32 gpmc_nand_config[] = { - ETAMIN_NAND_GPMC_CONFIG1, - ETAMIN_NAND_GPMC_CONFIG2, - ETAMIN_NAND_GPMC_CONFIG3, - ETAMIN_NAND_GPMC_CONFIG4, - ETAMIN_NAND_GPMC_CONFIG5, - ETAMIN_NAND_GPMC_CONFIG6, - /*CONFIG7- computed as params */ -}; - -static void board_nand_cs_init(void) -{ - enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1], - 0x18000000, GPMC_SIZE_16M); -} -#endif - -#include "../common/board.c" diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h index f027427d1fb..935f340a8f2 100644 --- a/board/siemens/draco/board.h +++ b/board/siemens/draco/board.h @@ -1,19 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * board.h + * Board definitions for draco products * * (C) Copyright 2013 Siemens Schweiz AG * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * Based on: - * TI AM335x boards information header - * u-boot:/board/ti/am335x/board.h - * - * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ + * TI am335x specifics moved to ../common/board_am335x.h */ -#ifndef _BOARD_H_ -#define _BOARD_H_ +#ifndef _BOARD_DRACO_H_ +#define _BOARD_DRACO_H_ #define PARGS(x) #x , /* Parameter Name */ \ settings.ddr3.x, /* EEPROM Value */ \ @@ -58,21 +54,4 @@ struct draco_baseboard_id { struct chip_data chip; }; -/* - * We have three pin mux functions that must exist. We must be able to enable - * uart0, for initial output and i2c0 to read the main EEPROM. We then have a - * main pinmux function that can be overridden to enable all other pinmux that - * is required on the board. - */ -void enable_uart0_pin_mux(void); -void enable_uart1_pin_mux(void); -void enable_uart2_pin_mux(void); -void enable_uart3_pin_mux(void); -void enable_uart4_pin_mux(void); -void enable_uart5_pin_mux(void); -void enable_i2c0_pin_mux(void); -void enable_board_pin_mux(void); - -/* Forwared declaration, defined in common board.c */ -void set_env_gpios(unsigned char state); -#endif +#endif /* _BOARD_DRACO_H_ */ diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c index 2632f050336..4149e628475 100644 --- a/board/siemens/draco/mux.c +++ b/board/siemens/draco/mux.c @@ -10,13 +10,11 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <common.h> +#include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> #include <asm/arch/mux.h> -#include <asm/io.h> -#include <i2c.h> -#include "board.h" +#include "eeprom.h" static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ diff --git a/board/siemens/pxm2/MAINTAINERS b/board/siemens/pxm2/MAINTAINERS index dc02fe87c9b..49025446079 100644 --- a/board/siemens/pxm2/MAINTAINERS +++ b/board/siemens/pxm2/MAINTAINERS @@ -1,5 +1,5 @@ PXM2 BOARD -M: Samuel Egli <samuel.egli@siemens.com> +M: Enrico Leto <enrico.leto@siemens.com> S: Maintained F: board/siemens/pxm2/ F: include/configs/pxm2.h diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile index e94456ab1c3..aae536472c5 100644 --- a/board/siemens/pxm2/Makefile +++ b/board/siemens/pxm2/Makefile @@ -14,6 +14,8 @@ obj-y := mux.o endif obj-y += board.o +obj-y += ../common/board_am335x.o +obj-y += ../common/eeprom.o ifndef CONFIG_SPL_BUILD obj-y += ../common/factoryset.o endif diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 40aee7c8b3e..888c7c09baf 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -12,37 +12,24 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> +#include <cpsw.h> #include <env.h> -#include <errno.h> +#include <i2c.h> #include <init.h> -#include <log.h> -#include <malloc.h> +#include <nand.h> #include <net.h> -#include <spl.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc_host_def.h> +#include <asm/arch/ddr_defs.h> #include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <asm/emif.h> #include <asm/gpio.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include <watchdog.h> -#include "board.h" -#include "../common/factoryset.h" +#include <asm/io.h> #include "pmic.h" -#include <nand.h> -#include <bmp_layout.h> +#include "../common/board_am335x.h" +#include "../common/eeprom.h" +#include "../common/factoryset.h" #ifdef CONFIG_SPL_BUILD -static void board_init_ddr(void) +void draco_init_ddr(void) { struct emif_regs pxm2_ddr3_emif_reg_data = { .sdram_config = 0x41805332, @@ -134,7 +121,7 @@ int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) const struct dpll_params dpll_mpu_pxm2 = { 720, OSC-1, 1, -1, -1, -1, -1}; -void spl_siemens_board_init(void) +void spl_draco_board_init(void) { uchar buf[4]; /* @@ -160,14 +147,14 @@ void spl_siemens_board_init(void) printf("voltage update failed\n"); } } -#endif /* if def CONFIG_SPL_BUILD */ -int read_eeprom(void) +int draco_read_eeprom(void) { /* nothing ToDo here for this board */ return 0; } +#endif /* if def CONFIG_SPL_BUILD */ #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) @@ -274,5 +261,3 @@ int board_late_init(void) return 0; } #endif - -#include "../common/board.c" diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h deleted file mode 100644 index 9067e4d5aa8..00000000000 --- a/board/siemens/pxm2/board.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * board.h - * - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * TI AM335x boards information header - * u-boot:/board/ti/am335x/board.h - * - * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -void enable_uart0_pin_mux(void); -void enable_i2c0_pin_mux(void); -void enable_board_pin_mux(void); -#endif diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c index d21ef47771d..bdf460b5920 100644 --- a/board/siemens/pxm2/mux.c +++ b/board/siemens/pxm2/mux.c @@ -11,13 +11,11 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <common.h> +#include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> #include <asm/arch/mux.h> -#include <asm/io.h> -#include <i2c.h> -#include "board.h" +#include "eeprom.h" static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ diff --git a/board/siemens/rut/MAINTAINERS b/board/siemens/rut/MAINTAINERS index 1e92710904b..4d8e2567099 100644 --- a/board/siemens/rut/MAINTAINERS +++ b/board/siemens/rut/MAINTAINERS @@ -1,5 +1,5 @@ RUT BOARD -M: Samuel Egli <samuel.egli@siemens.com> +M: Enrico Leto <enrico.leto@siemens.com> S: Maintained F: board/siemens/rut/ F: include/configs/rut.h diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile index e94456ab1c3..aae536472c5 100644 --- a/board/siemens/rut/Makefile +++ b/board/siemens/rut/Makefile @@ -14,6 +14,8 @@ obj-y := mux.o endif obj-y += board.o +obj-y += ../common/board_am335x.o +obj-y += ../common/eeprom.o ifndef CONFIG_SPL_BUILD obj-y += ../common/factoryset.o endif diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index bad0b71ce2d..8d316918e7a 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -10,44 +10,30 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> +#include <cpsw.h> #include <env.h> -#include <errno.h> #include <init.h> -#include <malloc.h> -#include <net.h> -#include <spi.h> -#include <spl.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/ddr_defs.h> +#include <linux/delay.h> +#include <nand.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc_host_def.h> +#include <asm/arch/ddr_defs.h> #include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <asm/emif.h> #include <asm/gpio.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include <video.h> -#include <watchdog.h> -#include <linux/delay.h> -#include "board.h" +#include <asm/io.h> +#include "../common/board_am335x.h" +#include "../common/eeprom.h" #include "../common/factoryset.h" +#ifdef CONFIG_SPL_BUILD /* * Read header information from EEPROM into global structure. */ -static int read_eeprom(void) +int draco_read_eeprom(void) { return 0; } -#ifdef CONFIG_SPL_BUILD -static void board_init_ddr(void) +void draco_init_ddr(void) { struct emif_regs rut_ddr3_emif_reg_data = { .sdram_config = 0x61C04AB2, @@ -124,7 +110,7 @@ err: #define REQUEST_AND_PULSE_RESET(N) \ request_and_pulse_reset(N, #N); -static void spl_siemens_board_init(void) +void spl_draco_board_init(void) { REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO); REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO); @@ -244,5 +230,3 @@ int board_late_init(void) return 0; } #endif - -#include "../common/board.c" diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h deleted file mode 100644 index 9067e4d5aa8..00000000000 --- a/board/siemens/rut/board.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * board.h - * - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * TI AM335x boards information header - * u-boot:/board/ti/am335x/board.h - * - * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -void enable_uart0_pin_mux(void); -void enable_i2c0_pin_mux(void); -void enable_board_pin_mux(void); -#endif diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c index 894a9bf1e3d..8947e4e537c 100644 --- a/board/siemens/rut/mux.c +++ b/board/siemens/rut/mux.c @@ -11,12 +11,10 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <common.h> +#include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> #include <asm/arch/mux.h> -#include <asm/io.h> -#include <i2c.h> static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */ diff --git a/board/skyworth/hc2910-2aghd05/Kconfig b/board/skyworth/hc2910-2aghd05/Kconfig index f85f1f2631d..620a3177f48 100644 --- a/board/skyworth/hc2910-2aghd05/Kconfig +++ b/board/skyworth/hc2910-2aghd05/Kconfig @@ -9,7 +9,4 @@ config SYS_VENDOR config SYS_SOC default "hi3798mv200" -config SYS_CONFIG_NAME - default "hc2910-2aghd05" - endif diff --git a/board/skyworth/hc2910-2aghd05/MAINTAINERS b/board/skyworth/hc2910-2aghd05/MAINTAINERS index 2c1e750018e..13915556bc5 100644 --- a/board/skyworth/hc2910-2aghd05/MAINTAINERS +++ b/board/skyworth/hc2910-2aghd05/MAINTAINERS @@ -2,5 +2,4 @@ HC2910 2AGHD05 BOARD M: Yang Xiwen <firbidden405@outlook.com> S: Maintained F: board/skyworth/hc2910-2aghd05 -F: include/configs/hc2910-2aghd05.h F: configs/hc2910_2aghd05_defconfig diff --git a/board/st/stih410-b2260/Kconfig b/board/st/stih410-b2260/Kconfig index 590add05fea..441a83cbaea 100644 --- a/board/st/stih410-b2260/Kconfig +++ b/board/st/stih410-b2260/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "stih410" config SYS_CONFIG_NAME - string default "stih410-b2260" endif diff --git a/board/st/stm32f429-discovery/Kconfig b/board/st/stm32f429-discovery/Kconfig index e73d11bada4..3c93df20afa 100644 --- a/board/st/stm32f429-discovery/Kconfig +++ b/board/st/stm32f429-discovery/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "stm32f4" config SYS_CONFIG_NAME - string default "stm32f429-discovery" endif diff --git a/board/st/stm32f429-evaluation/Kconfig b/board/st/stm32f429-evaluation/Kconfig index ca4bb3d9c95..eaa40db8a74 100644 --- a/board/st/stm32f429-evaluation/Kconfig +++ b/board/st/stm32f429-evaluation/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "stm32f4" config SYS_CONFIG_NAME - string default "stm32f429-evaluation" endif diff --git a/board/st/stm32f469-discovery/Kconfig b/board/st/stm32f469-discovery/Kconfig index de61b6f2f6d..622a8d82d81 100644 --- a/board/st/stm32f469-discovery/Kconfig +++ b/board/st/stm32f469-discovery/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "stm32f4" config SYS_CONFIG_NAME - string default "stm32f469-discovery" endif diff --git a/board/st/stm32f746-disco/Kconfig b/board/st/stm32f746-disco/Kconfig index 09289d23238..86ace17377c 100644 --- a/board/st/stm32f746-disco/Kconfig +++ b/board/st/stm32f746-disco/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "stm32f7" config SYS_CONFIG_NAME - string default "stm32f746-disco" endif diff --git a/board/st/stm32h743-disco/Kconfig b/board/st/stm32h743-disco/Kconfig index 7d6ec1d9586..bc116bcf32f 100644 --- a/board/st/stm32h743-disco/Kconfig +++ b/board/st/stm32h743-disco/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "stm32h7" config SYS_CONFIG_NAME - string default "stm32h743-disco" endif diff --git a/board/st/stm32h743-eval/Kconfig b/board/st/stm32h743-eval/Kconfig index ea879b13c8b..ff86de25f7d 100644 --- a/board/st/stm32h743-eval/Kconfig +++ b/board/st/stm32h743-eval/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "stm32h7" config SYS_CONFIG_NAME - string default "stm32h743-eval" endif diff --git a/board/st/stm32h750-art-pi/Kconfig b/board/st/stm32h750-art-pi/Kconfig index c31b9849fde..ab2d0f227d7 100644 --- a/board/st/stm32h750-art-pi/Kconfig +++ b/board/st/stm32h750-art-pi/Kconfig @@ -13,7 +13,6 @@ config SYS_SOC default "stm32h7" config SYS_CONFIG_NAME - string default "stm32h750-art-pi" endif diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig index dd9816ec243..e13ee8f6e90 100644 --- a/board/sysam/amcore/Kconfig +++ b/board/sysam/amcore/Kconfig @@ -13,7 +13,6 @@ config SYS_VENDOR default "sysam" config SYS_CONFIG_NAME - string default "amcore" endif diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env index a6d967e982d..334374abb73 100644 --- a/board/ti/am62ax/am62ax.env +++ b/board/ti/am62ax/am62ax.env @@ -1,5 +1,4 @@ #include <env/ti/ti_common.env> -#include <env/ti/default_findfdt.env> #include <env/ti/mmc.env> name_kern=Image diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index cd3360a4302..62d3664936e 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -13,6 +13,8 @@ #include <fdt_support.h> #include <spl.h> +#include "../common/fdt_ops.h" + int board_init(void) { return 0; @@ -27,3 +29,11 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + ti_set_fdt_env(NULL, NULL); + return 0; +} +#endif diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env index e53a55c38fb..9cb186c2a03 100644 --- a/board/ti/am62x/am62x.env +++ b/board/ti/am62x/am62x.env @@ -1,5 +1,4 @@ #include <env/ti/ti_common.env> -#include <env/ti/default_findfdt.env> #include <env/ti/mmc.env> name_kern=Image diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 88e02155ee3..b3e8680dfab 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -19,6 +19,8 @@ #include <asm/arch/hardware.h> #include <dm/uclass.h> +#include "../common/fdt_ops.h" + DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(SPLASH_SCREEN) @@ -54,6 +56,14 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + ti_set_fdt_env(NULL, NULL); + return 0; +} +#endif + int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index efd736b99be..9a8812d4ee5 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -2,14 +2,6 @@ #include <env/ti/mmc.env> #include <env/ti/k3_dfu.env> -findfdt= - if test $board_name = am64x_gpevm; then - setenv name_fdt ti/k3-am642-evm.dtb; fi; - if test $board_name = am64x_skevm; then - setenv name_fdt ti/k3-am642-sk.dtb; fi; - if test $name_fdt = undefined; then - echo WARNING: Could not determine device tree to use; fi; - setenv fdtfile ${name_fdt} name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts} @@ -43,7 +35,6 @@ get_fit_usb=load usb ${bootpart} ${addr_fit} usbboot=setenv boot usb; setenv bootpart 0:2; usb start; - run findfdt; run init_usb; run get_kern_usb; run get_fdt_usb; diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index a7ca6be436e..b8de69da06c 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -16,6 +16,7 @@ #include <env.h> #include "../common/board_detect.h" +#include "../common/fdt_ops.h" #define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \ board_ti_k3_is("AM64-EVM") || \ @@ -181,6 +182,12 @@ int checkboard(void) } #ifdef CONFIG_BOARD_LATE_INIT +static struct ti_fdt_map ti_am64_evm_fdt_map[] = { + {"am64x_gpevm", "k3-am642-evm.dtb"}, + {"am64x_skevm", "k3-am642-sk.dtb"}, + { /* Sentinel. */ } +}; + static void setup_board_eeprom_env(void) { char *name = "am64x_gpevm"; @@ -198,6 +205,7 @@ static void setup_board_eeprom_env(void) invalid_eeprom: set_board_info_env_am6(name); + ti_set_fdt_env(name, ti_am64_evm_fdt_map); } static void setup_serial(void) diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env index 286b9c300c0..814374d68cf 100644 --- a/board/ti/am65x/am65x.env +++ b/board/ti/am65x/am65x.env @@ -5,9 +5,6 @@ #include <env/ti/k3_rproc.env> #endif -findfdt= - setenv name_fdt ti/k3-am654-base-board.dtb; - setenv fdtfile ${name_fdt} name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index df209021c1b..3109c9a2aca 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -22,6 +22,7 @@ #include <linux/printk.h> #include "../common/board_detect.h" +#include "../common/fdt_ops.h" #define board_is_am65x_base_board() board_ti_is("AM6-COMPROCEVM") @@ -141,6 +142,7 @@ static void setup_board_eeprom_env(void) invalid_eeprom: set_board_info_env_am6(name); + ti_set_fdt_env(NULL, NULL); } static int init_daughtercard_det_gpio(char *gpio_name, struct gpio_desc *desc) diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 49edd98014a..de44e4de211 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -49,3 +49,15 @@ config TI_COMMON_CMD_OPTIONS imply CMD_SPI imply CMD_TIME imply CMD_USB if USB + +config TI_FDT_FOLDER_PATH + string "Location of Folder path where dtb is present" + default "ti/davinci" if ARCH_DAVINCI + default "ti/keystone" if ARCH_KEYSTONE + default "ti/omap" if ARCH_OMAP2PLUS + default "ti" if ARCH_K3 + depends on ARCH_DAVINCI || ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3 + help + Folder path for kernel device tree default. + This is used along with fdtfile path to locate the kernel + device tree blob. diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 26bf12e2e6d..5ac361ba7fc 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -3,3 +3,4 @@ obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o obj-${CONFIG_CMD_EXTENSION} += cape_detect.o +obj-${CONFIG_OF_LIBFDT} += fdt_ops.o diff --git a/board/ti/common/fdt_ops.c b/board/ti/common/fdt_ops.c new file mode 100644 index 00000000000..eb917be9e0d --- /dev/null +++ b/board/ti/common/fdt_ops.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Library to support FDT file operations which are common + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <env.h> +#include <vsprintf.h> +#include "fdt_ops.h" + +void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map) +{ + char *fdt_file_name = NULL; + char fdtfile[TI_FDT_FILE_MAX]; + + if (board_name) { + while (fdt_map) { + /* Check for NULL terminator in the list */ + if (!fdt_map->board_name) + break; + if (!strncmp(fdt_map->board_name, board_name, TI_BOARD_NAME_MAX)) { + fdt_file_name = fdt_map->fdt_file_name; + break; + } + fdt_map++; + } + } + + /* match not found OR null board_name */ + if (!fdt_file_name) { + /* + * Prioritize CONFIG_DEFAULT_FDT_FILE - if that is not defined, + * or is empty, then use CONFIG_DEFAULT_DEVICE_TREE + */ +#ifdef CONFIG_DEFAULT_FDT_FILE + if (strlen(CONFIG_DEFAULT_FDT_FILE)) { + snprintf(fdtfile, sizeof(fdtfile), "%s/%s", + CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_FDT_FILE); + } else +#endif + { + snprintf(fdtfile, sizeof(fdtfile), "%s/%s.dtb", + CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_DEVICE_TREE); + } + } else { + snprintf(fdtfile, sizeof(fdtfile), "%s/%s", CONFIG_TI_FDT_FOLDER_PATH, + fdt_file_name); + } + + env_set("fdtfile", fdtfile); + + /* + * XXX: DEPRECATION WARNING: 2 u-boot versions (2024.10). + * + * Maintain compatibility with downstream scripts that may be using + * name_fdt + */ + if (board_name) + env_set("name_fdt", fdtfile); + /* Also set the findfdt legacy script to warn users to stop using this */ + env_set("findfdt", + "echo WARN: fdtfile already set. Stop using findfdt in script"); +} diff --git a/board/ti/common/fdt_ops.h b/board/ti/common/fdt_ops.h new file mode 100644 index 00000000000..5d304994fb6 --- /dev/null +++ b/board/ti/common/fdt_ops.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Library to support common device tree manipulation for TI EVMs + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com + */ + +#ifndef __FDT_OPS_H +#define __FDT_OPS_H + +#define TI_BOARD_NAME_MAX 20 +#define TI_FDT_FILE_MAX 200 + +/** + * struct ti_fdt_map - mapping of device tree blob name to board name + * @board_name: board_name up to TI_BOARD_NAME_MAX long + * @fdt_file_name: device tree blob name as described by kernel + */ +struct ti_fdt_map { + const char *board_name; + char *fdt_file_name; +}; + +/** + * ti_set_fdt_env - Find the correct device tree file name based on the + * board name and set 'fdtfile' env variable with correct folder + * structure appropriate to the architecture and Linux kernel's + * 'make install_dtbs' conventions. This function is invoked typically + * as part of board_late_init. + * + * fdt name is picked by: + * a) If a board name match is found, use the match + * b) If not, CONFIG_DEFAULT_FDT_FILE (Boot OS device tree) if that is defined + * and not null + * c) If not, Use CONFIG_DEFAULT_DEVICE_TREE (DT control for bootloader) + * + * @board_name: match to search with (max of TI_BOARD_NAME_MAX chars) + * @fdt_map: NULL terminated array of device tree file name matches. + */ +void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map); + +#endif /* __FDT_OPS_H */ diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index b77cffc5ef5..9dc3ed6dfff 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -16,6 +16,7 @@ #include <dm.h> #include "../common/board_detect.h" +#include "../common/fdt_ops.h" #define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \ board_ti_k3_is("J721EX-PM2-SOM")) @@ -353,6 +354,12 @@ static int probe_daughtercards(void) #endif #ifdef CONFIG_BOARD_LATE_INIT +static struct ti_fdt_map ti_j721e_evm_fdt_map[] = { + {"j721e", "k3-j721e-common-proc-board.dtb"}, + {"j721e-sk", "k3-j721e-sk.dtb"}, + {"j7200", "k3-j7200-common-proc-board.dtb"}, + { /* Sentinel. */ } +}; static void setup_board_eeprom_env(void) { char *name = "j721e"; @@ -372,6 +379,7 @@ static void setup_board_eeprom_env(void) invalid_eeprom: set_board_info_env_am6(name); + ti_set_fdt_env(name, ti_j721e_evm_fdt_map); } static void setup_serial(void) diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index cb27bf5e2b2..38bfd7d4963 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -7,16 +7,6 @@ #include <env/ti/k3_rproc.env> #endif -default_device_tree=ti/k3-j721e-common-proc-board.dtb -findfdt= - setenv name_fdt ${default_device_tree}; - if test $board_name = j721e; then - setenv name_fdt ti/k3-j721e-common-proc-board.dtb; fi; - if test $board_name = j7200; then - setenv name_fdt ti/k3-j7200-common-proc-board.dtb; fi; - if test $board_name = j721e-eaik || test $board_name = j721e-sk; then - setenv name_fdt ti/k3-j721e-sk.dtb; fi; - setenv fdtfile ${name_fdt} name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 1220cd84519..5a0281d6b48 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -23,6 +23,7 @@ #include <dm/root.h> #include "../common/board_detect.h" +#include "../common/fdt_ops.h" DECLARE_GLOBAL_DATA_PTR; @@ -114,6 +115,12 @@ int checkboard(void) return 0; } +static struct ti_fdt_map ti_j721s2_evm_fdt_map[] = { + {"j721s2", "k3-j721s2-common-proc-board.dtb"}, + {"am68-sk", "k3-am68-sk-base-board.dtb"}, + { /* Sentinel. */ } +}; + static void setup_board_eeprom_env(void) { char *name = "j721s2"; @@ -131,6 +138,7 @@ static void setup_board_eeprom_env(void) invalid_eeprom: set_board_info_env_am6(name); + ti_set_fdt_env(name, ti_j721s2_evm_fdt_map); } static void setup_serial(void) diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index 64e3d9da85f..9a03b9f30ae 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -7,14 +7,6 @@ #include <env/ti/k3_rproc.env> #endif -default_device_tree=ti/k3-j721s2-common-proc-board.dtb -findfdt= - setenv name_fdt ${default_device_tree}; - if test $board_name = j721s2; then \ - setenv name_fdt ti/k3-j721s2-common-proc-board.dtb; fi; - if test $board_name = am68-sk; then - setenv name_fdt ti/k3-am68-sk-base-board.dtb; fi; - setenv fdtfile ${name_fdt} name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs earlycon=ns16550a,mmio32,0x02880000 diff --git a/board/ti/omap3evm/Kconfig b/board/ti/omap3evm/Kconfig index 08a8aa20ae8..cd71fe08317 100644 --- a/board/ti/omap3evm/Kconfig +++ b/board/ti/omap3evm/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "omap3_evm" +source "board/ti/common/Kconfig" + endif diff --git a/board/ti/panda/Kconfig b/board/ti/panda/Kconfig index 8f277b612a4..5912f69babe 100644 --- a/board/ti/panda/Kconfig +++ b/board/ti/panda/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "omap4_panda" +source "board/ti/common/Kconfig" + endif diff --git a/board/ti/sdp4430/Kconfig b/board/ti/sdp4430/Kconfig index 36f18528216..65e9107bc1b 100644 --- a/board/ti/sdp4430/Kconfig +++ b/board/ti/sdp4430/Kconfig @@ -12,4 +12,6 @@ config SYS_CONFIG_NAME config CMD_BAT bool "Enable board-specific battery command" +source "board/ti/common/Kconfig" + endif diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 7187e1ba377..4a7de5483d2 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -147,6 +147,16 @@ const struct toradex_som toradex_modules[] = { [74] = { "Verdin AM62 Dual 1GB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, [75] = { "Verdin AM62 Dual 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, [76] = { "Verdin AM62 Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + [77] = { "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + [78] = { "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + [79] = { "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + [80] = { "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + [81] = { "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + [82] = { "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) }, + [83] = { "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) }, + [84] = { "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, + [85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, + [86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index ea58bd43b17..021cc21b5e2 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -102,6 +102,16 @@ enum { VERDIN_AM62D_1G_IT, VERDIN_AM62D_1G_WIFI_BT_IT, /* 75 */ VERDIN_AM62Q_2G_WIFI_BT_IT, + COLIBRI_IMX6S_NOWINCE, + COLIBRI_IMX6S_IT_NOWINCE, + COLIBRI_IMX6DL_NOWINCE, + COLIBRI_IMX6DL_IT_NOWINCE, /* 80 */ + COLIBRI_IMX7D_NOWINCE, + APALIS_IMX6D_NOWINCE, + APALIS_IMX6Q_NOWINCE, + APALIS_IMX6D_IT_NOWINCE, + APALIS_IMX6Q_IT_NOWINCE, /* 85 */ + VERDIN_IMX8MMDL_2G_IT, }; enum { diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 395eb365a0b..e948fc16ba9 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -14,13 +14,10 @@ #include <fdt_support.h> #include <init.h> #include <k3-ddrss.h> -#include <power/regulator.h> #include <spl.h> #include "../common/tdx-cfg-block.h" -#define VDD_CORE_REG "buck1" - DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -53,37 +50,9 @@ int board_fit_config_name_match(const char *name) } #endif -static u32 get_vdd_core_nominal(void) -{ - int core_uvolt; - - switch (k3_get_speed_grade()) { - case 'G': - case 'K': - case 'S': - core_uvolt = 750000; - break; - case 'T': - default: - core_uvolt = 850000; - break; - } - return core_uvolt; -} - #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { - int core_uvolt; - - core_uvolt = get_vdd_core_nominal(); - if (core_uvolt != 850000) { - do_fixup_by_path_u32(blob, "/bus@f0000/i2c@20000000/pmic@30/regulators/buck1", - "regulator-max-microvolt", core_uvolt, 0); - do_fixup_by_path_u32(blob, "/bus@f0000/i2c@20000000/pmic@30/regulators/buck1", - "regulator-min-microvolt", core_uvolt, 0); - } - return ft_common_board_setup(blob, bd); } #endif @@ -118,22 +87,6 @@ static void select_dt_from_module_version(void) int board_late_init(void) { - int ret; - int core_uvolt; - struct udevice *dev = NULL; - - core_uvolt = get_vdd_core_nominal(); - if (core_uvolt != 850000) { - /* Set CPU core voltage to 0.75V for slower speed grades */ - ret = regulator_get_by_devname(VDD_CORE_REG, &dev); - if (ret) - pr_err("VDD CORE Regulator get error: %d\n", ret); - - ret = regulator_set_value_force(dev, core_uvolt); - if (ret) - pr_err("VDD CORE Regulator value setting error: %d\n", ret); - } - select_dt_from_module_version(); return 0; diff --git a/board/variscite/imx93_var_som/spl.c b/board/variscite/imx93_var_som/spl.c index 502e599b91a..e6db4eb562b 100644 --- a/board/variscite/imx93_var_som/spl.c +++ b/board/variscite/imx93_var_som/spl.c @@ -13,6 +13,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/imx93_pins.h> +#include <asm/arch/mu.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> @@ -114,9 +115,9 @@ void board_init_f(ulong dummy) preloader_console_init(); - ret = arch_cpu_init(); + ret = imx9_probe_mu(NULL, NULL); if (ret) { - printf("Fail to init Sentinel API\n"); + printf("Fail to init ELE API\n"); } else { printf("SOC: 0x%x\n", gd->arch.soc_rev); printf("LC: 0x%x\n", gd->arch.lifecycle); diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index 4bc9f72c541..d2dec397ed6 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_CPU default "generic" -config SYS_CONFIG_NAME - default "xilinx_mbv" - config TEXT_BASE default 0x80000000 if !RISCV_SMODE default 0x80400000 if RISCV_SMODE && ARCH_RV32I diff --git a/board/xilinx/mbv/MAINTAINERS b/board/xilinx/mbv/MAINTAINERS index 445654fe740..db9f03388df 100644 --- a/board/xilinx/mbv/MAINTAINERS +++ b/board/xilinx/mbv/MAINTAINERS @@ -4,4 +4,3 @@ S: Maintained F: arch/riscv/dts/xilinx-mbv* F: board/xilinx/mbv/ F: configs/xilinx_mbv* -F: include/configs/xilinx_mbv.h diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index dd5eacef52a..038ff0b6130 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -6,14 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "xilinx" -config SYS_CONFIG_NAME - string "Board configuration name" - default "microblaze-generic" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - config XILINX_MICROBLAZE0_USE_MSR_INSTR int "USE_MSR_INSTR range (0:1)" default 0 diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 9f500907202..ba49eb7be22 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -18,6 +18,7 @@ #include <ahci.h> #include <scsi.h> #include <soc.h> +#include <spl.h> #include <malloc.h> #include <memalign.h> #include <wdt.h> diff --git a/boot/Kconfig b/boot/Kconfig index 71ee41645f3..3d7aabd27d6 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -20,6 +20,21 @@ config TIMESTAMP loaded that does not, the message 'Wrong FIT format: no timestamp' is shown. +config BUTTON_CMD + bool "Support for running a command if a button is held during boot" + depends on CMDLINE + depends on BUTTON + help + For many embedded devices it's useful to enter a special flashing mode + such as fastboot mode when a button is held during boot. This option + allows arbitrary commands to be assigned to specific buttons. These will + be run after "preboot" if the button is held. Configuration is done via + the environment variables "button_cmd_N_name" and "button_cmd_N" where n is + the button number (starting from 0). e.g: + + "button_cmd_0_name=vol_down" + "button_cmd_0=fastboot usb 0" + menuconfig FIT bool "Flattened Image Tree (FIT)" select HASH diff --git a/cmd/avb.c b/cmd/avb.c index 783f51b8169..8fbd48ee5a2 100644 --- a/cmd/avb.c +++ b/cmd/avb.c @@ -1,8 +1,6 @@ - +// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2018, Linaro Limited - * - * SPDX-License-Identifier: GPL-2.0+ */ #include <avb_verify.h> @@ -13,6 +11,7 @@ #include <mmc.h> #define AVB_BOOTARGS "avb_bootargs" + static struct AvbOps *avb_ops; int do_avb_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -30,8 +29,10 @@ int do_avb_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) avb_ops = avb_ops_alloc(mmc_dev); if (avb_ops) return CMD_RET_SUCCESS; + else + printf("Can't allocate AvbOps"); - printf("Failed to initialize avb2\n"); + printf("Failed to initialize AVB\n"); return CMD_RET_FAILURE; } @@ -43,10 +44,11 @@ int do_avb_read_part(struct cmd_tbl *cmdtp, int flag, int argc, s64 offset; size_t bytes, bytes_read = 0; void *buffer; + int ret; if (!avb_ops) { - printf("AVB 2.0 is not initialized, please run 'avb init'\n"); - return CMD_RET_USAGE; + printf("AVB is not initialized, please run 'avb init <id>'\n"); + return CMD_RET_FAILURE; } if (argc != 5) @@ -57,14 +59,15 @@ int do_avb_read_part(struct cmd_tbl *cmdtp, int flag, int argc, bytes = hextoul(argv[3], NULL); buffer = (void *)hextoul(argv[4], NULL); - if (avb_ops->read_from_partition(avb_ops, part, offset, bytes, - buffer, &bytes_read) == - AVB_IO_RESULT_OK) { + ret = avb_ops->read_from_partition(avb_ops, part, offset, + bytes, buffer, &bytes_read); + if (ret == AVB_IO_RESULT_OK) { printf("Read %zu bytes\n", bytes_read); return CMD_RET_SUCCESS; } - printf("Failed to read from partition\n"); + printf("Failed to read from partition '%s', err = %d\n", + part, ret); return CMD_RET_FAILURE; } @@ -76,10 +79,11 @@ int do_avb_read_part_hex(struct cmd_tbl *cmdtp, int flag, int argc, s64 offset; size_t bytes, bytes_read = 0; char *buffer; + int ret; if (!avb_ops) { - printf("AVB 2.0 is not initialized, please run 'avb init'\n"); - return CMD_RET_USAGE; + printf("AVB is not initialized, please run 'avb init <id>'\n"); + return CMD_RET_FAILURE; } if (argc != 4) @@ -96,8 +100,9 @@ int do_avb_read_part_hex(struct cmd_tbl *cmdtp, int flag, int argc, } memset(buffer, 0, bytes); - if (avb_ops->read_from_partition(avb_ops, part, offset, bytes, buffer, - &bytes_read) == AVB_IO_RESULT_OK) { + ret = avb_ops->read_from_partition(avb_ops, part, offset, + bytes, buffer, &bytes_read); + if (ret == AVB_IO_RESULT_OK) { printf("Requested %zu, read %zu bytes\n", bytes, bytes_read); printf("Data: "); for (int i = 0; i < bytes_read; i++) @@ -109,7 +114,8 @@ int do_avb_read_part_hex(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } - printf("Failed to read from partition\n"); + printf("Failed to read from partition '%s', err = %d\n", + part, ret); free(buffer); return CMD_RET_FAILURE; @@ -122,9 +128,10 @@ int do_avb_write_part(struct cmd_tbl *cmdtp, int flag, int argc, s64 offset; size_t bytes; void *buffer; + int ret; if (!avb_ops) { - printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + printf("AVB is not initialized, please run 'avb init <id>'\n"); return CMD_RET_FAILURE; } @@ -136,13 +143,15 @@ int do_avb_write_part(struct cmd_tbl *cmdtp, int flag, int argc, bytes = hextoul(argv[3], NULL); buffer = (void *)hextoul(argv[4], NULL); - if (avb_ops->write_to_partition(avb_ops, part, offset, bytes, buffer) == - AVB_IO_RESULT_OK) { + ret = avb_ops->write_to_partition(avb_ops, part, offset, + bytes, buffer); + if (ret == AVB_IO_RESULT_OK) { printf("Wrote %zu bytes\n", bytes); return CMD_RET_SUCCESS; } - printf("Failed to write in partition\n"); + printf("Failed to write in partition '%s', err = %d\n", + part, ret); return CMD_RET_FAILURE; } @@ -152,9 +161,10 @@ int do_avb_read_rb(struct cmd_tbl *cmdtp, int flag, int argc, { size_t index; u64 rb_idx; + int ret; if (!avb_ops) { - printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + printf("AVB is not initialized, please run 'avb init <id>'\n"); return CMD_RET_FAILURE; } @@ -163,13 +173,14 @@ int do_avb_read_rb(struct cmd_tbl *cmdtp, int flag, int argc, index = (size_t)hextoul(argv[1], NULL); - if (avb_ops->read_rollback_index(avb_ops, index, &rb_idx) == - AVB_IO_RESULT_OK) { + ret = avb_ops->read_rollback_index(avb_ops, index, &rb_idx); + if (ret == AVB_IO_RESULT_OK) { printf("Rollback index: %llx\n", rb_idx); return CMD_RET_SUCCESS; } - printf("Failed to read rollback index\n"); + printf("Failed to read rollback index id = %zu, err = %d\n", + index, ret); return CMD_RET_FAILURE; } @@ -179,9 +190,10 @@ int do_avb_write_rb(struct cmd_tbl *cmdtp, int flag, int argc, { size_t index; u64 rb_idx; + int ret; if (!avb_ops) { - printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + printf("AVB is not initialized, please run 'avb init <id>'\n"); return CMD_RET_FAILURE; } @@ -191,11 +203,12 @@ int do_avb_write_rb(struct cmd_tbl *cmdtp, int flag, int argc, index = (size_t)hextoul(argv[1], NULL); rb_idx = hextoul(argv[2], NULL); - if (avb_ops->write_rollback_index(avb_ops, index, rb_idx) == - AVB_IO_RESULT_OK) + ret = avb_ops->write_rollback_index(avb_ops, index, rb_idx); + if (ret == AVB_IO_RESULT_OK) return CMD_RET_SUCCESS; - printf("Failed to write rollback index\n"); + printf("Failed to write rollback index id = %zu, err = %d\n", + index, ret); return CMD_RET_FAILURE; } @@ -205,9 +218,10 @@ int do_avb_get_uuid(struct cmd_tbl *cmdtp, int flag, { const char *part; char buffer[UUID_STR_LEN + 1]; + int ret; if (!avb_ops) { - printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + printf("AVB is not initialized, please run 'avb init <id>'\n"); return CMD_RET_FAILURE; } @@ -216,14 +230,16 @@ int do_avb_get_uuid(struct cmd_tbl *cmdtp, int flag, part = argv[1]; - if (avb_ops->get_unique_guid_for_partition(avb_ops, part, buffer, - UUID_STR_LEN + 1) == - AVB_IO_RESULT_OK) { + ret = avb_ops->get_unique_guid_for_partition(avb_ops, part, + buffer, + UUID_STR_LEN + 1); + if (ret == AVB_IO_RESULT_OK) { printf("'%s' UUID: %s\n", part, buffer); return CMD_RET_SUCCESS; } - printf("Failed to read UUID\n"); + printf("Failed to read partition '%s' UUID, err = %d\n", + part, ret); return CMD_RET_FAILURE; } @@ -234,15 +250,17 @@ int do_avb_verify_part(struct cmd_tbl *cmdtp, int flag, const char * const requested_partitions[] = {"boot", NULL}; AvbSlotVerifyResult slot_result; AvbSlotVerifyData *out_data; + enum avb_boot_state boot_state; char *cmdline; char *extra_args; char *slot_suffix = ""; + int ret; bool unlocked = false; int res = CMD_RET_FAILURE; if (!avb_ops) { - printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + printf("AVB is not initialized, please run 'avb init <id>'\n"); return CMD_RET_FAILURE; } @@ -255,9 +273,10 @@ int do_avb_verify_part(struct cmd_tbl *cmdtp, int flag, printf("## Android Verified Boot 2.0 version %s\n", avb_version_string()); - if (avb_ops->read_is_device_unlocked(avb_ops, &unlocked) != - AVB_IO_RESULT_OK) { - printf("Can't determine device lock state.\n"); + ret = avb_ops->read_is_device_unlocked(avb_ops, &unlocked); + if (ret != AVB_IO_RESULT_OK) { + printf("Can't determine device lock state, err = %d\n", + ret); return CMD_RET_FAILURE; } @@ -269,18 +288,23 @@ int do_avb_verify_part(struct cmd_tbl *cmdtp, int flag, AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, &out_data); - switch (slot_result) { - case AVB_SLOT_VERIFY_RESULT_OK: - /* Until we don't have support of changing unlock states, we - * assume that we are by default in locked state. - * So in this case we can boot only when verification is - * successful; we also supply in cmdline GREEN boot state - */ + /* + * LOCKED devices with custom root of trust setup is not supported (YELLOW) + */ + if (slot_result == AVB_SLOT_VERIFY_RESULT_OK) { printf("Verification passed successfully\n"); - /* export additional bootargs to AVB_BOOTARGS env var */ + /* + * ORANGE state indicates that device may be freely modified. + * Device integrity is left to the user to verify out-of-band. + */ + if (unlocked) + boot_state = AVB_ORANGE; + else + boot_state = AVB_GREEN; - extra_args = avb_set_state(avb_ops, AVB_GREEN); + /* export boot state to AVB_BOOTARGS env var */ + extra_args = avb_set_state(avb_ops, boot_state); if (extra_args) cmdline = append_cmd_line(out_data->cmdline, extra_args); @@ -290,30 +314,8 @@ int do_avb_verify_part(struct cmd_tbl *cmdtp, int flag, env_set(AVB_BOOTARGS, cmdline); res = CMD_RET_SUCCESS; - break; - case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: - printf("Verification failed\n"); - break; - case AVB_SLOT_VERIFY_RESULT_ERROR_IO: - printf("I/O error occurred during verification\n"); - break; - case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: - printf("OOM error occurred during verification\n"); - break; - case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: - printf("Corrupted dm-verity metadata detected\n"); - break; - case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: - printf("Unsupported version avbtool was used\n"); - break; - case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: - printf("Checking rollback index failed\n"); - break; - case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: - printf("Public key was rejected\n"); - break; - default: - printf("Unknown error occurred\n"); + } else { + printf("Verification failed, reason: %s\n", str_avb_slot_error(slot_result)); } if (out_data) @@ -326,9 +328,10 @@ int do_avb_is_unlocked(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { bool unlock; + int ret; if (!avb_ops) { - printf("AVB not initialized, run 'avb init' first\n"); + printf("AVB is not initialized, please run 'avb init <id>'\n"); return CMD_RET_FAILURE; } @@ -337,13 +340,14 @@ int do_avb_is_unlocked(struct cmd_tbl *cmdtp, int flag, return CMD_RET_USAGE; } - if (avb_ops->read_is_device_unlocked(avb_ops, &unlock) == - AVB_IO_RESULT_OK) { + ret = avb_ops->read_is_device_unlocked(avb_ops, &unlock); + if (ret == AVB_IO_RESULT_OK) { printf("Unlocked = %d\n", unlock); return CMD_RET_SUCCESS; } - printf("Can't determine device lock state.\n"); + printf("Can't determine device lock state, err = %d\n", + ret); return CMD_RET_FAILURE; } @@ -356,9 +360,10 @@ int do_avb_read_pvalue(struct cmd_tbl *cmdtp, int flag, int argc, size_t bytes_read; void *buffer; char *endp; + int ret; if (!avb_ops) { - printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + printf("AVB is not initialized, please run 'avb init <id>'\n"); return CMD_RET_FAILURE; } @@ -374,15 +379,16 @@ int do_avb_read_pvalue(struct cmd_tbl *cmdtp, int flag, int argc, if (!buffer) return CMD_RET_FAILURE; - if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer, - &bytes_read) == AVB_IO_RESULT_OK) { + ret = avb_ops->read_persistent_value(avb_ops, name, bytes, + buffer, &bytes_read); + if (ret == AVB_IO_RESULT_OK) { printf("Read %zu bytes, value = %s\n", bytes_read, (char *)buffer); free(buffer); return CMD_RET_SUCCESS; } - printf("Failed to read persistent value\n"); + printf("Failed to read persistent value, err = %d\n", ret); free(buffer); @@ -394,9 +400,10 @@ int do_avb_write_pvalue(struct cmd_tbl *cmdtp, int flag, int argc, { const char *name; const char *value; + int ret; if (!avb_ops) { - printf("AVB 2.0 is not initialized, run 'avb init' first\n"); + printf("AVB is not initialized, please run 'avb init <id>'\n"); return CMD_RET_FAILURE; } @@ -406,14 +413,16 @@ int do_avb_write_pvalue(struct cmd_tbl *cmdtp, int flag, int argc, name = argv[1]; value = argv[2]; - if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1, - (const uint8_t *)value) == - AVB_IO_RESULT_OK) { + ret = avb_ops->write_persistent_value(avb_ops, name, + strlen(value) + 1, + (const uint8_t *)value); + if (ret == AVB_IO_RESULT_OK) { printf("Wrote %zu bytes\n", strlen(value) + 1); return CMD_RET_SUCCESS; } - printf("Failed to write persistent value\n"); + printf("Failed to write persistent value `%s` = `%s`, err = %d\n", + name, value, ret); return CMD_RET_FAILURE; } diff --git a/cmd/hash.c b/cmd/hash.c index e163cd67742..5534a735fa7 100644 --- a/cmd/hash.c +++ b/cmd/hash.c @@ -14,15 +14,22 @@ #include <hash.h> #include <linux/ctype.h> +#if IS_ENABLED(CONFIG_HASH_VERIFY) +#define HARGS 6 +#else +#define HARGS 5 +#endif + static int do_hash(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { char *s; int flags = HASH_FLAG_ENV; -#ifdef CONFIG_HASH_VERIFY - if (argc < 4) + if (argc < (HARGS - 1)) return CMD_RET_USAGE; + +#if IS_ENABLED(CONFIG_HASH_VERIFY) if (!strcmp(argv[1], "-v")) { flags |= HASH_FLAG_VERIFY; argc--; @@ -37,18 +44,12 @@ static int do_hash(struct cmd_tbl *cmdtp, int flag, int argc, return hash_command(*argv, flags, cmdtp, flag, argc - 1, argv + 1); } -#ifdef CONFIG_HASH_VERIFY -#define HARGS 6 -#else -#define HARGS 5 -#endif - U_BOOT_CMD( hash, HARGS, 1, do_hash, "compute hash message digest", "algorithm address count [[*]hash_dest]\n" " - compute message digest [save to env var / *address]" -#ifdef CONFIG_HASH_VERIFY +#if IS_ENABLED(CONFIG_HASH_VERIFY) "\nhash -v algorithm address count [*]hash\n" " - verify message digest of memory area to immediate value, \n" " env var or *address" diff --git a/common/Makefile b/common/Makefile index f010c2a1b9b..e9835473420 100644 --- a/common/Makefile +++ b/common/Makefile @@ -12,6 +12,7 @@ obj-y += cli_getch.o cli_simple.o cli_readline.o obj-$(CONFIG_HUSH_OLD_PARSER) += cli_hush.o obj-$(CONFIG_HUSH_MODERN_PARSER) += cli_hush_modern.o obj-$(CONFIG_AUTOBOOT) += autoboot.o +obj-$(CONFIG_BUTTON_CMD) += button_cmd.o obj-y += version.o # # boards diff --git a/common/avb_verify.c b/common/avb_verify.c index 48ba8db51e5..cff9117d92f 100644 --- a/common/avb_verify.c +++ b/common/avb_verify.c @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2018, Linaro Limited - * - * SPDX-License-Identifier: GPL-2.0+ */ #include <avb_verify.h> @@ -120,6 +119,55 @@ static const unsigned char avb_root_pub[1032] = { 0xd8, 0x7e, }; +const char *str_avb_io_error(AvbIOResult res) +{ + switch (res) { + case AVB_IO_RESULT_OK: + return "Requested operation was successful"; + case AVB_IO_RESULT_ERROR_IO: + return "Underlying hardware encountered an I/O error"; + case AVB_IO_RESULT_ERROR_OOM: + return "Unable to allocate memory"; + case AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION: + return "Requested partition does not exist"; + case AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION: + return "Bytes requested is outside the range of partition"; + case AVB_IO_RESULT_ERROR_NO_SUCH_VALUE: + return "Named persistent value does not exist"; + case AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE: + return "Named persistent value size is not supported"; + case AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE: + return "Buffer is too small for the requested operation"; + default: + return "Unknown AVB error"; + } +} + +const char *str_avb_slot_error(AvbSlotVerifyResult res) +{ + switch (res) { + case AVB_SLOT_VERIFY_RESULT_OK: + return "Verification passed successfully"; + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + return "Allocation of memory failed"; + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + return "I/O error occurred while trying to load data"; + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + return "Digest didn't match or signature checks failed"; + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + return "Rollback index is less than its stored value"; + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + return "Public keys are not accepted"; + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + return "Metadata is invalid or inconsistent"; + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + return "Metadata requires a newer version of libavb"; + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + return "Invalid arguments are used"; + default: + return "Unknown AVB slot verification error"; + } +} /** * ============================================================================ * Boot states support (GREEN, YELLOW, ORANGE, RED) and dm_verity @@ -280,9 +328,9 @@ static unsigned long mmc_read_and_flush(struct mmc_part *part, * Reading fails on unaligned buffers, so we have to * use aligned temporary buffer and then copy to destination */ - if (unaligned) { - printf("Handling unaligned read buffer..\n"); + debug("%s: handling unaligned read buffer, addr = 0x%p\n", + __func__, buffer); tmp_buf = get_sector_buf(); buf_size = get_sector_buf_size(); if (sectors > buf_size / part->info.blksz) @@ -321,7 +369,8 @@ static unsigned long mmc_write(struct mmc_part *part, lbaint_t start, if (unaligned) { tmp_buf = get_sector_buf(); buf_size = get_sector_buf_size(); - printf("Handling unaligned wrire buffer..\n"); + debug("%s: handling unaligned read buffer, addr = 0x%p\n", + __func__, buffer); if (sectors > buf_size / part->info.blksz) sectors = buf_size / part->info.blksz; @@ -349,28 +398,35 @@ static struct mmc_part *get_partition(AvbOps *ops, const char *partition) dev_num = get_boot_device(ops); part->mmc = find_mmc_device(dev_num); if (!part->mmc) { - printf("No MMC device at slot %x\n", dev_num); + printf("%s: no MMC device at slot %x\n", __func__, dev_num); goto err; } - if (mmc_init(part->mmc)) { - printf("MMC initialization failed\n"); + ret = mmc_init(part->mmc); + if (ret) { + printf("%s: MMC initialization failed, err = %d\n", + __func__, ret); goto err; } - ret = mmc_switch_part(part->mmc, part_num); - if (ret) - goto err; + if (IS_MMC(part->mmc)) { + ret = mmc_switch_part(part->mmc, part_num); + if (ret) { + printf("%s: MMC part switch failed, err = %d\n", + __func__, ret); + goto err; + } + } mmc_blk = mmc_get_blk_desc(part->mmc); if (!mmc_blk) { - printf("Error - failed to obtain block descriptor\n"); + printf("%s: failed to obtain block descriptor\n", __func__); goto err; } ret = part_get_info_by_name(mmc_blk, partition, &part->info); if (ret < 0) { - printf("Can't find partition '%s'\n", partition); + printf("%s: can't find partition '%s'\n", __func__, partition); goto err; } @@ -683,7 +739,7 @@ static AvbIOResult read_rollback_index(AvbOps *ops, { #ifndef CONFIG_OPTEE_TA_AVB /* For now we always return 0 as the stored rollback index. */ - printf("%s not supported yet\n", __func__); + debug("%s: rollback protection is not implemented\n", __func__); if (out_rollback_index) *out_rollback_index = 0; @@ -729,7 +785,7 @@ static AvbIOResult write_rollback_index(AvbOps *ops, { #ifndef CONFIG_OPTEE_TA_AVB /* For now this is a no-op. */ - printf("%s not supported yet\n", __func__); + debug("%s: rollback protection is not implemented\n", __func__); return AVB_IO_RESULT_OK; #else @@ -765,8 +821,7 @@ static AvbIOResult read_is_device_unlocked(AvbOps *ops, bool *out_is_unlocked) { #ifndef CONFIG_OPTEE_TA_AVB /* For now we always return that the device is unlocked. */ - - printf("%s not supported yet\n", __func__); + debug("%s: device locking is not implemented\n", __func__); *out_is_unlocked = true; diff --git a/common/button_cmd.c b/common/button_cmd.c new file mode 100644 index 00000000000..b6a8434d6f2 --- /dev/null +++ b/common/button_cmd.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Caleb Connolly <caleb.connolly@linaro.org> + */ + +#include <button.h> +#include <command.h> +#include <env.h> +#include <log.h> +#include <vsprintf.h> + +/* Some sane limit "just in case" */ +#define MAX_BTN_CMDS 32 + +struct button_cmd { + bool pressed; + const char *btn_name; + const char *cmd; +}; + +/* + * Button commands are set via environment variables, e.g.: + * button_cmd_N_name=Volume Up + * button_cmd_N=fastboot usb 0 + * + * This function will retrieve the command for the given button N + * and populate the cmd struct with the command string and pressed + * state of the button. + * + * Returns 1 if a command was found, 0 otherwise. + */ +static int get_button_cmd(int n, struct button_cmd *cmd) +{ + const char *cmd_str; + struct udevice *btn; + char buf[24]; + + snprintf(buf, sizeof(buf), "button_cmd_%d_name", n); + cmd->btn_name = env_get(buf); + if (!cmd->btn_name) + return 0; + + button_get_by_label(cmd->btn_name, &btn); + if (!btn) { + log_err("No button labelled '%s'\n", cmd->btn_name); + return 0; + } + + cmd->pressed = button_get_state(btn) == BUTTON_ON; + /* If the button isn't pressed then cmd->cmd will be unused so don't waste + * cycles reading it + */ + if (!cmd->pressed) + return 1; + + snprintf(buf, sizeof(buf), "button_cmd_%d", n); + cmd_str = env_get(buf); + if (!cmd_str) { + log_err("No command set for button '%s'\n", cmd->btn_name); + return 0; + } + + cmd->cmd = cmd_str; + + return 1; +} + +void process_button_cmds(void) +{ + struct button_cmd cmd = {0}; + int i = 0; + + while (get_button_cmd(i++, &cmd) && i < MAX_BTN_CMDS) { + if (!cmd.pressed) + continue; + + log_info("BTN '%s'> %s\n", cmd.btn_name, cmd.cmd); + run_command(cmd.cmd, CMD_FLAG_ENV); + /* Don't run commands for multiple buttons */ + return; + } +} diff --git a/common/event.c b/common/event.c index dc61b9672f3..16c2ba6cc92 100644 --- a/common/event.c +++ b/common/event.c @@ -56,7 +56,10 @@ _Static_assert(ARRAY_SIZE(type_name) == EVT_COUNT, "event type_name size"); const char *event_type_name(enum event_t type) { #if CONFIG_IS_ENABLED(EVENT_DEBUG) - return type_name[type]; + if (type < ARRAY_SIZE(type_name)) + return type_name[type]; + else + return "(unknown)"; #else return "(unknown)"; #endif diff --git a/common/main.c b/common/main.c index 6dba6cba144..82d3aafa53c 100644 --- a/common/main.c +++ b/common/main.c @@ -8,6 +8,7 @@ #include <common.h> #include <autoboot.h> +#include <button.h> #include <bootstage.h> #include <bootstd.h> #include <cli.h> @@ -62,6 +63,8 @@ void main_loop(void) efi_launch_capsules(); } + process_button_cmds(); + s = bootdelay_process(); if (cli_process_fdt(&s)) cli_secure_boot_cmd(s); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 8805dd33fec..6405374bcc1 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -371,7 +371,8 @@ config SPL_SHARES_INIT_SP_ADDR config SPL_STACK hex "Initial stack pointer location" - depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK + depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && \ + SPL_FRAMEWORK || ROCKCHIP_RK3036 depends on !SPL_SHARES_INIT_SP_ADDR default 0x946bb8 if ARCH_MX7 default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB diff --git a/common/usb_hub.c b/common/usb_hub.c index 3fb7e14d106..2e054eb9353 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -174,8 +174,10 @@ static void usb_hub_power_on(struct usb_hub_device *hub) debug("enabling power on all ports\n"); for (i = 0; i < dev->maxchild; i++) { - usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_RESET); - debug("Reset : port %d returns %lX\n", i + 1, dev->status); + if (usb_hub_is_superspeed(dev)) { + usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_RESET); + debug("Reset : port %d returns %lX\n", i + 1, dev->status); + } usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); debug("PowerOn : port %d returns %lX\n", i + 1, dev->status); } diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 31f38bd3a5b..35707a65960 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -106,3 +107,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 38083586a3e..e5fcd8cc5b6 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 0be20045a97..1f43891d10b 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -33,7 +33,8 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load" +CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load" +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c80000 diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 457931faf21..a39b82d05a6 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c80000 diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index 59e9b3af846..f328af84dfa 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y @@ -82,3 +83,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig index a89494f9083..ec9331e625a 100644 --- a/configs/draco-etamin_defconfig +++ b/configs/draco-etamin_defconfig @@ -86,8 +86,10 @@ CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig index f4a9b860bf0..03fbe494901 100644 --- a/configs/draco-rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -84,8 +84,10 @@ CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig index cf2c46b3d20..fcc9b0380f4 100644 --- a/configs/draco-thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -84,8 +84,10 @@ CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig new file mode 100644 index 00000000000..bb41635ff78 --- /dev/null +++ b/configs/e850-96_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TEXT_BASE=0xf8800000 +CONFIG_SYS_MALLOC_LEN=0x81f000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ARCH_EXYNOS9=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000 +CONFIG_DEFAULT_DEVICE_TREE="exynos850-e850-96" +CONFIG_SYS_LOAD_ADDR=0x80000000 +# CONFIG_AUTOBOOT is not set +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_NET is not set +CONFIG_CLK_EXYNOS850=y +# CONFIG_MMC is not set +CONFIG_SOC_SAMSUNG=y +CONFIG_EXYNOS_PMU=y +CONFIG_EXYNOS_USI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_SYSCON=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index a5a4e362113..e21bea9d499 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" CONFIG_SPL_TEXT_BASE=0x10081000 CONFIG_ROCKCHIP_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK=0x10081fff CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x60800800 diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig index 0b7b4f2f627..bd99bf23f80 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -53,6 +54,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -61,6 +64,9 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y @@ -68,4 +74,12 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index 8f0a9c8c449..18a62b0033a 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_MMC=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y @@ -51,11 +51,14 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_MISC=y # CONFIG_ROCKCHIP_IODOMAIN is not set CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPL_PINCTRL=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 4220b9349b7..92bb5911765 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -104,3 +105,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/imx6dl_sielaff_defconfig b/configs/imx6dl_sielaff_defconfig new file mode 100644 index 00000000000..41574a41af1 --- /dev/null +++ b/configs/imx6dl_sielaff_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="imx6dl-sielaff" +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xF0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6S=y +CONFIG_TARGET_MX6S_SIELAFF=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sielaff" +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_LTO=y +CONFIG_FIT=y +CONFIG_SPL_FIT_PRINT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SPI_BOOT=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x20000 +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:-@0x0(rootfs)" +CONFIG_CMD_UBI=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_MDIO=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_SPL_USB_HOST=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 0db3ff890cd..a416ebc2e04 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -112,4 +112,5 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 7e9c48e224b..7cbc5d0e178 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -118,6 +118,7 @@ CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_GETTIME=y +CONFIG_CMD_KASLRSEED=y CONFIG_CMD_SYSBOOT=y CONFIG_CMD_UUID=y CONFIG_CMD_PMIC=y @@ -215,6 +216,7 @@ CONFIG_DM_REGULATOR_BD71837=y CONFIG_SPL_DM_REGULATOR_BD71837=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_RTC=y CONFIG_RTC_M41T62=y CONFIG_DM_SERIAL=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index fb4fb6707d5..048d39becdf 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -125,6 +125,7 @@ CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_GETTIME=y +CONFIG_CMD_KASLRSEED=y CONFIG_CMD_SYSBOOT=y CONFIG_CMD_UUID=y CONFIG_CMD_PMIC=y @@ -234,6 +235,7 @@ CONFIG_DM_REGULATOR_PCA9450=y CONFIG_SPL_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_RTC=y CONFIG_RTC_M41T62=y CONFIG_DM_SERIAL=y diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig new file mode 100644 index 00000000000..91a24c3456d --- /dev/null +++ b/configs/imx93-phyboard-segin_defconfig @@ -0,0 +1,138 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x20000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="phycore_imx93" +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-phyboard-segin" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_AHAB_BOOT=y +CONFIG_TARGET_PHYCORE_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x20519dd0 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x720000 +CONFIG_CMD_DEKBLOB=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" +CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051a000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_CLK_IMX93=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_GPIO_HOG=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig index cc0c5a79bc1..036f44d55d9 100644 --- a/configs/imx93_var_som_defconfig +++ b/configs/imx93_var_som_defconfig @@ -12,6 +12,7 @@ CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx93-var-som-symphony" CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_AHAB_BOOT=y CONFIG_TARGET_IMX93_VAR_SOM=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_SERIAL=y @@ -68,6 +69,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_READ=y +CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_SNTP=y @@ -94,6 +96,12 @@ CONFIG_SPL_CLK_IMX93=y CONFIG_CLK_IMX93=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y @@ -130,6 +138,14 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_PORT_AUTO=y CONFIG_ULP_WATCHDOG=y CONFIG_WDT=y CONFIG_LZO=y diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 8b5ce4e7358..086fc47ec27 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -10,21 +10,22 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20280000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000 CONFIG_ENV_OFFSET=0x80000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk" -CONFIG_SPL_TEXT_BASE=0x20209000 +CONFIG_SPL_TEXT_BASE=0x20002000 CONFIG_TARGET_IMXRT1050_EVK=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x20209000 +CONFIG_SYS_LOAD_ADDR=0x20002000 CONFIG_HAVE_SYS_UBOOT_START=y CONFIG_SYS_UBOOT_START=0x800023FD CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y +CONFIG_SPI_BOOT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 @@ -36,6 +37,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +CONFIG_SPL_NOR_SUPPORT=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig new file mode 100644 index 00000000000..4b252cfa5d0 --- /dev/null +++ b/configs/imxrt1050-evk_fspi_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_ARCH_IMXRT=y +CONFIG_TEXT_BASE=0x80002000 +CONFIG_SYS_MALLOC_LEN=0x40000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000 +CONFIG_ENV_OFFSET=0x80000 +CONFIG_IMX_CONFIG="board/freescale/imxrt1050-evk/imximage-nor.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk" +CONFIG_SPL_TEXT_BASE=0x20002000 +CONFIG_TARGET_IMXRT1050_EVK=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x20002000 +CONFIG_HAVE_SYS_UBOOT_START=y +CONFIG_SYS_UBOOT_START=0x800023FD +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SD_BOOT=y +CONFIG_SPI_BOOT=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +CONFIG_SPL_NOR_SUPPORT=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_USB=y +# CONFIG_CMD_MII is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_BLOCKSIZE=512 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +CONFIG_SPL_CLK_IMXRT1050=y +CONFIG_CLK_IMXRT1050=y +# CONFIG_SPL_DM_GPIO is not set +CONFIG_MXC_GPIO=y +# CONFIG_INPUT is not set +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMXRT=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_IMXRT_SDRAM=y +CONFIG_FSL_LPUART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LOGO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_BMP_16BPP=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_HEXDUMP=y +CONFIG_FSPI_CONF_HEADER=y +CONFIG_FSPI_CONF_FILE="fspi_header.bin" +CONFIG_READ_CLK_SOURCE=0x03 +CONFIG_DEVICE_TYPE=0x00 +CONFIG_FLASH_PAD_TYPE=0x08 +CONFIG_SERIAL_CLK_FREQUENCY=0x07 +CONFIG_FSPI_COL_ADDR_W=0x03 +CONFIG_FSPI_CONTROLLER_MISC=0x00000059 +CONFIG_FSPI_FLASH_A1_SIZE=0x04000000 +CONFIG_LUT_SEQUENCE="0xa0, 0x87, 0x18, 0x8b, 0x10, 0x8f, 0x06, 0xb3, 0x04, 0xa7" diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index 4b019fa2f30..3f061381f06 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -34,7 +34,8 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load" +CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load" +CONFIG_BOARD_LATE_INIT=y CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index b41c2660fff..ee62fe36d41 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_BOARD="vim3" CONFIG_SYS_CONFIG_NAME="khadas-vim3_android" CONFIG_ARCH_MESON=y CONFIG_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index 88197f5f5e9..cecbe506179 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_BOARD="vim3" CONFIG_SYS_CONFIG_NAME="khadas-vim3_android" CONFIG_ARCH_MESON=y CONFIG_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 3381d2e9270..ec4e0dc72e2 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_BOARD="vim3" CONFIG_SYS_CONFIG_NAME="khadas-vim3l_android" CONFIG_ARCH_MESON=y CONFIG_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index 3fa587ef1db..206f8defca6 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_BOARD="vim3" CONFIG_SYS_CONFIG_NAME="khadas-vim3l_android" CONFIG_ARCH_MESON=y CONFIG_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index d39533cc393..8d9c3b94499 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -104,3 +105,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index cb313a10a41..ed4f2ba5558 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_TEXT_BASE=0x10081000 CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK=0x10081fff CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x60800800 diff --git a/configs/lager_defconfig b/configs/lager_defconfig index da2ba58c6b0..d00314c60e4 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -106,3 +107,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig index bf1052db6f2..5688c7a64d1 100644 --- a/configs/msc_sm2s_imx8mp_defconfig +++ b/configs/msc_sm2s_imx8mp_defconfig @@ -5,7 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s" CONFIG_SPL_TEXT_BASE=0x920000 @@ -16,6 +17,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SYS_BOOT_GET_CMDLINE=y @@ -26,7 +28,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb" +CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s-ep1.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_SPL_MAX_SIZE=0x26000 @@ -62,6 +64,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y @@ -72,6 +76,7 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_LED=y CONFIG_LED_GPIO=y @@ -97,6 +102,7 @@ CONFIG_SPL_PMIC_RN5T567=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index d4de8df7b49..e2d3bc0b094 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -60,6 +60,8 @@ CONFIG_POWER_FSL=y CONFIG_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y @@ -67,3 +69,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index a90efe4a778..4afa61ce4d9 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_PCI=y +CONFIG_LTO=y +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=715766 CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y @@ -101,6 +104,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y @@ -127,3 +132,4 @@ CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig index 76099322092..26dcf3aae21 100644 --- a/configs/nanopc-t6-rk3588_defconfig +++ b/configs/nanopc-t6-rk3588_defconfig @@ -66,6 +66,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 833cff0e457..f5a472d03d7 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -58,8 +58,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 2736d382a35..99692d341f4 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -58,8 +58,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index d5301c630b2..a6549420c01 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -48,6 +48,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index b13c9b5db1b..b5739de147d 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -48,6 +48,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index ac4170d2e49..e1884df9dd2 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -102,6 +102,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y @@ -123,4 +125,5 @@ CONFIG_SPLASH_SOURCE=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig index a58f96d5779..e5325158d2a 100644 --- a/configs/orangepi-5-plus-rk3588_defconfig +++ b/configs/orangepi-5-plus-rk3588_defconfig @@ -69,6 +69,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index bcc38d51a7b..3a81ea7bd23 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -128,4 +128,5 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 519e0cfb3d4..c9555428390 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -27,7 +27,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" +CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 @@ -65,6 +65,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -85,6 +88,17 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x13000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1" +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set @@ -104,10 +118,14 @@ CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y @@ -120,4 +138,18 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_IMX_WATCHDOG=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 0a805deff65..a343c8e83de 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -104,3 +105,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig index 85af4c4ff95..bbbd2770f36 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00a00000 @@ -18,7 +19,9 @@ CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y @@ -39,20 +42,28 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -61,11 +72,27 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig new file mode 100644 index 00000000000..41aa0207086 --- /dev/null +++ b/configs/r8a779h0_grayhawk_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="r8a779h0-gray-hawk-u-boot" +CONFIG_RCAR_GEN4=y +CONFIG_TARGET_GRAYHAWK=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_SYS_CLK_FREQ=16666666 +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x58000000 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779h0-gray-hawk.dtb && booti 0x48080000 - 0x48000000" +CONFIG_DEFAULT_FDT_FILE="r8a779h0-gray-hawk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y +CONFIG_RENESAS_RAVB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_BAUDRATE=921600 +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig index 5a613abe0d2..fedb137877a 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -60,8 +60,6 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index c0375beffec..6dda900a9b4 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -76,6 +76,8 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig index efa7bcbdcda..10d6f658049 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -56,6 +56,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index a0678ff1290..76f57340df5 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -71,6 +71,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index fdc4b3d0ccc..711541f8462 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -89,6 +89,8 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 08bb30b1d7a..e4c4aef9a48 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_BCM283X=y -CONFIG_TEXT_BASE=0x00080000 +CONFIG_POSITION_INDEPENDENT=y CONFIG_TARGET_RPI_ARM64=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffe30 @@ -33,6 +33,7 @@ CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_MMC_SDHCI_BCMSTB=y CONFIG_BCMGENET=y CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 7c6b5b59c93..5f08ae0fcf9 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -106,3 +107,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/sonoff-ihost-rv1126_defconfig b/configs/sonoff-ihost-rv1126_defconfig new file mode 100644 index 00000000000..fe99bd92f9f --- /dev/null +++ b/configs/sonoff-ihost-rv1126_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_SYS_ARCH_TIMER=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost" +CONFIG_SYS_MONITOR_LEN=614400 +CONFIG_ROCKCHIP_RV1126=y +CONFIG_TARGET_RV1126_SONOFF_IHOST=y +CONFIG_DEBUG_UART_BASE=0xff570000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xe00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT_VERBOSE=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_DM_THERMAL=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 8fad272cf55..0375630adea 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -105,3 +106,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig index 289f2da775c..0d6c34d468e 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -75,6 +75,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 2601e55ebf5..f8e93bef4e7 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_TARGET_VEXPRESS_CA9X4=y CONFIG_TEXT_BASE=0x60800000 -CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60000f10 @@ -41,6 +41,7 @@ CONFIG_ARM_PL180_MMCI=y CONFIG_SYS_MMC_MAX_BLK_COUNT=127 CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_DM_SERIAL=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y CONFIG_FLASH_SHOW_PROGRESS=0 diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 72a123d9654..7a110350c2c 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index d9fbac986c8..58945a1cac9 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index 5f42243d22b..d78c9f80599 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single" CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index 4fa83faa401..b0567f857a3 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single" CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 371d14eb89b..0f1d990936f 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -146,3 +146,4 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 5f76a305ab3..3c55dd8dcde 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -153,3 +153,4 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 0dc6c5b6877..28b28f68411 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -224,3 +224,4 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 2742e38b599..1fcae45e95d 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -242,3 +242,4 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/doc/android/avb2.rst b/doc/android/avb2.rst index a072119574f..4aca7a5c660 100644 --- a/doc/android/avb2.rst +++ b/doc/android/avb2.rst @@ -38,16 +38,22 @@ AVB 2.0 U-Boot shell commands Provides CLI interface to invoke AVB 2.0 verification + misc. commands for different testing purposes:: - avb init <dev> - initialize avb 2.0 for <dev> - avb verify - run verification process using hash data from vbmeta structure + avb init <dev> - initialize avb 2 for <dev> avb read_rb <num> - read rollback index at location <num> avb write_rb <num> <rb> - write rollback index <rb> to <num> avb is_unlocked - returns unlock status of the device - avb get_uuid <partname> - read and print uuid of partition <partname> + avb get_uuid <partname> - read and print uuid of partition <part> avb read_part <partname> <offset> <num> <addr> - read <num> bytes from - partition <partname> to buffer <addr> + partition <partname> to buffer <addr> + avb read_part_hex <partname> <offset> <num> - read <num> bytes from + partition <partname> and print to stdout avb write_part <partname> <offset> <num> <addr> - write <num> bytes to - <partname> by <offset> using data from <addr> + <partname> by <offset> using data from <addr> + avb read_pvalue <name> <bytes> - read a persistent value <name> + avb write_pvalue <name> <value> - write a persistent value <name> + avb verify [slot_suffix] - run verification process using hash data + from vbmeta structure + [slot_suffix] - _a, _b, etc (if vbmeta partition is slotted) Partitions tampering (example) ------------------------------ diff --git a/doc/board/index.rst b/doc/board/index.rst index d0f9f355d2e..62357c99388 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc renesas/index rockchip/index samsung/index + sielaff/index siemens/index sifive/index sipeed/index diff --git a/doc/board/nxp/imxrt1050-evk.rst b/doc/board/nxp/imxrt1050-evk.rst index c1fb48f0cdd..e0cafe1035d 100644 --- a/doc/board/nxp/imxrt1050-evk.rst +++ b/doc/board/nxp/imxrt1050-evk.rst @@ -39,3 +39,33 @@ switch label numbers reference). The USB console connector is the one close the ethernet connector - Insert the micro SD card in the board, power it up and U-Boot messages should come up. + + +How to use U-Boot with SPI flash on NXP i.MXRT1050 EVK +------------------------------------------------------ + +- Build U-Boot for i.MXRT1050 EVK: + +.. code-block:: bash + + $ make mrproper + $ make imxrt1050-evk_fspi_defconfig + $ make + +This will generate SPL, uboot.img, fspi_header.bin, and the final image (flash.bin). + +To boot from SPI flash on other boards, you may need to change the flash header config, +which is specific to your flash chip, in Kconfig. +The flash config is 4K in size and is documented on page 217 of the imxrt1050 RM. +The default flash chip on the i.MXRT1050 EVK is the S26KS512SDPBHI02 HYPERFLASH. + +- Jumper settings:: + + SW7: 0 1 1 0 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + +- Use either JTAG or SWD to write `flash.bin` to the NOR. I used Mcuexpresso IDE's GUI flash tool. diff --git a/doc/board/nxp/imxrt1170-evk.rst b/doc/board/nxp/imxrt1170-evk.rst new file mode 100644 index 00000000000..86bd39ccb64 --- /dev/null +++ b/doc/board/nxp/imxrt1170-evk.rst @@ -0,0 +1,50 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +imxrt1170-evk +============= + +How to use U-Boot on NXP i.MXRT1170 EVK +--------------------------------------- + +- Build U-Boot for i.MXRT1170 EVK: + + .. code-block:: bash + + $ make mrproper + $ make imxrt1170-evk_defconfig + $ make + + This will generate the SPL image called SPL and the u-boot.img. + +- Flash the SPL image into the micro SD card: + + .. code-block:: bash + + $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync + + This location is not compatible with GPT partioning. Please, use MBR + partitioning instead. + +- Flash the u-boot.img image into the micro SD card: + + .. code-block:: bash + + $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync + +- Jumper settings + + .. list-table:: + :stub-columns: 1 + + * - SW1 + - 1 0 1 0 + * - SW2 + - 0 0 0 0 | 0 0 0 0 | 1 0 0 0 + + where 0 means bottom position and 1 means top position (from the + switch label numbers reference). + +- Connect the USB cable between the EVK and the PC for the console. + The USB console connector is the one close the ethernet connector + +- Insert the micro SD card in the board, power it up and U-Boot messages should come up. diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 3bd9ed3c873..94687730544 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -14,6 +14,7 @@ NXP Semiconductors imx93_11x11_evk imxrt1020-evk imxrt1050-evk + imxrt1170-evk ls1046ardb mx6sabreauto mx6sabresd diff --git a/doc/board/phytec/imx93-phyboard-segin.rst b/doc/board/phytec/imx93-phyboard-segin.rst new file mode 100644 index 00000000000..da8772ecd5c --- /dev/null +++ b/doc/board/phytec/imx93-phyboard-segin.rst @@ -0,0 +1,61 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +phyBOARD-Segin-i.MX93 +===================== + +U-Boot for the phyBOARD-Segin-i.MX93. + +Quick Start +----------- + +- Get and Build the ARM Trusted firmware +- Get the DDR firmware +- Get ahab-container.img +- Build U-Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.8 + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx93 bl31 + $ cp build/imx93/release/bl31.bin $(srctree) + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin + $ chmod +x firmware-imx-8.21.bin + $ ./firmware-imx-8.21.bin + $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree) + +Get ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin + $ chmod +x firmware-sentinel-0.10.bin + $ ./firmware-sentinel-0.10.bin + $ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree) + +Build U-Boot +------------ + +.. code-block:: bash + + $ make imx93-phyboard-segin_defconfig + $ make + +Burn the flash.bin to MicroSD card offset 32KB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index 965d40de4d4..fea0b076202 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -7,6 +7,7 @@ PHYTEC :maxdepth: 2 imx8mm-phygate-tauri-l + imx93-phyboard-segin phycore-am62x phycore-imx8mm phycore-imx8mp diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9fe69fc9422..e23ca4231cc 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -129,6 +129,7 @@ List of mainline supported Rockchip boards: * rv1126 - Edgeble Neural Compute Module 2 SoM - Neu2/Neu2k (neu2-io-r1126) + - Itead Sonoff iHost (sonoff-ihost-rv1126) Building -------- diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst new file mode 100644 index 00000000000..0cb95473e53 --- /dev/null +++ b/doc/board/samsung/e850-96.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Sam Protsenko <semen.protsenko@linaro.org> + +WinLink E850-96 board +===================== + +Overview +-------- + +WinLink's E850-96 board [1]_ is based on Samsung Exynos850 SoC and follows +96Boards Consumer Edition specification [2]_. That makes it possible to use +96Boards mezzanine boards [3]_ along with it. It's an open-hardware board and +the hardware design files [4]_ were published, along with the supported +software [5]_ and related documentation. + +U-Boot can be used on E850-96 instead of the original Samsung LittleKernel based +bootloader [6]_. Because FWBL1 [7]_ doesn't verify bootloader's signature, there +is no need to sign a U-Boot binary. That means U-Boot binary can be flashed into +``bootloader`` partition (instead of LittleKernel bootloader) and it will just +work. + +Because BL2 bootloader already sets up DRAM and runs the final bootloader +(U-Boot) from DRAM, there is no need in U-Boot SPL. It's enough to have only +U-Boot proper (``u-boot.bin``). + +Boot Flow +--------- + +The boot path for Exynos850 is shown on the figure below. + +.. image:: img/exynos850-boot-architecture.svg + :alt: Exynos850 SoC boot flow + +Legend: + +* ``BL0``: Boot ROM code +* ``BL1``: Software part of Boot ROM +* ``EPBL``: Exynos Primary Boot Loader +* ``BL2``: Initializes CMU and DRAM and runs the final bootloader +* ``Bootloader``: Final bootloader (e.g. U-Boot); also called BL33 in terms of + ARM boot flow +* ``EL3_MON``: EL3 monitor (trusted firmware, handles SMC calls); also called + BL31 in terms of ARM boot flow +* ``LDFW``: Loadable Firmware + +Build Procedure +--------------- + +.. warning:: + At the moment both eMMC and USB features are not enabled in U-Boot. Flashing + U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can + be used then to perform USB boot and flash LittleKernel bootloader binary [7]_ + to unbrick and revive the board. Flashing U-Boot binary might be helpful for + developers or anybody who want to check current state of U-Boot enablement on + E850-96 (which is mostly serial console and related blocks). + +Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain): + +.. prompt:: bash $ + + export PATH=<toolchain path>/bin:$PATH + export CROSS_COMPILE=<toolchain prefix> + make e850-96_defconfig + make + +Boot E850-96 board into fastboot mode as described in board software doc [9]_, +and flash U-Boot binary into ``bootloader`` eMMC partition: + +.. prompt:: bash $ + + fastboot flash bootloader u-boot.bin + fastboot reboot + +U-Boot will boot up to the shell. + +References +---------- + +.. [1] https://www.96boards.org/product/e850-96b/ +.. [2] https://www.96boards.org/products/ce/ +.. [3] https://www.96boards.org/products/mezzanine/ +.. [4] https://www.96boards.org/documentation/consumer/e850-96b/hardware-docs/ +.. [5] https://gitlab.com/Linaro/96boards/e850-96/ +.. [6] https://gitlab.com/Linaro/96boards/e850-96/lk +.. [7] https://gitlab.com/Linaro/96boards/e850-96/images +.. [8] https://gitlab.com/Linaro/96boards/e850-96/tools/dltool +.. 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00000000000..699079b3271 --- /dev/null +++ b/doc/board/sielaff/imx6dl-sielaff.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sielaff i.MX6 Solo Board +======================== + +The Sielaff i.MX6 Solo board is a control and Human Machine Interface (HMI) +board for vending machines. + +Quick Start +----------- + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + make imx6dl_sielaff_defconfig + make CROSS_COMPILE=arm-linux-gnueabi- + +Copy the flash.bin file to an SD card at an offset of 1 KiB: + +.. code-block:: bash + + dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 + +Boot +^^^^ + +Put the SD card in the slot on the board and apply power. diff --git a/doc/board/sielaff/index.rst b/doc/board/sielaff/index.rst new file mode 100644 index 00000000000..a8376484d88 --- /dev/null +++ b/doc/board/sielaff/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sielaff +======= + +.. toctree:: + :maxdepth: 2 + + imx6dl-sielaff diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index 6cb033ead04..abda8ac21bc 100644 --- a/doc/board/starfive/visionfive2.rst +++ b/doc/board/starfive/visionfive2.rst @@ -133,14 +133,14 @@ Sample boot log from StarFive VisionFive2 board Trying to boot from MMC2 OpenSBI v1.2-80-g4b28afc - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|___/_____| - | | - |_| + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| Platform Name : StarFive VisionFive 2 v1.3B Platform Features : medeleg diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst index b25bfbd271f..f6248cdcb1e 100644 --- a/doc/develop/codingstyle.rst +++ b/doc/develop/codingstyle.rst @@ -108,30 +108,29 @@ expected size, or that particular members appear at the right offset. Include files ------------- -You should follow this ordering in U-Boot. The common.h header (which is going -away at some point) should always be first, followed by other headers in order, -then headers with directories, then local files: +You should follow this ordering in U-Boot. In all cases, they should be listed +in alphabetical order. First comes headers which are located directly in our +top-level include diretory. This excludes the common.h header file which is to +be removed. Second are headers within subdirectories, Finally directory-local +includes should be listed. See this example: .. code-block:: C - #include <common.h> #include <bootstage.h> #include <dm.h> #include <others.h> #include <asm/...> - #include <arm/arch/...> + #include <asm/arch/...> #include <dm/device_compat.h> #include <linux/...> #include "local.h" -Within that order, sort your includes. - -It is important to include common.h first since it provides basic features used -by most files, e.g. CONFIG options. - For files that need to be compiled for the host (e.g. tools), you need to use -``#ifndef USE_HOSTCC`` to avoid including common.h since it includes a lot of -internal U-Boot things. See common/image.c for an example. +``#ifndef USE_HOSTCC`` to avoid including U-Boot specific include files. See +common/image.c for an example. + +If you encounter code which still uses <common.h> a patch to remove that and +replace it with any required include files directly is much appreciated. If your file uses driver model, include <dm.h> in the C file. Do not include dm.h in a header file. Try to use forward declarations (e.g. ``struct diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 4f18623b28e..1b2e1a290ce 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -66,9 +66,9 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2024.01-rc1 was released on Mon 29 January 2024. -.. * U-Boot v2024.01-rc2 was released on Mon 12 February 2024. +* U-Boot v2024.01-rc2 was released on Tue 13 February 2024. -.. * U-Boot v2024.01-rc3 was released on Mon 26 February 2024. +* U-Boot v2024.01-rc3 was released on Mon 26 February 2024. .. * U-Boot v2024.01-rc4 was released on Mon 11 March 2024. diff --git a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml new file mode 100644 index 00000000000..a0906efe122 --- /dev/null +++ b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml @@ -0,0 +1,307 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos850 SoC clock controller + +maintainers: + - Sam Protsenko <semen.protsenko@linaro.org> + +description: | + Exynos850 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external + clocks must be defined as fixed-rate clocks in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos850.h' header. + +properties: + compatible: + enum: + - samsung,exynos850-cmu-top + - samsung,exynos850-cmu-apm + - samsung,exynos850-cmu-aud + - samsung,exynos850-cmu-cmgp + - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d + - samsung,exynos850-cmu-hsi + - samsung,exynos850-cmu-is + - samsung,exynos850-cmu-mfcmscl + - samsung,exynos850-cmu-peri + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-apm + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_APM bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_apm_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-aud + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: AUD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_aud + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CMGP bus clock (from CMU_APM) + + clock-names: + items: + - const: oscclk + - const: gout_clkcmu_cmgp_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + - description: CCI clock (from CMU_TOP) + - description: eMMC clock (from CMU_TOP) + - description: SSS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_core_bus + - const: dout_core_cci + - const: dout_core_mmc_embd + - const: dout_core_sss + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-dpu + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: DPU clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_dpu + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_g3d_switch + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-hsi + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: External RTC clock (32768 Hz) + - description: CMU_HSI bus clock (from CMU_TOP) + - description: SD card clock (from CMU_TOP) + - description: USB 2.0 DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: rtcclk + - const: dout_hsi_bus + - const: dout_hsi_mmc_card + - const: dout_hsi_usb20drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-is + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_IS bus clock (from CMU_TOP) + - description: Image Texture Processing core clock (from CMU_TOP) + - description: Visual Recognition Accelerator clock (from CMU_TOP) + - description: Geometric Distortion Correction clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_is_bus + - const: dout_is_itp + - const: dout_is_vra + - const: dout_is_gdc + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-mfcmscl + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: Multi-Format Codec clock (from CMU_TOP) + - description: Memory to Memory Scaler clock (from CMU_TOP) + - description: Multi-Channel Scaler clock (from CMU_TOP) + - description: JPEG codec clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_mfcmscl_mfc + - const: dout_mfcmscl_m2m + - const: dout_mfcmscl_mcsc + - const: dout_mfcmscl_jpeg + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_TOP) + - description: UART clock (from CMU_TOP) + - description: Parent clock for HSI2C and SPI (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_peri_bus + - const: dout_peri_uart + - const: dout_peri_ip + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_PERI + - | + #include <dt-bindings/clock/exynos850.h> + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos850-cmu-peri"; + reg = <0x10030000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names = "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + +... diff --git a/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml new file mode 100644 index 00000000000..c3e95c33b01 --- /dev/null +++ b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Power Management Unit (PMU) + +maintainers: + - Sam Protsenko <semen.protsenko@linaro.org> + +description: |+ + PMU block controls the power and operation states of Exynos SoC. It contains + registers for changing the state of next features:: + + - Local power control. Exynos SoCs have various power domains, and it's + possible to turn them on and off independently, using corresponding + registers in PMU block + - System-level power control. That allows putting the system into power-down + modes (sleep) by turning off the power for most of the domains + - Miscellaneous PMU related features + +# Custom select to avoid matching all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - samsung,exynos850-pmu + required: + - compatible + +properties: + compatible: + oneOf: + - items: + - enum: + - samsung,exynos850-pmu + - const: syscon + + reg: + maxItems: 1 + + samsung,uart-debug-1: + type: boolean + description: + Enable this property if AP UART lines (Application Processor UART) must be + connected to UART_DEBUG_1 path in PMU block. That's usually needed when + the serial console is provided by uart1_pins. If this property is not + specified, the default behavior will be used (AP UART lines connected to + UART_DEBUG_0 path, which usually means uart0_pins are used for the serial + console). + + syscon-poweroff: + $ref: /schemas/power/reset/syscon-poweroff.yaml# + type: object + description: + Node for power off method + + syscon-reboot: + $ref: /schemas/power/reset/syscon-reboot.yaml# + type: object + description: + Node for reboot method + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmu_system_controller: system-controller@11860000 { + compatible = "samsung,exynos850-pmu", "syscon"; + reg = <0x11860000 0x10000>; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ + mask = <0x2>; /* SWRESET_SYSTEM */ + value = <0x2>; /* reset value */ + }; + }; diff --git a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml new file mode 100644 index 00000000000..8e6423f1156 --- /dev/null +++ b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung's Exynos USI (Universal Serial Interface) + +maintainers: + - Sam Protsenko <semen.protsenko@linaro.org> + +description: | + USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). + USI shares almost all internal circuits within each protocol, so only one + protocol can be chosen at a time. USI is modeled as a node with zero or more + child nodes, each representing a serial sub-node device. The mode setting + selects which particular function will be used. + +properties: + $nodename: + pattern: "^usi@[0-9a-f]+$" + + compatible: + enum: + - samsung,exynos850-usi + + reg: true + + clocks: true + + clock-names: true + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register syscon node + - description: offset of SW_CONF register for this USI controller + description: + Should be phandle/offset pair. The phandle to System Register syscon node + (for the same domain where this USI controller resides) and the offset + of SW_CONF register for this USI controller. + + samsung,mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects USI function (which serial protocol to use). Refer to + <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values. + + samsung,clkreq-on: + type: boolean + description: + Enable this property if underlying protocol requires the clock to be + continuously provided without automatic gating. As suggested by SoC + manual, it should be set in case of SPI/I2C slave, UART Rx and I2C + multi-master mode. Usually this property is needed if USI mode is set + to "UART". + + This property is optional. + +patternProperties: + "^i2c@[0-9a-f]+$": + $ref: /schemas/i2c/i2c-exynos5.yaml + description: Child node describing underlying I2C + + "^serial@[0-9a-f]+$": + $ref: /schemas/serial/samsung_uart.yaml + description: Child node describing underlying UART/serial + + "^spi@[0-9a-f]+$": + $ref: /schemas/spi/samsung,spi.yaml + description: Child node describing underlying SPI + +required: + - compatible + - ranges + - "#address-cells" + - "#size-cells" + - samsung,sysreg + - samsung,mode + +if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-usi + +then: + properties: + reg: + maxItems: 1 + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI/I2C protocol + + clock-names: + items: + - const: pclk + - const: ipclk + + required: + - reg + - clocks + - clock-names + +else: + properties: + reg: false + clocks: false + clock-names: false + samsung,clkreq-on: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/soc/samsung,exynos-usi.h> + + usi0: usi@138200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138200c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1010>; + samsung,mode = <USI_V2_UART>; + samsung,clkreq-on; /* needed for UART mode */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "pclk", "ipclk"; + + serial_0: serial@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0xc0>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + hsi2c_0: i2c@13820000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x13820000 0xc0>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peri 31>, <&cmu_peri 32>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 82b6ea7b6e7..ebf75fa948a 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -190,6 +190,10 @@ bootm_size bootstopkeysha256, bootdelaykey, bootstopkey See README.autoboot +button_cmd_0, button_cmd_0_name ... button_cmd_N, button_cmd_N_name + Used to map commands to run when a button is held during boot. + See CONFIG_BUTTON_CMD. + updatefile Location of the software update file on a TFTP server, used by the automatic software update feature. Please refer to diff --git a/drivers/block/host_dev.c b/drivers/block/host_dev.c index 30c74157934..52313435a0c 100644 --- a/drivers/block/host_dev.c +++ b/drivers/block/host_dev.c @@ -61,6 +61,7 @@ static int host_sb_attach_file(struct udevice *dev, const char *filename) if (size % desc->blksz) { printf("The size of host backing file '%s' is not multiple of " "the device block size\n", filename); + ret = -EINVAL; goto err_fname; } desc->lba = size / desc->blksz; diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c index 34a976d1e6c..bad445efa86 100644 --- a/drivers/button/button-qcom-pmic.c +++ b/drivers/button/button-qcom-pmic.c @@ -86,7 +86,7 @@ static int qcom_pwrkey_probe(struct udevice *dev) } ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE); - if ((ret & 0x7) == 0) { + if (ret < 0 || (ret & 0x7) == 0) { printf("%s: unexpected PMCI function subtype %d\n", dev->name, ret); return -ENXIO; } @@ -133,7 +133,7 @@ static int button_qcom_pmic_bind(struct udevice *parent) } else if (NODE_IS_RESIN(node)) { uc_plat->label = "vol_down"; } else { - printf("Unknown button node '%s' should be 'pwrkey' or 'resin'\n", + debug("Unknown button node '%s' should be 'pwrkey' or 'resin'\n", ofnode_get_name(node)); device_unbind(dev); } diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig index eb0efa97d15..85ce9d6e241 100644 --- a/drivers/clk/exynos/Kconfig +++ b/drivers/clk/exynos/Kconfig @@ -15,4 +15,11 @@ config CLK_EXYNOS7420 This enables common clock driver support for platforms based on Samsung Exynos7420 SoC. +config CLK_EXYNOS850 + bool "Clock driver for Samsung's Exynos850 SoC" + select CLK_CCF + help + This enables common clock driver support for platforms based + on Samsung Exynos850 SoC. + endmenu diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile index c9f29c873e9..734100e2bff 100644 --- a/drivers/clk/exynos/Makefile +++ b/drivers/clk/exynos/Makefile @@ -1,7 +1,12 @@ # SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2016 Samsung Electronics -# Thomas Abraham <thomas.ab@samsung.com> +# Copyright (C) 2023 Linaro Ltd. +# +# Authors: +# Thomas Abraham <thomas.ab@samsung.com> +# Sam Protsenko <semen.protsenko@linaro.org> -obj-y += clk-pll.o -obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o +obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o +obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o +obj-$(CONFIG_CLK_EXYNOS850) += clk-exynos850.o diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 7d869eb02b8..9caa932e12f 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -10,8 +10,15 @@ #include <errno.h> #include <clk-uclass.h> #include <asm/io.h> +#include <div64.h> #include <dt-bindings/clock/exynos7420-clk.h> -#include "clk-pll.h" + +#define PLL145X_MDIV_SHIFT 16 +#define PLL145X_MDIV_MASK 0x3ff +#define PLL145X_PDIV_SHIFT 8 +#define PLL145X_PDIV_MASK 0x3f +#define PLL145X_SDIV_SHIFT 0 +#define PLL145X_SDIV_MASK 0x7 #define DIVIDER(reg, shift, mask) \ (((readl(reg) >> shift) & mask) + 1) @@ -64,6 +71,22 @@ struct exynos7420_clk_top0_priv { unsigned long sclk_uart2; }; +static unsigned long pll145x_get_rate(unsigned int *con1, + unsigned long fin_freq) +{ + unsigned long pll_con1 = readl(con1); + unsigned long mdiv, sdiv, pdiv; + u64 fvco = fin_freq; + + mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; + pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK; + sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + return (unsigned long)fvco; +} + static ulong exynos7420_topc_get_rate(struct clk *clk) { struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev); diff --git a/drivers/clk/exynos/clk-exynos850.c b/drivers/clk/exynos/clk-exynos850.c new file mode 100644 index 00000000000..cf94a3e1b64 --- /dev/null +++ b/drivers/clk/exynos/clk-exynos850.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung Exynos850 clock driver. + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + */ + +#include <dm.h> +#include <asm/io.h> +#include <dt-bindings/clock/exynos850.h> +#include "clk.h" + +/* ---- CMU_TOP ------------------------------------------------------------- */ + +/* Register Offset definitions for CMU_TOP (0x120e0000) */ +#define PLL_CON0_PLL_MMC 0x0100 +#define PLL_CON3_PLL_MMC 0x010c +#define PLL_CON0_PLL_SHARED0 0x0140 +#define PLL_CON3_PLL_SHARED0 0x014c +#define PLL_CON0_PLL_SHARED1 0x0180 +#define PLL_CON3_PLL_SHARED1 0x018c +#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 +#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c +#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 +#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 + +static const struct samsung_pll_clock top_pure_pll_clks[] = { + PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk", + PLL_CON3_PLL_SHARED0), + PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk", + PLL_CON3_PLL_SHARED1), + PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk", + PLL_CON3_PLL_MMC), +}; + +/* List of parent clocks for Muxes in CMU_TOP */ +PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" }; +PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" }; +PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ +PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; +PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4", + "dout_shared1_div4", "clock-oscclk" }; +PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4", + "dout_shared1_div4", "clock-oscclk" }; + +static const struct samsung_mux_clock top_pure_mux_clks[] = { + MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, + PLL_CON0_PLL_SHARED0, 4, 1), + MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, + PLL_CON0_PLL_SHARED1, 4, 1), + MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, + PLL_CON0_PLL_MMC, 4, 1), +}; + +static const struct samsung_mux_clock top_peri_mux_clks[] = { + MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), + MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), + MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), +}; + +static const struct samsung_div_clock top_pure_div_clks[] = { + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), +}; + +static const struct samsung_div_clock top_peri_div_clks[] = { + DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", + CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), + DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", + CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), + DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", + CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), +}; + +static const struct samsung_gate_clock top_peri_gate_clks[] = { + GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", + CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), + GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", + CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), + GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", + CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), +}; + +static const struct samsung_clk_group top_cmu_clks[] = { + /* CMU_TOP_PURECLKCOMP */ + { S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) }, + { S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) }, + { S_CLK_DIV, top_pure_div_clks, ARRAY_SIZE(top_pure_div_clks) }, + + /* CMU_TOP clocks for CMU_PERI */ + { S_CLK_MUX, top_peri_mux_clks, ARRAY_SIZE(top_peri_mux_clks) }, + { S_CLK_GATE, top_peri_gate_clks, ARRAY_SIZE(top_peri_gate_clks) }, + { S_CLK_DIV, top_peri_div_clks, ARRAY_SIZE(top_peri_div_clks) }, +}; + +static int exynos850_cmu_top_probe(struct udevice *dev) +{ + return samsung_cmu_register_one(dev, top_cmu_clks, + ARRAY_SIZE(top_cmu_clks)); +} + +static const struct udevice_id exynos850_cmu_top_ids[] = { + { .compatible = "samsung,exynos850-cmu-top" }, + { } +}; + +U_BOOT_DRIVER(exynos850_cmu_top) = { + .name = "exynos850-cmu-top", + .id = UCLASS_CLK, + .of_match = exynos850_cmu_top_ids, + .ops = &ccf_clk_ops, + .probe = exynos850_cmu_top_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* ---- CMU_PERI ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_PERI (0x10030000) */ +#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 +#define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 +#define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac + +/* List of parent clocks for Muxes in CMU_PERI */ +PNAME(mout_peri_bus_user_p) = { "clock-oscclk", "dout_peri_bus" }; +PNAME(mout_peri_uart_user_p) = { "clock-oscclk", "dout_peri_uart" }; + +static const struct samsung_mux_clock peri_mux_clks[] = { + MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, + PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", + mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), +}; + +static const struct samsung_gate_clock peri_gate_clks[] = { + GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", + CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), + GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), +}; + +static const struct samsung_clk_group peri_cmu_clks[] = { + { S_CLK_MUX, peri_mux_clks, ARRAY_SIZE(peri_mux_clks) }, + { S_CLK_GATE, peri_gate_clks, ARRAY_SIZE(peri_gate_clks) }, +}; + +static int exynos850_cmu_peri_probe(struct udevice *dev) +{ + return samsung_register_cmu(dev, peri_cmu_clks, exynos850_cmu_top); +} + +static const struct udevice_id exynos850_cmu_peri_ids[] = { + { .compatible = "samsung,exynos850-cmu-peri" }, + { } +}; + +U_BOOT_DRIVER(exynos850_cmu_peri) = { + .name = "exynos850-cmu-peri", + .id = UCLASS_CLK, + .of_match = exynos850_cmu_peri_ids, + .ops = &ccf_clk_ops, + .probe = exynos850_cmu_peri_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c index 407fc71d415..4aacbc26b25 100644 --- a/drivers/clk/exynos/clk-pll.c +++ b/drivers/clk/exynos/clk-pll.c @@ -1,32 +1,167 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Exynos PLL helper functions for clock drivers. * Copyright (C) 2016 Samsung Electronics - * Thomas Abraham <thomas.ab@samsung.com> + * Copyright (C) 2023 Linaro Ltd. + * + * Authors: + * Thomas Abraham <thomas.ab@samsung.com> + * Sam Protsenko <semen.protsenko@linaro.org> + * + * This file contains the utility functions to register the pll clocks. */ -#include <common.h> #include <asm/io.h> #include <div64.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <clk.h> +#include "clk.h" -#define PLL145X_MDIV_SHIFT 16 -#define PLL145X_MDIV_MASK 0x3ff -#define PLL145X_PDIV_SHIFT 8 -#define PLL145X_PDIV_MASK 0x3f -#define PLL145X_SDIV_SHIFT 0 -#define PLL145X_SDIV_MASK 0x7 +#define UBOOT_DM_CLK_SAMSUNG_PLL0822X "samsung_clk_pll0822x" +#define UBOOT_DM_CLK_SAMSUNG_PLL0831X "samsung_clk_pll0831x" -unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) +struct samsung_clk_pll { + struct clk clk; + void __iomem *con_reg; + enum samsung_pll_type type; +}; + +#define to_clk_pll(_clk) container_of(_clk, struct samsung_clk_pll, clk) + +/* + * PLL0822x Clock Type + */ + +#define PLL0822X_MDIV_MASK 0x3ff +#define PLL0822X_PDIV_MASK 0x3f +#define PLL0822X_SDIV_MASK 0x7 +#define PLL0822X_MDIV_SHIFT 16 +#define PLL0822X_PDIV_SHIFT 8 +#define PLL0822X_SDIV_SHIFT 0 + +static unsigned long samsung_pll0822x_recalc_rate(struct clk *clk) { - unsigned long pll_con1 = readl(con1); - unsigned long mdiv, sdiv, pdiv; - uint64_t fvco = fin_freq; + struct samsung_clk_pll *pll = to_clk_pll(clk); + u32 mdiv, pdiv, sdiv, pll_con3; + u64 fvco = clk_get_parent_rate(clk); - mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; - pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK; - sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; + pll_con3 = readl_relaxed(pll->con_reg); + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; + pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; + sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; fvco *= mdiv; do_div(fvco, (pdiv << sdiv)); return (unsigned long)fvco; } + +static const struct clk_ops samsung_pll0822x_clk_min_ops = { + .get_rate = samsung_pll0822x_recalc_rate, +}; + +/* + * PLL0831x Clock Type + */ + +#define PLL0831X_KDIV_MASK 0xffff +#define PLL0831X_MDIV_MASK 0x1ff +#define PLL0831X_PDIV_MASK 0x3f +#define PLL0831X_SDIV_MASK 0x7 +#define PLL0831X_MDIV_SHIFT 16 +#define PLL0831X_PDIV_SHIFT 8 +#define PLL0831X_SDIV_SHIFT 0 +#define PLL0831X_KDIV_SHIFT 0 + +static unsigned long samsung_pll0831x_recalc_rate(struct clk *clk) +{ + struct samsung_clk_pll *pll = to_clk_pll(clk); + u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; + s16 kdiv; + u64 fvco = clk_get_parent_rate(clk); + + pll_con3 = readl_relaxed(pll->con_reg); + pll_con5 = readl_relaxed(pll->con_reg + 8); + mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK; + pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK; + sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK; + kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK); + + fvco *= (mdiv << 16) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>= 16; + + return (unsigned long)fvco; +} + +static const struct clk_ops samsung_pll0831x_clk_min_ops = { + .get_rate = samsung_pll0831x_recalc_rate, +}; + +static struct clk *_samsung_clk_register_pll(void __iomem *base, + const struct samsung_pll_clock *pll_clk) +{ + struct samsung_clk_pll *pll; + struct clk *clk; + const char *drv_name; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->con_reg = base + pll_clk->con_offset; + pll->type = pll_clk->type; + clk = &pll->clk; + clk->flags = pll_clk->flags; + + switch (pll_clk->type) { + case pll_0822x: + drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0822X; + break; + case pll_0831x: + drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0831X; + break; + default: + kfree(pll); + return ERR_PTR(-ENODEV); + } + + ret = clk_register(clk, drv_name, pll_clk->name, pll_clk->parent_name); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + return clk; +} + +void samsung_clk_register_pll(void __iomem *base, + const struct samsung_pll_clock *clk_list, + unsigned int nr_clk) +{ + unsigned int cnt; + + for (cnt = 0; cnt < nr_clk; cnt++) { + struct clk *clk; + const struct samsung_pll_clock *pll_clk; + + pll_clk = &clk_list[cnt]; + clk = _samsung_clk_register_pll(base, pll_clk); + clk_dm(pll_clk->id, clk); + } +} + +U_BOOT_DRIVER(samsung_pll0822x_clk) = { + .name = UBOOT_DM_CLK_SAMSUNG_PLL0822X, + .id = UCLASS_CLK, + .ops = &samsung_pll0822x_clk_min_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(samsung_pll0831x_clk) = { + .name = UBOOT_DM_CLK_SAMSUNG_PLL0831X, + .id = UCLASS_CLK, + .ops = &samsung_pll0831x_clk_min_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h index 7b7af5e6761..bd79309fa1c 100644 --- a/drivers/clk/exynos/clk-pll.h +++ b/drivers/clk/exynos/clk-pll.h @@ -1,13 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Exynos PLL helper functions for clock drivers. * Copyright (C) 2016 Samsung Electronics - * Thomas Abraham <thomas.ab@samsung.com> + * Copyright (C) 2023 Linaro Ltd. + * + * Authors: + * Thomas Abraham <thomas.ab@samsung.com> + * Sam Protsenko <semen.protsenko@linaro.org> + * + * Common Clock Framework support for all PLL's in Samsung platforms. */ #ifndef __EXYNOS_CLK_PLL_H #define __EXYNOS_CLK_PLL_H -unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq); +#include <linux/clk-provider.h> + +enum samsung_pll_type { + pll_0822x, + pll_0831x, +}; #endif /* __EXYNOS_CLK_PLL_H */ diff --git a/drivers/clk/exynos/clk.c b/drivers/clk/exynos/clk.c new file mode 100644 index 00000000000..430767f072d --- /dev/null +++ b/drivers/clk/exynos/clk.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + * + * This file includes utility functions to register clocks to common + * clock framework for Samsung platforms. + */ + +#include <dm.h> +#include "clk.h" + +void samsung_clk_register_mux(void __iomem *base, + const struct samsung_mux_clock *clk_list, + unsigned int nr_clk) +{ + unsigned int cnt; + + for (cnt = 0; cnt < nr_clk; cnt++) { + struct clk *clk; + const struct samsung_mux_clock *m; + + m = &clk_list[cnt]; + clk = clk_register_mux(NULL, m->name, m->parent_names, + m->num_parents, m->flags, base + m->offset, m->shift, + m->width, m->mux_flags); + clk_dm(m->id, clk); + } +} + +void samsung_clk_register_div(void __iomem *base, + const struct samsung_div_clock *clk_list, + unsigned int nr_clk) +{ + unsigned int cnt; + + for (cnt = 0; cnt < nr_clk; cnt++) { + struct clk *clk; + const struct samsung_div_clock *d; + + d = &clk_list[cnt]; + clk = clk_register_divider(NULL, d->name, d->parent_name, + d->flags, base + d->offset, d->shift, + d->width, d->div_flags); + clk_dm(d->id, clk); + } +} + +void samsung_clk_register_gate(void __iomem *base, + const struct samsung_gate_clock *clk_list, + unsigned int nr_clk) +{ + unsigned int cnt; + + for (cnt = 0; cnt < nr_clk; cnt++) { + struct clk *clk; + const struct samsung_gate_clock *g; + + g = &clk_list[cnt]; + clk = clk_register_gate(NULL, g->name, g->parent_name, + g->flags, base + g->offset, g->bit_idx, + g->gate_flags, NULL); + clk_dm(g->id, clk); + } +} + +typedef void (*samsung_clk_register_fn)(void __iomem *base, + const void *clk_list, + unsigned int nr_clk); + +static const samsung_clk_register_fn samsung_clk_register_fns[] = { + [S_CLK_MUX] = (samsung_clk_register_fn)samsung_clk_register_mux, + [S_CLK_DIV] = (samsung_clk_register_fn)samsung_clk_register_div, + [S_CLK_GATE] = (samsung_clk_register_fn)samsung_clk_register_gate, + [S_CLK_PLL] = (samsung_clk_register_fn)samsung_clk_register_pll, +}; + +/** + * samsung_cmu_register_clocks() - Register provided clock groups + * @base: Base address of CMU registers + * @clk_groups: list of clock groups + * @nr_groups: count of clock groups in @clk_groups + * + * Having the array of clock groups @clk_groups makes it possible to keep a + * correct clocks registration order. + */ +void samsung_cmu_register_clocks(void __iomem *base, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups) +{ + unsigned int i; + + for (i = 0; i < nr_groups; i++) { + const struct samsung_clk_group *g = &clk_groups[i]; + + samsung_clk_register_fns[g->type](base, g->clk_list, g->nr_clk); + } +} + +/** + * samsung_cmu_register_one - Register all CMU clocks + * @dev: CMU device + * @clk_groups: list of CMU clock groups + * @nr_groups: count of CMU clock groups in @clk_groups + * + * Return: 0 on success or negative value on error. + */ +int samsung_cmu_register_one(struct udevice *dev, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups) +{ + void __iomem *base; + + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + samsung_cmu_register_clocks(base, clk_groups, nr_groups); + + return 0; +} diff --git a/drivers/clk/exynos/clk.h b/drivers/clk/exynos/clk.h new file mode 100644 index 00000000000..91a51b877a6 --- /dev/null +++ b/drivers/clk/exynos/clk.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + * + * Common Clock Framework support for all Samsung platforms. + */ + +#ifndef __EXYNOS_CLK_H +#define __EXYNOS_CLK_H + +#include <errno.h> +#include <linux/clk-provider.h> +#include "clk-pll.h" + +/** + * struct samsung_mux_clock - information about mux clock + * @id: platform specific id of the clock + * @name: name of this mux clock + * @parent_names: array of pointer to parent clock names + * @num_parents: number of parents listed in @parent_names + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the mux + * @shift: starting bit location of the mux control bit-field in @reg + * @width: width of the mux control bit-field in @reg + * @mux_flags: flags for mux-type clock + */ +struct samsung_mux_clock { + unsigned int id; + const char *name; + const char * const *parent_names; + u8 num_parents; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 mux_flags; +}; + +#define PNAME(x) static const char * const x[] + +#define __MUX(_id, cname, pnames, o, s, w, f, mf) \ + { \ + .id = _id, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = (f) | CLK_SET_RATE_NO_REPARENT, \ + .offset = o, \ + .shift = s, \ + .width = w, \ + .mux_flags = mf, \ + } + +#define MUX(_id, cname, pnames, o, s, w) \ + __MUX(_id, cname, pnames, o, s, w, 0, 0) + +#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ + __MUX(_id, cname, pnames, o, s, w, f, mf) + +/** + * struct samsung_div_clock - information about div clock + * @id: platform specific id of the clock + * @name: name of this div clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the div + * @shift: starting bit location of the div control bit-field in @reg + * @width: width of the bitfield + * @div_flags: flags for div-type clock + */ +struct samsung_div_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 div_flags; +}; + +#define __DIV(_id, cname, pname, o, s, w, f, df) \ + { \ + .id = _id, \ + .name = cname, \ + .parent_name = pname, \ + .flags = f, \ + .offset = o, \ + .shift = s, \ + .width = w, \ + .div_flags = df, \ + } + +#define DIV(_id, cname, pname, o, s, w) \ + __DIV(_id, cname, pname, o, s, w, 0, 0) + +#define DIV_F(_id, cname, pname, o, s, w, f, df) \ + __DIV(_id, cname, pname, o, s, w, f, df) + +/** + * struct samsung_gate_clock - information about gate clock + * @id: platform specific id of the clock + * @name: name of this gate clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the gate + * @bit_idx: bit index of the gate control bit-field in @reg + * @gate_flags: flags for gate-type clock + */ +struct samsung_gate_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 bit_idx; + u8 gate_flags; +}; + +#define __GATE(_id, cname, pname, o, b, f, gf) \ + { \ + .id = _id, \ + .name = cname, \ + .parent_name = pname, \ + .flags = f, \ + .offset = o, \ + .bit_idx = b, \ + .gate_flags = gf, \ + } + +#define GATE(_id, cname, pname, o, b, f, gf) \ + __GATE(_id, cname, pname, o, b, f, gf) + +/** + * struct samsung_pll_clock - information about pll clock + * @id: platform specific id of the clock + * @name: name of this pll clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @con_offset: offset of the register for configuring the PLL + * @type: type of PLL to be registered + */ +struct samsung_pll_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + int con_offset; + enum samsung_pll_type type; +}; + +#define PLL(_typ, _id, _name, _pname, _con) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .flags = CLK_GET_RATE_NOCACHE, \ + .con_offset = _con, \ + .type = _typ, \ + } + +enum samsung_clock_type { + S_CLK_MUX, + S_CLK_DIV, + S_CLK_GATE, + S_CLK_PLL, +}; + +/** + * struct samsung_clock_group - contains a list of clocks of one type + * @type: type of clocks this structure contains + * @clk_list: list of clocks + * @nr_clk: count of clocks in @clk_list + */ +struct samsung_clk_group { + enum samsung_clock_type type; + const void *clk_list; + unsigned int nr_clk; +}; + +void samsung_clk_register_mux(void __iomem *base, + const struct samsung_mux_clock *clk_list, + unsigned int nr_clk); +void samsung_clk_register_div(void __iomem *base, + const struct samsung_div_clock *clk_list, + unsigned int nr_clk); +void samsung_clk_register_gate(void __iomem *base, + const struct samsung_gate_clock *clk_list, + unsigned int nr_clk); +void samsung_clk_register_pll(void __iomem *base, + const struct samsung_pll_clock *clk_list, + unsigned int nr_clk); + +void samsung_cmu_register_clocks(void __iomem *base, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups); +int samsung_cmu_register_one(struct udevice *dev, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups); + +/** + * samsung_register_cmu - Register CMU clocks ensuring parent CMU is present + * @dev: CMU device + * @clk_groups: list of CMU clock groups + * @parent_drv: name of parent CMU driver + * + * Register provided CMU clocks, but make sure CMU_TOP driver is instantiated + * first. + * + * Return: 0 on success or negative value on error. + */ +#define samsung_register_cmu(dev, clk_groups, parent_drv) \ +({ \ + struct udevice *__parent; \ + int __ret; \ + \ + __ret = uclass_get_device_by_driver(UCLASS_CLK, \ + DM_DRIVER_GET(parent_drv), &__parent); \ + if (__ret || !__parent) \ + __ret = -ENOENT; \ + else \ + __ret = samsung_cmu_register_one(dev, clk_groups, \ + ARRAY_SIZE(clk_groups)); \ + __ret; \ +}) + +#endif /* __EXYNOS_CLK_H */ diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 927d62cf99a..e9296ed9fe2 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -151,6 +151,12 @@ config CLK_R8A779G0 help Enable this to support the clocks on Renesas R8A779G0 SoC. +config CLK_R8A779H0 + bool "Renesas R8A779H0 clock driver" + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A779H0 SoC. + config CLK_R9A06G032 bool "Renesas R9A06G032 clock driver" depends on CLK_RENESAS diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index df7e225e9ca..6c742553091 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o +obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 66ffef96b69..89f2d966746 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -298,6 +298,15 @@ int gen2_clk_probe(struct udevice *dev) if (!priv->cpg_pll_config->extal_div) return -EINVAL; + if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { + priv->info->status_regs = mstpsr; + priv->info->control_regs = smstpcr; + priv->info->reset_regs = srcr; + priv->info->reset_clear_regs = srstclr; + } else { + return -EINVAL; + } + ret = clk_get_by_name(dev, "extal", &priv->clk_extal); if (ret < 0) return ret; diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 196903e406c..b84024266f4 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -306,6 +306,12 @@ static u64 gen3_clk_get_rate64(struct clk *clk) gen4_pll_config->pll6_div, "PLL6"); + case CLK_TYPE_GEN4_PLL7: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, + 0, gen4_pll_config->pll7_mult, + gen4_pll_config->pll7_div, + "PLL7"); + case CLK_TYPE_FF: return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, 0, core->mult, core->div, diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c new file mode 100644 index 00000000000..502b20b554a --- /dev/null +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a779h0 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2023 Renesas Electronics Corp. + * + * Based on r8a779g0-cpg-mssr.c + */ + +#include <clk-uclass.h> +#include <dm.h> + +#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A779H0_CLK_R, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL5, + CLK_PLL6, + CLK_PLL7, + CLK_PLL1_DIV2, + CLK_PLL2_DIV2, + CLK_PLL3_DIV2, + CLK_PLL4_DIV2, + CLK_PLL4_DIV5, + CLK_PLL5_DIV2, + CLK_PLL5_DIV4, + CLK_PLL6_DIV2, + CLK_PLL7_DIV2, + CLK_S0, + CLK_S0_VIO, + CLK_S0_VC, + CLK_S0_HSC, + CLK_SASYNCPER, + CLK_SV_VIP, + CLK_SV_IR, + CLK_IMPASRC, + CLK_IMPBSRC, + CLK_VIOSRC, + CLK_VCSRC, + CLK_SDSRC, + CLK_RPCSRC, + CLK_OCO, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a779h0_core_clks[] = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), + DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), + DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), + DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), + DEF_FIXED(".pll7_div2", CLK_PLL7_DIV2, CLK_PLL7, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1), + DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1), + DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1), + DEF_FIXED(".impasrc", CLK_IMPASRC, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".impbsrc", CLK_IMPBSRC, CLK_PLL1, 4, 1), + DEF_FIXED(".viosrc", CLK_VIOSRC, CLK_PLL1, 6, 1), + DEF_FIXED(".vcsrc", CLK_VCSRC, CLK_PLL1, 6, 1), + DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), + DEF_RATE(".oco", CLK_OCO, 32768), + + /* Core Clock Outputs */ + DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), + DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), + DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), + DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), + DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("cl16m", R8A779H0_CLK_CL16M, CLK_S0, 48, 1), + DEF_FIXED("s0d2_rt", R8A779H0_CLK_S0D2_RT, CLK_S0, 2, 1), + DEF_FIXED("s0d3_rt", R8A779H0_CLK_S0D3_RT, CLK_S0, 3, 1), + DEF_FIXED("s0d4_rt", R8A779H0_CLK_S0D4_RT, CLK_S0, 4, 1), + DEF_FIXED("s0d6_rt", R8A779H0_CLK_S0D6_RT, CLK_S0, 6, 1), + DEF_FIXED("cl16m_rt", R8A779H0_CLK_CL16M_RT, CLK_S0, 48, 1), + DEF_FIXED("s0d2_per", R8A779H0_CLK_S0D2_PER, CLK_S0, 2, 1), + DEF_FIXED("s0d3_per", R8A779H0_CLK_S0D3_PER, CLK_S0, 3, 1), + DEF_FIXED("s0d4_per", R8A779H0_CLK_S0D4_PER, CLK_S0, 4, 1), + DEF_FIXED("s0d6_per", R8A779H0_CLK_S0D6_PER, CLK_S0, 6, 1), + DEF_FIXED("s0d12_per", R8A779H0_CLK_S0D12_PER, CLK_S0, 12, 1), + DEF_FIXED("s0d24_per", R8A779H0_CLK_S0D24_PER, CLK_S0, 24, 1), + DEF_FIXED("cl16m_per", R8A779H0_CLK_CL16M_PER, CLK_S0, 48, 1), + DEF_FIXED("s0d2_mm", R8A779H0_CLK_S0D2_MM, CLK_S0, 2, 1), + DEF_FIXED("s0d4_mm", R8A779H0_CLK_S0D4_MM, CLK_S0, 4, 1), + DEF_FIXED("cl16m_mm", R8A779H0_CLK_CL16M_MM, CLK_S0, 48, 1), + DEF_FIXED("s0d2_u3dg", R8A779H0_CLK_S0D2_U3DG, CLK_S0, 2, 1), + DEF_FIXED("s0d4_u3dg", R8A779H0_CLK_S0D4_U3DG, CLK_S0, 4, 1), + DEF_FIXED("s0d1_vio", R8A779H0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1), + DEF_FIXED("s0d2_vio", R8A779H0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1), + DEF_FIXED("s0d4_vio", R8A779H0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1), + DEF_FIXED("s0d8_vio", R8A779H0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1), + DEF_FIXED("s0d1_vc", R8A779H0_CLK_S0D1_VC, CLK_S0_VC, 1, 1), + DEF_FIXED("s0d2_vc", R8A779H0_CLK_S0D2_VC, CLK_S0_VC, 2, 1), + DEF_FIXED("s0d4_vc", R8A779H0_CLK_S0D4_VC, CLK_S0_VC, 4, 1), + DEF_FIXED("s0d1_hsc", R8A779H0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1), + DEF_FIXED("s0d2_hsc", R8A779H0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1), + DEF_FIXED("s0d4_hsc", R8A779H0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1), + DEF_FIXED("s0d8_hsc", R8A779H0_CLK_S0D8_HSC, CLK_S0_HSC, 8, 1), + DEF_FIXED("cl16m_hsc", R8A779H0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1), + DEF_FIXED("sasyncrt", R8A779H0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1), + DEF_FIXED("sasyncperd1", R8A779H0_CLK_SASYNCPERD1, CLK_SASYNCPER, 1, 1), + DEF_FIXED("sasyncperd2", R8A779H0_CLK_SASYNCPERD2, CLK_SASYNCPER, 2, 1), + DEF_FIXED("sasyncperd4", R8A779H0_CLK_SASYNCPERD4, CLK_SASYNCPER, 4, 1), + DEF_FIXED("svd1_vip", R8A779H0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1), + DEF_FIXED("svd2_vip", R8A779H0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1), + DEF_FIXED("svd1_ir", R8A779H0_CLK_SVD1_IR, CLK_SV_IR, 1, 1), + DEF_FIXED("svd2_ir", R8A779H0_CLK_SVD2_IR, CLK_SV_IR, 2, 1), + DEF_FIXED("cbfusa", R8A779H0_CLK_CBFUSA, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A779H0_CLK_CPEX, CLK_EXTAL, 2, 1), + DEF_FIXED("cp", R8A779H0_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("impad1", R8A779H0_CLK_IMPAD1, CLK_IMPASRC, 1, 1), + DEF_FIXED("impad4", R8A779H0_CLK_IMPAD4, CLK_IMPASRC, 4, 1), + DEF_FIXED("impb", R8A779H0_CLK_IMPB, CLK_IMPBSRC, 1, 1), + DEF_FIXED("viobusd1", R8A779H0_CLK_VIOBUSD1, CLK_VIOSRC, 1, 1), + DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1), + DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1), + DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1), + DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), + DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, 0x880), + DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), + DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), + DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + + DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, 0x870), + DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, 0x870), + + DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC), + + DEF_GEN4_OSC("osc", R8A779H0_CLK_OSC, CLK_EXTAL, 8), + DEF_GEN4_MDSEL("r", R8A779H0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), +}; + +static const struct mssr_mod_clk r8a779h0_mod_clks[] = { + DEF_MOD("avb0-rgmii0", 211, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("avb1-rgmii1", 212, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("avb2-rgmii2", 213, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), + DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), + DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), + DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1), + DEF_MOD("i2c0", 518, R8A779H0_CLK_S0D6_PER), + DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER), + DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER), + DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER), + DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), + DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0), + DEF_MOD("pfc0", 915, R8A779H0_CLK_CL16M), + DEF_MOD("pfc1", 916, R8A779H0_CLK_CL16M), + DEF_MOD("pfc2", 917, R8A779H0_CLK_CL16M), +}; + +/* + * CPG Clock Data + */ +/* + * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC + * 14 13 (MHz) + * ------------------------------------------------------------------------ + * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16 + * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19 + * 1 0 Prohibited setting + * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ + (((md) & BIT(13)) >> 13)) + +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv PLL7 mult/div */ + { 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, 120, 1, }, + { 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, 100, 1, }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, 120, 1, }, +}; + +/* + * Note that the only clock left running before booting Linux are now + * MFIS, INTC-AP, INTC-EX, SCIF0, HSCIF0 on V4M + */ +#define MSTPCR5_INTCAP BIT(11) +#define MSTPCR5_HSCIF0 BIT(14) +#define MSTPCR6_INTCEX BIT(11) +#define MSTPCR7_SCIF0 BIT(2) + +static const struct mstp_stop_table r8a779h0_mstp_table[] = { + { 0x0FC102A1, 0x0, 0x0, 0x0 }, + { 0x00D50020, 0x0, 0x0, 0x0 }, + { 0x00003800, 0x0, 0x0, 0x0 }, + { 0xF0000000, 0x0, 0x0, 0x0 }, + { 0x0000CA01, 0x0, 0x0, 0x0 }, + { 0xE63FE100, MSTPCR5_HSCIF0 | MSTPCR5_INTCAP, 0x0, 0x0 }, + { 0xF1FF3900, MSTPCR6_INTCEX, 0x0, 0x0 }, + { 0xDFF7E6FC, MSTPCR7_SCIF0, 0x0, 0x0 }, + { 0x40003FFF, 0x0, 0x0, 0x0 }, + { 0x001BBCF8, 0x0, 0x0, 0x0 }, + { 0x10000000, 0x0, 0x0, 0x0 }, + { 0x00000001, 0x0, 0x0, 0x0 }, + { 0xDE000000, 0x0, 0x0, 0x0 }, + { 0x00000017, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, + { 0x308003C0, 0x0, 0x0, 0x0 }, + { 0x402200E6, 0x0, 0x0, 0x0 }, + { 0x0C000000, 0x0, 0x0, 0x0 }, +}; + +static const void *r8a779h0_get_pll_config(const u32 cpg_mode) +{ + return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; +} + +static const struct cpg_mssr_info r8a779h0_cpg_mssr_info = { + .core_clk = r8a779h0_core_clks, + .core_clk_size = ARRAY_SIZE(r8a779h0_core_clks), + .mod_clk = r8a779h0_mod_clks, + .mod_clk_size = ARRAY_SIZE(r8a779h0_mod_clks), + .mstp_table = r8a779h0_mstp_table, + .mstp_table_size = ARRAY_SIZE(r8a779h0_mstp_table), + .reset_node = "renesas,r8a779h0-rst", + .reset_modemr_offset = CPG_RST_MODEMR0, + .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, + .get_pll_config = r8a779h0_get_pll_config, + .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, +}; + +static const struct udevice_id r8a779h0_cpg_ids[] = { + { + .compatible = "renesas,r8a779h0-cpg-mssr", + .data = (ulong)&r8a779h0_cpg_mssr_info + }, + { } +}; + +U_BOOT_DRIVER(clk_r8a779h0) = { + .name = "cpg_r8a779h0", + .id = UCLASS_NOP, + .of_match = r8a779h0_cpg_ids, + .bind = gen3_cpg_bind, +}; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 370f26c4f0f..4efb9b6ceef 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -41,6 +41,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN4_PLL5, CLK_TYPE_GEN4_PLL4, CLK_TYPE_GEN4_PLL6, + CLK_TYPE_GEN4_PLL7, CLK_TYPE_GEN4_SDSRC, CLK_TYPE_GEN4_SDH, CLK_TYPE_GEN4_SD, @@ -130,6 +131,8 @@ struct rcar_gen4_cpg_pll_config { u8 pll6_mult; u8 pll6_div; u8 osc_prediv; + u8 pll7_mult; + u8 pll7_div; }; #define CPG_RST_MODEMR 0x060 diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 8a62d63dfef..eea9ec96598 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -876,13 +876,20 @@ static int udma_alloc_tx_resources(struct udma_chan *uc) { struct k3_nav_ring_cfg ring_cfg; struct udma_dev *ud = uc->ud; - int ret; + struct udma_tchan *tchan; + int ring_idx, ret; ret = udma_get_tchan(uc); if (ret) return ret; - ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->tchan->id, -1, + tchan = uc->tchan; + if (tchan->tflow_id >= 0) + ring_idx = tchan->tflow_id; + else + ring_idx = ud->bchan_cnt + tchan->id; + + ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1, &uc->tchan->t_ring, &uc->tchan->tc_ring); if (ret) { diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 6e9f93e9a30..ee092185588 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -236,21 +236,27 @@ static int ti_sci_do_xfer(struct ti_sci_info *info, { struct k3_sec_proxy_msg *msg = &xfer->tx_message; u8 secure_buf[info->desc->max_msg_size]; - struct ti_sci_secure_msg_hdr secure_hdr; + struct ti_sci_secure_msg_hdr *secure_hdr = (struct ti_sci_secure_msg_hdr *)secure_buf; int ret; + /* + * The reason why we need the is_secure code is because of boot R5. + * boot R5 starts off in "secure mode" when it hands off from Boot + * ROM over to the Secondary bootloader. The initial set of calls + * we have to make need to be on a secure pipe. + */ if (info->is_secure) { /* ToDo: get checksum of the entire message */ - secure_hdr.checksum = 0; - secure_hdr.reserved = 0; - memcpy(&secure_buf[sizeof(secure_hdr)], xfer->tx_message.buf, + secure_hdr->checksum = 0; + secure_hdr->reserved = 0; + memcpy(&secure_buf[sizeof(*secure_hdr)], xfer->tx_message.buf, xfer->tx_message.len); xfer->tx_message.buf = (u32 *)secure_buf; - xfer->tx_message.len += sizeof(secure_hdr); + xfer->tx_message.len += sizeof(*secure_hdr); if (xfer->rx_len) - xfer->rx_len += sizeof(secure_hdr); + xfer->rx_len += sizeof(*secure_hdr); } /* Send the message */ diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index 0b8674339ec..8877b8f4385 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -1196,6 +1196,12 @@ static int gpmc_probe(struct udevice *dev) gpmc_cfg = (struct gpmc *)priv->base; gpmc_base = priv->base; + /* + * Disable all IRQs as some bootroms might leave them enabled + * and that will cause a lock-up later + */ + gpmc_write_reg(GPMC_IRQENABLE, 0); + priv->l3_clk = devm_clk_get(dev, "fck"); if (IS_ERR(priv->l3_clk)) return PTR_ERR(priv->l3_clk); diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 3e3002ba6df..6e2c678e614 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -882,6 +882,28 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) misc_call(dev, SC_TRUE, &msg, size, &msg, size); } +int sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_PM; + RPC_FUNC(&msg) = (u8)PM_FUNC_RESET_REASON; + RPC_SIZE(&msg) = 1U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_U8(&msg, 0U)); + + if (reason) + *reason = RPC_U8(&msg, 0U); + + return ret; +} + int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_power_mode_t *mode) { diff --git a/drivers/mmc/bcmstb_sdhci.c b/drivers/mmc/bcmstb_sdhci.c index dc96818cff4..49846adcf54 100644 --- a/drivers/mmc/bcmstb_sdhci.c +++ b/drivers/mmc/bcmstb_sdhci.c @@ -38,15 +38,52 @@ */ #define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000 -/* - * This driver has only been tested with eMMC devices; SD devices may - * not work. - */ +#define SDIO_CFG_CTRL 0x0 +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) + +#define SDIO_CFG_SD_PIN_SEL 0x44 +#define SDIO_CFG_SD_PIN_SEL_MASK 0x3 +#define SDIO_CFG_SD_PIN_SEL_CARD BIT(1) + struct sdhci_bcmstb_plat { struct mmc_config cfg; struct mmc mmc; }; +struct sdhci_brcmstb_dev_priv { + int (*init)(struct udevice *dev); +}; + +static int sdhci_brcmstb_init_2712(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + void *cfg_regs; + u32 reg; + + /* Map in the non-standard CFG registers */ + cfg_regs = dev_remap_addr_name(dev, "cfg"); + if (!cfg_regs) + return -ENOENT; + + if ((host->mmc->host_caps & MMC_CAP_NONREMOVABLE) || + (host->mmc->host_caps & MMC_CAP_NEEDS_POLL)) { + /* Force presence */ + reg = readl(cfg_regs + SDIO_CFG_CTRL); + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN; + writel(reg, cfg_regs + SDIO_CFG_CTRL); + } else { + /* Enable card detection line */ + reg = readl(cfg_regs + SDIO_CFG_SD_PIN_SEL); + reg &= ~SDIO_CFG_SD_PIN_SEL_MASK; + reg |= SDIO_CFG_SD_PIN_SEL_CARD; + writel(reg, cfg_regs + SDIO_CFG_SD_PIN_SEL); + } + + return 0; +} + static int sdhci_bcmstb_bind(struct udevice *dev) { struct sdhci_bcmstb_plat *plat = dev_get_plat(dev); @@ -54,14 +91,20 @@ static int sdhci_bcmstb_bind(struct udevice *dev) return sdhci_bind(dev, &plat->mmc, &plat->cfg); } +/* No specific SDHCI operations are required */ +static const struct sdhci_ops bcmstb_sdhci_ops = { 0 }; + static int sdhci_bcmstb_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_bcmstb_plat *plat = dev_get_plat(dev); struct sdhci_host *host = dev_get_priv(dev); + struct sdhci_brcmstb_dev_priv *dev_priv; fdt_addr_t base; int ret; + dev_priv = (struct sdhci_brcmstb_dev_priv *)dev_get_driver_data(dev); + base = dev_read_addr(dev); if (base == FDT_ADDR_T_NONE) return -EINVAL; @@ -75,6 +118,8 @@ static int sdhci_bcmstb_probe(struct udevice *dev) host->mmc = &plat->mmc; host->mmc->dev = dev; + host->ops = &bcmstb_sdhci_ops; + ret = sdhci_setup_cfg(&plat->cfg, host, BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY, BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY); @@ -84,10 +129,21 @@ static int sdhci_bcmstb_probe(struct udevice *dev) upriv->mmc = &plat->mmc; host->mmc->priv = host; + if (dev_priv && dev_priv->init) { + ret = dev_priv->init(dev); + if (ret) + return ret; + } + return sdhci_probe(dev); } +static const struct sdhci_brcmstb_dev_priv match_priv_2712 = { + .init = sdhci_brcmstb_init_2712, +}; + static const struct udevice_id sdhci_bcmstb_match[] = { + { .compatible = "brcm,bcm2712-sdhci", .data = (ulong)&match_priv_2712 }, { .compatible = "brcm,bcm7425-sdhci" }, { .compatible = "brcm,sdhci-brcmstb" }, { } diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 285332d9f4f..706fb123579 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -71,7 +71,6 @@ #define DLL_RXCLK_NO_INVERTER BIT(29) #define DLL_RXCLK_ORI_GATE BIT(31) #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 -#define DLL_TXCLK_TAPNUM_90_DEGREES 0x9 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) #define DLL_TXCLK_NO_INVERTER BIT(29) #define DLL_STRBIN_TAPNUM_DEFAULT 0x4 @@ -314,8 +313,10 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab int val, ret; u32 extra, txclk_tapnum; - if (!enable) + if (!enable) { + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); return 0; + } if (clock >= 100 * MHz) { /* reset DLL */ @@ -648,7 +649,7 @@ static const struct sdhci_data rk3568_data = { .config_dll = rk3568_sdhci_config_dll, .flags = FLAG_INVERTER_FLAG_IN_RXCLK, .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, - .hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, + .hs400_txclk_tapnum = 0x8, }; static const struct sdhci_data rk3588_data = { @@ -656,7 +657,7 @@ static const struct sdhci_data rk3588_data = { .set_clock = rk3568_sdhci_set_clock, .config_dll = rk3568_sdhci_config_dll, .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, - .hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES, + .hs400_txclk_tapnum = 0x9, }; static const struct udevice_id sdhci_ids[] = { diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 38a287487ed..4e83b8c94c9 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -80,6 +80,7 @@ const struct flash_info spi_nor_ids[] = { #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ /* EON -- en25xxx */ + { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, diff --git a/drivers/mux/mux-uclass.c b/drivers/mux/mux-uclass.c index c98576ceb81..8833888ded3 100644 --- a/drivers/mux/mux-uclass.c +++ b/drivers/mux/mux-uclass.c @@ -318,7 +318,8 @@ int dm_mux_init(void) return ret; } uclass_foreach_dev(dev, uc) { - if (dev_read_bool(dev, "u-boot,mux-autoprobe")) { + if (dev_read_bool(dev, "u-boot,mux-autoprobe") || + dev_read_bool(dev, "idle-states")) { ret = device_probe(dev); if (ret) log_debug("unable to probe device %s\n", diff --git a/drivers/net/designware.c b/drivers/net/designware.c index c8696358d6f..c222197b114 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -13,6 +13,7 @@ #include <cpu_func.h> #include <dm.h> #include <errno.h> +#include <eth_phy.h> #include <log.h> #include <miiphy.h> #include <malloc.h> @@ -576,6 +577,9 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) struct phy_device *phydev; int ret; + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + eth_phy_set_mdio_bus(dev, NULL); + #if IS_ENABLED(CONFIG_DM_MDIO) phydev = dm_eth_phy_connect(dev); if (!phydev) @@ -583,6 +587,9 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) #else int phy_addr = -1; + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + phy_addr = eth_phy_get_addr(dev); + #ifdef CONFIG_PHY_ADDR phy_addr = CONFIG_PHY_ADDR; #endif @@ -678,8 +685,8 @@ int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct dw_eth_dev *priv = dev_get_priv(dev); - u32 iobase = pdata->iobase; - ulong ioaddr; + phys_addr_t iobase = pdata->iobase; + void *ioaddr; int ret, err; struct reset_ctl_bulk reset_bulk; #ifdef CONFIG_CLK @@ -739,16 +746,18 @@ int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in plat before we probe the hardware. */ if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) { - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = dm_pci_mem_to_phys(dev, iobase); + u32 pcibase; + + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &pcibase); + pcibase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = dm_pci_mem_to_phys(dev, pcibase); pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII; } - debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); - ioaddr = iobase; + debug("%s, iobase=%pa, priv=%p\n", __func__, &iobase, priv); + ioaddr = phys_to_virt(iobase); priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); priv->interface = pdata->phy_interface; diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index f701790194c..f24fc5b2de6 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -14,6 +14,7 @@ #include <phy.h> #define PHY_ID_TJA_1103 0x001BB010 +#define PHY_ID_TJA_1120 0x001BB031 #define VEND1_DEVICE_CONTROL 0x0040 #define DEVICE_CONTROL_RESET BIT(15) @@ -306,13 +307,35 @@ static int nxp_c45_config(struct phy_device *phydev) return nxp_c45_start_op(phydev); } +static int nxp_c45_speed(struct phy_device *phydev) +{ + int val; + + val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); + if (val < 0) + return val; + + if (val & MDIO_PMA_CTRL1_SPEED100) + phydev->speed = SPEED_100; + else if (val & MDIO_PMA_CTRL1_SPEED1000) + phydev->speed = SPEED_1000; + else + phydev->speed = 0; + + return 0; +} + static int nxp_c45_startup(struct phy_device *phydev) { u32 reg; + int ret; reg = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); phydev->link = !!(reg & MDIO_STAT1_LSTATUS); - phydev->speed = SPEED_100; + ret = nxp_c45_speed(phydev); + if (ret < 0) + return ret; + phydev->duplex = DUPLEX_FULL; return 0; } @@ -330,11 +353,25 @@ static int nxp_c45_probe(struct phy_device *phydev) return 0; } -U_BOOT_PHY_DRIVER(nxp_c45_tja11xx) = { +#define NXP_C45_COMMON_FEATURES (SUPPORTED_TP | \ + SUPPORTED_MII) + +U_BOOT_PHY_DRIVER(nxp_c45_tja1103) = { .name = "NXP C45 TJA1103", .uid = PHY_ID_TJA_1103, .mask = 0xfffff0, - .features = PHY_100BT1_FEATURES, + .features = NXP_C45_COMMON_FEATURES | SUPPORTED_100baseT_Full, + .probe = &nxp_c45_probe, + .config = &nxp_c45_config, + .startup = &nxp_c45_startup, + .shutdown = &genphy_shutdown, +}; + +U_BOOT_PHY_DRIVER(nxp_c45_tja1120) = { + .name = "NXP C45 TJA1120", + .uid = PHY_ID_TJA_1120, + .mask = 0xfffff0, + .features = NXP_C45_COMMON_FEATURES | SUPPORTED_1000baseT_Full, .probe = &nxp_c45_probe, .config = &nxp_c45_config, .startup = &nxp_c45_startup, diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig index a60f49869b4..1b7fb62bc4b 100644 --- a/drivers/pinctrl/exynos/Kconfig +++ b/drivers/pinctrl/exynos/Kconfig @@ -16,3 +16,11 @@ config PINCTRL_EXYNOS78x0 help Support pin multiplexing and pin configuration control on Samsung's Exynos78x0 SoC. + +config PINCTRL_EXYNOS850 + bool "Samsung Exynos850 pinctrl driver" + depends on ARCH_EXYNOS && PINCTRL_FULL + select PINCTRL_EXYNOS + help + Support pin multiplexing and pin configuration control on + Samsung's Exynos850 SoC. diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile index 07db970ca94..3abe1226eb7 100644 --- a/drivers/pinctrl/exynos/Makefile +++ b/drivers/pinctrl/exynos/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o +obj-$(CONFIG_PINCTRL_EXYNOS850) += pinctrl-exynos850.o diff --git a/drivers/pinctrl/exynos/pinctrl-exynos850.c b/drivers/pinctrl/exynos/pinctrl-exynos850.c new file mode 100644 index 00000000000..3ec2636e0d8 --- /dev/null +++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * Exynos850 pinctrl driver. + */ + +#include <dm.h> +#include <dm/pinctrl.h> +#include "pinctrl-exynos.h" + +#define EXYNOS850_PIN_BANK(pins, reg, id) \ + { \ + .type = &exynos850_bank_type, \ + .offset = reg, \ + .nr_pins = pins, \ + .name = id \ + } + +/* CON, DAT, PUD, DRV */ +static const struct samsung_pin_bank_type exynos850_bank_type = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +static const struct pinctrl_ops exynos850_pinctrl_ops = { + .set_state = exynos_pinctrl_set_state +}; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks0[] = { + EXYNOS850_PIN_BANK(8, 0x000, "gpa0"), + EXYNOS850_PIN_BANK(8, 0x020, "gpa1"), + EXYNOS850_PIN_BANK(8, 0x040, "gpa2"), + EXYNOS850_PIN_BANK(8, 0x060, "gpa3"), + EXYNOS850_PIN_BANK(4, 0x080, "gpa4"), + EXYNOS850_PIN_BANK(3, 0x0a0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos850_pin_banks1[] = { + EXYNOS850_PIN_BANK(1, 0x000, "gpm0"), + EXYNOS850_PIN_BANK(1, 0x020, "gpm1"), + EXYNOS850_PIN_BANK(1, 0x040, "gpm2"), + EXYNOS850_PIN_BANK(1, 0x060, "gpm3"), + EXYNOS850_PIN_BANK(1, 0x080, "gpm4"), + EXYNOS850_PIN_BANK(1, 0x0a0, "gpm5"), + EXYNOS850_PIN_BANK(1, 0x0c0, "gpm6"), + EXYNOS850_PIN_BANK(1, 0x0e0, "gpm7"), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static const struct samsung_pin_bank_data exynos850_pin_banks2[] = { + EXYNOS850_PIN_BANK(5, 0x000, "gpb0"), + EXYNOS850_PIN_BANK(5, 0x020, "gpb1"), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks3[] = { + EXYNOS850_PIN_BANK(6, 0x000, "gpf2"), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks4[] = { + EXYNOS850_PIN_BANK(4, 0x000, "gpf0"), + EXYNOS850_PIN_BANK(8, 0x020, "gpf1"), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks5[] = { + EXYNOS850_PIN_BANK(2, 0x000, "gpg0"), + EXYNOS850_PIN_BANK(6, 0x020, "gpp0"), + EXYNOS850_PIN_BANK(4, 0x040, "gpp1"), + EXYNOS850_PIN_BANK(4, 0x060, "gpp2"), + EXYNOS850_PIN_BANK(8, 0x080, "gpg1"), + EXYNOS850_PIN_BANK(8, 0x0a0, "gpg2"), + EXYNOS850_PIN_BANK(1, 0x0c0, "gpg3"), + EXYNOS850_PIN_BANK(3, 0x0e0, "gpc0"), + EXYNOS850_PIN_BANK(6, 0x100, "gpc1"), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + }, + {/* list terminator */} +}; + +static const struct udevice_id exynos850_pinctrl_ids[] = { + { .compatible = "samsung,exynos850-pinctrl", + .data = (ulong)exynos850_pin_ctrl }, + { } +}; + +U_BOOT_DRIVER(pinctrl_exynos850) = { + .name = "pinctrl_exynos850", + .id = UCLASS_PINCTRL, + .of_match = exynos850_pinctrl_ids, + .priv_auto = sizeof(struct exynos_pinctrl_priv), + .ops = &exynos850_pinctrl_ops, + .probe = exynos_pinctrl_probe, +}; diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 4c8ec9fcf18..171cd374b81 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -131,6 +131,12 @@ config PINCTRL_PFC_R8A779G0 help Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs. +config PINCTRL_PFC_R8A779H0 + bool "Renesas RCar Gen4 R8A779H0 pin control driver" + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RCar Gen4 R8A779H0 SoCs. + config PINCTRL_RZA1 bool "Renesas RZ/A1 R7S72100 pin control driver" depends on CPU_RZA1 diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index cf7ec109681..a5810dc0f10 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o +obj-$(CONFIG_PINCTRL_PFC_R8A779H0) += pfc-r8a779h0.o obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o obj-$(CONFIG_PINCTRL_RZG2L) += rzg2l-pfc.o diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c new file mode 100644 index 00000000000..17422395ad1 --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c @@ -0,0 +1,3969 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R8A779H0 processor support - PFC hardware block. + * + * Copyright (C) 2023 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c + */ + +#include <dm.h> +#include <errno.h> +#include <dm/pinctrl.h> +#include <linux/bitops.h> +#include <linux/kernel.h> + +#include "sh_pfc.h" + +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_GP(fn, sfx) \ + PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_16(2, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 30, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 31, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_14(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(4, 14, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 15, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ + PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ + PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8) +#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4) +#define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0) +#define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28) +#define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24) +#define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20) +#define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16) +#define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12) +#define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8) +#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4) +#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0) +#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28) +#define GPSR0_6 F_(IRQ0, IP0SR0_27_24) +#define GPSR0_5 F_(IRQ1, IP0SR0_23_20) +#define GPSR0_4 F_(IRQ2, IP0SR0_19_16) +#define GPSR0_3 F_(IRQ3, IP0SR0_15_12) +#define GPSR0_2 F_(GP0_02, IP0SR0_11_8) +#define GPSR0_1 F_(GP0_01, IP0SR0_7_4) +#define GPSR0_0 F_(GP0_00, IP0SR0_3_0) + +/* GPSR1 */ +#define GPSR1_29 F_(ERROROUTC_N_A, IP3SR1_23_20) +#define GPSR1_28 F_(HTX3, IP3SR1_19_16) +#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12) +#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8) +#define GPSR1_25 F_(HSCK3, IP3SR1_7_4) +#define GPSR1_24 F_(HRX3, IP3SR1_3_0) +#define GPSR1_23 F_(GP1_23, IP2SR1_31_28) +#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24) +#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20) +#define GPSR1_20 F_(SSI_SD, IP2SR1_19_16) +#define GPSR1_19 F_(SSI_WS, IP2SR1_15_12) +#define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8) +#define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4) +#define GPSR1_16 F_(HRX0, IP2SR1_3_0) +#define GPSR1_15 F_(HSCK0, IP1SR1_31_28) +#define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24) +#define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20) +#define GPSR1_12 F_(HTX0, IP1SR1_19_16) +#define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12) +#define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8) +#define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4) +#define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0) +#define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28) +#define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24) +#define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20) +#define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16) +#define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12) +#define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8) +#define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4) +#define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0) + +/* GPSR2 */ +#define GPSR2_19 F_(CANFD1_RX, IP2SR2_15_12) +#define GPSR2_17 F_(CANFD1_TX, IP2SR2_7_4) +#define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28) +#define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24) +#define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20) +#define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16) +#define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12) +#define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8) +#define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4) +#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0) +#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28) +#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24) +#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20) +#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16) +#define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12) +#define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8) +#define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4) +#define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0) + +/* GPSR3 */ +#define GPSR3_31 F_(TCLK4, IP3SR3_31_28) +#define GPSR3_30 F_(TCLK3, IP3SR3_27_24) +#define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20) +#define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16) +#define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12) +#define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8) +#define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4) +#define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0) +#define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28) +#define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24) +#define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20) +#define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16) +#define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12) +#define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8) +#define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4) +#define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0) +#define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28) +#define GPSR3_14 F_(PWM2, IP1SR3_27_24) +#define GPSR3_13 F_(PWM1, IP1SR3_23_20) +#define GPSR3_12 F_(SD_WP, IP1SR3_19_16) +#define GPSR3_11 F_(SD_CD, IP1SR3_15_12) +#define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8) +#define GPSR3_9 F_(MMC_D6, IP1SR3_7_4) +#define GPSR3_8 F_(MMC_D7, IP1SR3_3_0) +#define GPSR3_7 F_(MMC_D4, IP0SR3_31_28) +#define GPSR3_6 F_(MMC_D5, IP0SR3_27_24) +#define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20) +#define GPSR3_4 F_(MMC_DS, IP0SR3_19_16) +#define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12) +#define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8) +#define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4) +#define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0) + +/* GPSR4 */ +#define GPSR4_24 F_(AVS1, IP3SR4_3_0) +#define GPSR4_23 F_(AVS0, IP2SR4_31_28) +#define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20) +#define GPSR4_15 F_(PWM4, IP1SR4_31_28) +#define GPSR4_14 F_(PWM3, IP1SR4_27_24) +#define GPSR4_13 F_(HSCK2, IP1SR4_23_20) +#define GPSR4_12 F_(HCTS2_N, IP1SR4_19_16) +#define GPSR4_11 F_(SCIF_CLK2, IP1SR4_15_12) +#define GPSR4_10 F_(HRTS2_N, IP1SR4_11_8) +#define GPSR4_9 F_(HTX2, IP1SR4_7_4) +#define GPSR4_8 F_(HRX2, IP1SR4_3_0) +#define GPSR4_7 F_(SDA3, IP0SR4_31_28) +#define GPSR4_6 F_(SCL3, IP0SR4_27_24) +#define GPSR4_5 F_(SDA2, IP0SR4_23_20) +#define GPSR4_4 F_(SCL2, IP0SR4_19_16) +#define GPSR4_3 F_(SDA1, IP0SR4_15_12) +#define GPSR4_2 F_(SCL1, IP0SR4_11_8) +#define GPSR4_1 F_(SDA0, IP0SR4_7_4) +#define GPSR4_0 F_(SCL0, IP0SR4_3_0) + +/* GPSR 5 */ +#define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16) +#define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12) +#define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8) +#define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4) +#define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0) +#define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28) +#define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24) +#define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20) +#define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16) +#define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12) +#define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8) +#define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4) +#define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0) +#define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28) +#define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24) +#define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20) +#define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16) +#define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12) +#define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8) +#define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4) +#define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0) + +/* GPSR 6 */ +#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16) +#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12) +#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8) +#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4) +#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0) +#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28) +#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24) +#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20) +#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16) +#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12) +#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8) +#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4) +#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0) +#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28) +#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24) +#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20) +#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16) +#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12) +#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8) +#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4) +#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0) + +/* GPSR7 */ +#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16) +#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12) +#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8) +#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4) +#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0) +#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28) +#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24) +#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20) +#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16) +#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12) +#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8) +#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4) +#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0) +#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28) +#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24) +#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20) +#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16) +#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12) +#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8) +#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) +#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) + + +/* SR0 */ +/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR1 */ +/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_23_20 FM(ERROROUTC_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR2 */ +/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR2_3_0 FM(FXR_TXDA) F_(0, 0) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_7_4 FM(FXR_TXENA_N_A) F_(0, 0) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_11_8 FM(RXDA_EXTFXR) F_(0, 0) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_15_12 FM(CLK_EXTFXR) F_(0, 0) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_31_28 FM(TPU0TO1_A) F_(0, 0) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR2_3_0 FM(TPU0TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR2_7_4 FM(CANFD1_TX) F_(0, 0) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_15_12 FM(CANFD1_RX) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR3 */ +/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_27_24 FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_31_28 FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR4 */ +/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR4_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR4_3_0 FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_7_4 FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_11_8 FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_15_12 FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_19_16 FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_23_20 FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_27_24 FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_31_28 FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR5 */ +/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR5_3_0 FM(AVB2_AVTP_PPS) FM(Ether_GPTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) FM(Ether_GPTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) FM(Ether_GPTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_23_20 FM(AVB2_MAGIC) FM(Ether_GPTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR6 */ +/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR7 */ +/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ + GPSR3_31 \ + GPSR3_30 \ + GPSR1_29 GPSR3_29 \ + GPSR1_28 GPSR3_28 \ + GPSR1_27 GPSR3_27 \ + GPSR1_26 GPSR3_26 \ + GPSR1_25 GPSR3_25 \ + GPSR1_24 GPSR3_24 GPSR4_24 \ + GPSR1_23 GPSR3_23 GPSR4_23 \ + GPSR1_22 GPSR3_22 \ + GPSR1_21 GPSR3_21 GPSR4_21 \ + GPSR1_20 GPSR3_20 GPSR5_20 GPSR6_20 GPSR7_20 \ + GPSR1_19 GPSR2_19 GPSR3_19 GPSR5_19 GPSR6_19 GPSR7_19 \ +GPSR0_18 GPSR1_18 GPSR3_18 GPSR5_18 GPSR6_18 GPSR7_18 \ +GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR5_17 GPSR6_17 GPSR7_17 \ +GPSR0_16 GPSR1_16 GPSR3_16 GPSR5_16 GPSR6_16 GPSR7_16 \ +GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 + +#define PINMUX_IPSR \ +\ +FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \ +FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \ +FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \ +FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \ +FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \ +FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \ +FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \ +FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \ +\ +FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \ +FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \ +FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \ +FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \ +FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ +FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \ +FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \ +FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \ +\ +FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 \ +FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ +FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 \ +FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \ +FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \ +FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \ +FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \ +FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \ +\ +FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \ +FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \ +FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \ +FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \ +FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \ +FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \ +FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 FM(IP3SR3_27_24) IP3SR3_27_24 \ +FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 FM(IP3SR3_31_28) IP3SR3_31_28 \ +\ +FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \ +FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 \ +FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 \ +FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 \ +FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 \ +FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \ +FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \ +FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \ +\ +FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \ +FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ +FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ +FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ +FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ +FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \ +FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \ +FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \ +\ +FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \ +FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \ +FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \ +FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \ +FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \ +FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \ +FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \ +FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \ +\ +FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \ +FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \ +FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \ +FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \ +FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \ +FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \ +FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \ +FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \ + +/* MOD_SEL4 */ /* 0 */ /* 1 */ +#define MOD_SEL4_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1) +#define MOD_SEL4_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1) +#define MOD_SEL4_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1) +#define MOD_SEL4_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1) +#define MOD_SEL4_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1) +#define MOD_SEL4_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1) +#define MOD_SEL4_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1) +#define MOD_SEL4_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1) + +#define PINMUX_MOD_SELS \ +\ +MOD_SEL4_7 \ +MOD_SEL4_6 \ +MOD_SEL4_5 \ +MOD_SEL4_4 \ +MOD_SEL4_3 \ +MOD_SEL4_2 \ +MOD_SEL4_1 \ +MOD_SEL4_0 + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + /* IP0SR0 */ + PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B), + PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B), + + PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1), + + PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2), + + PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3), + PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK), + + PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2), + PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD), + + PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1), + PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD), + + PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0), + PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC), + + PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2), + + /* IP1SR0 */ + PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1), + + PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC), + + PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD), + + PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK), + + PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD), + + PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2), + PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A), + PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B), + + PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1), + PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A), + PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A), + + PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC), + PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A), + PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A), + + /* IP2SR0 */ + PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD), + PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A), + PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A), + + PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK), + PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A), + PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A), + + PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD), + PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A), + PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A), + + /* IP0SR1 */ + PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B), + PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B), + + PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1), + PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B), + PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B), + + PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B), + PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B), + + PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK), + PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B), + PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B), + + PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B), + PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B), + + PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD), + + PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2), + PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B), + PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B), + + PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1), + PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B), + PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B), + + /* IP1SR1 */ + PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B), + PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B), + + PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD), + PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B), + PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B), + + PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK), + PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B), + PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B), + + PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD), + + PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0), + PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0), + + PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N), + PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N), + + PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N), + PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N), + PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM0_B), + + PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0), + PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0), + PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A), + + /* IP2SR1 */ + PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0), + PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0), + + PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK), + PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A), + + PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK), + PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B), + + PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS), + PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B), + + PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD), + PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B), + + PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT), + PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B), + + PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN), + PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_C), + + PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A), + PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1), + PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B), + + /* IP3SR1 */ + PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A), + PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A), + PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2), + + PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A), + PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A), + PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK), + PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B), + + PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A), + PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A), + PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD), + PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B), + + PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A), + PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A), + PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD), + + PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A), + PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A), + PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC), + + PINMUX_IPSR_GPSR(IP3SR1_23_20, ERROROUTC_N_A), + + /* IP0SR2 */ + PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA), + PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B), + + PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A), + PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B), + + PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR), + PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5), + + PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR), + PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B), + + PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR), + + PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A), + + PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB), + + PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A), + PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C), + + /* IP1SR2 */ + PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A), + PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B), + + PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK), + PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B), + + PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX), + PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B), + + PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), + PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR), + + PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), + PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A), + PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C), + + PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX), + PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A), + PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B), + PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C), + + PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX), + PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B), + + PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX), + PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B), + + /* IP2SR2 */ + PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD1_TX), + PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM1_C), + + PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD1_RX), + PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM2_C), + + /* IP0SR3 */ + PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1), + + PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0), + + PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2), + + PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK), + + PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS), + + PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3), + + PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5), + + PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4), + + /* IP1SR3 */ + PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7), + + PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6), + + PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD), + + PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD), + + PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP), + + PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A), + + PINMUX_IPSR_GPSR(IP1SR3_27_24, PWM2_A), + + PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL), + + /* IP2SR3 */ + PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3), + + PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2), + + PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1), + + PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0), + + PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK), + + PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0), + + PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK), + + PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1), + + /* IP3SR3 */ + PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2), + + PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL), + + PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3), + + PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N), + + PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N), + + PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N), + + PINMUX_IPSR_GPSR(IP3SR3_27_24, TCLK3_A), + + PINMUX_IPSR_GPSR(IP3SR3_31_28, TCLK4_A), + + /* IP0SR4 */ + PINMUX_IPSR_MSEL(IP0SR4_3_0, SCL0, SEL_SCL0_0), + + PINMUX_IPSR_MSEL(IP0SR4_7_4, SDA0, SEL_SDA0_0), + + PINMUX_IPSR_MSEL(IP0SR4_11_8, SCL1, SEL_SCL1_0), + + PINMUX_IPSR_MSEL(IP0SR4_15_12, SDA1, SEL_SDA1_0), + + PINMUX_IPSR_MSEL(IP0SR4_19_16, SCL2, SEL_SCL2_0), + + PINMUX_IPSR_MSEL(IP0SR4_23_20, SDA2, SEL_SDA2_0), + + PINMUX_IPSR_MSEL(IP0SR4_27_24, SCL3, SEL_SCL3_0), + + PINMUX_IPSR_MSEL(IP0SR4_31_28, SDA3, SEL_SDA3_0), + + /* IP1SR4 */ + PINMUX_IPSR_GPSR(IP1SR4_3_0, HRX2), + PINMUX_IPSR_GPSR(IP1SR4_3_0, SCK4), + + PINMUX_IPSR_GPSR(IP1SR4_7_4, HTX2), + PINMUX_IPSR_GPSR(IP1SR4_7_4, CTS4_N), + + PINMUX_IPSR_GPSR(IP1SR4_11_8, HRTS2_N), + PINMUX_IPSR_GPSR(IP1SR4_11_8, RTS4_N), + + PINMUX_IPSR_GPSR(IP1SR4_15_12, SCIF_CLK2), + + PINMUX_IPSR_GPSR(IP1SR4_19_16, HCTS2_N), + PINMUX_IPSR_GPSR(IP1SR4_19_16, TX4), + + PINMUX_IPSR_GPSR(IP1SR4_23_20, HSCK2), + PINMUX_IPSR_GPSR(IP1SR4_23_20, RX4), + + PINMUX_IPSR_GPSR(IP1SR4_27_24, PWM3_A), + + PINMUX_IPSR_GPSR(IP1SR4_31_28, PWM4), + + /* IP2SR4 */ + PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N), + + PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0), + + /* IP3SR4 */ + PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1), + + /* IP0SR5 */ + PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS), + PINMUX_IPSR_GPSR(IP0SR5_3_0, Ether_GPTP_PPS0), + + PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP0SR5_7_4, Ether_GPTP_CAPTURE), + + PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP0SR5_11_8, Ether_GPTP_MATCH), + + PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK), + + PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT), + + PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC), + PINMUX_IPSR_GPSR(IP0SR5_23_20, Ether_GPTP_PPS1), + + PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC), + + PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK), + + /* IP1SR5 */ + PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3), + + PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3), + + PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO), + + PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2), + + PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1), + + PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2), + + PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1), + + PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0), + + /* IP2SR5 */ + PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC), + + PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0), + + PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC), + + PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL), + + PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL), + + /* IP0SR6 */ + PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO), + + PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC), + + PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC), + + PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT), + + PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK), + PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER), + + PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER), + + PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC), + PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC), + + PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL), + PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN), + + /* IP1SR6 */ + PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC), + PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC), + + PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL), + PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV), + + PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS), + PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL), + + PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS), + + PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1), + PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1), + + PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0), + PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0), + + PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1), + PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1), + + PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0), + PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0), + + /* IP2SR6 */ + PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2), + PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2), + + PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2), + PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2), + + PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3), + PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3), + + PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3), + PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3), + + PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK), + + /* IP0SR7 */ + PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS), + PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL), + + PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS), + + PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), + PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), + + PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), + PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3), + + PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK), + PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER), + + PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT), + + PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2), + PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2), + + PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1), + PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1), + + /* IP1SR7 */ + PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3), + PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3), + + PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK), + + PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC), + + PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0), + PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0), + + PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2), + PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2), + + PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC), + + PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO), + + PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC), + PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC), + + /* IP2SR7 */ + PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL), + PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN), + + PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1), + PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1), + + PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0), + PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0), + + PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC), + PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC), + + PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL), + PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV), +}; + +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), +}; + +/* - AUDIO CLOCK ----------------------------------------- */ +static const unsigned int audio_clkin_pins[] = { + /* CLK IN */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int audio_clkin_mux[] = { + AUDIO_CLKIN_MARK, +}; +static const unsigned int audio_clkout_pins[] = { + /* CLK OUT */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int audio_clkout_mux[] = { + AUDIO_CLKOUT_MARK, +}; + +/* - AVB0 ------------------------------------------------ */ +static const unsigned int avb0_link_pins[] = { + /* AVB0_LINK */ + RCAR_GP_PIN(7, 4), +}; +static const unsigned int avb0_link_mux[] = { + AVB0_LINK_MARK, +}; +static const unsigned int avb0_magic_pins[] = { + /* AVB0_MAGIC */ + RCAR_GP_PIN(7, 10), +}; +static const unsigned int avb0_magic_mux[] = { + AVB0_MAGIC_MARK, +}; +static const unsigned int avb0_phy_int_pins[] = { + /* AVB0_PHY_INT */ + RCAR_GP_PIN(7, 5), +}; +static const unsigned int avb0_phy_int_mux[] = { + AVB0_PHY_INT_MARK, +}; +static const unsigned int avb0_mdio_pins[] = { + /* AVB0_MDC, AVB0_MDIO */ + RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), +}; +static const unsigned int avb0_mdio_mux[] = { + AVB0_MDC_MARK, AVB0_MDIO_MARK, +}; +static const unsigned int avb0_rgmii_pins[] = { + /* + * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, + * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3, + */ + RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15), + RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), + RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3), + RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), + RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), + RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), +}; +static const unsigned int avb0_rgmii_mux[] = { + AVB0_TX_CTL_MARK, AVB0_TXC_MARK, + AVB0_TD0_MARK, AVB0_TD1_MARK, + AVB0_TD2_MARK, AVB0_TD3_MARK, + AVB0_RX_CTL_MARK, AVB0_RXC_MARK, + AVB0_RD0_MARK, AVB0_RD1_MARK, + AVB0_RD2_MARK, AVB0_RD3_MARK, +}; +static const unsigned int avb0_txcrefclk_pins[] = { + /* AVB0_TXCREFCLK */ + RCAR_GP_PIN(7, 9), +}; +static const unsigned int avb0_txcrefclk_mux[] = { + AVB0_TXCREFCLK_MARK, +}; +static const unsigned int avb0_avtp_pps_pins[] = { + /* AVB0_AVTP_PPS */ + RCAR_GP_PIN(7, 0), +}; +static const unsigned int avb0_avtp_pps_mux[] = { + AVB0_AVTP_PPS_MARK, +}; +static const unsigned int avb0_avtp_capture_pins[] = { + /* AVB0_AVTP_CAPTURE */ + RCAR_GP_PIN(7, 1), +}; +static const unsigned int avb0_avtp_capture_mux[] = { + AVB0_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb0_avtp_match_pins[] = { + /* AVB0_AVTP_MATCH */ + RCAR_GP_PIN(7, 2), +}; +static const unsigned int avb0_avtp_match_mux[] = { + AVB0_AVTP_MATCH_MARK, +}; + +/* - AVB1 ------------------------------------------------ */ +static const unsigned int avb1_link_pins[] = { + /* AVB1_LINK */ + RCAR_GP_PIN(6, 4), +}; +static const unsigned int avb1_link_mux[] = { + AVB1_LINK_MARK, +}; +static const unsigned int avb1_magic_pins[] = { + /* AVB1_MAGIC */ + RCAR_GP_PIN(6, 1), +}; +static const unsigned int avb1_magic_mux[] = { + AVB1_MAGIC_MARK, +}; +static const unsigned int avb1_phy_int_pins[] = { + /* AVB1_PHY_INT */ + RCAR_GP_PIN(6, 3), +}; +static const unsigned int avb1_phy_int_mux[] = { + AVB1_PHY_INT_MARK, +}; +static const unsigned int avb1_mdio_pins[] = { + /* AVB1_MDC, AVB1_MDIO */ + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0), +}; +static const unsigned int avb1_mdio_mux[] = { + AVB1_MDC_MARK, AVB1_MDIO_MARK, +}; +static const unsigned int avb1_rgmii_pins[] = { + /* + * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, + * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3, + */ + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), + RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18), + RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8), + RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14), + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), +}; +static const unsigned int avb1_rgmii_mux[] = { + AVB1_TX_CTL_MARK, AVB1_TXC_MARK, + AVB1_TD0_MARK, AVB1_TD1_MARK, + AVB1_TD2_MARK, AVB1_TD3_MARK, + AVB1_RX_CTL_MARK, AVB1_RXC_MARK, + AVB1_RD0_MARK, AVB1_RD1_MARK, + AVB1_RD2_MARK, AVB1_RD3_MARK, +}; +static const unsigned int avb1_txcrefclk_pins[] = { + /* AVB1_TXCREFCLK */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int avb1_txcrefclk_mux[] = { + AVB1_TXCREFCLK_MARK, +}; +static const unsigned int avb1_avtp_pps_pins[] = { + /* AVB1_AVTP_PPS */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int avb1_avtp_pps_mux[] = { + AVB1_AVTP_PPS_MARK, +}; +static const unsigned int avb1_avtp_capture_pins[] = { + /* AVB1_AVTP_CAPTURE */ + RCAR_GP_PIN(6, 11), +}; +static const unsigned int avb1_avtp_capture_mux[] = { + AVB1_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb1_avtp_match_pins[] = { + /* AVB1_AVTP_MATCH */ + RCAR_GP_PIN(6, 5), +}; +static const unsigned int avb1_avtp_match_mux[] = { + AVB1_AVTP_MATCH_MARK, +}; + +/* - AVB2 ------------------------------------------------ */ +static const unsigned int avb2_link_pins[] = { + /* AVB2_LINK */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int avb2_link_mux[] = { + AVB2_LINK_MARK, +}; +static const unsigned int avb2_magic_pins[] = { + /* AVB2_MAGIC */ + RCAR_GP_PIN(5, 5), +}; +static const unsigned int avb2_magic_mux[] = { + AVB2_MAGIC_MARK, +}; +static const unsigned int avb2_phy_int_pins[] = { + /* AVB2_PHY_INT */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int avb2_phy_int_mux[] = { + AVB2_PHY_INT_MARK, +}; +static const unsigned int avb2_mdio_pins[] = { + /* AVB2_MDC, AVB2_MDIO */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10), +}; +static const unsigned int avb2_mdio_mux[] = { + AVB2_MDC_MARK, AVB2_MDIO_MARK, +}; +static const unsigned int avb2_rgmii_pins[] = { + /* + * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3, + * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3, + */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12), + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18), + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9), +}; +static const unsigned int avb2_rgmii_mux[] = { + AVB2_TX_CTL_MARK, AVB2_TXC_MARK, + AVB2_TD0_MARK, AVB2_TD1_MARK, + AVB2_TD2_MARK, AVB2_TD3_MARK, + AVB2_RX_CTL_MARK, AVB2_RXC_MARK, + AVB2_RD0_MARK, AVB2_RD1_MARK, + AVB2_RD2_MARK, AVB2_RD3_MARK, +}; +static const unsigned int avb2_txcrefclk_pins[] = { + /* AVB2_TXCREFCLK */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int avb2_txcrefclk_mux[] = { + AVB2_TXCREFCLK_MARK, +}; +static const unsigned int avb2_avtp_pps_pins[] = { + /* AVB2_AVTP_PPS */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int avb2_avtp_pps_mux[] = { + AVB2_AVTP_PPS_MARK, +}; +static const unsigned int avb2_avtp_capture_pins[] = { + /* AVB2_AVTP_CAPTURE */ + RCAR_GP_PIN(5, 1), +}; +static const unsigned int avb2_avtp_capture_mux[] = { + AVB2_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb2_avtp_match_pins[] = { + /* AVB2_AVTP_MATCH */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int avb2_avtp_match_mux[] = { + AVB2_AVTP_MATCH_MARK, +}; + +/* - CANFD0 ----------------------------------------------------------------- */ +static const unsigned int canfd0_data_pins[] = { + /* CANFD0_TX, CANFD0_RX */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), +}; +static const unsigned int canfd0_data_mux[] = { + CANFD0_TX_MARK, CANFD0_RX_MARK, +}; + +/* - CANFD1 ----------------------------------------------------------------- */ +static const unsigned int canfd1_data_pins[] = { + /* CANFD1_TX, CANFD1_RX */ + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 19), +}; +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + +/* - CANFD2 ----------------------------------------------------------------- */ +static const unsigned int canfd2_data_pins[] = { + /* CANFD2_TX, CANFD2_RX */ + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), +}; +static const unsigned int canfd2_data_mux[] = { + CANFD2_TX_MARK, CANFD2_RX_MARK, +}; + +/* - CANFD3 ----------------------------------------------------------------- */ +static const unsigned int canfd3_data_pins[] = { + /* CANFD3_TX, CANFD3_RX */ + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), +}; +static const unsigned int canfd3_data_mux[] = { + CANFD3_TX_MARK, CANFD3_RX_MARK, +}; + +/* - CANFD Clock ------------------------------------------------------------ */ +static const unsigned int can_clk_pins[] = { + /* CAN_CLK */ + RCAR_GP_PIN(2, 9), +}; +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* HRX0, HTX0 */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* HSCK0 */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* HRTS0_N, HCTS0_N */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; + +/* - HSCIF1_A ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_a_pins[] = { + /* HRX1_A, HTX1_A */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), +}; +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, +}; +static const unsigned int hscif1_clk_a_pins[] = { + /* HSCK1_A */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, +}; +static const unsigned int hscif1_ctrl_a_pins[] = { + /* HRTS1_N_A, HCTS1_N_A */ + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), +}; +static const unsigned int hscif1_ctrl_a_mux[] = { + HRTS1_N_A_MARK, HCTS1_N_A_MARK, +}; + +/* - HSCIF1_B ---------------------------------------------------------------- */ +static const unsigned int hscif1_data_b_pins[] = { + /* HRX1_B, HTX1_B */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), +}; +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; +static const unsigned int hscif1_clk_b_pins[] = { + /* HSCK1_B */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* HRTS1_N_B, HCTS1_N_B */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; + +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* HRX2, HTX2 */ + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; +static const unsigned int hscif2_data_mux[] = { + HRX2_MARK, HTX2_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* HSCK2 */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCK2_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* HRTS2_N, HCTS2_N */ + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 12), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HRTS2_N_MARK, HCTS2_N_MARK, +}; + +/* - HSCIF3_A ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_a_pins[] = { + /* HRX3_A, HTX3_A */ + RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28), +}; +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; +static const unsigned int hscif3_clk_a_pins[] = { + /* HSCK3_A */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int hscif3_clk_a_mux[] = { + HSCK3_A_MARK, +}; +static const unsigned int hscif3_ctrl_a_pins[] = { + /* HRTS3_N_A, HCTS3_N_A */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), +}; +static const unsigned int hscif3_ctrl_a_mux[] = { + HRTS3_N_A_MARK, HCTS3_N_A_MARK, +}; + +/* - HSCIF3_B ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_b_pins[] = { + /* HRX3_B, HTX3_B */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), +}; +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, +}; +static const unsigned int hscif3_clk_b_pins[] = { + /* HSCK3_B */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int hscif3_clk_b_mux[] = { + HSCK3_B_MARK, +}; +static const unsigned int hscif3_ctrl_b_pins[] = { + /* HRTS3_N_B, HCTS3_N_B */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), +}; +static const unsigned int hscif3_ctrl_b_mux[] = { + HRTS3_N_B_MARK, HCTS3_N_B_MARK, +}; + +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SDA0, SCL0 */ + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), +}; +static const unsigned int i2c0_mux[] = { + SDA0_MARK, SCL0_MARK, +}; + +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SDA1, SCL1 */ + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), +}; +static const unsigned int i2c1_mux[] = { + SDA1_MARK, SCL1_MARK, +}; + +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SDA2, SCL2 */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), +}; +static const unsigned int i2c2_mux[] = { + SDA2_MARK, SCL2_MARK, +}; + +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SDA3, SCL3 */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), +}; +static const unsigned int i2c3_mux[] = { + SDA3_MARK, SCL3_MARK, +}; + +/* - MMC -------------------------------------------------------------------- */ +static const unsigned int mmc_data_pins[] = { + /* MMC_SD_D[0:3], MMC_D[4:7] */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), +}; +static const unsigned int mmc_data_mux[] = { + MMC_SD_D0_MARK, MMC_SD_D1_MARK, + MMC_SD_D2_MARK, MMC_SD_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, + MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* MMC_SD_CLK, MMC_SD_CMD */ + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, +}; +static const unsigned int mmc_cd_pins[] = { + /* SD_CD */ + RCAR_GP_PIN(3, 11), +}; +static const unsigned int mmc_cd_mux[] = { + SD_CD_MARK, +}; +static const unsigned int mmc_wp_pins[] = { + /* SD_WP */ + RCAR_GP_PIN(3, 12), +}; +static const unsigned int mmc_wp_mux[] = { + SD_WP_MARK, +}; +static const unsigned int mmc_ds_pins[] = { + /* MMC_DS */ + RCAR_GP_PIN(3, 4), +}; +static const unsigned int mmc_ds_mux[] = { + MMC_DS_MARK, +}; + +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* MSIOF0_SCK */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* MSIOF0_SYNC */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* MSIOF0_SS1 */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* MSIOF0_SS2 */ + RCAR_GP_PIN(1, 6), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* MSIOF0_TXD */ + RCAR_GP_PIN(1, 9), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* MSIOF0_RXD */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; + +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* MSIOF1_SCK */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* MSIOF1_SYNC */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* MSIOF1_SS1 */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* MSIOF1_SS2 */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_txd_pins[] = { + /* MSIOF1_TXD */ + RCAR_GP_PIN(1, 4), +}; +static const unsigned int msiof1_txd_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_rxd_pins[] = { + /* MSIOF1_RXD */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int msiof1_rxd_mux[] = { + MSIOF1_RXD_MARK, +}; + +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* MSIOF2_SCK */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* MSIOF2_SYNC */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* MSIOF2_SS1 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* MSIOF2_SS2 */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_txd_pins[] = { + /* MSIOF2_TXD */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int msiof2_txd_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_rxd_pins[] = { + /* MSIOF2_RXD */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int msiof2_rxd_mux[] = { + MSIOF2_RXD_MARK, +}; + +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_pins[] = { + /* MSIOF3_SCK */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int msiof3_clk_mux[] = { + MSIOF3_SCK_MARK, +}; +static const unsigned int msiof3_sync_pins[] = { + /* MSIOF3_SYNC */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int msiof3_sync_mux[] = { + MSIOF3_SYNC_MARK, +}; +static const unsigned int msiof3_ss1_pins[] = { + /* MSIOF3_SS1 */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof3_ss1_mux[] = { + MSIOF3_SS1_MARK, +}; +static const unsigned int msiof3_ss2_pins[] = { + /* MSIOF3_SS2 */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int msiof3_ss2_mux[] = { + MSIOF3_SS2_MARK, +}; +static const unsigned int msiof3_txd_pins[] = { + /* MSIOF3_TXD */ + RCAR_GP_PIN(0, 4), +}; +static const unsigned int msiof3_txd_mux[] = { + MSIOF3_TXD_MARK, +}; +static const unsigned int msiof3_rxd_pins[] = { + /* MSIOF3_RXD */ + RCAR_GP_PIN(0, 5), +}; +static const unsigned int msiof3_rxd_mux[] = { + MSIOF3_RXD_MARK, +}; + +/* - MSIOF4 ----------------------------------------------------------------- */ +static const unsigned int msiof4_clk_pins[] = { + /* MSIOF4_SCK */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int msiof4_clk_mux[] = { + MSIOF4_SCK_MARK, +}; +static const unsigned int msiof4_sync_pins[] = { + /* MSIOF4_SYNC */ + RCAR_GP_PIN(1, 28), +}; +static const unsigned int msiof4_sync_mux[] = { + MSIOF4_SYNC_MARK, +}; +static const unsigned int msiof4_ss1_pins[] = { + /* MSIOF4_SS1 */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int msiof4_ss1_mux[] = { + MSIOF4_SS1_MARK, +}; +static const unsigned int msiof4_ss2_pins[] = { + /* MSIOF4_SS2 */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int msiof4_ss2_mux[] = { + MSIOF4_SS2_MARK, +}; +static const unsigned int msiof4_txd_pins[] = { + /* MSIOF4_TXD */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int msiof4_txd_mux[] = { + MSIOF4_TXD_MARK, +}; +static const unsigned int msiof4_rxd_pins[] = { + /* MSIOF4_RXD */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int msiof4_rxd_mux[] = { + MSIOF4_RXD_MARK, +}; + +/* - MSIOF5 ----------------------------------------------------------------- */ +static const unsigned int msiof5_clk_pins[] = { + /* MSIOF5_SCK */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int msiof5_clk_mux[] = { + MSIOF5_SCK_MARK, +}; +static const unsigned int msiof5_sync_pins[] = { + /* MSIOF5_SYNC */ + RCAR_GP_PIN(0, 9), +}; +static const unsigned int msiof5_sync_mux[] = { + MSIOF5_SYNC_MARK, +}; +static const unsigned int msiof5_ss1_pins[] = { + /* MSIOF5_SS1 */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int msiof5_ss1_mux[] = { + MSIOF5_SS1_MARK, +}; +static const unsigned int msiof5_ss2_pins[] = { + /* MSIOF5_SS2 */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int msiof5_ss2_mux[] = { + MSIOF5_SS2_MARK, +}; +static const unsigned int msiof5_txd_pins[] = { + /* MSIOF5_TXD */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int msiof5_txd_mux[] = { + MSIOF5_TXD_MARK, +}; +static const unsigned int msiof5_rxd_pins[] = { + /* MSIOF5_RXD */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int msiof5_rxd_mux[] = { + MSIOF5_RXD_MARK, +}; + +/* - PCIE ------------------------------------------------------------------- */ +static const unsigned int pcie0_clkreq_n_pins[] = { + /* PCIE0_CLKREQ_N */ + RCAR_GP_PIN(4, 21), +}; + +static const unsigned int pcie0_clkreq_n_mux[] = { + PCIE0_CLKREQ_N_MARK, +}; + +/* - PWM0_A ------------------------------------------------------------------- */ +static const unsigned int pwm0_a_pins[] = { + /* PWM0_A */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int pwm0_a_mux[] = { + PWM0_A_MARK, +}; + +/* - PWM0_B ------------------------------------------------------------------- */ +static const unsigned int pwm0_b_pins[] = { + /* PWM0_B */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; + +/* - PWM1_A ------------------------------------------------------------------- */ +static const unsigned int pwm1_a_pins[] = { + /* PWM1_A */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int pwm1_a_mux[] = { + PWM1_A_MARK, +}; + +/* - PWM1_B ------------------------------------------------------------------- */ +static const unsigned int pwm1_b_pins[] = { + /* PWM1_B */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; + +/* - PWM1_C ------------------------------------------------------------------- */ +static const unsigned int pwm1_c_pins[] = { + /* PWM1_C */ + RCAR_GP_PIN(2, 17), +}; +static const unsigned int pwm1_c_mux[] = { + PWM1_C_MARK, +}; + +/* - PWM2_A ------------------------------------------------------------------- */ +static const unsigned int pwm2_a_pins[] = { + /* PWM2_A */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int pwm2_a_mux[] = { + PWM2_A_MARK, +}; + +/* - PWM2_B ------------------------------------------------------------------- */ +static const unsigned int pwm2_b_pins[] = { + /* PWM2_B */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; + +/* - PWM2_C ------------------------------------------------------------------- */ +static const unsigned int pwm2_c_pins[] = { + /* PWM2_C */ + RCAR_GP_PIN(2, 19), +}; +static const unsigned int pwm2_c_mux[] = { + PWM2_C_MARK, +}; + +/* - PWM3_A ------------------------------------------------------------------- */ +static const unsigned int pwm3_a_pins[] = { + /* PWM3_A */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int pwm3_a_mux[] = { + PWM3_A_MARK, +}; + +/* - PWM3_B ------------------------------------------------------------------- */ +static const unsigned int pwm3_b_pins[] = { + /* PWM3_B */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; + +/* - PWM3_C ------------------------------------------------------------------- */ +static const unsigned int pwm3_c_pins[] = { + /* PWM3_C */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int pwm3_c_mux[] = { + PWM3_C_MARK, +}; + +/* - PWM4 ------------------------------------------------------------------- */ +static const unsigned int pwm4_pins[] = { + /* PWM4 */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; + +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), +}; +static const unsigned int qspi0_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26), +}; +static const unsigned int qspi1_data_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX0, TX0 */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK0 */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS0_N, CTS0_N */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_MARK, CTS0_N_MARK, +}; + +/* - SCIF1_A ------------------------------------------------------------------ */ +static const unsigned int scif1_data_a_pins[] = { + /* RX1_A, TX1_A */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), +}; +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, +}; +static const unsigned int scif1_clk_a_pins[] = { + /* SCK1_A */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int scif1_clk_a_mux[] = { + SCK1_A_MARK, +}; +static const unsigned int scif1_ctrl_a_pins[] = { + /* RTS1_N_A, CTS1_N_A */ + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), +}; +static const unsigned int scif1_ctrl_a_mux[] = { + RTS1_N_A_MARK, CTS1_N_A_MARK, +}; + +/* - SCIF1_B ------------------------------------------------------------------ */ +static const unsigned int scif1_data_b_pins[] = { + /* RX1_B, TX1_B */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_clk_b_pins[] = { + /* SCK1_B */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int scif1_clk_b_mux[] = { + SCK1_B_MARK, +}; +static const unsigned int scif1_ctrl_b_pins[] = { + /* RTS1_N_B, CTS1_N_B */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), +}; +static const unsigned int scif1_ctrl_b_mux[] = { + RTS1_N_B_MARK, CTS1_N_B_MARK, +}; + +/* - SCIF3_A ------------------------------------------------------------------ */ +static const unsigned int scif3_data_a_pins[] = { + /* RX3_A, TX3_A */ + RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28), +}; +static const unsigned int scif3_data_a_mux[] = { + RX3_A_MARK, TX3_A_MARK, +}; +static const unsigned int scif3_clk_a_pins[] = { + /* SCK3_A */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int scif3_clk_a_mux[] = { + SCK3_A_MARK, +}; +static const unsigned int scif3_ctrl_a_pins[] = { + /* RTS3_N_A, CTS3_N_A */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int scif3_ctrl_a_mux[] = { + RTS3_N_A_MARK, CTS3_N_A_MARK, +}; + +/* - SCIF3_B ------------------------------------------------------------------ */ +static const unsigned int scif3_data_b_pins[] = { + /* RX3_B, TX3_B */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_MARK, TX3_B_MARK, +}; +static const unsigned int scif3_clk_b_pins[] = { + /* SCK3_B */ + RCAR_GP_PIN(1, 4), +}; +static const unsigned int scif3_clk_b_mux[] = { + SCK3_B_MARK, +}; +static const unsigned int scif3_ctrl_b_pins[] = { + /* RTS3_N_B, CTS3_N_B */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int scif3_ctrl_b_mux[] = { + RTS3_N_B_MARK, CTS3_N_B_MARK, +}; + +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX4, TX4 */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12), +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_clk_pins[] = { + /* SCK4 */ + RCAR_GP_PIN(4, 8), +}; +static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, +}; +static const unsigned int scif4_ctrl_pins[] = { + /* RTS4_N, CTS4_N */ + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 9), +}; +static const unsigned int scif4_ctrl_mux[] = { + RTS4_N_MARK, CTS4_N_MARK, +}; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; + +static const unsigned int scif_clk2_pins[] = { + /* SCIF_CLK2 */ + RCAR_GP_PIN(4, 11), +}; +static const unsigned int scif_clk2_mux[] = { + SCIF_CLK2_MARK, +}; + +/* - SSI ------------------------------------------------- */ +static const unsigned int ssi_data_pins[] = { + /* SSI_SD */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int ssi_data_mux[] = { + SSI_SD_MARK, +}; +static const unsigned int ssi_ctrl_pins[] = { + /* SSI_SCK, SSI_WS */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +}; +static const unsigned int ssi_ctrl_mux[] = { + SSI_SCK_MARK, SSI_WS_MARK, +}; + +/* - TPU_A ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_a_pins[] = { + /* TPU0TO0_A */ + RCAR_GP_PIN(2, 8), +}; +static const unsigned int tpu_to0_a_mux[] = { + TPU0TO0_A_MARK, +}; +static const unsigned int tpu_to1_a_pins[] = { + /* TPU0TO1_A */ + RCAR_GP_PIN(2, 7), +}; +static const unsigned int tpu_to1_a_mux[] = { + TPU0TO1_A_MARK, +}; +static const unsigned int tpu_to2_a_pins[] = { + /* TPU0TO2_A */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int tpu_to2_a_mux[] = { + TPU0TO2_A_MARK, +}; +static const unsigned int tpu_to3_a_pins[] = { + /* TPU0TO3_A */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int tpu_to3_a_mux[] = { + TPU0TO3_A_MARK, +}; + +/* - TPU_B ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_b_pins[] = { + /* TPU0TO0_B */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int tpu_to0_b_mux[] = { + TPU0TO0_B_MARK, +}; +static const unsigned int tpu_to1_b_pins[] = { + /* TPU0TO1_B */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int tpu_to1_b_mux[] = { + TPU0TO1_B_MARK, +}; +static const unsigned int tpu_to2_b_pins[] = { + /* TPU0TO2_B */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int tpu_to2_b_mux[] = { + TPU0TO2_B_MARK, +}; +static const unsigned int tpu_to3_b_pins[] = { + /* TPU0TO3_B */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int tpu_to3_b_mux[] = { + TPU0TO3_B_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clkin), + SH_PFC_PIN_GROUP(audio_clkout), + + SH_PFC_PIN_GROUP(avb0_link), + SH_PFC_PIN_GROUP(avb0_magic), + SH_PFC_PIN_GROUP(avb0_phy_int), + SH_PFC_PIN_GROUP(avb0_mdio), + SH_PFC_PIN_GROUP(avb0_rgmii), + SH_PFC_PIN_GROUP(avb0_txcrefclk), + SH_PFC_PIN_GROUP(avb0_avtp_pps), + SH_PFC_PIN_GROUP(avb0_avtp_capture), + SH_PFC_PIN_GROUP(avb0_avtp_match), + + SH_PFC_PIN_GROUP(avb1_link), + SH_PFC_PIN_GROUP(avb1_magic), + SH_PFC_PIN_GROUP(avb1_phy_int), + SH_PFC_PIN_GROUP(avb1_mdio), + SH_PFC_PIN_GROUP(avb1_rgmii), + SH_PFC_PIN_GROUP(avb1_txcrefclk), + SH_PFC_PIN_GROUP(avb1_avtp_pps), + SH_PFC_PIN_GROUP(avb1_avtp_capture), + SH_PFC_PIN_GROUP(avb1_avtp_match), + + SH_PFC_PIN_GROUP(avb2_link), + SH_PFC_PIN_GROUP(avb2_magic), + SH_PFC_PIN_GROUP(avb2_phy_int), + SH_PFC_PIN_GROUP(avb2_mdio), + SH_PFC_PIN_GROUP(avb2_rgmii), + SH_PFC_PIN_GROUP(avb2_txcrefclk), + SH_PFC_PIN_GROUP(avb2_avtp_pps), + SH_PFC_PIN_GROUP(avb2_avtp_capture), + SH_PFC_PIN_GROUP(avb2_avtp_match), + + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(canfd2_data), + SH_PFC_PIN_GROUP(canfd3_data), + SH_PFC_PIN_GROUP(can_clk), + + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk_a), + SH_PFC_PIN_GROUP(hscif3_ctrl_a), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_clk_b), + SH_PFC_PIN_GROUP(hscif3_ctrl_b), + + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c3), + + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_cd), + SH_PFC_PIN_GROUP(mmc_wp), + SH_PFC_PIN_GROUP(mmc_ds), + + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_txd), + SH_PFC_PIN_GROUP(msiof1_rxd), + + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_txd), + SH_PFC_PIN_GROUP(msiof2_rxd), + + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_txd), + SH_PFC_PIN_GROUP(msiof3_rxd), + + SH_PFC_PIN_GROUP(msiof4_clk), + SH_PFC_PIN_GROUP(msiof4_sync), + SH_PFC_PIN_GROUP(msiof4_ss1), + SH_PFC_PIN_GROUP(msiof4_ss2), + SH_PFC_PIN_GROUP(msiof4_txd), + SH_PFC_PIN_GROUP(msiof4_rxd), + + SH_PFC_PIN_GROUP(msiof5_clk), + SH_PFC_PIN_GROUP(msiof5_sync), + SH_PFC_PIN_GROUP(msiof5_ss1), + SH_PFC_PIN_GROUP(msiof5_ss2), + SH_PFC_PIN_GROUP(msiof5_txd), + SH_PFC_PIN_GROUP(msiof5_rxd), + + SH_PFC_PIN_GROUP(pcie0_clkreq_n), + + SH_PFC_PIN_GROUP(pwm0_a), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm1_c), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm2_c), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm3_c), + SH_PFC_PIN_GROUP(pwm4), + + SH_PFC_PIN_GROUP(qspi0_ctrl), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), + + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk_a), + SH_PFC_PIN_GROUP(scif1_ctrl_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_ctrl_b), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk_a), + SH_PFC_PIN_GROUP(scif3_ctrl_a), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_clk_b), + SH_PFC_PIN_GROUP(scif3_ctrl_b), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_clk), + SH_PFC_PIN_GROUP(scif4_ctrl), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk2), + + SH_PFC_PIN_GROUP(ssi_data), + SH_PFC_PIN_GROUP(ssi_ctrl), + + SH_PFC_PIN_GROUP(tpu_to0_a), + SH_PFC_PIN_GROUP(tpu_to0_b), + SH_PFC_PIN_GROUP(tpu_to1_a), + SH_PFC_PIN_GROUP(tpu_to1_b), + SH_PFC_PIN_GROUP(tpu_to2_a), + SH_PFC_PIN_GROUP(tpu_to2_b), + SH_PFC_PIN_GROUP(tpu_to3_a), + SH_PFC_PIN_GROUP(tpu_to3_b), +}; + +static const char * const audio_clk_groups[] = { + "audio_clkin", + "audio_clkout", +}; + +static const char * const avb0_groups[] = { + "avb0_link", + "avb0_magic", + "avb0_phy_int", + "avb0_mdio", + "avb0_rgmii", + "avb0_txcrefclk", + "avb0_avtp_pps", + "avb0_avtp_capture", + "avb0_avtp_match", +}; + +static const char * const avb1_groups[] = { + "avb1_link", + "avb1_magic", + "avb1_phy_int", + "avb1_mdio", + "avb1_rgmii", + "avb1_txcrefclk", + "avb1_avtp_pps", + "avb1_avtp_capture", + "avb1_avtp_match", +}; + +static const char * const avb2_groups[] = { + "avb2_link", + "avb2_magic", + "avb2_phy_int", + "avb2_mdio", + "avb2_rgmii", + "avb2_txcrefclk", + "avb2_avtp_pps", + "avb2_avtp_capture", + "avb2_avtp_match", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + +static const char * const canfd2_groups[] = { + "canfd2_data", +}; + +static const char * const canfd3_groups[] = { + "canfd3_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_ctrl_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data_a", + "hscif3_clk_a", + "hscif3_ctrl_a", + "hscif3_data_b", + "hscif3_clk_b", + "hscif3_ctrl_b", +}; + +static const char * const i2c0_groups[] = { + "i2c0", +}; + +static const char * const i2c1_groups[] = { + "i2c1", +}; + +static const char * const i2c2_groups[] = { + "i2c2", +}; + +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", + "mmc_cd", + "mmc_wp", + "mmc_ds", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk", + "msiof3_sync", + "msiof3_ss1", + "msiof3_ss2", + "msiof3_txd", + "msiof3_rxd", +}; + +static const char * const msiof4_groups[] = { + "msiof4_clk", + "msiof4_sync", + "msiof4_ss1", + "msiof4_ss2", + "msiof4_txd", + "msiof4_rxd", +}; + +static const char * const msiof5_groups[] = { + "msiof5_clk", + "msiof5_sync", + "msiof5_ss1", + "msiof5_ss2", + "msiof5_txd", + "msiof5_rxd", +}; + +static const char * const pcie_groups[] = { + "pcie0_clkreq_n", +}; + +static const char * const pwm0_groups[] = { + "pwm0_a", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1_a", + "pwm1_b", + "pwm1_c", +}; + +static const char * const pwm2_groups[] = { + "pwm2_a", + "pwm2_b", + "pwm2_c", +}; + +static const char * const pwm3_groups[] = { + "pwm3_a", + "pwm3_b", + "pwm3_c", +}; + +static const char * const pwm4_groups[] = { + "pwm4", +}; + +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_clk_a", + "scif1_ctrl_a", + "scif1_data_b", + "scif1_clk_b", + "scif1_ctrl_b", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_clk_a", + "scif3_ctrl_a", + "scif3_data_b", + "scif3_clk_b", + "scif3_ctrl_b", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_clk", + "scif4_ctrl", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const scif_clk2_groups[] = { + "scif_clk2", +}; + +static const char * const ssi_groups[] = { + "ssi_data", + "ssi_ctrl", +}; + +static const char * const tpu_groups[] = { + "tpu_to0_a", + "tpu_to0_b", + "tpu_to1_a", + "tpu_to1_b", + "tpu_to2_a", + "tpu_to2_b", + "tpu_to3_a", + "tpu_to3_b", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + + SH_PFC_FUNCTION(avb0), + SH_PFC_FUNCTION(avb1), + SH_PFC_FUNCTION(avb2), + + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(canfd2), + SH_PFC_FUNCTION(canfd3), + SH_PFC_FUNCTION(can_clk), + + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + + SH_PFC_FUNCTION(mmc), + + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(msiof4), + SH_PFC_FUNCTION(msiof5), + + SH_PFC_FUNCTION(pcie), + + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), + + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(scif_clk2), + + SH_PFC_FUNCTION(ssi), + + SH_PFC_FUNCTION(tpu), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32, + GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_19 RESERVED */ + GP_0_18_FN, GPSR0_18, + GP_0_17_FN, GPSR0_17, + GP_0_16_FN, GPSR0_16, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, )) + }, + { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP( + 0, 0, + 0, 0, + GP_1_29_FN, GPSR1_29, + GP_1_28_FN, GPSR1_28, + GP_1_27_FN, GPSR1_27, + GP_1_26_FN, GPSR1_26, + GP_1_25_FN, GPSR1_25, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, )) + }, + { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32, + GROUP(-12, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP2_31_20 RESERVED */ + GP_2_19_FN, GPSR2_19, + /* GP2_18 RESERVED */ + GP_2_17_FN, GPSR2_17, + /* GP2_16 RESERVED */ + GP_2_15_FN, GPSR2_15, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, )) + }, + { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP( + GP_3_31_FN, GPSR3_31, + GP_3_30_FN, GPSR3_30, + GP_3_29_FN, GPSR3_29, + GP_3_28_FN, GPSR3_28, + GP_3_27_FN, GPSR3_27, + GP_3_26_FN, GPSR3_26, + GP_3_25_FN, GPSR3_25, + GP_3_24_FN, GPSR3_24, + GP_3_23_FN, GPSR3_23, + GP_3_22_FN, GPSR3_22, + GP_3_21_FN, GPSR3_21, + GP_3_20_FN, GPSR3_20, + GP_3_19_FN, GPSR3_19, + GP_3_18_FN, GPSR3_18, + GP_3_17_FN, GPSR3_17, + GP_3_16_FN, GPSR3_16, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, )) + }, + { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060040, 32, + GROUP(-7, 1, 1, -1, 1, -5, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP4_31_25 RESERVED */ + GP_4_24_FN, GPSR4_24, + GP_4_23_FN, GPSR4_23, + /* GP4_22 RESERVED */ + GP_4_21_FN, GPSR4_21, + /* GP4_20_16 RESERVED */ + GP_4_15_FN, GPSR4_15, + GP_4_14_FN, GPSR4_14, + GP_4_13_FN, GPSR4_13, + GP_4_12_FN, GPSR4_12, + GP_4_11_FN, GPSR4_11, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, )) + }, + { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP5_31_21 RESERVED */ + GP_5_20_FN, GPSR5_20, + GP_5_19_FN, GPSR5_19, + GP_5_18_FN, GPSR5_18, + GP_5_17_FN, GPSR5_17, + GP_5_16_FN, GPSR5_16, + GP_5_15_FN, GPSR5_15, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, )) + }, + { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP6_31_21 RESERVED */ + GP_6_20_FN, GPSR6_20, + GP_6_19_FN, GPSR6_19, + GP_6_18_FN, GPSR6_18, + GP_6_17_FN, GPSR6_17, + GP_6_16_FN, GPSR6_16, + GP_6_15_FN, GPSR6_15, + GP_6_14_FN, GPSR6_14, + GP_6_13_FN, GPSR6_13, + GP_6_12_FN, GPSR6_12, + GP_6_11_FN, GPSR6_11, + GP_6_10_FN, GPSR6_10, + GP_6_9_FN, GPSR6_9, + GP_6_8_FN, GPSR6_8, + GP_6_7_FN, GPSR6_7, + GP_6_6_FN, GPSR6_6, + GP_6_5_FN, GPSR6_5, + GP_6_4_FN, GPSR6_4, + GP_6_3_FN, GPSR6_3, + GP_6_2_FN, GPSR6_2, + GP_6_1_FN, GPSR6_1, + GP_6_0_FN, GPSR6_0, )) + }, + { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP7_31_21 RESERVED */ + GP_7_20_FN, GPSR7_20, + GP_7_19_FN, GPSR7_19, + GP_7_18_FN, GPSR7_18, + GP_7_17_FN, GPSR7_17, + GP_7_16_FN, GPSR7_16, + GP_7_15_FN, GPSR7_15, + GP_7_14_FN, GPSR7_14, + GP_7_13_FN, GPSR7_13, + GP_7_12_FN, GPSR7_12, + GP_7_11_FN, GPSR7_11, + GP_7_10_FN, GPSR7_10, + GP_7_9_FN, GPSR7_9, + GP_7_8_FN, GPSR7_8, + GP_7_7_FN, GPSR7_7, + GP_7_6_FN, GPSR7_6, + GP_7_5_FN, GPSR7_5, + GP_7_4_FN, GPSR7_4, + GP_7_3_FN, GPSR7_3, + GP_7_2_FN, GPSR7_2, + GP_7_1_FN, GPSR7_1, + GP_7_0_FN, GPSR7_0, )) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP( + IP0SR0_31_28 + IP0SR0_27_24 + IP0SR0_23_20 + IP0SR0_19_16 + IP0SR0_15_12 + IP0SR0_11_8 + IP0SR0_7_4 + IP0SR0_3_0)) + }, + { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP( + IP1SR0_31_28 + IP1SR0_27_24 + IP1SR0_23_20 + IP1SR0_19_16 + IP1SR0_15_12 + IP1SR0_11_8 + IP1SR0_7_4 + IP1SR0_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32, + GROUP(-20, 4, 4, 4), + GROUP( + /* IP2SR0_31_12 RESERVED */ + IP2SR0_11_8 + IP2SR0_7_4 + IP2SR0_3_0)) + }, + { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP( + IP0SR1_31_28 + IP0SR1_27_24 + IP0SR1_23_20 + IP0SR1_19_16 + IP0SR1_15_12 + IP0SR1_11_8 + IP0SR1_7_4 + IP0SR1_3_0)) + }, + { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP( + IP1SR1_31_28 + IP1SR1_27_24 + IP1SR1_23_20 + IP1SR1_19_16 + IP1SR1_15_12 + IP1SR1_11_8 + IP1SR1_7_4 + IP1SR1_3_0)) + }, + { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP( + IP2SR1_31_28 + IP2SR1_27_24 + IP2SR1_23_20 + IP2SR1_19_16 + IP2SR1_15_12 + IP2SR1_11_8 + IP2SR1_7_4 + IP2SR1_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32, + GROUP(-8, 4, 4, 4, 4, 4, 4), + GROUP( + /* IP3SR1_31_24 RESERVED */ + IP3SR1_23_20 + IP3SR1_19_16 + IP3SR1_15_12 + IP3SR1_11_8 + IP3SR1_7_4 + IP3SR1_3_0)) + }, + { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP( + IP0SR2_31_28 + IP0SR2_27_24 + IP0SR2_23_20 + IP0SR2_19_16 + IP0SR2_15_12 + IP0SR2_11_8 + IP0SR2_7_4 + IP0SR2_3_0)) + }, + { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP( + IP1SR2_31_28 + IP1SR2_27_24 + IP1SR2_23_20 + IP1SR2_19_16 + IP1SR2_15_12 + IP1SR2_11_8 + IP1SR2_7_4 + IP1SR2_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32, + GROUP(-16, 4, -4, 4, -4), + GROUP( + /* IP2SR2_31_16 RESERVED */ + IP2SR2_15_12 + /* IP2SR2_11_8 RESERVED */ + IP2SR2_7_4 + /* IP2SR2_3_0 RESERVED */)) + }, + { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP( + IP0SR3_31_28 + IP0SR3_27_24 + IP0SR3_23_20 + IP0SR3_19_16 + IP0SR3_15_12 + IP0SR3_11_8 + IP0SR3_7_4 + IP0SR3_3_0)) + }, + { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP( + IP1SR3_31_28 + IP1SR3_27_24 + IP1SR3_23_20 + IP1SR3_19_16 + IP1SR3_15_12 + IP1SR3_11_8 + IP1SR3_7_4 + IP1SR3_3_0)) + }, + { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP( + IP2SR3_31_28 + IP2SR3_27_24 + IP2SR3_23_20 + IP2SR3_19_16 + IP2SR3_15_12 + IP2SR3_11_8 + IP2SR3_7_4 + IP2SR3_3_0)) + }, + { PINMUX_CFG_REG("IP3SR3", 0xE605886C, 32, 4, GROUP( + IP3SR3_31_28 + IP3SR3_27_24 + IP3SR3_23_20 + IP3SR3_19_16 + IP3SR3_15_12 + IP3SR3_11_8 + IP3SR3_7_4 + IP3SR3_3_0)) + }, + { PINMUX_CFG_REG("IP0SR4", 0xE6060060, 32, 4, GROUP( + IP0SR4_31_28 + IP0SR4_27_24 + IP0SR4_23_20 + IP0SR4_19_16 + IP0SR4_15_12 + IP0SR4_11_8 + IP0SR4_7_4 + IP0SR4_3_0)) + }, + { PINMUX_CFG_REG("IP1SR4", 0xE6060064, 32, 4, GROUP( + IP1SR4_31_28 + IP1SR4_27_24 + IP1SR4_23_20 + IP1SR4_19_16 + IP1SR4_15_12 + IP1SR4_11_8 + IP1SR4_7_4 + IP1SR4_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32, + GROUP(4, -4, 4, -20), + GROUP( + IP2SR4_31_28 + /* IP2SR4_27_24 RESERVED */ + IP2SR4_23_20 + /* IP2SR4_19_0 RESERVED */)) + }, + { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32, + GROUP(-28, 4), + GROUP( + /* IP3SR4_31_4 RESERVED */ + IP3SR4_3_0)) + }, + { PINMUX_CFG_REG("IP0SR5", 0xE6060860, 32, 4, GROUP( + IP0SR5_31_28 + IP0SR5_27_24 + IP0SR5_23_20 + IP0SR5_19_16 + IP0SR5_15_12 + IP0SR5_11_8 + IP0SR5_7_4 + IP0SR5_3_0)) + }, + { PINMUX_CFG_REG("IP1SR5", 0xE6060864, 32, 4, GROUP( + IP1SR5_31_28 + IP1SR5_27_24 + IP1SR5_23_20 + IP1SR5_19_16 + IP1SR5_15_12 + IP1SR5_11_8 + IP1SR5_7_4 + IP1SR5_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32, + GROUP(-12, 4, 4, 4, 4, 4), + GROUP( + /* IP2SR5_31_20 RESERVED */ + IP2SR5_19_16 + IP2SR5_15_12 + IP2SR5_11_8 + IP2SR5_7_4 + IP2SR5_3_0)) + }, + { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP( + IP0SR6_31_28 + IP0SR6_27_24 + IP0SR6_23_20 + IP0SR6_19_16 + IP0SR6_15_12 + IP0SR6_11_8 + IP0SR6_7_4 + IP0SR6_3_0)) + }, + { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP( + IP1SR6_31_28 + IP1SR6_27_24 + IP1SR6_23_20 + IP1SR6_19_16 + IP1SR6_15_12 + IP1SR6_11_8 + IP1SR6_7_4 + IP1SR6_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32, + GROUP(-12, 4, 4, 4, 4, 4), + GROUP( + /* IP2SR6_31_20 RESERVED */ + IP2SR6_19_16 + IP2SR6_15_12 + IP2SR6_11_8 + IP2SR6_7_4 + IP2SR6_3_0)) + }, + { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP( + IP0SR7_31_28 + IP0SR7_27_24 + IP0SR7_23_20 + IP0SR7_19_16 + IP0SR7_15_12 + IP0SR7_11_8 + IP0SR7_7_4 + IP0SR7_3_0)) + }, + { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP( + IP1SR7_31_28 + IP1SR7_27_24 + IP1SR7_23_20 + IP1SR7_19_16 + IP1SR7_15_12 + IP1SR7_11_8 + IP1SR7_7_4 + IP1SR7_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32, + GROUP(-12, 4, 4, 4, 4, 4), + GROUP( + /* IP2SR7_31_20 RESERVED */ + IP2SR7_19_16 + IP2SR7_15_12 + IP2SR7_11_8 + IP2SR7_7_4 + IP2SR7_3_0)) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32, + GROUP(-24, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* RESERVED 31-8 */ + MOD_SEL4_7 + MOD_SEL4_6 + MOD_SEL4_5 + MOD_SEL4_4 + MOD_SEL4_3 + MOD_SEL4_2 + MOD_SEL4_1 + MOD_SEL4_0)) + }, + { }, +}; + +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) { + { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */ + { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */ + { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */ + { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */ + { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */ + { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */ + { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */ + { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) { + { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */ + { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */ + { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */ + { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */ + { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */ + { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */ + { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */ + { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) { + { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */ + { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */ + { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) { + { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */ + { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */ + { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */ + { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */ + { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */ + { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */ + { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) { + { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */ + { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */ + { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */ + { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */ + { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */ + { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */ + { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) { + { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */ + { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */ + { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */ + { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */ + { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */ + { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */ + { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */ + { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) { + { RCAR_GP_PIN(1, 29), 20, 2 }, /* ERROROUTC_N */ + { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */ + { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */ + { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */ + { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */ + { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) { + { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */ + { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */ + { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */ + { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */ + { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */ + { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */ + { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */ + { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) { + { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */ + { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */ + { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */ + { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */ + { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */ + { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */ + { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */ + { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) { + { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD1_RX */ + { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD1_TX */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) { + { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */ + { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */ + { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */ + { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */ + { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */ + { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */ + { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */ + { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) { + { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */ + { RCAR_GP_PIN(3, 14), 24, 2 }, /* PWM2 */ + { RCAR_GP_PIN(3, 13), 20, 2 }, /* PWM1 */ + { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */ + { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */ + { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */ + { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/ + { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) { + { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */ + { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */ + { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */ + { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */ + { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */ + { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */ + { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */ + { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) { + { RCAR_GP_PIN(3, 31), 28, 2 }, /* TCLK4 */ + { RCAR_GP_PIN(3, 30), 24, 2 }, /* TCLK3 */ + { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */ + { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */ + { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */ + { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */ + { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */ + { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) { + { RCAR_GP_PIN(4, 7), 28, 3 }, /* SDA3 */ + { RCAR_GP_PIN(4, 6), 24, 3 }, /* SCL3 */ + { RCAR_GP_PIN(4, 5), 20, 3 }, /* SDA2 */ + { RCAR_GP_PIN(4, 4), 16, 3 }, /* SCL2 */ + { RCAR_GP_PIN(4, 3), 12, 3 }, /* SDA1 */ + { RCAR_GP_PIN(4, 2), 8, 3 }, /* SCL1 */ + { RCAR_GP_PIN(4, 1), 4, 3 }, /* SDA0 */ + { RCAR_GP_PIN(4, 0), 0, 3 }, /* SCL0 */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) { + { RCAR_GP_PIN(4, 15), 28, 3 }, /* PWM4 */ + { RCAR_GP_PIN(4, 14), 24, 3 }, /* PWM3 */ + { RCAR_GP_PIN(4, 13), 20, 3 }, /* HSCK2 */ + { RCAR_GP_PIN(4, 12), 16, 3 }, /* HCTS2_N */ + { RCAR_GP_PIN(4, 11), 12, 3 }, /* SCIF_CLK2 */ + { RCAR_GP_PIN(4, 10), 8, 3 }, /* HRTS2_N */ + { RCAR_GP_PIN(4, 9), 4, 3 }, /* HTX2 */ + { RCAR_GP_PIN(4, 8), 0, 3 }, /* HRX2 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) { + { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */ + { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) { + { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) { + { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */ + { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */ + { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */ + { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */ + { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */ + { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */ + { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */ + { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) { + { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */ + { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */ + { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */ + { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */ + { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */ + { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */ + { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */ + { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) { + { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */ + { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */ + { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */ + { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */ + { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) { + { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */ + { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */ + { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */ + { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */ + { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */ + { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */ + { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */ + { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) { + { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */ + { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */ + { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */ + { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */ + { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */ + { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */ + { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */ + { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) { + { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */ + { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */ + { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */ + { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */ + { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) { + { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */ + { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */ + { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */ + { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */ + { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */ + { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */ + { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */ + { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) { + { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */ + { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */ + { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */ + { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */ + { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */ + { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */ + { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */ + { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) { + { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */ + { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */ + { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */ + { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */ + { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */ + } }, + { }, +}; + +enum ioctrl_regs { + POC0, + POC1, + POC3, + POC4, + POC5, + POC6, + POC7, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POC0] = { 0xE60500A0, }, + [POC1] = { 0xE60508A0, }, + [POC3] = { 0xE60588A0, }, + [POC4] = { 0xE60600A0, }, + [POC5] = { 0xE60608A0, }, + [POC6] = { 0xE60610A0, }, + [POC7] = { 0xE60618A0, }, + { /* sentinel */ }, +}; + +static int r8a779h0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) +{ + int bit = pin & 0x1f; + + switch (pin) { + case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18): + *pocctrl = pinmux_ioctrl_regs[POC0].reg; + return bit; + + case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 28): + *pocctrl = pinmux_ioctrl_regs[POC1].reg; + return bit; + + case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12): + *pocctrl = pinmux_ioctrl_regs[POC3].reg; + return bit; + + case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 13): + *pocctrl = pinmux_ioctrl_regs[POC4].reg; + return bit; + + case PIN_VDDQ_AVB2: + *pocctrl = pinmux_ioctrl_regs[POC5].reg; + return 0; + + case PIN_VDDQ_AVB1: + *pocctrl = pinmux_ioctrl_regs[POC6].reg; + return 0; + + case PIN_VDDQ_AVB0: + *pocctrl = pinmux_ioctrl_regs[POC7].reg; + return 0; + + default: + return -EINVAL; + } +} + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) { + [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */ + [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */ + [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */ + [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */ + [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */ + [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */ + [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */ + [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */ + [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */ + [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */ + [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */ + [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */ + [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */ + [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */ + [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */ + [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */ + [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */ + [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */ + [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */ + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) { + [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */ + [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */ + [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */ + [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */ + [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */ + [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */ + [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */ + [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */ + [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */ + [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */ + [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */ + [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */ + [12] = RCAR_GP_PIN(1, 12), /* HTX0 */ + [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */ + [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */ + [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */ + [16] = RCAR_GP_PIN(1, 16), /* HRX0 */ + [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */ + [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */ + [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */ + [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */ + [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */ + [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */ + [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */ + [24] = RCAR_GP_PIN(1, 24), /* HRX3 */ + [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */ + [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */ + [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */ + [28] = RCAR_GP_PIN(1, 28), /* HTX3 */ + [29] = RCAR_GP_PIN(1, 29), /* ERROROUTC_N */ + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) { + [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */ + [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */ + [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */ + [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */ + [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */ + [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */ + [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */ + [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */ + [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */ + [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */ + [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */ + [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */ + [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */ + [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */ + [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */ + [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */ + [16] = SH_PFC_PIN_NONE, + [17] = RCAR_GP_PIN(2, 17), /* CANFD1_TX */ + [18] = SH_PFC_PIN_NONE, + [19] = RCAR_GP_PIN(2, 19), /* CANFD1_RX */ + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) { + [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */ + [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */ + [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */ + [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */ + [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */ + [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */ + [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */ + [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */ + [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */ + [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */ + [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */ + [11] = RCAR_GP_PIN(3, 11), /* SD_CD */ + [12] = RCAR_GP_PIN(3, 12), /* SD_WP */ + [13] = RCAR_GP_PIN(3, 13), /* PWM1 */ + [14] = RCAR_GP_PIN(3, 14), /* PWM2 */ + [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */ + [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */ + [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */ + [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */ + [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */ + [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */ + [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */ + [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */ + [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */ + [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */ + [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */ + [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */ + [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */ + [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */ + [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */ + [30] = RCAR_GP_PIN(3, 30), /* TCLK3 */ + [31] = RCAR_GP_PIN(3, 31), /* TCLK4 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) { + [ 0] = RCAR_GP_PIN(4, 0), /* SCL0 */ + [ 1] = RCAR_GP_PIN(4, 1), /* SDA0 */ + [ 2] = RCAR_GP_PIN(4, 2), /* SCL1 */ + [ 3] = RCAR_GP_PIN(4, 3), /* SDA1 */ + [ 4] = RCAR_GP_PIN(4, 4), /* SCL2 */ + [ 5] = RCAR_GP_PIN(4, 5), /* SDA2 */ + [ 6] = RCAR_GP_PIN(4, 6), /* SCL3 */ + [ 7] = RCAR_GP_PIN(4, 7), /* SDA3 */ + [ 8] = RCAR_GP_PIN(4, 8), /* HRX2 */ + [ 9] = RCAR_GP_PIN(4, 9), /* HTX2 */ + [10] = RCAR_GP_PIN(4, 10), /* HRTS2_N */ + [11] = RCAR_GP_PIN(4, 11), /* SCIF_CLK2 */ + [12] = RCAR_GP_PIN(4, 12), /* HCTS2_N */ + [13] = RCAR_GP_PIN(4, 13), /* HSCK2 */ + [14] = RCAR_GP_PIN(4, 14), /* PWM3 */ + [15] = RCAR_GP_PIN(4, 15), /* PWM4 */ + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */ + [22] = SH_PFC_PIN_NONE, + [23] = RCAR_GP_PIN(4, 23), /* AVS0 */ + [24] = RCAR_GP_PIN(4, 24), /* AVS1 */ + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) { + [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */ + [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */ + [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */ + [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */ + [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */ + [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */ + [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */ + [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */ + [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */ + [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */ + [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */ + [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */ + [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */ + [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */ + [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */ + [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */ + [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */ + [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */ + [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */ + [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */ + [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) { + [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */ + [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */ + [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */ + [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */ + [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */ + [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */ + [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */ + [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */ + [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */ + [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */ + [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */ + [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */ + [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */ + [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */ + [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/ + [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */ + [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */ + [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */ + [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */ + [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */ + [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) { + [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */ + [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */ + [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */ + [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */ + [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */ + [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */ + [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */ + [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */ + [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */ + [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */ + [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */ + [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */ + [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */ + [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */ + [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */ + [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */ + [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */ + [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */ + [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */ + [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */ + [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ }, +}; + +static const struct sh_pfc_soc_operations r8a779h0_pin_ops = { + .pin_to_pocctrl = r8a779h0_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a779h0_pinmux_info = { + .name = "r8a779h0_pfc", + .ops = &r8a779h0_pin_ops, + .unlock_reg = 0x1ff, /* PMMRn mask */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 4ceb5db47ff..96a47daac35 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -44,6 +44,7 @@ enum sh_pfc_model { SH_PFC_R8A779A0, SH_PFC_R8A779F0, SH_PFC_R8A779G0, + SH_PFC_R8A779H0, }; struct sh_pfc_pin_config { @@ -1041,6 +1042,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (model == SH_PFC_R8A779G0) priv->pfc.info = &r8a779g0_pinmux_info; #endif +#ifdef CONFIG_PINCTRL_PFC_R8A779H0 + if (model == SH_PFC_R8A779H0) + priv->pfc.info = &r8a779h0_pinmux_info; +#endif priv->pmx.pfc = &priv->pfc; sh_pfc_init_ranges(&priv->pfc); @@ -1170,6 +1175,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = { .data = SH_PFC_R8A779G0, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A779H0 + { + .compatible = "renesas,pfc-r8a779h0", + .data = SH_PFC_R8A779H0, + }, +#endif { }, }; diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index e6c21176125..79c6125a0d7 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -307,6 +307,7 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; extern const struct sh_pfc_soc_info r8a779f0_pinmux_info; extern const struct sh_pfc_soc_info r8a779g0_pinmux_info; +extern const struct sh_pfc_soc_info r8a779h0_pinmux_info; /* ----------------------------------------------------------------------------- * Helper macros to create pin and port lists diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc new file mode 100644 index 00000000000..295b0871e04 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x561d1219}, + {0x10030703}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000034b}, + 0x000000ff + } + }, + { + .ddr_freq = 1056, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43041010}, /* MSTR */ + {0x00000064, 0x008000b9}, /* RFSHTMG */ + {0x000000d0, 0x00020103}, /* INIT0 */ + {0x000000d4, 0x00690000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x07340401}, /* INIT3 */ + {0x000000e0, 0x00100000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000800}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0f102411}, /* DRAMTMG0 */ + {0x00000104, 0x0004041a}, /* DRAMTMG1 */ + {0x00000108, 0x0608060d}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x08030409}, /* DRAMTMG4 */ + {0x00000114, 0x06060403}, /* DRAMTMG5 */ + {0x00000120, 0x07070d07}, /* DRAMTMG8 */ + {0x00000124, 0x00020309}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07060004}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000614}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x00000010}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x0000000b}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc new file mode 100644 index 00000000000..4b424fb4409 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x4d110a08}, + {0x06020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000232}, + 0x000000ff + } + }, + { + .ddr_freq = 328, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43049010}, /* MSTR */ + {0x00000064, 0x0027003a}, /* RFSHTMG */ + {0x000000d0, 0x00020052}, /* INIT0 */ + {0x000000d4, 0x00220000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x00040000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x09060b06}, /* DRAMTMG0 */ + {0x00000104, 0x00020209}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030206}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x03030b03}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc new file mode 100644 index 00000000000..980be8cf182 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x4d110a0a}, + {0x07020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000232}, + 0x000000ff + } + }, + { + .ddr_freq = 396, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43049010}, /* MSTR */ + {0x00000064, 0x00300046}, /* RFSHTMG */ + {0x000000d0, 0x00020062}, /* INIT0 */ + {0x000000d4, 0x00280000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x00040000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x09070d07}, /* DRAMTMG0 */ + {0x00000104, 0x0002020a}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030206}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x04040b04}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc new file mode 100644 index 00000000000..3bde055e8dd --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x4d120a0d}, + {0x09020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000232}, + 0x000000ff + } + }, + { + .ddr_freq = 528, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43049010}, /* MSTR */ + {0x00000064, 0x0040005d}, /* RFSHTMG */ + {0x000000d0, 0x00020082}, /* INIT0 */ + {0x000000d4, 0x00350000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x00040000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0a0a1209}, /* DRAMTMG0 */ + {0x00000104, 0x0002020e}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030206}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x04040b04}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc new file mode 100644 index 00000000000..c9341166d65 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x4d130a11}, + {0x0c020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000023a}, + 0x000000ff + } + }, + { + .ddr_freq = 664, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43041010}, /* MSTR */ + {0x00000064, 0x00500075}, /* RFSHTMG */ + {0x000000d0, 0x000200a4}, /* INIT0 */ + {0x000000d4, 0x00420000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x01040401}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0b0c160c}, /* DRAMTMG0 */ + {0x00000104, 0x00020211}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030306}, /* DRAMTMG4 */ + {0x00000114, 0x04040302}, /* DRAMTMG5 */ + {0x00000120, 0x05050b05}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc new file mode 100644 index 00000000000..ef2e9347bf6 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x50160d14}, + {0x0e020502}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000033a}, + 0x000000ff + } + }, + { + .ddr_freq = 784, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43041010}, /* MSTR */ + {0x00000064, 0x005f008a}, /* RFSHTMG */ + {0x000000d0, 0x000200c1}, /* INIT0 */ + {0x000000d4, 0x004e0000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x03140401}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0c0e1a0e}, /* DRAMTMG0 */ + {0x00000104, 0x00030314}, /* DRAMTMG1 */ + {0x00000108, 0x0506050b}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x06030307}, /* DRAMTMG4 */ + {0x00000114, 0x04040302}, /* DRAMTMG5 */ + {0x00000120, 0x06060b06}, /* DRAMTMG8 */ + {0x00000124, 0x00020308}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07040003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0600060c}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000c}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc new file mode 100644 index 00000000000..acb33bd315b --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x531a0f17}, + {0x0e020603}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000342}, + 0x000000ff + } + }, + { + .ddr_freq = 924, /* clock rate(MHz) */ + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43041010}, /* MSTR */ + {0x00000064, 0x007000a2}, /* RFSHTMG */ + {0x000000d0, 0x000200e3}, /* INIT0 */ + {0x000000d4, 0x005c0000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x05240401}, /* INIT3 */ + {0x000000e0, 0x00080000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0e0e1f10}, /* DRAMTMG0 */ + {0x00000104, 0x00030317}, /* DRAMTMG1 */ + {0x00000108, 0x0507050c}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x07030308}, /* DRAMTMG4 */ + {0x00000114, 0x05050303}, /* DRAMTMG5 */ + {0x00000120, 0x07070b07}, /* DRAMTMG8 */ + {0x00000124, 0x00020309}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07050003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000610}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008c}, /* PHYREG01 */ + {0x00000014, 0x0000000e}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x0000000a}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram_rv1126.c b/drivers/ram/rockchip/sdram_rv1126.c index 9e1376a940f..0a78e18c732 100644 --- a/drivers/ram/rockchip/sdram_rv1126.c +++ b/drivers/ram/rockchip/sdram_rv1126.c @@ -76,6 +76,14 @@ struct rv1126_sdram_params sdram_configs[] = { # include "sdram-rv1126-lpddr4-detect-784.inc" # include "sdram-rv1126-lpddr4-detect-924.inc" # include "sdram-rv1126-lpddr4-detect-1056.inc" +#elif defined(CONFIG_RAM_ROCKCHIP_DDR4) +# include "sdram-rv1126-ddr4-detect-328.inc" +# include "sdram-rv1126-ddr4-detect-396.inc" +# include "sdram-rv1126-ddr4-detect-528.inc" +# include "sdram-rv1126-ddr4-detect-664.inc" +# include "sdram-rv1126-ddr4-detect-784.inc" +# include "sdram-rv1126-ddr4-detect-924.inc" +# include "sdram-rv1126-ddr4-detect-1056.inc" #else # include "sdram-rv1126-ddr3-detect-328.inc" # include "sdram-rv1126-ddr3-detect-396.inc" diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 7d04dcff54f..801b7645afa 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -257,6 +257,7 @@ static const struct dm_serial_ops s5p_serial_ops = { static const struct udevice_id s5p_serial_ids[] = { { .compatible = "samsung,exynos4210-uart", .data = PORT_S5P }, + { .compatible = "samsung,exynos850-uart", .data = PORT_S5P }, { .compatible = "apple,s5l-uart", .data = PORT_S5L }, { } }; diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 85dac9de78a..03433bc0e6d 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -40,6 +40,7 @@ config SOC_XILINX_VERSAL_NET This allows other drivers to verify the SoC familiy & revision using matching SoC attributes. +source "drivers/soc/samsung/Kconfig" source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 84385650d46..610bf816d40 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # # Makefile for the U-Boot SOC specific device drivers. +obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig new file mode 100644 index 00000000000..737b7ca8cd1 --- /dev/null +++ b/drivers/soc/samsung/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0+ + +menuconfig SOC_SAMSUNG + bool "Samsung SoC drivers support" + +if SOC_SAMSUNG + +config EXYNOS_PMU + bool "Exynos PMU controller driver" + depends on ARCH_EXYNOS + select REGMAP + select SYSCON + help + Enable support for system controller configuration driver. It allows + one to configure system controller registers (e.g. some register in + PMU syscon) by providing register's offset, mask and value. + +config EXYNOS_USI + bool "Exynos USI (Universal Serial Interface) driver" + depends on ARCH_EXYNOS + select MISC + select REGMAP + select SYSCON + help + Enable support for USI block. USI (Universal Serial Interface) is an + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and + ExynosAutoV9. USI block can be configured to provide one of the + following serial protocols: UART, SPI or High Speed I2C. + + This driver allows one to configure USI for desired protocol, which + is usually done in USI node in Device Tree. + +endif diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile new file mode 100644 index 00000000000..0eb3ed8353b --- /dev/null +++ b/drivers/soc/samsung/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o +obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c new file mode 100644 index 00000000000..233ad4a908f --- /dev/null +++ b/drivers/soc/samsung/exynos-pmu.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * Exynos PMU (Power Management Unit) driver. + */ + +#include <dm.h> +#include <errno.h> +#include <regmap.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/err.h> + +#define EXYNOS850_UART_IO_SHARE_CTRL 0x0760 +#define SEL_RXD_AP_UART_SHIFT 16 +#define SEL_RXD_AP_UART_MASK GENMASK(17, 16) +#define SEL_TXD_GPIO_1_SHIFT 20 +#define SEL_TXD_GPIO_1_MASK GENMASK(21, 20) +#define RXD_GPIO_1 0x3 +#define TXD_AP_UART 0x0 + +struct exynos_pmu { + struct udevice *dev; + const struct exynos_pmu_data *pmu_data; + struct regmap *regmap; +}; + +struct exynos_pmu_data { + int (*pmu_init)(struct exynos_pmu *priv); +}; + +static int exynos850_pmu_init(struct exynos_pmu *priv) +{ + ofnode node; + bool uart_debug_1; + unsigned int offset, mask, value; + + node = dev_ofnode(priv->dev); + uart_debug_1 = ofnode_read_bool(node, "samsung,uart-debug-1"); + if (!uart_debug_1) + return 0; + + /* + * If uart1_pins are used for serial, AP UART lines have to be muxed + * in PMU block to UART_DEBUG_1 path (GPIO_1). By default (reset value) + * UART_DEBUG_0 path (uart0_pins) is connected to AP UART lines. + */ + offset = EXYNOS850_UART_IO_SHARE_CTRL; + mask = SEL_RXD_AP_UART_MASK | SEL_TXD_GPIO_1_MASK; + value = RXD_GPIO_1 << SEL_RXD_AP_UART_SHIFT | + TXD_AP_UART << SEL_TXD_GPIO_1_SHIFT; + return regmap_update_bits(priv->regmap, offset, mask, value); +} + +static const struct exynos_pmu_data exynos850_pmu_data = { + .pmu_init = exynos850_pmu_init, +}; + +static int exynos_pmu_bind(struct udevice *dev) +{ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + return 0; +} + +static int exynos_pmu_probe(struct udevice *dev) +{ + ofnode node; + struct exynos_pmu *priv; + + priv = dev_get_priv(dev); + priv->dev = dev; + + node = dev_ofnode(dev); + priv->regmap = syscon_node_to_regmap(node); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->pmu_data = (struct exynos_pmu_data *)dev_get_driver_data(dev); + if (priv->pmu_data && priv->pmu_data->pmu_init) + return priv->pmu_data->pmu_init(priv); + + return 0; +} + +static const struct udevice_id exynos_pmu_ids[] = { + { + .compatible = "samsung,exynos850-pmu", + .data = (ulong)&exynos850_pmu_data + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(exynos_pmu) = { + .name = "exynos-pmu", + .id = UCLASS_NOP, + .of_match = exynos_pmu_ids, + .bind = exynos_pmu_bind, + .probe = exynos_pmu_probe, + .priv_auto = sizeof(struct exynos_pmu), +}; diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c new file mode 100644 index 00000000000..b746a7838e1 --- /dev/null +++ b/drivers/soc/samsung/exynos-usi.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * Samsung Exynos USI driver (Universal Serial Interface). + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> + +#include <dt-bindings/soc/samsung,exynos-usi.h> + +/* USIv2: System Register: SW_CONF register bits */ +#define USI_V2_SW_CONF_NONE 0x0 +#define USI_V2_SW_CONF_UART BIT(0) +#define USI_V2_SW_CONF_SPI BIT(1) +#define USI_V2_SW_CONF_I2C BIT(2) +#define USI_V2_SW_CONF_MASK (USI_V2_SW_CONF_UART | USI_V2_SW_CONF_SPI | \ + USI_V2_SW_CONF_I2C) + +/* USIv2: USI register offsets */ +#define USI_CON 0x04 +#define USI_OPTION 0x08 + +/* USIv2: USI register bits */ +#define USI_CON_RESET BIT(0) +#define USI_OPTION_CLKREQ_ON BIT(1) +#define USI_OPTION_CLKSTOP_ON BIT(2) + +enum exynos_usi_ver { + USI_VER2 = 2, +}; + +struct exynos_usi_variant { + enum exynos_usi_ver ver; /* USI IP-core version */ + unsigned int sw_conf_mask; /* SW_CONF mask for all protocols */ + size_t min_mode; /* first index in exynos_usi_modes[] */ + size_t max_mode; /* last index in exynos_usi_modes[] */ +}; + +struct exynos_usi { + void __iomem *regs; /* USI register map */ + + size_t mode; /* current USI SW_CONF mode index */ + bool clkreq_on; /* always provide clock to IP */ + + /* System Register */ + struct regmap *sysreg; /* System Register map */ + unsigned int sw_conf; /* SW_CONF register offset in sysreg */ + + const struct exynos_usi_variant *data; +}; + +struct exynos_usi_mode { + const char *name; /* mode name */ + unsigned int val; /* mode register value */ +}; + +static const struct exynos_usi_mode exynos_usi_modes[] = { + [USI_V2_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE }, + [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, + [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, + [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, +}; + +static const struct exynos_usi_variant exynos850_usi_data = { + .ver = USI_VER2, + .sw_conf_mask = USI_V2_SW_CONF_MASK, + .min_mode = USI_V2_NONE, + .max_mode = USI_V2_I2C, +}; + +static const struct udevice_id exynos_usi_ids[] = { + { + .compatible = "samsung,exynos850-usi", + .data = (ulong)&exynos850_usi_data, + }, + { } /* sentinel */ +}; + +/** + * exynos_usi_set_sw_conf - Set USI block configuration mode + * @dev: Driver object + * + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core as specified + * in @usi.mode. + * + * Return: 0 on success, or negative error code on failure. + */ +static int exynos_usi_set_sw_conf(struct udevice *dev) +{ + struct exynos_usi *usi = dev_get_priv(dev); + size_t mode = usi->mode; + unsigned int val; + int ret; + + if (mode < usi->data->min_mode || mode > usi->data->max_mode) + return -EINVAL; + + val = exynos_usi_modes[mode].val; + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, + usi->data->sw_conf_mask, val); + if (ret) + return ret; + + dev_dbg(dev, "protocol: %s\n", exynos_usi_modes[mode].name); + + return 0; +} + +/** + * exynos_usi_enable - Initialize USI block + * @usi: USI driver object + * + * USI IP-core start state is "reset" (on startup and after CPU resume). This + * routine enables the USI block by clearing the reset flag. It also configures + * HWACG behavior (needed e.g. for UART Rx). It should be performed before + * underlying protocol becomes functional. + */ +static void exynos_usi_enable(const struct exynos_usi *usi) +{ + u32 val; + + /* Enable USI block */ + val = readl(usi->regs + USI_CON); + val &= ~USI_CON_RESET; + writel(val, usi->regs + USI_CON); + udelay(1); + + /* Continuously provide the clock to USI IP w/o gating */ + if (usi->clkreq_on) { + val = readl(usi->regs + USI_OPTION); + val &= ~USI_OPTION_CLKSTOP_ON; + val |= USI_OPTION_CLKREQ_ON; + writel(val, usi->regs + USI_OPTION); + } +} + +static int exynos_usi_configure(struct udevice *dev) +{ + struct exynos_usi *usi = dev_get_priv(dev); + int ret; + + ret = exynos_usi_set_sw_conf(dev); + if (ret) + return ret; + + if (usi->data->ver == USI_VER2) + exynos_usi_enable(usi); + + return 0; +} + +static int exynos_usi_of_to_plat(struct udevice *dev) +{ + struct exynos_usi *usi = dev_get_priv(dev); + ofnode node = dev_ofnode(dev); + int ret; + u32 mode; + + usi->data = (struct exynos_usi_variant *)dev_get_driver_data(dev); + if (usi->data->ver == USI_VER2) { + usi->regs = dev_read_addr_ptr(dev); + if (!usi->regs) + return -ENODEV; + } + + ret = ofnode_read_u32(node, "samsung,mode", &mode); + if (ret) + return ret; + if (mode < usi->data->min_mode || mode > usi->data->max_mode) + return -EINVAL; + usi->mode = mode; + + usi->sysreg = syscon_regmap_lookup_by_phandle(dev, "samsung,sysreg"); + if (IS_ERR(usi->sysreg)) + return PTR_ERR(usi->sysreg); + + ret = ofnode_read_u32_index(node, "samsung,sysreg", 1, &usi->sw_conf); + if (ret) + return ret; + + usi->clkreq_on = ofnode_read_bool(node, "samsung,clkreq-on"); + + return 0; +} + +static int exynos_usi_probe(struct udevice *dev) +{ + return exynos_usi_configure(dev); +} + +U_BOOT_DRIVER(exynos_usi) = { + .name = "exynos-usi", + .id = UCLASS_MISC, + .of_match = exynos_usi_ids, + .of_to_plat = exynos_usi_of_to_plat, + .probe = exynos_usi_probe, + .priv_auto = sizeof(struct exynos_usi), +}; diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index d9a5944965b..786825d920c 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -35,13 +35,15 @@ static const char zynqmp_family[] = "ZynqMP"; #define IDCODE2_PL_INIT_SHIFT 9 #define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT) -#define ZYNQMP_VERSION_SIZE 7 +#define ZYNQMP_VERSION_SIZE 10 enum { ZYNQMP_VARIANT_EG = BIT(0), ZYNQMP_VARIANT_EV = BIT(1), ZYNQMP_VARIANT_CG = BIT(2), ZYNQMP_VARIANT_DR = BIT(3), + ZYNQMP_VARIANT_DR_SE = BIT(4), + ZYNQMP_VARIANT_EG_SE = BIT(5), }; struct zynqmp_device { @@ -106,6 +108,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_EG, }, { + .id = 0x04741093, + .device = 11, + .variants = ZYNQMP_VARIANT_EG_SE, + }, + { .id = 0x04750093, .device = 15, .variants = ZYNQMP_VARIANT_EG, @@ -121,6 +128,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_EG, }, { + .id = 0x0475C093, + .device = 19, + .variants = ZYNQMP_VARIANT_EG_SE, + }, + { .id = 0x047E1093, .device = 21, .variants = ZYNQMP_VARIANT_DR, @@ -171,6 +183,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_DR, }, { + .id = 0x047FA093, + .device = 47, + .variants = ZYNQMP_VARIANT_DR_SE, + }, + { .id = 0x047FB093, .device = 48, .variants = ZYNQMP_VARIANT_DR, @@ -186,6 +203,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_DR, }, { + .id = 0x046d7093, + .device = 67, + .variants = ZYNQMP_VARIANT_DR_SE, + }, + { .id = 0x04712093, .device = 24, .variants = 0, @@ -271,8 +293,12 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, "cg" : "eg", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_EG) { strlcat(priv->machine, "eg", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_EG_SE) { + strlcat(priv->machine, "eg_SE", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_DR) { strlcat(priv->machine, "dr", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_DR_SE) { + strlcat(priv->machine, "dr_SE", sizeof(priv->machine)); } return 0; diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 33360a18329..e291092c481 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -670,6 +670,7 @@ static const struct dm_spi_ops mxc_spi_ops = { static const struct udevice_id mxc_spi_ids[] = { { .compatible = "fsl,imx51-ecspi" }, + { .compatible = "fsl,imx6ul-ecspi" }, { } }; diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 51c37d72eb6..3eb14061c81 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -215,7 +215,8 @@ static u32 rpc_spi_get_strobe_delay(void) if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1) return RPC_PHYCNT_STRTIM(6); else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 || - cpu_type == RMOBILE_CPU_TYPE_R8A779G0) + cpu_type == RMOBILE_CPU_TYPE_R8A779G0 || + cpu_type == RMOBILE_CPU_TYPE_R8A779H0) return RPC_PHYCNT_STRTIM2(15); else #endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0dd5736433c..f96027d7bd2 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -210,10 +210,10 @@ config USB_EHCI_MX6 config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 || IMX8M + depends on ARCH_MX7 || IMX8M || IMX93 select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7 - select PHY if IMX8M - select NOP_PHY if IMX8M + select PHY if IMX8M || IMX93 + select NOP_PHY if IMX8M || IMX93 default y ---help--- Enables support for the on-chip EHCI controller on i.MX7 SoCs. diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index a9ed5e7a0d5..a35fcca43a2 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -538,7 +538,7 @@ static int ehci_usb_phy_mode(struct udevice *dev) plat->init_type = USB_INIT_DEVICE; else plat->init_type = USB_INIT_HOST; - } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { + } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) { phy_status = (void __iomem *)(addr + USBNC_PHY_STATUS_OFFSET); val = readl(phy_status); diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 14942526f19..63efa762db1 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -16,7 +16,7 @@ static int bcm2835_video_probe(struct udevice *dev) struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); int ret; - int w, h, pitch; + int w, h, pitch, bpp; ulong fb_base, fb_size, fb_start, fb_end; debug("bcm2835: Query resolution...\n"); @@ -41,9 +41,23 @@ static int bcm2835_video_probe(struct udevice *dev) DCACHE_WRITEBACK); video_set_flush_dcache(dev, true); + bpp = pitch / w; + switch (bpp) { + case 2: + uc_priv->bpix = VIDEO_BPP16; + break; + case 4: + uc_priv->bpix = VIDEO_BPP32; + break; + default: + printf("bcm2835: unexpected bpp %d, pitch %d, width %d\n", + bpp, pitch, w); + uc_priv->bpix = VIDEO_BPP32; + break; + } + uc_priv->xsize = w; uc_priv->ysize = h; - uc_priv->bpix = VIDEO_BPP32; plat->base = fb_base; plat->size = fb_size; diff --git a/include/asm-generic/pe.h b/include/asm-generic/pe.h index b9d674b6da4..cd5b6ad62bf 100644 --- a/include/asm-generic/pe.h +++ b/include/asm-generic/pe.h @@ -51,6 +51,9 @@ #define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12 #define IMAGE_SUBSYSTEM_EFI_ROM 13 +/* DLL characteristics */ +#define IMAGE_DLLCHARACTERISTICS_NX_COMPAT 0x100 + /* Section flags */ #define IMAGE_SCN_CNT_CODE 0x00000020 #define IMAGE_SCN_CNT_INITIALIZED_DATA 0x00000040 diff --git a/include/avb_verify.h b/include/avb_verify.h index 1e787ba6668..5d998b5a302 100644 --- a/include/avb_verify.h +++ b/include/avb_verify.h @@ -1,8 +1,6 @@ - +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2018, Linaro Limited - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _AVB_VERIFY_H @@ -54,7 +52,8 @@ char *avb_set_enforce_verity(const char *cmdline); char *avb_set_ignore_corruption(const char *cmdline); char *append_cmd_line(char *cmdline_orig, char *cmdline_new); - +const char *str_avb_io_error(AvbIOResult res); +const char *str_avb_slot_error(AvbSlotVerifyResult res); /** * ============================================================================ * I/O helper inline functions diff --git a/include/button.h b/include/button.h index 207f4a0f4db..8d38e521324 100644 --- a/include/button.h +++ b/include/button.h @@ -74,4 +74,13 @@ enum button_state_t button_get_state(struct udevice *dev); */ int button_get_code(struct udevice *dev); +#if IS_ENABLED(CONFIG_BUTTON_CMD) +/* Process button command mappings specified in the environment, + * running the commands for buttons which are pressed + */ +void process_button_cmds(void); +#else +static inline void process_button_cmds(void) {} +#endif /* CONFIG_BUTTON_CMD */ + #endif diff --git a/include/charset.h b/include/charset.h index 44034c71d3d..f1050c903d6 100644 --- a/include/charset.h +++ b/include/charset.h @@ -324,11 +324,21 @@ int utf_to_cp(s32 *c, const u16 *codepage); int utf8_to_cp437_stream(u8 c, char *buffer); /** - * utf8_to_utf32_stream() - convert UTF-8 stream to UTF-32 + * utf8_to_utf32_stream() - convert UTF-8 byte stream to Unicode code points + * + * The function is called for each byte @c in a UTF-8 stream. The byte is + * appended to the temporary storage @buffer until the UTF-8 stream in + * @buffer describes a Unicode code point. + * + * When a new code point has been decoded it is returned and buffer[0] is + * set to '\0', otherwise the return value is 0. + * + * The buffer must be at least 5 characters long. Before the first function + * invocation buffer[0] must be set to '\0'." * * @c: next UTF-8 character to convert * @buffer: buffer, at least 5 characters - * Return: next codepage 437 character or 0 + * Return: Unicode code point or 0 */ int utf8_to_utf32_stream(u8 c, char *buffer); diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h deleted file mode 100644 index 9b0f5cedcd7..00000000000 --- a/include/configs/bayleybay.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h deleted file mode 100644 index a3009571de9..00000000000 --- a/include/configs/cherryhill.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h deleted file mode 100644 index e00c408f29a..00000000000 --- a/include/configs/coreboot.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h deleted file mode 100644 index 0406786f7c6..00000000000 --- a/include/configs/cougarcanyon2.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h deleted file mode 100644 index 0c842dd01eb..00000000000 --- a/include/configs/crownbay.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/draco-etamin.h b/include/configs/draco-etamin.h index 97585a4fd12..6ae85b575b7 100644 --- a/include/configs/draco-etamin.h +++ b/include/configs/draco-etamin.h @@ -69,9 +69,6 @@ /* Physical Memory Map */ #define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - /* nedded by compliance test in read mode */ #undef COMMON_ENV_DFU_ARGS diff --git a/include/configs/draco-rastaban.h b/include/configs/draco-rastaban.h index 0991ebfd00c..1b95606cca9 100644 --- a/include/configs/draco-rastaban.h +++ b/include/configs/draco-rastaban.h @@ -34,9 +34,6 @@ /* Physical Memory Map */ #define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - /* Default env settings */ #define CFG_EXTRA_ENV_SETTINGS \ "hostname=rastaban\0" \ diff --git a/include/configs/draco-thuban.h b/include/configs/draco-thuban.h index f4c04c55ebf..629558e27ec 100644 --- a/include/configs/draco-thuban.h +++ b/include/configs/draco-thuban.h @@ -27,9 +27,6 @@ /* Physical Memory Map */ #define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - /* Default env settings */ #define CFG_EXTRA_ENV_SETTINGS \ "hostname=thuban\0" \ diff --git a/include/configs/e850-96.h b/include/configs/e850-96.h new file mode 100644 index 00000000000..4607b3089b2 --- /dev/null +++ b/include/configs/e850-96.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020, Linaro Limited + * Sam Protsenko <semen.protsenko@linaro.org> + * + * Configuration for E850-96 board. + */ + +#ifndef __E850_96_H +#define __E850_96_H + +#endif /* __E850_96_H */ diff --git a/include/configs/edison.h b/include/configs/edison.h deleted file mode 100644 index 127c2c4546e..00000000000 --- a/include/configs/edison.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Intel Corp. - */ diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h deleted file mode 100644 index d5824049d69..00000000000 --- a/include/configs/efi-x86_app.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Google, Inc - */ diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h deleted file mode 100644 index e00c408f29a..00000000000 --- a/include/configs/efi-x86_payload.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/galileo.h b/include/configs/galileo.h deleted file mode 100644 index 9b0f5cedcd7..00000000000 --- a/include/configs/galileo.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/grayhawk.h b/include/configs/grayhawk.h new file mode 100644 index 00000000000..f1bb84f0a13 --- /dev/null +++ b/include/configs/grayhawk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/grayhawk.h + * This file is Gray Hawk board configuration. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#ifndef __GRAYHAWK_H +#define __GRAYHAWK_H + +#include "rcar-gen4-common.h" + +#endif /* __GRAYHAWK_H */ diff --git a/include/configs/hc2910-2aghd05.h b/include/configs/hc2910-2aghd05.h deleted file mode 100644 index 3db9a474ec7..00000000000 --- a/include/configs/hc2910-2aghd05.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __HC2910_2AGHD05_CONFIG_H__ -#define __HC2910_2AGHD05_CONFIG_H__ - -#endif diff --git a/include/configs/imx6dl-sielaff.h b/include/configs/imx6dl-sielaff.h new file mode 100644 index 00000000000..df074135079 --- /dev/null +++ b/include/configs/imx6dl-sielaff.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ +#ifndef __MX6SSIELAFF_CONFIG_H +#define __MX6SSIELAFF_CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" + +#define CFG_MXC_UART_BASE UART2_BASE + +#define PHYS_SDRAM_SIZE SZ_512M +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR +#define CFG_SYS_FSL_USDHC_NUM 1 + +#define CFG_SYS_NAND_BASE 0x40000000 + +#endif /* __MX6SSIELAFF_CONFIG_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 2af2dde2aea..b370e25105a 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -25,4 +25,10 @@ "stderr=serial,vidconsole\0" #endif +/* + * Address of U-Boot for SPI NOR boot + */ + +#define CFG_SYS_UBOOT_BASE 0x60010000 + #endif /* __IMXRT1050_EVK_H */ diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h deleted file mode 100644 index 068a2af2c1f..00000000000 --- a/include/configs/minnowmax.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Google, Inc - */ diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index c1c1fd5a784..3c7d96cb3c0 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -55,8 +55,6 @@ #define PHYS_SDRAM_2 0xc0000000 #define PHYS_SDRAM_2_SIZE 0x0 -#define CFG_MXC_UART_BASE UART2_BASE_ADDR - #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/neural-compute-module-2.h b/include/configs/neural-compute-module-2.h index f0934ae00c7..43a560906a5 100644 --- a/include/configs/neural-compute-module-2.h +++ b/include/configs/neural-compute-module-2.h @@ -12,10 +12,4 @@ #include <configs/rv1126_common.h> -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) - #endif /* __NEURAL_COMPUTE_MODULE_2_H */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index d79d364c8e2..11a17be7fe1 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -19,6 +19,11 @@ "fdt_addr=0x48000000\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "ip_dyn=yes\0" \ + "dofastboot=0\0" \ + "fastboot_raw_partition_bootloader=64 8128\0" \ + "fastboot_raw_partition_all=0 4194304\0" \ + "emmc_dev=2\0" \ + "sd_dev=1\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "mmcroot=2\0" \ diff --git a/include/configs/phycore_imx93.h b/include/configs/phycore_imx93.h new file mode 100644 index 00000000000..07364dff403 --- /dev/null +++ b/include/configs/phycore_imx93.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner <c.stoidner@phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + */ + +#ifndef __PHYCORE_IMX93_H +#define __PHYCORE_IMX93_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif /* __PHYCORE_IMX93_H */ diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h deleted file mode 100644 index 9b0f5cedcd7..00000000000 --- a/include/configs/qemu-x86.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - */ diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h index a64c0c63642..ea290f763c0 100644 --- a/include/configs/rv1126_common.h +++ b/include/configs/rv1126_common.h @@ -26,9 +26,8 @@ "fdt_addr_r=0x08300000\0" \ "fdtoverlay_addr_r=0x02000000\0" \ "kernel_addr_r=0x02008000\0" \ - "ramdisk_addr_r=0x0a200000\0" + "ramdisk_addr_r=0x0a400000\0" -#include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fffffff\0" \ "initrd_high=0x0fffffff\0" \ @@ -36,6 +35,6 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV + "boot_targets=" BOOT_TARGETS "\0" #endif /* __CONFIG_RV1126_COMMON_H */ diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h deleted file mode 100644 index 85f6a968e04..00000000000 --- a/include/configs/slimbootloader.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Intel Corporation <www.intel.com> - */ diff --git a/include/configs/sonoff-ihost.h b/include/configs/sonoff-ihost.h new file mode 100644 index 00000000000..affc24ddcd9 --- /dev/null +++ b/include/configs/sonoff-ihost.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SONOFF_IHOST_H +#define __SONOFF_IHOST_H + +#define ROCKCHIP_DEVICE_SETTINGS + +#include <configs/rv1126_common.h> + +#endif /* __SONOFF_IHOST_H */ diff --git a/include/configs/xilinx_mbv.h b/include/configs/xilinx_mbv.h deleted file mode 100644 index dba398aeec4..00000000000 --- a/include/configs/xilinx_mbv.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2023, Advanced Micro Devices, Inc. - * - * Michal Simek <michal.simek@amd.com> - */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 2b441da91a1..9cb6b2bfea3 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -16,8 +16,8 @@ /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ /* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xF9000000 -#define GICR_BASE 0xF9060000 +#define GICD_BASE 0xe2000000 +#define GICR_BASE 0xe2060000 /* Serial setup */ #define CFG_SYS_BAUDRATE_TABLE \ diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h new file mode 100644 index 00000000000..3090e09c9a5 --- /dev/null +++ b/include/dt-bindings/clock/exynos850.h @@ -0,0 +1,337 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * Device Tree binding constants for Exynos850 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H +#define _DT_BINDINGS_CLOCK_EXYNOS_850_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_MMC_PLL 3 +#define CLK_MOUT_SHARED0_PLL 4 +#define CLK_MOUT_SHARED1_PLL 5 +#define CLK_MOUT_MMC_PLL 6 +#define CLK_MOUT_CORE_BUS 7 +#define CLK_MOUT_CORE_CCI 8 +#define CLK_MOUT_CORE_MMC_EMBD 9 +#define CLK_MOUT_CORE_SSS 10 +#define CLK_MOUT_DPU 11 +#define CLK_MOUT_HSI_BUS 12 +#define CLK_MOUT_HSI_MMC_CARD 13 +#define CLK_MOUT_HSI_USB20DRD 14 +#define CLK_MOUT_PERI_BUS 15 +#define CLK_MOUT_PERI_UART 16 +#define CLK_MOUT_PERI_IP 17 +#define CLK_DOUT_SHARED0_DIV3 18 +#define CLK_DOUT_SHARED0_DIV2 19 +#define CLK_DOUT_SHARED1_DIV3 20 +#define CLK_DOUT_SHARED1_DIV2 21 +#define CLK_DOUT_SHARED0_DIV4 22 +#define CLK_DOUT_SHARED1_DIV4 23 +#define CLK_DOUT_CORE_BUS 24 +#define CLK_DOUT_CORE_CCI 25 +#define CLK_DOUT_CORE_MMC_EMBD 26 +#define CLK_DOUT_CORE_SSS 27 +#define CLK_DOUT_DPU 28 +#define CLK_DOUT_HSI_BUS 29 +#define CLK_DOUT_HSI_MMC_CARD 30 +#define CLK_DOUT_HSI_USB20DRD 31 +#define CLK_DOUT_PERI_BUS 32 +#define CLK_DOUT_PERI_UART 33 +#define CLK_DOUT_PERI_IP 34 +#define CLK_GOUT_CORE_BUS 35 +#define CLK_GOUT_CORE_CCI 36 +#define CLK_GOUT_CORE_MMC_EMBD 37 +#define CLK_GOUT_CORE_SSS 38 +#define CLK_GOUT_DPU 39 +#define CLK_GOUT_HSI_BUS 40 +#define CLK_GOUT_HSI_MMC_CARD 41 +#define CLK_GOUT_HSI_USB20DRD 42 +#define CLK_GOUT_PERI_BUS 43 +#define CLK_GOUT_PERI_UART 44 +#define CLK_GOUT_PERI_IP 45 +#define CLK_MOUT_CLKCMU_APM_BUS 46 +#define CLK_DOUT_CLKCMU_APM_BUS 47 +#define CLK_GOUT_CLKCMU_APM_BUS 48 +#define CLK_MOUT_AUD 49 +#define CLK_GOUT_AUD 50 +#define CLK_DOUT_AUD 51 +#define CLK_MOUT_IS_BUS 52 +#define CLK_MOUT_IS_ITP 53 +#define CLK_MOUT_IS_VRA 54 +#define CLK_MOUT_IS_GDC 55 +#define CLK_GOUT_IS_BUS 56 +#define CLK_GOUT_IS_ITP 57 +#define CLK_GOUT_IS_VRA 58 +#define CLK_GOUT_IS_GDC 59 +#define CLK_DOUT_IS_BUS 60 +#define CLK_DOUT_IS_ITP 61 +#define CLK_DOUT_IS_VRA 62 +#define CLK_DOUT_IS_GDC 63 +#define CLK_MOUT_MFCMSCL_MFC 64 +#define CLK_MOUT_MFCMSCL_M2M 65 +#define CLK_MOUT_MFCMSCL_MCSC 66 +#define CLK_MOUT_MFCMSCL_JPEG 67 +#define CLK_GOUT_MFCMSCL_MFC 68 +#define CLK_GOUT_MFCMSCL_M2M 69 +#define CLK_GOUT_MFCMSCL_MCSC 70 +#define CLK_GOUT_MFCMSCL_JPEG 71 +#define CLK_DOUT_MFCMSCL_MFC 72 +#define CLK_DOUT_MFCMSCL_M2M 73 +#define CLK_DOUT_MFCMSCL_MCSC 74 +#define CLK_DOUT_MFCMSCL_JPEG 75 +#define CLK_MOUT_G3D_SWITCH 76 +#define CLK_GOUT_G3D_SWITCH 77 +#define CLK_DOUT_G3D_SWITCH 78 + +/* CMU_APM */ +#define CLK_RCO_I3C_PMIC 1 +#define OSCCLK_RCO_APM 2 +#define CLK_RCO_APM__ALV 3 +#define CLK_DLL_DCO 4 +#define CLK_MOUT_APM_BUS_USER 5 +#define CLK_MOUT_RCO_APM_I3C_USER 6 +#define CLK_MOUT_RCO_APM_USER 7 +#define CLK_MOUT_DLL_USER 8 +#define CLK_MOUT_CLKCMU_CHUB_BUS 9 +#define CLK_MOUT_APM_BUS 10 +#define CLK_MOUT_APM_I3C 11 +#define CLK_DOUT_CLKCMU_CHUB_BUS 12 +#define CLK_DOUT_APM_BUS 13 +#define CLK_DOUT_APM_I3C 14 +#define CLK_GOUT_CLKCMU_CMGP_BUS 15 +#define CLK_GOUT_CLKCMU_CHUB_BUS 16 +#define CLK_GOUT_RTC_PCLK 17 +#define CLK_GOUT_TOP_RTC_PCLK 18 +#define CLK_GOUT_I3C_PCLK 19 +#define CLK_GOUT_I3C_SCLK 20 +#define CLK_GOUT_SPEEDY_PCLK 21 +#define CLK_GOUT_GPIO_ALIVE_PCLK 22 +#define CLK_GOUT_PMU_ALIVE_PCLK 23 +#define CLK_GOUT_SYSREG_APM_PCLK 24 + +/* CMU_AUD */ +#define CLK_DOUT_AUD_AUDIF 1 +#define CLK_DOUT_AUD_BUSD 2 +#define CLK_DOUT_AUD_BUSP 3 +#define CLK_DOUT_AUD_CNT 4 +#define CLK_DOUT_AUD_CPU 5 +#define CLK_DOUT_AUD_CPU_ACLK 6 +#define CLK_DOUT_AUD_CPU_PCLKDBG 7 +#define CLK_DOUT_AUD_FM 8 +#define CLK_DOUT_AUD_FM_SPDY 9 +#define CLK_DOUT_AUD_MCLK 10 +#define CLK_DOUT_AUD_UAIF0 11 +#define CLK_DOUT_AUD_UAIF1 12 +#define CLK_DOUT_AUD_UAIF2 13 +#define CLK_DOUT_AUD_UAIF3 14 +#define CLK_DOUT_AUD_UAIF4 15 +#define CLK_DOUT_AUD_UAIF5 16 +#define CLK_DOUT_AUD_UAIF6 17 +#define CLK_FOUT_AUD_PLL 18 +#define CLK_GOUT_AUD_ABOX_ACLK 19 +#define CLK_GOUT_AUD_ASB_CCLK 20 +#define CLK_GOUT_AUD_CA32_CCLK 21 +#define CLK_GOUT_AUD_CNT_BCLK 22 +#define CLK_GOUT_AUD_CODEC_MCLK 23 +#define CLK_GOUT_AUD_DAP_CCLK 24 +#define CLK_GOUT_AUD_GPIO_PCLK 25 +#define CLK_GOUT_AUD_PPMU_ACLK 26 +#define CLK_GOUT_AUD_PPMU_PCLK 27 +#define CLK_GOUT_AUD_SPDY_BCLK 28 +#define CLK_GOUT_AUD_SYSMMU_CLK 29 +#define CLK_GOUT_AUD_SYSREG_PCLK 30 +#define CLK_GOUT_AUD_TZPC_PCLK 31 +#define CLK_GOUT_AUD_UAIF0_BCLK 32 +#define CLK_GOUT_AUD_UAIF1_BCLK 33 +#define CLK_GOUT_AUD_UAIF2_BCLK 34 +#define CLK_GOUT_AUD_UAIF3_BCLK 35 +#define CLK_GOUT_AUD_UAIF4_BCLK 36 +#define CLK_GOUT_AUD_UAIF5_BCLK 37 +#define CLK_GOUT_AUD_UAIF6_BCLK 38 +#define CLK_GOUT_AUD_WDT_PCLK 39 +#define CLK_MOUT_AUD_CPU 40 +#define CLK_MOUT_AUD_CPU_HCH 41 +#define CLK_MOUT_AUD_CPU_USER 42 +#define CLK_MOUT_AUD_FM 43 +#define CLK_MOUT_AUD_PLL 44 +#define CLK_MOUT_AUD_TICK_USB_USER 45 +#define CLK_MOUT_AUD_UAIF0 46 +#define CLK_MOUT_AUD_UAIF1 47 +#define CLK_MOUT_AUD_UAIF2 48 +#define CLK_MOUT_AUD_UAIF3 49 +#define CLK_MOUT_AUD_UAIF4 50 +#define CLK_MOUT_AUD_UAIF5 51 +#define CLK_MOUT_AUD_UAIF6 52 +#define IOCLK_AUDIOCDCLK0 53 +#define IOCLK_AUDIOCDCLK1 54 +#define IOCLK_AUDIOCDCLK2 55 +#define IOCLK_AUDIOCDCLK3 56 +#define IOCLK_AUDIOCDCLK4 57 +#define IOCLK_AUDIOCDCLK5 58 +#define IOCLK_AUDIOCDCLK6 59 +#define TICK_USB 60 +#define CLK_GOUT_AUD_CMU_AUD_PCLK 61 + +/* CMU_CMGP */ +#define CLK_RCO_CMGP 1 +#define CLK_MOUT_CMGP_ADC 2 +#define CLK_MOUT_CMGP_USI0 3 +#define CLK_MOUT_CMGP_USI1 4 +#define CLK_DOUT_CMGP_ADC 5 +#define CLK_DOUT_CMGP_USI0 6 +#define CLK_DOUT_CMGP_USI1 7 +#define CLK_GOUT_CMGP_ADC_S0_PCLK 8 +#define CLK_GOUT_CMGP_ADC_S1_PCLK 9 +#define CLK_GOUT_CMGP_GPIO_PCLK 10 +#define CLK_GOUT_CMGP_USI0_IPCLK 11 +#define CLK_GOUT_CMGP_USI0_PCLK 12 +#define CLK_GOUT_CMGP_USI1_IPCLK 13 +#define CLK_GOUT_CMGP_USI1_PCLK 14 +#define CLK_GOUT_SYSREG_CMGP_PCLK 15 + +/* CMU_G3D */ +#define CLK_FOUT_G3D_PLL 1 +#define CLK_MOUT_G3D_PLL 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_BUSD 4 +#define CLK_DOUT_G3D_BUSP 5 +#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 +#define CLK_GOUT_G3D_GPU_CLK 7 +#define CLK_GOUT_G3D_TZPC_PCLK 8 +#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 +#define CLK_GOUT_G3D_BUSD_CLK 10 +#define CLK_GOUT_G3D_BUSP_CLK 11 +#define CLK_GOUT_G3D_SYSREG_PCLK 12 + +/* CMU_HSI */ +#define CLK_MOUT_HSI_BUS_USER 1 +#define CLK_MOUT_HSI_MMC_CARD_USER 2 +#define CLK_MOUT_HSI_USB20DRD_USER 3 +#define CLK_MOUT_HSI_RTC 4 +#define CLK_GOUT_USB_RTC_CLK 5 +#define CLK_GOUT_USB_REF_CLK 6 +#define CLK_GOUT_USB_PHY_REF_CLK 7 +#define CLK_GOUT_USB_PHY_ACLK 8 +#define CLK_GOUT_USB_BUS_EARLY_CLK 9 +#define CLK_GOUT_GPIO_HSI_PCLK 10 +#define CLK_GOUT_MMC_CARD_ACLK 11 +#define CLK_GOUT_MMC_CARD_SDCLKIN 12 +#define CLK_GOUT_SYSREG_HSI_PCLK 13 +#define CLK_GOUT_HSI_PPMU_ACLK 14 +#define CLK_GOUT_HSI_PPMU_PCLK 15 +#define CLK_GOUT_HSI_CMU_HSI_PCLK 16 + +/* CMU_IS */ +#define CLK_MOUT_IS_BUS_USER 1 +#define CLK_MOUT_IS_ITP_USER 2 +#define CLK_MOUT_IS_VRA_USER 3 +#define CLK_MOUT_IS_GDC_USER 4 +#define CLK_DOUT_IS_BUSP 5 +#define CLK_GOUT_IS_CMU_IS_PCLK 6 +#define CLK_GOUT_IS_CSIS0_ACLK 7 +#define CLK_GOUT_IS_CSIS1_ACLK 8 +#define CLK_GOUT_IS_CSIS2_ACLK 9 +#define CLK_GOUT_IS_TZPC_PCLK 10 +#define CLK_GOUT_IS_CSIS_DMA_CLK 11 +#define CLK_GOUT_IS_GDC_CLK 12 +#define CLK_GOUT_IS_IPP_CLK 13 +#define CLK_GOUT_IS_ITP_CLK 14 +#define CLK_GOUT_IS_MCSC_CLK 15 +#define CLK_GOUT_IS_VRA_CLK 16 +#define CLK_GOUT_IS_PPMU_IS0_ACLK 17 +#define CLK_GOUT_IS_PPMU_IS0_PCLK 18 +#define CLK_GOUT_IS_PPMU_IS1_ACLK 19 +#define CLK_GOUT_IS_PPMU_IS1_PCLK 20 +#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 +#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 +#define CLK_GOUT_IS_SYSREG_PCLK 23 + +/* CMU_MFCMSCL */ +#define CLK_MOUT_MFCMSCL_MFC_USER 1 +#define CLK_MOUT_MFCMSCL_M2M_USER 2 +#define CLK_MOUT_MFCMSCL_MCSC_USER 3 +#define CLK_MOUT_MFCMSCL_JPEG_USER 4 +#define CLK_DOUT_MFCMSCL_BUSP 5 +#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6 +#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7 +#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8 +#define CLK_GOUT_MFCMSCL_M2M_ACLK 9 +#define CLK_GOUT_MFCMSCL_MCSC_CLK 10 +#define CLK_GOUT_MFCMSCL_MFC_ACLK 11 +#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12 +#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 +#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 +#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 + +/* CMU_PERI */ +#define CLK_MOUT_PERI_BUS_USER 1 +#define CLK_MOUT_PERI_UART_USER 2 +#define CLK_MOUT_PERI_HSI2C_USER 3 +#define CLK_MOUT_PERI_SPI_USER 4 +#define CLK_DOUT_PERI_HSI2C0 5 +#define CLK_DOUT_PERI_HSI2C1 6 +#define CLK_DOUT_PERI_HSI2C2 7 +#define CLK_DOUT_PERI_SPI0 8 +#define CLK_GOUT_PERI_HSI2C0 9 +#define CLK_GOUT_PERI_HSI2C1 10 +#define CLK_GOUT_PERI_HSI2C2 11 +#define CLK_GOUT_GPIO_PERI_PCLK 12 +#define CLK_GOUT_HSI2C0_IPCLK 13 +#define CLK_GOUT_HSI2C0_PCLK 14 +#define CLK_GOUT_HSI2C1_IPCLK 15 +#define CLK_GOUT_HSI2C1_PCLK 16 +#define CLK_GOUT_HSI2C2_IPCLK 17 +#define CLK_GOUT_HSI2C2_PCLK 18 +#define CLK_GOUT_I2C0_PCLK 19 +#define CLK_GOUT_I2C1_PCLK 20 +#define CLK_GOUT_I2C2_PCLK 21 +#define CLK_GOUT_I2C3_PCLK 22 +#define CLK_GOUT_I2C4_PCLK 23 +#define CLK_GOUT_I2C5_PCLK 24 +#define CLK_GOUT_I2C6_PCLK 25 +#define CLK_GOUT_MCT_PCLK 26 +#define CLK_GOUT_PWM_MOTOR_PCLK 27 +#define CLK_GOUT_SPI0_IPCLK 28 +#define CLK_GOUT_SPI0_PCLK 29 +#define CLK_GOUT_SYSREG_PERI_PCLK 30 +#define CLK_GOUT_UART_IPCLK 31 +#define CLK_GOUT_UART_PCLK 32 +#define CLK_GOUT_WDT0_PCLK 33 +#define CLK_GOUT_WDT1_PCLK 34 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_MOUT_CORE_CCI_USER 2 +#define CLK_MOUT_CORE_MMC_EMBD_USER 3 +#define CLK_MOUT_CORE_SSS_USER 4 +#define CLK_MOUT_CORE_GIC 5 +#define CLK_DOUT_CORE_BUSP 6 +#define CLK_GOUT_CCI_ACLK 7 +#define CLK_GOUT_GIC_CLK 8 +#define CLK_GOUT_MMC_EMBD_ACLK 9 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 10 +#define CLK_GOUT_SSS_ACLK 11 +#define CLK_GOUT_SSS_PCLK 12 +#define CLK_GOUT_GPIO_CORE_PCLK 13 +#define CLK_GOUT_SYSREG_CORE_PCLK 14 + +/* CMU_DPU */ +#define CLK_MOUT_DPU_USER 1 +#define CLK_DOUT_DPU_BUSP 2 +#define CLK_GOUT_DPU_CMU_DPU_PCLK 3 +#define CLK_GOUT_DPU_DECON0_ACLK 4 +#define CLK_GOUT_DPU_DMA_ACLK 5 +#define CLK_GOUT_DPU_DPP_ACLK 6 +#define CLK_GOUT_DPU_PPMU_ACLK 7 +#define CLK_GOUT_DPU_PPMU_PCLK 8 +#define CLK_GOUT_DPU_SMMU_CLK 9 +#define CLK_GOUT_DPU_SYSREG_PCLK 10 +#define DPU_NR_CLK 11 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h new file mode 100644 index 00000000000..7ab6cfbaf90 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779h0 CPG Core Clocks */ + +#define R8A779H0_CLK_ZX 0 +#define R8A779H0_CLK_ZD 1 +#define R8A779H0_CLK_ZS 2 +#define R8A779H0_CLK_ZT 3 +#define R8A779H0_CLK_ZTR 4 +#define R8A779H0_CLK_S0D2 5 +#define R8A779H0_CLK_S0D3 6 +#define R8A779H0_CLK_S0D4 7 +#define R8A779H0_CLK_S0D1_VIO 8 +#define R8A779H0_CLK_S0D2_VIO 9 +#define R8A779H0_CLK_S0D4_VIO 10 +#define R8A779H0_CLK_S0D8_VIO 11 +#define R8A779H0_CLK_VIOBUSD1 12 +#define R8A779H0_CLK_VIOBUSD2 13 +#define R8A779H0_CLK_S0D1_VC 14 +#define R8A779H0_CLK_S0D2_VC 15 +#define R8A779H0_CLK_S0D4_VC 16 +#define R8A779H0_CLK_VCBUSD1 17 +#define R8A779H0_CLK_VCBUSD2 18 +#define R8A779H0_CLK_S0D2_MM 19 +#define R8A779H0_CLK_S0D4_MM 20 +#define R8A779H0_CLK_S0D2_U3DG 21 +#define R8A779H0_CLK_S0D4_U3DG 22 +#define R8A779H0_CLK_S0D2_RT 23 +#define R8A779H0_CLK_S0D3_RT 24 +#define R8A779H0_CLK_S0D4_RT 25 +#define R8A779H0_CLK_S0D6_RT 26 +#define R8A779H0_CLK_S0D2_PER 27 +#define R8A779H0_CLK_S0D3_PER 28 +#define R8A779H0_CLK_S0D4_PER 29 +#define R8A779H0_CLK_S0D6_PER 30 +#define R8A779H0_CLK_S0D12_PER 31 +#define R8A779H0_CLK_S0D24_PER 32 +#define R8A779H0_CLK_S0D1_HSC 33 +#define R8A779H0_CLK_S0D2_HSC 34 +#define R8A779H0_CLK_S0D4_HSC 35 +#define R8A779H0_CLK_S0D8_HSC 36 +#define R8A779H0_CLK_SVD1_IR 37 +#define R8A779H0_CLK_SVD2_IR 38 +#define R8A779H0_CLK_IMPAD1 39 +#define R8A779H0_CLK_IMPAD4 40 +#define R8A779H0_CLK_IMPB 41 +#define R8A779H0_CLK_SVD1_VIP 42 +#define R8A779H0_CLK_SVD2_VIP 43 +#define R8A779H0_CLK_CL 44 +#define R8A779H0_CLK_CL16M 45 +#define R8A779H0_CLK_CL16M_MM 46 +#define R8A779H0_CLK_CL16M_RT 47 +#define R8A779H0_CLK_CL16M_PER 48 +#define R8A779H0_CLK_CL16M_HSC 49 +#define R8A779H0_CLK_ZC0 50 +#define R8A779H0_CLK_ZC1 51 +#define R8A779H0_CLK_ZC2 52 +#define R8A779H0_CLK_ZC3 53 +#define R8A779H0_CLK_ZB3 54 +#define R8A779H0_CLK_ZB3D2 55 +#define R8A779H0_CLK_ZB3D4 56 +#define R8A779H0_CLK_ZG 57 +#define R8A779H0_CLK_SD0H 58 +#define R8A779H0_CLK_SD0 59 +#define R8A779H0_CLK_RPC 60 +#define R8A779H0_CLK_RPCD2 61 +#define R8A779H0_CLK_MSO 62 +#define R8A779H0_CLK_CANFD 63 +#define R8A779H0_CLK_CSI 64 +#define R8A779H0_CLK_FRAY 65 +#define R8A779H0_CLK_IPC 66 +#define R8A779H0_CLK_SASYNCRT 67 +#define R8A779H0_CLK_SASYNCPERD1 68 +#define R8A779H0_CLK_SASYNCPERD2 69 +#define R8A779H0_CLK_SASYNCPERD4 70 +#define R8A779H0_CLK_DSIEXT 71 +#define R8A779H0_CLK_DSIREF 72 +#define R8A779H0_CLK_ADGH 73 +#define R8A779H0_CLK_OSC 74 +#define R8A779H0_CLK_ZR0 75 +#define R8A779H0_CLK_ZR1 76 +#define R8A779H0_CLK_ZR2 77 +#define R8A779H0_CLK_RGMII 78 +#define R8A779H0_CLK_CPEX 79 +#define R8A779H0_CLK_CP 80 +#define R8A779H0_CLK_CBFUSA 81 +#define R8A779H0_CLK_R 82 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h index c1942422a43..d2989086515 100644 --- a/include/dt-bindings/clock/rk3568-cru.h +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -478,6 +478,7 @@ #define CPLL_50M 415 #define CPLL_25M 416 #define CPLL_100M 417 +#define SCLK_DDRCLK 418 #define PCLK_CORE_PVTM 450 diff --git a/include/dt-bindings/power/renesas,r8a779h0-sysc.h b/include/dt-bindings/power/renesas,r8a779h0-sysc.h new file mode 100644 index 00000000000..f27976f523e --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a779h0-sysc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779H0_PD_A1E0D0C0 0 +#define R8A779H0_PD_A1E0D0C1 1 +#define R8A779H0_PD_A1E0D0C2 2 +#define R8A779H0_PD_A1E0D0C3 3 +#define R8A779H0_PD_A2E0D0 16 +#define R8A779H0_PD_A3CR0 21 +#define R8A779H0_PD_A3CR1 22 +#define R8A779H0_PD_A3CR2 23 +#define R8A779H0_PD_A33DGA 24 +#define R8A779H0_PD_A23DGB 25 +#define R8A779H0_PD_C4 31 +#define R8A779H0_PD_A1DSP0 33 +#define R8A779H0_PD_A2IMP01 34 +#define R8A779H0_PD_A2PSC 35 +#define R8A779H0_PD_A2CV0 36 +#define R8A779H0_PD_A2CV1 37 +#define R8A779H0_PD_A3IMR0 38 +#define R8A779H0_PD_A3IMR1 39 +#define R8A779H0_PD_A3VC 40 +#define R8A779H0_PD_A2CN0 42 +#define R8A779H0_PD_A1CN0 44 +#define R8A779H0_PD_A1DSP1 45 +#define R8A779H0_PD_A2DMA 47 +#define R8A779H0_PD_A2CV2 48 +#define R8A779H0_PD_A2CV3 49 +#define R8A779H0_PD_A3IMR2 50 +#define R8A779H0_PD_A3IMR3 51 +#define R8A779H0_PD_A3PCI 52 +#define R8A779H0_PD_A2PCIPHY 53 +#define R8A779H0_PD_A3VIP0 56 +#define R8A779H0_PD_A3VIP2 58 +#define R8A779H0_PD_A3ISP0 60 +#define R8A779H0_PD_A3DUL 62 + +/* Always-on power area */ +#define R8A779H0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */ diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h index 6e66a802b96..668f199df9f 100644 --- a/include/dt-bindings/soc/rockchip,vop2.h +++ b/include/dt-bindings/soc/rockchip,vop2.h @@ -10,5 +10,9 @@ #define ROCKCHIP_VOP2_EP_LVDS0 5 #define ROCKCHIP_VOP2_EP_MIPI1 6 #define ROCKCHIP_VOP2_EP_LVDS1 7 +#define ROCKCHIP_VOP2_EP_HDMI1 8 +#define ROCKCHIP_VOP2_EP_EDP1 9 +#define ROCKCHIP_VOP2_EP_DP0 10 +#define ROCKCHIP_VOP2_EP_DP1 11 #endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h new file mode 100644 index 00000000000..a01af169d24 --- /dev/null +++ b/include/dt-bindings/soc/samsung,exynos-usi.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface). + */ + +#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H +#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H + +#define USI_V2_NONE 0 +#define USI_V2_UART 1 +#define USI_V2_SPI 2 +#define USI_V2_I2C 3 + +#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */ diff --git a/include/env/ti/default_findfdt.env b/include/env/ti/default_findfdt.env deleted file mode 100644 index a2b51dd923b..00000000000 --- a/include/env/ti/default_findfdt.env +++ /dev/null @@ -1,12 +0,0 @@ -default_device_tree=CONFIG_DEFAULT_DEVICE_TREE -default_device_tree_arch=ti -#ifdef CONFIG_ARM64 -findfdt= - setenv name_fdt ${default_device_tree_arch}/${default_device_tree}.dtb; - setenv fdtfile ${name_fdt} -#else -default_device_tree_subarch=omap -findfdt= - setenv name_fdt ${default_device_tree_arch}/${default_device_tree_subarch}/${default_device_tree}.dtb; - setenv fdtfile ${name_fdt} -#endif diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index f832982b3de..7d8499f070a 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -75,6 +75,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, sc_faddr_t address); void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); +int sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); @@ -385,6 +386,11 @@ static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) { } +static inline int sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason) +{ + return -EOPNOTSUPP; +} + static inline int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) { return -EOPNOTSUPP; diff --git a/include/imximage.h b/include/imximage.h index c1ecc0b7cb0..a951699d0a6 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -210,33 +210,37 @@ typedef struct { uint8_t datasetup; uint8_t coladdrwidth; uint8_t devcfgenable; - uint8_t reserved_2[3]; + uint8_t deviceModeType; + uint16_t waitTimeCfgCommands; uint8_t devmodeseq[4]; - uint8_t devmodearg[4]; + uint32_t devmodearg; uint8_t cmd_enable; - uint8_t reserved_3[3]; + uint8_t configModeType[3]; uint8_t cmd_seq[16] ; uint8_t cmd_arg[16]; - uint8_t controllermisc[4]; + uint32_t controllermisc; uint8_t dev_type; uint8_t sflash_pad; uint8_t serial_clk; - uint8_t lut_custom ; - uint8_t reserved_4[8]; - uint8_t sflashA1[4]; - uint8_t sflashA2[4]; - uint8_t sflashB1[4]; - uint8_t sflashB2[4]; - uint8_t cspadover[4]; - uint8_t sclkpadover[4]; - uint8_t datapadover[4]; - uint8_t dqspadover[4]; - uint8_t timeout[4]; - uint8_t commandInt[4]; - uint8_t datavalid[4]; - uint8_t busyoffset[2]; - uint8_t busybitpolarity[2]; + uint8_t lut_custom; + uint8_t reserved_2[8]; + uint32_t sflashA1; + uint32_t sflashA2; + uint32_t sflashB1; + uint32_t sflashB2; + uint32_t cspadover; + uint32_t sclkpadover; + uint32_t datapadover; + uint32_t dqspadover; + uint32_t timeout; + uint32_t commandInt; + uint16_t datavalid[2]; + uint16_t busyoffset; + uint16_t busybitpolarity; uint8_t lut[256]; + uint8_t lutCustomSeq[48]; + uint8_t reserved_3[16]; + } __attribute__((packed)) fspi_conf; typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, diff --git a/include/phy.h b/include/phy.h index 27effdb5763..e02cbdb58c9 100644 --- a/include/phy.h +++ b/include/phy.h @@ -51,10 +51,6 @@ struct udevice; PHY_100BT_FEATURES | \ PHY_DEFAULT_FEATURES) -#define PHY_100BT1_FEATURES (SUPPORTED_TP | \ - SUPPORTED_MII | \ - SUPPORTED_100baseT_Full) - #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ PHY_1000BT_FEATURES) diff --git a/lib/efi_driver/Makefile b/lib/efi_driver/Makefile index f2b6c05cc24..0da20fe91d3 100644 --- a/lib/efi_driver/Makefile +++ b/lib/efi_driver/Makefile @@ -9,3 +9,4 @@ obj-y += efi_uclass.o ifeq ($(CONFIG_PARTITIONS),y) obj-y += efi_block_device.o endif +obj-$(CONFIG_SYSRESET_SBI) += efi_reset_riscv.o diff --git a/lib/efi_driver/efi_reset_riscv.c b/lib/efi_driver/efi_reset_riscv.c new file mode 100644 index 00000000000..89b23522e95 --- /dev/null +++ b/lib/efi_driver/efi_reset_riscv.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include <efi_loader.h> +#include <asm/sbi.h> + +void __efi_runtime EFIAPI efi_reset_system(enum efi_reset_type reset_type, + efi_status_t reset_status, + unsigned long data_size, + void *reset_data) +{ + register unsigned long eid asm("a7") = SBI_EXT_SRST; + register unsigned long fid asm("a6") = SBI_EXT_SRST_RESET; + register unsigned long type asm("a0"); + register unsigned long reason asm("a1") = SBI_SRST_RESET_REASON_NONE; + + switch (reset_type) { + case EFI_RESET_WARM: + type = SBI_SRST_RESET_TYPE_WARM_REBOOT; + break; + case EFI_RESET_SHUTDOWN: + type = SBI_SRST_RESET_TYPE_SHUTDOWN; + break; + default: + type = SBI_SRST_RESET_TYPE_COLD_REBOOT; + break; + } + asm volatile ("ecall\n" + : : "r" (eid), "r" (fid), "r" (type), "r" (reason)); +} diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index db5571de1d9..a7c3e05c13a 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -366,7 +366,7 @@ config EFI_HAVE_RUNTIME_RESET bool default y depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || \ - SANDBOX || SYSRESET_X86 + SANDBOX || SYSRESET_SBI || SYSRESET_X86 config EFI_GRUB_ARM32_WORKAROUND bool "Workaround for GRUB on 32bit ARM" diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index b1739d99201..93a9a5ac025 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -574,7 +574,8 @@ static int efi_disk_create_raw(struct udevice *dev, efi_handle_t agent_handle) log_notice("Disk %s not ready\n", dev->name); ret = -EBUSY; } else { - log_err("Adding disk for %s failed (err=%ld/%#lx)\n", dev->name, ret, ret); + log_err("Adding block device %s failed, r = %lu\n", + dev->name, ret & ~EFI_ERROR_MASK); ret = -ENOENT; } diff --git a/lib/image-sparse.c b/lib/image-sparse.c index f8289064692..09225692e9b 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -211,7 +211,7 @@ int write_sparse_image(struct sparse_storage *info, blks = write_sparse_chunk_raw(info, blk, blkcnt, data, response); - if (blks < 0) + if (IS_ERR_VALUE(blks)) return -1; blk += blks; diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index 0ade91642ae..8208ffe2274 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -113,7 +113,7 @@ vpl/include/autoconf.mk: vpl/u-boot.cfg define filechk_config_h (echo "/* Automatically generated - do not edit */"; \ echo \#define CFG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\ - echo \#include \<configs/$(CONFIG_SYS_CONFIG_NAME).h\>; \ + $(if $(CONFIG_SYS_CONFIG_NAME),echo \#include \<configs/$(CONFIG_SYS_CONFIG_NAME).h\> ;) \ echo \#include \<asm/config.h\>; \ echo \#include \<linux/kconfig.h\>; \ echo \#include \<config_fallbacks.h\>;) diff --git a/scripts/gen_compile_commands.py b/scripts/gen_compile_commands.py index cdca85e6b07..fec513e5547 100755 --- a/scripts/gen_compile_commands.py +++ b/scripts/gen_compile_commands.py @@ -21,7 +21,7 @@ _DEFAULT_OUTPUT = 'compile_commands.json' _DEFAULT_LOG_LEVEL = 'WARNING' _FILENAME_PATTERN = r'^\..*\.cmd$' -_LINE_PATTERN = r'^cmd_[^ ]*\.o := (.* )([^ ]*\.c) *(;|$)' +_LINE_PATTERN = r'^(saved)?cmd_[^ ]*\.o := (?P<command_prefix>.* )(?P<file_path>[^ ]*\.[cS]) *(;|$)' _VALID_LOG_LEVELS = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL'] # The tools/ directory adopts a different build system, and produces .cmd # files in a different format. Do not support it. @@ -66,7 +66,7 @@ def parse_arguments(): args = parser.parse_args() return (args.log_level, - os.path.abspath(args.directory), + os.path.realpath(args.directory), args.output, args.ar, args.paths if len(args.paths) > 0 else [args.directory]) @@ -174,8 +174,8 @@ def process_line(root_directory, command_prefix, file_path): # by Make, so this code replaces the escaped version with '#'. prefix = command_prefix.replace('\#', '#').replace('$(pound)', '#') - # Use os.path.abspath() to normalize the path resolving '.' and '..' . - abs_path = os.path.abspath(os.path.join(root_directory, file_path)) + # Return the canonical path, eliminating any symbolic links encountered in the path. + abs_path = os.path.realpath(os.path.join(root_directory, file_path)) if not os.path.exists(abs_path): raise ValueError('File %s not found' % abs_path) return { @@ -215,15 +215,15 @@ def main(): result = line_matcher.match(f.readline()) if result: try: - entry = process_line(directory, result.group(1), - result.group(2)) + entry = process_line(directory, result.group('command_prefix'), + result.group('file_path')) compile_commands.append(entry) except ValueError as err: logging.info('Could not add line from %s: %s', cmdfile, err) with open(output, 'wt') as f: - json.dump(compile_commands, f, indent=2, sort_keys=True) + json.dump(sorted(compile_commands, key=lambda x: x["file"]), f, indent=2, sort_keys=True) if __name__ == '__main__': diff --git a/test/py/tests/test_android/test_avb.py b/test/py/tests/test_android/test_avb.py index 238b48c90fa..865efbca4de 100644 --- a/test/py/tests/test_android/test_avb.py +++ b/test/py/tests/test_android/test_avb.py @@ -1,6 +1,5 @@ -# Copyright (c) 2018, Linaro Limited -# # SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2018, Linaro Limited # # Android Verified Boot 2.0 Test diff --git a/tools/Kconfig b/tools/Kconfig index f01ed783e6f..667807b3317 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -148,6 +148,27 @@ config SERIAL_CLK_FREQUENCY Chip specific frequency: other value 30MHz 1-30MHz 2-50MHz 3-60MHz 4-75MHz 5-80MHz 6-100MHz 7-133MHz 8-166MHz +config FSPI_COL_ADDR_W + hex "Column Address With" + default 0x00 + depends on FSPI_CONF_HEADER + help + Default 0. For HyperBus protocol, it is fixed to 3 + +config FSPI_CONTROLLER_MISC + hex "FSPI miscellaneous control" + default 0x00000000 + depends on FSPI_CONF_HEADER + help + Default 0. [0x40] Controller Misc Options + +config FSPI_FLASH_A1_SIZE + hex "Size in bytes of Flash A1" + default 0x10000000 + depends on FSPI_CONF_HEADER + help + Size of Flash connected to A1 in bytes + config LUT_CUSTOM_SEQUENCE hex "Enable Custom Look Up Table(LUT) Sequence" default 0x00 diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index 21075c23799..939f829a9f7 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -426,36 +426,39 @@ static int generate_fspi_header (int ifd) .read_sample = CONFIG_READ_CLK_SOURCE, .datahold = 0x03, .datasetup = 0x03, - .coladdrwidth = 0x00, + .coladdrwidth = CONFIG_FSPI_COL_ADDR_W, .devcfgenable = 0x00, - .reserved_2 = {0x00, 0x00, 0x00}, + .deviceModeType = 0x00, + .waitTimeCfgCommands = 0x0000, .devmodeseq = {0x00, 0x00, 0x00, 0x00}, - .devmodearg = {0x00, 0x00, 0x00, 0x00}, + .devmodearg = 0x00000000, .cmd_enable = 0x00, - .reserved_3 = {0x00}, + .configModeType = {0x00}, .cmd_seq = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, .cmd_arg = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .controllermisc = {0x00, 0x00, 0x00, 0x00}, + .controllermisc = cpu_to_le32(CONFIG_FSPI_CONTROLLER_MISC), .dev_type = CONFIG_DEVICE_TYPE, .sflash_pad = CONFIG_FLASH_PAD_TYPE, .serial_clk = CONFIG_SERIAL_CLK_FREQUENCY, .lut_custom = CONFIG_LUT_CUSTOM_SEQUENCE, - .reserved_4 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .sflashA1 = {0x00, 0x00, 0x00, 0x10}, - .sflashA2 = {0x00, 0x00, 0x00, 0x00}, - .sflashB1 = {0x00, 0x00, 0x00, 0x00}, - .sflashB2 = {0x00, 0x00, 0x00, 0x00}, - .cspadover = {0x00, 0x00, 0x00, 0x00}, - .sclkpadover = {0x00, 0x00, 0x00, 0x00}, - .datapadover = {0x00, 0x00, 0x00, 0x00}, - .dqspadover = {0x00, 0x00, 0x00, 0x00}, - .timeout = {0x00, 0x00, 0x00, 0x00}, - .commandInt = {0x00, 0x00, 0x00, 0x00}, - .datavalid = {0x00, 0x00, 0x00, 0x00}, - .busyoffset = {0x00, 0x00}, - .busybitpolarity = {0x00, 0x00}, + .reserved_2 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .sflashA1 = cpu_to_le32(CONFIG_FSPI_FLASH_A1_SIZE), + .sflashA2 = 0x00000000, + .sflashB1 = 0x00000000, + .sflashB2 = 0x00000000, + .cspadover = 0x00000000, + .sclkpadover = 0x00000000, + .datapadover = 0x00000000, + .dqspadover = 0x00000000, + .timeout = 0x00000000, + .commandInt = 0x00000000, + .datavalid = {0x0000, 0x0000}, + .busyoffset = 0x0000, + .busybitpolarity = 0x0000, + .lutCustomSeq = {0x00}, + .reserved_3 = {0x00} }; for (val = strtok(lut_str, ","); val; val = strtok(NULL, ",")) { diff --git a/tools/imximage.c b/tools/imximage.c index b3da1f244cd..2df4c7dd491 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -908,6 +908,64 @@ int imximage_check_params(struct image_tool_params *params) (params->xflag) || !(strlen(params->imagename)); } +#ifdef CONFIG_FSPI_CONF_HEADER +static void generate_fspi_header(int ifd) +{ + int i = 0; + char *val; + char lut_str[] = CONFIG_LUT_SEQUENCE; + + fspi_conf fspi_conf_data = { + .tag = {0x46, 0x43, 0x46, 0x42}, + .version = {0x00, 0x00, 0x01, 0x56}, + .reserved_1 = {0x00, 0x00, 0x00, 0x00}, + .read_sample = CONFIG_READ_CLK_SOURCE, + .datahold = 0x03, + .datasetup = 0x03, + .coladdrwidth = CONFIG_FSPI_COL_ADDR_W, + .devcfgenable = 0x00, + .deviceModeType = 0x00, + .waitTimeCfgCommands = 0x0000, + .devmodeseq = {0x00, 0x00, 0x00, 0x00}, + .devmodearg = 0x00000000, + .cmd_enable = 0x00, + .configModeType = {0x00}, + .cmd_seq = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .cmd_arg = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .controllermisc = cpu_to_le32(CONFIG_FSPI_CONTROLLER_MISC), + .dev_type = CONFIG_DEVICE_TYPE, + .sflash_pad = CONFIG_FLASH_PAD_TYPE, + .serial_clk = CONFIG_SERIAL_CLK_FREQUENCY, + .lut_custom = CONFIG_LUT_CUSTOM_SEQUENCE, + .reserved_2 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .sflashA1 = cpu_to_le32(CONFIG_FSPI_FLASH_A1_SIZE), + .sflashA2 = 0x00000000, + .sflashB1 = 0x00000000, + .sflashB2 = 0x00000000, + .cspadover = 0x00000000, + .sclkpadover = 0x00000000, + .datapadover = 0x00000000, + .dqspadover = 0x00000000, + .timeout = 0x00000000, + .commandInt = 0x00000000, + .datavalid = {0x0000, 0x0000}, + .busyoffset = 0x0000, + .busybitpolarity = 0x0000, + .lutCustomSeq = {0x00}, + .reserved_3 = {0x00} + }; + + for (val = strtok(lut_str, ","); val; val = strtok(NULL, ",")) + fspi_conf_data.lut[i++] = strtoul(val, NULL, 16); + + lseek(ifd, 0, SEEK_CUR); + if (write(ifd, &fspi_conf_data, sizeof(fspi_conf_data)) == -1) + exit(EXIT_FAILURE); +} +#endif + static int imximage_generate(struct image_tool_params *params, struct image_type_params *tparams) { @@ -917,6 +975,11 @@ static int imximage_generate(struct image_tool_params *params, char *datafile = params->datafile; uint32_t pad_len, header_size; +#ifdef CONFIG_FSPI_CONF_HEADER + int fspi_fd; + char *fspi; +#endif + memset(&imximage_header, 0, sizeof(imximage_header)); /* @@ -977,6 +1040,20 @@ static int imximage_generate(struct image_tool_params *params, pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size; +#ifdef CONFIG_FSPI_CONF_HEADER + fspi = CONFIG_FSPI_CONF_FILE; + fspi_fd = open(fspi, O_RDWR | O_CREAT, S_IRWXU); + if (fspi_fd < 0) { + fprintf(stderr, "Can't open %s: %s\n", + fspi, strerror(errno)); + exit(EXIT_FAILURE); + } + + generate_fspi_header(fspi_fd); + close(fspi_fd); + +#endif + return pad_len; } |
