diff options
277 files changed, 5581 insertions, 8574 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 27f69583c65..c43bb51066a 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -8,6 +8,17 @@ variables: # since our $(ci_runner_image) user is not root. container_option: -u 0 work_dir: /u + # We define all of these as variables so we can easily reference them twice + am33xx_kirkwood_ls1_mvebu_omap: "am33xx kirkwood ls1 mvebu omap -x siemens,freescale" + amlogic_bcm_boundary_engicam_siemens_technexion_oradex: "amlogic bcm boundary engicam siemens technexion toradex -x mips" + arm_nxp_minus_imx_and_at91: "at91 freescale -x powerpc,m68k,imx,mx" + imx: "mx imx -x boundary,engicam,technexion,toradex" + rk: "rk" + sunxi: "sunxi" + powerpc: "powerpc" + arm_catch_all: "arm -x aarch64,am33xx,at91,bcm,ls1,kirkwood,mvebu,omap,rk,siemens,mx,sunxi,technexion,toradex" + aarch64_catch_all: "aarch64 -x amlogic,bcm,engicam,imx,ls1,ls2,lx216,mvebu,rk,siemens,sunxi,toradex" + everything_but_arm_and_powerpc: "arc m68k microblaze mips nios2 riscv sandbox sh x86 xtensa -x arm,powerpc" stages: - stage: testsuites @@ -185,6 +196,34 @@ stages: steps: - script: make pip + - job: count_built_machines + displayName: 'Ensure we build all possible machines' + pool: + vmImage: $(ubuntu_vm) + container: + image: $(ci_runner_image) + options: $(container_option) + steps: + - script: | + BMANARGS="-o /tmp --dry-run -v" + # First get the total number of boards + total=$(tools/buildman/buildman ${BMANARGS} | grep "Total boards to build for each commit" | cut -d ' ' -f 8) + # Now build up the list of what each job built. + built="$(tools/buildman/buildman ${BMANARGS} $(am33xx_kirkwood_ls1_mvebu_omap) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(amlogic_bcm_boundary_engicam_siemens_technexion_oradex) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(arm_nxp_minus_imx_and_at91) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(imx) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(rk) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(sunxi) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(powerpc) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(arm_catch_all) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(aarch64_catch_all) | grep '^ ')" + built="$built $(tools/buildman/buildman ${BMANARGS} $(everything_but_arm_and_powerpc) | grep '^ ')" + # Finally see how many machines that is. + actual=$(tools/buildman/buildman ${BMANARGS} $built | grep "Total boards to build for each commit" | cut -d ' ' -f 8) + echo We would build a total of $actual out of $total platforms this CI run + [ $actual -eq $total ] && exit 0 || exit 1 + - job: create_test_py_wrapper_script displayName: 'Create and stage a wrapper for test.py runs' pool: @@ -473,29 +512,29 @@ stages: pool: vmImage: $(ubuntu_vm) strategy: - # Use almost the same target division in .travis.yml, only merged - # 3 small build jobs (arc/microblaze/xtensa) into one. + # We split the world up in to 10 jobs as we can have at most 10 + # parallel jobs going on the free tier of Azure. matrix: - am33xx_at91_kirkwood_mvebu_omap: - BUILDMAN: "am33xx at91_kirkwood mvebu omap -x siemens" + am33xx_kirkwood_ls1_mvebu_omap: + BUILDMAN: $(am33xx_kirkwood_ls1_mvebu_omap) amlogic_bcm_boundary_engicam_siemens_technexion_oradex: - BUILDMAN: "amlogic bcm boundary engicam siemens technexion toradex -x mips" - arm_nxp_minus_imx: - BUILDMAN: "freescale -x powerpc,m68k,imx,mx" + BUILDMAN: $(amlogic_bcm_boundary_engicam_siemens_technexion_oradex) + arm_nxp_minus_imx_and_at91: + BUILDMAN: $(arm_nxp_minus_imx_and_at91) imx: - BUILDMAN: "mx imx -x boundary,engicam,technexion,toradex" + BUILDMAN: $(imx) rk: - BUILDMAN: "rk" + BUILDMAN: $(rk) sunxi: - BUILDMAN: "sunxi" + BUILDMAN: $(sunxi) powerpc: - BUILDMAN: "powerpc" + BUILDMAN: $(powerpc) arm_catch_all: - BUILDMAN: "arm -x aarch64,am33xx,at91,bcm,ls1,kirkwood,mvebu,omap,rk,siemens,mx,sunxi,technexion,toradex" + BUILDMAN: $(arm_catch_all) aarch64_catch_all: - BUILDMAN: "aarch64 -x amlogic,bcm,engicam,imx,ls1,ls2,lx216,mvebu,rk,siemens,sunxi,toradex" + BUILDMAN: $(aarch64_catch_all) everything_but_arm_and_powerpc: - BUILDMAN: "-x arm,powerpc" + BUILDMAN: $(everything_but_arm_and_powerpc) steps: - script: | cat << EOF > build.sh @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = NAME = # *DOCUMENTATION* diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index d4c64f2d60d..c3f8dac648b 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -396,6 +396,251 @@ static int count_ranges(void) return count; } +#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) +#define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) + +enum walker_state { + WALKER_STATE_START = 0, + WALKER_STATE_TABLE, + WALKER_STATE_REGION, /* block or page, depending on level */ +}; + + +/** + * __pagetable_walk() - Walk through the pagetable and call cb() for each memory region + * + * This is a software implementation of the ARMv8-A MMU translation table walk. As per + * section D5.4 of the ARMv8-A Architecture Reference Manual. It recursively walks the + * 4 or 3 levels of the page table and calls the callback function for each discrete + * region of memory (that being the discovery of a new table, a collection of blocks + * with the same attributes, or of pages with the same attributes). + * + * U-Boot picks the smallest number of virtual address (VA) bits that it can based on the + * memory map configured by the board. If this is less than 39 then the MMU will only use + * 3 levels of translation instead of 3 - skipping level 0. + * + * Each level has 512 entries of 64-bits each. Each entry includes attribute bits and + * an address. When the attribute bits indicate a table, the address is the physical + * address of the table, so we can recursively call _pagetable_walk() on it (after calling + * @cb). If instead they indicate a block or page, we record the start address and attributes + * and continue walking until we find a region with different attributes, or the end of the + * table, in either case we call @cb with the start and end address of the region. + * + * This approach can be used to fully emulate the MMU's translation table walk, as per + * Figure D5-25 of the ARMv8-A Architecture Reference Manual. + * + * @addr: The address of the table to walk + * @tcr: The TCR register value + * @level: The current level of the table + * @cb: The callback function to call for each region + * @priv: Private data to pass to the callback function + */ +static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, void *priv) +{ + u64 *table = (u64 *)addr; + u64 attrs, last_attrs = 0, last_addr = 0, entry_start = 0; + int i; + u64 va_bits = 64 - (tcr & (BIT(6) - 1)); + static enum walker_state state[4] = { 0 }; + static bool exit; + + if (!level) { + exit = false; + if (va_bits < 39) + level = 1; + } + + state[level] = WALKER_STATE_START; + + /* Walk through the table entries */ + for (i = 0; i < MAX_PTE_ENTRIES; i++) { + u64 pte = table[i]; + u64 _addr = pte & GENMASK_ULL(va_bits, PAGE_SHIFT); + + if (exit) + return; + + if (pte_type(&pte) == PTE_TYPE_FAULT) + continue; + + attrs = pte & ALL_ATTRS; + /* If we're currently inside a block or set of pages */ + if (state[level] > WALKER_STATE_START && state[level] != WALKER_STATE_TABLE) { + /* + * Continue walking if this entry has the same attributes as the last and + * is one page/block away -- it's a contiguous region. + */ + if (attrs == last_attrs && _addr == last_addr + (1 << level2shift(level))) { + last_attrs = attrs; + last_addr = _addr; + continue; + } else { + /* We either hit a table or a new region */ + exit = cb(entry_start, last_addr + (1 << level2shift(level)), + va_bits, level, priv); + if (exit) + return; + state[level] = WALKER_STATE_START; + } + } + last_attrs = attrs; + last_addr = _addr; + + if (PTE_IS_TABLE(pte, level)) { + /* After the end of the table might be corrupted data */ + if (!_addr || (pte & 0xfff) > 0x3ff) + return; + state[level] = WALKER_STATE_TABLE; + /* Signify the start of a table */ + exit = cb(pte, 0, va_bits, level, priv); + if (exit) + return; + + /* Go down a level */ + __pagetable_walk(_addr, tcr, level + 1, cb, priv); + state[level] = WALKER_STATE_START; + } else if (pte_type(&pte) == PTE_TYPE_BLOCK || pte_type(&pte) == PTE_TYPE_PAGE) { + /* We foud a block or page, start walking */ + entry_start = pte; + state[level] = WALKER_STATE_REGION; + } + } + + if (state[level] > WALKER_STATE_START) + exit = cb(entry_start, last_addr + (1 << level2shift(level)), va_bits, level, priv); +} + +static void pretty_print_pte_type(u64 pte) +{ + switch (pte_type(&pte)) { + case PTE_TYPE_FAULT: + printf(" %-5s", "Fault"); + break; + case PTE_TYPE_BLOCK: + printf(" %-5s", "Block"); + break; + case PTE_TYPE_PAGE: + printf(" %-5s", "Pages"); + break; + default: + printf(" %-5s", "Unk"); + } +} + +static void pretty_print_table_attrs(u64 pte) +{ + int ap = (pte & PTE_TABLE_AP) >> 61; + + printf(" | %2s %10s", + (ap & 2) ? "RO" : "", + (ap & 1) ? "!EL0" : ""); + printf(" | %3s %2s %2s", + (pte & PTE_TABLE_PXN) ? "PXN" : "", + (pte & PTE_TABLE_XN) ? "XN" : "", + (pte & PTE_TABLE_NS) ? "NS" : ""); +} + +static void pretty_print_block_attrs(u64 pte) +{ + u64 attrs = pte & PMD_ATTRINDX_MASK; + + switch (attrs) { + case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): + printf(" | %-13s", "Device-nGnRnE"); + break; + case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE): + printf(" | %-13s", "Device-nGnRE"); + break; + case PTE_BLOCK_MEMTYPE(MT_DEVICE_GRE): + printf(" | %-13s", "Device-GRE"); + break; + case PTE_BLOCK_MEMTYPE(MT_NORMAL_NC): + printf(" | %-13s", "Normal-NC"); + break; + case PTE_BLOCK_MEMTYPE(MT_NORMAL): + printf(" | %-13s", "Normal"); + break; + default: + printf(" | %-13s", "Unknown"); + } +} + +static void pretty_print_block_memtype(u64 pte) +{ + u64 share = pte & (3 << 8); + + switch (share) { + case PTE_BLOCK_NON_SHARE: + printf(" | %-16s", "Non-shareable"); + break; + case PTE_BLOCK_OUTER_SHARE: + printf(" | %-16s", "Outer-shareable"); + break; + case PTE_BLOCK_INNER_SHARE: + printf(" | %-16s", "Inner-shareable"); + break; + default: + printf(" | %-16s", "Unknown"); + } +} + +static void print_pte(u64 pte, int level) +{ + if (PTE_IS_TABLE(pte, level)) { + printf(" %-5s", "Table"); + pretty_print_table_attrs(pte); + } else { + pretty_print_pte_type(pte); + pretty_print_block_attrs(pte); + pretty_print_block_memtype(pte); + } + printf("\n"); +} + +/** + * pagetable_print_entry() - Callback function to print a single pagetable region + * + * This is the default callback used by @dump_pagetable(). It does some basic pretty + * printing (see example in the U-Boot arm64 documentation). It can be replaced by + * a custom callback function if more detailed information is needed. + * + * @start_attrs: The start address and attributes of the region (or table address) + * @end: The end address of the region (or 0 if it's a table) + * @va_bits: The number of bits used for the virtual address + * @level: The level of the region + * @priv: Private data for the callback (unused) + */ +static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int level, void *priv) +{ + u64 _addr = start_attrs & GENMASK_ULL(va_bits, PAGE_SHIFT); + int indent = va_bits < 39 ? level - 1 : level; + + printf("%*s", indent * 2, ""); + if (PTE_IS_TABLE(start_attrs, level)) + printf("[%#011llx]%14s", _addr, ""); + else + printf("[%#011llx - %#011llx]", _addr, end); + + printf("%*s | ", (3 - level) * 2, ""); + print_pte(start_attrs, level); + + return false; +} + +void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv) +{ + __pagetable_walk(ttbr, tcr, 0, cb, priv); +} + +void dump_pagetable(u64 ttbr, u64 tcr) +{ + u64 va_bits = 64 - (tcr & (BIT(6) - 1)); + + printf("Walking pagetable at %p, va_bits: %lld. Using %d levels\n", (void *)ttbr, + va_bits, va_bits < 39 ? 3 : 4); + walk_pagetable(ttbr, tcr, pagetable_print_entry, NULL); +} + /* Returns the estimated required size of all page tables */ __weak u64 get_page_table_size(void) { diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 39699027d3f..06c234afbeb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -864,7 +864,6 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ - imx6ulz-bsh-smm-m2.dtb \ imx6ulz-14x14-evk.dtb dtb-$(CONFIG_ARCH_MX6) += \ @@ -916,8 +915,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-phg.dtb \ - imx8mn-bsh-smm-s2.dtb \ - imx8mn-bsh-smm-s2pro.dtb \ imx8mq-cm.dtb \ imx8mn-var-som-symphony.dtb \ imx8mq-mnt-reform2.dtb \ diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts index 26b0f1b3cea..3076fb9f344 100644 --- a/arch/arm/dts/corstone1000-fvp.dts +++ b/arch/arm/dts/corstone1000-fvp.dts @@ -49,3 +49,28 @@ clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; + diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi index 1e0ec075e4c..5d9d95b21cb 100644 --- a/arch/arm/dts/corstone1000.dtsi +++ b/arch/arm/dts/corstone1000.dtsi @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/dts/imx6ulz-bsh-smm-m2.dts deleted file mode 100644 index 59bcfc9a6b1..00000000000 --- a/arch/arm/dts/imx6ulz-bsh-smm-m2.dts +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include "imx6ulz.dtsi" - -/ { - model = "BSH SMM M2"; - compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; - - chosen { - stdout-path = &uart4; - }; - - usdhc2_pwrseq: usdhc2-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - bus-width = <4>; - no-1-8-v; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - cap-sdio-irq; - mmc-pwrseq = <&usdhc2_pwrseq>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&wdog1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ - MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ - MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ - MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ - MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi deleted file mode 100644 index c11895d9d58..00000000000 --- a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Collabora Ltd. - * Copyright 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include "imx8mn.dtsi" - -/ { - chosen { - stdout-path = &uart4; - }; - - fec_supply: fec-supply-en { - compatible = "regulator-fixed"; - vin-supply = <&buck4_reg>; - regulator-name = "tja1101_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usdhc2_pwrseq: usdhc2-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwrseq>; - reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_espi2>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - phy-supply = <&fec_supply>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - reset-assert-us = <20>; - reset-deassert-us = <2000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - bd71847: pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - /* PMIC_BUCK1 - VDD_SOC */ - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - /* PMIC_BUCK2 - VDD_ARM */ - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */ - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - /* PMIC_BUCK6 - VDD_3V3 */ - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - /* PMIC_BUCK7 - VDD_1V8 */ - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - /* PMIC_BUCK8 - NVCC_DRAM */ - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - /* PMIC_LDO1 - NVCC_SNVS_1V8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - /* PMIC_LDO2 - VDD_SNVS_0V8 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - /* PMIC_LDO3 - VDDA_1V8 */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - /* PMIC_LDO4 - VDD_MIPI_0V9 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - /* PMIC_LDO6 - VDD_MIPI_1V2 */ - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MN_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bluetooth>; - shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - }; -}; - -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - mmc-pwrseq = <&usdhc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_bluetooth: bluetoothgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */ - MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */ - MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */ - >; - }; - - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 - MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 - MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 - MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090 - MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090 - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016 - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016 - MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090 - MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016 - MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */ - MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */ - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */ - MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2 - MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2 - >; - }; - - pinctrl_pmic: pmicirq { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040 - MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040 - MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040 - MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 - MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6 - >; - }; - - pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */ - MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */ - MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */ - MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */ - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2.dts b/arch/arm/dts/imx8mn-bsh-smm-s2.dts deleted file mode 100644 index 33f98582eac..00000000000 --- a/arch/arm/dts/imx8mn-bsh-smm-s2.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Collabora Ltd. - * Copyright 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include "imx8mn-bsh-smm-s2-common.dtsi" - -/ { - model = "BSH SMM S2"; - compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn"; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x10000000>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 - MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 - MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 - MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 - MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 - MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 - MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 - MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 - MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 - MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 - MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 - MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 - MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 - MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 - MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts b/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts deleted file mode 100644 index fbbb3367037..00000000000 --- a/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Collabora Ltd. - * Copyright 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include "imx8mn-bsh-smm-s2-common.dtsi" -#include <dt-bindings/sound/tlv320aic31xx.h> - -/ { - model = "BSH SMM S2 PRO"; - compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn"; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x20000000>; - }; - - sound-tlv320aic31xx { - compatible = "fsl,imx-audio-tlv320aic31xx"; - model = "tlv320aic31xx-hifi"; - audio-cpu = <&sai3>; - audio-codec = <&tlv320dac3101>; - audio-asrc = <&easrc>; - audio-routing = - "Ext Spk", "SPL", - "Ext Spk", "SPR"; - mclk-id = <PLL_CLKIN_BCLK>; - }; - - vdd_input: vdd_input { - compatible = "regulator-fixed"; - regulator-name = "vdd_input"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&easrc { - fsl,asrc-rate = <48000>; - fsl,asrc-format = <10>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - tlv320dac3101: audio-codec@18 { - compatible = "ti,tlv320dac3101"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dac_rst>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <&buck4_reg>; - SPRVDD-supply = <&vdd_input>; - SPLVDD-supply = <&vdd_input>; - AVDD-supply = <&buck4_reg>; - IOVDD-supply = <&buck4_reg>; - DVDD-supply = <&buck5_reg>; - reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - ai31xx-micbias-vg = <MICBIAS_AVDDV>; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - }; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MN_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_dac_rst: dacrstgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */ - >; - }; - - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 - MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 - MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 - MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0 - MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0 - MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0 - MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0 - MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0 - MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4 - MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4 - MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4 - MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4 - MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4 - MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6 - MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6 - MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6 - MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6 - MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6 - MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi index b9e3db7de93..98f71c73c98 100644 --- a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi @@ -4,9 +4,3 @@ */ #include "imx8mp-venice-u-boot.dtsi" - -&eqos { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - /delete-property/ assigned-clock-rates; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi index 240fbc1b568..a90794d8108 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi @@ -243,3 +243,8 @@ &wdog1 { bootph-pre-ram; }; + +/* gpio-usb-con not supported yet in U-Boot so make this a host for now */ +&usb_dwc3_0 { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index 1766adc5d4c..467cac68d0f 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -80,6 +80,7 @@ ti-spl_unsigned { filename = "tispl.bin_unsigned"; + symlink = "tispl.bin"; pad-byte = <0xff>; fit { diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index 162d4800b17..f0b66f0cb94 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -79,6 +79,7 @@ &binman { tiboot3-am62x-gp-evm.bin { filename = "tiboot3-am62x-gp-evm.bin"; + symlink = "tiboot3.bin"; ti-secure-rom { content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index 793ed4ae8ae..c7e849816a6 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -4,7 +4,7 @@ / { chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0; + u-boot,spl-boot-order = &sdmmc0, &sdhci; }; }; diff --git a/arch/arm/include/asm/arch-meson/usb-gx.h b/arch/arm/include/asm/arch-meson/usb-gx.h deleted file mode 100644 index 61f1809df9c..00000000000 --- a/arch/arm/include/asm/arch-meson/usb-gx.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ -#ifndef _ARCH_MESON_USB_GX_H_ -#define _ARCH_MESON_USB_GX_H_ - -#include <generic-phy.h> -#include <linux/usb/otg.h> - -/* TOFIX add set_mode to struct phy_ops */ -void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode); - -int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode); - -#endif diff --git a/arch/arm/include/asm/arch-meson/usb.h b/arch/arm/include/asm/arch-meson/usb.h deleted file mode 100644 index b794b5ce77a..00000000000 --- a/arch/arm/include/asm/arch-meson/usb.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef __MESON_USB_H__ -#define __MESON_USB_H__ - -int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode); - -#endif /* __MESON_USB_H__ */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index ce655ce7a95..0ab681c893d 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -51,7 +51,7 @@ #define PTE_TABLE_PXN (1UL << 59) #define PTE_TABLE_XN (1UL << 60) -#define PTE_TABLE_AP (1UL << 61) +#define PTE_TABLE_AP (3UL << 61) #define PTE_TABLE_NS (1UL << 63) /* @@ -129,6 +129,62 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) asm volatile("isb"); } +static inline void get_ttbr_tcr_mair(int el, u64 *table, u64 *tcr, u64 *attr) +{ + if (el == 1) { + asm volatile("mrs %0, ttbr0_el1" : "=r" (*table)); + asm volatile("mrs %0, tcr_el1" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el1" : "=r" (*attr)); + } else if (el == 2) { + asm volatile("mrs %0, ttbr0_el2" : "=r" (*table)); + asm volatile("mrs %0, tcr_el2" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el2" : "=r" (*attr)); + } else if (el == 3) { + asm volatile("mrs %0, ttbr0_el3" : "=r" (*table)); + asm volatile("mrs %0, tcr_el3" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el3" : "=r" (*attr)); + } else { + hang(); + } +} + +/** + * typedef pte_walker_cb_t - callback function for walk_pagetable. + * + * This function is called when the walker finds a table entry + * or after parsing a block or pages. For a table the @end address + * is 0, and @addr is the address of the table. Otherwise, they + * are the start and end physical addresses of the block or page. + * + * @addr: PTE start address (PA), or address of table. Includes attributes. + * @end: End address of the region (or 0 for a table) + * @va_bits: Number of bits in the virtual address + * @level: Table level + * @priv: Private data for the callback + * + * Return: true to stop walking, false to continue + */ +typedef bool (*pte_walker_cb_t)(u64 addr, u64 end, int va_bits, int level, void *priv); + +/** + * walk_pagetable() - Walk the pagetable at ttbr and call @cb for each region + * + * @ttbr: Address of the pagetable to dump + * @tcr: TCR value to use + * @cb: Callback function to call for each entry + * @priv: Private data for the callback + */ +void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv); + +/** + * dump_pagetable() - Dump the pagetable at ttbr, printing each region and + * level. + * + * @ttbr: Address of the pagetable to dump + * @tcr: TCR value to use + */ +void dump_pagetable(u64 ttbr, u64 tcr); + struct mm_region { u64 virt; u64 phys; diff --git a/arch/arm/mach-davinci/include/mach/timer_defs.h b/arch/arm/mach-davinci/include/mach/timer_defs.h index 110e67e454c..a25f6d1796a 100644 --- a/arch/arm/mach-davinci/include/mach/timer_defs.h +++ b/arch/arm/mach-davinci/include/mach/timer_defs.h @@ -20,24 +20,4 @@ struct davinci_timer { u_int32_t wdtcr; }; -#define DV_TIMER_TCR_ENAMODE_MASK 3 - -#define DV_TIMER_TCR_ENAMODE12_SHIFT 6 -#define DV_TIMER_TCR_CLKSRC12_SHIFT 8 -#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10 -#define DV_TIMER_TCR_CAPMODE12_SHIFT 11 -#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12 -#define DV_TIMER_TCR_ENAMODE34_SHIFT 22 -#define DV_TIMER_TCR_CLKSRC34_SHIFT 24 -#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26 -#define DV_TIMER_TCR_CAPMODE34_SHIFT 27 -#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28 - -#define DV_WDT_ENABLE_SYS_RESET 0x00020000 -#define DV_WDT_TRIGGER_SYS_RESET 0x00020002 - -#ifdef CONFIG_HW_WATCHDOG -void davinci_hw_watchdog_enable(void); -void davinci_hw_watchdog_reset(void); -#endif #endif /* _TIMER_DEFS_H_ */ diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c index f2990f71877..474dc6b1abd 100644 --- a/arch/arm/mach-davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c @@ -98,34 +98,3 @@ ulong get_tbclk(void) { return gd->arch.timer_rate_hz; } - -#ifdef CONFIG_HW_WATCHDOG -static struct davinci_timer * const wdttimer = - (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE; - -/* - * See prufw2.pdf for using Timer as a WDT - */ -void davinci_hw_watchdog_enable(void) -{ - writel(0x0, &wdttimer->tcr); - writel(0x0, &wdttimer->tgcr); - /* TIMMODE = 2h */ - writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr); - writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12); - writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34); - writel(2 << 22, &wdttimer->tcr); - writel(0x0, &wdttimer->tim12); - writel(0x0, &wdttimer->tim34); - /* set WDEN bit, WDKEY 0xa5c6 */ - writel(0xa5c64000, &wdttimer->wdtcr); - /* clear counter register */ - writel(0xda7e4000, &wdttimer->wdtcr); -} - -void davinci_hw_watchdog_reset(void) -{ - writel(0xa5c64000, &wdttimer->wdtcr); - writel(0xda7e4000, &wdttimer->wdtcr); -} -#endif diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index c7962ead2d5..56e1a8f8be7 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -395,10 +395,10 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc, } /***************************************************/ -static char dek_blob_help_text[] = +U_BOOT_LONGHELP(dek_blob, "src dst len - Encapsulate and create blob of data\n" " $len bits long at address $src and\n" - " store the result at address $dst.\n"; + " store the result at address $dst.\n"); U_BOOT_CMD( dek_blob, 4, 1, do_dek_blob, diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 9925c992268..9f37e611a1e 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -134,12 +134,12 @@ free_m: } /***************************************************/ -static char mfgprot_help_text[] = +U_BOOT_LONGHELP(mfgprot, "Usage:\n" "Print the public key for Manufacturing Protection\n" "\tmfgprot pubk\n" "Generates a Manufacturing Protection signature\n" - "\tmfgprot sign <data_addr> <size>"; + "\tmfgprot sign <data_addr> <size>\n"); U_BOOT_CMD( mfgprot, 4, 1, do_mfgprot, diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c index f13dfc15516..df8c22b5706 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc.c +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -597,7 +597,7 @@ exit: } #endif /* CONFIG_IMX_SNVS_SEC_SC_AUTO */ -static char snvs_cfg_help_text[] = +U_BOOT_LONGHELP(snvs_cfg, "snvs_cfg\n" "\thp.lock\n" "\thp.secvio_ctl\n" @@ -618,7 +618,7 @@ static char snvs_cfg_help_text[] = "\tlp.act_tamper_routing_ctl1\n" "\tlp.act_tamper_routing_ctl2\n" "\n" - "ALL values should be in hexadecimal format"; + "ALL values should be in hexadecimal format\n"); #define NB_REGISTERS 18 static int do_snvs_cfg(struct cmd_tbl *cmdtp, int flag, int argc, @@ -662,7 +662,7 @@ U_BOOT_CMD(snvs_cfg, snvs_cfg_help_text ); -static char snvs_dgo_cfg_help_text[] = +U_BOOT_LONGHELP(snvs_dgo_cfg, "snvs_dgo_cfg\n" "\ttamper_offset_ctl\n" "\ttamper_pull_ctl\n" @@ -671,7 +671,7 @@ static char snvs_dgo_cfg_help_text[] = "\ttamper_misc_ctl\n" "\ttamper_core_volt_mon_ctl\n" "\n" - "ALL values should be in hexadecimal format"; + "ALL values should be in hexadecimal format\n"); static int do_snvs_dgo_cfg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -702,12 +702,12 @@ U_BOOT_CMD(snvs_dgo_cfg, snvs_dgo_cfg_help_text ); -static char tamper_pin_cfg_help_text[] = +U_BOOT_LONGHELP(tamper_pin_cfg, "snvs_dgo_cfg\n" "\tpad\n" "\tvalue\n" "\n" - "ALL values should be in hexadecimal format"; + "ALL values should be in hexadecimal format\n"); static int do_tamper_pin_cfg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -734,7 +734,7 @@ U_BOOT_CMD(tamper_pin_cfg, tamper_pin_cfg_help_text ); -static char snvs_clear_status_help_text[] = +U_BOOT_LONGHELP(snvs_clear_status, "snvs_clear_status\n" "\tHPSR\n" "\tHPSVSR\n" @@ -742,7 +742,7 @@ static char snvs_clear_status_help_text[] = "\tLPTDSR\n" "\n" "Write the status registers with the value provided," - " clearing the status"; + " clearing the status\n"); static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -778,9 +778,9 @@ U_BOOT_CMD(snvs_clear_status, snvs_clear_status_help_text ); -static char snvs_sec_status_help_text[] = +U_BOOT_LONGHELP(snvs_sec_status, "snvs_sec_status\n" - "Display information about the security related to tamper and secvio"; + "Display information about the security related to tamper and secvio\n"); static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 046c78547b2..d1fdaec7043 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -137,12 +137,14 @@ config TARGET_IMX8MN_BSH_SMM_S2 select IMX8MN select SUPPORT_SPL select IMX8M_DDR3L + imply OF_UPSTREAM config TARGET_IMX8MN_BSH_SMM_S2PRO bool "imx8mn-bsh-smm-s2pro" select IMX8MN select SUPPORT_SPL select IMX8M_DDR3L + imply OF_UPSTREAM config TARGET_IMX8MN_EVK bool "imx8mn LPDDR4 EVK board" diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 15ee2b933f6..7800553ae8d 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -481,6 +481,7 @@ config TARGET_MX6ULZ_SMM_M2 select DM_MTD select DM_THERMAL select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_MYS_6ULX bool "MYiR MYS-6ULX" diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h b/arch/arm/mach-k3/include/mach/k3-qos.h index e00e1de5b9c..eb0f2a0448a 100644 --- a/arch/arm/mach-k3/include/mach/k3-qos.h +++ b/arch/arm/mach-k3/include/mach/k3-qos.h @@ -9,6 +9,26 @@ #include <linux/kernel.h> +/* K3_QOS_REG: Registers to configure the channel for a given endpoint */ + +#define K3_QOS_REG(base_reg, i) (base_reg + 0x100 + (i) * 4) + +#define K3_QOS_VAL(qos, orderid, asel, epriority, virtid, atype) \ + (qos << 0 | \ + orderid << 4 | \ + asel << 8 | \ + epriority << 12 | \ + virtid << 16 | \ + atype << 28) + +/* + * K3_QOS_GROUP_REG: Registers to set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. + */ +#define K3_QOS_GROUP_REG(base_reg, i) (base_reg + (i) * 4) + +#define K3_QOS_GROUP_DEFAULT_VAL_LOW 0x76543210 +#define K3_QOS_GROUP_DEFAULT_VAL_HIGH 0xfedcba98 struct k3_qos_data { u32 reg; u32 val; diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index c2024f2500d..e9ed8cb267c 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -23,6 +23,22 @@ #include "../sysfw-loader.h" #include "../common.h" +/* NAVSS North Bridge (NB) registers */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03803000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-7 to VBUSM.C thread number + * Bit[1] maps orderID 8-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) + #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_TARGET_J721E_R5_EVM) @@ -124,6 +140,13 @@ void k3_mmc_restart_clock(void) } #endif +/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -288,6 +311,11 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); #endif spl_enable_cache(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index fe9766e9b4b..05453fcad41 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -22,6 +22,24 @@ #include "../sysfw-loader.h" #include "../common.h" +/* NAVSS North Bridge (NB) */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-3 to VBUSM.C thread number + * Bit[1] maps orderID 4-9 to VBUSM.C thread number + * Bit[2] maps orderID 10-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) +#define NB_THREADMAP_BIT2 BIT(2) + struct fwl_data cbass_hc_cfg0_fwls[] = { { "PCIE0_CFG", 2577, 7 }, { "EMMC8SS0_CFG", 2579, 4 }, @@ -123,6 +141,13 @@ void k3_mmc_restart_clock(void) } } +/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -295,6 +320,11 @@ void board_init_f(ulong dummy) do_dt_magic(); #endif k3_mem_init(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); } #endif diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 1ce13e0f494..07b5d7d7504 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -23,6 +23,24 @@ #define J784S4_MAX_DDR_CONTROLLERS 4 +/* NAVSS North Bridge (NB) */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-3 to VBUSM.C thread number + * Bit[1] maps orderID 4-9 to VBUSM.C thread number + * Bit[2] maps orderID 10-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) +#define NB_THREADMAP_BIT2 BIT(2) + struct fwl_data infra_cbass0_fwls[] = { { "PSC0", 5, 1 }, { "PLL_CTRL0", 6, 1 }, @@ -94,6 +112,13 @@ static void ctrl_mmr_unlock(void) mmr_unlock(CTRL_MMR0_BASE, 7); } +/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -210,6 +235,11 @@ void board_init_f(ulong dummy) { k3_spl_init(); k3_mem_init(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h index c74d69a28f8..84a6dc72406 100644 --- a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h @@ -6,80 +6,6 @@ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */ -#define QOS_0 (0 << 0) -#define QOS_1 (1 << 0) -#define QOS_2 (2 << 0) -#define QOS_3 (3 << 0) -#define QOS_4 (4 << 0) -#define QOS_5 (5 << 0) -#define QOS_6 (6 << 0) -#define QOS_7 (7 << 0) - -#define ORDERID_0 (0 << 4) -#define ORDERID_1 (1 << 4) -#define ORDERID_2 (2 << 4) -#define ORDERID_3 (3 << 4) -#define ORDERID_4 (4 << 4) -#define ORDERID_5 (5 << 4) -#define ORDERID_6 (6 << 4) -#define ORDERID_7 (7 << 4) -#define ORDERID_8 (8 << 4) -#define ORDERID_9 (9 << 4) -#define ORDERID_10 (10 << 4) -#define ORDERID_11 (11 << 4) -#define ORDERID_12 (12 << 4) -#define ORDERID_13 (13 << 4) -#define ORDERID_14 (14 << 4) -#define ORDERID_15 (15 << 4) - -#define ASEL_0 (0 << 8) -#define ASEL_1 (1 << 8) -#define ASEL_2 (2 << 8) -#define ASEL_3 (3 << 8) -#define ASEL_4 (4 << 8) -#define ASEL_5 (5 << 8) -#define ASEL_6 (6 << 8) -#define ASEL_7 (7 << 8) -#define ASEL_8 (8 << 8) -#define ASEL_9 (9 << 8) -#define ASEL_10 (10 << 8) -#define ASEL_11 (11 << 8) -#define ASEL_12 (12 << 8) -#define ASEL_13 (13 << 8) -#define ASEL_14 (14 << 8) -#define ASEL_15 (15 << 8) - -#define EPRIORITY_0 (0 << 12) -#define EPRIORITY_1 (1 << 12) -#define EPRIORITY_2 (2 << 12) -#define EPRIORITY_3 (3 << 12) -#define EPRIORITY_4 (4 << 12) -#define EPRIORITY_5 (5 << 12) -#define EPRIORITY_6 (6 << 12) -#define EPRIORITY_7 (7 << 12) - -#define VIRTID_0 (0 << 16) -#define VIRTID_1 (1 << 16) -#define VIRTID_2 (2 << 16) -#define VIRTID_3 (3 << 16) -#define VIRTID_4 (4 << 16) -#define VIRTID_5 (5 << 16) -#define VIRTID_6 (6 << 16) -#define VIRTID_7 (7 << 16) -#define VIRTID_8 (8 << 16) -#define VIRTID_9 (9 << 16) -#define VIRTID_10 (10 << 16) -#define VIRTID_11 (11 << 16) -#define VIRTID_12 (12 << 16) -#define VIRTID_13 (13 << 16) -#define VIRTID_14 (14 << 16) -#define VIRTID_15 (15 << 16) - -#define ATYPE_0 (0 << 28) -#define ATYPE_1 (1 << 28) -#define ATYPE_2 (2 << 28) -#define ATYPE_3 (3 << 28) - #define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000 #define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400 #define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800 diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c index 9a82944d5fe..1d588acea4d 100644 --- a/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c @@ -12,20 +12,20 @@ struct k3_qos_data qos_data[] = { /* modules_qosConfig0 - 1 endpoints, 4 channels */ { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, - .val = ORDERID_8, + .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0), + .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0), }, { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1, - .val = ORDERID_8, + .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1), + .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0), }, { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2, - .val = ORDERID_8, + .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2), + .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0), }, { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3, - .val = ORDERID_8, + .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3), + .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0), }, /* Following registers set 1:1 mapping for orderID MAP1/MAP2 @@ -35,12 +35,12 @@ struct k3_qos_data qos_data[] = { /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */ { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0, - .val = 0x76543210, + .reg = K3_QOS_GROUP_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, }, { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4, - .val = 0xfedcba98, + .reg = K3_QOS_GROUP_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, }, }; diff --git a/arch/arm/mach-k3/r5/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile index 78325db402c..07bfb0dd935 100644 --- a/arch/arm/mach-k3/r5/j721e/Makefile +++ b/arch/arm/mach-k3/r5/j721e/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j721e_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h b/arch/arm/mach-k3/r5/j721e/j721e_qos.h new file mode 100644 index 00000000000..9ec0b7c6301 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define PULSAR_SL_MCU_0_MEMBDG_RMST0 0x45D10000 +#define PULSAR_SL_MCU_0_MEMBDG_WMST0 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_MEMBDG_RMST1 0x45D11000 +#define PULSAR_SL_MCU_0_MEMBDG_WMST1 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA2_UL_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define ICSS_G_MAIN_0_PR1_EXT_VBUSM 0x45D80000 +#define ICSS_G_MAIN_1_PR1_EXT_VBUSM 0x45D80400 +#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000 +#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82000 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82400 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D82C00 +#define PULSAR_SL_MAIN_0_MEMBDG_RMST0 0x45D84000 +#define PULSAR_SL_MAIN_0_MEMBDG_RMST1 0x45D84400 +#define PULSAR_SL_MAIN_0_MEMBDG_WMST0 0x45D84800 +#define PULSAR_SL_MAIN_0_MEMBDG_WMST1 0x45D84C00 +#define PULSAR_SL_MAIN_1_MEMBDG_RMST0 0x45D85000 +#define PULSAR_SL_MAIN_1_MEMBDG_RMST1 0x45D85400 +#define PULSAR_SL_MAIN_1_MEMBDG_WMST0 0x45D85800 +#define PULSAR_SL_MAIN_1_MEMBDG_WMST1 0x45D85C00 +#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define K3_C66_COREPAC_MAIN_0_C66_CFG 0x45D87000 +#define K3_C66_COREPAC_MAIN_1_C66_CFG 0x45D87400 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D88800 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D89800 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D89C00 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D8A000 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D8A400 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45D8A800 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45D8AC00 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45D8B000 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45D8B400 +#define VPFE_MAIN_0_VBUSM_DMA 0x45D8C000 +#define VPE_MAIN_0_VPDMA_MST0 0x45D8C400 +#define VPE_MAIN_0_VPDMA_MST1 0x45D8C800 +#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_HP 0x45D90000 +#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_LP 0x45D90400 +#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_HP 0x45D90800 +#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_LP 0x45D90C00 +#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_HP 0x45D91000 +#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_LP 0x45D91400 +#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_HP 0x45D91800 +#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_LP 0x45D91C00 +#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_HP 0x45D92000 +#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_LP 0x45D92400 +#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_HP 0x45D92800 +#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_LP 0x45D92C00 +#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_HP 0x45D93000 +#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_LP 0x45D93400 +#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_HP 0x45D93800 +#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_LP 0x45D93C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D98000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D98400 +#define USB3P0SS_16FFC_MAIN_1_MSTR0 0x45D98800 +#define USB3P0SS_16FFC_MAIN_1_MSTW0 0x45D98C00 +#define USB3P0SS_16FFC_MAIN_2_MSTR0 0x45D99000 +#define USB3P0SS_16FFC_MAIN_2_MSTW0 0x45D99400 +#define MLBSS2P0_MAIN_0_MLBSS_DMA_VBUSP 0x45D99C00 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9A000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9B000 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B400 +#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_RD 0x45D9B800 +#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_WR 0x45D9BC00 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_0_CPU0_PMST 0x45DA4000 +#define PULSAR_SL_MAIN_0_CPU1_PMST 0x45DA4400 +#define PULSAR_SL_MAIN_1_CPU0_PMST 0x45DA4800 +#define PULSAR_SL_MAIN_1_CPU1_PMST 0x45DA4C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_D5520MP2_MAIN_0_M_VBUSM_R 0x45DC0400 +#define K3_D5520MP2_MAIN_0_M_VBUSM_W 0x45DC0800 +#define K3_VXE384MP2_MAIN_0_M_VBUSM_R 0x45DC0C00 +#define K3_VXE384MP2_MAIN_0_M_VBUSM_W 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_R_ASYNC 0x45DC5000 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_W_ASYNC 0x45DC5800 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_R_ASYNC 0x45DC6000 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_W_ASYNC 0x45DC6800 diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c new file mode 100644 index 00000000000..713849a41b3 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j721e Quality of Service (QoS) Configuration Data + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <asm/arch/k3-qos.h> +#include "j721e_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 2 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 2 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data); diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile b/arch/arm/mach-k3/r5/j721s2/Makefile index 8588c5e4c39..89c0284b568 100644 --- a/arch/arm/mach-k3/r5/j721s2/Makefile +++ b/arch/arm/mach-k3/r5/j721s2/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j721s2_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h new file mode 100644 index 00000000000..ab3e4773a4f --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000 +#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400 +#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000 +#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000 +#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00 +#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000 +#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000 +#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400 +#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800 +#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00 +#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000 +#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400 +#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800 +#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800 +#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00 +#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800 +#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000 +#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400 +#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800 +#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00 +#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000 +#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400 +#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800 +#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00 diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c b/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c new file mode 100644 index 00000000000..54d81d929a2 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j721s2 Quality of Service (QoS) Configuration Data + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <asm/arch/k3-qos.h> +#include "j721s2_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 1 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 1 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data); diff --git a/arch/arm/mach-k3/r5/j784s4/Makefile b/arch/arm/mach-k3/r5/j784s4/Makefile index 9ce88305f57..0fd6cabd3fa 100644 --- a/arch/arm/mach-k3/r5/j784s4/Makefile +++ b/arch/arm/mach-k3/r5/j784s4/Makefile @@ -5,3 +5,4 @@ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j784s4_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index feaa13ee266..793bcac9324 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -134,7 +134,7 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { static const char * const mcu_clkout_mux_out0_parents[] = { "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", }; static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { @@ -338,7 +338,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 174, "mcu_clkout_mux_out0"), DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h new file mode 100644 index 00000000000..5851f889fe2 --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000 +#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400 +#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000 +#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000 +#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00 +#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000 +#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400 +#define PCIE_G3X4_128_MAIN_2_PCIE_MST_RD 0x45D9CC00 +#define PCIE_G3X4_128_MAIN_3_PCIE_MST_WR 0x45D9D400 +#define PCIE_G3X4_128_MAIN_2_PCIE_MST_WR 0x45D9D800 +#define PCIE_G3X4_128_MAIN_3_PCIE_MST_RD 0x45D9DC00 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000 +#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400 +#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800 +#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00 +#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000 +#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400 +#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800 +#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800 +#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00 +#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800 +#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000 +#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400 +#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800 +#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00 +#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000 +#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400 +#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800 +#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00 diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c b/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c new file mode 100644 index 00000000000..8c96da6ce56 --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j784s4 Quality of Service (QoS) Configuration Data + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <asm/arch/k3-qos.h> +#include "j784s4_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 1 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 1 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data); diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c index 6e970acf8b0..368f2916224 100644 --- a/arch/arm/mach-mediatek/mt7622/init.c +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -27,7 +27,7 @@ int dram_init(void) if (ret) return ret; - gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G); + gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G); return 0; } diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 0cb3c7a9fa4..040a70f581c 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -419,12 +419,12 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co return CMD_RET_SUCCESS; } -static char stm32key_help_text[] = +U_BOOT_LONGHELP(stm32key, "list : list the supported key with description\n" "stm32key select [<key>] : Select the key identified by <key> or display the key used for read/fuse command\n" "stm32key read [<addr> | -a ] : Read the curent key at <addr> or current / all (-a) key in OTP\n" "stm32key fuse [-y] <addr> : Fuse the current key at addr in OTP\n" - "stm32key close [-y] : Close the device\n"; + "stm32key close [-y] : Close the device\n"); U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text, U_BOOT_SUBCMD_MKENT(list, 1, 0, do_stm32key_list), diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 7772546b2fe..bfbf420fdb5 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -809,6 +809,27 @@ void __secure psci_system_suspend(u32 __always_unused function_id, clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); /* + * Make sure the OS would not get any spurious IWDG pretimeout IRQ + * right after the system wakes up. This may happen in case the SoC + * got woken up by another source than the IWDG pretimeout and the + * pretimeout IRQ arrived immediately afterward, but too late to be + * handled by the main loop above. In case either of the IWDG is + * enabled, ping it first and then return to the OS. + */ + + /* Ping IWDG1 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(22)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(23)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + + /* * The system has resumed successfully. Rewrite LR register stored * on stack with 'ep' value, so that on return from this PSCI call, * the code would jump to that 'ep' resume entry point code path diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 7a8fd3178ad..6eae5c2f557 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -118,7 +118,7 @@ static int optee_get_reserved_memory(uint32_t *start, uint32_t *size) node = ofnode_path("/reserved-memory/optee"); if (!ofnode_valid(node)) - return 0; + return -ENOENT; fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); *start = fdt_start; @@ -134,7 +134,7 @@ void stm32_init_tzc_for_optee(void) { const uint32_t dram_size = stm32mp_get_dram_size(); const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1); - uint32_t optee_base, optee_size, tee_shmem_base; + u32 optee_base = 0, optee_size = 0, tee_shmem_base; const uintptr_t tzc = STM32_TZC_BASE; int ret; diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 154a5d77490..d7869b2e368 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -109,7 +109,7 @@ int os_open(const char *pathname, int os_flags) */ flags |= O_CLOEXEC; - return open(pathname, flags, 0777); + return open(pathname, flags, 0644); } int os_close(int fd) @@ -746,7 +746,7 @@ int os_write_ram_buf(const char *fname) struct sandbox_state *state = state_get_current(); int fd, ret; - fd = open(fname, O_CREAT | O_WRONLY, 0777); + fd = open(fname, O_CREAT | O_WRONLY, 0644); if (fd < 0) return -ENOENT; ret = write(fd, state->ram_buf, state->ram_size); @@ -791,7 +791,7 @@ static int make_exec(char *fname, const void *data, int size) if (write(fd, data, size) < 0) return -EIO; close(fd); - if (chmod(fname, 0777)) + if (chmod(fname, 0755)) return -ENOEXEC; return 0; diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds index 52f13af3742..6ee8095b6cb 100644 --- a/arch/sandbox/cpu/u-boot.lds +++ b/arch/sandbox/cpu/u-boot.lds @@ -19,30 +19,18 @@ SECTIONS *(_u_boot_sandbox_getopt_end) } - efi_runtime_start : { - *(___efi_runtime_start) - } - efi_runtime : { + __efi_runtime_start = .; *(efi_runtime_text) *(efi_runtime_data) - } - - efi_runtime_stop : { - *(___efi_runtime_stop) - } - - efi_runtime_rel_start : { - *(___efi_runtime_rel_start) + __efi_runtime_stop = .; } efi_runtime_rel : { + __efi_runtime_rel_start = .; *(.relefi_runtime_text) *(.relefi_runtime_data) - } - - efi_runtime_rel_stop : { - *(___efi_runtime_rel_stop) + __efi_runtime_rel_stop = .; } .dynsym : diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index a2bc5a7ee60..d7d15a50bb6 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -5,7 +5,7 @@ # (C) Copyright 2002-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y += fdt_fixup.o interrupts.o sections.o +obj-y += fdt_fixup.o interrupts.o obj-$(CONFIG_PCI) += pci_io.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o diff --git a/arch/sandbox/lib/sections.c b/arch/sandbox/lib/sections.c deleted file mode 100644 index 2f2f3fbfdb8..00000000000 --- a/arch/sandbox/lib/sections.c +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - */ -#include <linux/compiler.h> - -char __efi_runtime_start[0] __section("___efi_runtime_start"); -char __efi_runtime_stop[0] __section("___efi_runtime_stop"); -char __efi_runtime_rel_start[0] - __section("___efi_runtime_rel_start"); -char __efi_runtime_rel_stop[0] - __section("___efi_runtime_rel_stop"); diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index e0de3318091..fdd28979e0b 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -24,9 +24,11 @@ #ifdef CONFIG_HAVE_INTEL_ME intel-descriptor { filename = CONFIG_FLASH_DESCRIPTOR_FILE; + assume-size = <0x1000>; }; intel-me { filename = CONFIG_INTEL_ME_FILE; + assume-size = <0x1ff000>; }; #endif #ifdef CONFIG_TPL @@ -87,6 +89,7 @@ #ifdef CONFIG_HAVE_MRC intel-mrc { offset = <CFG_X86_MRC_ADDR>; + assume-size = <0x2fc94>; }; #endif #ifdef CONFIG_FSP_VERSION1 @@ -98,6 +101,7 @@ #ifdef CONFIG_FSP_VERSION2 intel-descriptor { filename = CONFIG_FLASH_DESCRIPTOR_FILE; + assume-size = <4096>; }; intel-ifwi { filename = CONFIG_IFWI_INPUT_FILE; @@ -139,6 +143,7 @@ intel-vga { filename = CONFIG_VGA_BIOS_FILE; offset = <CONFIG_VGA_BIOS_ADDR>; + assume-size = <0x10000>; }; #endif #ifdef CONFIG_HAVE_VBT diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index a42a7e6bbd6..e38ce19ff7c 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -478,7 +478,6 @@ static int acpi_create_hpet(struct acpi_hpet *hpet) /* Fill out header fields. */ acpi_fill_header(header, "HPET"); - header->creator_revision = ASL_REVISION; header->length = sizeof(struct acpi_hpet); header->revision = acpi_get_table_revision(ACPITAB_HPET); @@ -569,7 +568,6 @@ void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, OEM_TABLE_ID, 8); memcpy(header->creator_id, ASLC_ID, 4); - header->creator_revision = 1; fadt->x_firmware_ctrl = map_to_sysmem(facs); fadt->x_dsdt = map_to_sysmem(dsdt); diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c index fbd99918a7f..56ae39bc6a1 100644 --- a/board/amd/versal2/cmds.c +++ b/board/amd/versal2/cmds.c @@ -71,10 +71,9 @@ static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, return cmd_process_error(cmdtp, ret); } -static char versal2_help_text[] = +U_BOOT_LONGHELP(versal2, "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n" -; + "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text, U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index 099eea60c39..5c57b902d14 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -6,14 +6,12 @@ #include <abuf.h> #include <adc.h> #include <asm/io.h> -#include <command.h> #include <display.h> #include <dm.h> #include <dm/lists.h> #include <env.h> #include <fdt_support.h> #include <linux/delay.h> -#include <linux/iopoll.h> #include <mipi_dsi.h> #include <mmc.h> #include <panel.h> @@ -21,8 +19,6 @@ #include <stdlib.h> #include <video_bridge.h> -#define BOOT_BROM_DOWNLOAD 0xef08a53c - #define GPIO0_BASE 0xfdd60000 #define GPIO4_BASE 0xfe770000 #define GPIO_SWPORT_DR_L 0x0000 @@ -36,14 +32,6 @@ #define GPIO_WRITEMASK(bits) ((bits) << 16) -#define SARADC_BASE 0xfe720000 -#define SARADC_DATA 0x0000 -#define SARADC_STAS 0x0004 -#define SARADC_ADC_STATUS BIT(0) -#define SARADC_CTRL 0x0008 -#define SARADC_INPUT_SRC_MSK 0x7 -#define SARADC_POWER_CTRL BIT(3) - #define DTB_DIR "rockchip/" struct rg3xx_model { @@ -170,63 +158,11 @@ static const struct rg353_panel rg353_panel_details[] = { }; /* - * The device has internal eMMC, and while some devices have an exposed - * clk pin you can ground to force a bypass not all devices do. As a - * result it may be possible for some devices to become a perma-brick - * if a corrupted TPL or SPL stage with a valid header is flashed to - * the internal eMMC. Add functionality to read ADC channel 0 (the func - * button) as early as possible in the boot process to provide some - * protection against this. If we ever get an open TPL stage, we should - * consider moving this function there. - */ -void read_func_button(void) -{ - int ret; - u32 reg; - - /* Turn off SARADC to reset it. */ - writel(0, (SARADC_BASE + SARADC_CTRL)); - - /* Enable channel 0 and power on SARADC. */ - writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL), - (SARADC_BASE + SARADC_CTRL)); - - /* - * Wait for data to be ready. Use timeout of 20000us from - * rockchip_saradc driver. - */ - ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg, - !(reg & SARADC_ADC_STATUS), 20000); - if (ret) { - printf("ADC Timeout"); - return; - } - - /* Read the data from the SARADC. */ - reg = readl((SARADC_BASE + SARADC_DATA)); - - /* Turn the SARADC back off so it's ready to be used again. */ - writel(0, (SARADC_BASE + SARADC_CTRL)); - - /* - * If the value is less than 30 the button is being pressed. - * Reset the device back into Rockchip download mode. - */ - if (reg <= 30) { - printf("download key pressed, entering download mode..."); - writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); - do_reset(NULL, 0, 0, NULL); - } -}; - -/* * Start LED very early so user knows device is on. Set color * to red. */ void spl_board_init(void) { - read_func_button(); - /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */ writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \ (GPIO_C7 | GPIO_C6 | GPIO_C5), diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig index b0e67dc8ef3..592b53e493c 100644 --- a/board/beagle/beagleplay/Kconfig +++ b/board/beagle/beagleplay/Kconfig @@ -12,6 +12,7 @@ config TARGET_AM625_A53_BEAGLEPLAY bool "BeagleBoard.org AM625 BeaglePlay running on A53" select ARM64 select BINMAN + select OF_SYSTEM_SETUP config TARGET_AM625_R5_BEAGLEPLAY bool "BeagleBoard.org AM625 BeaglePlay running on R5" diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env index 8dbfc2f7d24..354bc987d12 100644 --- a/board/beagle/beagleplay/beagleplay.env +++ b/board/beagle/beagleplay/beagleplay.env @@ -12,7 +12,7 @@ set_led_state_start_load=led led-0 on; led led-1 off; led led-2 on; led led-3 off; led led-4 on boot=mmc mmcdev=1 -bootpart=1:1 +bootpart=1:2 bootdir=/boot boot_targets=mmc1 mmc0 bootmeths=script extlinux efi pxe diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c index 0da641834d4..33452d2ad5b 100644 --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x20 }, { 0x3d400000, 0xa1040001 }, - { 0x3d400064, 0x610040 }, + { 0x3d400064, 0x300040 }, { 0x3d4000d0, 0xc00200c5 }, { 0x3d4000d4, 0x1000b }, { 0x3d4000dc, 0x1d700004 }, - { 0x3d4000e0, 0x180000 }, + { 0x3d4000e0, 0x580000 }, { 0x3d4000e4, 0x90000 }, - { 0x3d4000f0, 0x0 }, + { 0x3d4000f0, 0x2 }, { 0x3d4000f4, 0xee5 }, - { 0x3d400100, 0xc101b0e }, + { 0x3d400100, 0xc100d0e }, { 0x3d400104, 0x30314 }, { 0x3d400108, 0x4060509 }, { 0x3d40010c, 0x2006 }, @@ -67,10 +67,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400498, 0x7ff }, { 0x3d40049c, 0xe00 }, { 0x3d4004a0, 0x7ff }, - { 0x3d402064, 0x28001b }, + { 0x3d402064, 0x14001b }, { 0x3d4020dc, 0x12200004 }, - { 0x3d4020e0, 0x0 }, - { 0x3d402100, 0x7090b07 }, + { 0x3d4020e0, 0x400000 }, + { 0x3d402100, 0x7090507 }, { 0x3d402104, 0x20209 }, { 0x3d402108, 0x3030407 }, { 0x3d40210c, 0x2006 }, @@ -680,12 +680,13 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x31f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1d70 }, { 0x54030, 0x4 }, - { 0x54031, 0x18 }, + { 0x54031, 0x58 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -700,11 +701,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x21f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1220 }, { 0x54030, 0x4 }, + { 0x54031, 0x40 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -886,11 +889,11 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, + { 0x2000b, 0x1c2 }, { 0x2000c, 0x64 }, { 0x2000d, 0x3e8 }, { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, + { 0x12000b, 0xbb }, { 0x12000c, 0x26 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c index f845395ad97..ca14a474429 100644 --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x20 }, { 0x3d400000, 0xa1040001 }, - { 0x3d400064, 0x610068 }, + { 0x3d400064, 0x300068 }, { 0x3d4000d0, 0xc00200c5 }, { 0x3d4000d4, 0x1000b }, { 0x3d4000dc, 0x1d700004 }, - { 0x3d4000e0, 0x180000 }, + { 0x3d4000e0, 0x580000 }, { 0x3d4000e4, 0x90000 }, - { 0x3d4000f0, 0x0 }, + { 0x3d4000f0, 0x2 }, { 0x3d4000f4, 0xee5 }, - { 0x3d400100, 0xc101b0e }, + { 0x3d400100, 0xc100d0e }, { 0x3d400104, 0x30314 }, { 0x3d400108, 0x4060509 }, { 0x3d40010c, 0x2006 }, @@ -700,11 +700,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x21f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1220 }, { 0x54030, 0x4 }, + { 0x54031, 0x40 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -886,11 +888,11 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, + { 0x2000b, 0x1c2 }, { 0x2000c, 0x64 }, { 0x2000d, 0x3e8 }, { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, + { 0x12000b, 0xbb }, { 0x12000c, 0x26 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index ebd45f9053f..4f4f537fee5 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -76,14 +76,25 @@ static bool dh_stm32_mac_is_in_ks8851(void) { - ofnode node; + struct udevice *udev; u32 reg, cider, ccr; + char path[256]; + ofnode node; + int ret; node = ofnode_path("ethernet1"); if (!ofnode_valid(node)) return false; - if (ofnode_device_is_compatible(node, "micrel,ks8851-mll")) + ret = ofnode_get_path(node, path, sizeof(path)); + if (ret) + return false; + + ret = uclass_get_device_by_of_path(UCLASS_ETH, path, &udev); + if (ret) + return false; + + if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll")) return false; /* diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index d4192e5ab52..3344653ba2d 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -63,14 +63,14 @@ static int do_esbc_validate(struct cmd_tbl *cmdtp, int flag, int argc, } /***************************************************/ -static char esbc_validate_help_text[] = +U_BOOT_LONGHELP(esbc_validate, "esbc_validate hdr_addr <hash_val> - Validates signature using\n" " RSA verification\n" " $hdr_addr Address of header of the image\n" " to be validated.\n" " $hash_val -Optional\n" " It provides Hash of public/srk key to be\n" - " used to verify signature.\n"; + " used to verify signature.\n"); U_BOOT_CMD( esbc_validate, 3, 0, do_esbc_validate, diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index f10d310a46d..e9cdede6214 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -118,13 +118,29 @@ static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) return dm_i2c_write(dev, reg, &val, 1); } -static int power_init_board(void) +static int power_init_board(struct udevice *gsc) { const char *model = eeprom_get_model(); struct udevice *bus; struct udevice *dev; int ret; + /* Enable GSC voltage supervisor for new board models */ + if ((!strncmp(model, "GW7100", 6) && model[10] > 'D') || + (!strncmp(model, "GW7101", 6) && model[10] > 'D') || + (!strncmp(model, "GW7200", 6) && model[10] > 'E') || + (!strncmp(model, "GW7201", 6) && model[10] > 'E') || + (!strncmp(model, "GW7300", 6) && model[10] > 'E') || + (!strncmp(model, "GW7301", 6) && model[10] > 'E') || + (!strncmp(model, "GW740", 5) && model[7] > 'B')) { + u8 ver; + + if (!dm_i2c_read(gsc, 14, &ver, 1) && ver > 62) { + printf("GSC : enabling voltage supervisor\n"); + dm_i2c_clrsetbits(gsc, 25, 0, BIT(1)); + } + } + if ((!strncmp(model, "GW71", 4)) || (!strncmp(model, "GW72", 4)) || (!strncmp(model, "GW73", 4)) || @@ -286,6 +302,7 @@ void board_init_f(ulong dummy) mdelay(10); } pinctrl_select_state(bus, "default"); + mdelay(10); } } /* Wait indefiniately until the GSC probes */ @@ -297,7 +314,7 @@ void board_init_f(ulong dummy) dram_sz = venice_eeprom_init(0); /* PMIC */ - power_init_board(); + power_init_board(dev); /* DDR initialization */ spl_dram_init(dram_sz); diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 5b105d7659e..d4c22121497 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -45,22 +45,6 @@ int board_fit_config_name_match(const char *path) return -1; } -static int __maybe_unused setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - -#ifndef CONFIG_IMX8MP - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); -#else - /* Enable RGMII TX clk output */ - setbits_le32(&gpr->gpr[1], BIT(22)); -#endif - - return 0; -} - #if (IS_ENABLED(CONFIG_NET)) int board_phy_config(struct phy_device *phydev) { @@ -75,6 +59,9 @@ int board_phy_config(struct phy_device *phydev) val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */ phy_write(phydev, MDIO_DEVAD_NONE, 24, val); break; + case 0xd565a401: /* MaxLinear GPY111 */ + puts("GPY111 "); + break; } if (phydev->drv->config) @@ -88,9 +75,6 @@ int board_init(void) { venice_eeprom_init(1); - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - return 0; } diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 53c3435c92f..bd8ce633772 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -28,44 +28,38 @@ static int veyron_init(void) int ret; ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) { - debug("Cannot set regulator name\n"); - return ret; - } + if (ret) + return log_msg_ret("vdd", ret); /* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000); if (ret) - return ret; + return log_msg_ret("s12", ret); udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ ret = regulator_set_value(dev, 1400000); if (ret) - return ret; + return log_msg_ret("s14", ret); udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ ret = rockchip_get_clk(&clk.dev); if (ret) - return ret; + return log_msg_ret("clk", ret); clk.id = PLL_APLL; ret = clk_set_rate(&clk, 1800000000); if (IS_ERR_VALUE(ret)) - return ret; + return log_msg_ret("s18", ret); ret = regulator_get_by_platname("vcc33_sd", &dev); - if (ret) { - debug("Cannot get regulator name\n"); - return ret; - } + if (ret) + return log_msg_ret("vcc", ret); ret = regulator_set_value(dev, 3300000); if (ret) - return ret; + return log_msg_ret("s33", ret); ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulators\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("boo", ret); return 0; } @@ -80,7 +74,7 @@ int board_early_init_r(void) if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { ret = veyron_init(); if (ret) - return ret; + return log_msg_ret("vey", ret); } #endif /* diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c index 7851361c48c..07514778753 100644 --- a/board/kontron/sl28/cmds.c +++ b/board/kontron/sl28/cmds.c @@ -172,8 +172,8 @@ out: return CMD_RET_FAILURE; } -static char sl28_help_text[] = - "nvm [<hex>] - display/set the 16 non-volatile bits\n"; +U_BOOT_LONGHELP(sl28, + "nvm [<hex>] - display/set the 16 non-volatile bits\n"); U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text, U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm)); diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS index 22f3b97d8b1..d092b5a8111 100644 --- a/board/microchip/mpfs_icicle/MAINTAINERS +++ b/board/microchip/mpfs_icicle/MAINTAINERS @@ -1,5 +1,5 @@ Microchip MPFS icicle -M: Padmarao Begari <padmarao.begari@microchip.com> +M: Conor Dooley <conor.dooley@microchip.com> M: Cyril Jean <cyril.jean@microchip.com> S: Maintained F: board/microchip/mpfs_icicle/ diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS index 219c8715bf1..ed8800a2663 100644 --- a/board/ti/am335x/MAINTAINERS +++ b/board/ti/am335x/MAINTAINERS @@ -3,6 +3,5 @@ M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am335x/ F: include/configs/am335x_evm.h -F: configs/am335x_boneblack_vboot_defconfig F: configs/am335x_evm_defconfig F: configs/am335x_evm_spiboot_defconfig diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index 9a8812d4ee5..8ad805a613c 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -39,3 +39,8 @@ usbboot=setenv boot usb; run get_kern_usb; run get_fdt_usb; run run_kern; + +#if CONFIG_TI_ICSSG_PRUETH +storage_interface=mmc +fw_dev_part=1:2 +#endif diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 30a81376ac4..0b43407b9e9 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -701,11 +701,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) #define MAX_RAND_SIZE 8 int ft_board_setup(void *blob, struct bd_info *bd) { - size_t n = MAX_RAND_SIZE; - struct udevice *dev; - u8 buf[MAX_RAND_SIZE]; - int nodeoffset, ret; - static const struct node_info nodes[] = { { "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, }, }; @@ -713,41 +708,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS) && IS_ENABLED(CONFIG_NAND_ZYNQ)) fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { - debug("No RNG device\n"); - return 0; - } - - if (dm_rng_read(dev, buf, n)) { - debug("Reading RNG failed\n"); - return 0; - } - - if (!blob) { - debug("No FDT memory address configured. Please configure\n" - "the FDT address via \"fdt addr <address>\" command.\n" - "Aborting!\n"); - return 0; - } - - ret = fdt_check_header(blob); - if (ret < 0) { - debug("fdt_chosen: %s\n", fdt_strerror(ret)); - return ret; - } - - nodeoffset = fdt_find_or_add_subnode(blob, 0, "chosen"); - if (nodeoffset < 0) { - debug("Reading chosen node failed\n"); - return nodeoffset; - } - - ret = fdt_setprop(blob, nodeoffset, "kaslr-seed", buf, sizeof(buf)); - if (ret < 0) { - debug("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret)); - return ret; - } - return 0; } #endif diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c index 4d52084846b..e8b669f0fd4 100644 --- a/board/xilinx/versal-net/cmds.c +++ b/board/xilinx/versal-net/cmds.c @@ -71,10 +71,9 @@ static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, return cmd_process_error(cmdtp, ret); } -static char versalnet_help_text[] = +U_BOOT_LONGHELP(versalnet, "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n" -; + "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text, U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, diff --git a/boot/Kconfig b/boot/Kconfig index 6f3096c15a6..11175fb7bb2 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -85,7 +85,7 @@ config FIT_SIGNATURE using a hash signed and verified using RSA. If CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive hashing is available using hardware, then the RSA library will use - it. See doc/uImage.FIT/signature.txt for more details. + it. See doc/usage/fit/signature.rst for more details. WARNING: When relying on signed FIT images with a required signature check the legacy image format is disabled by default, so that @@ -223,8 +223,8 @@ config SPL_LOAD_FIT 1. "loadables" images, other than FDTs, which do not have a "load" property will not be loaded. This limitation also applies to FPGA images with the correct "compatible" string. - 2. For FPGA images, the supported "compatible" list is in the - doc/uImage.FIT/source_file_format.txt. + 2. For FPGA images, the supported "compatible" list may be found in + https://fitspec.osfw.foundation/. 3. FDTs are only loaded for images with an "os" property of "u-boot". "linux" images are also supported with Falcon boot mode. @@ -423,7 +423,7 @@ config SPL_BOOTSTD depends on SPL && SPL_DM && SPL_OF_CONTROL && SPL_BLK default y if VPL help - This enables standard boot in SPL. This is neeeded so that VBE + This enables standard boot in SPL. This is needed so that VBE (Verified Boot for Embedded) can be used, since it depends on standard boot. It is enabled by default since the main purpose of VPL is to handle the firmware part of VBE. @@ -433,7 +433,7 @@ config VPL_BOOTSTD depends on VPL && VPL_DM && VPL_OF_CONTROL && VPL_BLK default y help - This enables standard boot in SPL. This is neeeded so that VBE + This enables standard boot in SPL. This is needed so that VBE (Verified Boot for Embedded) can be used, since it depends on standard boot. It is enabled by default since the main purpose of VPL is to handle the firmware part of VBE. @@ -449,7 +449,7 @@ config BOOTSTD_FULL - bootdev, bootmeth commands - extra features in the bootflow command - support for selecting the ordering of bootmeths ("bootmeth order") - - support for selecting the ordering of bootdevs using the devicetree + - support for selecting the ordering of bootdevs using the Device Tree as well as the "boot_targets" environment variable config BOOTSTD_DEFAULTS @@ -481,7 +481,7 @@ config BOOTSTD_PROG default y help Enable this to provide a board_run_command() function which can boot - a systen without using commands. If the boot fails, then U-Boot will + a system without using commands. If the boot fails, then U-Boot will panic. Note: This currently has many limitations and is not a useful booting @@ -517,7 +517,7 @@ config BOOTMETH_EXTLINUX bootdevs look for a 'extlinux/extlinux.conf' on each filesystem they scan. - The specification for this filed is here: + The specification for this file is here: https://uapi-group.org/specifications/specs/boot_loader_specification/ @@ -576,7 +576,7 @@ config BOOTMETH_VBE select EVENT help Enables support for VBE boot. This is a standard boot method which - supports selection of various firmware components, seleciton of an OS to + supports selection of various firmware components, selection of an OS to boot as well as updating these using fwupd. config BOOTMETH_DISTRO @@ -593,7 +593,7 @@ config SPL_BOOTMETH_VBE default y if VPL help Enables support for VBE boot. This is a standard boot method which - supports selection of various firmware components, seleciton of an OS to + supports selection of various firmware components, selection of an OS to boot as well as updating these using fwupd. config VPL_BOOTMETH_VBE @@ -603,7 +603,7 @@ config VPL_BOOTMETH_VBE default y help Enables support for VBE boot. This is a standard boot method which - supports selection of various firmware components, seleciton of an OS to + supports selection of various firmware components, selection of an OS to boot as well as updating these using fwupd. if BOOTMETH_VBE @@ -734,6 +734,10 @@ config LEGACY_IMAGE_FORMAT config MEASURED_BOOT bool "Measure boot images and configuration when booting without EFI" depends on HASH && TPM_V2 + select SHA1 + select SHA256 + select SHA384 + select SHA512 help This option enables measurement of the boot process when booting without UEFI . Measurement involves creating cryptographic hashes @@ -748,7 +752,7 @@ if MEASURED_BOOT bool "Measure the devicetree image" default y if MEASURED_BOOT help - On some platforms, the devicetree is not static as it may contain + On some platforms, the Device Tree is not static as it may contain random MAC addresses or other such data that changes each boot. Therefore, it should not be measured into the TPM. In that case, disable the measurement here. @@ -1303,7 +1307,7 @@ config AUTOBOOT_PROMPT Note that this define is used as the (only) argument to a printf() call, so it may contain '%' format specifications, - provided that it also includes, sepearated by commas exactly + provided that it also includes, separated by commas exactly like in a printf statement, the required arguments. It is the responsibility of the user to select only such arguments that are valid in the given context. @@ -1402,7 +1406,7 @@ config AUTOBOOT_STOP_STR_SHA256 help This option adds the feature to only stop the autobooting, and therefore boot into the U-Boot prompt, when the input - string / password matches a values that is encypted via + string / password matches a values that is encrypted via a SHA256 hash and saved in the environment variable "bootstopkeysha256". If the value in that variable includes a ":", the portion prior to the ":" will be treated diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index 143ef841332..9d0dc352f97 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD #include <bootflow.h> +#include <bootmeth.h> #include <bootstd.h> #include <cli.h> #include <dm.h> @@ -76,6 +77,7 @@ int bootflow_menu_new(struct expo **expp) last_bootdev = NULL; for (ret = bootflow_first_glob(&bflow), i = 0; !ret && i < 36; ret = bootflow_next_glob(&bflow), i++) { + struct bootmeth_uc_plat *ucp; char str[2], *label, *key; uint preview_id; bool add_gap; @@ -83,6 +85,11 @@ int bootflow_menu_new(struct expo **expp) if (bflow->state != BOOTFLOWST_READY) continue; + /* No media to show for BOOTMETHF_GLOBAL bootmeths */ + ucp = dev_get_uclass_plat(bflow->method); + if (ucp->flags & BOOTMETHF_GLOBAL) + continue; + *str = i < 10 ? '0' + i : 'A' + i - 10; str[1] = '\0'; key = strdup(str); diff --git a/boot/bootm.c b/boot/bootm.c index 6fa8edab021..376d63aafc9 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -24,6 +24,7 @@ #include <asm/io.h> #include <linux/sizes.h> #include <tpm-v2.h> +#include <tpm_tcg2.h> #if defined(CONFIG_CMD_USB) #include <usb.h> #endif @@ -963,7 +964,7 @@ int bootm_measure(struct bootm_headers *images) goto unmap_initrd; if (IS_ENABLED(CONFIG_MEASURE_DEVICETREE)) { - ret = tcg2_measure_data(dev, &elog, 0, images->ft_len, + ret = tcg2_measure_data(dev, &elog, 1, images->ft_len, (u8 *)images->ft_addr, EV_TABLE_OF_DEVICES, strlen("dts") + 1, diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c index 645b8bed102..1d5fd8b193d 100644 --- a/boot/bootmeth_cros.c +++ b/boot/bootmeth_cros.c @@ -147,7 +147,7 @@ static int scan_part(struct udevice *blk, int partnum, { struct blk_desc *desc = dev_get_uclass_plat(blk); struct vb2_keyblock *hdr; - struct uuid type; + efi_guid_t type; ulong num_blks; int ret; @@ -160,7 +160,7 @@ static int scan_part(struct udevice *blk, int partnum, /* Check for kernel partition type */ log_debug("part %x: type=%s\n", partnum, info->type_guid); - if (uuid_str_to_bin(info->type_guid, (u8 *)&type, UUID_STR_FORMAT_GUID)) + if (uuid_str_to_bin(info->type_guid, type.b, UUID_STR_FORMAT_GUID)) return log_msg_ret("typ", -EINVAL); if (memcmp(&cros_kern_type, &type, sizeof(type))) diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 874ca4d6f5a..2392027d40b 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -6,12 +6,15 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ +#include <dm.h> #include <abuf.h> #include <env.h> #include <log.h> #include <mapmem.h> #include <net.h> +#include <rng.h> #include <stdio_dev.h> +#include <dm/device_compat.h> #include <dm/ofnode.h> #include <linux/ctype.h> #include <linux/types.h> @@ -273,6 +276,47 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end) return 0; } +int fdt_kaslrseed(void *fdt, bool overwrite) +{ + int len, err, nodeoffset; + struct udevice *dev; + const u64 *orig; + u64 data = 0; + + err = fdt_check_header(fdt); + if (err < 0) + return err; + + /* find or create "/chosen" node. */ + nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen"); + if (nodeoffset < 0) + return nodeoffset; + + /* return without error if we are not overwriting and existing non-zero node */ + orig = fdt_getprop(fdt, nodeoffset, "kaslr-seed", &len); + if (orig && len == sizeof(*orig)) + data = fdt64_to_cpu(*orig); + if (data && !overwrite) { + debug("not overwriting existing kaslr-seed\n"); + return 0; + } + err = uclass_get_device(UCLASS_RNG, 0, &dev); + if (err) { + printf("No RNG device\n"); + return err; + } + err = dm_rng_read(dev, &data, sizeof(data)); + if (err) { + dev_err(dev, "dm_rng_read failed: %d\n", err); + return err; + } + err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", &data, sizeof(data)); + if (err < 0) + printf("WARNING: could not set kaslr-seed %s.\n", fdt_strerror(err)); + + return err; +} + /** * board_fdt_chosen_bootargs - boards may override this function to use * alternative kernel command line arguments @@ -300,6 +344,15 @@ int fdt_chosen(void *fdt) if (nodeoffset < 0) return nodeoffset; + /* if DM_RNG enabled automatically inject kaslr-seed node unless: + * CONFIG_MEASURED_BOOT enabled: as dt modifications break measured boot + * CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT enabled: as that implementation does not use dm yet + */ + if (IS_ENABLED(CONFIG_DM_RNG) && + !IS_ENABLED(CONFIG_MEASURED_BOOT) && + !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)) + fdt_kaslrseed(fdt, false); + if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) { err = fdt_setprop(fdt, nodeoffset, "rng-seed", abuf_data(&buf), abuf_size(&buf)); diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index 4b22bb6f525..53d6cf700b2 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -4,6 +4,8 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ +#define LOG_CATEGORY LOGC_BOOT + #include <command.h> #include <dm.h> #include <env.h> @@ -323,10 +325,6 @@ static void label_boot_kaslrseed(void) #if CONFIG_IS_ENABLED(DM_RNG) ulong fdt_addr; struct fdt_header *working_fdt; - size_t n = 0x8; - struct udevice *dev; - u64 *buf; - int nodeoffset; int err; /* Get the main fdt and map it */ @@ -342,35 +340,7 @@ static void label_boot_kaslrseed(void) if (err <= 0) return; - if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { - printf("No RNG device\n"); - return; - } - - nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen"); - if (nodeoffset < 0) { - printf("Reading chosen node failed\n"); - return; - } - - buf = malloc(n); - if (!buf) { - printf("Out of memory\n"); - return; - } - - if (dm_rng_read(dev, buf, n)) { - printf("Reading RNG failed\n"); - goto err; - } - - err = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf)); - if (err < 0) { - printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(err)); - goto err; - } -err: - free(buf); + fdt_kaslrseed(working_fdt, true); #endif return; } @@ -762,17 +732,22 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) /* Try bootm for legacy and FIT format image */ if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID && - IS_ENABLED(CONFIG_CMD_BOOTM)) + IS_ENABLED(CONFIG_CMD_BOOTM)) { + log_debug("using bootm\n"); do_bootm(ctx->cmdtp, 0, bootm_argc, bootm_argv); /* Try booting an AArch64 Linux kernel image */ - else if (IS_ENABLED(CONFIG_CMD_BOOTI)) + } else if (IS_ENABLED(CONFIG_CMD_BOOTI)) { + log_debug("using booti\n"); do_booti(ctx->cmdtp, 0, bootm_argc, bootm_argv); /* Try booting a Image */ - else if (IS_ENABLED(CONFIG_CMD_BOOTZ)) + } else if (IS_ENABLED(CONFIG_CMD_BOOTZ)) { + log_debug("using bootz\n"); do_bootz(ctx->cmdtp, 0, bootm_argc, bootm_argv); /* Try booting an x86_64 Linux kernel image */ - else if (IS_ENABLED(CONFIG_CMD_ZBOOT)) + } else if (IS_ENABLED(CONFIG_CMD_ZBOOT)) { + log_debug("using zboot\n"); do_zboot_parent(ctx->cmdtp, 0, zboot_argc, zboot_argv, NULL); + } unmap_sysmem(buf); diff --git a/cmd/Kconfig b/cmd/Kconfig index ff0f5941ecc..40ac5a8dbac 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -308,7 +308,7 @@ config CMD_BOOTMETH depends on BOOTSTD default y if BOOTSTD_FULL help - Support listing available bootmethds (methods used to boot an + Support listing available bootmeths (methods used to boot an Operating System), as well as selecting the order that the bootmeths are used. @@ -622,7 +622,7 @@ config CMD_ZBOOT Consider using FIT in preference to this since it supports directly booting both 32- and 64-bit kernels, as well as secure boot. - Documentation is available in doc/uImage.FIT/x86-fit-boot.txt + Documentation is available in doc/usage/fit/x86-fit-boot.rst. endmenu diff --git a/cmd/adc.c b/cmd/adc.c index f87f9785a11..4d3b5b61f6f 100644 --- a/cmd/adc.c +++ b/cmd/adc.c @@ -152,11 +152,11 @@ static int do_adc_scan(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } -static char adc_help_text[] = +U_BOOT_LONGHELP(adc, "list - list ADC devices\n" "adc info <name> - Get ADC device info\n" "adc single <name> <channel> [varname] - Get Single data of ADC device channel\n" - "adc scan <name> [channel mask] - Scan all [or masked] ADC channels"; + "adc scan <name> [channel mask] - Scan all [or masked] ADC channels\n"); U_BOOT_CMD_WITH_SUBCMDS(adc, "ADC sub-system", adc_help_text, U_BOOT_SUBCMD_MKENT(list, 1, 1, do_adc_list), diff --git a/cmd/arm/exception.c b/cmd/arm/exception.c index 98a9795b68c..8857f121604 100644 --- a/cmd/arm/exception.c +++ b/cmd/arm/exception.c @@ -49,12 +49,11 @@ static struct cmd_tbl cmd_sub[] = { "", ""), }; -static char exception_help_text[] = +U_BOOT_LONGHELP(exception, "<ex>\n" " The following exceptions are available:\n" " breakpoint - prefetch abort\n" " unaligned - data abort\n" - " undefined - undefined instruction\n" - ; + " undefined - undefined instruction\n"); #include <exception.h> diff --git a/cmd/arm/exception64.c b/cmd/arm/exception64.c index 73d6c20ccac..4c5b953168c 100644 --- a/cmd/arm/exception64.c +++ b/cmd/arm/exception64.c @@ -77,12 +77,11 @@ static struct cmd_tbl cmd_sub[] = { "", ""), }; -static char exception_help_text[] = +U_BOOT_LONGHELP(exception, "<ex>\n" " The following exceptions are available:\n" " breakpoint - breakpoint instruction exception\n" " unaligned - unaligned LDAR data abort\n" - " undefined - undefined instruction exception\n" - ; + " undefined - undefined instruction exception\n"); #include <exception.h> diff --git a/cmd/blob.c b/cmd/blob.c index a3c1dc49224..b1c72e3f440 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -99,7 +99,7 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc, } /***************************************************/ -static char blob_help_text[] = +U_BOOT_LONGHELP(blob, "enc src dst len km - Encapsulate and create blob of data\n" " $len bytes long at address $src and\n" " store the result at address $dst.\n" @@ -115,7 +115,7 @@ static char blob_help_text[] = " modifier is stored.\n" " The modifier is required for generation\n" " /use as key for cryptographic operation.\n" - " Key modifier should be 16 byte long.\n"; + " Key modifier should be 16 byte long.\n"); U_BOOT_CMD( blob, 6, 1, do_blob, diff --git a/cmd/cli.c b/cmd/cli.c index be3bf7dfe20..e0ddd0a43d0 100644 --- a/cmd/cli.c +++ b/cmd/cli.c @@ -118,16 +118,11 @@ static int do_cli(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; } -#if CONFIG_IS_ENABLED(SYS_LONGHELP) -static char cli_help_text[] = +U_BOOT_LONGHELP(cli, "get - print current cli\n" - "set - set the current cli, possible value are: old, modern" - ; -#endif + "set - set the current cli, possible value are: old, modern\n"); U_BOOT_CMD(cli, 3, 1, do_cli, "cli", -#if CONFIG_IS_ENABLED(SYS_LONGHELP) cli_help_text -#endif ); diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c index 3c8be576ac7..9c048d69a13 100644 --- a/cmd/fwu_mdata.c +++ b/cmd/fwu_mdata.c @@ -22,6 +22,7 @@ static void print_mdata(struct fwu_data *data) printf("\tFWU Metadata\n"); printf("crc32: %#x\n", data->crc32); printf("version: %#x\n", data->version); + printf("size: %#x\n", data->metadata_size); printf("active_index: %#x\n", data->active_index); printf("previous_active_index: %#x\n", data->previous_active_index); diff --git a/cmd/gpt.c b/cmd/gpt.c index 36b112d5978..aeabd19dd76 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -682,7 +682,8 @@ static int gpt_verify(struct blk_desc *blk_dev_desc, const char *str_part) free(str_disk_guid); free(partitions); out: - free(gpt_pte); + if (!ret) + free(gpt_pte); return ret; } diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c index e0d3c7fe748..2ad983a11f9 100644 --- a/cmd/kaslrseed.c +++ b/cmd/kaslrseed.c @@ -15,60 +15,25 @@ static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - size_t n = 0x8; - struct udevice *dev; - u64 *buf; - int nodeoffset; - int ret = CMD_RET_SUCCESS; + int err = CMD_RET_SUCCESS; - if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { - printf("No RNG device\n"); - return CMD_RET_FAILURE; - } - - buf = malloc(n); - if (!buf) { - printf("Out of memory\n"); - return CMD_RET_FAILURE; - } - - if (dm_rng_read(dev, buf, n)) { - printf("Reading RNG failed\n"); - return CMD_RET_FAILURE; - } + printf("Notice: a /chosen/kaslr-seed is automatically added to the device-tree when booted via booti/bootm/bootz therefore using this command is likely no longer needed\n"); if (!working_fdt) { printf("No FDT memory address configured. Please configure\n" "the FDT address via \"fdt addr <address>\" command.\n" "Aborting!\n"); - return CMD_RET_FAILURE; - } - - ret = fdt_check_header(working_fdt); - if (ret < 0) { - printf("fdt_chosen: %s\n", fdt_strerror(ret)); - return CMD_RET_FAILURE; - } - - nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen"); - if (nodeoffset < 0) { - printf("Reading chosen node failed\n"); - return CMD_RET_FAILURE; + err = CMD_RET_FAILURE; + } else { + if (fdt_kaslrseed(working_fdt, true) < 0) + err = CMD_RET_FAILURE; } - ret = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf)); - if (ret < 0) { - printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret)); - return CMD_RET_FAILURE; - } - - free(buf); - - return ret; + return cmd_process_error(cmdtp, err); } U_BOOT_LONGHELP(kaslrseed, - "[n]\n" + "\n" " - append random bytes to chosen kaslr-seed node\n"); U_BOOT_CMD( diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c index 14ad6c440a5..2b58b1c449c 100644 --- a/cmd/riscv/exception.c +++ b/cmd/riscv/exception.c @@ -68,14 +68,13 @@ static struct cmd_tbl cmd_sub[] = { "", ""), }; -static char exception_help_text[] = +U_BOOT_LONGHELP(exception, "<ex>\n" " The following exceptions are available:\n" " compressed - compressed instruction\n" " ebreak - breakpoint\n" " ialign16 - 16 bit aligned instruction\n" " undefined - illegal instruction\n" - " unaligned - load address misaligned\n" - ; + " unaligned - load address misaligned\n"); #include <exception.h> diff --git a/cmd/scmi.c b/cmd/scmi.c index 664062c4eff..cfbca63e164 100644 --- a/cmd/scmi.c +++ b/cmd/scmi.c @@ -369,7 +369,7 @@ static int do_scmi(struct cmd_tbl *cmdtp, int flag, return cp->cmd(cmdtp, flag, argc, argv); } -static char scmi_help_text[] = +U_BOOT_LONGHELP(scmi, " - SCMI utility\n" " info - get the info of SCMI services\n" " perm_dev <agent-id in hex> <device-id in hex> <flags in hex>\n" @@ -377,8 +377,7 @@ static char scmi_help_text[] = " perm_proto <agent-id in hex> <device-id in hex> <protocol-id in hex> <flags in hex>\n" " - set protocol permission to device\n" " reset <agent-id in hex> <flags in hex>\n" - " - reset platform resource settings\n" - ""; + " - reset platform resource settings\n"); U_BOOT_CMD(scmi, CONFIG_SYS_MAXARGS, 0, do_scmi, "SCMI utility", scmi_help_text); diff --git a/cmd/sound.c b/cmd/sound.c index 08bf74112f1..8f67cbd96e1 100644 --- a/cmd/sound.c +++ b/cmd/sound.c @@ -98,7 +98,7 @@ U_BOOT_CMD( sound, INT_MAX, 1, do_sound, "sound sub-system", "init - initialise the sound driver\n" - "sound play [[[-q|-s] len [freq]] ...] - play sounds\n" + "sound play [len [freq [len [freq ...]]]] - play sounds\n" " len - duration in ms\n" " freq - frequency in Hz\n" ); diff --git a/cmd/ubi.c b/cmd/ubi.c index 8c1b5df0572..92998af2b02 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -248,7 +248,7 @@ static int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id, static struct ubi_volume *ubi_find_volume(char *volume) { - struct ubi_volume *vol = NULL; + struct ubi_volume *vol; int i; for (i = 0; i < ubi->vtbl_slots; i++) { @@ -355,13 +355,18 @@ static int ubi_rename_vol(char *oldname, char *newname) static int ubi_volume_continue_write(char *volume, void *buf, size_t size) { - int err = 1; + int err; struct ubi_volume *vol; vol = ubi_find_volume(volume); if (vol == NULL) return ENODEV; + if (!vol->updating) { + printf("UBI volume update was not initiated\n"); + return EINVAL; + } + err = ubi_more_update_data(ubi, vol, buf, size); if (err < 0) { printf("Couldnt or partially wrote data\n"); @@ -391,8 +396,8 @@ static int ubi_volume_continue_write(char *volume, void *buf, size_t size) int ubi_volume_begin_write(char *volume, void *buf, size_t size, size_t full_size) { - int err = 1; - int rsvd_bytes = 0; + int err; + int rsvd_bytes; struct ubi_volume *vol; vol = ubi_find_volume(volume); @@ -411,6 +416,10 @@ int ubi_volume_begin_write(char *volume, void *buf, size_t size, return -err; } + /* The volume is just wiped out */ + if (!full_size) + return 0; + return ubi_volume_continue_write(volume, buf, size); } @@ -573,7 +582,7 @@ static int ubi_detach(void) int ubi_part(char *part_name, const char *vid_header_offset) { struct mtd_info *mtd; - int err = 0; + int err; if (ubi && ubi->mtd && !strcmp(ubi->mtd->name, part_name)) { printf("UBI partition '%s' already selected\n", part_name); @@ -604,7 +613,7 @@ int ubi_part(char *part_name, const char *vid_header_offset) static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int64_t size = 0; + int64_t size; ulong addr = 0; bool skipcheck = false; diff --git a/cmd/unlz4.c b/cmd/unlz4.c index fc5200117ad..2eadc753e6c 100644 --- a/cmd/unlz4.c +++ b/cmd/unlz4.c @@ -6,6 +6,7 @@ #include <command.h> #include <env.h> +#include <mapmem.h> #include <vsprintf.h> #include <u-boot/lz4.h> @@ -26,7 +27,8 @@ static int do_unlz4(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; } - ret = ulz4fn((void *)src, src_len, (void *)dst, &dst_len); + ret = ulz4fn(map_sysmem(src, 0), src_len, map_sysmem(dst, dst_len), + &dst_len); if (ret) { printf("Uncompressed err :%d\n", ret); return 1; diff --git a/cmd/usb.c b/cmd/usb.c index 3a3764a5b86..225d9291765 100644 --- a/cmd/usb.c +++ b/cmd/usb.c @@ -25,9 +25,6 @@ #ifdef CONFIG_USB_STORAGE static int usb_stor_curr_dev = -1; /* current device */ #endif -#if defined(CONFIG_USB_HOST_ETHER) && !defined(CONFIG_DM_ETH) -static int __maybe_unused usb_ether_curr_dev = -1; /* current ethernet device */ -#endif /* some display routines (info command) */ static char *usb_get_class_desc(unsigned char dclass) diff --git a/cmd/x86/exception.c b/cmd/x86/exception.c index 14b6bd6f493..02735494a3c 100644 --- a/cmd/x86/exception.c +++ b/cmd/x86/exception.c @@ -19,10 +19,9 @@ static struct cmd_tbl cmd_sub[] = { "", ""), }; -static char exception_help_text[] = +U_BOOT_LONGHELP(exception, "<ex>\n" " The following exceptions are available:\n" - " undefined - undefined instruction\n" - ; + " undefined - undefined instruction\n"); #include <exception.h> diff --git a/cmd/x86/zboot.c b/cmd/x86/zboot.c index addf28cb4aa..94e602b8a5b 100644 --- a/cmd/x86/zboot.c +++ b/cmd/x86/zboot.c @@ -5,6 +5,8 @@ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> */ +#define LOG_CATEGORY LOGC_BOOT + #include <command.h> #include <mapmem.h> #include <vsprintf.h> @@ -14,8 +16,14 @@ static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { ulong bzimage_addr = 0, bzimage_size, initrd_addr, initrd_size; - ulong base_addr; const char *s, *cmdline; + ulong base_addr; + int i; + + log_debug("argc %d:", argc); + for (i = 0; i < argc; i++) + log_debug(" %s", argv[i]); + log_debug("\n"); /* argv[1] holds the address of the bzImage */ s = cmd_arg1(argc, argv) ? : env_get("fileaddr"); @@ -114,17 +122,18 @@ U_BOOT_SUBCMDS(zboot, int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], int state_mask) { - int ret; + int ret = 0; - if (flag & ZBOOT_STATE_START) + log_debug("state_mask %x\n", state_mask); + if (state_mask & ZBOOT_STATE_START) ret = do_zboot_start(cmdtp, flag, argc, argv); - if (!ret && (flag & ZBOOT_STATE_LOAD)) + if (!ret && (state_mask & ZBOOT_STATE_LOAD)) ret = do_zboot_load(cmdtp, flag, argc, argv); - if (!ret && (flag & ZBOOT_STATE_SETUP)) + if (!ret && (state_mask & ZBOOT_STATE_SETUP)) ret = do_zboot_setup(cmdtp, flag, argc, argv); - if (!ret && (flag & ZBOOT_STATE_INFO)) + if (!ret && (state_mask & ZBOOT_STATE_INFO)) ret = do_zboot_info(cmdtp, flag, argc, argv); - if (!ret && (flag & ZBOOT_STATE_GO)) + if (!ret && (state_mask & ZBOOT_STATE_GO)) ret = do_zboot_go(cmdtp, flag, argc, argv); if (ret) return ret; diff --git a/common/Kconfig b/common/Kconfig index 5e3070e9253..4bb9f08977a 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -628,7 +628,7 @@ if CYCLIC config CYCLIC_MAX_CPU_TIME_US int "Sets the max allowed time for a cyclic function in us" - default 1000 + default 5000 help The max allowed time for a cyclic function in us. If a functions takes longer than this duration this function will get unregistered diff --git a/common/board_r.c b/common/board_r.c index c823cd262f1..d4ba245ac69 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -230,8 +230,7 @@ static int initr_dm(void) oftree_reset(); - /* Save the pre-reloc driver model and start a new one */ - gd->dm_root_f = gd->dm_root; + /* Drop the pre-reloc driver model and start a new one */ gd->dm_root = NULL; #ifdef CONFIG_TIMER gd->timer = NULL; diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index 0b1c981a105..0397b86a33b 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -203,7 +203,8 @@ static void __noreturn bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry, fdt_addr); raw_write_daif(SPSR_EXCEPTION_MASK); - dcache_disable(); + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + dcache_disable(); atf_entry(bl31_params, (void *)fdt_addr); } diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 988125be008..2a097f4464c 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -587,7 +587,7 @@ __weak void *spl_load_simple_fit_fix_load(const void *fit) static void warn_deprecated(const char *msg) { printf("DEPRECATED: %s\n", msg); - printf("\tSee doc/uImage.FIT/source_file_format.txt\n"); + printf("\tSee https://fitspec.osfw.foundation/\n"); } static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node, diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig deleted file mode 100644 index d473a1a793b..00000000000 --- a/configs/am335x_boneblack_vboot_defconfig +++ /dev/null @@ -1,94 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -# CONFIG_SPL_USE_ARCH_MEMCPY is not set -# CONFIG_SPL_USE_ARCH_MEMSET is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack" -CONFIG_AM33XX=y -CONFIG_CLOCK_SYNTHESIZER=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x280000 -CONFIG_TIMESTAMP=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_SYS_BOOTM_LEN=0x1000000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd" -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -CONFIG_SPL_MUSB_NEW=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_NET=y -CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL" -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_FALCON_BOOT_MMCSD=y -CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 -CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 -CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 -CONFIG_CMD_SPL=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -# CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_DNS2=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RETRY_COUNT=10 -CONFIG_BOOTP_SEND_HOSTNAME=y -# CONFIG_SPL_BLK is not set -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_BOOTCOUNT_BE=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_DM_I2C=y -CONFIG_MISC=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_SPL_DM_MMC is not set -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_DM_PMIC=y -# CONFIG_SPL_DM_PMIC is not set -CONFIG_PMIC_TPS65217=y -CONFIG_SPL_POWER_TPS65910=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_TIMER=y -CONFIG_OMAP_TIMER=y -CONFIG_USB=y -CONFIG_DM_USB_GADGET=y -CONFIG_SPL_DM_USB_GADGET=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_TI=y -CONFIG_USB_GADGET=y -CONFIG_SPL_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y -CONFIG_SPL_USB_ETHER=y -CONFIG_LZO=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index d243cb16e72..cabc181460a 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -13,6 +13,8 @@ CONFIG_AM335X_USB0_PERIPHERAL=y CONFIG_AM335X_USB1=y CONFIG_SPL=y CONFIG_TIMESTAMP=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_DISTRO_DEFAULTS=y @@ -119,5 +121,4 @@ CONFIG_SPL_USB_ETHER=y CONFIG_WDT=y # CONFIG_SPL_WDT is not set CONFIG_DYNAMIC_CRC_TABLE=y -CONFIG_RSA=y CONFIG_LZO=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 44c22458ab2..94c7ce9b8e8 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -126,8 +126,10 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_MULTIPLEXER=y CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_TI_DP83869=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_ICSSG_PRUETH=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_TORRENT=y @@ -143,6 +145,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_TPS65219=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_PRU=y +CONFIG_CMD_REMOTEPROC=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y @@ -150,6 +154,7 @@ CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y CONFIG_SOC_TI=y +CONFIG_TI_PRUSS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index ee79adef699..925a88e2547 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -16,7 +16,6 @@ CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -36,6 +35,7 @@ CONFIG_PCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;" @@ -68,7 +68,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y -CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0" diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index acfe3934104..b2ecfa6050c 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00200000 diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 95fdb418d82..0fba5912e0e 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00200000 diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index a9f91dd9b26..70c57aebab8 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -15,6 +15,8 @@ CONFIG_DEBUG_UART=y CONFIG_HAVE_MRC=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=630000 CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y @@ -78,5 +80,6 @@ CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_VIDEO_IVYBRIDGE_IGD=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y +# CONFIG_SHA256 is not set # CONFIG_GZIP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig index b92488587d8..86ca4f81fed 100644 --- a/configs/hmibsc_defconfig +++ b/configs/hmibsc_defconfig @@ -10,44 +10,42 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="apq8016-schneider-hmibsc" -# CONFIG_OF_UPSTREAM is not set CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_IDENT_STRING="\nSchneider Electric-HMIBSC" CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_REMAKE_ELF=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=2048 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="hmibsc => " -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_FS_GENERIC=y # CONFIG_CMD_IMI is not set +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_NVEDIT_INFO=y CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y -CONFIG_CMD_ENV_FLAGS=y -CONFIG_CMD_ENV_EXISTS=y -CONFIG_CMD_NVEDIT_INFO=y -CONFIG_ENV_WRITEABLE_LIST=y -CONFIG_ENV_ACCESS_IGNORE_FORCE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_OF_UPSTREAM is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_APQ8016=y @@ -79,10 +77,9 @@ CONFIG_USB_ULPI=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_PHYLIB=y -CONFIG_USB_ETHER_LAN75XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig index 064758c48c8..93ead4c373b 100644 --- a/configs/imx6ulz_smm_m2_defconfig +++ b/configs/imx6ulz_smm_m2_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x400000 CONFIG_MX6ULL=y CONFIG_TARGET_MX6ULZ_SMM_M2=y -CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-bsh-smm-m2" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6ulz-bsh-smm-m2" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_SERIAL=y CONFIG_SPL_BSS_START_ADDR=0x84100000 diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 0e0a548a57f..b4351a392ef 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mn-bsh-smm-s2" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-bsh-smm-s2" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_BSH_SMM_S2=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index f739569dde9..0faa3376fd3 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mn-bsh-smm-s2pro" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-bsh-smm-s2pro" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_BSH_SMM_S2PRO=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 5944c6c5304..0ad0e238767 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -15,7 +15,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk2" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_MMC=y @@ -41,6 +40,7 @@ CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_SYSTEM_SETUP=y @@ -66,6 +66,7 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +# CONFIG_SPL_FIT_IMAGE_TINY is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 7b3dae504f8..5520a4dab73 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -160,8 +160,6 @@ CONFIG_TFTP_TSIZE=y CONFIG_PROT_TCP_SACK=y CONFIG_IPV6=y CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 CONFIG_SPL_CLK_COMPOSITE_CCF=y @@ -232,7 +230,6 @@ CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PCA9450=y CONFIG_SPL_DM_PMIC_PCA9450=y -CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_PCA9450=y CONFIG_SPL_DM_REGULATOR_PCA9450=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 37d582b7750..ffaf21d4999 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_J721E=y CONFIG_K3_EARLY_CONS=y +CONFIG_K3_QOS=y CONFIG_TARGET_J721E_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0 diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index e676dbc03e4..6404b1cc303 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_J721S2=y CONFIG_K3_EARLY_CONS=y +CONFIG_K3_QOS=y CONFIG_TARGET_J721S2_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000 diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 07edb7f62db..7ace6615261 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_J784S4=y CONFIG_K3_EARLY_CONS=y +CONFIG_K3_QOS=y CONFIG_TARGET_J784S4_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000 diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index 0cb2922de44..d350ec14eb1 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -32,11 +32,11 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_CV1800B=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_CV1800B=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI=y CONFIG_CV1800B_SPIF=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CV1800B=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 1483d17d975..6d43a259989 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -11,13 +11,10 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SPL_STACK=0x800ffffc CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000 -CONFIG_DEBUG_UART_BASE=0x70006000 -CONFIG_DEBUG_UART_CLOCK=408000000 CONFIG_TEGRA124=y CONFIG_TARGET_NYAN_BIG=y CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x82408000 -CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y CONFIG_BOOTSTAGE=y @@ -76,7 +73,6 @@ CONFIG_DM_REGULATOR=y CONFIG_REGULATOR_AS3722=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y -CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SOUND=y CONFIG_I2S=y diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig index f7c35536a02..5a8db5a0876 100644 --- a/configs/octeon_nic23_defconfig +++ b/configs/octeon_nic23_defconfig @@ -25,7 +25,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_CYCLIC=y -CONFIG_CYCLIC_MAX_CPU_TIME_US=5000 CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 7b16e8ef58e..57e320af603 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_SYS_I2C_MXC_I2C1=y @@ -12,7 +13,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y -CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 80ad3b32e13..37966bfb201 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -1,16 +1,17 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y +CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_SNAPDRAGON=y CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" CONFIG_SYS_LOAD_ADDR=0xA0000000 -CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTSTD_FULL=y # CONFIG_BOOTMETH_VBE is not set CONFIG_BOOTDELAY=1 +CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y CONFIG_SYS_CBSIZE=512 @@ -34,7 +35,6 @@ CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y -CONFIG_OF_BOARD_SETUP=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCM2290=y @@ -106,5 +106,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y CONFIG_HEXDUMP=y -CONFIG_GENERATE_SMBIOS_TABLE=y CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 2bd4eeaade9..dd0582d2a0c 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -267,6 +267,7 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_ERRNO_STR=y CONFIG_GETOPT=y +CONFIG_EFI_RT_VOLATILE_STORE=y CONFIG_EFI_SECURE_BOOT=y CONFIG_TEST_FDTDEC=y CONFIG_UNIT_TEST=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 93b52f2de5c..da8c1976d7b 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -348,6 +348,7 @@ CONFIG_ECDSA_VERIFY=y CONFIG_TPM=y CONFIG_ERRNO_STR=y CONFIG_GETOPT=y +CONFIG_EFI_RT_VOLATILE_STORE=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 377081c92e0..53ef81e64d4 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -27,6 +27,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SYS_PROMPT="Versal NET> " +CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 59fdd30fd83..915f0b993ce 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SYS_PROMPT="Versal> " +CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 3d1cfe850a9..58e88b25fd6 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -54,6 +54,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index a9e65039d3e..fa912ae3bbd 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -52,6 +52,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_THOR_RESET_OFF=y diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst index 7c0713504c4..19662be6fc6 100644 --- a/doc/arch/arm64.rst +++ b/doc/arch/arm64.rst @@ -48,6 +48,55 @@ Notes 6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and aarch32 specific codes. +MMU +--- + +U-Boot uses a simple page table for MMU setup. It uses the smallest number of bits +possible for the virtual address based on the maximum memory address (see the logic +in ``get_tcr()``). If this is less than 39 bits, the MMU will use only 3 levels for +address translation. + +As with all platforms, U-Boot on ARM64 uses a 1:1 mapping of virtual to physical addresses. +In general, the memory map is expected to remain static once the MMU is enabled. + +Software pagetable walker +^^^^^^^^^^^^^^^^^^^^^^^^^ + +It is possible to debug the pagetable generated by U-Boot with the built in +``dump_pagetable()`` and ``walk_pagetable()`` functions (the former being a simple +wrapper for the latter). For example the following can be added to ``setup_all_pgtables()`` +after the first call to ``setup_pgtables()``: + +.. code-block:: c + + dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL)); + +.. kernel-doc:: arch/arm/cpu/armv8/cache_v8.c + :identifiers: __pagetable_walk pagetable_print_entry + +The pagetable walker can be used as follows: + +.. kernel-doc:: arch/arm/include/asm/armv8/mmu.h + :identifiers: pte_walker_cb_t walk_pagetable dump_pagetable + +This will result in a print like the following: + +.. code-block:: text + + Walking pagetable at 000000017df90000, va_bits: 36. Using 3 levels + [0x17df91000] | Table | | + [0x17df92000] | Table | | + [0x000001000 - 0x000200000] | Pages | Device-nGnRnE | Non-shareable + [0x000200000 - 0x040000000] | Block | Device-nGnRnE | Non-shareable + [0x040000000 - 0x080000000] | Block | Device-nGnRnE | Non-shareable + [0x080000000 - 0x140000000] | Block | Normal | Inner-shareable + [0x17df93000] | Table | | + [0x140000000 - 0x17de00000] | Block | Normal | Inner-shareable + [0x17df94000] | Table | | + [0x17de00000 - 0x17dfa0000] | Pages | Normal | Inner-shareable + +For more information, please refer to the additional function documentation in +``arch/arm/include/asm/armv8/mmu.h``. Contributors ------------ diff --git a/doc/board/beagle/am62x_beagleplay.rst b/doc/board/beagle/am62x_beagleplay.rst index cdc610264e1..01f04beb55a 100644 --- a/doc/board/beagle/am62x_beagleplay.rst +++ b/doc/board/beagle/am62x_beagleplay.rst @@ -71,11 +71,10 @@ Set the variables corresponding to this platform: Target Images ------------- -Copy the below images to an SD card and boot: +Copy these images to an SD card and boot: -* tiboot3-am62x-gp-evm.bin from R5 build as tiboot3.bin -* tispl.bin_unsigned from Cortex-A build as tispl.bin -* u-boot.img_unsigned from Cortex-A build as u-boot.img +* tiboot3.bin from Cortex-R5 build. +* tispl.bin and u-boot.img from Cortex-A build Image formats ------------- diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index a615d01474e..ce7ec5545a6 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -159,4 +159,4 @@ Further Information ------------------- Please see :doc:`../ti/am62x_sk` chapter for further AM62 SoC related documentation -and https://docs.phytec.com/phycore-am62x for vendor documentation. +and https://docs.phytec.com/projects/yocto-phycore-am62x/en/latest/ for vendor documentation. diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst index 189da179534..2b9cd32c508 100644 --- a/doc/board/phytec/phycore-am64x.rst +++ b/doc/board/phytec/phycore-am64x.rst @@ -9,7 +9,7 @@ SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family. -A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am64x>`_ +A development Kit, called `phyBOARD-Electra <https://www.phytec.com/product/phyboard-am64x>`_ is used as a carrier board reference design around the AM64x SoM. Quickstart @@ -156,4 +156,4 @@ Further Information ------------------- Please see :doc:`../ti/am64x_evm` chapter for further AM64 SoC related documentation -and https://docs.phytec.com/phycore-am64x for vendor documentation. +and https://docs.phytec.com/projects/yocto-phycore-am64x/en/latest/ for vendor documentation. diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 76375473185..67b066a07d3 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -204,6 +204,11 @@ online Build Procedure --------------- +.. note :: + + Make sure you have installed all necessary host package dependencies + before proceeding. See :ref:`build/gcc:Building with GCC`. + Depending on the specifics of your device, you will need three or more binaries to boot your SoC. @@ -388,6 +393,30 @@ wakeup and main domain and to boot to the U-Boot prompt | `tispl.bin` for HS devices or `tispl.bin_unsigned` for GP devices | `u-boot.img` for HS devices or `u-boot.img_unsigned` for GP devices +Capsules +-------- + +Most K3 boards have support for UEFI capsule update via capsule-on-disk +functionality. Check the ``CONFIG_EFI_CAPSULE_ON_DISK`` config option for +the board under question to verify. If configured, capsules for each of the +binaries above are automatically generated as part of the binary's build. +They are named `<binary>-capsule.bin`. For example, the capsule for +`u-boot.img` would be called `uboot-capsule.bin`. + +See :ref:`uefi_capsule_update_ref` for more information on U-Boot's support +for capsule update and how they are applied. + +Each board defines the capsules generated, including where those capsules +are applied. See the ``update_info`` definition for a board, typically +found at `board/ti/<board>/evm.c`. For example, `board/ti/am62x/evm.c`. +Usually, if the board has OSPI flash, the capsules will be applied there, +else the boot partition of the eMMC device. + +Once applied, the board will have U-Boot binaries in on-board non-volatile +storage. To start booting from that storage, set the bootmode pins +accordingly. Future updates can be performed by using the capsules +generated from the corresponding U-Boot builds. + FIT signature signing --------------------- diff --git a/doc/develop/bootstd.rst b/doc/develop/bootstd.rst index a07a72581e7..34631089ae0 100644 --- a/doc/develop/bootstd.rst +++ b/doc/develop/bootstd.rst @@ -39,7 +39,7 @@ Bootflow A bootflow is a file that describes how to boot a distro. Conceptually there can be different formats for that file but at present U-Boot only supports the -BootLoaderSpec_ format. which looks something like this:: +BootLoaderSpec_ format which looks something like this:: menu autoboot Welcome to Fedora-Workstation-armhfp-31-1.9. Automatic boot in # second{,s}. Press a key for options. menu title Fedora-Workstation-armhfp-31-1.9 Boot Options. @@ -52,7 +52,7 @@ BootLoaderSpec_ format. which looks something like this:: initrd /initramfs-5.3.7-301.fc31.armv7hl.img As you can see it specifies a kernel, a ramdisk (initrd) and a directory from -which to load devicetree files. The details are described in distro_bootcmd_. +which to load Device Tree files. The details are described in distro_bootcmd_. The bootflow is provided by the distro. It is not part of U-Boot. U-Boot's job is simply to interpret the file and carry out the instructions. This allows @@ -85,7 +85,7 @@ Bootmeth -------- Once the list of filesystems is provided, how does U-Boot find the bootflow -files in these filesystems. That is the job of bootmeth. Each boot method has +files in these filesystems? That is the job of bootmeth. Each boot method has its own way of doing this. For example, the distro bootmeth simply looks through the provided filesystem @@ -106,7 +106,7 @@ they scan a lot of devices. Boot process ------------ -U-Boot tries to use the 'lazy init' approach whereever possible and distro boot +U-Boot tries to use the 'lazy init' approach wherever possible and distro boot is no exception. The algorithm is:: while (get next bootdev) @@ -174,13 +174,13 @@ the same way as setting this variable. Bootdev uclass -------------- -The bootdev uclass provides an simple API call to obtain a bootflows from a +The bootdev uclass provides a simple API call to obtain a bootflow from a device:: int bootdev_get_bootflow(struct udevice *dev, struct bootflow_iter *iter, struct bootflow *bflow); -This takes a iterator which indicates the bootdev, partition and bootmeth to +This takes an iterator which indicates the bootdev, partition and bootmeth to use. It returns a bootflow. This is the core of the bootdev implementation. The bootdev drivers that implement this differ depending on the media they are reading from, but each is responsible for returning a valid bootflow if @@ -188,7 +188,7 @@ available. A helper called `bootdev_find_in_blk()` makes it fairly easy to implement this function for each media device uclass, in a few lines of code. For many types -ot bootdevs, the `get_bootflow` member can be NULL, indicating that the default +of bootdevs, the `get_bootflow` member can be NULL, indicating that the default handler is used. This is called `default_get_bootflow()` and it only works with block devices. @@ -196,7 +196,7 @@ block devices. Bootdev drivers --------------- -A bootdev driver is typically fairly simple. Here is one for mmc:: +A bootdev driver is typically fairly simple. Here is one for MMC:: static int mmc_bootdev_bind(struct udevice *dev) { @@ -328,7 +328,7 @@ or:: Here, `eth_bootdev` is the name of the Ethernet bootdev driver and `dev` -is the ethernet device. This function is safe to call even if standard boot is +is the Ethernet device. This function is safe to call even if standard boot is not enabled, since it does nothing in that case. It can be added to all uclasses which implement suitable media. @@ -340,7 +340,7 @@ Standard boot requires a single instance of the bootstd device to make things work. This includes global information about the state of standard boot. See `struct bootstd_priv` for this structure, accessed with `bootstd_get_priv()`. -Within the devicetree, if you add bootmeth devices, they should be children of +Within the Device Tree, if you add bootmeth devices, they should be children of the bootstd device. See `arch/sandbox/dts/test.dts` for an example of this. @@ -349,12 +349,12 @@ the bootstd device. See `arch/sandbox/dts/test.dts` for an example of this. Automatic devices ----------------- -It is possible to define all the required devices in the devicetree manually, +It is possible to define all the required devices in the Device Tree manually, but it is not necessary. The bootstd uclass includes a `dm_scan_other()` function which creates the bootstd device if not found. If no bootmeth devices are found at all, it creates one for each available bootmeth driver. -If your devicetree has any bootmeth device it must have all of them that you +If your Device Tree has any bootmeth device it must have all of them that you want to use, since no bootmeth devices will be created automatically in that case. @@ -363,8 +363,8 @@ Using devicetree ---------------- If a bootdev is complicated or needs configuration information, it can be -added to the devicetree as a child of the media device. For example, imagine a -bootdev which reads a bootflow from SPI flash. The devicetree fragment might +added to the Device Tree as a child of the media device. For example, imagine a +bootdev which reads a bootflow from SPI flash. The Device Tree fragment might look like this:: spi@0 { @@ -398,7 +398,7 @@ Standard boot is enabled with `CONFIG_BOOTSTD`. Each bootmeth has its own CONFIG option also. For example, `CONFIG_BOOTMETH_EXTLINUX` enables support for booting from a disk using an `extlinux.conf` file. -To enable all feature sof standard boot, use `CONFIG_BOOTSTD_FULL`. This +To enable all features of standard boot, use `CONFIG_BOOTSTD_FULL`. This includes the full set of commands, more error messages when things go wrong and bootmeth ordering with the bootmeths environment variable. @@ -492,9 +492,9 @@ Theory of operation This describes how standard boot progresses through to booting an operating system. -To start. all the necessary devices must be bound, including bootstd, which +To start, all the necessary devices must be bound, including bootstd, which provides the top-level `struct bootstd_priv` containing optional configuration -information. The bootstd device is also holds the various lists used while +information. The bootstd device also holds the various lists used while scanning. This step is normally handled automatically by driver model, as described in `Automatic Devices`_. @@ -504,7 +504,7 @@ those bootdevs. So, all up, we need a single bootstd device, one or more bootdev devices and one or more bootmeth devices. Once these are ready, typically a `bootflow scan` command is issued. This kicks -of the iteration process, which involves hunting for bootdevs and looking +off the iteration process, which involves hunting for bootdevs and looking through the bootdevs and their partitions one by one to find bootflows. Iteration is kicked off using `bootflow_scan_first()`. @@ -526,7 +526,7 @@ Then the iterator is set up to according to the parameters given: - If `label` indicates a numeric bootdev number (e.g. "2") then `BOOTFLOW_METHF_SINGLE_DEV` is set. In this case, moving to the next bootdev - simple stops, since there is only one. No hunters are used. + simply stops, since there is only one. No hunters are used. - If `label` indicates a particular media device (e.g. "mmc1") then `BOOTFLOWIF_SINGLE_MEDIA` is set. In this case, moving to the next bootdev processes just the children of the media device. Hunters are used, in this @@ -554,7 +554,7 @@ bootdev and disturb the original ordering. Next, the ordering of bootmeths is determined, by `bootmeth_setup_iter_order()`. By default the ordering is again by sequence number, i.e. the `/aliases` node, -or failing that the order in the devicetree. But the `bootmeth order` command +or failing that the order in the Device Tree. But the `bootmeth order` command or `bootmeths` environment variable can be used to set up an ordering. If that has been done, the ordering is in `struct bootstd_priv`, so that ordering is simply copied into the iterator. Either way, the `method_order` array it set up, @@ -652,12 +652,12 @@ valid bootflow is found early on. With `bootflow scan -b`, that causes the bootflow to be immediately booted. Assuming it is successful, the iteration never completes. -Also note that the iterator hold the **current** combination being considered. +Also note that the iterator holds the **current** combination being considered. So when `iter_incr()` is called, it increments to the next one and returns it, the new **current** combination. Note also the `err` field in `struct bootflow_iter`. This is normally 0 and has -thus has no effect on `iter_inc()`. But if it is non-zero, signalling an error, +thus no effect on `iter_inc()`. But if it is non-zero, signalling an error, it indicates to the iterator what it should do when called. It can force moving to the next partition, or bootdev, for example. The special values `BF_NO_MORE_PARTS` and `BF_NO_MORE_DEVICES` handle this. When `iter_incr` sees @@ -675,7 +675,7 @@ So what happens inside of `bootflow_check()`? It simply calls the uclass method `bootdev_get_bootflow()` to ask the bootdev to return a bootflow. It passes the iterator to the bootdev method, so that function knows what we are talking about. At first, the bootflow is set up in the state `BOOTFLOWST_BASE`, -with just the `method` and `dev` intiialised. But the bootdev may fill in more, +with just the `method` and `dev` initialised. But the bootdev may fill in more, e.g. updating the state, depending on what it finds. For global bootmeths the `bootmeth_get_bootflow()` function is called instead of `bootdev_get_bootflow()`. @@ -733,12 +733,12 @@ bootflow is handled by the bootmeth driver for that bootflow. In the case of extlinux boot, this parses and processes the `extlinux.conf` file that was read. See `extlinux_boot()` for how that works. The processing may involve reading additional files, which is handled by the `read_file()` method, which is -`extlinux_read_file()` in this case. All bootmethds should support reading +`extlinux_read_file()` in this case. All bootmeths should support reading files, since the bootflow is typically only the basic instructions and does not include the operating system itself, ramdisk, device tree, etc. The vast majority of the bootstd code is concerned with iterating through -partitions on bootdevs and using bootmethds to find bootflows. +partitions on bootdevs and using bootmeths to find bootflows. How about bootdevs which are not block devices? They are handled by the same methods as above, but with a different implementation. For example, the bootmeth diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index 4cc1457d4ea..ca4fb0b5b10 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -113,9 +113,12 @@ SoC being used via Kconfig and set `DEFAULT_DEVICE_TREE=<vendor>/<name>` when prompted by Kconfig. However, if `dts/upstream/` hasn't yet received devicetree source file for your -newly added board support then you can add corresponding devicetree source file -as `arch/<arch>/dts/<name>.dts`. To select that add `# CONFIG_OF_UPSTREAM is not -set` and set `DEFAULT_DEVICE_TREE=<name>` when prompted by Kconfig. +newly added board support then one option is that you can add the corresponding +devicetree source file as `arch/<arch>/dts/<name>.dts`. To select that add `# +CONFIG_OF_UPSTREAM is not set` and set `DEFAULT_DEVICE_TREE=<name>` when +prompted by Kconfig. Another option is that you can use use the "pick" option of +`dts/update-dts-subtree.sh` mentioned above to bring in the commits that you +need. This should include your CPU or SoC's devicetree file. On top of that any U-Boot specific tweaks (see: :ref:`dttweaks`) can be made for your board. diff --git a/doc/develop/gdb.rst b/doc/develop/gdb.rst new file mode 100644 index 00000000000..4e359c7f226 --- /dev/null +++ b/doc/develop/gdb.rst @@ -0,0 +1,171 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (c) 2024 Alexander Dahl + +Debugging U-Boot with GDB +========================= + +Using a JTAG adapter it is possible to debug a running U-Boot with GDB. +A common way is to connect a debug adapter to the JTAG connector of your +board, run a GDB server, connect GDB to the GDB server, and use GDB as usual. + +Similarly QEMU can provide a GDB server. + +Preparing build +--------------- + +Building U-Boot with with reduced optimization (-Og) and without link time +optimization is recommended for easier debugging:: + + CONFIG_CC_OPTIMIZE_FOR_DEBUG=y + CONFIG_LTO=n + +Otherwise build, install, and run U-Boot as usual. + +Using OpenOCD as GDB server +--------------------------- + +`OpenOCD <https://openocd.org/>`_ is an open source tool supporting hardware +debug probes, and providing a GDB server. It is readily available in major Linux +distributions or you can build it from source. + +Here is example of starting OpenOCD on Debian using a J-Link adapter and a +board with an AT91 SAMA5D2 SoC: + +.. code-block:: console + + $ openocd -f interface/jlink.cfg -f target/at91sama5d2.cfg -c 'adapter speed 4000' + Open On-Chip Debugger 0.12.0 + Licensed under GNU GPL v2 + For bug reports, read + http://openocd.org/doc/doxygen/bugs.html + Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. + adapter speed: 4000 kHz + + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : J-Link V10 compiled Jan 30 2023 11:28:07 + Info : Hardware version: 10.10 + Info : VTarget = 3.244 V + Info : clock speed 4000 kHz + Info : JTAG tap: at91sama5d2.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x5) + Info : at91sama5d2.cpu_a5.0: hardware has 3 breakpoints, 2 watchpoints + Info : at91sama5d2.cpu_a5.0: MPIDR level2 0, cluster 0, core 0, mono core, no SMT + Info : starting gdb server for at91sama5d2.cpu_a5.0 on 3333 + Info : Listening on port 3333 for gdb connections + +Notice that OpenOCD is listening on port 3333 for GDB connections. + +Using QEMU as GDB server +------------------------ + +When running U-Boot on QEMU you can used the '-gdb' parameter to provide a +GDB server: + + qemu-system-riscv64 -M virt -nographic -gdb tcp::3333 -kernel u-boot + +Running a GDB session +---------------------- + +You need a GDB suited for your target. This can be the GDB coming with your +toolchain or *gdb-multiarch* available in your Linux distribution. + +.. prompt:: bash $ + + gdb-multiarch u-boot + +In the above command-line *u-boot* is the U-boot binary in your build +directory. You may need to adjust the path when calling GDB. + +Connect to the GDB server like this: + +.. code-block:: console + + (gdb) target extended-remote :3333 + Remote debugging using :3333 + 0x27fa9ac6 in ?? () + (gdb) + +This is fine for debugging before U-Boot relocates itself. + +For debugging U-Boot after relocation you need to indicate the relocation +address to GDB. You can retrieve the relocation address from the U-Boot shell +with the command *bdinfo*: + +.. code-block:: console + + U-Boot> bdinfo + boot_params = 0x20000100 + DRAM bank = 0x00000000 + -> start = 0x20000000 + -> size = 0x08000000 + flashstart = 0x00000000 + flashsize = 0x00000000 + flashoffset = 0x00000000 + baudrate = 115200 bps + relocaddr = 0x27f7a000 + reloc off = 0x0607a000 + Build = 32-bit + current eth = ethernet@f8008000 + ethaddr = 00:50:c2:31:58:d4 + IP addr = <NULL> + fdt_blob = 0x27b36060 + new_fdt = 0x27b36060 + fdt_size = 0x00003e40 + lmb_dump_all: + memory.cnt = 0x1 / max = 0x10 + memory[0] [0x20000000-0x27ffffff], 0x08000000 bytes flags: 0 + reserved.cnt = 0x1 / max = 0x10 + reserved[0] [0x27b31d00-0x27ffffff], 0x004ce300 bytes flags: 0 + devicetree = separate + arch_number = 0x00000000 + TLB addr = 0x27ff0000 + irq_sp = 0x27b36050 + sp start = 0x27b36040 + Early malloc usage: cd8 / 2000 + +Look out for the line starting with *relocaddr* which has the address +you need, ``0x27f7a000`` in this case. + +On most architectures (not sandbox, x86, Xtensa) the global data pointer is +stored in a fixed register: + +============ ======== +Architecture Register +============ ======== +arc r25 +arm r9 +arm64 x18 +m68k d7 +microblaze r31 +mips k0 +nios2 gp +powerpc r2 +riscv gp +sh r13 +============ ======== + +On these architecture the relocation address cat be determined by +dereferencing the global data pointer stored in register, *r9* in the example: + +.. code-block:: console + + (gdb) p/x (*(struct global_data*)$r9)->relocaddr + $1 = 0x27f7a000 + +In the GDB shell discard the previously loaded symbol file and add it once +again with the relocation address like this: + +.. code-block:: console + + (gdb) symbol-file + Discard symbol table from `/home/adahl/build/u-boot/v2024.04.x/u-boot'? (y or n) y + No symbol file now. + (gdb) add-symbol-file u-boot 0x27f7a000 + add symbol table from file "u-boot" at + .text_addr = 0x27f7a000 + (y or n) y + Reading symbols from u-boot... + (gdb) + +You can now use GDB as usual, setting breakpoints, printing backtraces, +inspecting variables, stepping through the code, etc. diff --git a/doc/develop/index.rst b/doc/develop/index.rst index f82e148b101..f9c4bf839ee 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -60,6 +60,7 @@ Debugging :maxdepth: 1 crash_dumps + gdb trace Packaging diff --git a/doc/develop/process.rst b/doc/develop/process.rst index 92477d05dd8..0542b3fc124 100644 --- a/doc/develop/process.rst +++ b/doc/develop/process.rst @@ -34,7 +34,7 @@ It is followed by a *Stabilization Period*. The end of a Release Cycle is marked by the release of a new U-Boot version. Merge Window ------------- +^^^^^^^^^^^^ The Merge Window is the period when new patches get submitted (and hopefully accepted) for inclusion into U-Boot mainline. This period lasts for 21 days (3 @@ -44,7 +44,7 @@ This is the only time when new code (like support for new processors or new boards, or other new features or reorganization of code) is accepted. Twilight Time -------------- +^^^^^^^^^^^^^ Usually patches do not get accepted as they are - the peer review that takes place will usually require changes and resubmissions of the patches before they @@ -65,13 +65,13 @@ the Merge Window does not preclude patches that were already posted from being merged for the upcoming release. Stabilization Period --------------------- +^^^^^^^^^^^^^^^^^^^^ During the Stabilization Period only patches containing bug fixes get applied. Corner Cases ------------- +^^^^^^^^^^^^ Sometimes it is not clear if a patch contains a bug fix or not. For example, changes that remove dead code, unused macros etc. or @@ -108,6 +108,19 @@ Differences to the Linux Development Process In U-Boot, ``"-rc1"`` will only be released after all (or at least most of the) patches that were submitted during the merge window have been applied. +Resyncing of the device tree subtree +------------------------------------ + +As explained in :doc:`devicetree/control` some platforms make use of device tree +files which come from a git subtree that mirrors the Linux Kernel sources +itself. For our purposes, we only track releases and not release candidates for +merging in our tree. These merges follow the normal merge window rules. + +In the case of specific changes, such as bug fixes or new platform support, +these can be "cherry-picked" and are subject to the normal merge rules. For +example, a bug fix can come in later in the window but a full re-sync only +happens within the merge window itself. + .. _custodians: Custodians diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index c9fb07f59e1..541ab0adaf8 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -51,13 +51,14 @@ Examples:: Current Status -------------- -* U-Boot v2024.04 was released on Tue 02 April 2024. +* U-Boot v2024.07 was released on Mon 01 July 2024. -* The Merge Window for the next release (v2024.07) is **closed**. +* The Merge Window for the next release (v2024.10) is **open** until the -rc1 + release on Mon 22 July 2024. -* The next branch is now **open**. +* The next branch is now **closed**. -* Release "v2024.07" is scheduled for 01 July 2024. +* Release "v2024.10" is scheduled for 07 October 2024. Future Releases --------------- @@ -65,29 +66,31 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -For the next scheduled release, release candidates were made on:: +.. For the next scheduled release, release candidates were made on:: -* U-Boot v2024.07-rc1 was released on Mon 22 April 2024. +.. * U-Boot v2024.10-rc1 was released on Mon 22 July 2024. -* U-Boot v2024.07-rc2 was released on Mon 06 May 2024. +.. * U-Boot v2024.10-rc2 was released on Mon 05 August 2024. -* U-Boot v2024.07-rc3 was released on Mon 20 May 2024. +.. * U-Boot v2024.10-rc3 was released on Mon 19 August 2024. -* U-Boot v2024.07-rc4 was released on Mon 03 June 2024. +.. * U-Boot v2024.10-rc4 was released on Mon 02 September 2024. -.. * U-Boot v2024.07-rc5 was released on Mon 17 June 2024. +.. * U-Boot v2024.10-rc5 was released on Mon 16 September 2024. + +.. * U-Boot v2024.10-rc6 was released on Mon 30 September 2024. Please note that the following dates are planned only and may be deviated from as needed. -* "v2024.07": end of MW = Mon, Apr 22, 2024; release = Mon, Jul 01, 2024 - * "v2024.10": end of MW = Mon, Jul 22, 2024; release = Mon, Oct 07, 2024 * "v2025.01": end of MW = Mon, Oct 21, 2024; release = Mon, Jan 06, 2025 * "v2025.04": end of MW = Mon, Jan 27, 2025; release = Mon, Apr 07, 2025 +* "v2025.07": end of MW = Mon, Apr 21, 2025; release = Mon, Jul 07, 2025 + Previous Releases ----------------- @@ -95,6 +98,8 @@ Note: these statistics are generated by our fork of `gitdm <https://source.denx.de/u-boot/gitdm>`_, which was originally created by Jonathan Corbet. +* :doc:`statistics/u-boot-stats-v2024.07` which was released on 01 July 2024. + * :doc:`statistics/u-boot-stats-v2024.04` which was released on 02 April 2024. * :doc:`statistics/u-boot-stats-v2024.01` which was released on 08 January 2024. diff --git a/doc/develop/statistics/u-boot-stats-v2024.07.rst b/doc/develop/statistics/u-boot-stats-v2024.07.rst new file mode 100644 index 00000000000..b437e926659 --- /dev/null +++ b/doc/develop/statistics/u-boot-stats-v2024.07.rst @@ -0,0 +1,890 @@ +:orphan: + +Release Statistics for U-Boot v2024.07 +====================================== + +* Processed 1624 changesets from 191 developers + +* 28 employers found + +* A total of 2308875 lines added, 242831 removed (delta 2066044) + +.. table:: Developers with the most changesets + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Tom Rini 324 (20.0%) + Jonas Karlman 155 (9.5%) + Caleb Connolly 98 (6.0%) + Heinrich Schuchardt 84 (5.2%) + Quentin Schulz 59 (3.6%) + Marek Vasut 52 (3.2%) + Simon Glass 44 (2.7%) + Patrice Chotard 32 (2.0%) + Sumit Garg 31 (1.9%) + Svyatoslav Ryhel 31 (1.9%) + Michal Simek 26 (1.6%) + Ilias Apalodimas 23 (1.4%) + Neil Armstrong 23 (1.4%) + Jonathan Humphreys 22 (1.4%) + Andrew Davis 18 (1.1%) + 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Chen-Yu Tsai 5 (0.3%) + Javier Martinez Canillas 4 (0.2%) + Francesco Dolcini 4 (0.2%) + Felipe Balbi 4 (0.2%) + Aniket Limaye 4 (0.2%) + Christopher Obbard 4 (0.2%) + Mathieu Othacehe 4 (0.2%) + Joao Paulo Goncalves 4 (0.2%) + Sughosh Ganu 4 (0.2%) + Volodymyr Babchuk 4 (0.2%) + Lukasz Majewski 4 (0.2%) + Jacky Chou 4 (0.2%) + Dan Carpenter 4 (0.2%) + Mihai Sain 4 (0.2%) + Arseniy Krasnov 3 (0.2%) + Fiona Klute 3 (0.2%) + Hanyuan Zhao 3 (0.2%) + Greg Malysa 3 (0.2%) + Nathan Barrett-Morrison 3 (0.2%) + Peter Robinson 3 (0.2%) + Lukas Funke 3 (0.2%) + Yannic Moog 3 (0.2%) + Udit Kumar 3 (0.2%) + Michael Walle 3 (0.2%) + Devarsh Thakkar 3 (0.2%) + Christophe Kerello 3 (0.2%) + Viacheslav Bocharov 3 (0.2%) + Emanuele Ghidoli 3 (0.2%) + Hari Nagalla 3 (0.2%) + Love Kumar 3 (0.2%) + Thomas Weißschuh 3 (0.2%) + Weijie Gao 3 (0.2%) + Dragan Simic 2 (0.1%) + Michael Trimarchi 2 (0.1%) + Patrick Delaunay 2 (0.1%) + Tony Dinh 2 (0.1%) + Sam Povilus 2 (0.1%) + H Bell 2 (0.1%) + Thinh Nguyen 2 (0.1%) + Benjamin Hahn 2 (0.1%) + Neha Malcom Francis 2 (0.1%) + Ian Roberts 2 (0.1%) + Sean Anderson 2 (0.1%) + Kamlesh Gurudasani 2 (0.1%) + Stefan Eichenberger 2 (0.1%) + Parth Pancholi 2 (0.1%) + Maksim Kiselev 2 (0.1%) + Christophe Roullier 2 (0.1%) + Hugo Dubois 2 (0.1%) + CASAUBON Jean Michel 2 (0.1%) + Ahelenia Ziemiańska 2 (0.1%) + Yasuharu Shibata 2 (0.1%) + Wan Yee Lau 2 (0.1%) + Vincent Stehlé 2 (0.1%) + Marcel Ziswiler 2 (0.1%) + Maxim Moskalets 2 (0.1%) + Sébastien Szymanski 2 (0.1%) + Tejas Bhumkar 2 (0.1%) + Bhupesh Sharma 2 (0.1%) + Colin McAllister 2 (0.1%) + Andy Yan 2 (0.1%) + Dasnavis Sabiya 2 (0.1%) + Stefan Bosch 2 (0.1%) + Frank Wunderlich 1 (0.1%) + Jiaxun Yang 1 (0.1%) + Ravi Minnikanti 1 (0.1%) + John Watts 1 (0.1%) + Heiko Schocher 1 (0.1%) + Thomas Perl 1 (0.1%) + Kristian Amlie 1 (0.1%) + Heiko Stuebner 1 (0.1%) + Anand Moon 1 (0.1%) + Alexander Sverdlin 1 (0.1%) + Aswath Govindraju 1 (0.1%) + Sam Day 1 (0.1%) + Boon Khai Ng 1 (0.1%) + William Zhang 1 (0.1%) + Jaehoon Chung 1 (0.1%) + Sam Edwards 1 (0.1%) + Linus Walleij 1 (0.1%) + Kishan Dudhatra 1 (0.1%) + Yu Chien Peter Lin 1 (0.1%) + Nitin Yadav 1 (0.1%) + Andrea Calabrese 1 (0.1%) + Lukasz Czechowski 1 (0.1%) + Finley Xiao 1 (0.1%) + Jason Zhu 1 (0.1%) + Maximilian Brune 1 (0.1%) + cmachida 1 (0.1%) + Hector Martin 1 (0.1%) + Anton Bambura 1 (0.1%) + Khem Raj 1 (0.1%) + Jianan Huang 1 (0.1%) + Charles Hardin 1 (0.1%) + Gireesh Hiremath 1 (0.1%) + Alexey Romanov 1 (0.1%) + Eugeniu Rosca 1 (0.1%) + Bruce Suen 1 (0.1%) + Kunihiko Hayashi 1 (0.1%) + Hugo Cornelis 1 (0.1%) + Vitor Soares 1 (0.1%) + Martyn Welch 1 (0.1%) + Manorit Chawdhry 1 (0.1%) + Jixiong Hu 1 (0.1%) + Pierre-Clément Tosi 1 (0.1%) + Hiago De Franco 1 (0.1%) + Petr Zejdl 1 (0.1%) + Łukasz Stelmach 1 (0.1%) + Ben Dooks 1 (0.1%) + Javier Viguera 1 (0.1%) + Josua Mayer 1 (0.1%) + James Hilliard 1 (0.1%) + Marjolaine Amate 1 (0.1%) + Vishal Sagar 1 (0.1%) + Manikanta Guntupalli 1 (0.1%) + Shubhangi Shrikrushna Mahalle 1 (0.1%) + Piotr Wojtaszczyk 1 (0.1%) + Kelly Hung 1 (0.1%) + Leon M. Busch-George 1 (0.1%) + Lukasz Wiecaszek 1 (0.1%) + Jit Loon Lim 1 (0.1%) + William Wu 1 (0.1%) + Ben Wolsieffer 1 (0.1%) + Elon Zhang 1 (0.1%) + Vignesh Raghavendra 1 (0.1%) + Maks Mishin 1 (0.1%) + Bob Wolff 1 (0.1%) + Romain Naour 1 (0.1%) + Dmitry Baryshkov 1 (0.1%) + Vishal Mahaveer 1 (0.1%) + Siddharth Vadapalli 1 (0.1%) + Ivan Orlov 1 (0.1%) + Nam Cao 1 (0.1%) + Massimiliano Minella 1 (0.1%) + BELOUARGA Mohamed 1 (0.1%) + Alexander Gendin 1 (0.1%) + Ivan Mikhaylov 1 (0.1%) + ==================================== ===== + + +.. table:: Developers with the most changed lines + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Tom Rini 2187616 (86.6%) + Jonas Karlman 69460 (2.8%) + Marek Vasut 53285 (2.1%) + Caleb Connolly 47393 (1.9%) + Apurva Nandan 26241 (1.0%) + Neil Armstrong 23816 (0.9%) + Tim Harvey 10971 (0.4%) + Christophe Leroy 10210 (0.4%) + Wadim Egorov 8248 (0.3%) + Bryan Brattlof 7039 (0.3%) + Tony Dinh 5540 (0.2%) + Marcel Ziswiler 5068 (0.2%) + Nathan Barrett-Morrison 4872 (0.2%) + Adam Ford 4867 (0.2%) + Sumit Garg 4743 (0.2%) + Andrew Davis 4066 (0.2%) + Quentin Schulz 3449 (0.1%) + Peng Fan 3071 (0.1%) + Sam Protsenko 3021 (0.1%) + Jit Loon Lim 2717 (0.1%) + MD Danish Anwar 2686 (0.1%) + Anand Moon 2526 (0.1%) + Svyatoslav Ryhel 2445 (0.1%) + Andy Yan 1978 (0.1%) + Peter Robinson 1907 (0.1%) + Boon Khai Ng 1709 (0.1%) + Arseniy Krasnov 1669 (0.1%) + Heinrich Schuchardt 1350 (0.1%) + Jagan Teki 1347 (0.1%) + Fabio Estevam 1209 (0.0%) + Ilias Apalodimas 1189 (0.0%) + Simon Glass 1137 (0.0%) + Roger Quadros 955 (0.0%) + Marek Behún 939 (0.0%) + Elon Zhang 889 (0.0%) + Kongyang Liu 846 (0.0%) + Mihai Sain 789 (0.0%) + Bhupesh Sharma 662 (0.0%) + Jonas Schwöbel 620 (0.0%) + Javier Martinez Canillas 597 (0.0%) + Michael Walle 505 (0.0%) + Eugene Uriev 501 (0.0%) + Christophe Kerello 479 (0.0%) + Chris Morgan 452 (0.0%) + Michal Simek 449 (0.0%) + Bhargav Raviprakash 388 (0.0%) + Janne Grunau 386 (0.0%) + Robert Marko 332 (0.0%) + Vignesh Raghavendra 332 (0.0%) + H Bell 291 (0.0%) + Yang Xiwen 278 (0.0%) + Bruce Suen 269 (0.0%) + Daniel Schultz 265 (0.0%) + Love Kumar 258 (0.0%) + Igor Opaniuk 219 (0.0%) + Raymond Mao 208 (0.0%) + Wan Yee Lau 206 (0.0%) + Sughosh Ganu 201 (0.0%) + Greg Malysa 200 (0.0%) + Patrice Chotard 199 (0.0%) + Masahisa Kojima 193 (0.0%) + Dasnavis Sabiya 189 (0.0%) + Neha Malcom Francis 183 (0.0%) + Jonathan Humphreys 173 (0.0%) + Anton Bambura 167 (0.0%) + Kelly Hung 164 (0.0%) + Andre Przywara 163 (0.0%) + Kamlesh Gurudasani 163 (0.0%) + Volodymyr Babchuk 147 (0.0%) + Parth Pancholi 146 (0.0%) + Piotr Wojtaszczyk 144 (0.0%) + Judith Mendez 131 (0.0%) + Joao Paulo Goncalves 131 (0.0%) + Leonard Anderweit 117 (0.0%) + BELOUARGA Mohamed 114 (0.0%) + Finley Xiao 109 (0.0%) + Jianan Huang 99 (0.0%) + Venkatesh Yadav Abbarapu 95 (0.0%) + Chen-Yu Tsai 92 (0.0%) + Mathieu Othacehe 92 (0.0%) + Michał Barnaś 86 (0.0%) + Lukasz Majewski 74 (0.0%) + Alexander Dahl 67 (0.0%) + Nishanth Menon 66 (0.0%) + Conor Dooley 64 (0.0%) + Francesco Dolcini 64 (0.0%) + Maksim Kiselev 64 (0.0%) + Linus Walleij 64 (0.0%) + Weizhao Ouyang 63 (0.0%) + Yannic Moog 61 (0.0%) + Weijie Gao 60 (0.0%) + Ben Dooks 60 (0.0%) + Leo Yu-Chi Liang 59 (0.0%) + Fiona Klute 56 (0.0%) + Alexey Romanov 56 (0.0%) + Jim Liu 55 (0.0%) + Devarsh Thakkar 53 (0.0%) + Colin McAllister 53 (0.0%) + Maxim Moskalets 51 (0.0%) + Josua Mayer 50 (0.0%) + Ivan Mikhaylov 50 (0.0%) + Ian Roberts 47 (0.0%) + Christophe Roullier 44 (0.0%) + Vincent Stehlé 44 (0.0%) + Nam Cao 43 (0.0%) + Ben Wolsieffer 42 (0.0%) + Felipe Balbi 41 (0.0%) + Vishal Sagar 40 (0.0%) + Hanyuan Zhao 38 (0.0%) + Hugo Dubois 37 (0.0%) + Christopher Obbard 34 (0.0%) + Aniket Limaye 33 (0.0%) + Romain Naour 33 (0.0%) + Heiko Stuebner 31 (0.0%) + Emanuele Ghidoli 30 (0.0%) + Stefan Bosch 30 (0.0%) + mwleeds@mailtundra.com 28 (0.0%) + Michael Trimarchi 23 (0.0%) + Thomas Weißschuh 22 (0.0%) + Thinh Nguyen 21 (0.0%) + Nitin Yadav 19 (0.0%) + Jixiong Hu 18 (0.0%) + Marjolaine Amate 18 (0.0%) + Dan Carpenter 17 (0.0%) + Stefan Eichenberger 17 (0.0%) + Sam Povilus 15 (0.0%) + Sébastien Szymanski 15 (0.0%) + Massimiliano Minella 15 (0.0%) + Mattijs Korpershoek 14 (0.0%) + Sean Anderson 14 (0.0%) + Lukas Funke 13 (0.0%) + Yasuharu Shibata 13 (0.0%) + Sam Edwards 13 (0.0%) + Kunihiko Hayashi 13 (0.0%) + Jacky Chou 12 (0.0%) + Vitor Soares 12 (0.0%) + Ye Li 11 (0.0%) + Udit Kumar 11 (0.0%) + Hiago De Franco 11 (0.0%) + Hari Nagalla 10 (0.0%) + Maximilian Brune 10 (0.0%) + Leon M. Busch-George 10 (0.0%) + Viacheslav Bocharov 9 (0.0%) + Benjamin Hahn 9 (0.0%) + cmachida 9 (0.0%) + James Hilliard 9 (0.0%) + Lukasz Wiecaszek 9 (0.0%) + Charles Hardin 8 (0.0%) + Petr Zejdl 8 (0.0%) + Vishal Mahaveer 8 (0.0%) + Sam Day 7 (0.0%) + Manorit Chawdhry 7 (0.0%) + Łukasz Stelmach 7 (0.0%) + Andrea Calabrese 6 (0.0%) + Siddharth Vadapalli 6 (0.0%) + CASAUBON Jean Michel 5 (0.0%) + Ahelenia Ziemiańska 5 (0.0%) + Ravi Minnikanti 5 (0.0%) + Hugo Cornelis 5 (0.0%) + Bob Wolff 5 (0.0%) + Alexander Gendin 5 (0.0%) + Dragan Simic 4 (0.0%) + Aswath Govindraju 4 (0.0%) + Kishan Dudhatra 4 (0.0%) + Khem Raj 4 (0.0%) + Tejas Bhumkar 3 (0.0%) + Heiko Schocher 3 (0.0%) + Lukasz Czechowski 3 (0.0%) + Jason Zhu 3 (0.0%) + Maks Mishin 3 (0.0%) + Patrick Delaunay 2 (0.0%) + Jiaxun Yang 2 (0.0%) + William Zhang 2 (0.0%) + Eugeniu Rosca 2 (0.0%) + Pierre-Clément Tosi 2 (0.0%) + Javier Viguera 2 (0.0%) + Manikanta Guntupalli 2 (0.0%) + Dmitry Baryshkov 2 (0.0%) + Frank Wunderlich 1 (0.0%) + John Watts 1 (0.0%) + Thomas Perl 1 (0.0%) + Kristian Amlie 1 (0.0%) + Alexander Sverdlin 1 (0.0%) + Jaehoon Chung 1 (0.0%) + Yu Chien Peter Lin 1 (0.0%) + Hector Martin 1 (0.0%) + Gireesh Hiremath 1 (0.0%) + Martyn Welch 1 (0.0%) + Shubhangi Shrikrushna Mahalle 1 (0.0%) + William Wu 1 (0.0%) + Ivan Orlov 1 (0.0%) + ==================================== ===== + + +.. table:: Developers with the most lines removed + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Jonas Karlman 59892 (24.7%) + Marek Vasut 51731 (21.3%) + Neil Armstrong 19240 (7.9%) + Tim Harvey 10397 (4.3%) + Tony Dinh 5465 (2.3%) + Marcel Ziswiler 5061 (2.1%) + Adam Ford 4818 (2.0%) + Andrew Davis 3493 (1.4%) + Peng Fan 2778 (1.1%) + Anand Moon 2523 (1.0%) + Sam Protsenko 2273 (0.9%) + Peter Robinson 1907 (0.8%) + Fabio Estevam 1185 (0.5%) + Sumit Garg 845 (0.3%) + Javier Martinez Canillas 582 (0.2%) + Michael Walle 494 (0.2%) + Chen-Yu Tsai 80 (0.0%) + Igor Opaniuk 72 (0.0%) + Linus Walleij 61 (0.0%) + Francesco Dolcini 36 (0.0%) + Sam Edwards 12 (0.0%) + Ben Wolsieffer 11 (0.0%) + Hiago De Franco 11 (0.0%) + Kunihiko Hayashi 10 (0.0%) + Colin McAllister 7 (0.0%) + Heiko Schocher 3 (0.0%) + Dan Carpenter 2 (0.0%) + Dragan Simic 2 (0.0%) + Jiaxun Yang 1 (0.0%) + William Zhang 1 (0.0%) + ==================================== ===== + + +.. table:: Developers with the most signoffs (total 231) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Caleb Connolly 41 (17.7%) + Mattijs Korpershoek 19 (8.2%) + Michal Simek 15 (6.5%) + Dario Binacchi 11 (4.8%) + Chris Morgan 10 (4.3%) + Ilias Apalodimas 10 (4.3%) + Svyatoslav Ryhel 10 (4.3%) + Hari Nagalla 8 (3.5%) + Minkyu Kang 7 (3.0%) + Alexander Sverdlin 6 (2.6%) + Ian Roberts 6 (2.6%) + Greg Malysa 5 (2.2%) + Nathan Barrett-Morrison 5 (2.2%) + Manorit Chawdhry 4 (1.7%) + Dasnavis Sabiya 4 (1.7%) + Christophe Leroy 4 (1.7%) + Apurva Nandan 4 (1.7%) + Neil Armstrong 3 (1.3%) + Francesco Dolcini 3 (1.3%) + Vasileios Bimpikas 3 (1.3%) + Utsav Agarwal 3 (1.3%) + Arturs Artamonovs 3 (1.3%) + Neha Malcom Francis 3 (1.3%) + Janne Grunau 3 (1.3%) + Heinrich Schuchardt 3 (1.3%) + Jonas Karlman 2 (0.9%) + Marek Vasut 2 (0.9%) + Sumit Garg 2 (0.9%) + Dhruva Gole 2 (0.9%) + Kever Yang 2 (0.9%) + Ravi Gunasekaran 2 (0.9%) + Parvathi Bhogaraju 2 (0.9%) + Jayesh Choudhary 2 (0.9%) + Bo-Cun Chen 2 (0.9%) + Daniel Schultz 2 (0.9%) + Jonas Schwöbel 2 (0.9%) + Bryan Brattlof 2 (0.9%) + Peng Fan 1 (0.4%) + Fabio Estevam 1 (0.4%) + Stefan Roese 1 (0.4%) + Greg Kroah-Hartman 1 (0.4%) + Angelo Dureghello 1 (0.4%) + Anatolij Gustschin 1 (0.4%) + Vaishnav Achath 1 (0.4%) + Ashok Reddy Soma 1 (0.4%) + Dong Huang 1 (0.4%) + Shubhangi Shrikrushna Mahalle 1 (0.4%) + Felipe Balbi 1 (0.4%) + Judith Mendez 1 (0.4%) + Patrice Chotard 1 (0.4%) + Quentin Schulz 1 (0.4%) + ==================================== ===== + + +.. table:: Developers with the most reviews (total 1025) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Kever Yang 223 (21.8%) + Neil Armstrong 71 (6.9%) + Sumit Garg 70 (6.8%) + Dragan Simic 45 (4.4%) + Ilias Apalodimas 42 (4.1%) + Heinrich Schuchardt 35 (3.4%) + Patrick Delaunay 33 (3.2%) + Quentin Schulz 32 (3.1%) + Mattijs Korpershoek 31 (3.0%) + Leo Yu-Chi Liang 31 (3.0%) + Marek Vasut 28 (2.7%) + Jaehoon Chung 28 (2.7%) + Patrice Chotard 22 (2.1%) + Caleb Connolly 21 (2.0%) + Tom Rini 21 (2.0%) + Stefan Roese 20 (2.0%) + Neha Malcom Francis 17 (1.7%) + Simon Glass 16 (1.6%) + Peter Robinson 13 (1.3%) + Igor Opaniuk 13 (1.3%) + Thierry Reding 12 (1.2%) + Neal Gompa 11 (1.1%) + Heiko Schocher 9 (0.9%) + Michael Trimarchi 9 (0.9%) + Roger Quadros 9 (0.9%) + Tony Dinh 8 (0.8%) + Christopher Obbard 8 (0.8%) + Jonas Karlman 6 (0.6%) + Dhruva Gole 6 (0.6%) + E Shattow 6 (0.6%) + Christophe ROULLIER 6 (0.6%) + Richard Henderson 6 (0.6%) + Nishanth Menon 6 (0.6%) + Ravi Gunasekaran 5 (0.5%) + Teresa Remmet 5 (0.5%) + Mark Kettenis 5 (0.5%) + Paul Barker 5 (0.5%) + Udit Kumar 5 (0.5%) + Sean Anderson 5 (0.5%) + Fabio Estevam 4 (0.4%) + Sam Protsenko 4 (0.4%) + Enric Balletbo i Serra 4 (0.4%) + Laurent Pinchart 4 (0.4%) + Bryan Brattlof 3 (0.3%) + Andrew Davis 3 (0.3%) + Sam Edwards 3 (0.3%) + Dan Carpenter 3 (0.3%) + William Zhang 3 (0.3%) + Chris Packham 3 (0.3%) + Nikhil M Jain 3 (0.3%) + Tianling Shen 3 (0.3%) + Anatolij Gustschin 2 (0.2%) + CASAUBON Jean Michel 2 (0.2%) + Ian Ray 2 (0.2%) + Oleksandr Suvorov 2 (0.2%) + Bin Meng 2 (0.2%) + Tien Fong Chee 2 (0.2%) + Minkyu Kang 1 (0.1%) + Tim Harvey 1 (0.1%) + Adam Ford 1 (0.1%) + Linus Walleij 1 (0.1%) + Eddie James 1 (0.1%) + Guillaume La Roque 1 (0.1%) + Julien Masson 1 (0.1%) + Miquel Raynal 1 (0.1%) + Tim Lunn 1 (0.1%) + Cédric Le Goater 1 (0.1%) + Biju Das 1 (0.1%) + Holger Brunck 1 (0.1%) + Otavio Salvador 1 (0.1%) + Chia-Wei Wang 1 (0.1%) + Keerthy 1 (0.1%) + Philipp Tomsich 1 (0.1%) + Gao Xiang 1 (0.1%) + Frieder Schrempf 1 (0.1%) + Dmitrii Merkurev 1 (0.1%) + Marc Zyngier 1 (0.1%) + Ramon Fried 1 (0.1%) + Jai Luthra 1 (0.1%) + Alexander Dahl 1 (0.1%) + Heiko Stuebner 1 (0.1%) + Hugo Dubois 1 (0.1%) + Weizhao Ouyang 1 (0.1%) + Andre Przywara 1 (0.1%) + Mathieu Othacehe 1 (0.1%) + Wadim Egorov 1 (0.1%) + ==================================== ===== + + +.. table:: Developers with the most test credits (total 166) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Sumit Garg 19 (11.4%) + Marcel Ziswiler 15 (9.0%) + Svyatoslav Ryhel 10 (6.0%) + Mattijs Korpershoek 9 (5.4%) + Ion Agorria 9 (5.4%) + Tim Harvey 7 (4.2%) + Adam Ford 7 (4.2%) + Andreas Westman Dorcsak 7 (4.2%) + Sam Edwards 6 (3.6%) + Agneli 6 (3.6%) + Robert Eckelmann 6 (3.6%) + Simon Glass 5 (3.0%) + Teresa Remmet 5 (3.0%) + Fabio Estevam 5 (3.0%) + Ilias Apalodimas 4 (2.4%) + Jonathan Humphreys 4 (2.4%) + Neil Armstrong 3 (1.8%) + Paul Barker 3 (1.8%) + Heiko Stuebner 3 (1.8%) + Christian Gmeiner 3 (1.8%) + Heinrich Schuchardt 2 (1.2%) + Caleb Connolly 2 (1.2%) + Tony Dinh 2 (1.2%) + Hiago De Franco 2 (1.2%) + Robert Nelson 2 (1.2%) + Leo Yu-Chi Liang 1 (0.6%) + Jaehoon Chung 1 (0.6%) + Patrice Chotard 1 (0.6%) + Dhruva Gole 1 (0.6%) + E Shattow 1 (0.6%) + Ravi Gunasekaran 1 (0.6%) + Bryan Brattlof 1 (0.6%) + Andrew Davis 1 (0.6%) + Tim Lunn 1 (0.6%) + Otavio Salvador 1 (0.6%) + Wadim Egorov 1 (0.6%) + Michal Simek 1 (0.6%) + Alexander Sverdlin 1 (0.6%) + Jonas Schwöbel 1 (0.6%) + Judith Mendez 1 (0.6%) + Michael Walle 1 (0.6%) + Patrick Bruenn 1 (0.6%) + Jethro Bull 1 (0.6%) + Kamlesh Gurudasani 1 (0.6%) + Robert Marko 1 (0.6%) + ==================================== ===== + + +.. table:: Developers who gave the most tested-by credits (total 166) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Svyatoslav Ryhel 36 (21.7%) + Caleb Connolly 23 (13.9%) + Sumit Garg 15 (9.0%) + Apurva Nandan 12 (7.2%) + Marek Vasut 10 (6.0%) + Ilias Apalodimas 6 (3.6%) + Quentin Schulz 6 (3.6%) + Tom Rini 6 (3.6%) + Neil Armstrong 5 (3.0%) + Andrew Davis 5 (3.0%) + Leonard Anderweit 5 (3.0%) + Jonas Schwöbel 4 (2.4%) + Fabio Estevam 3 (1.8%) + Heinrich Schuchardt 3 (1.8%) + Bryan Brattlof 3 (1.8%) + Alexander Sverdlin 2 (1.2%) + Dasnavis Sabiya 2 (1.2%) + Pierre-Clément Tosi 2 (1.2%) + Yasuharu Shibata 2 (1.2%) + Josua Mayer 2 (1.2%) + Masahisa Kojima 2 (1.2%) + Tim Harvey 1 (0.6%) + Simon Glass 1 (0.6%) + Tony Dinh 1 (0.6%) + Judith Mendez 1 (0.6%) + Igor Opaniuk 1 (0.6%) + Roger Quadros 1 (0.6%) + Nishanth Menon 1 (0.6%) + Anand Moon 1 (0.6%) + Sébastien Szymanski 1 (0.6%) + Maksim Kiselev 1 (0.6%) + Ben Dooks 1 (0.6%) + Yang Xiwen 1 (0.6%) + ==================================== ===== + + +.. table:: Developers with the most report credits (total 27) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + E Shattow 4 (14.8%) + Sumit Garg 2 (7.4%) + Jonas Karlman 2 (7.4%) + Laurent Pinchart 2 (7.4%) + Suman Anna 2 (7.4%) + Marek Vasut 1 (3.7%) + Andrew Davis 1 (3.7%) + Heinrich Schuchardt 1 (3.7%) + Tim Harvey 1 (3.7%) + Simon Glass 1 (3.7%) + Jonathan Humphreys 1 (3.7%) + Patrice Chotard 1 (3.7%) + Dhruva Gole 1 (3.7%) + Dan Carpenter 1 (3.7%) + Christophe Leroy 1 (3.7%) + Eugeniu Rosca 1 (3.7%) + Janusz Dziedzic 1 (3.7%) + David Virag 1 (3.7%) + Jan Kiszka 1 (3.7%) + Aniket Limaye 1 (3.7%) + ==================================== ===== + + +.. table:: Developers who gave the most report credits (total 27) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Heinrich Schuchardt 6 (22.2%) + Neha Malcom Francis 3 (11.1%) + Marek Vasut 2 (7.4%) + Caleb Connolly 2 (7.4%) + Tom Rini 2 (7.4%) + Fabio Estevam 2 (7.4%) + Bryan Brattlof 2 (7.4%) + Andrew Davis 1 (3.7%) + Ilias Apalodimas 1 (3.7%) + Quentin Schulz 1 (3.7%) + Yasuharu Shibata 1 (3.7%) + Nishanth Menon 1 (3.7%) + Sam Protsenko 1 (3.7%) + Felipe Balbi 1 (3.7%) + Alexander Gendin 1 (3.7%) + ==================================== ===== + + +.. table:: Top changeset contributors by employer + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 645 (39.7%) + Konsulko Group 324 (20.0%) + Linaro 201 (12.4%) + Texas Instruments 119 (7.3%) + Google LLC 50 (3.1%) + AMD 43 (2.6%) + ST Microelectronics 39 (2.4%) + DENX Software Engineering 34 (2.1%) + Phytec 27 (1.7%) + Renesas Electronics 25 (1.5%) + Toradex 19 (1.2%) + NXP 17 (1.0%) + Edgeble AI Technologies Pvt. Ltd. 14 (0.9%) + ARM 13 (0.8%) + Intel 9 (0.6%) + Amarula Solutions 7 (0.4%) + BayLibre SAS 6 (0.4%) + Socionext Inc. 6 (0.4%) + Collabora Ltd. 5 (0.3%) + Red Hat 4 (0.2%) + linutronix 4 (0.2%) + Rockchip 4 (0.2%) + Weidmüller Interface GmbH & Co. KG 3 (0.2%) + Samsung 2 (0.1%) + Broadcom 1 (0.1%) + Digi International 1 (0.1%) + Marvell 1 (0.1%) + Siemens 1 (0.1%) + ==================================== ===== + + +.. table:: Top lines changed by employer + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Konsulko Group 2187616 (86.6%) + (Unknown) 130949 (5.2%) + Linaro 80577 (3.2%) + Renesas Electronics 52143 (2.1%) + Texas Instruments 41420 (1.6%) + Phytec 8700 (0.3%) + Toradex 5479 (0.2%) + Intel 4682 (0.2%) + Edgeble AI Technologies Pvt. Ltd. 3856 (0.2%) + NXP 3082 (0.1%) + DENX Software Engineering 1283 (0.1%) + Google LLC 1225 (0.0%) + Rockchip 1002 (0.0%) + AMD 863 (0.0%) + ST Microelectronics 724 (0.0%) + Red Hat 597 (0.0%) + ARM 207 (0.0%) + Socionext Inc. 206 (0.0%) + linutronix 65 (0.0%) + Amarula Solutions 46 (0.0%) + Collabora Ltd. 35 (0.0%) + BayLibre SAS 14 (0.0%) + Weidmüller Interface GmbH & Co. KG 13 (0.0%) + Samsung 8 (0.0%) + Marvell 5 (0.0%) + Broadcom 2 (0.0%) + Digi International 2 (0.0%) + Siemens 1 (0.0%) + ==================================== ===== + + +.. table:: Employers with the most signoffs (total 231) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 56 (24.2%) + Linaro 56 (24.2%) + Texas Instruments 33 (14.3%) + BayLibre SAS 19 (8.2%) + AMD 17 (7.4%) + Amarula Solutions 11 (4.8%) + Analog Devices 9 (3.9%) + Samsung 7 (3.0%) + Siemens 6 (2.6%) + DENX Software Engineering 4 (1.7%) + Toradex 3 (1.3%) + Canonical 3 (1.3%) + Phytec 2 (0.9%) + Rockchip 2 (0.9%) + Intel 1 (0.4%) + NXP 1 (0.4%) + ST Microelectronics 1 (0.4%) + ==================================== ===== + + +.. table:: Employers with the most hackers (total 195) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 98 (50.3%) + Texas Instruments 20 (10.3%) + Linaro 10 (5.1%) + AMD 8 (4.1%) + Toradex 8 (4.1%) + Phytec 5 (2.6%) + Intel 5 (2.6%) + DENX Software Engineering 4 (2.1%) + Rockchip 4 (2.1%) + ST Microelectronics 4 (2.1%) + Amarula Solutions 3 (1.5%) + Google LLC 3 (1.5%) + Samsung 2 (1.0%) + NXP 2 (1.0%) + Edgeble AI Technologies Pvt. Ltd. 2 (1.0%) + ARM 2 (1.0%) + Socionext Inc. 2 (1.0%) + linutronix 2 (1.0%) + Collabora Ltd. 2 (1.0%) + BayLibre SAS 1 (0.5%) + Siemens 1 (0.5%) + Konsulko Group 1 (0.5%) + Renesas Electronics 1 (0.5%) + Red Hat 1 (0.5%) + Weidmüller Interface GmbH & Co. KG 1 (0.5%) + Marvell 1 (0.5%) + Broadcom 1 (0.5%) + Digi International 1 (0.5%) + ==================================== ===== + diff --git a/doc/develop/testing.rst b/doc/develop/testing.rst index 5afeb42f696..9114d11ad26 100644 --- a/doc/develop/testing.rst +++ b/doc/develop/testing.rst @@ -69,7 +69,7 @@ build:: ./test/py/test.py --bd sandbox_spl --build -k test_spl -See test/py/README.md for more information about the pytest suite. +See :doc:`py_testing` for more information about the pytest suite. See :doc:`tests_sandbox` for how to run tests directly (not through pytest). @@ -123,7 +123,7 @@ or is covered sparingly. So here are some suggestions: is much easier to add onto a test - writing a new large test can seem daunting to most contributors. -See doc:`tests_writing` for how to write tests. +See :doc:`tests_writing` for how to write tests. Future work diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index 36ac75278fa..88596f312c0 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -72,7 +72,7 @@ bootm command. This feature is available if U-Boot is configured with:: CONFIG_BOOTM_EFI=y -A sample configuration is provided as file doc/uImage.FIT/uefi.its. +A sample configuration is provided in :doc:`../../usage/fit/uefi`. Below you find the output of an example session starting GRUB:: @@ -96,7 +96,7 @@ Below you find the output of an example session starting GRUB:: ## Transferring control to EFI (at address 404000d0) ... Welcome to GRUB! -See doc/uImage.FIT/howto.txt for an introduction to FIT images. +See :doc:`../../usage/fit/howto` for an introduction to FIT images. Configuring UEFI secure boot ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 426f41e1a02..306b05a995e 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -1,18 +1,18 @@ alabaster==0.7.16 -Babel==2.14.0 -certifi==2023.11.17 +Babel==2.15.0 +certifi==2024.6.2 charset-normalizer==3.3.2 docutils==0.20.1 idna==3.7 imagesize==1.4.1 Jinja2==3.1.4 -MarkupSafe==2.1.3 -packaging==23.2 -Pygments==2.17.2 -requests==2.31.0 +MarkupSafe==2.1.5 +packaging==24.1 +Pygments==2.18.0 +requests==2.32.3 six==1.16.0 snowballstemmer==2.2.0 -Sphinx==7.2.6 +Sphinx==7.3.7 sphinx-prompt==1.8.0 sphinx-rtd-theme==2.0.0 sphinxcontrib-applehelp==1.0.8 @@ -22,4 +22,4 @@ sphinxcontrib-jquery==4.1 sphinxcontrib-jsmath==1.0.1 sphinxcontrib-qthelp==1.0.7 sphinxcontrib-serializinghtml==1.1.10 -urllib3==2.1.0 +urllib3==2.2.1 diff --git a/doc/usage/cmd/bootmeth.rst b/doc/usage/cmd/bootmeth.rst index 2903977ee54..bac9fdf85cd 100644 --- a/doc/usage/cmd/bootmeth.rst +++ b/doc/usage/cmd/bootmeth.rst @@ -48,7 +48,7 @@ The format looks like this: ===== === ================== ================================= Order Seq Name Description ===== === ================== ================================= - 0 0 extlinunx Extlinux boot from a block device + 0 0 extlinux Extlinux boot from a block device 1 1 efi EFI boot from an .efi file 2 2 pxe PXE boot from a network device 3 3 sandbox Sandbox boot for testing diff --git a/doc/usage/fit/beaglebone_vboot.rst b/doc/usage/fit/beaglebone_vboot.rst index cd6bb141910..1298ba1ae08 100644 --- a/doc/usage/fit/beaglebone_vboot.rst +++ b/doc/usage/fit/beaglebone_vboot.rst @@ -67,18 +67,20 @@ a. Set up the environment variable to point to your toolchain. You will need export CROSS_COMPILE=arm-linux-gnueabi- -b. Configure and build U-Boot with verified boot enabled:: +b. Configure and build U-Boot with verified boot enabled. Note that we use the +am335x_evm target since it covers all boards based on the AM335x evaluation +board:: export UBOOT=/path/to/u-boot cd $UBOOT # You can add -j10 if you have 10 CPUs to make it faster - make O=b/am335x_boneblack_vboot am335x_boneblack_vboot_config all - export UOUT=$UBOOT/b/am335x_boneblack_vboot + make O=b/am335x_evm am335x_evm_config all + export UOUT=$UBOOT/b/am335x_evm c. You will now have a U-Boot image:: - file b/am335x_boneblack_vboot/u-boot-dtb.img - b/am335x_boneblack_vboot/u-boot-dtb.img: u-boot legacy uImage, + file b/am335x_evm/u-boot-dtb.img + b/am335x_evm/u-boot-dtb.img: u-boot legacy uImage, U-Boot 2014.07-rc2-00065-g2f69f8, Firmware/ARM, Firmware Image (Not compressed), 395375 bytes, Sat May 31 16:19:04 2014, Load Address: 0x80800000, Entry Point: 0x00000000, @@ -466,7 +468,7 @@ the private key that you signed with so that it can verify any kernels that you sign:: cd $UBOOT - make O=b/am335x_boneblack_vboot EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb + make O=b/am335x_evm EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb Here we are overriding the normal device tree file with our one, which contains the public key. @@ -597,14 +599,11 @@ Further Improvements Several of the steps here can be easily automated. In particular it would be capital if signing and packaging a kernel were easy, perhaps a simple make -target in the kernel. +target in the kernel. A starting point for this is the 'make image.fit' target +for ARM64 in Linux from v6.9 onwards. Some mention of how to use multiple .dtb files in a FIT might be useful. -U-Boot's verified boot mechanism has not had a robust and independent security -review. Such a review should look at the implementation and its resistance to -attacks. - Perhaps the verified boot feature could be integrated into the Amstrom distribution. diff --git a/doc/usage/fit/signature.rst b/doc/usage/fit/signature.rst index 03a71b5192d..b868dcbf9fd 100644 --- a/doc/usage/fit/signature.rst +++ b/doc/usage/fit/signature.rst @@ -15,7 +15,7 @@ that it can be verified using a public key later. Provided that the private key is kept secret and the public key is stored in a non-volatile place, any image can be verified in this way. -See verified-boot.txt for more general information on verified boot. +See :doc:`verified-boot` for more general information on verified boot. Concepts diff --git a/doc/usage/fit/source_file_format.rst b/doc/usage/fit/source_file_format.rst index b2b1e42bd73..15990e3ff54 100644 --- a/doc/usage/fit/source_file_format.rst +++ b/doc/usage/fit/source_file_format.rst @@ -192,13 +192,13 @@ type invalid Invalid Image aisimage Davinci AIS image atmelimage ATMEL ROM-Boot Image - copro Coprocessor Image} + copro Coprocessor Image fdt_legacy legacy Image with Flat Device Tree filesystem Filesystem Image firmware Firmware - firmware_ivt Firmware with HABv4 IVT } + firmware_ivt Firmware with HABv4 IVT flat_dt Flat Device Tree - fpga FPGA Image } + fpga FPGA Device Image (bitstream file, vendor specific) gpimage TI Keystone SPL Image imx8image NXP i.MX8 Boot Image imx8mimage NXP i.MX8M Boot Image @@ -207,31 +207,31 @@ type kernel_noload Kernel Image (no loading done) kwbimage Kirkwood Boot Image lpc32xximage LPC32XX Boot Image - mtk_image MediaTek BootROM loadable Image } + mtk_image MediaTek BootROM loadable Image multi Multi-File Image mxsimage Freescale MXS Boot Image omapimage TI OMAP SPL With GP CH pblimage Freescale PBL Boot Image pmmc TI Power Management Micro-Controller Firmware ramdisk RAMDisk Image - rkimage Rockchip Boot Image } - rksd Rockchip SD Boot Image } - rkspi Rockchip SPI Boot Image } + rkimage Rockchip Boot Image + rksd Rockchip SD Boot Image + rkspi Rockchip SPI Boot Image script Script socfpgaimage Altera SoCFPGA CV/AV preloader socfpgaimage_v1 Altera SoCFPGA A10 preloader - spkgimage Renesas SPKG Image } + spkgimage Renesas SPKG Image standalone Standalone Program - stm32image STMicroelectronics STM32 Image } - sunxi_egon Allwinner eGON Boot Image } - sunxi_toc0 Allwinner TOC0 Boot Image } + stm32image STMicroelectronics STM32 Image + sunxi_egon Allwinner eGON Boot Image + sunxi_toc0 Allwinner TOC0 Boot Image tee Trusted Execution Environment Image ublimage Davinci UBL image vybridimage Vybrid Boot Image x86_setup x86 setup.bin - zynqimage Xilinx Zynq Boot Image } - zynqmpbif Xilinx ZynqMP Boot Image (bif) } - zynqmpimage Xilinx ZynqMP Boot Image } + zynqimage Xilinx Zynq Boot Image + zynqmpbif Xilinx ZynqMP Boot Image (bif) + zynqmpimage Xilinx ZynqMP Boot Image ==================== ================== compression @@ -254,9 +254,6 @@ compression zstd zstd compressed ==================== ================== -data-size - size of the data in bytes - Conditionally mandatory property ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -276,6 +273,9 @@ data-position not relative to the loading of the FIT. This is mandatory if external data used with a fixed address. +data-size + Size of the data in bytes. This is mandatory if external data is used. + os OS name, mandatory for types "kernel". Valid OS names are: diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst index 9691904a9d8..05c439e9ac6 100644 --- a/doc/usage/measured_boot.rst +++ b/doc/usage/measured_boot.rst @@ -7,19 +7,46 @@ U-Boot can perform a measured boot, the process of hashing various components of the boot process, extending the results in the TPM and logging the component's measurement in memory for the operating system to consume. +The functionality is available when booting via the EFI subsystem or 'bootm' +command. + +UEFI measured boot +------------------ + +The EFI subsystem implements the `EFI TCG protocol +<https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/>`_ +and the `TCG PC Client Specific Platform Firmware Profile Specification +<https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firmware-profile-specification/>`_ +which defines the binaries to be measured and the corresponding PCRs to be used. + +Requirements +~~~~~~~~~~~~ + +* A hardware TPM 2.0 supported by an enabled U-Boot driver +* CONFIG_EFI_TCG2_PROTOCOL=y +* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y +* optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB + in PCR 1 + +Legacy measured boot +-------------------- + +The commands booti, bootm, and bootz can be used for measured boot +using the legacy entry point of the Linux kernel. + By default, U-Boot will measure the operating system (linux) image, the initrd image, and the "bootargs" environment variable. By enabling -CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image. +CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image in PCR1. The operating system typically would verify that the hashes found in the TPM PCRs match the contents of the event log. This can further be checked against the hash results of previous boots. Requirements ------------- +~~~~~~~~~~~~ -* A hardware TPM 2.0 supported by the U-Boot drivers -* CONFIG_TPM=y +* A hardware TPM 2.0 supported by an enabled U-Boot driver +* CONFIG_TPMv2=y * CONFIG_MEASURED_BOOT=y * Device-tree configuration of the TPM device to specify the memory area for event logging. The TPM device node must either contain a phandle to diff --git a/doc/usage/netconsole.rst b/doc/usage/netconsole.rst index 2aa3b9ccc59..df27b78342f 100644 --- a/doc/usage/netconsole.rst +++ b/doc/usage/netconsole.rst @@ -3,10 +3,10 @@ Network console In U-Boot, we implemented the networked console via the standard "devices" mechanism, which means that you can switch between the -serial and network input/output devices by adjusting the 'stdin' and -'stdout' environment variables. To switch to the networked console, -set either of these variables to "nc". Input and output can be -switched independently. +serial and network input/output devices by adjusting the 'stdin', +'stdout', and 'stderr' environment variables. To switch to the +networked console, set either of these variables to "nc". Input and +output can be switched independently. The default buffer size can be overridden by setting CFG_NETCONSOLE_BUFFER_SIZE. @@ -18,14 +18,18 @@ broadcast address and port 6666 are used. If it is set to an IP address of 0 (or 0.0.0.0) then no messages are sent to the network. The source / listening port can be configured separately by setting the 'ncinport' environment variable and the destination port can be -configured by setting the 'ncoutport' environment variable. +configured by setting the 'ncoutport' environment variable. Note that +you need to set up the network interface (e.g. using DHCP) before it +can be used for network console. -For example, if your server IP is 192.168.1.1, you could use:: +For example, if your server IP is 192.168.1.1, you could use: - => setenv nc 'setenv stdout nc;setenv stdin nc' - => setenv ncip 192.168.1.1 - => saveenv - => run nc +.. prompt:: bash => + + env set nc 'env set stdout nc; env set stderr nc; env set stdin nc' + env set ncip '192.168.1.1' + env save + run nc On the host side, please use this script to access the console @@ -107,3 +111,34 @@ as follows: Note that unlike the U-Boot implementation the Linux netconsole is unidirectional, i. e. you have console output only in Linux. + +Setup via environment +--------------------- + +If persistent environment is enabled in your U-Boot configuration, you +can configure the network console using the environment. For example: + +.. prompt:: bash => + + env set autoload no + env set hostname "u-boot" + env set bootdelay 5 + env set nc 'dhcp; env set stdout nc; env set stderr nc; env set stdin nc' + env set ncip '192.168.1.1' + env set preboot "${preboot}; run nc;" + env save + reset + +``autoload no`` tells the ``dhcp`` command to configure the network +interface without trying to load an image. ``hostname "u-boot"`` sets +the hostname to be sent in DHCP requests, so they are easy to +recognize in the DHCP server log. The command in ``nc`` calls ``dhcp`` +to make sure the network interface is set up before enabling +netconsole. + +Adding ``nc`` to ``preboot`` tells U-Boot to activate netconsole +before trying to find any boot options, so you can interact with it if +desired. + +``env save`` stores the settings persistently, and ``reset`` then +triggers a fresh start that will use the changed settings. diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 1081d61fcf0..1a7be4d9b4d 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -56,7 +56,7 @@ config DM_WARN out - it will do nothing when called. config SPL_DM_WARN - bool "Enable warnings in driver model wuth SPL" + bool "Enable warnings in driver model in SPL" depends on SPL_DM help Enable this to see warnings related to driver model in SPL @@ -113,7 +113,7 @@ config DM_EVENT select EVENT help This enables support for generating events related to driver model - operations, such as prbing or removing a device. Subsystems can + operations, such as probing or removing a device. Subsystems can register a 'spy' function that is called when the event occurs. Such subsystems must select this option. diff --git a/drivers/core/device.c b/drivers/core/device.c index 18e2bd02dd5..779f371b9d5 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -58,7 +58,7 @@ static int device_bind_common(struct udevice *parent, const struct driver *drv, ret = uclass_get(drv->id, &uc); if (ret) { - debug("Missing uclass for driver %s\n", drv->name); + dm_warn("Missing uclass for driver %s\n", drv->name); return ret; } diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 6be8ea0c0a9..9e59968df01 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -15,6 +15,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <dm/device-internal.h> +#include <dm/util.h> DECLARE_GLOBAL_DATA_PTR; @@ -32,19 +33,19 @@ fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index) na = fdt_address_cells(gd->fdt_blob, parent); if (na < 1) { - debug("bad #address-cells\n"); + dm_warn("bad #address-cells\n"); return FDT_ADDR_T_NONE; } ns = fdt_size_cells(gd->fdt_blob, parent); if (ns < 0) { - debug("bad #size-cells\n"); + dm_warn("bad #size-cells\n"); return FDT_ADDR_T_NONE; } reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) { - debug("Req index out of range\n"); + dm_warn("Req index out of range\n"); return FDT_ADDR_T_NONE; } diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 2839a9b7371..bd0ab4f16c9 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -144,7 +144,7 @@ int device_bind_driver_to_node(struct udevice *parent, const char *drv_name, drv = lists_driver_lookup_name(drv_name); if (!drv) { - debug("Cannot find driver '%s'\n", drv_name); + dm_warn("Cannot find driver '%s'\n", drv_name); return -ENOENT; } ret = device_bind_with_driver_data(parent, drv, dev_name, 0 /* data */, @@ -246,9 +246,8 @@ int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp, } if (entry->of_match) - log_debug(" - found match at '%s': '%s' matches '%s'\n", - entry->name, entry->of_match->compatible, - id->compatible); + log_debug(" - found match at driver '%s' for '%s'\n", + entry->name, id->compatible); ret = device_bind_with_driver_data(parent, entry, name, id ? id->data : 0, node, &dev); diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index 41f2e09b9c2..d05be273e7b 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -25,6 +25,7 @@ #include <linux/bug.h> #include <linux/libfdt.h> #include <dm/of_access.h> +#include <dm/util.h> #include <linux/ctype.h> #include <linux/err.h> #include <linux/ioport.h> @@ -489,17 +490,17 @@ int of_read_u8(const struct device_node *np, const char *propname, u8 *outp) { const u8 *val; - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (!np) return -EINVAL; val = of_find_property_value_of_size(np, propname, sizeof(*outp)); if (IS_ERR(val)) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return PTR_ERR(val); } *outp = *val; - debug("%#x (%d)\n", *outp, *outp); + dm_warn("%#x (%d)\n", *outp, *outp); return 0; } @@ -508,17 +509,17 @@ int of_read_u16(const struct device_node *np, const char *propname, u16 *outp) { const __be16 *val; - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (!np) return -EINVAL; val = of_find_property_value_of_size(np, propname, sizeof(*outp)); if (IS_ERR(val)) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return PTR_ERR(val); } *outp = be16_to_cpup(val); - debug("%#x (%d)\n", *outp, *outp); + dm_warn("%#x (%d)\n", *outp, *outp); return 0; } @@ -533,14 +534,14 @@ int of_read_u32_array(const struct device_node *np, const char *propname, { const __be32 *val; - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); val = of_find_property_value_of_size(np, propname, sz * sizeof(*out_values)); if (IS_ERR(val)) return PTR_ERR(val); - debug("size %zd\n", sz); + dm_warn("size %zd\n", sz); while (sz--) *out_values++ = be32_to_cpup(val++); @@ -552,19 +553,19 @@ int of_read_u32_index(const struct device_node *np, const char *propname, { const __be32 *val; - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (!np) return -EINVAL; val = of_find_property_value_of_size(np, propname, sizeof(*outp) * (index + 1)); if (IS_ERR(val)) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return PTR_ERR(val); } *outp = be32_to_cpup(val + index); - debug("%#x (%d)\n", *outp, *outp); + dm_warn("%#x (%d)\n", *outp, *outp); return 0; } @@ -574,20 +575,20 @@ int of_read_u64_index(const struct device_node *np, const char *propname, { const __be64 *val; - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (!np) return -EINVAL; val = of_find_property_value_of_size(np, propname, sizeof(*outp) * (index + 1)); if (IS_ERR(val)) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return PTR_ERR(val); } *outp = be64_to_cpup(val + index); - debug("%#llx (%lld)\n", (unsigned long long)*outp, - (unsigned long long)*outp); + dm_warn("%#llx (%lld)\n", (unsigned long long)*outp, + (unsigned long long)*outp); return 0; } @@ -620,7 +621,7 @@ int of_property_match_string(const struct device_node *np, const char *propname, l = strnlen(p, end - p) + 1; if (p + l > end) return -EILSEQ; - debug("comparing %s with %s\n", string, p); + dm_warn("comparing %s with %s\n", string, p); if (strcmp(string, p) == 0) return i; /* Found it; return index */ } @@ -707,17 +708,17 @@ static int __of_parse_phandle_with_args(const struct device_node *np, if (cells_name || cur_index == index) { node = of_find_node_by_phandle(NULL, phandle); if (!node) { - debug("%s: could not find phandle\n", - np->full_name); + dm_warn("%s: could not find phandle\n", + np->full_name); goto err; } } if (cells_name) { if (of_read_u32(node, cells_name, &count)) { - debug("%s: could not get %s for %s\n", - np->full_name, cells_name, - node->full_name); + dm_warn("%s: could not get %s for %s\n", + np->full_name, cells_name, + node->full_name); goto err; } } else { @@ -729,8 +730,8 @@ static int __of_parse_phandle_with_args(const struct device_node *np, * remaining property data length */ if (list + count > list_end) { - debug("%s: arguments longer than property\n", - np->full_name); + dm_warn("%s: arguments longer than property\n", + np->full_name); goto err; } } @@ -825,8 +826,8 @@ static void of_alias_add(struct alias_prop *ap, struct device_node *np, strncpy(ap->stem, stem, stem_len); ap->stem[stem_len] = 0; list_add_tail(&ap->link, &aliases_lookup); - debug("adding DT alias:%s: stem=%s id=%i node=%s\n", - ap->alias, ap->stem, ap->id, of_node_full_name(np)); + dm_warn("adding DT alias:%s: stem=%s id=%i node=%s\n", + ap->alias, ap->stem, ap->id, of_node_full_name(np)); } int of_alias_scan(void) diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c index d7913ab3d2f..c893447a1b1 100644 --- a/drivers/core/of_addr.c +++ b/drivers/core/of_addr.c @@ -11,6 +11,7 @@ #include <linux/libfdt.h> #include <dm/of_access.h> #include <dm/of_addr.h> +#include <dm/util.h> #include <linux/err.h> #include <linux/ioport.h> #include <linux/printk.h> @@ -26,7 +27,7 @@ static struct of_bus *of_match_bus(struct device_node *np); #ifdef DEBUG static void of_dump_addr(const char *s, const __be32 *addr, int na) { - debug("%s", s); + dm_warn("%s", s); while (na--) pr_cont(" %08x", be32_to_cpu(*(addr++))); pr_cont("\n"); @@ -65,9 +66,9 @@ static u64 of_bus_default_map(__be32 *addr, const __be32 *range, s = of_read_number(range + na + pna, ns); da = of_read_number(addr, na); - debug("default map, cp=%llx, s=%llx, da=%llx\n", - (unsigned long long)cp, (unsigned long long)s, - (unsigned long long)da); + dm_warn("default map, cp=%llx, s=%llx, da=%llx\n", + (unsigned long long)cp, (unsigned long long)s, + (unsigned long long)da); if (da < cp || da >= (cp + s)) return OF_BAD_ADDR; @@ -193,17 +194,17 @@ static int of_translate_one(const struct device_node *parent, ranges = of_get_property(parent, rprop, &rlen); if (ranges == NULL && !of_empty_ranges_quirk(parent) && strcmp(rprop, "dma-ranges")) { - debug("no ranges; cannot translate\n"); + dm_warn("no ranges; cannot translate\n"); return 1; } if (ranges == NULL || rlen == 0) { offset = of_read_number(addr, na); memset(addr, 0, pna * 4); - debug("empty ranges; 1:1 translation\n"); + dm_warn("empty ranges; 1:1 translation\n"); goto finish; } - debug("walking ranges...\n"); + dm_warn("walking ranges...\n"); /* Now walk through the ranges */ rlen /= 4; @@ -214,14 +215,14 @@ static int of_translate_one(const struct device_node *parent, break; } if (offset == OF_BAD_ADDR) { - debug("not found !\n"); + dm_warn("not found !\n"); return 1; } memcpy(addr, ranges + na, 4 * pna); finish: of_dump_addr("parent translation for:", addr, pna); - debug("with offset: %llx\n", (unsigned long long)offset); + dm_warn("with offset: %llx\n", (unsigned long long)offset); /* Translate it into parent bus space */ return pbus->translate(addr, offset, pna); @@ -246,7 +247,7 @@ static u64 __of_translate_address(const struct device_node *dev, int na, ns, pna, pns; u64 result = OF_BAD_ADDR; - debug("** translation for device %s **\n", of_node_full_name(dev)); + dm_warn("** translation for device %s **\n", of_node_full_name(dev)); /* Increase refcount at current level */ (void)of_node_get(dev); @@ -260,13 +261,13 @@ static u64 __of_translate_address(const struct device_node *dev, /* Count address cells & copy address locally */ bus->count_cells(dev, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { - debug("Bad cell count for %s\n", of_node_full_name(dev)); + dm_warn("Bad cell count for %s\n", of_node_full_name(dev)); goto bail; } memcpy(addr, in_addr, na * 4); - debug("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns, - of_node_full_name(parent)); + dm_warn("bus is %s (na=%d, ns=%d) on %s\n", bus->name, na, ns, + of_node_full_name(parent)); of_dump_addr("translating address:", addr, na); /* Translate */ @@ -278,7 +279,7 @@ static u64 __of_translate_address(const struct device_node *dev, /* If root, we have finished */ if (parent == NULL) { - debug("reached root node\n"); + dm_warn("reached root node\n"); result = of_read_number(addr, na); break; } @@ -287,13 +288,13 @@ static u64 __of_translate_address(const struct device_node *dev, pbus = of_match_bus(parent); pbus->count_cells(dev, &pna, &pns); if (!OF_CHECK_COUNTS(pna, pns)) { - debug("Bad cell count for %s\n", - of_node_full_name(dev)); + dm_warn("Bad cell count for %s\n", + of_node_full_name(dev)); break; } - debug("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name, - pna, pns, of_node_full_name(parent)); + dm_warn("parent bus is %s (na=%d, ns=%d) on %s\n", pbus->name, + pna, pns, of_node_full_name(parent)); /* Apply bus translation */ if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop)) @@ -358,8 +359,8 @@ int of_get_dma_range(const struct device_node *dev, phys_addr_t *cpu, } if (!dev || !ranges) { - debug("no dma-ranges found for node %s\n", - of_node_full_name(dev)); + dm_warn("no dma-ranges found for node %s\n", + of_node_full_name(dev)); ret = -ENOENT; goto out; } diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c index a3ebe9e9c24..bfc1e3441b1 100644 --- a/drivers/core/of_extra.c +++ b/drivers/core/of_extra.c @@ -9,6 +9,7 @@ #include <dm/of_access.h> #include <dm/of_extra.h> #include <dm/ofnode.h> +#include <dm/util.h> int ofnode_read_fmap_entry(ofnode node, struct fmap_entry *entry) { @@ -16,13 +17,13 @@ int ofnode_read_fmap_entry(ofnode node, struct fmap_entry *entry) ofnode subnode; if (ofnode_read_u32(node, "image-pos", &entry->offset)) { - debug("Node '%s' has bad/missing 'image-pos' property\n", - ofnode_get_name(node)); + dm_warn("Node '%s' has bad/missing 'image-pos' property\n", + ofnode_get_name(node)); return log_msg_ret("image-pos", -ENOENT); } if (ofnode_read_u32(node, "size", &entry->length)) { - debug("Node '%s' has bad/missing 'size' property\n", - ofnode_get_name(node)); + dm_warn("Node '%s' has bad/missing 'size' property\n", + ofnode_get_name(node)); return log_msg_ret("size", -ENOENT); } entry->used = ofnode_read_s32_default(node, "used", entry->length); @@ -57,17 +58,17 @@ int ofnode_decode_region(ofnode node, const char *prop_name, fdt_addr_t *basep, const fdt_addr_t *cell; int len; - debug("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name); + dm_warn("%s: %s: %s\n", __func__, ofnode_get_name(node), prop_name); cell = ofnode_get_property(node, prop_name, &len); if (!cell || (len < sizeof(fdt_addr_t) * 2)) { - debug("cell=%p, len=%d\n", cell, len); + dm_warn("cell=%p, len=%d\n", cell, len); return -1; } *basep = fdt_addr_to_cpu(*cell); *sizep = fdt_size_to_cpu(cell[1]); - debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep, - (ulong)*sizep); + dm_warn("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep, + (ulong)*sizep); return 0; } @@ -85,7 +86,7 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, if (!ofnode_valid(config_node)) { config_node = ofnode_path("/config"); if (!ofnode_valid(config_node)) { - debug("%s: Cannot find /config node\n", __func__); + dm_warn("%s: Cannot find /config node\n", __func__); return -ENOENT; } } @@ -96,14 +97,14 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, suffix); mem = ofnode_read_string(config_node, prop_name); if (!mem) { - debug("%s: No memory type for '%s', using /memory\n", __func__, - prop_name); + dm_warn("%s: No memory type for '%s', using /memory\n", __func__, + prop_name); mem = "/memory"; } node = ofnode_path(mem); if (!ofnode_valid(node)) { - debug("%s: Failed to find node '%s'\n", __func__, mem); + dm_warn("%s: Failed to find node '%s'\n", __func__, mem); return -ENOENT; } @@ -112,8 +113,8 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, * use the first */ if (ofnode_decode_region(node, "reg", &base, &size)) { - debug("%s: Failed to decode memory region %s\n", __func__, - mem); + dm_warn("%s: Failed to decode memory region %s\n", __func__, + mem); return -EINVAL; } @@ -121,8 +122,8 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, suffix); if (ofnode_decode_region(config_node, prop_name, &offset, &offset_size)) { - debug("%s: Failed to decode memory region '%s'\n", __func__, - prop_name); + dm_warn("%s: Failed to decode memory region '%s'\n", __func__, + prop_name); return -EINVAL; } diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 9a5eaaa4d13..4d563b47a5a 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -16,6 +16,7 @@ #include <dm/of_access.h> #include <dm/of_addr.h> #include <dm/ofnode.h> +#include <dm/util.h> #include <linux/err.h> #include <linux/ioport.h> #include <asm/global_data.h> @@ -314,7 +315,7 @@ int ofnode_read_u8(ofnode node, const char *propname, u8 *outp) int len; assert(ofnode_valid(node)); - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) return of_read_u8(ofnode_to_np(node), propname, outp); @@ -322,11 +323,11 @@ int ofnode_read_u8(ofnode node, const char *propname, u8 *outp) cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname, &len); if (!cell || len < sizeof(*cell)) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return -EINVAL; } *outp = *cell; - debug("%#x (%d)\n", *outp, *outp); + dm_warn("%#x (%u)\n", *outp, *outp); return 0; } @@ -345,7 +346,7 @@ int ofnode_read_u16(ofnode node, const char *propname, u16 *outp) int len; assert(ofnode_valid(node)); - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) return of_read_u16(ofnode_to_np(node), propname, outp); @@ -353,11 +354,11 @@ int ofnode_read_u16(ofnode node, const char *propname, u16 *outp) cell = fdt_getprop(gd->fdt_blob, ofnode_to_offset(node), propname, &len); if (!cell || len < sizeof(*cell)) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return -EINVAL; } *outp = be16_to_cpup(cell); - debug("%#x (%d)\n", *outp, *outp); + dm_warn("%#x (%u)\n", *outp, *outp); return 0; } @@ -390,7 +391,7 @@ int ofnode_read_u32_index(ofnode node, const char *propname, int index, int len; assert(ofnode_valid(node)); - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) return of_read_u32_index(ofnode_to_np(node), propname, index, @@ -399,17 +400,17 @@ int ofnode_read_u32_index(ofnode node, const char *propname, int index, cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node), propname, &len); if (!cell) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return -EINVAL; } if (len < (sizeof(int) * (index + 1))) { - debug("(not large enough)\n"); + dm_warn("(not large enough)\n"); return -EOVERFLOW; } *outp = fdt32_to_cpu(cell[index]); - debug("%#x (%d)\n", *outp, *outp); + dm_warn("%#x (%u)\n", *outp, *outp); return 0; } @@ -429,17 +430,17 @@ int ofnode_read_u64_index(ofnode node, const char *propname, int index, cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node), propname, &len); if (!cell) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return -EINVAL; } if (len < (sizeof(u64) * (index + 1))) { - debug("(not large enough)\n"); + dm_warn("(not large enough)\n"); return -EOVERFLOW; } *outp = fdt64_to_cpu(cell[index]); - debug("%#llx (%lld)\n", *outp, *outp); + dm_warn("%#llx (%llu)\n", *outp, *outp); return 0; } @@ -467,7 +468,7 @@ int ofnode_read_u64(ofnode node, const char *propname, u64 *outp) int len; assert(ofnode_valid(node)); - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) return of_read_u64(ofnode_to_np(node), propname, outp); @@ -475,12 +476,12 @@ int ofnode_read_u64(ofnode node, const char *propname, u64 *outp) cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node), propname, &len); if (!cell || len < sizeof(*cell)) { - debug("(not found)\n"); + dm_warn("(not found)\n"); return -EINVAL; } *outp = fdt64_to_cpu(cell[0]); - debug("%#llx (%lld)\n", (unsigned long long)*outp, - (unsigned long long)*outp); + dm_warn("%#llx (%llu)\n", (unsigned long long)*outp, + (unsigned long long)*outp); return 0; } @@ -498,11 +499,11 @@ bool ofnode_read_bool(ofnode node, const char *propname) bool prop; assert(ofnode_valid(node)); - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); prop = ofnode_has_property(node, propname); - debug("%s\n", prop ? "true" : "false"); + dm_warn("%s\n", prop ? "true" : "false"); return prop ? true : false; } @@ -513,7 +514,7 @@ const void *ofnode_read_prop(ofnode node, const char *propname, int *sizep) int len; assert(ofnode_valid(node)); - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) { struct property *prop = of_find_property( @@ -528,7 +529,7 @@ const void *ofnode_read_prop(ofnode node, const char *propname, int *sizep) propname, &len); } if (!val) { - debug("<not found>\n"); + dm_warn("<not found>\n"); if (sizep) *sizep = -FDT_ERR_NOTFOUND; return NULL; @@ -549,10 +550,10 @@ const char *ofnode_read_string(ofnode node, const char *propname) return NULL; if (strnlen(str, len) >= len) { - debug("<invalid>\n"); + dm_warn("<invalid>\n"); return NULL; } - debug("%s\n", str); + dm_warn("%s\n", str); return str; } @@ -572,7 +573,7 @@ ofnode ofnode_find_subnode(ofnode node, const char *subnode_name) ofnode subnode; assert(ofnode_valid(node)); - debug("%s: %s: ", __func__, subnode_name); + dm_warn("%s: %s: ", __func__, subnode_name); if (ofnode_is_np(node)) { struct device_node *np = ofnode_to_np(node); @@ -587,8 +588,8 @@ ofnode ofnode_find_subnode(ofnode node, const char *subnode_name) ofnode_to_offset(node), subnode_name); subnode = noffset_to_ofnode(node, ooffset); } - debug("%s\n", ofnode_valid(subnode) ? - ofnode_get_name(subnode) : "<none>"); + dm_warn("%s\n", ofnode_valid(subnode) ? + ofnode_get_name(subnode) : "<none>"); return subnode; } @@ -597,7 +598,7 @@ int ofnode_read_u32_array(ofnode node, const char *propname, u32 *out_values, size_t sz) { assert(ofnode_valid(node)); - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); if (ofnode_is_np(node)) { return of_read_u32_array(ofnode_to_np(node), propname, @@ -669,7 +670,7 @@ ofnode ofnode_get_parent(ofnode node) const char *ofnode_get_name(ofnode node) { if (!ofnode_valid(node)) { - debug("%s node not valid\n", __func__); + dm_warn("%s node not valid\n", __func__); return NULL; } @@ -1030,7 +1031,7 @@ ofnode ofnode_get_aliases_node(const char *name) if (!prop) return ofnode_null(); - debug("%s: node_path: %s\n", __func__, prop); + dm_warn("%s: node_path: %s\n", __func__, prop); return ofnode_path(prop); } @@ -1053,8 +1054,8 @@ static int decode_timing_property(ofnode node, const char *name, length = ofnode_read_size(node, name); if (length < 0) { - debug("%s: could not find property %s\n", - ofnode_get_name(node), name); + dm_warn("%s: could not find property %s\n", + ofnode_get_name(node), name); return length; } @@ -1299,7 +1300,7 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, int len; int ret = -ENOENT; - debug("%s: %s: ", __func__, propname); + dm_warn("%s: %s: ", __func__, propname); /* * If we follow the pci bus bindings strictly, we should check @@ -1316,8 +1317,8 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, int i; for (i = 0; i < num; i++) { - debug("pci address #%d: %08lx %08lx %08lx\n", i, - (ulong)fdt32_to_cpu(cell[0]), + dm_warn("pci address #%d: %08lx %08lx %08lx\n", i, + (ulong)fdt32_to_cpu(cell[0]), (ulong)fdt32_to_cpu(cell[1]), (ulong)fdt32_to_cpu(cell[2])); if ((fdt32_to_cpu(*cell) & type) == type) { @@ -1346,7 +1347,7 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, ret = -EINVAL; fail: - debug("(not found)\n"); + dm_warn("(not found)\n"); return ret; } @@ -1630,7 +1631,7 @@ int ofnode_write_string(ofnode node, const char *propname, const char *value) { assert(ofnode_valid(node)); - debug("%s: %s = %s", __func__, propname, value); + dm_warn("%s: %s = %s", __func__, propname, value); return ofnode_write_prop(node, propname, value, strlen(value) + 1, false); @@ -1743,7 +1744,7 @@ int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset) uboot = ofnode_path("/options/u-boot"); if (!ofnode_valid(uboot)) { - debug("%s: Missing /u-boot node\n", __func__); + dm_warn("%s: Missing /u-boot node\n", __func__); return -EINVAL; } @@ -1769,7 +1770,7 @@ int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset, uboot = ofnode_path("/options/u-boot"); if (!ofnode_valid(uboot)) { - debug("%s: Missing /u-boot node\n", __func__); + dm_warn("%s: Missing /u-boot node\n", __func__); return -EINVAL; } @@ -1784,7 +1785,7 @@ int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset, return -EINVAL; if (!bootscr_flash_size) { - debug("bootscr-flash-size is zero. Ignoring properties!\n"); + dm_warn("bootscr-flash-size is zero. Ignoring properties!\n"); *bootscr_flash_offset = 0; return -EINVAL; } @@ -1831,7 +1832,7 @@ phy_interface_t ofnode_read_phy_mode(ofnode node) if (!strcmp(mode, phy_interface_strings[i])) return i; - debug("%s: Invalid PHY interface '%s'\n", __func__, mode); + dm_warn("%s: Invalid PHY interface '%s'\n", __func__, mode); return PHY_INTERFACE_MODE_NA; } diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 7ff7834bdf0..304d5b02bcd 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <dm/of_addr.h> #include <dm/devres.h> +#include <dm/util.h> #include <linux/ioport.h> #include <linux/compat.h> #include <linux/err.h> @@ -139,8 +140,8 @@ static int init_range(ofnode node, struct regmap_range *range, int addr_len, ret = of_address_to_resource(ofnode_to_np(node), index, &r); if (ret) { - debug("%s: Could not read resource of range %d (ret = %d)\n", - ofnode_get_name(node), index, ret); + dm_warn("%s: Could not read resource of range %d (ret = %d)\n", + ofnode_get_name(node), index, ret); return ret; } @@ -154,8 +155,8 @@ static int init_range(ofnode node, struct regmap_range *range, int addr_len, addr_len, size_len, &sz, true); if (range->start == FDT_ADDR_T_NONE) { - debug("%s: Could not read start of range %d\n", - ofnode_get_name(node), index); + dm_warn("%s: Could not read start of range %d\n", + ofnode_get_name(node), index); return -EINVAL; } @@ -173,15 +174,15 @@ int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index) addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); if (addr_len < 0) { - debug("%s: Error while reading the addr length (ret = %d)\n", - ofnode_get_name(node), addr_len); + dm_warn("%s: Error while reading the addr length (ret = %d)\n", + ofnode_get_name(node), addr_len); return addr_len; } size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node)); if (size_len < 0) { - debug("%s: Error while reading the size length: (ret = %d)\n", - ofnode_get_name(node), size_len); + dm_warn("%s: Error while reading the size length: (ret = %d)\n", + ofnode_get_name(node), size_len); return size_len; } @@ -250,36 +251,36 @@ int regmap_init_mem(ofnode node, struct regmap **mapp) addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); if (addr_len < 0) { - debug("%s: Error while reading the addr length (ret = %d)\n", - ofnode_get_name(node), addr_len); + dm_warn("%s: Error while reading the addr length (ret = %d)\n", + ofnode_get_name(node), addr_len); return addr_len; } size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node)); if (size_len < 0) { - debug("%s: Error while reading the size length: (ret = %d)\n", - ofnode_get_name(node), size_len); + dm_warn("%s: Error while reading the size length: (ret = %d)\n", + ofnode_get_name(node), size_len); return size_len; } both_len = addr_len + size_len; if (!both_len) { - debug("%s: Both addr and size length are zero\n", - ofnode_get_name(node)); + dm_warn("%s: Both addr and size length are zero\n", + ofnode_get_name(node)); return -EINVAL; } len = ofnode_read_size(node, "reg"); if (len < 0) { - debug("%s: Error while reading reg size (ret = %d)\n", - ofnode_get_name(node), len); + dm_warn("%s: Error while reading reg size (ret = %d)\n", + ofnode_get_name(node), len); return len; } len /= sizeof(fdt32_t); count = len / both_len; if (!count) { - debug("%s: Not enough data in reg property\n", - ofnode_get_name(node)); + dm_warn("%s: Not enough data in reg property\n", + ofnode_get_name(node)); return -EINVAL; } @@ -424,8 +425,8 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, void *ptr; if (do_range_check() && range_num >= map->range_count) { - debug("%s: range index %d larger than range count\n", - __func__, range_num); + dm_warn("%s: range index %d larger than range count\n", + __func__, range_num); return -ERANGE; } range = &map->ranges[range_num]; @@ -433,7 +434,7 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, offset <<= map->reg_offset_shift; if (do_range_check() && (offset + val_len > range->size || offset + val_len < offset)) { - debug("%s: offset/size combination invalid\n", __func__); + dm_warn("%s: offset/size combination invalid\n", __func__); return -ERANGE; } @@ -455,7 +456,7 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, break; #endif default: - debug("%s: regmap size %zu unknown\n", __func__, val_len); + dm_warn("%s: regmap size %zu unknown\n", __func__, val_len); return -EINVAL; } @@ -564,15 +565,15 @@ int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, void *ptr; if (range_num >= map->range_count) { - debug("%s: range index %d larger than range count\n", - __func__, range_num); + dm_warn("%s: range index %d larger than range count\n", + __func__, range_num); return -ERANGE; } range = &map->ranges[range_num]; offset <<= map->reg_offset_shift; if (offset + val_len > range->size || offset + val_len < offset) { - debug("%s: offset/size combination invalid\n", __func__); + dm_warn("%s: offset/size combination invalid\n", __func__); return -ERANGE; } @@ -594,7 +595,7 @@ int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, break; #endif default: - debug("%s: regmap size %zu unknown\n", __func__, val_len); + dm_warn("%s: regmap size %zu unknown\n", __func__, val_len); return -EINVAL; } @@ -630,8 +631,8 @@ int regmap_write(struct regmap *map, uint offset, uint val) u.v64 = val; break; default: - debug("%s: regmap size %zu unknown\n", __func__, - (size_t)map->width); + dm_warn("%s: regmap size %zu unknown\n", __func__, + (size_t)map->width); return -EINVAL; } diff --git a/drivers/core/root.c b/drivers/core/root.c index 4bfd08f4813..7cf6607a9b7 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -207,7 +207,7 @@ static int dm_scan_fdt_node(struct udevice *parent, ofnode parent_node, err = lists_bind_fdt(parent, node, NULL, NULL, pre_reloc_only); if (err && !ret) { ret = err; - debug("%s: ret=%d\n", node_name, ret); + dm_warn("%s: ret=%d\n", node_name, ret); } } @@ -248,7 +248,7 @@ int dm_extended_scan(bool pre_reloc_only) ret = dm_scan_fdt(pre_reloc_only); if (ret) { - debug("dm_scan_fdt() failed: %d\n", ret); + dm_warn("dm_scan_fdt() failed: %d\n", ret); return ret; } @@ -256,8 +256,8 @@ int dm_extended_scan(bool pre_reloc_only) for (i = 0; i < ARRAY_SIZE(nodes); i++) { ret = dm_scan_fdt_ofnode_path(nodes[i], pre_reloc_only); if (ret) { - debug("dm_scan_fdt() scan for %s failed: %d\n", - nodes[i], ret); + dm_warn("dm_scan_fdt() scan for %s failed: %d\n", + nodes[i], ret); return ret; } } @@ -320,14 +320,14 @@ static int dm_scan(bool pre_reloc_only) ret = dm_scan_plat(pre_reloc_only); if (ret) { - debug("dm_scan_plat() failed: %d\n", ret); + dm_warn("dm_scan_plat() failed: %d\n", ret); return ret; } if (CONFIG_IS_ENABLED(OF_REAL)) { ret = dm_extended_scan(pre_reloc_only); if (ret) { - debug("dm_extended_scan() failed: %d\n", ret); + dm_warn("dm_extended_scan() failed: %d\n", ret); return ret; } } @@ -345,7 +345,7 @@ int dm_init_and_scan(bool pre_reloc_only) ret = dm_init(CONFIG_IS_ENABLED(OF_LIVE)); if (ret) { - debug("dm_init() failed: %d\n", ret); + dm_warn("dm_init() failed: %d\n", ret); return ret; } if (!CONFIG_IS_ENABLED(OF_PLATDATA_INST)) { diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 762536eebc6..7ae0884a75e 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -59,8 +59,8 @@ static int uclass_add(enum uclass_id id, struct uclass **ucp) *ucp = NULL; uc_drv = lists_uclass_lookup(id); if (!uc_drv) { - debug("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n", - id); + dm_warn("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n", + id); /* * Use a strange error to make this case easier to find. When * a uclass is not available it can prevent driver model from diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 0360d9da142..971204758aa 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -68,6 +68,7 @@ config DFU_RAM config DFU_SF bool "SPI flash back end for DFU" + depends on SPI_FLASH || DM_SPI_FLASH help This option enables using DFU to read and write to SPI flash based storage. diff --git a/drivers/mtd/nand/raw/nand_macronix.c b/drivers/mtd/nand/raw/nand_macronix.c index dc972e59092..4c6ddd92331 100644 --- a/drivers/mtd/nand/raw/nand_macronix.c +++ b/drivers/mtd/nand/raw/nand_macronix.c @@ -16,13 +16,183 @@ * GNU General Public License for more details. */ +#include <dm/device_compat.h> #include <linux/mtd/rawnand.h> +#define ONFI_FEATURE_ADDR_30LFXG18AC_OTP 0x90 +#define MACRONIX_30LFXG18AC_OTP_START_PAGE 2 +#define MACRONIX_30LFXG18AC_OTP_PAGES 30 +#define MACRONIX_30LFXG18AC_OTP_PAGE_SIZE 2112 +#define MACRONIX_30LFXG18AC_OTP_SIZE_BYTES \ + (MACRONIX_30LFXG18AC_OTP_PAGES * \ + MACRONIX_30LFXG18AC_OTP_PAGE_SIZE) + +#define MACRONIX_30LFXG18AC_OTP_EN BIT(0) + +static int macronix_30lfxg18ac_get_otp_info(struct mtd_info *mtd, size_t len, + size_t *retlen, + struct otp_info *buf) +{ + if (len < sizeof(*buf)) + return -EINVAL; + + /* Always report that OTP is unlocked. Reason is that this + * type of flash chip doesn't provide way to check that OTP + * is locked or not: subfeature parameter is implemented as + * volatile register. Technically OTP region could be locked + * and become readonly, but as there is no way to check it, + * don't allow to lock it ('_lock_user_prot_reg' callback + * always returns -EOPNOTSUPP) and thus we report that OTP + * is unlocked. + */ + buf->locked = 0; + buf->start = 0; + buf->length = MACRONIX_30LFXG18AC_OTP_SIZE_BYTES; + + *retlen = sizeof(*buf); + + return 0; +} + +static int macronix_30lfxg18ac_otp_enable(struct nand_chip *nand) +{ + u8 feature_buf[ONFI_SUBFEATURE_PARAM_LEN] = { 0 }; + struct mtd_info *mtd; + + mtd = nand_to_mtd(nand); + feature_buf[0] = MACRONIX_30LFXG18AC_OTP_EN; + + return nand->onfi_set_features(mtd, nand, ONFI_FEATURE_ADDR_30LFXG18AC_OTP, feature_buf); +} + +static int macronix_30lfxg18ac_otp_disable(struct nand_chip *nand) +{ + u8 feature_buf[ONFI_SUBFEATURE_PARAM_LEN] = { 0 }; + struct mtd_info *mtd; + + mtd = nand_to_mtd(nand); + return nand->onfi_set_features(mtd, nand, ONFI_FEATURE_ADDR_30LFXG18AC_OTP, feature_buf); +} + +static int __macronix_30lfxg18ac_rw_otp(struct mtd_info *mtd, + loff_t offs_in_flash, + size_t len, size_t *retlen, + u_char *buf, bool write) +{ + struct nand_chip *nand; + size_t bytes_handled; + off_t offs_in_page; + u64 page; + int ret; + + nand = mtd_to_nand(mtd); + nand->select_chip(mtd, 0); + + ret = macronix_30lfxg18ac_otp_enable(nand); + if (ret) + goto out_otp; + + page = offs_in_flash; + /* 'page' will be result of division. */ + offs_in_page = do_div(page, MACRONIX_30LFXG18AC_OTP_PAGE_SIZE); + bytes_handled = 0; + + while (bytes_handled < len && + page < MACRONIX_30LFXG18AC_OTP_PAGES) { + size_t bytes_to_handle; + u64 phys_page = page + MACRONIX_30LFXG18AC_OTP_START_PAGE; + + bytes_to_handle = min_t(size_t, len - bytes_handled, + MACRONIX_30LFXG18AC_OTP_PAGE_SIZE - + offs_in_page); + + if (write) + ret = nand_prog_page_op(nand, phys_page, offs_in_page, + &buf[bytes_handled], bytes_to_handle); + else + ret = nand_read_page_op(nand, phys_page, offs_in_page, + &buf[bytes_handled], bytes_to_handle); + if (ret) + goto out_otp; + + bytes_handled += bytes_to_handle; + offs_in_page = 0; + page++; + } + + *retlen = bytes_handled; + +out_otp: + if (ret) + dev_err(mtd->dev, "failed to perform OTP IO: %i\n", ret); + + ret = macronix_30lfxg18ac_otp_disable(nand); + if (ret) + dev_err(mtd->dev, "failed to leave OTP mode after %s\n", + write ? "write" : "read"); + + nand->select_chip(mtd, -1); + + return ret; +} + +static int macronix_30lfxg18ac_write_otp(struct mtd_info *mtd, loff_t to, + size_t len, size_t *rlen, + u_char *buf) +{ + return __macronix_30lfxg18ac_rw_otp(mtd, to, len, rlen, (u_char *)buf, + true); +} + +static int macronix_30lfxg18ac_read_otp(struct mtd_info *mtd, loff_t from, + size_t len, size_t *rlen, + u_char *buf) +{ + return __macronix_30lfxg18ac_rw_otp(mtd, from, len, rlen, buf, false); +} + +static int macronix_30lfxg18ac_lock_otp(struct mtd_info *mtd, loff_t from, + size_t len) +{ + /* See comment in 'macronix_30lfxg18ac_get_otp_info()'. */ + return -EOPNOTSUPP; +} + +static void macronix_nand_setup_otp(struct nand_chip *chip) +{ + static const char * const supported_otp_models[] = { + "MX30LF1G18AC", + "MX30LF2G18AC", + "MX30LF4G18AC", + }; + int i; + + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) + return; + + for (i = 0; i < ARRAY_SIZE(supported_otp_models); i++) { + if (!strcmp(chip->onfi_params.model, supported_otp_models[i])) { + struct mtd_info *mtd; + + mtd = nand_to_mtd(chip); + mtd->_get_user_prot_info = macronix_30lfxg18ac_get_otp_info; + mtd->_read_user_prot_reg = macronix_30lfxg18ac_read_otp; + mtd->_write_user_prot_reg = macronix_30lfxg18ac_write_otp; + mtd->_lock_user_prot_reg = macronix_30lfxg18ac_lock_otp; + return; + } + } +} + static int macronix_nand_init(struct nand_chip *chip) { if (nand_is_slc(chip)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + macronix_nand_setup_otp(chip); + return 0; } diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 17c5601bead..b78b4e60238 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -799,6 +799,11 @@ static void prepare_start_command(struct pxa3xx_nand_info *info, int command) info->ecc_err_cnt = 0; info->ndcb3 = 0; info->need_wait = 0; + /* + * Reset max_bitflips to zero. Once command is complete, + * max_bitflips for this READ is returned in ecc.read_page() + */ + info->max_bitflips = 0; switch (command) { case NAND_CMD_READ0: diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 5783d36c048..fd446d6efb3 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -9,6 +9,7 @@ config UBI_SILENCE_MSG config MTD_UBI bool "Enable UBI - Unsorted block images" + depends on MTD select RBTREE select MTD_PARTITIONS help diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c index 158102363e9..b06cb5c6d51 100644 --- a/drivers/nvme/nvme_show.c +++ b/drivers/nvme/nvme_show.c @@ -67,7 +67,7 @@ static void print_formats(struct nvme_id_ns *id, struct nvme_ns *ns) printf("Blk device %d: LBA Format Support:\n", ns->devnum); for (i = 0; i < id->nlbaf; i++) { - printf("\tLBA Foramt %d Support: ", i); + printf("\tLBA Format %d Support: ", i); if (i == ns->flbas) printf("(current)\n"); else diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c index 92c285103c4..140e936b47a 100644 --- a/drivers/phy/meson-gxl-usb2.c +++ b/drivers/phy/meson-gxl-usb2.c @@ -19,8 +19,6 @@ #include <linux/printk.h> #include <linux/usb/otg.h> -#include <asm/arch/usb-gx.h> - #include <linux/bitops.h> #include <linux/compat.h> @@ -121,33 +119,40 @@ static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv) udelay(RESET_COMPLETE_TIME); } -void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode) +static int phy_meson_gxl_usb2_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct udevice *dev = phy->dev; struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); uint val; + if (submode) + return -EOPNOTSUPP; + regmap_read(priv->regmap, U2P_R0, &val); switch (mode) { - case USB_DR_MODE_UNKNOWN: - case USB_DR_MODE_HOST: - case USB_DR_MODE_OTG: + case PHY_MODE_USB_DEVICE: + val &= ~U2P_R0_DM_PULLDOWN; + val &= ~U2P_R0_DP_PULLDOWN; + val |= U2P_R0_ID_PULLUP; + break; + + case PHY_MODE_USB_HOST: + case PHY_MODE_USB_OTG: val |= U2P_R0_DM_PULLDOWN; val |= U2P_R0_DP_PULLDOWN; val &= ~U2P_R0_ID_PULLUP; break; - case USB_DR_MODE_PERIPHERAL: - val &= ~U2P_R0_DM_PULLDOWN; - val &= ~U2P_R0_DP_PULLDOWN; - val |= U2P_R0_ID_PULLUP; - break; + default: + return -EINVAL; } regmap_write(priv->regmap, U2P_R0, val); phy_meson_gxl_usb2_reset(priv); + + return 0; } static int phy_meson_gxl_usb2_power_on(struct phy *phy) @@ -161,7 +166,7 @@ static int phy_meson_gxl_usb2_power_on(struct phy *phy) val &= ~U2P_R0_POWER_ON_RESET; regmap_write(priv->regmap, U2P_R0, val); - phy_meson_gxl_usb2_set_mode(phy, USB_DR_MODE_HOST); + phy_meson_gxl_usb2_set_mode(phy, PHY_MODE_USB_HOST, 0); return 0; } @@ -183,6 +188,7 @@ static int phy_meson_gxl_usb2_power_off(struct phy *phy) struct phy_ops meson_gxl_usb2_phy_ops = { .power_on = phy_meson_gxl_usb2_power_on, .power_off = phy_meson_gxl_usb2_power_off, + .set_mode = phy_meson_gxl_usb2_set_mode, }; int meson_gxl_usb2_phy_probe(struct udevice *dev) diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c index 52c726cf038..15ebd574ef1 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c @@ -179,7 +179,7 @@ static const struct dm_gpio_ops meson_axg_gpio_ops = { .direction_output = meson_gpio_direction_output, }; -const struct driver meson_axg_gpio_driver = { +U_BOOT_DRIVER(meson_axg_gpio) = { .name = "meson-axg-gpio", .id = UCLASS_GPIO, .probe = meson_gpio_probe, diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index 94e09cd3f8a..ed3f92b2d75 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -939,7 +939,7 @@ struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_axg_periphs_groups), .num_funcs = ARRAY_SIZE(meson_axg_periphs_functions), .num_banks = ARRAY_SIZE(meson_axg_periphs_banks), - .gpio_driver = &meson_axg_gpio_driver, + .gpio_driver = DM_DRIVER_REF(meson_axg_gpio), .pmx_data = &meson_axg_periphs_pmx_banks_data, }; @@ -953,7 +953,7 @@ struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_axg_aobus_groups), .num_funcs = ARRAY_SIZE(meson_axg_aobus_functions), .num_banks = ARRAY_SIZE(meson_axg_aobus_banks), - .gpio_driver = &meson_axg_gpio_driver, + .gpio_driver = DM_DRIVER_REF(meson_axg_gpio), .pmx_data = &meson_axg_aobus_pmx_banks_data, }; diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.h b/drivers/pinctrl/meson/pinctrl-meson-axg.h index c8d2b3af036..a6581bab500 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.h +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.h @@ -61,6 +61,6 @@ struct meson_pmx_axg_data { } extern const struct pinctrl_ops meson_axg_pinctrl_ops; -extern const struct driver meson_axg_gpio_driver; +extern U_BOOT_DRIVER(meson_axg_gpio); #endif /* __PINCTRL_MESON_AXG_H__ */ diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 24f47f82558..67114df6824 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -1253,7 +1253,7 @@ static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_g12a_periphs_groups), .num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions), .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks), - .gpio_driver = &meson_axg_gpio_driver, + .gpio_driver = DM_DRIVER_REF(meson_axg_gpio), .pmx_data = &meson_g12a_periphs_pmx_banks_data, }; @@ -1267,7 +1267,7 @@ static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_g12a_aobus_groups), .num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions), .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks), - .gpio_driver = &meson_axg_gpio_driver, + .gpio_driver = DM_DRIVER_REF(meson_axg_gpio), .pmx_data = &meson_g12a_aobus_pmx_banks_data, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 3e74e2f1489..d449d07d32e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -13,10 +13,10 @@ #include <linux/libfdt.h> #include "pinctrl-rockchip.h" +#include <dt-bindings/pinctrl/rockchip.h> #define MAX_ROCKCHIP_PINS_ENTRIES 30 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 -#define RK_FUNC_GPIO 0 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) { @@ -131,8 +131,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) return RK_FUNC_GPIO; - regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) - ? priv->regmap_pmu : priv->regmap_base; + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) + regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; + else + regmap = priv->regmap_base; /* get basic quadrupel of mux registers and the correct reg inside */ mux_type = bank->iomux[iomux_num].type; @@ -142,6 +146,28 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588)) { + if (bank->bank_num == 0) { + if (pin >= RK_PB4 && pin <= RK_PD7) { + u32 reg0 = 0; + + reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ + ret = regmap_read(regmap, reg0, &val); + if (ret) + return ret; + + ret = ((val >> bit) & mask); + if (ret != 8) + return ret; + + reg = reg + 0x8000; /* BUS_IOC_BASE */ + regmap = priv->regmap_base; + } + } else if (bank->bank_num > 0) { + reg += 0x8000; /* BUS_IOC_BASE */ + } + } + ret = regmap_read(regmap, reg, &val); if (ret) return ret; @@ -171,7 +197,7 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, } if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { - if (mux != IOMUX_GPIO_ONLY) { + if (mux != RK_FUNC_GPIO) { debug("pin %d only supports a gpio mux\n", pin); return -ENOTSUPP; } @@ -531,12 +557,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d /* preset iomux offset value, set new start value */ if (iom->offset >= 0) { - if (iom->type & IOMUX_SOURCE_PMU) + if ((iom->type & IOMUX_SOURCE_PMU) || + (iom->type & IOMUX_L_SOURCE_PMU)) pmu_offs = iom->offset; else grf_offs = iom->offset; } else { /* set current iomux offset */ - iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? + iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || + (iom->type & IOMUX_L_SOURCE_PMU)) ? pmu_offs : grf_offs; } diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 66fd531da04..88a8525b3c4 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -517,7 +517,7 @@ int regulators_enable_boot_on(bool verbose) dev; uclass_next_device(&dev)) { ret = regulator_autoset(dev); - if (ret == -EMEDIUMTYPE) { + if (ret == -EMEDIUMTYPE || ret == -EALREADY) { ret = 0; continue; } diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index bf3af781527..34e61511d88 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -519,7 +519,7 @@ static int _buck_get_enable(struct udevice *pmic, int buck) if (ret < 0) return ret; - return ret & mask ? true : false; + return (ret & mask) ? true : false; } static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) @@ -584,7 +584,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic, int buck) val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; break; case RK806_ID: { @@ -607,7 +607,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic, int buck) val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1); if (val < 0) return val; - ret = val & mask ? 0 : 1; + ret = (val & mask) ? 0 : 1; break; case RK809_ID: case RK817_ID: @@ -619,7 +619,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic, int buck) val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; break; default: ret = -EINVAL; @@ -722,7 +722,7 @@ static int _ldo_get_enable(struct udevice *pmic, int ldo) if (ret < 0) return ret; - return ret & mask ? true : false; + return (ret & mask) ? true : false; } static int _nldo_get_enable(struct udevice *pmic, int nldo) @@ -979,7 +979,7 @@ static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; break; case RK808_ID: case RK818_ID: @@ -987,7 +987,7 @@ static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2); if (val < 0) return val; - ret = val & mask ? 0 : 1; + ret = (val & mask) ? 0 : 1; break; case RK809_ID: case RK817_ID: @@ -996,13 +996,13 @@ static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; } else { mask = 1 << ldo; val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1)); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; } break; } @@ -1133,14 +1133,14 @@ static int buck_get_enable(struct udevice *dev) return _buck_get_enable(dev->parent, buck); } -static int _ldo_get_value(struct udevice *dev, const struct rk8xx_reg_info *info) +static int _ldo_get_value(struct udevice *pmic, const struct rk8xx_reg_info *info) { int mask = info->vsel_mask; int ret, val; if (info->vsel_reg == NA) return -ENOSYS; - ret = pmic_reg_read(dev->parent, info->vsel_reg); + ret = pmic_reg_read(pmic, info->vsel_reg); if (ret < 0) return ret; val = ret & mask; @@ -1153,7 +1153,7 @@ static int ldo_get_value(struct udevice *dev) int ldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); - return _ldo_get_value(dev, info); + return _ldo_get_value(dev->parent, info); } static int nldo_get_value(struct udevice *dev) @@ -1161,7 +1161,7 @@ static int nldo_get_value(struct udevice *dev) int nldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, 0); - return _ldo_get_value(dev, info); + return _ldo_get_value(dev->parent, info); } static int pldo_get_value(struct udevice *dev) @@ -1169,10 +1169,10 @@ static int pldo_get_value(struct udevice *dev) int pldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, 0); - return _ldo_get_value(dev, info); + return _ldo_get_value(dev->parent, info); } -static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt) +static int _ldo_set_value(struct udevice *pmic, const struct rk8xx_reg_info *info, int uvolt) { int mask = info->vsel_mask; int val; @@ -1188,7 +1188,7 @@ static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n", __func__, uvolt, info->vsel_reg, mask, val); - return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); + return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); } static int ldo_set_value(struct udevice *dev, int uvolt) @@ -1196,7 +1196,7 @@ static int ldo_set_value(struct udevice *dev, int uvolt) int ldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); - return _ldo_set_value(dev, info, uvolt); + return _ldo_set_value(dev->parent, info, uvolt); } static int nldo_set_value(struct udevice *dev, int uvolt) @@ -1204,7 +1204,7 @@ static int nldo_set_value(struct udevice *dev, int uvolt) int nldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, uvolt); - return _ldo_set_value(dev, info, uvolt); + return _ldo_set_value(dev->parent, info, uvolt); } static int pldo_set_value(struct udevice *dev, int uvolt) @@ -1212,10 +1212,10 @@ static int pldo_set_value(struct udevice *dev, int uvolt) int pldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, uvolt); - return _ldo_set_value(dev, info, uvolt); + return _ldo_set_value(dev->parent, info, uvolt); } -static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt) +static int _ldo_set_suspend_value(struct udevice *pmic, const struct rk8xx_reg_info *info, int uvolt) { int mask = info->vsel_mask; int val; @@ -1231,7 +1231,7 @@ static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_in debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n", __func__, uvolt, info->vsel_sleep_reg, mask, val); - return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); + return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); } static int ldo_set_suspend_value(struct udevice *dev, int uvolt) @@ -1258,7 +1258,7 @@ static int pldo_set_suspend_value(struct udevice *dev, int uvolt) return _ldo_set_suspend_value(dev->parent, info, uvolt); } -static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info) +static int _ldo_get_suspend_value(struct udevice *pmic, const struct rk8xx_reg_info *info) { int mask = info->vsel_mask; int val, ret; @@ -1266,7 +1266,7 @@ static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_in if (info->vsel_sleep_reg == NA) return -ENOSYS; - ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); + ret = pmic_reg_read(pmic, info->vsel_sleep_reg); if (ret < 0) return ret; @@ -1437,7 +1437,7 @@ static int switch_get_enable(struct udevice *dev) if (ret < 0) return ret; - return ret & mask ? true : false; + return (ret & mask) ? true : false; } static int switch_set_suspend_value(struct udevice *dev, int uvolt) @@ -1492,21 +1492,21 @@ static int switch_get_suspend_enable(struct udevice *dev) val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); if (val < 0) return val; - ret = val & mask ? 0 : 1; + ret = (val & mask) ? 0 : 1; break; case RK809_ID: mask = 1 << (sw + 6); val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0)); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; break; case RK818_ID: mask = 1 << 6; val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); if (val < 0) return val; - ret = val & mask ? 0 : 1; + ret = (val & mask) ? 0 : 1; break; } diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 21e4f637bb1..41d15996e5b 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -270,7 +270,7 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) return 0; } -int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode) +static int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode) { struct dwc3_meson_g12a *priv = dev_get_plat(dev); diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index 3e693c5ff31..5fb9b477ada 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -26,7 +26,6 @@ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/compat.h> -#include <asm/arch/usb-gx.h> /* USB Glue Control Registers */ @@ -158,9 +157,9 @@ static int dwc3_meson_gxl_usb2_init(struct dwc3_meson_gxl *priv) if (!priv->phys[i].dev) continue; - phy_meson_gxl_usb2_set_mode(&priv->phys[i], - (i == USB2_OTG_PHY) ? USB_DR_MODE_PERIPHERAL - : USB_DR_MODE_HOST); + generic_phy_set_mode(&priv->phys[i], + (i == USB2_OTG_PHY) ? PHY_MODE_USB_DEVICE + : PHY_MODE_USB_HOST, 0); } return 0; @@ -193,7 +192,7 @@ static int dwc3_meson_gxl_usb_init(struct dwc3_meson_gxl *priv) return 0; } -int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode) +static int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode) { struct dwc3_meson_gxl *priv = dev_get_plat(dev); @@ -224,7 +223,9 @@ int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode) #endif priv->otg_phy_mode = mode; - phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY], mode); + generic_phy_set_mode(&priv->phys[USB2_OTG_PHY], + mode == USB_DR_MODE_PERIPHERAL ? PHY_MODE_USB_DEVICE + : PHY_MODE_USB_HOST, 0); dwc3_meson_gxl_usb2_set_mode(priv, mode); @@ -361,8 +362,9 @@ static int dwc3_meson_gxl_probe(struct udevice *dev) } if (priv->phys[USB2_OTG_PHY].dev) - phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY], - priv->otg_phy_mode); + generic_phy_set_mode(&priv->phys[USB2_OTG_PHY], + priv->otg_phy_mode == USB_DR_MODE_PERIPHERAL ? PHY_MODE_USB_DEVICE + : PHY_MODE_USB_HOST, 0); dwc3_meson_gxl_usb2_set_mode(priv, priv->otg_phy_mode); diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 117d38a0340..24f516a131b 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -60,7 +60,7 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, dep = dwc->eps[epnum]; if (dep->flags & DWC3_EP_BUSY) { - dev_vdbg(dwc->dev, "%s still busy", dep->name); + dev_vdbg(dwc->dev, "%s still busy\n", dep->name); return 0; } @@ -237,9 +237,9 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, goto out; } - dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'", - request, dep->name, request->length, - dwc3_ep0_state_string(dwc->ep0state)); + dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s\n'", + request, dep->name, request->length, + dwc3_ep0_state_string(dwc->ep0state)); ret = __dwc3_gadget_ep0_queue(dep, req); @@ -696,35 +696,35 @@ static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) switch (ctrl->bRequest) { case USB_REQ_GET_STATUS: - dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS"); + dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); ret = dwc3_ep0_handle_status(dwc, ctrl); break; case USB_REQ_CLEAR_FEATURE: - dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE"); + dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); break; case USB_REQ_SET_FEATURE: - dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE"); + dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); break; case USB_REQ_SET_ADDRESS: - dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS"); + dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); ret = dwc3_ep0_set_address(dwc, ctrl); break; case USB_REQ_SET_CONFIGURATION: - dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION"); + dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); ret = dwc3_ep0_set_config(dwc, ctrl); break; case USB_REQ_SET_SEL: - dev_vdbg(dwc->dev, "USB_REQ_SET_SEL"); + dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n"); ret = dwc3_ep0_set_sel(dwc, ctrl); break; case USB_REQ_SET_ISOCH_DELAY: - dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY"); + dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n"); ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); break; default: - dev_vdbg(dwc->dev, "Forwarding to gadget driver"); + dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); ret = dwc3_ep0_delegate_req(dwc, ctrl); break; } @@ -910,17 +910,17 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, switch (dwc->ep0state) { case EP0_SETUP_PHASE: - dev_vdbg(dwc->dev, "Setup Phase"); + dev_vdbg(dwc->dev, "Setup Phase\n"); dwc3_ep0_inspect_setup(dwc, event); break; case EP0_DATA_PHASE: - dev_vdbg(dwc->dev, "Data Phase"); + dev_vdbg(dwc->dev, "Data Phase\n"); dwc3_ep0_complete_data(dwc, event); break; case EP0_STATUS_PHASE: - dev_vdbg(dwc->dev, "Status Phase"); + dev_vdbg(dwc->dev, "Status Phase\n"); dwc3_ep0_complete_status(dwc, event); break; default: @@ -1046,7 +1046,7 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc, switch (event->status) { case DEPEVT_STATUS_CONTROL_DATA: - dev_vdbg(dwc->dev, "Control Data"); + dev_vdbg(dwc->dev, "Control Data\n"); /* * We already have a DATA transfer in the controller's cache, @@ -1060,7 +1060,7 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc, if (dwc->ep0_expect_in != event->endpoint_number) { struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; - dev_vdbg(dwc->dev, "Wrong direction for Data phase"); + dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); dwc3_ep0_end_control_data(dwc, dep); dwc3_ep0_stall_and_restart(dwc); return; @@ -1072,13 +1072,13 @@ static void dwc3_ep0_xfernotready(struct dwc3 *dwc, if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) return; - dev_vdbg(dwc->dev, "Control Status"); + dev_vdbg(dwc->dev, "Control Status\n"); dwc->ep0state = EP0_STATUS_PHASE; if (dwc->delayed_status) { WARN_ON_ONCE(event->endpoint_number != 1); - dev_vdbg(dwc->dev, "Delayed Status"); + dev_vdbg(dwc->dev, "Delayed Status\n"); return; } @@ -1091,10 +1091,10 @@ void dwc3_ep0_interrupt(struct dwc3 *dwc, { u8 epnum = event->endpoint_number; - dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'", - dwc3_ep_event_string(event->endpoint_event), - epnum >> 1, (epnum & 1) ? "in" : "out", - dwc3_ep0_state_string(dwc->ep0state)); + dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", + dwc3_ep_event_string(event->endpoint_event), + epnum >> 1, (epnum & 1) ? "in" : "out", + dwc3_ep0_state_string(dwc->ep0state)); switch (event->endpoint_event) { case DWC3_DEPEVT_XFERCOMPLETE: diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index fab32575647..92c7c6d08b7 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -248,7 +248,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, list_del(&req->list); req->trb = NULL; - if (req->request.length) + if (req->request.dma && req->request.length) dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length); if (req->request.status == -EINPROGRESS) @@ -256,7 +256,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, if (dwc->ep0_bounced && dep->number == 0) dwc->ep0_bounced = false; - else + else if (req->request.dma) usb_gadget_unmap_request(&dwc->gadget, &req->request, req->direction); diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index cd3a07e4c37..bfec303e7af 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -387,7 +387,7 @@ int usb_init(void) /* if we were not able to find at least one working bus, bail out */ if (controllers_initialized == 0) - printf("No working controllers found\n"); + printf("No USB controllers found\n"); return usb_started ? 0 : -ENOENT; } diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index 4691612eda3..3998ffc2c81 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -640,7 +640,11 @@ static int read_and_truncate_page(struct btrfs_path *path, extent_type = btrfs_file_extent_type(leaf, fi); if (extent_type == BTRFS_FILE_EXTENT_INLINE) { ret = btrfs_read_extent_inline(path, fi, buf); - memcpy(dest, buf + page_off, min(page_len, ret)); + if (ret < 0) { + free(buf); + return ret; + } + memcpy(dest, buf + page_off, min3(page_len, ret, len)); free(buf); return len; } @@ -652,7 +656,7 @@ static int read_and_truncate_page(struct btrfs_path *path, free(buf); return ret; } - memcpy(dest, buf + page_off, page_len); + memcpy(dest, buf + page_off, min(page_len, len)); free(buf); return len; } diff --git a/fs/ubifs/ubifs-media.h b/fs/ubifs/ubifs-media.h index 2b5b26a01b0..299d80f928c 100644 --- a/fs/ubifs/ubifs-media.h +++ b/fs/ubifs/ubifs-media.h @@ -320,12 +320,14 @@ enum { * UBIFS_COMPR_NONE: no compression * UBIFS_COMPR_LZO: LZO compression * UBIFS_COMPR_ZLIB: ZLIB compression + * UBIFS_COMPR_ZSTD: ZSTD compression * UBIFS_COMPR_TYPES_CNT: count of supported compression types */ enum { UBIFS_COMPR_NONE, UBIFS_COMPR_LZO, UBIFS_COMPR_ZLIB, + UBIFS_COMPR_ZSTD, UBIFS_COMPR_TYPES_CNT, }; diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 75de01e95f7..f0ea7e5c168 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -26,6 +26,11 @@ #include <linux/err.h> #include <linux/lzo.h> +#if IS_ENABLED(CONFIG_ZSTD) +#include <linux/zstd.h> +#include <abuf.h> +#endif + DECLARE_GLOBAL_DATA_PTR; /* compress.c */ @@ -41,6 +46,25 @@ static int gzip_decompress(const unsigned char *in, size_t in_len, (unsigned long *)out_len, 0, 0); } +#if IS_ENABLED(CONFIG_ZSTD) +static int zstd_decompress_wrapper(const unsigned char *in, size_t in_len, + unsigned char *out, size_t *out_len) +{ + struct abuf abuf_in, abuf_out; + int ret; + + abuf_init_set(&abuf_in, (void *)in, in_len); + abuf_init_set(&abuf_out, (void *)out, *out_len); + + ret = zstd_decompress(&abuf_in, &abuf_out); + if (ret < 0) + return ret; + + *out_len = ret; + return 0; +} +#endif + /* Fake description object for the "none" compressor */ static struct ubifs_compressor none_compr = { .compr_type = UBIFS_COMPR_NONE, @@ -70,8 +94,21 @@ static struct ubifs_compressor zlib_compr = { .decompress = gzip_decompress, }; +#if IS_ENABLED(CONFIG_ZSTD) +static struct ubifs_compressor zstd_compr = { + .compr_type = UBIFS_COMPR_ZSTD, +#ifndef __UBOOT__ + .comp_mutex = &zstd_enc_mutex, + .decomp_mutex = &zstd_dec_mutex, +#endif + .name = "zstd", + .capi_name = "zstd", + .decompress = zstd_decompress_wrapper, +}; +#endif + /* All UBIFS compressors */ -struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT]; +struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT] = {NULL}; #ifdef __UBOOT__ @@ -165,8 +202,14 @@ int ubifs_decompress(const struct ubifs_info *c, const void *in_buf, compr = ubifs_compressors[compr_type]; + if (unlikely(!compr)) { + ubifs_err(c, "compression type %d is not compiled in", compr_type); + return -EINVAL; + } + if (unlikely(!compr->capi_name)) { - ubifs_err(c, "%s compression is not compiled in", compr->name); + ubifs_err(c, "%s compression is not compiled in", + compr->name ? compr->name : "unknown"); return -EINVAL; } @@ -231,6 +274,12 @@ int __init ubifs_compressors_init(void) if (err) return err; +#if IS_ENABLED(CONFIG_ZSTD) + err = compr_init(&zstd_compr); + if (err) + return err; +#endif + err = compr_init(&none_compr); if (err) return err; diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index fcc3c6e14ca..aa336d63e3a 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -196,10 +196,6 @@ struct global_data { */ struct udevice *dm_root; /** - * @dm_root_f: pre-relocation root instance - */ - struct udevice *dm_root_f; - /** * @uclass_root_s: * head of core tree when uclasses are not in read-only memory. * diff --git a/include/bootflow.h b/include/bootflow.h index 080ee850122..6affc5e1a4f 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -63,7 +63,8 @@ enum bootflow_flags_t { * * @bm_node: Points to siblings in the same bootdev * @glob_node: Points to siblings in the global list (all bootdev) - * @dev: Bootdev device which produced this bootflow + * @dev: Bootdev device which produced this bootflow, NULL for flows created by + * BOOTMETHF_GLOBAL bootmeths * @blk: Block device which contains this bootflow, NULL if this is a network * device or sandbox 'host' device * @part: Partition number (0 for whole device) diff --git a/include/bootmeth.h b/include/bootmeth.h index cd9517321c0..4d8ca48efd4 100644 --- a/include/bootmeth.h +++ b/include/bootmeth.h @@ -42,7 +42,7 @@ struct bootmeth_ops { /** * get_state_desc() - get detailed state information * - * Prodecues a textual description of the state of the bootmeth. This + * Produces a textual description of the state of the boot method. This * can include newline characters if it extends to multiple lines. It * must be a nul-terminated string. * @@ -140,7 +140,7 @@ struct bootmeth_ops { * @dev: Bootmethod device to boot * @bflow: Bootflow to boot * Return: does not return on success, since it should boot the - * Operating Systemn. Returns -EFAULT if that fails, -ENOTSUPP if + * operating system. Returns -EFAULT if that fails, -ENOTSUPP if * trying method resulted in finding out that is not actually * supported for this boot and should not be tried again unless * something changes, other -ve on other error @@ -153,7 +153,7 @@ struct bootmeth_ops { /** * bootmeth_get_state_desc() - get detailed state information * - * Prodecues a textual description of the state of the bootmeth. This + * Produces a textual description of the state of the boot method. This * can include newline characters if it extends to multiple lines. It * must be a nul-terminated string. * @@ -246,7 +246,7 @@ int bootmeth_read_file(struct udevice *dev, struct bootflow *bflow, * @dev: Bootmethod device to use * @bflow: Bootflow to read * Return: does not return on success, since it should boot the - * Operating Systemn. Returns -EFAULT if that fails, other -ve on + * operating system. Returns -EFAULT if that fails, other -ve on * other error */ int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow); @@ -257,7 +257,7 @@ int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow); * @dev: Bootmethod device to boot * @bflow: Bootflow to boot * Return: does not return on success, since it should boot the - * Operating Systemn. Returns -EFAULT if that fails, other -ve on + * operating system. Returns -EFAULT if that fails, other -ve on * other error */ int bootmeth_boot(struct udevice *dev, struct bootflow *bflow); @@ -266,7 +266,7 @@ int bootmeth_boot(struct udevice *dev, struct bootflow *bflow); * bootmeth_setup_iter_order() - Set up the ordering of bootmeths to scan * * This sets up the ordering information in @iter, based on the selected - * ordering of the bootmethds in bootstd_priv->bootmeth_order. If there is no + * ordering of the boot methods in bootstd_priv->bootmeth_order. If there is no * ordering there, then all bootmethods are added * * @iter: Iterator to update with the order diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 046d5685d04..66816618b0c 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -23,6 +23,7 @@ func(MMC, mmc, 2) \ func(USB, usb, 0) \ func(USB, usb, 1) \ + func(NVME, nvme, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 47413ecd7fb..81144300885 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -17,6 +17,7 @@ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(USB, usb, 0) \ + func(NVME, nvme, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h deleted file mode 100644 index d382fc71aa8..00000000000 --- a/include/dt-bindings/clock/imx5-clock.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX5_H -#define __DT_BINDINGS_CLOCK_IMX5_H - -#define IMX5_CLK_DUMMY 0 -#define IMX5_CLK_CKIL 1 -#define IMX5_CLK_OSC 2 -#define IMX5_CLK_CKIH1 3 -#define IMX5_CLK_CKIH2 4 -#define IMX5_CLK_AHB 5 -#define IMX5_CLK_IPG 6 -#define IMX5_CLK_AXI_A 7 -#define IMX5_CLK_AXI_B 8 -#define IMX5_CLK_UART_PRED 9 -#define IMX5_CLK_UART_ROOT 10 -#define IMX5_CLK_ESDHC_A_PRED 11 -#define IMX5_CLK_ESDHC_B_PRED 12 -#define IMX5_CLK_ESDHC_C_SEL 13 -#define IMX5_CLK_ESDHC_D_SEL 14 -#define IMX5_CLK_EMI_SEL 15 -#define IMX5_CLK_EMI_SLOW_PODF 16 -#define IMX5_CLK_NFC_PODF 17 -#define IMX5_CLK_ECSPI_PRED 18 -#define IMX5_CLK_ECSPI_PODF 19 -#define IMX5_CLK_USBOH3_PRED 20 -#define IMX5_CLK_USBOH3_PODF 21 -#define IMX5_CLK_USB_PHY_PRED 22 -#define IMX5_CLK_USB_PHY_PODF 23 -#define IMX5_CLK_CPU_PODF 24 -#define IMX5_CLK_DI_PRED 25 -#define IMX5_CLK_TVE_SEL 27 -#define IMX5_CLK_UART1_IPG_GATE 28 -#define IMX5_CLK_UART1_PER_GATE 29 -#define IMX5_CLK_UART2_IPG_GATE 30 -#define IMX5_CLK_UART2_PER_GATE 31 -#define IMX5_CLK_UART3_IPG_GATE 32 -#define IMX5_CLK_UART3_PER_GATE 33 -#define IMX5_CLK_I2C1_GATE 34 -#define IMX5_CLK_I2C2_GATE 35 -#define IMX5_CLK_GPT_IPG_GATE 36 -#define IMX5_CLK_PWM1_IPG_GATE 37 -#define IMX5_CLK_PWM1_HF_GATE 38 -#define IMX5_CLK_PWM2_IPG_GATE 39 -#define IMX5_CLK_PWM2_HF_GATE 40 -#define IMX5_CLK_GPT_HF_GATE 41 -#define IMX5_CLK_FEC_GATE 42 -#define IMX5_CLK_USBOH3_PER_GATE 43 -#define IMX5_CLK_ESDHC1_IPG_GATE 44 -#define IMX5_CLK_ESDHC2_IPG_GATE 45 -#define IMX5_CLK_ESDHC3_IPG_GATE 46 -#define IMX5_CLK_ESDHC4_IPG_GATE 47 -#define IMX5_CLK_SSI1_IPG_GATE 48 -#define IMX5_CLK_SSI2_IPG_GATE 49 -#define IMX5_CLK_SSI3_IPG_GATE 50 -#define IMX5_CLK_ECSPI1_IPG_GATE 51 -#define IMX5_CLK_ECSPI1_PER_GATE 52 -#define IMX5_CLK_ECSPI2_IPG_GATE 53 -#define IMX5_CLK_ECSPI2_PER_GATE 54 -#define IMX5_CLK_CSPI_IPG_GATE 55 -#define IMX5_CLK_SDMA_GATE 56 -#define IMX5_CLK_EMI_SLOW_GATE 57 -#define IMX5_CLK_IPU_SEL 58 -#define IMX5_CLK_IPU_GATE 59 -#define IMX5_CLK_NFC_GATE 60 -#define IMX5_CLK_IPU_DI1_GATE 61 -#define IMX5_CLK_VPU_SEL 62 -#define IMX5_CLK_VPU_GATE 63 -#define IMX5_CLK_VPU_REFERENCE_GATE 64 -#define IMX5_CLK_UART4_IPG_GATE 65 -#define IMX5_CLK_UART4_PER_GATE 66 -#define IMX5_CLK_UART5_IPG_GATE 67 -#define IMX5_CLK_UART5_PER_GATE 68 -#define IMX5_CLK_TVE_GATE 69 -#define IMX5_CLK_TVE_PRED 70 -#define IMX5_CLK_ESDHC1_PER_GATE 71 -#define IMX5_CLK_ESDHC2_PER_GATE 72 -#define IMX5_CLK_ESDHC3_PER_GATE 73 -#define IMX5_CLK_ESDHC4_PER_GATE 74 -#define IMX5_CLK_USB_PHY_GATE 75 -#define IMX5_CLK_HSI2C_GATE 76 -#define IMX5_CLK_MIPI_HSC1_GATE 77 -#define IMX5_CLK_MIPI_HSC2_GATE 78 -#define IMX5_CLK_MIPI_ESC_GATE 79 -#define IMX5_CLK_MIPI_HSP_GATE 80 -#define IMX5_CLK_LDB_DI1_DIV_3_5 81 -#define IMX5_CLK_LDB_DI1_DIV 82 -#define IMX5_CLK_LDB_DI0_DIV_3_5 83 -#define IMX5_CLK_LDB_DI0_DIV 84 -#define IMX5_CLK_LDB_DI1_GATE 85 -#define IMX5_CLK_CAN2_SERIAL_GATE 86 -#define IMX5_CLK_CAN2_IPG_GATE 87 -#define IMX5_CLK_I2C3_GATE 88 -#define IMX5_CLK_LP_APM 89 -#define IMX5_CLK_PERIPH_APM 90 -#define IMX5_CLK_MAIN_BUS 91 -#define IMX5_CLK_AHB_MAX 92 -#define IMX5_CLK_AIPS_TZ1 93 -#define IMX5_CLK_AIPS_TZ2 94 -#define IMX5_CLK_TMAX1 95 -#define IMX5_CLK_TMAX2 96 -#define IMX5_CLK_TMAX3 97 -#define IMX5_CLK_SPBA 98 -#define IMX5_CLK_UART_SEL 99 -#define IMX5_CLK_ESDHC_A_SEL 100 -#define IMX5_CLK_ESDHC_B_SEL 101 -#define IMX5_CLK_ESDHC_A_PODF 102 -#define IMX5_CLK_ESDHC_B_PODF 103 -#define IMX5_CLK_ECSPI_SEL 104 -#define IMX5_CLK_USBOH3_SEL 105 -#define IMX5_CLK_USB_PHY_SEL 106 -#define IMX5_CLK_IIM_GATE 107 -#define IMX5_CLK_USBOH3_GATE 108 -#define IMX5_CLK_EMI_FAST_GATE 109 -#define IMX5_CLK_IPU_DI0_GATE 110 -#define IMX5_CLK_GPC_DVFS 111 -#define IMX5_CLK_PLL1_SW 112 -#define IMX5_CLK_PLL2_SW 113 -#define IMX5_CLK_PLL3_SW 114 -#define IMX5_CLK_IPU_DI0_SEL 115 -#define IMX5_CLK_IPU_DI1_SEL 116 -#define IMX5_CLK_TVE_EXT_SEL 117 -#define IMX5_CLK_MX51_MIPI 118 -#define IMX5_CLK_PLL4_SW 119 -#define IMX5_CLK_LDB_DI1_SEL 120 -#define IMX5_CLK_DI_PLL4_PODF 121 -#define IMX5_CLK_LDB_DI0_SEL 122 -#define IMX5_CLK_LDB_DI0_GATE 123 -#define IMX5_CLK_USB_PHY1_GATE 124 -#define IMX5_CLK_USB_PHY2_GATE 125 -#define IMX5_CLK_PER_LP_APM 126 -#define IMX5_CLK_PER_PRED1 127 -#define IMX5_CLK_PER_PRED2 128 -#define IMX5_CLK_PER_PODF 129 -#define IMX5_CLK_PER_ROOT 130 -#define IMX5_CLK_SSI_APM 131 -#define IMX5_CLK_SSI1_ROOT_SEL 132 -#define IMX5_CLK_SSI2_ROOT_SEL 133 -#define IMX5_CLK_SSI3_ROOT_SEL 134 -#define IMX5_CLK_SSI_EXT1_SEL 135 -#define IMX5_CLK_SSI_EXT2_SEL 136 -#define IMX5_CLK_SSI_EXT1_COM_SEL 137 -#define IMX5_CLK_SSI_EXT2_COM_SEL 138 -#define IMX5_CLK_SSI1_ROOT_PRED 139 -#define IMX5_CLK_SSI1_ROOT_PODF 140 -#define IMX5_CLK_SSI2_ROOT_PRED 141 -#define IMX5_CLK_SSI2_ROOT_PODF 142 -#define IMX5_CLK_SSI_EXT1_PRED 143 -#define IMX5_CLK_SSI_EXT1_PODF 144 -#define IMX5_CLK_SSI_EXT2_PRED 145 -#define IMX5_CLK_SSI_EXT2_PODF 146 -#define IMX5_CLK_SSI1_ROOT_GATE 147 -#define IMX5_CLK_SSI2_ROOT_GATE 148 -#define IMX5_CLK_SSI3_ROOT_GATE 149 -#define IMX5_CLK_SSI_EXT1_GATE 150 -#define IMX5_CLK_SSI_EXT2_GATE 151 -#define IMX5_CLK_EPIT1_IPG_GATE 152 -#define IMX5_CLK_EPIT1_HF_GATE 153 -#define IMX5_CLK_EPIT2_IPG_GATE 154 -#define IMX5_CLK_EPIT2_HF_GATE 155 -#define IMX5_CLK_CAN_SEL 156 -#define IMX5_CLK_CAN1_SERIAL_GATE 157 -#define IMX5_CLK_CAN1_IPG_GATE 158 -#define IMX5_CLK_OWIRE_GATE 159 -#define IMX5_CLK_GPU3D_SEL 160 -#define IMX5_CLK_GPU2D_SEL 161 -#define IMX5_CLK_GPU3D_GATE 162 -#define IMX5_CLK_GPU2D_GATE 163 -#define IMX5_CLK_GARB_GATE 164 -#define IMX5_CLK_CKO1_SEL 165 -#define IMX5_CLK_CKO1_PODF 166 -#define IMX5_CLK_CKO1 167 -#define IMX5_CLK_CKO2_SEL 168 -#define IMX5_CLK_CKO2_PODF 169 -#define IMX5_CLK_CKO2 170 -#define IMX5_CLK_SRTC_GATE 171 -#define IMX5_CLK_PATA_GATE 172 -#define IMX5_CLK_SATA_GATE 173 -#define IMX5_CLK_SPDIF_XTAL_SEL 174 -#define IMX5_CLK_SPDIF0_SEL 175 -#define IMX5_CLK_SPDIF1_SEL 176 -#define IMX5_CLK_SPDIF0_PRED 177 -#define IMX5_CLK_SPDIF0_PODF 178 -#define IMX5_CLK_SPDIF1_PRED 179 -#define IMX5_CLK_SPDIF1_PODF 180 -#define IMX5_CLK_SPDIF0_COM_SEL 181 -#define IMX5_CLK_SPDIF1_COM_SEL 182 -#define IMX5_CLK_SPDIF0_GATE 183 -#define IMX5_CLK_SPDIF1_GATE 184 -#define IMX5_CLK_SPDIF_IPG_GATE 185 -#define IMX5_CLK_OCRAM 186 -#define IMX5_CLK_SAHARA_IPG_GATE 187 -#define IMX5_CLK_SATA_REF 188 -#define IMX5_CLK_STEP_SEL 189 -#define IMX5_CLK_CPU_PODF_SEL 190 -#define IMX5_CLK_ARM 191 -#define IMX5_CLK_FIRI_PRED 192 -#define IMX5_CLK_FIRI_SEL 193 -#define IMX5_CLK_FIRI_PODF 194 -#define IMX5_CLK_FIRI_SERIAL_GATE 195 -#define IMX5_CLK_FIRI_IPG_GATE 196 -#define IMX5_CLK_CSI0_MCLK1_PRED 197 -#define IMX5_CLK_CSI0_MCLK1_SEL 198 -#define IMX5_CLK_CSI0_MCLK1_PODF 199 -#define IMX5_CLK_CSI0_MCLK1_GATE 200 -#define IMX5_CLK_IEEE1588_PRED 201 -#define IMX5_CLK_IEEE1588_SEL 202 -#define IMX5_CLK_IEEE1588_PODF 203 -#define IMX5_CLK_IEEE1588_GATE 204 -#define IMX5_CLK_END 205 - -#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h deleted file mode 100644 index e20c43cc36f..00000000000 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ /dev/null @@ -1,278 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H -#define __DT_BINDINGS_CLOCK_IMX6QDL_H - -#define IMX6QDL_CLK_DUMMY 0 -#define IMX6QDL_CLK_CKIL 1 -#define IMX6QDL_CLK_CKIH 2 -#define IMX6QDL_CLK_OSC 3 -#define IMX6QDL_CLK_PLL2_PFD0_352M 4 -#define IMX6QDL_CLK_PLL2_PFD1_594M 5 -#define IMX6QDL_CLK_PLL2_PFD2_396M 6 -#define IMX6QDL_CLK_PLL3_PFD0_720M 7 -#define IMX6QDL_CLK_PLL3_PFD1_540M 8 -#define IMX6QDL_CLK_PLL3_PFD2_508M 9 -#define IMX6QDL_CLK_PLL3_PFD3_454M 10 -#define IMX6QDL_CLK_PLL2_198M 11 -#define IMX6QDL_CLK_PLL3_120M 12 -#define IMX6QDL_CLK_PLL3_80M 13 -#define IMX6QDL_CLK_PLL3_60M 14 -#define IMX6QDL_CLK_TWD 15 -#define IMX6QDL_CLK_STEP 16 -#define IMX6QDL_CLK_PLL1_SW 17 -#define IMX6QDL_CLK_PERIPH_PRE 18 -#define IMX6QDL_CLK_PERIPH2_PRE 19 -#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 -#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 -#define IMX6QDL_CLK_AXI_SEL 22 -#define IMX6QDL_CLK_ESAI_SEL 23 -#define IMX6QDL_CLK_ASRC_SEL 24 -#define IMX6QDL_CLK_SPDIF_SEL 25 -#define IMX6QDL_CLK_GPU2D_AXI 26 -#define IMX6QDL_CLK_GPU3D_AXI 27 -#define IMX6QDL_CLK_GPU2D_CORE_SEL 28 -#define IMX6QDL_CLK_GPU3D_CORE_SEL 29 -#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 -#define IMX6QDL_CLK_IPU1_SEL 31 -#define IMX6QDL_CLK_IPU2_SEL 32 -#define IMX6QDL_CLK_LDB_DI0_SEL 33 -#define IMX6QDL_CLK_LDB_DI1_SEL 34 -#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 -#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 -#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 -#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 -#define IMX6QDL_CLK_IPU1_DI0_SEL 39 -#define IMX6QDL_CLK_IPU1_DI1_SEL 40 -#define IMX6QDL_CLK_IPU2_DI0_SEL 41 -#define IMX6QDL_CLK_IPU2_DI1_SEL 42 -#define IMX6QDL_CLK_HSI_TX_SEL 43 -#define IMX6QDL_CLK_PCIE_AXI_SEL 44 -#define IMX6QDL_CLK_SSI1_SEL 45 -#define IMX6QDL_CLK_SSI2_SEL 46 -#define IMX6QDL_CLK_SSI3_SEL 47 -#define IMX6QDL_CLK_USDHC1_SEL 48 -#define IMX6QDL_CLK_USDHC2_SEL 49 -#define IMX6QDL_CLK_USDHC3_SEL 50 -#define IMX6QDL_CLK_USDHC4_SEL 51 -#define IMX6QDL_CLK_ENFC_SEL 52 -#define IMX6QDL_CLK_EIM_SEL 53 -#define IMX6QDL_CLK_EIM_SLOW_SEL 54 -#define IMX6QDL_CLK_VDO_AXI_SEL 55 -#define IMX6QDL_CLK_VPU_AXI_SEL 56 -#define IMX6QDL_CLK_CKO1_SEL 57 -#define IMX6QDL_CLK_PERIPH 58 -#define IMX6QDL_CLK_PERIPH2 59 -#define IMX6QDL_CLK_PERIPH_CLK2 60 -#define IMX6QDL_CLK_PERIPH2_CLK2 61 -#define IMX6QDL_CLK_IPG 62 -#define IMX6QDL_CLK_IPG_PER 63 -#define IMX6QDL_CLK_ESAI_PRED 64 -#define IMX6QDL_CLK_ESAI_PODF 65 -#define IMX6QDL_CLK_ASRC_PRED 66 -#define IMX6QDL_CLK_ASRC_PODF 67 -#define IMX6QDL_CLK_SPDIF_PRED 68 -#define IMX6QDL_CLK_SPDIF_PODF 69 -#define IMX6QDL_CLK_CAN_ROOT 70 -#define IMX6QDL_CLK_ECSPI_ROOT 71 -#define IMX6QDL_CLK_GPU2D_CORE_PODF 72 -#define IMX6QDL_CLK_GPU3D_CORE_PODF 73 -#define IMX6QDL_CLK_GPU3D_SHADER 74 -#define IMX6QDL_CLK_IPU1_PODF 75 -#define IMX6QDL_CLK_IPU2_PODF 76 -#define IMX6QDL_CLK_LDB_DI0_PODF 77 -#define IMX6QDL_CLK_LDB_DI1_PODF 78 -#define IMX6QDL_CLK_IPU1_DI0_PRE 79 -#define IMX6QDL_CLK_IPU1_DI1_PRE 80 -#define IMX6QDL_CLK_IPU2_DI0_PRE 81 -#define IMX6QDL_CLK_IPU2_DI1_PRE 82 -#define IMX6QDL_CLK_HSI_TX_PODF 83 -#define IMX6QDL_CLK_SSI1_PRED 84 -#define IMX6QDL_CLK_SSI1_PODF 85 -#define IMX6QDL_CLK_SSI2_PRED 86 -#define IMX6QDL_CLK_SSI2_PODF 87 -#define IMX6QDL_CLK_SSI3_PRED 88 -#define IMX6QDL_CLK_SSI3_PODF 89 -#define IMX6QDL_CLK_UART_SERIAL_PODF 90 -#define IMX6QDL_CLK_USDHC1_PODF 91 -#define IMX6QDL_CLK_USDHC2_PODF 92 -#define IMX6QDL_CLK_USDHC3_PODF 93 -#define IMX6QDL_CLK_USDHC4_PODF 94 -#define IMX6QDL_CLK_ENFC_PRED 95 -#define IMX6QDL_CLK_ENFC_PODF 96 -#define IMX6QDL_CLK_EIM_PODF 97 -#define IMX6QDL_CLK_EIM_SLOW_PODF 98 -#define IMX6QDL_CLK_VPU_AXI_PODF 99 -#define IMX6QDL_CLK_CKO1_PODF 100 -#define IMX6QDL_CLK_AXI 101 -#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 -#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 -#define IMX6QDL_CLK_ARM 104 -#define IMX6QDL_CLK_AHB 105 -#define IMX6QDL_CLK_APBH_DMA 106 -#define IMX6QDL_CLK_ASRC 107 -#define IMX6QDL_CLK_CAN1_IPG 108 -#define IMX6QDL_CLK_CAN1_SERIAL 109 -#define IMX6QDL_CLK_CAN2_IPG 110 -#define IMX6QDL_CLK_CAN2_SERIAL 111 -#define IMX6QDL_CLK_ECSPI1 112 -#define IMX6QDL_CLK_ECSPI2 113 -#define IMX6QDL_CLK_ECSPI3 114 -#define IMX6QDL_CLK_ECSPI4 115 -#define IMX6Q_CLK_ECSPI5 116 -#define IMX6DL_CLK_I2C4 116 -#define IMX6QDL_CLK_ENET 117 -#define IMX6QDL_CLK_ESAI_EXTAL 118 -#define IMX6QDL_CLK_GPT_IPG 119 -#define IMX6QDL_CLK_GPT_IPG_PER 120 -#define IMX6QDL_CLK_GPU2D_CORE 121 -#define IMX6QDL_CLK_GPU3D_CORE 122 -#define IMX6QDL_CLK_HDMI_IAHB 123 -#define IMX6QDL_CLK_HDMI_ISFR 124 -#define IMX6QDL_CLK_I2C1 125 -#define IMX6QDL_CLK_I2C2 126 -#define IMX6QDL_CLK_I2C3 127 -#define IMX6QDL_CLK_IIM 128 -#define IMX6QDL_CLK_ENFC 129 -#define IMX6QDL_CLK_IPU1 130 -#define IMX6QDL_CLK_IPU1_DI0 131 -#define IMX6QDL_CLK_IPU1_DI1 132 -#define IMX6QDL_CLK_IPU2 133 -#define IMX6QDL_CLK_IPU2_DI0 134 -#define IMX6QDL_CLK_LDB_DI0 135 -#define IMX6QDL_CLK_LDB_DI1 136 -#define IMX6QDL_CLK_IPU2_DI1 137 -#define IMX6QDL_CLK_HSI_TX 138 -#define IMX6QDL_CLK_MLB 139 -#define IMX6QDL_CLK_MMDC_CH0_AXI 140 -#define IMX6QDL_CLK_MMDC_CH1_AXI 141 -#define IMX6QDL_CLK_OCRAM 142 -#define IMX6QDL_CLK_OPENVG_AXI 143 -#define IMX6QDL_CLK_PCIE_AXI 144 -#define IMX6QDL_CLK_PWM1 145 -#define IMX6QDL_CLK_PWM2 146 -#define IMX6QDL_CLK_PWM3 147 -#define IMX6QDL_CLK_PWM4 148 -#define IMX6QDL_CLK_PER1_BCH 149 -#define IMX6QDL_CLK_GPMI_BCH_APB 150 -#define IMX6QDL_CLK_GPMI_BCH 151 -#define IMX6QDL_CLK_GPMI_IO 152 -#define IMX6QDL_CLK_GPMI_APB 153 -#define IMX6QDL_CLK_SATA 154 -#define IMX6QDL_CLK_SDMA 155 -#define IMX6QDL_CLK_SPBA 156 -#define IMX6QDL_CLK_SSI1 157 -#define IMX6QDL_CLK_SSI2 158 -#define IMX6QDL_CLK_SSI3 159 -#define IMX6QDL_CLK_UART_IPG 160 -#define IMX6QDL_CLK_UART_SERIAL 161 -#define IMX6QDL_CLK_USBOH3 162 -#define IMX6QDL_CLK_USDHC1 163 -#define IMX6QDL_CLK_USDHC2 164 -#define IMX6QDL_CLK_USDHC3 165 -#define IMX6QDL_CLK_USDHC4 166 -#define IMX6QDL_CLK_VDO_AXI 167 -#define IMX6QDL_CLK_VPU_AXI 168 -#define IMX6QDL_CLK_CKO1 169 -#define IMX6QDL_CLK_PLL1_SYS 170 -#define IMX6QDL_CLK_PLL2_BUS 171 -#define IMX6QDL_CLK_PLL3_USB_OTG 172 -#define IMX6QDL_CLK_PLL4_AUDIO 173 -#define IMX6QDL_CLK_PLL5_VIDEO 174 -#define IMX6QDL_CLK_PLL8_MLB 175 -#define IMX6QDL_CLK_PLL7_USB_HOST 176 -#define IMX6QDL_CLK_PLL6_ENET 177 -#define IMX6QDL_CLK_SSI1_IPG 178 -#define IMX6QDL_CLK_SSI2_IPG 179 -#define IMX6QDL_CLK_SSI3_IPG 180 -#define IMX6QDL_CLK_ROM 181 -#define IMX6QDL_CLK_USBPHY1 182 -#define IMX6QDL_CLK_USBPHY2 183 -#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 -#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 -#define IMX6QDL_CLK_SATA_REF 186 -#define IMX6QDL_CLK_SATA_REF_100M 187 -#define IMX6QDL_CLK_PCIE_REF 188 -#define IMX6QDL_CLK_PCIE_REF_125M 189 -#define IMX6QDL_CLK_ENET_REF 190 -#define IMX6QDL_CLK_USBPHY1_GATE 191 -#define IMX6QDL_CLK_USBPHY2_GATE 192 -#define IMX6QDL_CLK_PLL4_POST_DIV 193 -#define IMX6QDL_CLK_PLL5_POST_DIV 194 -#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 -#define IMX6QDL_CLK_EIM_SLOW 196 -#define IMX6QDL_CLK_SPDIF 197 -#define IMX6QDL_CLK_CKO2_SEL 198 -#define IMX6QDL_CLK_CKO2_PODF 199 -#define IMX6QDL_CLK_CKO2 200 -#define IMX6QDL_CLK_CKO 201 -#define IMX6QDL_CLK_VDOA 202 -#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 -#define IMX6QDL_CLK_LVDS1_SEL 204 -#define IMX6QDL_CLK_LVDS2_SEL 205 -#define IMX6QDL_CLK_LVDS1_GATE 206 -#define IMX6QDL_CLK_LVDS2_GATE 207 -#define IMX6QDL_CLK_ESAI_IPG 208 -#define IMX6QDL_CLK_ESAI_MEM 209 -#define IMX6QDL_CLK_ASRC_IPG 210 -#define IMX6QDL_CLK_ASRC_MEM 211 -#define IMX6QDL_CLK_LVDS1_IN 212 -#define IMX6QDL_CLK_LVDS2_IN 213 -#define IMX6QDL_CLK_ANACLK1 214 -#define IMX6QDL_CLK_ANACLK2 215 -#define IMX6QDL_PLL1_BYPASS_SRC 216 -#define IMX6QDL_PLL2_BYPASS_SRC 217 -#define IMX6QDL_PLL3_BYPASS_SRC 218 -#define IMX6QDL_PLL4_BYPASS_SRC 219 -#define IMX6QDL_PLL5_BYPASS_SRC 220 -#define IMX6QDL_PLL6_BYPASS_SRC 221 -#define IMX6QDL_PLL7_BYPASS_SRC 222 -#define IMX6QDL_CLK_PLL1 223 -#define IMX6QDL_CLK_PLL2 224 -#define IMX6QDL_CLK_PLL3 225 -#define IMX6QDL_CLK_PLL4 226 -#define IMX6QDL_CLK_PLL5 227 -#define IMX6QDL_CLK_PLL6 228 -#define IMX6QDL_CLK_PLL7 229 -#define IMX6QDL_PLL1_BYPASS 230 -#define IMX6QDL_PLL2_BYPASS 231 -#define IMX6QDL_PLL3_BYPASS 232 -#define IMX6QDL_PLL4_BYPASS 233 -#define IMX6QDL_PLL5_BYPASS 234 -#define IMX6QDL_PLL6_BYPASS 235 -#define IMX6QDL_PLL7_BYPASS 236 -#define IMX6QDL_CLK_GPT_3M 237 -#define IMX6QDL_CLK_VIDEO_27M 238 -#define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_MIPI_IPG 240 -#define IMX6QDL_CLK_CAAM_MEM 241 -#define IMX6QDL_CLK_CAAM_ACLK 242 -#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_SPDIF_GCLK 244 -#define IMX6QDL_CLK_UART_SEL 245 -#define IMX6QDL_CLK_IPG_PER_SEL 246 -#define IMX6QDL_CLK_ECSPI_SEL 247 -#define IMX6QDL_CLK_CAN_SEL 248 -#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 -#define IMX6QDL_CLK_PRE0 250 -#define IMX6QDL_CLK_PRE1 251 -#define IMX6QDL_CLK_PRE2 252 -#define IMX6QDL_CLK_PRE3 253 -#define IMX6QDL_CLK_PRG0_AXI 254 -#define IMX6QDL_CLK_PRG1_AXI 255 -#define IMX6QDL_CLK_PRG0_APB 256 -#define IMX6QDL_CLK_PRG1_APB 257 -#define IMX6QDL_CLK_PRE_AXI 258 -#define IMX6QDL_CLK_MLB_SEL 259 -#define IMX6QDL_CLK_MLB_PODF 260 -#define IMX6QDL_CLK_EPIT1 261 -#define IMX6QDL_CLK_EPIT2 262 -#define IMX6QDL_CLK_MMDC_P0_IPG 263 -#define IMX6QDL_CLK_DCIC1 264 -#define IMX6QDL_CLK_DCIC2 265 -#define IMX6QDL_CLK_END 266 - -#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h deleted file mode 100644 index 31364d2caae..00000000000 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H -#define __DT_BINDINGS_CLOCK_IMX6SL_H - -#define IMX6SL_CLK_DUMMY 0 -#define IMX6SL_CLK_CKIL 1 -#define IMX6SL_CLK_OSC 2 -#define IMX6SL_CLK_PLL1_SYS 3 -#define IMX6SL_CLK_PLL2_BUS 4 -#define IMX6SL_CLK_PLL3_USB_OTG 5 -#define IMX6SL_CLK_PLL4_AUDIO 6 -#define IMX6SL_CLK_PLL5_VIDEO 7 -#define IMX6SL_CLK_PLL6_ENET 8 -#define IMX6SL_CLK_PLL7_USB_HOST 9 -#define IMX6SL_CLK_USBPHY1 10 -#define IMX6SL_CLK_USBPHY2 11 -#define IMX6SL_CLK_USBPHY1_GATE 12 -#define IMX6SL_CLK_USBPHY2_GATE 13 -#define IMX6SL_CLK_PLL4_POST_DIV 14 -#define IMX6SL_CLK_PLL5_POST_DIV 15 -#define IMX6SL_CLK_PLL5_VIDEO_DIV 16 -#define IMX6SL_CLK_ENET_REF 17 -#define IMX6SL_CLK_PLL2_PFD0 18 -#define IMX6SL_CLK_PLL2_PFD1 19 -#define IMX6SL_CLK_PLL2_PFD2 20 -#define IMX6SL_CLK_PLL3_PFD0 21 -#define IMX6SL_CLK_PLL3_PFD1 22 -#define IMX6SL_CLK_PLL3_PFD2 23 -#define IMX6SL_CLK_PLL3_PFD3 24 -#define IMX6SL_CLK_PLL2_198M 25 -#define IMX6SL_CLK_PLL3_120M 26 -#define IMX6SL_CLK_PLL3_80M 27 -#define IMX6SL_CLK_PLL3_60M 28 -#define IMX6SL_CLK_STEP 29 -#define IMX6SL_CLK_PLL1_SW 30 -#define IMX6SL_CLK_OCRAM_ALT_SEL 31 -#define IMX6SL_CLK_OCRAM_SEL 32 -#define IMX6SL_CLK_PRE_PERIPH2_SEL 33 -#define IMX6SL_CLK_PRE_PERIPH_SEL 34 -#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 -#define IMX6SL_CLK_PERIPH_CLK2_SEL 36 -#define IMX6SL_CLK_CSI_SEL 37 -#define IMX6SL_CLK_LCDIF_AXI_SEL 38 -#define IMX6SL_CLK_USDHC1_SEL 39 -#define IMX6SL_CLK_USDHC2_SEL 40 -#define IMX6SL_CLK_USDHC3_SEL 41 -#define IMX6SL_CLK_USDHC4_SEL 42 -#define IMX6SL_CLK_SSI1_SEL 43 -#define IMX6SL_CLK_SSI2_SEL 44 -#define IMX6SL_CLK_SSI3_SEL 45 -#define IMX6SL_CLK_PERCLK_SEL 46 -#define IMX6SL_CLK_PXP_AXI_SEL 47 -#define IMX6SL_CLK_EPDC_AXI_SEL 48 -#define IMX6SL_CLK_GPU2D_OVG_SEL 49 -#define IMX6SL_CLK_GPU2D_SEL 50 -#define IMX6SL_CLK_LCDIF_PIX_SEL 51 -#define IMX6SL_CLK_EPDC_PIX_SEL 52 -#define IMX6SL_CLK_SPDIF0_SEL 53 -#define IMX6SL_CLK_SPDIF1_SEL 54 -#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 -#define IMX6SL_CLK_ECSPI_SEL 56 -#define IMX6SL_CLK_UART_SEL 57 -#define IMX6SL_CLK_PERIPH 58 -#define IMX6SL_CLK_PERIPH2 59 -#define IMX6SL_CLK_OCRAM_PODF 60 -#define IMX6SL_CLK_PERIPH_CLK2_PODF 61 -#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 -#define IMX6SL_CLK_IPG 63 -#define IMX6SL_CLK_CSI_PODF 64 -#define IMX6SL_CLK_LCDIF_AXI_PODF 65 -#define IMX6SL_CLK_USDHC1_PODF 66 -#define IMX6SL_CLK_USDHC2_PODF 67 -#define IMX6SL_CLK_USDHC3_PODF 68 -#define IMX6SL_CLK_USDHC4_PODF 69 -#define IMX6SL_CLK_SSI1_PRED 70 -#define IMX6SL_CLK_SSI1_PODF 71 -#define IMX6SL_CLK_SSI2_PRED 72 -#define IMX6SL_CLK_SSI2_PODF 73 -#define IMX6SL_CLK_SSI3_PRED 74 -#define IMX6SL_CLK_SSI3_PODF 75 -#define IMX6SL_CLK_PERCLK 76 -#define IMX6SL_CLK_PXP_AXI_PODF 77 -#define IMX6SL_CLK_EPDC_AXI_PODF 78 -#define IMX6SL_CLK_GPU2D_OVG_PODF 79 -#define IMX6SL_CLK_GPU2D_PODF 80 -#define IMX6SL_CLK_LCDIF_PIX_PRED 81 -#define IMX6SL_CLK_EPDC_PIX_PRED 82 -#define IMX6SL_CLK_LCDIF_PIX_PODF 83 -#define IMX6SL_CLK_EPDC_PIX_PODF 84 -#define IMX6SL_CLK_SPDIF0_PRED 85 -#define IMX6SL_CLK_SPDIF0_PODF 86 -#define IMX6SL_CLK_SPDIF1_PRED 87 -#define IMX6SL_CLK_SPDIF1_PODF 88 -#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 -#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 -#define IMX6SL_CLK_ECSPI_ROOT 91 -#define IMX6SL_CLK_UART_ROOT 92 -#define IMX6SL_CLK_AHB 93 -#define IMX6SL_CLK_MMDC_ROOT 94 -#define IMX6SL_CLK_ARM 95 -#define IMX6SL_CLK_ECSPI1 96 -#define IMX6SL_CLK_ECSPI2 97 -#define IMX6SL_CLK_ECSPI3 98 -#define IMX6SL_CLK_ECSPI4 99 -#define IMX6SL_CLK_EPIT1 100 -#define IMX6SL_CLK_EPIT2 101 -#define IMX6SL_CLK_EXTERN_AUDIO 102 -#define IMX6SL_CLK_GPT 103 -#define IMX6SL_CLK_GPT_SERIAL 104 -#define IMX6SL_CLK_GPU2D_OVG 105 -#define IMX6SL_CLK_I2C1 106 -#define IMX6SL_CLK_I2C2 107 -#define IMX6SL_CLK_I2C3 108 -#define IMX6SL_CLK_OCOTP 109 -#define IMX6SL_CLK_CSI 110 -#define IMX6SL_CLK_PXP_AXI 111 -#define IMX6SL_CLK_EPDC_AXI 112 -#define IMX6SL_CLK_LCDIF_AXI 113 -#define IMX6SL_CLK_LCDIF_PIX 114 -#define IMX6SL_CLK_EPDC_PIX 115 -#define IMX6SL_CLK_OCRAM 116 -#define IMX6SL_CLK_PWM1 117 -#define IMX6SL_CLK_PWM2 118 -#define IMX6SL_CLK_PWM3 119 -#define IMX6SL_CLK_PWM4 120 -#define IMX6SL_CLK_SDMA 121 -#define IMX6SL_CLK_SPDIF 122 -#define IMX6SL_CLK_SSI1 123 -#define IMX6SL_CLK_SSI2 124 -#define IMX6SL_CLK_SSI3 125 -#define IMX6SL_CLK_UART 126 -#define IMX6SL_CLK_UART_SERIAL 127 -#define IMX6SL_CLK_USBOH3 128 -#define IMX6SL_CLK_USDHC1 129 -#define IMX6SL_CLK_USDHC2 130 -#define IMX6SL_CLK_USDHC3 131 -#define IMX6SL_CLK_USDHC4 132 -#define IMX6SL_CLK_PLL4_AUDIO_DIV 133 -#define IMX6SL_CLK_SPBA 134 -#define IMX6SL_CLK_ENET 135 -#define IMX6SL_CLK_LVDS1_SEL 136 -#define IMX6SL_CLK_LVDS1_OUT 137 -#define IMX6SL_CLK_LVDS1_IN 138 -#define IMX6SL_CLK_ANACLK1 139 -#define IMX6SL_PLL1_BYPASS_SRC 140 -#define IMX6SL_PLL2_BYPASS_SRC 141 -#define IMX6SL_PLL3_BYPASS_SRC 142 -#define IMX6SL_PLL4_BYPASS_SRC 143 -#define IMX6SL_PLL5_BYPASS_SRC 144 -#define IMX6SL_PLL6_BYPASS_SRC 145 -#define IMX6SL_PLL7_BYPASS_SRC 146 -#define IMX6SL_CLK_PLL1 147 -#define IMX6SL_CLK_PLL2 148 -#define IMX6SL_CLK_PLL3 149 -#define IMX6SL_CLK_PLL4 150 -#define IMX6SL_CLK_PLL5 151 -#define IMX6SL_CLK_PLL6 152 -#define IMX6SL_CLK_PLL7 153 -#define IMX6SL_PLL1_BYPASS 154 -#define IMX6SL_PLL2_BYPASS 155 -#define IMX6SL_PLL3_BYPASS 156 -#define IMX6SL_PLL4_BYPASS 157 -#define IMX6SL_PLL5_BYPASS 158 -#define IMX6SL_PLL6_BYPASS 159 -#define IMX6SL_PLL7_BYPASS 160 -#define IMX6SL_CLK_SSI1_IPG 161 -#define IMX6SL_CLK_SSI2_IPG 162 -#define IMX6SL_CLK_SSI3_IPG 163 -#define IMX6SL_CLK_SPDIF_GCLK 164 -#define IMX6SL_CLK_MMDC_P0_IPG 165 -#define IMX6SL_CLK_MMDC_P1_IPG 166 -#define IMX6SL_CLK_END 167 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h deleted file mode 100644 index 494fd0c37fb..00000000000 --- a/include/dt-bindings/clock/imx6sll-clock.h +++ /dev/null @@ -1,210 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H -#define __DT_BINDINGS_CLOCK_IMX6SLL_H - -#define IMX6SLL_CLK_DUMMY 0 -#define IMX6SLL_CLK_CKIL 1 -#define IMX6SLL_CLK_OSC 2 -#define IMX6SLL_PLL1_BYPASS_SRC 3 -#define IMX6SLL_PLL2_BYPASS_SRC 4 -#define IMX6SLL_PLL3_BYPASS_SRC 5 -#define IMX6SLL_PLL4_BYPASS_SRC 6 -#define IMX6SLL_PLL5_BYPASS_SRC 7 -#define IMX6SLL_PLL6_BYPASS_SRC 8 -#define IMX6SLL_PLL7_BYPASS_SRC 9 -#define IMX6SLL_CLK_PLL1 10 -#define IMX6SLL_CLK_PLL2 11 -#define IMX6SLL_CLK_PLL3 12 -#define IMX6SLL_CLK_PLL4 13 -#define IMX6SLL_CLK_PLL5 14 -#define IMX6SLL_CLK_PLL6 15 -#define IMX6SLL_CLK_PLL7 16 -#define IMX6SLL_PLL1_BYPASS 17 -#define IMX6SLL_PLL2_BYPASS 18 -#define IMX6SLL_PLL3_BYPASS 19 -#define IMX6SLL_PLL4_BYPASS 20 -#define IMX6SLL_PLL5_BYPASS 21 -#define IMX6SLL_PLL6_BYPASS 22 -#define IMX6SLL_PLL7_BYPASS 23 -#define IMX6SLL_CLK_PLL1_SYS 24 -#define IMX6SLL_CLK_PLL2_BUS 25 -#define IMX6SLL_CLK_PLL3_USB_OTG 26 -#define IMX6SLL_CLK_PLL4_AUDIO 27 -#define IMX6SLL_CLK_PLL5_VIDEO 28 -#define IMX6SLL_CLK_PLL6_ENET 29 -#define IMX6SLL_CLK_PLL7_USB_HOST 30 -#define IMX6SLL_CLK_USBPHY1 31 -#define IMX6SLL_CLK_USBPHY2 32 -#define IMX6SLL_CLK_USBPHY1_GATE 33 -#define IMX6SLL_CLK_USBPHY2_GATE 34 -#define IMX6SLL_CLK_PLL2_PFD0 35 -#define IMX6SLL_CLK_PLL2_PFD1 36 -#define IMX6SLL_CLK_PLL2_PFD2 37 -#define IMX6SLL_CLK_PLL2_PFD3 38 -#define IMX6SLL_CLK_PLL3_PFD0 39 -#define IMX6SLL_CLK_PLL3_PFD1 40 -#define IMX6SLL_CLK_PLL3_PFD2 41 -#define IMX6SLL_CLK_PLL3_PFD3 42 -#define IMX6SLL_CLK_PLL4_POST_DIV 43 -#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 -#define IMX6SLL_CLK_PLL5_POST_DIV 45 -#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 -#define IMX6SLL_CLK_PLL2_198M 47 -#define IMX6SLL_CLK_PLL3_120M 48 -#define IMX6SLL_CLK_PLL3_80M 49 -#define IMX6SLL_CLK_PLL3_60M 50 -#define IMX6SLL_CLK_STEP 51 -#define IMX6SLL_CLK_PLL1_SW 52 -#define IMX6SLL_CLK_AXI_ALT_SEL 53 -#define IMX6SLL_CLK_AXI_SEL 54 -#define IMX6SLL_CLK_PERIPH_PRE 55 -#define IMX6SLL_CLK_PERIPH2_PRE 56 -#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 -#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 -#define IMX6SLL_CLK_PERCLK_SEL 59 -#define IMX6SLL_CLK_USDHC1_SEL 60 -#define IMX6SLL_CLK_USDHC2_SEL 61 -#define IMX6SLL_CLK_USDHC3_SEL 62 -#define IMX6SLL_CLK_SSI1_SEL 63 -#define IMX6SLL_CLK_SSI2_SEL 64 -#define IMX6SLL_CLK_SSI3_SEL 65 -#define IMX6SLL_CLK_PXP_SEL 66 -#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 -#define IMX6SLL_CLK_LCDIF_SEL 68 -#define IMX6SLL_CLK_EPDC_PRE_SEL 69 -#define IMX6SLL_CLK_SPDIF_SEL 70 -#define IMX6SLL_CLK_ECSPI_SEL 71 -#define IMX6SLL_CLK_UART_SEL 72 -#define IMX6SLL_CLK_ARM 73 -#define IMX6SLL_CLK_PERIPH 74 -#define IMX6SLL_CLK_PERIPH2 75 -#define IMX6SLL_CLK_PERIPH2_CLK2 76 -#define IMX6SLL_CLK_PERIPH_CLK2 77 -#define IMX6SLL_CLK_MMDC_PODF 78 -#define IMX6SLL_CLK_AXI_PODF 79 -#define IMX6SLL_CLK_AHB 80 -#define IMX6SLL_CLK_IPG 81 -#define IMX6SLL_CLK_PERCLK 82 -#define IMX6SLL_CLK_USDHC1_PODF 83 -#define IMX6SLL_CLK_USDHC2_PODF 84 -#define IMX6SLL_CLK_USDHC3_PODF 85 -#define IMX6SLL_CLK_SSI1_PRED 86 -#define IMX6SLL_CLK_SSI2_PRED 87 -#define IMX6SLL_CLK_SSI3_PRED 88 -#define IMX6SLL_CLK_SSI1_PODF 89 -#define IMX6SLL_CLK_SSI2_PODF 90 -#define IMX6SLL_CLK_SSI3_PODF 91 -#define IMX6SLL_CLK_PXP_PODF 92 -#define IMX6SLL_CLK_LCDIF_PRED 93 -#define IMX6SLL_CLK_LCDIF_PODF 94 -#define IMX6SLL_CLK_EPDC_SEL 95 -#define IMX6SLL_CLK_EPDC_PODF 96 -#define IMX6SLL_CLK_SPDIF_PRED 97 -#define IMX6SLL_CLK_SPDIF_PODF 98 -#define IMX6SLL_CLK_ECSPI_PODF 99 -#define IMX6SLL_CLK_UART_PODF 100 - -/* CCGR 0 */ -#define IMX6SLL_CLK_AIPSTZ1 101 -#define IMX6SLL_CLK_AIPSTZ2 102 -#define IMX6SLL_CLK_DCP 103 -#define IMX6SLL_CLK_UART2_IPG 104 -#define IMX6SLL_CLK_UART2_SERIAL 105 - -/* CCGR 1 */ -#define IMX6SLL_CLK_ECSPI1 106 -#define IMX6SLL_CLK_ECSPI2 107 -#define IMX6SLL_CLK_ECSPI3 108 -#define IMX6SLL_CLK_ECSPI4 109 -#define IMX6SLL_CLK_UART3_IPG 110 -#define IMX6SLL_CLK_UART3_SERIAL 111 -#define IMX6SLL_CLK_UART4_IPG 112 -#define IMX6SLL_CLK_UART4_SERIAL 113 -#define IMX6SLL_CLK_EPIT1 114 -#define IMX6SLL_CLK_EPIT2 115 -#define IMX6SLL_CLK_GPT_BUS 116 -#define IMX6SLL_CLK_GPT_SERIAL 117 - -/* CCGR2 */ -#define IMX6SLL_CLK_CSI 118 -#define IMX6SLL_CLK_I2C1 119 -#define IMX6SLL_CLK_I2C2 120 -#define IMX6SLL_CLK_I2C3 121 -#define IMX6SLL_CLK_OCOTP 122 -#define IMX6SLL_CLK_LCDIF_APB 123 -#define IMX6SLL_CLK_PXP 124 - -/* CCGR3 */ -#define IMX6SLL_CLK_UART5_IPG 125 -#define IMX6SLL_CLK_UART5_SERIAL 126 -#define IMX6SLL_CLK_EPDC_AXI 127 -#define IMX6SLL_CLK_EPDC_PIX 128 -#define IMX6SLL_CLK_LCDIF_PIX 129 -#define IMX6SLL_CLK_WDOG1 130 -#define IMX6SLL_CLK_MMDC_P0_FAST 131 -#define IMX6SLL_CLK_MMDC_P0_IPG 132 -#define IMX6SLL_CLK_OCRAM 133 - -/* CCGR4 */ -#define IMX6SLL_CLK_PWM1 134 -#define IMX6SLL_CLK_PWM2 135 -#define IMX6SLL_CLK_PWM3 136 -#define IMX6SLL_CLK_PWM4 137 - -/* CCGR 5 */ -#define IMX6SLL_CLK_ROM 138 -#define IMX6SLL_CLK_SDMA 139 -#define IMX6SLL_CLK_KPP 140 -#define IMX6SLL_CLK_WDOG2 141 -#define IMX6SLL_CLK_SPBA 142 -#define IMX6SLL_CLK_SPDIF 143 -#define IMX6SLL_CLK_SPDIF_GCLK 144 -#define IMX6SLL_CLK_SSI1 145 -#define IMX6SLL_CLK_SSI1_IPG 146 -#define IMX6SLL_CLK_SSI2 147 -#define IMX6SLL_CLK_SSI2_IPG 148 -#define IMX6SLL_CLK_SSI3 149 -#define IMX6SLL_CLK_SSI3_IPG 150 -#define IMX6SLL_CLK_UART1_IPG 151 -#define IMX6SLL_CLK_UART1_SERIAL 152 - -/* CCGR 6 */ -#define IMX6SLL_CLK_USBOH3 153 -#define IMX6SLL_CLK_USDHC1 154 -#define IMX6SLL_CLK_USDHC2 155 -#define IMX6SLL_CLK_USDHC3 156 - -#define IMX6SLL_CLK_IPP_DI0 157 -#define IMX6SLL_CLK_IPP_DI1 158 -#define IMX6SLL_CLK_LDB_DI0_SEL 159 -#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 -#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 -#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 -#define IMX6SLL_CLK_LDB_DI0 163 -#define IMX6SLL_CLK_LDB_DI1_SEL 164 -#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 -#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 -#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 -#define IMX6SLL_CLK_LDB_DI1 168 -#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 -#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 -#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 -#define IMX6SLL_CLK_EXTERN_AUDIO 172 - -#define IMX6SLL_CLK_GPIO1 173 -#define IMX6SLL_CLK_GPIO2 174 -#define IMX6SLL_CLK_GPIO3 175 -#define IMX6SLL_CLK_GPIO4 176 -#define IMX6SLL_CLK_GPIO5 177 -#define IMX6SLL_CLK_GPIO6 178 -#define IMX6SLL_CLK_MMDC_P1_IPG 179 - -#define IMX6SLL_CLK_END 180 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h deleted file mode 100644 index 1c64997d619..00000000000 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ /dev/null @@ -1,281 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H -#define __DT_BINDINGS_CLOCK_IMX6SX_H - -#define IMX6SX_CLK_DUMMY 0 -#define IMX6SX_CLK_CKIL 1 -#define IMX6SX_CLK_CKIH 2 -#define IMX6SX_CLK_OSC 3 -#define IMX6SX_CLK_PLL1_SYS 4 -#define IMX6SX_CLK_PLL2_BUS 5 -#define IMX6SX_CLK_PLL3_USB_OTG 6 -#define IMX6SX_CLK_PLL4_AUDIO 7 -#define IMX6SX_CLK_PLL5_VIDEO 8 -#define IMX6SX_CLK_PLL6_ENET 9 -#define IMX6SX_CLK_PLL7_USB_HOST 10 -#define IMX6SX_CLK_USBPHY1 11 -#define IMX6SX_CLK_USBPHY2 12 -#define IMX6SX_CLK_USBPHY1_GATE 13 -#define IMX6SX_CLK_USBPHY2_GATE 14 -#define IMX6SX_CLK_PCIE_REF 15 -#define IMX6SX_CLK_PCIE_REF_125M 16 -#define IMX6SX_CLK_ENET_REF 17 -#define IMX6SX_CLK_PLL2_PFD0 18 -#define IMX6SX_CLK_PLL2_PFD1 19 -#define IMX6SX_CLK_PLL2_PFD2 20 -#define IMX6SX_CLK_PLL2_PFD3 21 -#define IMX6SX_CLK_PLL3_PFD0 22 -#define IMX6SX_CLK_PLL3_PFD1 23 -#define IMX6SX_CLK_PLL3_PFD2 24 -#define IMX6SX_CLK_PLL3_PFD3 25 -#define IMX6SX_CLK_PLL2_198M 26 -#define IMX6SX_CLK_PLL3_120M 27 -#define IMX6SX_CLK_PLL3_80M 28 -#define IMX6SX_CLK_PLL3_60M 29 -#define IMX6SX_CLK_TWD 30 -#define IMX6SX_CLK_PLL4_POST_DIV 31 -#define IMX6SX_CLK_PLL4_AUDIO_DIV 32 -#define IMX6SX_CLK_PLL5_POST_DIV 33 -#define IMX6SX_CLK_PLL5_VIDEO_DIV 34 -#define IMX6SX_CLK_STEP 35 -#define IMX6SX_CLK_PLL1_SW 36 -#define IMX6SX_CLK_OCRAM_SEL 37 -#define IMX6SX_CLK_PERIPH_PRE 38 -#define IMX6SX_CLK_PERIPH2_PRE 39 -#define IMX6SX_CLK_PERIPH_CLK2_SEL 40 -#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 -#define IMX6SX_CLK_PCIE_AXI_SEL 42 -#define IMX6SX_CLK_GPU_AXI_SEL 43 -#define IMX6SX_CLK_GPU_CORE_SEL 44 -#define IMX6SX_CLK_EIM_SLOW_SEL 45 -#define IMX6SX_CLK_USDHC1_SEL 46 -#define IMX6SX_CLK_USDHC2_SEL 47 -#define IMX6SX_CLK_USDHC3_SEL 48 -#define IMX6SX_CLK_USDHC4_SEL 49 -#define IMX6SX_CLK_SSI1_SEL 50 -#define IMX6SX_CLK_SSI2_SEL 51 -#define IMX6SX_CLK_SSI3_SEL 52 -#define IMX6SX_CLK_QSPI1_SEL 53 -#define IMX6SX_CLK_PERCLK_SEL 54 -#define IMX6SX_CLK_VID_SEL 55 -#define IMX6SX_CLK_ESAI_SEL 56 -#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 -#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 -#define IMX6SX_CLK_CAN_SEL 59 -#define IMX6SX_CLK_UART_SEL 60 -#define IMX6SX_CLK_QSPI2_SEL 61 -#define IMX6SX_CLK_LDB_DI1_SEL 62 -#define IMX6SX_CLK_LDB_DI0_SEL 63 -#define IMX6SX_CLK_SPDIF_SEL 64 -#define IMX6SX_CLK_AUDIO_SEL 65 -#define IMX6SX_CLK_ENET_PRE_SEL 66 -#define IMX6SX_CLK_ENET_SEL 67 -#define IMX6SX_CLK_M4_PRE_SEL 68 -#define IMX6SX_CLK_M4_SEL 69 -#define IMX6SX_CLK_ECSPI_SEL 70 -#define IMX6SX_CLK_LCDIF1_PRE_SEL 71 -#define IMX6SX_CLK_LCDIF2_PRE_SEL 72 -#define IMX6SX_CLK_LCDIF1_SEL 73 -#define IMX6SX_CLK_LCDIF2_SEL 74 -#define IMX6SX_CLK_DISPLAY_SEL 75 -#define IMX6SX_CLK_CSI_SEL 76 -#define IMX6SX_CLK_CKO1_SEL 77 -#define IMX6SX_CLK_CKO2_SEL 78 -#define IMX6SX_CLK_CKO 79 -#define IMX6SX_CLK_PERIPH_CLK2 80 -#define IMX6SX_CLK_PERIPH2_CLK2 81 -#define IMX6SX_CLK_IPG 82 -#define IMX6SX_CLK_GPU_CORE_PODF 83 -#define IMX6SX_CLK_GPU_AXI_PODF 84 -#define IMX6SX_CLK_LCDIF1_PODF 85 -#define IMX6SX_CLK_QSPI1_PODF 86 -#define IMX6SX_CLK_EIM_SLOW_PODF 87 -#define IMX6SX_CLK_LCDIF2_PODF 88 -#define IMX6SX_CLK_PERCLK 89 -#define IMX6SX_CLK_VID_PODF 90 -#define IMX6SX_CLK_CAN_PODF 91 -#define IMX6SX_CLK_USDHC1_PODF 92 -#define IMX6SX_CLK_USDHC2_PODF 93 -#define IMX6SX_CLK_USDHC3_PODF 94 -#define IMX6SX_CLK_USDHC4_PODF 95 -#define IMX6SX_CLK_UART_PODF 96 -#define IMX6SX_CLK_ESAI_PRED 97 -#define IMX6SX_CLK_ESAI_PODF 98 -#define IMX6SX_CLK_SSI3_PRED 99 -#define IMX6SX_CLK_SSI3_PODF 100 -#define IMX6SX_CLK_SSI1_PRED 101 -#define IMX6SX_CLK_SSI1_PODF 102 -#define IMX6SX_CLK_QSPI2_PRED 103 -#define IMX6SX_CLK_QSPI2_PODF 104 -#define IMX6SX_CLK_SSI2_PRED 105 -#define IMX6SX_CLK_SSI2_PODF 106 -#define IMX6SX_CLK_SPDIF_PRED 107 -#define IMX6SX_CLK_SPDIF_PODF 108 -#define IMX6SX_CLK_AUDIO_PRED 109 -#define IMX6SX_CLK_AUDIO_PODF 110 -#define IMX6SX_CLK_ENET_PODF 111 -#define IMX6SX_CLK_M4_PODF 112 -#define IMX6SX_CLK_ECSPI_PODF 113 -#define IMX6SX_CLK_LCDIF1_PRED 114 -#define IMX6SX_CLK_LCDIF2_PRED 115 -#define IMX6SX_CLK_DISPLAY_PODF 116 -#define IMX6SX_CLK_CSI_PODF 117 -#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 -#define IMX6SX_CLK_LDB_DI0_DIV_7 119 -#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 -#define IMX6SX_CLK_LDB_DI1_DIV_7 121 -#define IMX6SX_CLK_CKO1_PODF 122 -#define IMX6SX_CLK_CKO2_PODF 123 -#define IMX6SX_CLK_PERIPH 124 -#define IMX6SX_CLK_PERIPH2 125 -#define IMX6SX_CLK_OCRAM 126 -#define IMX6SX_CLK_AHB 127 -#define IMX6SX_CLK_MMDC_PODF 128 -#define IMX6SX_CLK_ARM 129 -#define IMX6SX_CLK_AIPS_TZ1 130 -#define IMX6SX_CLK_AIPS_TZ2 131 -#define IMX6SX_CLK_APBH_DMA 132 -#define IMX6SX_CLK_ASRC_GATE 133 -#define IMX6SX_CLK_CAAM_MEM 134 -#define IMX6SX_CLK_CAAM_ACLK 135 -#define IMX6SX_CLK_CAAM_IPG 136 -#define IMX6SX_CLK_CAN1_IPG 137 -#define IMX6SX_CLK_CAN1_SERIAL 138 -#define IMX6SX_CLK_CAN2_IPG 139 -#define IMX6SX_CLK_CAN2_SERIAL 140 -#define IMX6SX_CLK_CPU_DEBUG 141 -#define IMX6SX_CLK_DCIC1 142 -#define IMX6SX_CLK_DCIC2 143 -#define IMX6SX_CLK_AIPS_TZ3 144 -#define IMX6SX_CLK_ECSPI1 145 -#define IMX6SX_CLK_ECSPI2 146 -#define IMX6SX_CLK_ECSPI3 147 -#define IMX6SX_CLK_ECSPI4 148 -#define IMX6SX_CLK_ECSPI5 149 -#define IMX6SX_CLK_EPIT1 150 -#define IMX6SX_CLK_EPIT2 151 -#define IMX6SX_CLK_ESAI_EXTAL 152 -#define IMX6SX_CLK_WAKEUP 153 -#define IMX6SX_CLK_GPT_BUS 154 -#define IMX6SX_CLK_GPT_SERIAL 155 -#define IMX6SX_CLK_GPU 156 -#define IMX6SX_CLK_OCRAM_S 157 -#define IMX6SX_CLK_CANFD 158 -#define IMX6SX_CLK_CSI 159 -#define IMX6SX_CLK_I2C1 160 -#define IMX6SX_CLK_I2C2 161 -#define IMX6SX_CLK_I2C3 162 -#define IMX6SX_CLK_OCOTP 163 -#define IMX6SX_CLK_IOMUXC 164 -#define IMX6SX_CLK_IPMUX1 165 -#define IMX6SX_CLK_IPMUX2 166 -#define IMX6SX_CLK_IPMUX3 167 -#define IMX6SX_CLK_TZASC1 168 -#define IMX6SX_CLK_LCDIF_APB 169 -#define IMX6SX_CLK_PXP_AXI 170 -#define IMX6SX_CLK_M4 171 -#define IMX6SX_CLK_ENET 172 -#define IMX6SX_CLK_DISPLAY_AXI 173 -#define IMX6SX_CLK_LCDIF2_PIX 174 -#define IMX6SX_CLK_LCDIF1_PIX 175 -#define IMX6SX_CLK_LDB_DI0 176 -#define IMX6SX_CLK_QSPI1 177 -#define IMX6SX_CLK_MLB 178 -#define IMX6SX_CLK_MMDC_P0_FAST 179 -#define IMX6SX_CLK_MMDC_P0_IPG 180 -#define IMX6SX_CLK_AXI 181 -#define IMX6SX_CLK_PCIE_AXI 182 -#define IMX6SX_CLK_QSPI2 183 -#define IMX6SX_CLK_PER1_BCH 184 -#define IMX6SX_CLK_PER2_MAIN 185 -#define IMX6SX_CLK_PWM1 186 -#define IMX6SX_CLK_PWM2 187 -#define IMX6SX_CLK_PWM3 188 -#define IMX6SX_CLK_PWM4 189 -#define IMX6SX_CLK_GPMI_BCH_APB 190 -#define IMX6SX_CLK_GPMI_BCH 191 -#define IMX6SX_CLK_GPMI_IO 192 -#define IMX6SX_CLK_GPMI_APB 193 -#define IMX6SX_CLK_ROM 194 -#define IMX6SX_CLK_SDMA 195 -#define IMX6SX_CLK_SPBA 196 -#define IMX6SX_CLK_SPDIF 197 -#define IMX6SX_CLK_SSI1_IPG 198 -#define IMX6SX_CLK_SSI2_IPG 199 -#define IMX6SX_CLK_SSI3_IPG 200 -#define IMX6SX_CLK_SSI1 201 -#define IMX6SX_CLK_SSI2 202 -#define IMX6SX_CLK_SSI3 203 -#define IMX6SX_CLK_UART_IPG 204 -#define IMX6SX_CLK_UART_SERIAL 205 -#define IMX6SX_CLK_SAI1 206 -#define IMX6SX_CLK_SAI2 207 -#define IMX6SX_CLK_USBOH3 208 -#define IMX6SX_CLK_USDHC1 209 -#define IMX6SX_CLK_USDHC2 210 -#define IMX6SX_CLK_USDHC3 211 -#define IMX6SX_CLK_USDHC4 212 -#define IMX6SX_CLK_EIM_SLOW 213 -#define IMX6SX_CLK_PWM8 214 -#define IMX6SX_CLK_VADC 215 -#define IMX6SX_CLK_GIS 216 -#define IMX6SX_CLK_I2C4 217 -#define IMX6SX_CLK_PWM5 218 -#define IMX6SX_CLK_PWM6 219 -#define IMX6SX_CLK_PWM7 220 -#define IMX6SX_CLK_CKO1 221 -#define IMX6SX_CLK_CKO2 222 -#define IMX6SX_CLK_IPP_DI0 223 -#define IMX6SX_CLK_IPP_DI1 224 -#define IMX6SX_CLK_ENET_AHB 225 -#define IMX6SX_CLK_OCRAM_PODF 226 -#define IMX6SX_CLK_GPT_3M 227 -#define IMX6SX_CLK_ENET_PTP 228 -#define IMX6SX_CLK_ENET_PTP_REF 229 -#define IMX6SX_CLK_ENET2_REF 230 -#define IMX6SX_CLK_ENET2_REF_125M 231 -#define IMX6SX_CLK_AUDIO 232 -#define IMX6SX_CLK_LVDS1_SEL 233 -#define IMX6SX_CLK_LVDS1_OUT 234 -#define IMX6SX_CLK_ASRC_IPG 235 -#define IMX6SX_CLK_ASRC_MEM 236 -#define IMX6SX_CLK_SAI1_IPG 237 -#define IMX6SX_CLK_SAI2_IPG 238 -#define IMX6SX_CLK_ESAI_IPG 239 -#define IMX6SX_CLK_ESAI_MEM 240 -#define IMX6SX_CLK_LVDS1_IN 241 -#define IMX6SX_CLK_ANACLK1 242 -#define IMX6SX_PLL1_BYPASS_SRC 243 -#define IMX6SX_PLL2_BYPASS_SRC 244 -#define IMX6SX_PLL3_BYPASS_SRC 245 -#define IMX6SX_PLL4_BYPASS_SRC 246 -#define IMX6SX_PLL5_BYPASS_SRC 247 -#define IMX6SX_PLL6_BYPASS_SRC 248 -#define IMX6SX_PLL7_BYPASS_SRC 249 -#define IMX6SX_CLK_PLL1 250 -#define IMX6SX_CLK_PLL2 251 -#define IMX6SX_CLK_PLL3 252 -#define IMX6SX_CLK_PLL4 253 -#define IMX6SX_CLK_PLL5 254 -#define IMX6SX_CLK_PLL6 255 -#define IMX6SX_CLK_PLL7 256 -#define IMX6SX_PLL1_BYPASS 257 -#define IMX6SX_PLL2_BYPASS 258 -#define IMX6SX_PLL3_BYPASS 259 -#define IMX6SX_PLL4_BYPASS 260 -#define IMX6SX_PLL5_BYPASS 261 -#define IMX6SX_PLL6_BYPASS 262 -#define IMX6SX_PLL7_BYPASS 263 -#define IMX6SX_CLK_SPDIF_GCLK 264 -#define IMX6SX_CLK_LVDS2_SEL 265 -#define IMX6SX_CLK_LVDS2_OUT 266 -#define IMX6SX_CLK_LVDS2_IN 267 -#define IMX6SX_CLK_ANACLK2 268 -#define IMX6SX_CLK_MMDC_P1_IPG 269 -#define IMX6SX_CLK_CLK_END 270 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h deleted file mode 100644 index 79094338e6f..00000000000 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H -#define __DT_BINDINGS_CLOCK_IMX6UL_H - -#define IMX6UL_CLK_DUMMY 0 -#define IMX6UL_CLK_CKIL 1 -#define IMX6UL_CLK_CKIH 2 -#define IMX6UL_CLK_OSC 3 -#define IMX6UL_PLL1_BYPASS_SRC 4 -#define IMX6UL_PLL2_BYPASS_SRC 5 -#define IMX6UL_PLL3_BYPASS_SRC 6 -#define IMX6UL_PLL4_BYPASS_SRC 7 -#define IMX6UL_PLL5_BYPASS_SRC 8 -#define IMX6UL_PLL6_BYPASS_SRC 9 -#define IMX6UL_PLL7_BYPASS_SRC 10 -#define IMX6UL_CLK_PLL1 11 -#define IMX6UL_CLK_PLL2 12 -#define IMX6UL_CLK_PLL3 13 -#define IMX6UL_CLK_PLL4 14 -#define IMX6UL_CLK_PLL5 15 -#define IMX6UL_CLK_PLL6 16 -#define IMX6UL_CLK_PLL7 17 -#define IMX6UL_PLL1_BYPASS 18 -#define IMX6UL_PLL2_BYPASS 19 -#define IMX6UL_PLL3_BYPASS 20 -#define IMX6UL_PLL4_BYPASS 21 -#define IMX6UL_PLL5_BYPASS 22 -#define IMX6UL_PLL6_BYPASS 23 -#define IMX6UL_PLL7_BYPASS 24 -#define IMX6UL_CLK_PLL1_SYS 25 -#define IMX6UL_CLK_PLL2_BUS 26 -#define IMX6UL_CLK_PLL3_USB_OTG 27 -#define IMX6UL_CLK_PLL4_AUDIO 28 -#define IMX6UL_CLK_PLL5_VIDEO 29 -#define IMX6UL_CLK_PLL6_ENET 30 -#define IMX6UL_CLK_PLL7_USB_HOST 31 -#define IMX6UL_CLK_USBPHY1 32 -#define IMX6UL_CLK_USBPHY2 33 -#define IMX6UL_CLK_USBPHY1_GATE 34 -#define IMX6UL_CLK_USBPHY2_GATE 35 -#define IMX6UL_CLK_PLL2_PFD0 36 -#define IMX6UL_CLK_PLL2_PFD1 37 -#define IMX6UL_CLK_PLL2_PFD2 38 -#define IMX6UL_CLK_PLL2_PFD3 39 -#define IMX6UL_CLK_PLL3_PFD0 40 -#define IMX6UL_CLK_PLL3_PFD1 41 -#define IMX6UL_CLK_PLL3_PFD2 42 -#define IMX6UL_CLK_PLL3_PFD3 43 -#define IMX6UL_CLK_ENET_REF 44 -#define IMX6UL_CLK_ENET2_REF 45 -#define IMX6UL_CLK_ENET2_REF_125M 46 -#define IMX6UL_CLK_ENET_PTP_REF 47 -#define IMX6UL_CLK_ENET_PTP 48 -#define IMX6UL_CLK_PLL4_POST_DIV 49 -#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 -#define IMX6UL_CLK_PLL5_POST_DIV 51 -#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 -#define IMX6UL_CLK_PLL2_198M 53 -#define IMX6UL_CLK_PLL3_80M 54 -#define IMX6UL_CLK_PLL3_60M 55 -#define IMX6UL_CLK_STEP 56 -#define IMX6UL_CLK_PLL1_SW 57 -#define IMX6UL_CLK_AXI_ALT_SEL 58 -#define IMX6UL_CLK_AXI_SEL 59 -#define IMX6UL_CLK_PERIPH_PRE 60 -#define IMX6UL_CLK_PERIPH2_PRE 61 -#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 -#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 -#define IMX6UL_CLK_USDHC1_SEL 64 -#define IMX6UL_CLK_USDHC2_SEL 65 -#define IMX6UL_CLK_BCH_SEL 66 -#define IMX6UL_CLK_GPMI_SEL 67 -#define IMX6UL_CLK_EIM_SLOW_SEL 68 -#define IMX6UL_CLK_SPDIF_SEL 69 -#define IMX6UL_CLK_SAI1_SEL 70 -#define IMX6UL_CLK_SAI2_SEL 71 -#define IMX6UL_CLK_SAI3_SEL 72 -#define IMX6UL_CLK_LCDIF_PRE_SEL 73 -#define IMX6UL_CLK_SIM_PRE_SEL 74 -#define IMX6UL_CLK_LDB_DI0_SEL 75 -#define IMX6UL_CLK_LDB_DI1_SEL 76 -#define IMX6UL_CLK_ENFC_SEL 77 -#define IMX6UL_CLK_CAN_SEL 78 -#define IMX6UL_CLK_ECSPI_SEL 79 -#define IMX6UL_CLK_UART_SEL 80 -#define IMX6UL_CLK_QSPI1_SEL 81 -#define IMX6UL_CLK_PERCLK_SEL 82 -#define IMX6UL_CLK_LCDIF_SEL 83 -#define IMX6UL_CLK_SIM_SEL 84 -#define IMX6UL_CLK_PERIPH 85 -#define IMX6UL_CLK_PERIPH2 86 -#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 -#define IMX6UL_CLK_LDB_DI0_DIV_7 88 -#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 -#define IMX6UL_CLK_LDB_DI1_DIV_7 90 -#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 -#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 -#define IMX6UL_CLK_ARM 93 -#define IMX6UL_CLK_PERIPH_CLK2 94 -#define IMX6UL_CLK_PERIPH2_CLK2 95 -#define IMX6UL_CLK_AHB 96 -#define IMX6UL_CLK_MMDC_PODF 97 -#define IMX6UL_CLK_AXI_PODF 98 -#define IMX6UL_CLK_PERCLK 99 -#define IMX6UL_CLK_IPG 100 -#define IMX6UL_CLK_USDHC1_PODF 101 -#define IMX6UL_CLK_USDHC2_PODF 102 -#define IMX6UL_CLK_BCH_PODF 103 -#define IMX6UL_CLK_GPMI_PODF 104 -#define IMX6UL_CLK_EIM_SLOW_PODF 105 -#define IMX6UL_CLK_SPDIF_PRED 106 -#define IMX6UL_CLK_SPDIF_PODF 107 -#define IMX6UL_CLK_SAI1_PRED 108 -#define IMX6UL_CLK_SAI1_PODF 109 -#define IMX6UL_CLK_SAI2_PRED 110 -#define IMX6UL_CLK_SAI2_PODF 111 -#define IMX6UL_CLK_SAI3_PRED 112 -#define IMX6UL_CLK_SAI3_PODF 113 -#define IMX6UL_CLK_LCDIF_PRED 114 -#define IMX6UL_CLK_LCDIF_PODF 115 -#define IMX6UL_CLK_SIM_PODF 116 -#define IMX6UL_CLK_QSPI1_PDOF 117 -#define IMX6UL_CLK_ENFC_PRED 118 -#define IMX6UL_CLK_ENFC_PODF 119 -#define IMX6UL_CLK_CAN_PODF 120 -#define IMX6UL_CLK_ECSPI_PODF 121 -#define IMX6UL_CLK_UART_PODF 122 -#define IMX6UL_CLK_ADC1 123 -#define IMX6UL_CLK_ADC2 124 -#define IMX6UL_CLK_AIPSTZ1 125 -#define IMX6UL_CLK_AIPSTZ2 126 -#define IMX6UL_CLK_AIPSTZ3 127 -#define IMX6UL_CLK_APBHDMA 128 -#define IMX6UL_CLK_ASRC_IPG 129 -#define IMX6UL_CLK_ASRC_MEM 130 -#define IMX6UL_CLK_GPMI_BCH_APB 131 -#define IMX6UL_CLK_GPMI_BCH 132 -#define IMX6UL_CLK_GPMI_IO 133 -#define IMX6UL_CLK_GPMI_APB 134 -#define IMX6UL_CLK_CAAM_MEM 135 -#define IMX6UL_CLK_CAAM_ACLK 136 -#define IMX6UL_CLK_CAAM_IPG 137 -#define IMX6UL_CLK_CSI 138 -#define IMX6UL_CLK_ECSPI1 139 -#define IMX6UL_CLK_ECSPI2 140 -#define IMX6UL_CLK_ECSPI3 141 -#define IMX6UL_CLK_ECSPI4 142 -#define IMX6UL_CLK_EIM 143 -#define IMX6UL_CLK_ENET 144 -#define IMX6UL_CLK_ENET_AHB 145 -#define IMX6UL_CLK_EPIT1 146 -#define IMX6UL_CLK_EPIT2 147 -#define IMX6UL_CLK_CAN1_IPG 148 -#define IMX6UL_CLK_CAN1_SERIAL 149 -#define IMX6UL_CLK_CAN2_IPG 150 -#define IMX6UL_CLK_CAN2_SERIAL 151 -#define IMX6UL_CLK_GPT1_BUS 152 -#define IMX6UL_CLK_GPT1_SERIAL 153 -#define IMX6UL_CLK_GPT2_BUS 154 -#define IMX6UL_CLK_GPT2_SERIAL 155 -#define IMX6UL_CLK_I2C1 156 -#define IMX6UL_CLK_I2C2 157 -#define IMX6UL_CLK_I2C3 158 -#define IMX6UL_CLK_I2C4 159 -#define IMX6UL_CLK_IOMUXC 160 -#define IMX6UL_CLK_LCDIF_APB 161 -#define IMX6UL_CLK_LCDIF_PIX 162 -#define IMX6UL_CLK_MMDC_P0_FAST 163 -#define IMX6UL_CLK_MMDC_P0_IPG 164 -#define IMX6UL_CLK_OCOTP 165 -#define IMX6UL_CLK_OCRAM 166 -#define IMX6UL_CLK_PWM1 167 -#define IMX6UL_CLK_PWM2 168 -#define IMX6UL_CLK_PWM3 169 -#define IMX6UL_CLK_PWM4 170 -#define IMX6UL_CLK_PWM5 171 -#define IMX6UL_CLK_PWM6 172 -#define IMX6UL_CLK_PWM7 173 -#define IMX6UL_CLK_PWM8 174 -#define IMX6UL_CLK_PXP 175 -#define IMX6UL_CLK_QSPI 176 -#define IMX6UL_CLK_ROM 177 -#define IMX6UL_CLK_SAI1 178 -#define IMX6UL_CLK_SAI1_IPG 179 -#define IMX6UL_CLK_SAI2 180 -#define IMX6UL_CLK_SAI2_IPG 181 -#define IMX6UL_CLK_SAI3 182 -#define IMX6UL_CLK_SAI3_IPG 183 -#define IMX6UL_CLK_SDMA 184 -#define IMX6UL_CLK_SIM 185 -#define IMX6UL_CLK_SIM_S 186 -#define IMX6UL_CLK_SPBA 187 -#define IMX6UL_CLK_SPDIF 188 -#define IMX6UL_CLK_UART1_IPG 189 -#define IMX6UL_CLK_UART1_SERIAL 190 -#define IMX6UL_CLK_UART2_IPG 191 -#define IMX6UL_CLK_UART2_SERIAL 192 -#define IMX6UL_CLK_UART3_IPG 193 -#define IMX6UL_CLK_UART3_SERIAL 194 -#define IMX6UL_CLK_UART4_IPG 195 -#define IMX6UL_CLK_UART4_SERIAL 196 -#define IMX6UL_CLK_UART5_IPG 197 -#define IMX6UL_CLK_UART5_SERIAL 198 -#define IMX6UL_CLK_UART6_IPG 199 -#define IMX6UL_CLK_UART6_SERIAL 200 -#define IMX6UL_CLK_UART7_IPG 201 -#define IMX6UL_CLK_UART7_SERIAL 202 -#define IMX6UL_CLK_UART8_IPG 203 -#define IMX6UL_CLK_UART8_SERIAL 204 -#define IMX6UL_CLK_USBOH3 205 -#define IMX6UL_CLK_USDHC1 206 -#define IMX6UL_CLK_USDHC2 207 -#define IMX6UL_CLK_WDOG1 208 -#define IMX6UL_CLK_WDOG2 209 -#define IMX6UL_CLK_WDOG3 210 -#define IMX6UL_CLK_LDB_DI0 211 -#define IMX6UL_CLK_AXI 212 -#define IMX6UL_CLK_SPDIF_GCLK 213 -#define IMX6UL_CLK_GPT_3M 214 -#define IMX6UL_CLK_SIM2 215 -#define IMX6UL_CLK_SIM1 216 -#define IMX6UL_CLK_IPP_DI0 217 -#define IMX6UL_CLK_IPP_DI1 218 -#define IMX6UL_CA7_SECONDARY_SEL 219 -#define IMX6UL_CLK_PER_BCH 220 -#define IMX6UL_CLK_CSI_SEL 221 -#define IMX6UL_CLK_CSI_PODF 222 -#define IMX6UL_CLK_PLL3_120M 223 -#define IMX6UL_CLK_KPP 224 -#define IMX6ULL_CLK_ESAI_PRED 225 -#define IMX6ULL_CLK_ESAI_PODF 226 -#define IMX6ULL_CLK_ESAI_EXTAL 227 -#define IMX6ULL_CLK_ESAI_MEM 228 -#define IMX6ULL_CLK_ESAI_IPG 229 -#define IMX6ULL_CLK_DCP_CLK 230 -#define IMX6ULL_CLK_EPDC_PRE_SEL 231 -#define IMX6ULL_CLK_EPDC_SEL 232 -#define IMX6ULL_CLK_EPDC_PODF 233 -#define IMX6ULL_CLK_EPDC_ACLK 234 -#define IMX6ULL_CLK_EPDC_PIX 235 -#define IMX6ULL_CLK_ESAI_SEL 236 -#define IMX6UL_CLK_CKO1_SEL 237 -#define IMX6UL_CLK_CKO1_PODF 238 -#define IMX6UL_CLK_CKO1 239 -#define IMX6UL_CLK_CKO2_SEL 240 -#define IMX6UL_CLK_CKO2_PODF 241 -#define IMX6UL_CLK_CKO2 242 -#define IMX6UL_CLK_CKO 243 -#define IMX6UL_CLK_GPIO1 244 -#define IMX6UL_CLK_GPIO2 245 -#define IMX6UL_CLK_GPIO3 246 -#define IMX6UL_CLK_GPIO4 247 -#define IMX6UL_CLK_GPIO5 248 -#define IMX6UL_CLK_MMDC_P1_IPG 249 - -#define IMX6UL_CLK_END 250 - -#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h deleted file mode 100644 index 1d4c0dfe020..00000000000 --- a/include/dt-bindings/clock/imx7d-clock.h +++ /dev/null @@ -1,456 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX7D_H -#define __DT_BINDINGS_CLOCK_IMX7D_H - -#define IMX7D_OSC_24M_CLK 0 -#define IMX7D_PLL_ARM_MAIN 1 -#define IMX7D_PLL_ARM_MAIN_CLK 2 -#define IMX7D_PLL_ARM_MAIN_SRC 3 -#define IMX7D_PLL_ARM_MAIN_BYPASS 4 -#define IMX7D_PLL_SYS_MAIN 5 -#define IMX7D_PLL_SYS_MAIN_CLK 6 -#define IMX7D_PLL_SYS_MAIN_SRC 7 -#define IMX7D_PLL_SYS_MAIN_BYPASS 8 -#define IMX7D_PLL_SYS_MAIN_480M 9 -#define IMX7D_PLL_SYS_MAIN_240M 10 -#define IMX7D_PLL_SYS_MAIN_120M 11 -#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 -#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 -#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 -#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 -#define IMX7D_PLL_SYS_PFD0_196M 16 -#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 -#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 -#define IMX7D_PLL_SYS_PFD1_166M 19 -#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 -#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 -#define IMX7D_PLL_SYS_PFD2_135M 22 -#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 -#define IMX7D_PLL_SYS_PFD3_CLK 24 -#define IMX7D_PLL_SYS_PFD4_CLK 25 -#define IMX7D_PLL_SYS_PFD5_CLK 26 -#define IMX7D_PLL_SYS_PFD6_CLK 27 -#define IMX7D_PLL_SYS_PFD7_CLK 28 -#define IMX7D_PLL_ENET_MAIN 29 -#define IMX7D_PLL_ENET_MAIN_CLK 30 -#define IMX7D_PLL_ENET_MAIN_SRC 31 -#define IMX7D_PLL_ENET_MAIN_BYPASS 32 -#define IMX7D_PLL_ENET_MAIN_500M 33 -#define IMX7D_PLL_ENET_MAIN_250M 34 -#define IMX7D_PLL_ENET_MAIN_125M 35 -#define IMX7D_PLL_ENET_MAIN_100M 36 -#define IMX7D_PLL_ENET_MAIN_50M 37 -#define IMX7D_PLL_ENET_MAIN_40M 38 -#define IMX7D_PLL_ENET_MAIN_25M 39 -#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 -#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 -#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 -#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 -#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 -#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 -#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 -#define IMX7D_PLL_DRAM_MAIN 47 -#define IMX7D_PLL_DRAM_MAIN_CLK 48 -#define IMX7D_PLL_DRAM_MAIN_SRC 49 -#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 -#define IMX7D_PLL_DRAM_MAIN_533M 51 -#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 -#define IMX7D_PLL_AUDIO_MAIN 53 -#define IMX7D_PLL_AUDIO_MAIN_CLK 54 -#define IMX7D_PLL_AUDIO_MAIN_SRC 55 -#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 -#define IMX7D_PLL_VIDEO_MAIN_CLK 57 -#define IMX7D_PLL_VIDEO_MAIN 58 -#define IMX7D_PLL_VIDEO_MAIN_SRC 59 -#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 -#define IMX7D_USB_MAIN_480M_CLK 61 -#define IMX7D_ARM_A7_ROOT_CLK 62 -#define IMX7D_ARM_A7_ROOT_SRC 63 -#define IMX7D_ARM_A7_ROOT_CG 64 -#define IMX7D_ARM_A7_ROOT_DIV 65 -#define IMX7D_ARM_M4_ROOT_CLK 66 -#define IMX7D_ARM_M4_ROOT_SRC 67 -#define IMX7D_ARM_M4_ROOT_CG 68 -#define IMX7D_ARM_M4_ROOT_DIV 69 -#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ -#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ -#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ -#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ -#define IMX7D_MAIN_AXI_ROOT_CLK 74 -#define IMX7D_MAIN_AXI_ROOT_SRC 75 -#define IMX7D_MAIN_AXI_ROOT_CG 76 -#define IMX7D_MAIN_AXI_ROOT_DIV 77 -#define IMX7D_DISP_AXI_ROOT_CLK 78 -#define IMX7D_DISP_AXI_ROOT_SRC 79 -#define IMX7D_DISP_AXI_ROOT_CG 80 -#define IMX7D_DISP_AXI_ROOT_DIV 81 -#define IMX7D_ENET_AXI_ROOT_CLK 82 -#define IMX7D_ENET_AXI_ROOT_SRC 83 -#define IMX7D_ENET_AXI_ROOT_CG 84 -#define IMX7D_ENET_AXI_ROOT_DIV 85 -#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 -#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 -#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 -#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 -#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 -#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 -#define IMX7D_AHB_CHANNEL_ROOT_CG 92 -#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 -#define IMX7D_DRAM_PHYM_ROOT_CLK 94 -#define IMX7D_DRAM_PHYM_ROOT_SRC 95 -#define IMX7D_DRAM_PHYM_ROOT_CG 96 -#define IMX7D_DRAM_PHYM_ROOT_DIV 97 -#define IMX7D_DRAM_ROOT_CLK 98 -#define IMX7D_DRAM_ROOT_SRC 99 -#define IMX7D_DRAM_ROOT_CG 100 -#define IMX7D_DRAM_ROOT_DIV 101 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 -#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 -#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 -#define IMX7D_DRAM_ALT_ROOT_CLK 106 -#define IMX7D_DRAM_ALT_ROOT_SRC 107 -#define IMX7D_DRAM_ALT_ROOT_CG 108 -#define IMX7D_DRAM_ALT_ROOT_DIV 109 -#define IMX7D_USB_HSIC_ROOT_CLK 110 -#define IMX7D_USB_HSIC_ROOT_SRC 111 -#define IMX7D_USB_HSIC_ROOT_CG 112 -#define IMX7D_USB_HSIC_ROOT_DIV 113 -#define IMX7D_PCIE_CTRL_ROOT_CLK 114 -#define IMX7D_PCIE_CTRL_ROOT_SRC 115 -#define IMX7D_PCIE_CTRL_ROOT_CG 116 -#define IMX7D_PCIE_CTRL_ROOT_DIV 117 -#define IMX7D_PCIE_PHY_ROOT_CLK 118 -#define IMX7D_PCIE_PHY_ROOT_SRC 119 -#define IMX7D_PCIE_PHY_ROOT_CG 120 -#define IMX7D_PCIE_PHY_ROOT_DIV 121 -#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 -#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 -#define IMX7D_EPDC_PIXEL_ROOT_CG 124 -#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 -#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 -#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 -#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 -#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 -#define IMX7D_MIPI_DSI_ROOT_CLK 130 -#define IMX7D_MIPI_DSI_ROOT_SRC 131 -#define IMX7D_MIPI_DSI_ROOT_CG 132 -#define IMX7D_MIPI_DSI_ROOT_DIV 133 -#define IMX7D_MIPI_CSI_ROOT_CLK 134 -#define IMX7D_MIPI_CSI_ROOT_SRC 135 -#define IMX7D_MIPI_CSI_ROOT_CG 136 -#define IMX7D_MIPI_CSI_ROOT_DIV 137 -#define IMX7D_MIPI_DPHY_ROOT_CLK 138 -#define IMX7D_MIPI_DPHY_ROOT_SRC 139 -#define IMX7D_MIPI_DPHY_ROOT_CG 140 -#define IMX7D_MIPI_DPHY_ROOT_DIV 141 -#define IMX7D_SAI1_ROOT_CLK 142 -#define IMX7D_SAI1_ROOT_SRC 143 -#define IMX7D_SAI1_ROOT_CG 144 -#define IMX7D_SAI1_ROOT_DIV 145 -#define IMX7D_SAI2_ROOT_CLK 146 -#define IMX7D_SAI2_ROOT_SRC 147 -#define IMX7D_SAI2_ROOT_CG 148 -#define IMX7D_SAI2_ROOT_DIV 149 -#define IMX7D_SAI3_ROOT_CLK 150 -#define IMX7D_SAI3_ROOT_SRC 151 -#define IMX7D_SAI3_ROOT_CG 152 -#define IMX7D_SAI3_ROOT_DIV 153 -#define IMX7D_SPDIF_ROOT_CLK 154 -#define IMX7D_SPDIF_ROOT_SRC 155 -#define IMX7D_SPDIF_ROOT_CG 156 -#define IMX7D_SPDIF_ROOT_DIV 157 -#define IMX7D_ENET1_IPG_ROOT_CLK 158 -#define IMX7D_ENET1_REF_ROOT_SRC 159 -#define IMX7D_ENET1_REF_ROOT_CG 160 -#define IMX7D_ENET1_REF_ROOT_DIV 161 -#define IMX7D_ENET1_TIME_ROOT_CLK 162 -#define IMX7D_ENET1_TIME_ROOT_SRC 163 -#define IMX7D_ENET1_TIME_ROOT_CG 164 -#define IMX7D_ENET1_TIME_ROOT_DIV 165 -#define IMX7D_ENET2_IPG_ROOT_CLK 166 -#define IMX7D_ENET2_REF_ROOT_SRC 167 -#define IMX7D_ENET2_REF_ROOT_CG 168 -#define IMX7D_ENET2_REF_ROOT_DIV 169 -#define IMX7D_ENET2_TIME_ROOT_CLK 170 -#define IMX7D_ENET2_TIME_ROOT_SRC 171 -#define IMX7D_ENET2_TIME_ROOT_CG 172 -#define IMX7D_ENET2_TIME_ROOT_DIV 173 -#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 -#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 -#define IMX7D_ENET_PHY_REF_ROOT_CG 176 -#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 -#define IMX7D_EIM_ROOT_CLK 178 -#define IMX7D_EIM_ROOT_SRC 179 -#define IMX7D_EIM_ROOT_CG 180 -#define IMX7D_EIM_ROOT_DIV 181 -#define IMX7D_NAND_ROOT_CLK 182 -#define IMX7D_NAND_ROOT_SRC 183 -#define IMX7D_NAND_ROOT_CG 184 -#define IMX7D_NAND_ROOT_DIV 185 -#define IMX7D_QSPI_ROOT_CLK 186 -#define IMX7D_QSPI_ROOT_SRC 187 -#define IMX7D_QSPI_ROOT_CG 188 -#define IMX7D_QSPI_ROOT_DIV 189 -#define IMX7D_USDHC1_ROOT_CLK 190 -#define IMX7D_USDHC1_ROOT_SRC 191 -#define IMX7D_USDHC1_ROOT_CG 192 -#define IMX7D_USDHC1_ROOT_DIV 193 -#define IMX7D_USDHC2_ROOT_CLK 194 -#define IMX7D_USDHC2_ROOT_SRC 195 -#define IMX7D_USDHC2_ROOT_CG 196 -#define IMX7D_USDHC2_ROOT_DIV 197 -#define IMX7D_USDHC3_ROOT_CLK 198 -#define IMX7D_USDHC3_ROOT_SRC 199 -#define IMX7D_USDHC3_ROOT_CG 200 -#define IMX7D_USDHC3_ROOT_DIV 201 -#define IMX7D_CAN1_ROOT_CLK 202 -#define IMX7D_CAN1_ROOT_SRC 203 -#define IMX7D_CAN1_ROOT_CG 204 -#define IMX7D_CAN1_ROOT_DIV 205 -#define IMX7D_CAN2_ROOT_CLK 206 -#define IMX7D_CAN2_ROOT_SRC 207 -#define IMX7D_CAN2_ROOT_CG 208 -#define IMX7D_CAN2_ROOT_DIV 209 -#define IMX7D_I2C1_ROOT_CLK 210 -#define IMX7D_I2C1_ROOT_SRC 211 -#define IMX7D_I2C1_ROOT_CG 212 -#define IMX7D_I2C1_ROOT_DIV 213 -#define IMX7D_I2C2_ROOT_CLK 214 -#define IMX7D_I2C2_ROOT_SRC 215 -#define IMX7D_I2C2_ROOT_CG 216 -#define IMX7D_I2C2_ROOT_DIV 217 -#define IMX7D_I2C3_ROOT_CLK 218 -#define IMX7D_I2C3_ROOT_SRC 219 -#define IMX7D_I2C3_ROOT_CG 220 -#define IMX7D_I2C3_ROOT_DIV 221 -#define IMX7D_I2C4_ROOT_CLK 222 -#define IMX7D_I2C4_ROOT_SRC 223 -#define IMX7D_I2C4_ROOT_CG 224 -#define IMX7D_I2C4_ROOT_DIV 225 -#define IMX7D_UART1_ROOT_CLK 226 -#define IMX7D_UART1_ROOT_SRC 227 -#define IMX7D_UART1_ROOT_CG 228 -#define IMX7D_UART1_ROOT_DIV 229 -#define IMX7D_UART2_ROOT_CLK 230 -#define IMX7D_UART2_ROOT_SRC 231 -#define IMX7D_UART2_ROOT_CG 232 -#define IMX7D_UART2_ROOT_DIV 233 -#define IMX7D_UART3_ROOT_CLK 234 -#define IMX7D_UART3_ROOT_SRC 235 -#define IMX7D_UART3_ROOT_CG 236 -#define IMX7D_UART3_ROOT_DIV 237 -#define IMX7D_UART4_ROOT_CLK 238 -#define IMX7D_UART4_ROOT_SRC 239 -#define IMX7D_UART4_ROOT_CG 240 -#define IMX7D_UART4_ROOT_DIV 241 -#define IMX7D_UART5_ROOT_CLK 242 -#define IMX7D_UART5_ROOT_SRC 243 -#define IMX7D_UART5_ROOT_CG 244 -#define IMX7D_UART5_ROOT_DIV 245 -#define IMX7D_UART6_ROOT_CLK 246 -#define IMX7D_UART6_ROOT_SRC 247 -#define IMX7D_UART6_ROOT_CG 248 -#define IMX7D_UART6_ROOT_DIV 249 -#define IMX7D_UART7_ROOT_CLK 250 -#define IMX7D_UART7_ROOT_SRC 251 -#define IMX7D_UART7_ROOT_CG 252 -#define IMX7D_UART7_ROOT_DIV 253 -#define IMX7D_ECSPI1_ROOT_CLK 254 -#define IMX7D_ECSPI1_ROOT_SRC 255 -#define IMX7D_ECSPI1_ROOT_CG 256 -#define IMX7D_ECSPI1_ROOT_DIV 257 -#define IMX7D_ECSPI2_ROOT_CLK 258 -#define IMX7D_ECSPI2_ROOT_SRC 259 -#define IMX7D_ECSPI2_ROOT_CG 260 -#define IMX7D_ECSPI2_ROOT_DIV 261 -#define IMX7D_ECSPI3_ROOT_CLK 262 -#define IMX7D_ECSPI3_ROOT_SRC 263 -#define IMX7D_ECSPI3_ROOT_CG 264 -#define IMX7D_ECSPI3_ROOT_DIV 265 -#define IMX7D_ECSPI4_ROOT_CLK 266 -#define IMX7D_ECSPI4_ROOT_SRC 267 -#define IMX7D_ECSPI4_ROOT_CG 268 -#define IMX7D_ECSPI4_ROOT_DIV 269 -#define IMX7D_PWM1_ROOT_CLK 270 -#define IMX7D_PWM1_ROOT_SRC 271 -#define IMX7D_PWM1_ROOT_CG 272 -#define IMX7D_PWM1_ROOT_DIV 273 -#define IMX7D_PWM2_ROOT_CLK 274 -#define IMX7D_PWM2_ROOT_SRC 275 -#define IMX7D_PWM2_ROOT_CG 276 -#define IMX7D_PWM2_ROOT_DIV 277 -#define IMX7D_PWM3_ROOT_CLK 278 -#define IMX7D_PWM3_ROOT_SRC 279 -#define IMX7D_PWM3_ROOT_CG 280 -#define IMX7D_PWM3_ROOT_DIV 281 -#define IMX7D_PWM4_ROOT_CLK 282 -#define IMX7D_PWM4_ROOT_SRC 283 -#define IMX7D_PWM4_ROOT_CG 284 -#define IMX7D_PWM4_ROOT_DIV 285 -#define IMX7D_FLEXTIMER1_ROOT_CLK 286 -#define IMX7D_FLEXTIMER1_ROOT_SRC 287 -#define IMX7D_FLEXTIMER1_ROOT_CG 288 -#define IMX7D_FLEXTIMER1_ROOT_DIV 289 -#define IMX7D_FLEXTIMER2_ROOT_CLK 290 -#define IMX7D_FLEXTIMER2_ROOT_SRC 291 -#define IMX7D_FLEXTIMER2_ROOT_CG 292 -#define IMX7D_FLEXTIMER2_ROOT_DIV 293 -#define IMX7D_SIM1_ROOT_CLK 294 -#define IMX7D_SIM1_ROOT_SRC 295 -#define IMX7D_SIM1_ROOT_CG 296 -#define IMX7D_SIM1_ROOT_DIV 297 -#define IMX7D_SIM2_ROOT_CLK 298 -#define IMX7D_SIM2_ROOT_SRC 299 -#define IMX7D_SIM2_ROOT_CG 300 -#define IMX7D_SIM2_ROOT_DIV 301 -#define IMX7D_GPT1_ROOT_CLK 302 -#define IMX7D_GPT1_ROOT_SRC 303 -#define IMX7D_GPT1_ROOT_CG 304 -#define IMX7D_GPT1_ROOT_DIV 305 -#define IMX7D_GPT2_ROOT_CLK 306 -#define IMX7D_GPT2_ROOT_SRC 307 -#define IMX7D_GPT2_ROOT_CG 308 -#define IMX7D_GPT2_ROOT_DIV 309 -#define IMX7D_GPT3_ROOT_CLK 310 -#define IMX7D_GPT3_ROOT_SRC 311 -#define IMX7D_GPT3_ROOT_CG 312 -#define IMX7D_GPT3_ROOT_DIV 313 -#define IMX7D_GPT4_ROOT_CLK 314 -#define IMX7D_GPT4_ROOT_SRC 315 -#define IMX7D_GPT4_ROOT_CG 316 -#define IMX7D_GPT4_ROOT_DIV 317 -#define IMX7D_TRACE_ROOT_CLK 318 -#define IMX7D_TRACE_ROOT_SRC 319 -#define IMX7D_TRACE_ROOT_CG 320 -#define IMX7D_TRACE_ROOT_DIV 321 -#define IMX7D_WDOG1_ROOT_CLK 322 -#define IMX7D_WDOG_ROOT_SRC 323 -#define IMX7D_WDOG_ROOT_CG 324 -#define IMX7D_WDOG_ROOT_DIV 325 -#define IMX7D_CSI_MCLK_ROOT_CLK 326 -#define IMX7D_CSI_MCLK_ROOT_SRC 327 -#define IMX7D_CSI_MCLK_ROOT_CG 328 -#define IMX7D_CSI_MCLK_ROOT_DIV 329 -#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 -#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 -#define IMX7D_AUDIO_MCLK_ROOT_CG 332 -#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 -#define IMX7D_WRCLK_ROOT_CLK 334 -#define IMX7D_WRCLK_ROOT_SRC 335 -#define IMX7D_WRCLK_ROOT_CG 336 -#define IMX7D_WRCLK_ROOT_DIV 337 -#define IMX7D_CLKO1_ROOT_SRC 338 -#define IMX7D_CLKO1_ROOT_CG 339 -#define IMX7D_CLKO1_ROOT_DIV 340 -#define IMX7D_CLKO2_ROOT_SRC 341 -#define IMX7D_CLKO2_ROOT_CG 342 -#define IMX7D_CLKO2_ROOT_DIV 343 -#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 -#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 -#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 -#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 -#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 -#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 -#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 -#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 -#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 -#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 -#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 -#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 -#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 -#define IMX7D_SAI1_ROOT_PRE_DIV 357 -#define IMX7D_SAI2_ROOT_PRE_DIV 358 -#define IMX7D_SAI3_ROOT_PRE_DIV 359 -#define IMX7D_SPDIF_ROOT_PRE_DIV 360 -#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 -#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 -#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 -#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 -#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 -#define IMX7D_EIM_ROOT_PRE_DIV 366 -#define IMX7D_NAND_ROOT_PRE_DIV 367 -#define IMX7D_QSPI_ROOT_PRE_DIV 368 -#define IMX7D_USDHC1_ROOT_PRE_DIV 369 -#define IMX7D_USDHC2_ROOT_PRE_DIV 370 -#define IMX7D_USDHC3_ROOT_PRE_DIV 371 -#define IMX7D_CAN1_ROOT_PRE_DIV 372 -#define IMX7D_CAN2_ROOT_PRE_DIV 373 -#define IMX7D_I2C1_ROOT_PRE_DIV 374 -#define IMX7D_I2C2_ROOT_PRE_DIV 375 -#define IMX7D_I2C3_ROOT_PRE_DIV 376 -#define IMX7D_I2C4_ROOT_PRE_DIV 377 -#define IMX7D_UART1_ROOT_PRE_DIV 378 -#define IMX7D_UART2_ROOT_PRE_DIV 379 -#define IMX7D_UART3_ROOT_PRE_DIV 380 -#define IMX7D_UART4_ROOT_PRE_DIV 381 -#define IMX7D_UART5_ROOT_PRE_DIV 382 -#define IMX7D_UART6_ROOT_PRE_DIV 383 -#define IMX7D_UART7_ROOT_PRE_DIV 384 -#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 -#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 -#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 -#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 -#define IMX7D_PWM1_ROOT_PRE_DIV 389 -#define IMX7D_PWM2_ROOT_PRE_DIV 390 -#define IMX7D_PWM3_ROOT_PRE_DIV 391 -#define IMX7D_PWM4_ROOT_PRE_DIV 392 -#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 -#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 -#define IMX7D_SIM1_ROOT_PRE_DIV 395 -#define IMX7D_SIM2_ROOT_PRE_DIV 396 -#define IMX7D_GPT1_ROOT_PRE_DIV 397 -#define IMX7D_GPT2_ROOT_PRE_DIV 398 -#define IMX7D_GPT3_ROOT_PRE_DIV 399 -#define IMX7D_GPT4_ROOT_PRE_DIV 400 -#define IMX7D_TRACE_ROOT_PRE_DIV 401 -#define IMX7D_WDOG_ROOT_PRE_DIV 402 -#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 -#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 -#define IMX7D_WRCLK_ROOT_PRE_DIV 405 -#define IMX7D_CLKO1_ROOT_PRE_DIV 406 -#define IMX7D_CLKO2_ROOT_PRE_DIV 407 -#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 -#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 -#define IMX7D_LVDS1_IN_CLK 410 -#define IMX7D_LVDS1_OUT_SEL 411 -#define IMX7D_LVDS1_OUT_CLK 412 -#define IMX7D_CLK_DUMMY 413 -#define IMX7D_GPT_3M_CLK 414 -#define IMX7D_OCRAM_CLK 415 -#define IMX7D_OCRAM_S_CLK 416 -#define IMX7D_WDOG2_ROOT_CLK 417 -#define IMX7D_WDOG3_ROOT_CLK 418 -#define IMX7D_WDOG4_ROOT_CLK 419 -#define IMX7D_SDMA_CORE_CLK 420 -#define IMX7D_USB1_MAIN_480M_CLK 421 -#define IMX7D_USB_CTRL_CLK 422 -#define IMX7D_USB_PHY1_CLK 423 -#define IMX7D_USB_PHY2_CLK 424 -#define IMX7D_IPG_ROOT_CLK 425 -#define IMX7D_SAI1_IPG_CLK 426 -#define IMX7D_SAI2_IPG_CLK 427 -#define IMX7D_SAI3_IPG_CLK 428 -#define IMX7D_PLL_AUDIO_TEST_DIV 429 -#define IMX7D_PLL_AUDIO_POST_DIV 430 -#define IMX7D_PLL_VIDEO_TEST_DIV 431 -#define IMX7D_PLL_VIDEO_POST_DIV 432 -#define IMX7D_MU_ROOT_CLK 433 -#define IMX7D_SEMA4_HS_ROOT_CLK 434 -#define IMX7D_PLL_DRAM_TEST_DIV 435 -#define IMX7D_ADC_ROOT_CLK 436 -#define IMX7D_CLK_ARM 437 -#define IMX7D_CKIL 438 -#define IMX7D_OCOTP_CLK 439 -#define IMX7D_NAND_RAWNAND_CLK 440 -#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 -#define IMX7D_SNVS_CLK 442 -#define IMX7D_CAAM_CLK 443 -#define IMX7D_KPP_ROOT_CLK 444 -#define IMX7D_PXP_CLK 445 -#define IMX7D_CLK_END 446 -#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h deleted file mode 100644 index b58370d146e..00000000000 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017~2018 NXP - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H -#define __DT_BINDINGS_CLOCK_IMX7ULP_H - -/* SCG1 */ - -#define IMX7ULP_CLK_DUMMY 0 -#define IMX7ULP_CLK_ROSC 1 -#define IMX7ULP_CLK_SOSC 2 -#define IMX7ULP_CLK_FIRC 3 -#define IMX7ULP_CLK_SPLL_PRE_SEL 4 -#define IMX7ULP_CLK_SPLL_PRE_DIV 5 -#define IMX7ULP_CLK_SPLL 6 -#define IMX7ULP_CLK_SPLL_POST_DIV1 7 -#define IMX7ULP_CLK_SPLL_POST_DIV2 8 -#define IMX7ULP_CLK_SPLL_PFD0 9 -#define IMX7ULP_CLK_SPLL_PFD1 10 -#define IMX7ULP_CLK_SPLL_PFD2 11 -#define IMX7ULP_CLK_SPLL_PFD3 12 -#define IMX7ULP_CLK_SPLL_PFD_SEL 13 -#define IMX7ULP_CLK_SPLL_SEL 14 -#define IMX7ULP_CLK_APLL_PRE_SEL 15 -#define IMX7ULP_CLK_APLL_PRE_DIV 16 -#define IMX7ULP_CLK_APLL 17 -#define IMX7ULP_CLK_APLL_POST_DIV1 18 -#define IMX7ULP_CLK_APLL_POST_DIV2 19 -#define IMX7ULP_CLK_APLL_PFD0 20 -#define IMX7ULP_CLK_APLL_PFD1 21 -#define IMX7ULP_CLK_APLL_PFD2 22 -#define IMX7ULP_CLK_APLL_PFD3 23 -#define IMX7ULP_CLK_APLL_PFD_SEL 24 -#define IMX7ULP_CLK_APLL_SEL 25 -#define IMX7ULP_CLK_UPLL 26 -#define IMX7ULP_CLK_SYS_SEL 27 -#define IMX7ULP_CLK_CORE_DIV 28 -#define IMX7ULP_CLK_BUS_DIV 29 -#define IMX7ULP_CLK_PLAT_DIV 30 -#define IMX7ULP_CLK_DDR_SEL 31 -#define IMX7ULP_CLK_DDR_DIV 32 -#define IMX7ULP_CLK_NIC_SEL 33 -#define IMX7ULP_CLK_NIC0_DIV 34 -#define IMX7ULP_CLK_GPU_DIV 35 -#define IMX7ULP_CLK_NIC1_DIV 36 -#define IMX7ULP_CLK_NIC1_BUS_DIV 37 -#define IMX7ULP_CLK_NIC1_EXT_DIV 38 -/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ -#define IMX7ULP_CLK_MIPI_PLL 39 -#define IMX7ULP_CLK_SIRC 40 -#define IMX7ULP_CLK_SOSC_BUS_CLK 41 -#define IMX7ULP_CLK_FIRC_BUS_CLK 42 -#define IMX7ULP_CLK_SPLL_BUS_CLK 43 -#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 -#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 - -#define IMX7ULP_CLK_CORE 46 -#define IMX7ULP_CLK_HSRUN_CORE 47 - -#define IMX7ULP_CLK_SCG1_END 48 - -/* PCC2 */ -#define IMX7ULP_CLK_DMA1 0 -#define IMX7ULP_CLK_RGPIO2P1 1 -#define IMX7ULP_CLK_FLEXBUS 2 -#define IMX7ULP_CLK_SEMA42_1 3 -#define IMX7ULP_CLK_DMA_MUX1 4 -#define IMX7ULP_CLK_CAAM 6 -#define IMX7ULP_CLK_LPTPM4 7 -#define IMX7ULP_CLK_LPTPM5 8 -#define IMX7ULP_CLK_LPIT1 9 -#define IMX7ULP_CLK_LPSPI2 10 -#define IMX7ULP_CLK_LPSPI3 11 -#define IMX7ULP_CLK_LPI2C4 12 -#define IMX7ULP_CLK_LPI2C5 13 -#define IMX7ULP_CLK_LPUART4 14 -#define IMX7ULP_CLK_LPUART5 15 -#define IMX7ULP_CLK_FLEXIO1 16 -#define IMX7ULP_CLK_USB0 17 -#define IMX7ULP_CLK_USB1 18 -#define IMX7ULP_CLK_USB_PHY 19 -#define IMX7ULP_CLK_USB_PL301 20 -#define IMX7ULP_CLK_USDHC0 21 -#define IMX7ULP_CLK_USDHC1 22 -#define IMX7ULP_CLK_WDG1 23 -#define IMX7ULP_CLK_WDG2 24 - -#define IMX7ULP_CLK_PCC2_END 25 - -/* PCC3 */ -#define IMX7ULP_CLK_LPTPM6 0 -#define IMX7ULP_CLK_LPTPM7 1 -#define IMX7ULP_CLK_LPI2C6 2 -#define IMX7ULP_CLK_LPI2C7 3 -#define IMX7ULP_CLK_LPUART6 4 -#define IMX7ULP_CLK_LPUART7 5 -#define IMX7ULP_CLK_VIU 6 -#define IMX7ULP_CLK_DSI 7 -#define IMX7ULP_CLK_LCDIF 8 -#define IMX7ULP_CLK_MMDC 9 -#define IMX7ULP_CLK_PCTLC 10 -#define IMX7ULP_CLK_PCTLD 11 -#define IMX7ULP_CLK_PCTLE 12 -#define IMX7ULP_CLK_PCTLF 13 -#define IMX7ULP_CLK_GPU3D 14 -#define IMX7ULP_CLK_GPU2D 15 - -#define IMX7ULP_CLK_PCC3_END 16 - -/* SMC1 */ -#define IMX7ULP_CLK_ARM 0 - -#define IMX7ULP_CLK_SMC1_END 1 - -#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h deleted file mode 100644 index 1f768b2eeb1..00000000000 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ /dev/null @@ -1,286 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2017-2018 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H -#define __DT_BINDINGS_CLOCK_IMX8MM_H - -#define IMX8MM_CLK_DUMMY 0 -#define IMX8MM_CLK_32K 1 -#define IMX8MM_CLK_24M 2 -#define IMX8MM_OSC_HDMI_CLK 3 -#define IMX8MM_CLK_EXT1 4 -#define IMX8MM_CLK_EXT2 5 -#define IMX8MM_CLK_EXT3 6 -#define IMX8MM_CLK_EXT4 7 -#define IMX8MM_AUDIO_PLL1_REF_SEL 8 -#define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 -#define IMX8MM_DRAM_PLL_REF_SEL 11 -#define IMX8MM_GPU_PLL_REF_SEL 12 -#define IMX8MM_VPU_PLL_REF_SEL 13 -#define IMX8MM_ARM_PLL_REF_SEL 14 -#define IMX8MM_SYS_PLL1_REF_SEL 15 -#define IMX8MM_SYS_PLL2_REF_SEL 16 -#define IMX8MM_SYS_PLL3_REF_SEL 17 -#define IMX8MM_AUDIO_PLL1 18 -#define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 -#define IMX8MM_DRAM_PLL 21 -#define IMX8MM_GPU_PLL 22 -#define IMX8MM_VPU_PLL 23 -#define IMX8MM_ARM_PLL 24 -#define IMX8MM_SYS_PLL1 25 -#define IMX8MM_SYS_PLL2 26 -#define IMX8MM_SYS_PLL3 27 -#define IMX8MM_AUDIO_PLL1_BYPASS 28 -#define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 -#define IMX8MM_DRAM_PLL_BYPASS 31 -#define IMX8MM_GPU_PLL_BYPASS 32 -#define IMX8MM_VPU_PLL_BYPASS 33 -#define IMX8MM_ARM_PLL_BYPASS 34 -#define IMX8MM_SYS_PLL1_BYPASS 35 -#define IMX8MM_SYS_PLL2_BYPASS 36 -#define IMX8MM_SYS_PLL3_BYPASS 37 -#define IMX8MM_AUDIO_PLL1_OUT 38 -#define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 -#define IMX8MM_DRAM_PLL_OUT 41 -#define IMX8MM_GPU_PLL_OUT 42 -#define IMX8MM_VPU_PLL_OUT 43 -#define IMX8MM_ARM_PLL_OUT 44 -#define IMX8MM_SYS_PLL1_OUT 45 -#define IMX8MM_SYS_PLL2_OUT 46 -#define IMX8MM_SYS_PLL3_OUT 47 -#define IMX8MM_SYS_PLL1_40M 48 -#define IMX8MM_SYS_PLL1_80M 49 -#define IMX8MM_SYS_PLL1_100M 50 -#define IMX8MM_SYS_PLL1_133M 51 -#define IMX8MM_SYS_PLL1_160M 52 -#define IMX8MM_SYS_PLL1_200M 53 -#define IMX8MM_SYS_PLL1_266M 54 -#define IMX8MM_SYS_PLL1_400M 55 -#define IMX8MM_SYS_PLL1_800M 56 -#define IMX8MM_SYS_PLL2_50M 57 -#define IMX8MM_SYS_PLL2_100M 58 -#define IMX8MM_SYS_PLL2_125M 59 -#define IMX8MM_SYS_PLL2_166M 60 -#define IMX8MM_SYS_PLL2_200M 61 -#define IMX8MM_SYS_PLL2_250M 62 -#define IMX8MM_SYS_PLL2_333M 63 -#define IMX8MM_SYS_PLL2_500M 64 -#define IMX8MM_SYS_PLL2_1000M 65 - -/* core */ -#define IMX8MM_CLK_A53_SRC 66 -#define IMX8MM_CLK_M4_SRC 67 -#define IMX8MM_CLK_VPU_SRC 68 -#define IMX8MM_CLK_GPU3D_SRC 69 -#define IMX8MM_CLK_GPU2D_SRC 70 -#define IMX8MM_CLK_A53_CG 71 -#define IMX8MM_CLK_M4_CG 72 -#define IMX8MM_CLK_VPU_CG 73 -#define IMX8MM_CLK_GPU3D_CG 74 -#define IMX8MM_CLK_GPU2D_CG 75 -#define IMX8MM_CLK_A53_DIV 76 -#define IMX8MM_CLK_M4_DIV 77 -#define IMX8MM_CLK_VPU_DIV 78 -#define IMX8MM_CLK_GPU3D_DIV 79 -#define IMX8MM_CLK_GPU2D_DIV 80 - -/* bus */ -#define IMX8MM_CLK_MAIN_AXI 81 -#define IMX8MM_CLK_ENET_AXI 82 -#define IMX8MM_CLK_NAND_USDHC_BUS 83 -#define IMX8MM_CLK_VPU_BUS 84 -#define IMX8MM_CLK_DISP_AXI 85 -#define IMX8MM_CLK_DISP_APB 86 -#define IMX8MM_CLK_DISP_RTRM 87 -#define IMX8MM_CLK_USB_BUS 88 -#define IMX8MM_CLK_GPU_AXI 89 -#define IMX8MM_CLK_GPU_AHB 90 -#define IMX8MM_CLK_NOC 91 -#define IMX8MM_CLK_NOC_APB 92 - -#define IMX8MM_CLK_AHB 93 -#define IMX8MM_CLK_AUDIO_AHB 94 -#define IMX8MM_CLK_IPG_ROOT 95 -#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 - -#define IMX8MM_CLK_DRAM_ALT 97 -#define IMX8MM_CLK_DRAM_APB 98 -#define IMX8MM_CLK_VPU_G1 99 -#define IMX8MM_CLK_VPU_G2 100 -#define IMX8MM_CLK_DISP_DTRC 101 -#define IMX8MM_CLK_DISP_DC8000 102 -#define IMX8MM_CLK_PCIE1_CTRL 103 -#define IMX8MM_CLK_PCIE1_PHY 104 -#define IMX8MM_CLK_PCIE1_AUX 105 -#define IMX8MM_CLK_DC_PIXEL 106 -#define IMX8MM_CLK_LCDIF_PIXEL 107 -#define IMX8MM_CLK_SAI1 108 -#define IMX8MM_CLK_SAI2 109 -#define IMX8MM_CLK_SAI3 110 -#define IMX8MM_CLK_SAI4 111 -#define IMX8MM_CLK_SAI5 112 -#define IMX8MM_CLK_SAI6 113 -#define IMX8MM_CLK_SPDIF1 114 -#define IMX8MM_CLK_SPDIF2 115 -#define IMX8MM_CLK_ENET_REF 116 -#define IMX8MM_CLK_ENET_TIMER 117 -#define IMX8MM_CLK_ENET_PHY_REF 118 -#define IMX8MM_CLK_NAND 119 -#define IMX8MM_CLK_QSPI 120 -#define IMX8MM_CLK_USDHC1 121 -#define IMX8MM_CLK_USDHC2 122 -#define IMX8MM_CLK_I2C1 123 -#define IMX8MM_CLK_I2C2 124 -#define IMX8MM_CLK_I2C3 125 -#define IMX8MM_CLK_I2C4 126 -#define IMX8MM_CLK_UART1 127 -#define IMX8MM_CLK_UART2 128 -#define IMX8MM_CLK_UART3 129 -#define IMX8MM_CLK_UART4 130 -#define IMX8MM_CLK_USB_CORE_REF 131 -#define IMX8MM_CLK_USB_PHY_REF 132 -#define IMX8MM_CLK_ECSPI1 133 -#define IMX8MM_CLK_ECSPI2 134 -#define IMX8MM_CLK_PWM1 135 -#define IMX8MM_CLK_PWM2 136 -#define IMX8MM_CLK_PWM3 137 -#define IMX8MM_CLK_PWM4 138 -#define IMX8MM_CLK_GPT1 139 -#define IMX8MM_CLK_WDOG 140 -#define IMX8MM_CLK_WRCLK 141 -#define IMX8MM_CLK_DSI_CORE 142 -#define IMX8MM_CLK_DSI_PHY_REF 143 -#define IMX8MM_CLK_DSI_DBI 144 -#define IMX8MM_CLK_USDHC3 145 -#define IMX8MM_CLK_CSI1_CORE 146 -#define IMX8MM_CLK_CSI1_PHY_REF 147 -#define IMX8MM_CLK_CSI1_ESC 148 -#define IMX8MM_CLK_CSI2_CORE 149 -#define IMX8MM_CLK_CSI2_PHY_REF 150 -#define IMX8MM_CLK_CSI2_ESC 151 -#define IMX8MM_CLK_PCIE2_CTRL 152 -#define IMX8MM_CLK_PCIE2_PHY 153 -#define IMX8MM_CLK_PCIE2_AUX 154 -#define IMX8MM_CLK_ECSPI3 155 -#define IMX8MM_CLK_PDM 156 -#define IMX8MM_CLK_VPU_H1 157 -#define IMX8MM_CLK_CLKO1 158 - -#define IMX8MM_CLK_ECSPI1_ROOT 159 -#define IMX8MM_CLK_ECSPI2_ROOT 160 -#define IMX8MM_CLK_ECSPI3_ROOT 161 -#define IMX8MM_CLK_ENET1_ROOT 162 -#define IMX8MM_CLK_GPT1_ROOT 163 -#define IMX8MM_CLK_I2C1_ROOT 164 -#define IMX8MM_CLK_I2C2_ROOT 165 -#define IMX8MM_CLK_I2C3_ROOT 166 -#define IMX8MM_CLK_I2C4_ROOT 167 -#define IMX8MM_CLK_OCOTP_ROOT 168 -#define IMX8MM_CLK_PCIE1_ROOT 169 -#define IMX8MM_CLK_PWM1_ROOT 170 -#define IMX8MM_CLK_PWM2_ROOT 171 -#define IMX8MM_CLK_PWM3_ROOT 172 -#define IMX8MM_CLK_PWM4_ROOT 173 -#define IMX8MM_CLK_QSPI_ROOT 174 -#define IMX8MM_CLK_NAND_ROOT 175 -#define IMX8MM_CLK_SAI1_ROOT 176 -#define IMX8MM_CLK_SAI1_IPG 177 -#define IMX8MM_CLK_SAI2_ROOT 178 -#define IMX8MM_CLK_SAI2_IPG 179 -#define IMX8MM_CLK_SAI3_ROOT 180 -#define IMX8MM_CLK_SAI3_IPG 181 -#define IMX8MM_CLK_SAI4_ROOT 182 -#define IMX8MM_CLK_SAI4_IPG 183 -#define IMX8MM_CLK_SAI5_ROOT 184 -#define IMX8MM_CLK_SAI5_IPG 185 -#define IMX8MM_CLK_SAI6_ROOT 186 -#define IMX8MM_CLK_SAI6_IPG 187 -#define IMX8MM_CLK_UART1_ROOT 188 -#define IMX8MM_CLK_UART2_ROOT 189 -#define IMX8MM_CLK_UART3_ROOT 190 -#define IMX8MM_CLK_UART4_ROOT 191 -#define IMX8MM_CLK_USB1_CTRL_ROOT 192 -#define IMX8MM_CLK_GPU3D_ROOT 193 -#define IMX8MM_CLK_USDHC1_ROOT 194 -#define IMX8MM_CLK_USDHC2_ROOT 195 -#define IMX8MM_CLK_WDOG1_ROOT 196 -#define IMX8MM_CLK_WDOG2_ROOT 197 -#define IMX8MM_CLK_WDOG3_ROOT 198 -#define IMX8MM_CLK_VPU_G1_ROOT 199 -#define IMX8MM_CLK_GPU_BUS_ROOT 200 -#define IMX8MM_CLK_VPU_H1_ROOT 201 -#define IMX8MM_CLK_VPU_G2_ROOT 202 -#define IMX8MM_CLK_PDM_ROOT 203 -#define IMX8MM_CLK_DISP_ROOT 204 -#define IMX8MM_CLK_DISP_AXI_ROOT 205 -#define IMX8MM_CLK_DISP_APB_ROOT 206 -#define IMX8MM_CLK_DISP_RTRM_ROOT 207 -#define IMX8MM_CLK_USDHC3_ROOT 208 -#define IMX8MM_CLK_TMU_ROOT 209 -#define IMX8MM_CLK_VPU_DEC_ROOT 210 -#define IMX8MM_CLK_SDMA1_ROOT 211 -#define IMX8MM_CLK_SDMA2_ROOT 212 -#define IMX8MM_CLK_SDMA3_ROOT 213 -#define IMX8MM_CLK_GPT_3M 214 -#define IMX8MM_CLK_ARM 215 -#define IMX8MM_CLK_PDM_IPG 216 -#define IMX8MM_CLK_GPU2D_ROOT 217 -#define IMX8MM_CLK_MU_ROOT 218 -#define IMX8MM_CLK_CSI1_ROOT 219 - -#define IMX8MM_CLK_DRAM_CORE 220 -#define IMX8MM_CLK_DRAM_ALT_ROOT 221 - -#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 - -#define IMX8MM_CLK_GPIO1_ROOT 223 -#define IMX8MM_CLK_GPIO2_ROOT 224 -#define IMX8MM_CLK_GPIO3_ROOT 225 -#define IMX8MM_CLK_GPIO4_ROOT 226 -#define IMX8MM_CLK_GPIO5_ROOT 227 - -#define IMX8MM_CLK_SNVS_ROOT 228 -#define IMX8MM_CLK_GIC 229 - -#define IMX8MM_SYS_PLL1_40M_CG 230 -#define IMX8MM_SYS_PLL1_80M_CG 231 -#define IMX8MM_SYS_PLL1_100M_CG 232 -#define IMX8MM_SYS_PLL1_133M_CG 233 -#define IMX8MM_SYS_PLL1_160M_CG 234 -#define IMX8MM_SYS_PLL1_200M_CG 235 -#define IMX8MM_SYS_PLL1_266M_CG 236 -#define IMX8MM_SYS_PLL1_400M_CG 237 -#define IMX8MM_SYS_PLL2_50M_CG 238 -#define IMX8MM_SYS_PLL2_100M_CG 239 -#define IMX8MM_SYS_PLL2_125M_CG 240 -#define IMX8MM_SYS_PLL2_166M_CG 241 -#define IMX8MM_SYS_PLL2_200M_CG 242 -#define IMX8MM_SYS_PLL2_250M_CG 243 -#define IMX8MM_SYS_PLL2_333M_CG 244 -#define IMX8MM_SYS_PLL2_500M_CG 245 - -#define IMX8MM_CLK_M4_CORE 246 -#define IMX8MM_CLK_VPU_CORE 247 -#define IMX8MM_CLK_GPU3D_CORE 248 -#define IMX8MM_CLK_GPU2D_CORE 249 - -#define IMX8MM_CLK_CLKO2 250 - -#define IMX8MM_CLK_A53_CORE 251 - -#define IMX8MM_CLK_CLKOUT1_SEL 252 -#define IMX8MM_CLK_CLKOUT1_DIV 253 -#define IMX8MM_CLK_CLKOUT1 254 -#define IMX8MM_CLK_CLKOUT2_SEL 255 -#define IMX8MM_CLK_CLKOUT2_DIV 256 -#define IMX8MM_CLK_CLKOUT2 257 - -#define IMX8MM_CLK_END 258 - -#endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h deleted file mode 100644 index 07b8a282c26..00000000000 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H -#define __DT_BINDINGS_CLOCK_IMX8MN_H - -#define IMX8MN_CLK_DUMMY 0 -#define IMX8MN_CLK_32K 1 -#define IMX8MN_CLK_24M 2 -#define IMX8MN_OSC_HDMI_CLK 3 -#define IMX8MN_CLK_EXT1 4 -#define IMX8MN_CLK_EXT2 5 -#define IMX8MN_CLK_EXT3 6 -#define IMX8MN_CLK_EXT4 7 -#define IMX8MN_AUDIO_PLL1_REF_SEL 8 -#define IMX8MN_AUDIO_PLL2_REF_SEL 9 -#define IMX8MN_VIDEO_PLL1_REF_SEL 10 -#define IMX8MN_DRAM_PLL_REF_SEL 11 -#define IMX8MN_GPU_PLL_REF_SEL 12 -#define IMX8MN_VPU_PLL_REF_SEL 13 -#define IMX8MN_ARM_PLL_REF_SEL 14 -#define IMX8MN_SYS_PLL1_REF_SEL 15 -#define IMX8MN_SYS_PLL2_REF_SEL 16 -#define IMX8MN_SYS_PLL3_REF_SEL 17 -#define IMX8MN_AUDIO_PLL1 18 -#define IMX8MN_AUDIO_PLL2 19 -#define IMX8MN_VIDEO_PLL1 20 -#define IMX8MN_DRAM_PLL 21 -#define IMX8MN_GPU_PLL 22 -#define IMX8MN_VPU_PLL 23 -#define IMX8MN_ARM_PLL 24 -#define IMX8MN_SYS_PLL1 25 -#define IMX8MN_SYS_PLL2 26 -#define IMX8MN_SYS_PLL3 27 -#define IMX8MN_AUDIO_PLL1_BYPASS 28 -#define IMX8MN_AUDIO_PLL2_BYPASS 29 -#define IMX8MN_VIDEO_PLL1_BYPASS 30 -#define IMX8MN_DRAM_PLL_BYPASS 31 -#define IMX8MN_GPU_PLL_BYPASS 32 -#define IMX8MN_VPU_PLL_BYPASS 33 -#define IMX8MN_ARM_PLL_BYPASS 34 -#define IMX8MN_SYS_PLL1_BYPASS 35 -#define IMX8MN_SYS_PLL2_BYPASS 36 -#define IMX8MN_SYS_PLL3_BYPASS 37 -#define IMX8MN_AUDIO_PLL1_OUT 38 -#define IMX8MN_AUDIO_PLL2_OUT 39 -#define IMX8MN_VIDEO_PLL1_OUT 40 -#define IMX8MN_DRAM_PLL_OUT 41 -#define IMX8MN_GPU_PLL_OUT 42 -#define IMX8MN_VPU_PLL_OUT 43 -#define IMX8MN_ARM_PLL_OUT 44 -#define IMX8MN_SYS_PLL1_OUT 45 -#define IMX8MN_SYS_PLL2_OUT 46 -#define IMX8MN_SYS_PLL3_OUT 47 -#define IMX8MN_SYS_PLL1_40M 48 -#define IMX8MN_SYS_PLL1_80M 49 -#define IMX8MN_SYS_PLL1_100M 50 -#define IMX8MN_SYS_PLL1_133M 51 -#define IMX8MN_SYS_PLL1_160M 52 -#define IMX8MN_SYS_PLL1_200M 53 -#define IMX8MN_SYS_PLL1_266M 54 -#define IMX8MN_SYS_PLL1_400M 55 -#define IMX8MN_SYS_PLL1_800M 56 -#define IMX8MN_SYS_PLL2_50M 57 -#define IMX8MN_SYS_PLL2_100M 58 -#define IMX8MN_SYS_PLL2_125M 59 -#define IMX8MN_SYS_PLL2_166M 60 -#define IMX8MN_SYS_PLL2_200M 61 -#define IMX8MN_SYS_PLL2_250M 62 -#define IMX8MN_SYS_PLL2_333M 63 -#define IMX8MN_SYS_PLL2_500M 64 -#define IMX8MN_SYS_PLL2_1000M 65 - -/* CORE CLOCK ROOT */ -#define IMX8MN_CLK_A53_SRC 66 -#define IMX8MN_CLK_GPU_CORE_SRC 67 -#define IMX8MN_CLK_GPU_SHADER_SRC 68 -#define IMX8MN_CLK_A53_CG 69 -#define IMX8MN_CLK_GPU_CORE_CG 70 -#define IMX8MN_CLK_GPU_SHADER_CG 71 -#define IMX8MN_CLK_A53_DIV 72 -#define IMX8MN_CLK_GPU_CORE_DIV 73 -#define IMX8MN_CLK_GPU_SHADER_DIV 74 - -/* BUS CLOCK ROOT */ -#define IMX8MN_CLK_MAIN_AXI 75 -#define IMX8MN_CLK_ENET_AXI 76 -#define IMX8MN_CLK_NAND_USDHC_BUS 77 -#define IMX8MN_CLK_DISP_AXI 78 -#define IMX8MN_CLK_DISP_APB 79 -#define IMX8MN_CLK_USB_BUS 80 -#define IMX8MN_CLK_GPU_AXI 81 -#define IMX8MN_CLK_GPU_AHB 82 -#define IMX8MN_CLK_NOC 83 -#define IMX8MN_CLK_AHB 84 -#define IMX8MN_CLK_AUDIO_AHB 85 - -/* IPG CLOCK ROOT */ -#define IMX8MN_CLK_IPG_ROOT 86 -#define IMX8MN_CLK_IPG_AUDIO_ROOT 87 - -/* IP */ -#define IMX8MN_CLK_DRAM_CORE 88 -#define IMX8MN_CLK_DRAM_ALT 89 -#define IMX8MN_CLK_DRAM_APB 90 -#define IMX8MN_CLK_DRAM_ALT_ROOT 91 -#define IMX8MN_CLK_DISP_PIXEL 92 -#define IMX8MN_CLK_SAI2 93 -#define IMX8MN_CLK_SAI3 94 -#define IMX8MN_CLK_SAI5 95 -#define IMX8MN_CLK_SAI6 96 -#define IMX8MN_CLK_SPDIF1 97 -#define IMX8MN_CLK_ENET_REF 98 -#define IMX8MN_CLK_ENET_TIMER 99 -#define IMX8MN_CLK_ENET_PHY_REF 100 -#define IMX8MN_CLK_NAND 101 -#define IMX8MN_CLK_QSPI 102 -#define IMX8MN_CLK_USDHC1 103 -#define IMX8MN_CLK_USDHC2 104 -#define IMX8MN_CLK_I2C1 105 -#define IMX8MN_CLK_I2C2 106 -#define IMX8MN_CLK_I2C3 107 -#define IMX8MN_CLK_I2C4 108 -#define IMX8MN_CLK_UART1 109 -#define IMX8MN_CLK_UART2 110 -#define IMX8MN_CLK_UART3 111 -#define IMX8MN_CLK_UART4 112 -#define IMX8MN_CLK_USB_CORE_REF 113 -#define IMX8MN_CLK_USB_PHY_REF 114 -#define IMX8MN_CLK_ECSPI1 115 -#define IMX8MN_CLK_ECSPI2 116 -#define IMX8MN_CLK_PWM1 117 -#define IMX8MN_CLK_PWM2 118 -#define IMX8MN_CLK_PWM3 119 -#define IMX8MN_CLK_PWM4 120 -#define IMX8MN_CLK_WDOG 121 -#define IMX8MN_CLK_WRCLK 122 -#define IMX8MN_CLK_CLKO1 123 -#define IMX8MN_CLK_CLKO2 124 -#define IMX8MN_CLK_DSI_CORE 125 -#define IMX8MN_CLK_DSI_PHY_REF 126 -#define IMX8MN_CLK_DSI_DBI 127 -#define IMX8MN_CLK_USDHC3 128 -#define IMX8MN_CLK_CAMERA_PIXEL 129 -#define IMX8MN_CLK_CSI1_PHY_REF 130 -#define IMX8MN_CLK_CSI2_PHY_REF 131 -#define IMX8MN_CLK_CSI2_ESC 132 -#define IMX8MN_CLK_ECSPI3 133 -#define IMX8MN_CLK_PDM 134 -#define IMX8MN_CLK_SAI7 135 - -#define IMX8MN_CLK_ECSPI1_ROOT 136 -#define IMX8MN_CLK_ECSPI2_ROOT 137 -#define IMX8MN_CLK_ECSPI3_ROOT 138 -#define IMX8MN_CLK_ENET1_ROOT 139 -#define IMX8MN_CLK_GPIO1_ROOT 140 -#define IMX8MN_CLK_GPIO2_ROOT 141 -#define IMX8MN_CLK_GPIO3_ROOT 142 -#define IMX8MN_CLK_GPIO4_ROOT 143 -#define IMX8MN_CLK_GPIO5_ROOT 144 -#define IMX8MN_CLK_I2C1_ROOT 145 -#define IMX8MN_CLK_I2C2_ROOT 146 -#define IMX8MN_CLK_I2C3_ROOT 147 -#define IMX8MN_CLK_I2C4_ROOT 148 -#define IMX8MN_CLK_MU_ROOT 149 -#define IMX8MN_CLK_OCOTP_ROOT 150 -#define IMX8MN_CLK_PWM1_ROOT 151 -#define IMX8MN_CLK_PWM2_ROOT 152 -#define IMX8MN_CLK_PWM3_ROOT 153 -#define IMX8MN_CLK_PWM4_ROOT 154 -#define IMX8MN_CLK_QSPI_ROOT 155 -#define IMX8MN_CLK_NAND_ROOT 156 -#define IMX8MN_CLK_SAI2_ROOT 157 -#define IMX8MN_CLK_SAI2_IPG 158 -#define IMX8MN_CLK_SAI3_ROOT 159 -#define IMX8MN_CLK_SAI3_IPG 160 -#define IMX8MN_CLK_SAI5_ROOT 161 -#define IMX8MN_CLK_SAI5_IPG 162 -#define IMX8MN_CLK_SAI6_ROOT 163 -#define IMX8MN_CLK_SAI6_IPG 164 -#define IMX8MN_CLK_SAI7_ROOT 165 -#define IMX8MN_CLK_SAI7_IPG 166 -#define IMX8MN_CLK_SDMA1_ROOT 167 -#define IMX8MN_CLK_SDMA2_ROOT 168 -#define IMX8MN_CLK_UART1_ROOT 169 -#define IMX8MN_CLK_UART2_ROOT 170 -#define IMX8MN_CLK_UART3_ROOT 171 -#define IMX8MN_CLK_UART4_ROOT 172 -#define IMX8MN_CLK_USB1_CTRL_ROOT 173 -#define IMX8MN_CLK_USDHC1_ROOT 174 -#define IMX8MN_CLK_USDHC2_ROOT 175 -#define IMX8MN_CLK_WDOG1_ROOT 176 -#define IMX8MN_CLK_WDOG2_ROOT 177 -#define IMX8MN_CLK_WDOG3_ROOT 178 -#define IMX8MN_CLK_GPU_BUS_ROOT 179 -#define IMX8MN_CLK_ASRC_ROOT 180 -#define IMX8MN_CLK_GPU3D_ROOT 181 -#define IMX8MN_CLK_PDM_ROOT 182 -#define IMX8MN_CLK_PDM_IPG 183 -#define IMX8MN_CLK_DISP_AXI_ROOT 184 -#define IMX8MN_CLK_DISP_APB_ROOT 185 -#define IMX8MN_CLK_DISP_PIXEL_ROOT 186 -#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 -#define IMX8MN_CLK_USDHC3_ROOT 188 -#define IMX8MN_CLK_SDMA3_ROOT 189 -#define IMX8MN_CLK_TMU_ROOT 190 -#define IMX8MN_CLK_ARM 191 -#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 -#define IMX8MN_CLK_GPU_CORE_ROOT 193 -#define IMX8MN_CLK_GIC 194 - -#define IMX8MN_SYS_PLL1_40M_CG 195 -#define IMX8MN_SYS_PLL1_80M_CG 196 -#define IMX8MN_SYS_PLL1_100M_CG 197 -#define IMX8MN_SYS_PLL1_133M_CG 198 -#define IMX8MN_SYS_PLL1_160M_CG 199 -#define IMX8MN_SYS_PLL1_200M_CG 200 -#define IMX8MN_SYS_PLL1_266M_CG 201 -#define IMX8MN_SYS_PLL1_400M_CG 202 -#define IMX8MN_SYS_PLL2_50M_CG 203 -#define IMX8MN_SYS_PLL2_100M_CG 204 -#define IMX8MN_SYS_PLL2_125M_CG 205 -#define IMX8MN_SYS_PLL2_166M_CG 206 -#define IMX8MN_SYS_PLL2_200M_CG 207 -#define IMX8MN_SYS_PLL2_250M_CG 208 -#define IMX8MN_SYS_PLL2_333M_CG 209 -#define IMX8MN_SYS_PLL2_500M_CG 210 - -#define IMX8MN_CLK_SNVS_ROOT 211 -#define IMX8MN_CLK_GPU_CORE 212 -#define IMX8MN_CLK_GPU_SHADER 213 - -#define IMX8MN_CLK_A53_CORE 214 - -#define IMX8MN_CLK_CLKOUT1_SEL 215 -#define IMX8MN_CLK_CLKOUT1_DIV 216 -#define IMX8MN_CLK_CLKOUT1 217 -#define IMX8MN_CLK_CLKOUT2_SEL 218 -#define IMX8MN_CLK_CLKOUT2_DIV 219 -#define IMX8MN_CLK_CLKOUT2 220 - -#define IMX8MN_CLK_M7_CORE 221 - -#define IMX8MN_CLK_GPT_3M 222 -#define IMX8MN_CLK_GPT1 223 -#define IMX8MN_CLK_GPT1_ROOT 224 -#define IMX8MN_CLK_GPT2 225 -#define IMX8MN_CLK_GPT2_ROOT 226 -#define IMX8MN_CLK_GPT3 227 -#define IMX8MN_CLK_GPT3_ROOT 228 -#define IMX8MN_CLK_GPT4 229 -#define IMX8MN_CLK_GPT4_ROOT 230 -#define IMX8MN_CLK_GPT5 231 -#define IMX8MN_CLK_GPT5_ROOT 232 -#define IMX8MN_CLK_GPT6 233 -#define IMX8MN_CLK_GPT6_ROOT 234 - -#define IMX8MN_CLK_END 235 - -#endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h deleted file mode 100644 index 7da4243984b..00000000000 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ /dev/null @@ -1,401 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2019 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H -#define __DT_BINDINGS_CLOCK_IMX8MP_H - -#define IMX8MP_CLK_DUMMY 0 -#define IMX8MP_CLK_32K 1 -#define IMX8MP_CLK_24M 2 -#define IMX8MP_OSC_HDMI_CLK 3 -#define IMX8MP_CLK_EXT1 4 -#define IMX8MP_CLK_EXT2 5 -#define IMX8MP_CLK_EXT3 6 -#define IMX8MP_CLK_EXT4 7 -#define IMX8MP_AUDIO_PLL1_REF_SEL 8 -#define IMX8MP_AUDIO_PLL2_REF_SEL 9 -#define IMX8MP_VIDEO_PLL1_REF_SEL 10 -#define IMX8MP_DRAM_PLL_REF_SEL 11 -#define IMX8MP_GPU_PLL_REF_SEL 12 -#define IMX8MP_VPU_PLL_REF_SEL 13 -#define IMX8MP_ARM_PLL_REF_SEL 14 -#define IMX8MP_SYS_PLL1_REF_SEL 15 -#define IMX8MP_SYS_PLL2_REF_SEL 16 -#define IMX8MP_SYS_PLL3_REF_SEL 17 -#define IMX8MP_AUDIO_PLL1 18 -#define IMX8MP_AUDIO_PLL2 19 -#define IMX8MP_VIDEO_PLL1 20 -#define IMX8MP_DRAM_PLL 21 -#define IMX8MP_GPU_PLL 22 -#define IMX8MP_VPU_PLL 23 -#define IMX8MP_ARM_PLL 24 -#define IMX8MP_SYS_PLL1 25 -#define IMX8MP_SYS_PLL2 26 -#define IMX8MP_SYS_PLL3 27 -#define IMX8MP_AUDIO_PLL1_BYPASS 28 -#define IMX8MP_AUDIO_PLL2_BYPASS 29 -#define IMX8MP_VIDEO_PLL1_BYPASS 30 -#define IMX8MP_DRAM_PLL_BYPASS 31 -#define IMX8MP_GPU_PLL_BYPASS 32 -#define IMX8MP_VPU_PLL_BYPASS 33 -#define IMX8MP_ARM_PLL_BYPASS 34 -#define IMX8MP_SYS_PLL1_BYPASS 35 -#define IMX8MP_SYS_PLL2_BYPASS 36 -#define IMX8MP_SYS_PLL3_BYPASS 37 -#define IMX8MP_AUDIO_PLL1_OUT 38 -#define IMX8MP_AUDIO_PLL2_OUT 39 -#define IMX8MP_VIDEO_PLL1_OUT 40 -#define IMX8MP_DRAM_PLL_OUT 41 -#define IMX8MP_GPU_PLL_OUT 42 -#define IMX8MP_VPU_PLL_OUT 43 -#define IMX8MP_ARM_PLL_OUT 44 -#define IMX8MP_SYS_PLL1_OUT 45 -#define IMX8MP_SYS_PLL2_OUT 46 -#define IMX8MP_SYS_PLL3_OUT 47 -#define IMX8MP_SYS_PLL1_40M 48 -#define IMX8MP_SYS_PLL1_80M 49 -#define IMX8MP_SYS_PLL1_100M 50 -#define IMX8MP_SYS_PLL1_133M 51 -#define IMX8MP_SYS_PLL1_160M 52 -#define IMX8MP_SYS_PLL1_200M 53 -#define IMX8MP_SYS_PLL1_266M 54 -#define IMX8MP_SYS_PLL1_400M 55 -#define IMX8MP_SYS_PLL1_800M 56 -#define IMX8MP_SYS_PLL2_50M 57 -#define IMX8MP_SYS_PLL2_100M 58 -#define IMX8MP_SYS_PLL2_125M 59 -#define IMX8MP_SYS_PLL2_166M 60 -#define IMX8MP_SYS_PLL2_200M 61 -#define IMX8MP_SYS_PLL2_250M 62 -#define IMX8MP_SYS_PLL2_333M 63 -#define IMX8MP_SYS_PLL2_500M 64 -#define IMX8MP_SYS_PLL2_1000M 65 -#define IMX8MP_CLK_A53_SRC 66 -#define IMX8MP_CLK_M7_SRC 67 -#define IMX8MP_CLK_ML_SRC 68 -#define IMX8MP_CLK_GPU3D_CORE_SRC 69 -#define IMX8MP_CLK_GPU3D_SHADER_SRC 70 -#define IMX8MP_CLK_GPU2D_SRC 71 -#define IMX8MP_CLK_AUDIO_AXI_SRC 72 -#define IMX8MP_CLK_HSIO_AXI_SRC 73 -#define IMX8MP_CLK_MEDIA_ISP_SRC 74 -#define IMX8MP_CLK_A53_CG 75 -#define IMX8MP_CLK_M4_CG 76 -#define IMX8MP_CLK_ML_CG 77 -#define IMX8MP_CLK_GPU3D_CORE_CG 78 -#define IMX8MP_CLK_GPU3D_SHADER_CG 79 -#define IMX8MP_CLK_GPU2D_CG 80 -#define IMX8MP_CLK_AUDIO_AXI_CG 81 -#define IMX8MP_CLK_HSIO_AXI_CG 82 -#define IMX8MP_CLK_MEDIA_ISP_CG 83 -#define IMX8MP_CLK_A53_DIV 84 -#define IMX8MP_CLK_M7_DIV 85 -#define IMX8MP_CLK_ML_DIV 86 -#define IMX8MP_CLK_GPU3D_CORE_DIV 87 -#define IMX8MP_CLK_GPU3D_SHADER_DIV 88 -#define IMX8MP_CLK_GPU2D_DIV 89 -#define IMX8MP_CLK_AUDIO_AXI_DIV 90 -#define IMX8MP_CLK_HSIO_AXI_DIV 91 -#define IMX8MP_CLK_MEDIA_ISP_DIV 92 -#define IMX8MP_CLK_MAIN_AXI 93 -#define IMX8MP_CLK_ENET_AXI 94 -#define IMX8MP_CLK_NAND_USDHC_BUS 95 -#define IMX8MP_CLK_VPU_BUS 96 -#define IMX8MP_CLK_MEDIA_AXI 97 -#define IMX8MP_CLK_MEDIA_APB 98 -#define IMX8MP_CLK_HDMI_APB 99 -#define IMX8MP_CLK_HDMI_AXI 100 -#define IMX8MP_CLK_GPU_AXI 101 -#define IMX8MP_CLK_GPU_AHB 102 -#define IMX8MP_CLK_NOC 103 -#define IMX8MP_CLK_NOC_IO 104 -#define IMX8MP_CLK_ML_AXI 105 -#define IMX8MP_CLK_ML_AHB 106 -#define IMX8MP_CLK_AHB 107 -#define IMX8MP_CLK_AUDIO_AHB 108 -#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 -#define IMX8MP_CLK_IPG_ROOT 110 -#define IMX8MP_CLK_DRAM_ALT 112 -#define IMX8MP_CLK_DRAM_APB 113 -#define IMX8MP_CLK_VPU_G1 114 -#define IMX8MP_CLK_VPU_G2 115 -#define IMX8MP_CLK_CAN1 116 -#define IMX8MP_CLK_CAN2 117 -#define IMX8MP_CLK_MEMREPAIR 118 -#define IMX8MP_CLK_PCIE_AUX 120 -#define IMX8MP_CLK_I2C5 121 -#define IMX8MP_CLK_I2C6 122 -#define IMX8MP_CLK_SAI1 123 -#define IMX8MP_CLK_SAI2 124 -#define IMX8MP_CLK_SAI3 125 -/* #define IMX8MP_CLK_SAI4 126 */ -#define IMX8MP_CLK_SAI5 127 -#define IMX8MP_CLK_SAI6 128 -#define IMX8MP_CLK_ENET_QOS 129 -#define IMX8MP_CLK_ENET_QOS_TIMER 130 -#define IMX8MP_CLK_ENET_REF 131 -#define IMX8MP_CLK_ENET_TIMER 132 -#define IMX8MP_CLK_ENET_PHY_REF 133 -#define IMX8MP_CLK_NAND 134 -#define IMX8MP_CLK_QSPI 135 -#define IMX8MP_CLK_USDHC1 136 -#define IMX8MP_CLK_USDHC2 137 -#define IMX8MP_CLK_I2C1 138 -#define IMX8MP_CLK_I2C2 139 -#define IMX8MP_CLK_I2C3 140 -#define IMX8MP_CLK_I2C4 141 -#define IMX8MP_CLK_UART1 142 -#define IMX8MP_CLK_UART2 143 -#define IMX8MP_CLK_UART3 144 -#define IMX8MP_CLK_UART4 145 -#define IMX8MP_CLK_USB_CORE_REF 146 -#define IMX8MP_CLK_USB_PHY_REF 147 -#define IMX8MP_CLK_GIC 148 -#define IMX8MP_CLK_ECSPI1 149 -#define IMX8MP_CLK_ECSPI2 150 -#define IMX8MP_CLK_PWM1 151 -#define IMX8MP_CLK_PWM2 152 -#define IMX8MP_CLK_PWM3 153 -#define IMX8MP_CLK_PWM4 154 -#define IMX8MP_CLK_GPT1 155 -#define IMX8MP_CLK_GPT2 156 -#define IMX8MP_CLK_GPT3 157 -#define IMX8MP_CLK_GPT4 158 -#define IMX8MP_CLK_GPT5 159 -#define IMX8MP_CLK_GPT6 160 -#define IMX8MP_CLK_TRACE 161 -#define IMX8MP_CLK_WDOG 162 -#define IMX8MP_CLK_WRCLK 163 -#define IMX8MP_CLK_IPP_DO_CLKO1 164 -#define IMX8MP_CLK_IPP_DO_CLKO2 165 -#define IMX8MP_CLK_HDMI_FDCC_TST 166 -#define IMX8MP_CLK_HDMI_24M 167 -#define IMX8MP_CLK_HDMI_REF_266M 168 -#define IMX8MP_CLK_USDHC3 169 -#define IMX8MP_CLK_MEDIA_CAM1_PIX 170 -#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 -#define IMX8MP_CLK_MEDIA_DISP1_PIX 172 -#define IMX8MP_CLK_MEDIA_CAM2_PIX 173 -#define IMX8MP_CLK_MEDIA_LDB 174 -#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 -#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 -#define IMX8MP_CLK_ECSPI3 179 -#define IMX8MP_CLK_PDM 180 -#define IMX8MP_CLK_VPU_VC8000E 181 -#define IMX8MP_CLK_SAI7 182 -#define IMX8MP_CLK_GPC_ROOT 183 -#define IMX8MP_CLK_ANAMIX_ROOT 184 -#define IMX8MP_CLK_CPU_ROOT 185 -#define IMX8MP_CLK_CSU_ROOT 186 -#define IMX8MP_CLK_DEBUG_ROOT 187 -#define IMX8MP_CLK_DRAM1_ROOT 188 -#define IMX8MP_CLK_ECSPI1_ROOT 189 -#define IMX8MP_CLK_ECSPI2_ROOT 190 -#define IMX8MP_CLK_ECSPI3_ROOT 191 -#define IMX8MP_CLK_ENET1_ROOT 192 -#define IMX8MP_CLK_GPIO1_ROOT 193 -#define IMX8MP_CLK_GPIO2_ROOT 194 -#define IMX8MP_CLK_GPIO3_ROOT 195 -#define IMX8MP_CLK_GPIO4_ROOT 196 -#define IMX8MP_CLK_GPIO5_ROOT 197 -#define IMX8MP_CLK_GPT1_ROOT 198 -#define IMX8MP_CLK_GPT2_ROOT 199 -#define IMX8MP_CLK_GPT3_ROOT 200 -#define IMX8MP_CLK_GPT4_ROOT 201 -#define IMX8MP_CLK_GPT5_ROOT 202 -#define IMX8MP_CLK_GPT6_ROOT 203 -#define IMX8MP_CLK_HS_ROOT 204 -#define IMX8MP_CLK_I2C1_ROOT 205 -#define IMX8MP_CLK_I2C2_ROOT 206 -#define IMX8MP_CLK_I2C3_ROOT 207 -#define IMX8MP_CLK_I2C4_ROOT 208 -#define IMX8MP_CLK_IOMUX_ROOT 209 -#define IMX8MP_CLK_IPMUX1_ROOT 210 -#define IMX8MP_CLK_IPMUX2_ROOT 211 -#define IMX8MP_CLK_IPMUX3_ROOT 212 -#define IMX8MP_CLK_MU_ROOT 213 -#define IMX8MP_CLK_OCOTP_ROOT 214 -#define IMX8MP_CLK_OCRAM_ROOT 215 -#define IMX8MP_CLK_OCRAM_S_ROOT 216 -#define IMX8MP_CLK_PCIE_ROOT 217 -#define IMX8MP_CLK_PERFMON1_ROOT 218 -#define IMX8MP_CLK_PERFMON2_ROOT 219 -#define IMX8MP_CLK_PWM1_ROOT 220 -#define IMX8MP_CLK_PWM2_ROOT 221 -#define IMX8MP_CLK_PWM3_ROOT 222 -#define IMX8MP_CLK_PWM4_ROOT 223 -#define IMX8MP_CLK_QOS_ROOT 224 -#define IMX8MP_CLK_QOS_ENET_ROOT 225 -#define IMX8MP_CLK_QSPI_ROOT 226 -#define IMX8MP_CLK_NAND_ROOT 227 -#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 -#define IMX8MP_CLK_RDC_ROOT 229 -#define IMX8MP_CLK_ROM_ROOT 230 -#define IMX8MP_CLK_I2C5_ROOT 231 -#define IMX8MP_CLK_I2C6_ROOT 232 -#define IMX8MP_CLK_CAN1_ROOT 233 -#define IMX8MP_CLK_CAN2_ROOT 234 -#define IMX8MP_CLK_SCTR_ROOT 235 -#define IMX8MP_CLK_SDMA1_ROOT 236 -#define IMX8MP_CLK_ENET_QOS_ROOT 237 -#define IMX8MP_CLK_SEC_DEBUG_ROOT 238 -#define IMX8MP_CLK_SEMA1_ROOT 239 -#define IMX8MP_CLK_SEMA2_ROOT 240 -#define IMX8MP_CLK_IRQ_STEER_ROOT 241 -#define IMX8MP_CLK_SIM_ENET_ROOT 242 -#define IMX8MP_CLK_SIM_M_ROOT 243 -#define IMX8MP_CLK_SIM_MAIN_ROOT 244 -#define IMX8MP_CLK_SIM_S_ROOT 245 -#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 -#define IMX8MP_CLK_GPU2D_ROOT 247 -#define IMX8MP_CLK_GPU3D_ROOT 248 -#define IMX8MP_CLK_SNVS_ROOT 249 -#define IMX8MP_CLK_TRACE_ROOT 250 -#define IMX8MP_CLK_UART1_ROOT 251 -#define IMX8MP_CLK_UART2_ROOT 252 -#define IMX8MP_CLK_UART3_ROOT 253 -#define IMX8MP_CLK_UART4_ROOT 254 -#define IMX8MP_CLK_USB_ROOT 255 -#define IMX8MP_CLK_USB_PHY_ROOT 256 -#define IMX8MP_CLK_USDHC1_ROOT 257 -#define IMX8MP_CLK_USDHC2_ROOT 258 -#define IMX8MP_CLK_WDOG1_ROOT 259 -#define IMX8MP_CLK_WDOG2_ROOT 260 -#define IMX8MP_CLK_WDOG3_ROOT 261 -#define IMX8MP_CLK_VPU_G1_ROOT 262 -#define IMX8MP_CLK_GPU_ROOT 263 -#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 -#define IMX8MP_CLK_VPU_VC8KE_ROOT 265 -#define IMX8MP_CLK_VPU_G2_ROOT 266 -#define IMX8MP_CLK_NPU_ROOT 267 -#define IMX8MP_CLK_HSIO_ROOT 268 -#define IMX8MP_CLK_MEDIA_APB_ROOT 269 -#define IMX8MP_CLK_MEDIA_AXI_ROOT 270 -#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 -#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 -#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 -#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 -#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 -#define IMX8MP_CLK_MEDIA_ISP_ROOT 276 -#define IMX8MP_CLK_USDHC3_ROOT 277 -#define IMX8MP_CLK_HDMI_ROOT 278 -#define IMX8MP_CLK_XTAL_ROOT 279 -#define IMX8MP_CLK_PLL_ROOT 280 -#define IMX8MP_CLK_TSENSOR_ROOT 281 -#define IMX8MP_CLK_VPU_ROOT 282 -#define IMX8MP_CLK_MRPR_ROOT 283 -#define IMX8MP_CLK_AUDIO_ROOT 284 -#define IMX8MP_CLK_DRAM_ALT_ROOT 285 -#define IMX8MP_CLK_DRAM_CORE 286 -#define IMX8MP_CLK_ARM 287 -#define IMX8MP_CLK_A53_CORE 288 - -#define IMX8MP_SYS_PLL1_40M_CG 289 -#define IMX8MP_SYS_PLL1_80M_CG 290 -#define IMX8MP_SYS_PLL1_100M_CG 291 -#define IMX8MP_SYS_PLL1_133M_CG 292 -#define IMX8MP_SYS_PLL1_160M_CG 293 -#define IMX8MP_SYS_PLL1_200M_CG 294 -#define IMX8MP_SYS_PLL1_266M_CG 295 -#define IMX8MP_SYS_PLL1_400M_CG 296 -#define IMX8MP_SYS_PLL2_50M_CG 297 -#define IMX8MP_SYS_PLL2_100M_CG 298 -#define IMX8MP_SYS_PLL2_125M_CG 299 -#define IMX8MP_SYS_PLL2_166M_CG 300 -#define IMX8MP_SYS_PLL2_200M_CG 301 -#define IMX8MP_SYS_PLL2_250M_CG 302 -#define IMX8MP_SYS_PLL2_333M_CG 303 -#define IMX8MP_SYS_PLL2_500M_CG 304 - -#define IMX8MP_CLK_M7_CORE 305 -#define IMX8MP_CLK_ML_CORE 306 -#define IMX8MP_CLK_GPU3D_CORE 307 -#define IMX8MP_CLK_GPU3D_SHADER_CORE 308 -#define IMX8MP_CLK_GPU2D_CORE 309 -#define IMX8MP_CLK_AUDIO_AXI 310 -#define IMX8MP_CLK_HSIO_AXI 311 -#define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_MEDIA_DISP2_PIX 313 -#define IMX8MP_CLK_CLKOUT1_SEL 314 -#define IMX8MP_CLK_CLKOUT1_DIV 315 -#define IMX8MP_CLK_CLKOUT1 316 -#define IMX8MP_CLK_CLKOUT2_SEL 317 -#define IMX8MP_CLK_CLKOUT2_DIV 318 -#define IMX8MP_CLK_CLKOUT2 319 -#define IMX8MP_CLK_USB_SUSP 320 -#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT -#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 -#define IMX8MP_CLK_SAI1_ROOT 322 -#define IMX8MP_CLK_SAI2_ROOT 323 -#define IMX8MP_CLK_SAI3_ROOT 324 -#define IMX8MP_CLK_SAI5_ROOT 325 -#define IMX8MP_CLK_SAI6_ROOT 326 -#define IMX8MP_CLK_SAI7_ROOT 327 -#define IMX8MP_CLK_PDM_ROOT 328 -#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 -#define IMX8MP_CLK_END 330 - -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 - -#define IMX8MP_CLK_AUDIOMIX_END 59 - -#endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h deleted file mode 100644 index afa74d7ba10..00000000000 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ /dev/null @@ -1,431 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H -#define __DT_BINDINGS_CLOCK_IMX8MQ_H - -#define IMX8MQ_CLK_DUMMY 0 -#define IMX8MQ_CLK_32K 1 -#define IMX8MQ_CLK_25M 2 -#define IMX8MQ_CLK_27M 3 -#define IMX8MQ_CLK_EXT1 4 -#define IMX8MQ_CLK_EXT2 5 -#define IMX8MQ_CLK_EXT3 6 -#define IMX8MQ_CLK_EXT4 7 - -/* ANAMIX PLL clocks */ -/* FRAC PLLs */ -/* ARM PLL */ -#define IMX8MQ_ARM_PLL_REF_SEL 8 -#define IMX8MQ_ARM_PLL_REF_DIV 9 -#define IMX8MQ_ARM_PLL 10 -#define IMX8MQ_ARM_PLL_BYPASS 11 -#define IMX8MQ_ARM_PLL_OUT 12 - -/* GPU PLL */ -#define IMX8MQ_GPU_PLL_REF_SEL 13 -#define IMX8MQ_GPU_PLL_REF_DIV 14 -#define IMX8MQ_GPU_PLL 15 -#define IMX8MQ_GPU_PLL_BYPASS 16 -#define IMX8MQ_GPU_PLL_OUT 17 - -/* VPU PLL */ -#define IMX8MQ_VPU_PLL_REF_SEL 18 -#define IMX8MQ_VPU_PLL_REF_DIV 19 -#define IMX8MQ_VPU_PLL 20 -#define IMX8MQ_VPU_PLL_BYPASS 21 -#define IMX8MQ_VPU_PLL_OUT 22 - -/* AUDIO PLL1 */ -#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 -#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 -#define IMX8MQ_AUDIO_PLL1 25 -#define IMX8MQ_AUDIO_PLL1_BYPASS 26 -#define IMX8MQ_AUDIO_PLL1_OUT 27 - -/* AUDIO PLL2 */ -#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 -#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 -#define IMX8MQ_AUDIO_PLL2 30 -#define IMX8MQ_AUDIO_PLL2_BYPASS 31 -#define IMX8MQ_AUDIO_PLL2_OUT 32 - -/* VIDEO PLL1 */ -#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 -#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 -#define IMX8MQ_VIDEO_PLL1 35 -#define IMX8MQ_VIDEO_PLL1_BYPASS 36 -#define IMX8MQ_VIDEO_PLL1_OUT 37 - -/* SYS1 PLL */ -#define IMX8MQ_SYS1_PLL1_REF_SEL 38 -#define IMX8MQ_SYS1_PLL1_REF_DIV 39 -#define IMX8MQ_SYS1_PLL1 40 -#define IMX8MQ_SYS1_PLL1_OUT 41 -#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 -#define IMX8MQ_SYS1_PLL2 43 -#define IMX8MQ_SYS1_PLL2_DIV 44 -#define IMX8MQ_SYS1_PLL2_OUT 45 - -/* SYS2 PLL */ -#define IMX8MQ_SYS2_PLL1_REF_SEL 46 -#define IMX8MQ_SYS2_PLL1_REF_DIV 47 -#define IMX8MQ_SYS2_PLL1 48 -#define IMX8MQ_SYS2_PLL1_OUT 49 -#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 -#define IMX8MQ_SYS2_PLL2 51 -#define IMX8MQ_SYS2_PLL2_DIV 52 -#define IMX8MQ_SYS2_PLL2_OUT 53 - -/* SYS3 PLL */ -#define IMX8MQ_SYS3_PLL1_REF_SEL 54 -#define IMX8MQ_SYS3_PLL1_REF_DIV 55 -#define IMX8MQ_SYS3_PLL1 56 -#define IMX8MQ_SYS3_PLL1_OUT 57 -#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 -#define IMX8MQ_SYS3_PLL2 59 -#define IMX8MQ_SYS3_PLL2_DIV 60 -#define IMX8MQ_SYS3_PLL2_OUT 61 - -/* DRAM PLL */ -#define IMX8MQ_DRAM_PLL1_REF_SEL 62 -#define IMX8MQ_DRAM_PLL1_REF_DIV 63 -#define IMX8MQ_DRAM_PLL1 64 -#define IMX8MQ_DRAM_PLL1_OUT 65 -#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 -#define IMX8MQ_DRAM_PLL2 67 -#define IMX8MQ_DRAM_PLL2_DIV 68 -#define IMX8MQ_DRAM_PLL2_OUT 69 - -/* SYS PLL DIV */ -#define IMX8MQ_SYS1_PLL_40M 70 -#define IMX8MQ_SYS1_PLL_80M 71 -#define IMX8MQ_SYS1_PLL_100M 72 -#define IMX8MQ_SYS1_PLL_133M 73 -#define IMX8MQ_SYS1_PLL_160M 74 -#define IMX8MQ_SYS1_PLL_200M 75 -#define IMX8MQ_SYS1_PLL_266M 76 -#define IMX8MQ_SYS1_PLL_400M 77 -#define IMX8MQ_SYS1_PLL_800M 78 - -#define IMX8MQ_SYS2_PLL_50M 79 -#define IMX8MQ_SYS2_PLL_100M 80 -#define IMX8MQ_SYS2_PLL_125M 81 -#define IMX8MQ_SYS2_PLL_166M 82 -#define IMX8MQ_SYS2_PLL_200M 83 -#define IMX8MQ_SYS2_PLL_250M 84 -#define IMX8MQ_SYS2_PLL_333M 85 -#define IMX8MQ_SYS2_PLL_500M 86 -#define IMX8MQ_SYS2_PLL_1000M 87 - -/* CCM ROOT clocks */ -/* A53 */ -#define IMX8MQ_CLK_A53_SRC 88 -#define IMX8MQ_CLK_A53_CG 89 -#define IMX8MQ_CLK_A53_DIV 90 -/* M4 */ -#define IMX8MQ_CLK_M4_SRC 91 -#define IMX8MQ_CLK_M4_CG 92 -#define IMX8MQ_CLK_M4_DIV 93 -/* VPU */ -#define IMX8MQ_CLK_VPU_SRC 94 -#define IMX8MQ_CLK_VPU_CG 95 -#define IMX8MQ_CLK_VPU_DIV 96 -/* GPU CORE */ -#define IMX8MQ_CLK_GPU_CORE_SRC 97 -#define IMX8MQ_CLK_GPU_CORE_CG 98 -#define IMX8MQ_CLK_GPU_CORE_DIV 99 -/* GPU SHADER */ -#define IMX8MQ_CLK_GPU_SHADER_SRC 100 -#define IMX8MQ_CLK_GPU_SHADER_CG 101 -#define IMX8MQ_CLK_GPU_SHADER_DIV 102 - -/* BUS TYPE */ -/* MAIN AXI */ -#define IMX8MQ_CLK_MAIN_AXI 103 -/* ENET AXI */ -#define IMX8MQ_CLK_ENET_AXI 104 -/* NAND_USDHC_BUS */ -#define IMX8MQ_CLK_NAND_USDHC_BUS 105 -/* VPU BUS */ -#define IMX8MQ_CLK_VPU_BUS 106 -/* DISP_AXI */ -#define IMX8MQ_CLK_DISP_AXI 107 -/* DISP APB */ -#define IMX8MQ_CLK_DISP_APB 108 -/* DISP RTRM */ -#define IMX8MQ_CLK_DISP_RTRM 109 -/* USB_BUS */ -#define IMX8MQ_CLK_USB_BUS 110 -/* GPU_AXI */ -#define IMX8MQ_CLK_GPU_AXI 111 -/* GPU_AHB */ -#define IMX8MQ_CLK_GPU_AHB 112 -/* NOC */ -#define IMX8MQ_CLK_NOC 113 -/* NOC_APB */ -#define IMX8MQ_CLK_NOC_APB 115 - -/* AHB */ -#define IMX8MQ_CLK_AHB 116 -/* AUDIO AHB */ -#define IMX8MQ_CLK_AUDIO_AHB 117 - -/* DRAM_ALT */ -#define IMX8MQ_CLK_DRAM_ALT 118 -/* DRAM APB */ -#define IMX8MQ_CLK_DRAM_APB 119 -/* VPU_G1 */ -#define IMX8MQ_CLK_VPU_G1 120 -/* VPU_G2 */ -#define IMX8MQ_CLK_VPU_G2 121 -/* DISP_DTRC */ -#define IMX8MQ_CLK_DISP_DTRC 122 -/* DISP_DC8000 */ -#define IMX8MQ_CLK_DISP_DC8000 123 -/* PCIE_CTRL */ -#define IMX8MQ_CLK_PCIE1_CTRL 124 -/* PCIE_PHY */ -#define IMX8MQ_CLK_PCIE1_PHY 125 -/* PCIE_AUX */ -#define IMX8MQ_CLK_PCIE1_AUX 126 -/* DC_PIXEL */ -#define IMX8MQ_CLK_DC_PIXEL 127 -/* LCDIF_PIXEL */ -#define IMX8MQ_CLK_LCDIF_PIXEL 128 -/* SAI1~6 */ -#define IMX8MQ_CLK_SAI1 129 - -#define IMX8MQ_CLK_SAI2 130 - -#define IMX8MQ_CLK_SAI3 131 - -#define IMX8MQ_CLK_SAI4 132 - -#define IMX8MQ_CLK_SAI5 133 - -#define IMX8MQ_CLK_SAI6 134 -/* SPDIF1 */ -#define IMX8MQ_CLK_SPDIF1 135 -/* SPDIF2 */ -#define IMX8MQ_CLK_SPDIF2 136 -/* ENET_REF */ -#define IMX8MQ_CLK_ENET_REF 137 -/* ENET_TIMER */ -#define IMX8MQ_CLK_ENET_TIMER 138 -/* ENET_PHY */ -#define IMX8MQ_CLK_ENET_PHY_REF 139 -/* NAND */ -#define IMX8MQ_CLK_NAND 140 -/* QSPI */ -#define IMX8MQ_CLK_QSPI 141 -/* USDHC1 */ -#define IMX8MQ_CLK_USDHC1 142 -/* USDHC2 */ -#define IMX8MQ_CLK_USDHC2 143 -/* I2C1 */ -#define IMX8MQ_CLK_I2C1 144 -/* I2C2 */ -#define IMX8MQ_CLK_I2C2 145 -/* I2C3 */ -#define IMX8MQ_CLK_I2C3 146 -/* I2C4 */ -#define IMX8MQ_CLK_I2C4 147 -/* UART1 */ -#define IMX8MQ_CLK_UART1 148 -/* UART2 */ -#define IMX8MQ_CLK_UART2 149 -/* UART3 */ -#define IMX8MQ_CLK_UART3 150 -/* UART4 */ -#define IMX8MQ_CLK_UART4 151 -/* USB_CORE_REF */ -#define IMX8MQ_CLK_USB_CORE_REF 152 -/* USB_PHY_REF */ -#define IMX8MQ_CLK_USB_PHY_REF 153 -/* ECSPI1 */ -#define IMX8MQ_CLK_ECSPI1 154 -/* ECSPI2 */ -#define IMX8MQ_CLK_ECSPI2 155 -/* PWM1 */ -#define IMX8MQ_CLK_PWM1 156 -/* PWM2 */ -#define IMX8MQ_CLK_PWM2 157 -/* PWM3 */ -#define IMX8MQ_CLK_PWM3 158 -/* PWM4 */ -#define IMX8MQ_CLK_PWM4 159 -/* GPT1 */ -#define IMX8MQ_CLK_GPT1 160 -/* WDOG */ -#define IMX8MQ_CLK_WDOG 161 -/* WRCLK */ -#define IMX8MQ_CLK_WRCLK 162 -/* DSI_CORE */ -#define IMX8MQ_CLK_DSI_CORE 163 -/* DSI_PHY */ -#define IMX8MQ_CLK_DSI_PHY_REF 164 -/* DSI_DBI */ -#define IMX8MQ_CLK_DSI_DBI 165 -/*DSI_ESC */ -#define IMX8MQ_CLK_DSI_ESC 166 -/* CSI1_CORE */ -#define IMX8MQ_CLK_CSI1_CORE 167 -/* CSI1_PHY */ -#define IMX8MQ_CLK_CSI1_PHY_REF 168 -/* CSI_ESC */ -#define IMX8MQ_CLK_CSI1_ESC 169 -/* CSI2_CORE */ -#define IMX8MQ_CLK_CSI2_CORE 170 -/* CSI2_PHY */ -#define IMX8MQ_CLK_CSI2_PHY_REF 171 -/* CSI2_ESC */ -#define IMX8MQ_CLK_CSI2_ESC 172 -/* PCIE2_CTRL */ -#define IMX8MQ_CLK_PCIE2_CTRL 173 -/* PCIE2_PHY */ -#define IMX8MQ_CLK_PCIE2_PHY 174 -/* PCIE2_AUX */ -#define IMX8MQ_CLK_PCIE2_AUX 175 -/* ECSPI3 */ -#define IMX8MQ_CLK_ECSPI3 176 - -/* CCGR clocks */ -#define IMX8MQ_CLK_A53_ROOT 177 -#define IMX8MQ_CLK_DRAM_ROOT 178 -#define IMX8MQ_CLK_ECSPI1_ROOT 179 -#define IMX8MQ_CLK_ECSPI2_ROOT 180 -#define IMX8MQ_CLK_ECSPI3_ROOT 181 -#define IMX8MQ_CLK_ENET1_ROOT 182 -#define IMX8MQ_CLK_GPT1_ROOT 183 -#define IMX8MQ_CLK_I2C1_ROOT 184 -#define IMX8MQ_CLK_I2C2_ROOT 185 -#define IMX8MQ_CLK_I2C3_ROOT 186 -#define IMX8MQ_CLK_I2C4_ROOT 187 -#define IMX8MQ_CLK_M4_ROOT 188 -#define IMX8MQ_CLK_PCIE1_ROOT 189 -#define IMX8MQ_CLK_PCIE2_ROOT 190 -#define IMX8MQ_CLK_PWM1_ROOT 191 -#define IMX8MQ_CLK_PWM2_ROOT 192 -#define IMX8MQ_CLK_PWM3_ROOT 193 -#define IMX8MQ_CLK_PWM4_ROOT 194 -#define IMX8MQ_CLK_QSPI_ROOT 195 -#define IMX8MQ_CLK_SAI1_ROOT 196 -#define IMX8MQ_CLK_SAI2_ROOT 197 -#define IMX8MQ_CLK_SAI3_ROOT 198 -#define IMX8MQ_CLK_SAI4_ROOT 199 -#define IMX8MQ_CLK_SAI5_ROOT 200 -#define IMX8MQ_CLK_SAI6_ROOT 201 -#define IMX8MQ_CLK_UART1_ROOT 202 -#define IMX8MQ_CLK_UART2_ROOT 203 -#define IMX8MQ_CLK_UART3_ROOT 204 -#define IMX8MQ_CLK_UART4_ROOT 205 -#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 -#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 -#define IMX8MQ_CLK_USB1_PHY_ROOT 208 -#define IMX8MQ_CLK_USB2_PHY_ROOT 209 -#define IMX8MQ_CLK_USDHC1_ROOT 210 -#define IMX8MQ_CLK_USDHC2_ROOT 211 -#define IMX8MQ_CLK_WDOG1_ROOT 212 -#define IMX8MQ_CLK_WDOG2_ROOT 213 -#define IMX8MQ_CLK_WDOG3_ROOT 214 -#define IMX8MQ_CLK_GPU_ROOT 215 -#define IMX8MQ_CLK_HEVC_ROOT 216 -#define IMX8MQ_CLK_AVC_ROOT 217 -#define IMX8MQ_CLK_VP9_ROOT 218 -#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 -#define IMX8MQ_CLK_DISP_ROOT 220 -#define IMX8MQ_CLK_HDMI_ROOT 221 -#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 -#define IMX8MQ_CLK_VPU_DEC_ROOT 223 -#define IMX8MQ_CLK_CSI1_ROOT 224 -#define IMX8MQ_CLK_CSI2_ROOT 225 -#define IMX8MQ_CLK_RAWNAND_ROOT 226 -#define IMX8MQ_CLK_SDMA1_ROOT 227 -#define IMX8MQ_CLK_SDMA2_ROOT 228 -#define IMX8MQ_CLK_VPU_G1_ROOT 229 -#define IMX8MQ_CLK_VPU_G2_ROOT 230 - -/* SCCG PLL GATE */ -#define IMX8MQ_SYS1_PLL_OUT 231 -#define IMX8MQ_SYS2_PLL_OUT 232 -#define IMX8MQ_SYS3_PLL_OUT 233 -#define IMX8MQ_DRAM_PLL_OUT 234 - -#define IMX8MQ_GPT_3M_CLK 235 - -#define IMX8MQ_CLK_IPG_ROOT 236 -#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 -#define IMX8MQ_CLK_SAI1_IPG 238 -#define IMX8MQ_CLK_SAI2_IPG 239 -#define IMX8MQ_CLK_SAI3_IPG 240 -#define IMX8MQ_CLK_SAI4_IPG 241 -#define IMX8MQ_CLK_SAI5_IPG 242 -#define IMX8MQ_CLK_SAI6_IPG 243 - -/* DSI AHB/IPG clocks */ -/* rxesc clock */ -#define IMX8MQ_CLK_DSI_AHB 244 -/* txesc clock */ -#define IMX8MQ_CLK_DSI_IPG_DIV 245 - -#define IMX8MQ_CLK_TMU_ROOT 246 - -/* Display root clocks */ -#define IMX8MQ_CLK_DISP_AXI_ROOT 247 -#define IMX8MQ_CLK_DISP_APB_ROOT 248 -#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 - -#define IMX8MQ_CLK_OCOTP_ROOT 250 - -#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 -#define IMX8MQ_CLK_DRAM_CORE 252 - -#define IMX8MQ_CLK_MU_ROOT 253 -#define IMX8MQ_VIDEO2_PLL_OUT 254 - -#define IMX8MQ_CLK_CLKO2 255 - -#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 - -#define IMX8MQ_CLK_CLKO1 257 -#define IMX8MQ_CLK_ARM 258 - -#define IMX8MQ_CLK_GPIO1_ROOT 259 -#define IMX8MQ_CLK_GPIO2_ROOT 260 -#define IMX8MQ_CLK_GPIO3_ROOT 261 -#define IMX8MQ_CLK_GPIO4_ROOT 262 -#define IMX8MQ_CLK_GPIO5_ROOT 263 - -#define IMX8MQ_CLK_SNVS_ROOT 264 -#define IMX8MQ_CLK_GIC 265 - -#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 - -#define IMX8MQ_CLK_GPU_CORE 285 -#define IMX8MQ_CLK_GPU_SHADER 286 -#define IMX8MQ_CLK_M4_CORE 287 -#define IMX8MQ_CLK_VPU_CORE 288 - -#define IMX8MQ_CLK_A53_CORE 289 - -#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290 -#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291 -#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292 -#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293 -#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294 -#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295 -#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296 -#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297 -#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298 -#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299 -#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300 -#define IMX8MQ_CLK_MON_SEL 301 -#define IMX8MQ_CLK_MON_CLK2_OUT 302 - -#define IMX8MQ_CLK_END 303 - -#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h deleted file mode 100644 index 953ecfe8ebc..00000000000 --- a/include/dt-bindings/clock/imx8ulp-clock.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Copyright 2021 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H -#define __DT_BINDINGS_CLOCK_IMX8ULP_H - -#define IMX8ULP_CLK_DUMMY 0 - -/* CGC1 */ -#define IMX8ULP_CLK_SPLL2 5 -#define IMX8ULP_CLK_SPLL3 6 -#define IMX8ULP_CLK_A35_SEL 7 -#define IMX8ULP_CLK_A35_DIV 8 -#define IMX8ULP_CLK_SPLL2_PRE_SEL 9 -#define IMX8ULP_CLK_SPLL3_PRE_SEL 10 -#define IMX8ULP_CLK_SPLL3_PFD0 11 -#define IMX8ULP_CLK_SPLL3_PFD1 12 -#define IMX8ULP_CLK_SPLL3_PFD2 13 -#define IMX8ULP_CLK_SPLL3_PFD3 14 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22 -#define IMX8ULP_CLK_NIC_SEL 23 -#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24 -#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25 -#define IMX8ULP_CLK_XBAR_SEL 26 -#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27 -#define IMX8ULP_CLK_XBAR_DIVBUS 28 -#define IMX8ULP_CLK_XBAR_AD_SLOW 29 -#define IMX8ULP_CLK_SOSC_DIV1 30 -#define IMX8ULP_CLK_SOSC_DIV2 31 -#define IMX8ULP_CLK_SOSC_DIV3 32 -#define IMX8ULP_CLK_FROSC_DIV1 33 -#define IMX8ULP_CLK_FROSC_DIV2 34 -#define IMX8ULP_CLK_FROSC_DIV3 35 -#define IMX8ULP_CLK_SPLL3_VCODIV 36 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44 -#define IMX8ULP_CLK_SOSC_DIV1_GATE 45 -#define IMX8ULP_CLK_SOSC_DIV2_GATE 46 -#define IMX8ULP_CLK_SOSC_DIV3_GATE 47 -#define IMX8ULP_CLK_FROSC_DIV1_GATE 48 -#define IMX8ULP_CLK_FROSC_DIV2_GATE 49 -#define IMX8ULP_CLK_FROSC_DIV3_GATE 50 -#define IMX8ULP_CLK_SAI4_SEL 51 -#define IMX8ULP_CLK_SAI5_SEL 52 -#define IMX8ULP_CLK_AUD_CLK1 53 -#define IMX8ULP_CLK_ARM 54 -#define IMX8ULP_CLK_ENET_TS_SEL 55 - -#define IMX8ULP_CLK_CGC1_END 56 - -/* CGC2 */ -#define IMX8ULP_CLK_PLL4_PRE_SEL 0 -#define IMX8ULP_CLK_PLL4 1 -#define IMX8ULP_CLK_PLL4_VCODIV 2 -#define IMX8ULP_CLK_DDR_SEL 3 -#define IMX8ULP_CLK_DDR_DIV 4 -#define IMX8ULP_CLK_LPAV_AXI_SEL 5 -#define IMX8ULP_CLK_LPAV_AXI_DIV 6 -#define IMX8ULP_CLK_LPAV_AHB_DIV 7 -#define IMX8ULP_CLK_LPAV_BUS_DIV 8 -#define IMX8ULP_CLK_PLL4_PFD0 9 -#define IMX8ULP_CLK_PLL4_PFD1 10 -#define IMX8ULP_CLK_PLL4_PFD2 11 -#define IMX8ULP_CLK_PLL4_PFD3 12 -#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 -#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 -#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15 -#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16 -#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17 -#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18 -#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19 -#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20 -#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21 -#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22 -#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23 -#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24 -#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25 -#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26 -#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27 -#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28 -#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29 -#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30 -#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31 -#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32 -#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33 -#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34 -#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35 -#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36 -#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37 -#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38 -#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39 -#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40 -#define IMX8ULP_CLK_AUD_CLK2 41 -#define IMX8ULP_CLK_SAI6_SEL 42 -#define IMX8ULP_CLK_SAI7_SEL 43 -#define IMX8ULP_CLK_SPDIF_SEL 44 -#define IMX8ULP_CLK_HIFI_SEL 45 -#define IMX8ULP_CLK_HIFI_DIVCORE 46 -#define IMX8ULP_CLK_HIFI_DIVPLAT 47 -#define IMX8ULP_CLK_DSI_PHY_REF 48 - -#define IMX8ULP_CLK_CGC2_END 49 - -/* PCC3 */ -#define IMX8ULP_CLK_WDOG3 0 -#define IMX8ULP_CLK_WDOG4 1 -#define IMX8ULP_CLK_LPIT1 2 -#define IMX8ULP_CLK_TPM4 3 -#define IMX8ULP_CLK_TPM5 4 -#define IMX8ULP_CLK_FLEXIO1 5 -#define IMX8ULP_CLK_I3C2 6 -#define IMX8ULP_CLK_LPI2C4 7 -#define IMX8ULP_CLK_LPI2C5 8 -#define IMX8ULP_CLK_LPUART4 9 -#define IMX8ULP_CLK_LPUART5 10 -#define IMX8ULP_CLK_LPSPI4 11 -#define IMX8ULP_CLK_LPSPI5 12 -#define IMX8ULP_CLK_DMA1_MP 13 -#define IMX8ULP_CLK_DMA1_CH0 14 -#define IMX8ULP_CLK_DMA1_CH1 15 -#define IMX8ULP_CLK_DMA1_CH2 16 -#define IMX8ULP_CLK_DMA1_CH3 17 -#define IMX8ULP_CLK_DMA1_CH4 18 -#define IMX8ULP_CLK_DMA1_CH5 19 -#define IMX8ULP_CLK_DMA1_CH6 20 -#define IMX8ULP_CLK_DMA1_CH7 21 -#define IMX8ULP_CLK_DMA1_CH8 22 -#define IMX8ULP_CLK_DMA1_CH9 23 -#define IMX8ULP_CLK_DMA1_CH10 24 -#define IMX8ULP_CLK_DMA1_CH11 25 -#define IMX8ULP_CLK_DMA1_CH12 26 -#define IMX8ULP_CLK_DMA1_CH13 27 -#define IMX8ULP_CLK_DMA1_CH14 28 -#define IMX8ULP_CLK_DMA1_CH15 29 -#define IMX8ULP_CLK_DMA1_CH16 30 -#define IMX8ULP_CLK_DMA1_CH17 31 -#define IMX8ULP_CLK_DMA1_CH18 32 -#define IMX8ULP_CLK_DMA1_CH19 33 -#define IMX8ULP_CLK_DMA1_CH20 34 -#define IMX8ULP_CLK_DMA1_CH21 35 -#define IMX8ULP_CLK_DMA1_CH22 36 -#define IMX8ULP_CLK_DMA1_CH23 37 -#define IMX8ULP_CLK_DMA1_CH24 38 -#define IMX8ULP_CLK_DMA1_CH25 39 -#define IMX8ULP_CLK_DMA1_CH26 40 -#define IMX8ULP_CLK_DMA1_CH27 41 -#define IMX8ULP_CLK_DMA1_CH28 42 -#define IMX8ULP_CLK_DMA1_CH29 43 -#define IMX8ULP_CLK_DMA1_CH30 44 -#define IMX8ULP_CLK_DMA1_CH31 45 -#define IMX8ULP_CLK_MU3_A 46 -#define IMX8ULP_CLK_MU0_B 47 - -#define IMX8ULP_CLK_PCC3_END 48 - -/* PCC4 */ -#define IMX8ULP_CLK_FLEXSPI2 0 -#define IMX8ULP_CLK_TPM6 1 -#define IMX8ULP_CLK_TPM7 2 -#define IMX8ULP_CLK_LPI2C6 3 -#define IMX8ULP_CLK_LPI2C7 4 -#define IMX8ULP_CLK_LPUART6 5 -#define IMX8ULP_CLK_LPUART7 6 -#define IMX8ULP_CLK_SAI4 7 -#define IMX8ULP_CLK_SAI5 8 -#define IMX8ULP_CLK_PCTLE 9 -#define IMX8ULP_CLK_PCTLF 10 -#define IMX8ULP_CLK_USDHC0 11 -#define IMX8ULP_CLK_USDHC1 12 -#define IMX8ULP_CLK_USDHC2 13 -#define IMX8ULP_CLK_USB0 14 -#define IMX8ULP_CLK_USB0_PHY 15 -#define IMX8ULP_CLK_USB1 16 -#define IMX8ULP_CLK_USB1_PHY 17 -#define IMX8ULP_CLK_USB_XBAR 18 -#define IMX8ULP_CLK_ENET 19 -#define IMX8ULP_CLK_SFA1 20 -#define IMX8ULP_CLK_RGPIOE 21 -#define IMX8ULP_CLK_RGPIOF 22 - -#define IMX8ULP_CLK_PCC4_END 23 - -/* PCC5 */ -#define IMX8ULP_CLK_TPM8 0 -#define IMX8ULP_CLK_SAI6 1 -#define IMX8ULP_CLK_SAI7 2 -#define IMX8ULP_CLK_SPDIF 3 -#define IMX8ULP_CLK_ISI 4 -#define IMX8ULP_CLK_CSI_REGS 5 -#define IMX8ULP_CLK_PCTLD 6 -#define IMX8ULP_CLK_CSI 7 -#define IMX8ULP_CLK_DSI 8 -#define IMX8ULP_CLK_WDOG5 9 -#define IMX8ULP_CLK_EPDC 10 -#define IMX8ULP_CLK_PXP 11 -#define IMX8ULP_CLK_SFA2 12 -#define IMX8ULP_CLK_GPU2D 13 -#define IMX8ULP_CLK_GPU3D 14 -#define IMX8ULP_CLK_DC_NANO 15 -#define IMX8ULP_CLK_CSI_CLK_UI 16 -#define IMX8ULP_CLK_CSI_CLK_ESC 17 -#define IMX8ULP_CLK_RGPIOD 18 -#define IMX8ULP_CLK_DMA2_MP 19 -#define IMX8ULP_CLK_DMA2_CH0 20 -#define IMX8ULP_CLK_DMA2_CH1 21 -#define IMX8ULP_CLK_DMA2_CH2 22 -#define IMX8ULP_CLK_DMA2_CH3 23 -#define IMX8ULP_CLK_DMA2_CH4 24 -#define IMX8ULP_CLK_DMA2_CH5 25 -#define IMX8ULP_CLK_DMA2_CH6 26 -#define IMX8ULP_CLK_DMA2_CH7 27 -#define IMX8ULP_CLK_DMA2_CH8 28 -#define IMX8ULP_CLK_DMA2_CH9 29 -#define IMX8ULP_CLK_DMA2_CH10 30 -#define IMX8ULP_CLK_DMA2_CH11 31 -#define IMX8ULP_CLK_DMA2_CH12 32 -#define IMX8ULP_CLK_DMA2_CH13 33 -#define IMX8ULP_CLK_DMA2_CH14 34 -#define IMX8ULP_CLK_DMA2_CH15 35 -#define IMX8ULP_CLK_DMA2_CH16 36 -#define IMX8ULP_CLK_DMA2_CH17 37 -#define IMX8ULP_CLK_DMA2_CH18 38 -#define IMX8ULP_CLK_DMA2_CH19 39 -#define IMX8ULP_CLK_DMA2_CH20 40 -#define IMX8ULP_CLK_DMA2_CH21 41 -#define IMX8ULP_CLK_DMA2_CH22 42 -#define IMX8ULP_CLK_DMA2_CH23 43 -#define IMX8ULP_CLK_DMA2_CH24 44 -#define IMX8ULP_CLK_DMA2_CH25 45 -#define IMX8ULP_CLK_DMA2_CH26 46 -#define IMX8ULP_CLK_DMA2_CH27 47 -#define IMX8ULP_CLK_DMA2_CH28 48 -#define IMX8ULP_CLK_DMA2_CH29 49 -#define IMX8ULP_CLK_DMA2_CH30 50 -#define IMX8ULP_CLK_DMA2_CH31 51 -#define IMX8ULP_CLK_MU2_B 52 -#define IMX8ULP_CLK_MU3_B 53 -#define IMX8ULP_CLK_AVD_SIM 54 -#define IMX8ULP_CLK_DSI_TX_ESC 55 - -#define IMX8ULP_CLK_PCC5_END 56 - -#endif diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h deleted file mode 100644 index 787c9e74dc9..00000000000 --- a/include/dt-bindings/clock/imx93-clock.h +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Copyright 2022 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H -#define __DT_BINDINGS_CLOCK_IMX93_CLK_H - -#define IMX93_CLK_DUMMY 0 -#define IMX93_CLK_24M 1 -#define IMX93_CLK_EXT1 2 -#define IMX93_CLK_SYS_PLL_PFD0 3 -#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 -#define IMX93_CLK_SYS_PLL_PFD1 5 -#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 -#define IMX93_CLK_SYS_PLL_PFD2 7 -#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 -#define IMX93_CLK_AUDIO_PLL 9 -#define IMX93_CLK_VIDEO_PLL 10 -#define IMX93_CLK_A55_PERIPH 11 -#define IMX93_CLK_A55_MTR_BUS 12 -#define IMX93_CLK_A55 13 -#define IMX93_CLK_M33 14 -#define IMX93_CLK_BUS_WAKEUP 15 -#define IMX93_CLK_BUS_AON 16 -#define IMX93_CLK_WAKEUP_AXI 17 -#define IMX93_CLK_SWO_TRACE 18 -#define IMX93_CLK_M33_SYSTICK 19 -#define IMX93_CLK_FLEXIO1 20 -#define IMX93_CLK_FLEXIO2 21 -#define IMX93_CLK_LPTMR1 24 -#define IMX93_CLK_LPTMR2 25 -#define IMX93_CLK_TPM2 27 -#define IMX93_CLK_TPM4 29 -#define IMX93_CLK_TPM5 30 -#define IMX93_CLK_TPM6 31 -#define IMX93_CLK_FLEXSPI1 32 -#define IMX93_CLK_CAN1 33 -#define IMX93_CLK_CAN2 34 -#define IMX93_CLK_LPUART1 35 -#define IMX93_CLK_LPUART2 36 -#define IMX93_CLK_LPUART3 37 -#define IMX93_CLK_LPUART4 38 -#define IMX93_CLK_LPUART5 39 -#define IMX93_CLK_LPUART6 40 -#define IMX93_CLK_LPUART7 41 -#define IMX93_CLK_LPUART8 42 -#define IMX93_CLK_LPI2C1 43 -#define IMX93_CLK_LPI2C2 44 -#define IMX93_CLK_LPI2C3 45 -#define IMX93_CLK_LPI2C4 46 -#define IMX93_CLK_LPI2C5 47 -#define IMX93_CLK_LPI2C6 48 -#define IMX93_CLK_LPI2C7 49 -#define IMX93_CLK_LPI2C8 50 -#define IMX93_CLK_LPSPI1 51 -#define IMX93_CLK_LPSPI2 52 -#define IMX93_CLK_LPSPI3 53 -#define IMX93_CLK_LPSPI4 54 -#define IMX93_CLK_LPSPI5 55 -#define IMX93_CLK_LPSPI6 56 -#define IMX93_CLK_LPSPI7 57 -#define IMX93_CLK_LPSPI8 58 -#define IMX93_CLK_I3C1 59 -#define IMX93_CLK_I3C2 60 -#define IMX93_CLK_USDHC1 61 -#define IMX93_CLK_USDHC2 62 -#define IMX93_CLK_USDHC3 63 -#define IMX93_CLK_SAI1 64 -#define IMX93_CLK_SAI2 65 -#define IMX93_CLK_SAI3 66 -#define IMX93_CLK_CCM_CKO1 67 -#define IMX93_CLK_CCM_CKO2 68 -#define IMX93_CLK_CCM_CKO3 69 -#define IMX93_CLK_CCM_CKO4 70 -#define IMX93_CLK_HSIO 71 -#define IMX93_CLK_HSIO_USB_TEST_60M 72 -#define IMX93_CLK_HSIO_ACSCAN_80M 73 -#define IMX93_CLK_HSIO_ACSCAN_480M 74 -#define IMX93_CLK_ML_APB 75 -#define IMX93_CLK_ML 76 -#define IMX93_CLK_MEDIA_AXI 77 -#define IMX93_CLK_MEDIA_APB 78 -#define IMX93_CLK_MEDIA_LDB 79 -#define IMX93_CLK_MEDIA_DISP_PIX 80 -#define IMX93_CLK_CAM_PIX 81 -#define IMX93_CLK_MIPI_TEST_BYTE 82 -#define IMX93_CLK_MIPI_PHY_CFG 83 -#define IMX93_CLK_ADC 84 -#define IMX93_CLK_PDM 85 -#define IMX93_CLK_TSTMR1 86 -#define IMX93_CLK_TSTMR2 87 -#define IMX93_CLK_MQS1 88 -#define IMX93_CLK_MQS2 89 -#define IMX93_CLK_AUDIO_XCVR 90 -#define IMX93_CLK_SPDIF 91 -#define IMX93_CLK_ENET 92 -#define IMX93_CLK_ENET_TIMER1 93 -#define IMX93_CLK_ENET_TIMER2 94 -#define IMX93_CLK_ENET_REF 95 -#define IMX93_CLK_ENET_REF_PHY 96 -#define IMX93_CLK_I3C1_SLOW 97 -#define IMX93_CLK_I3C2_SLOW 98 -#define IMX93_CLK_USB_PHY_BURUNIN 99 -#define IMX93_CLK_PAL_CAME_SCAN 100 -#define IMX93_CLK_A55_GATE 101 -#define IMX93_CLK_CM33_GATE 102 -#define IMX93_CLK_ADC1_GATE 103 -#define IMX93_CLK_WDOG1_GATE 104 -#define IMX93_CLK_WDOG2_GATE 105 -#define IMX93_CLK_WDOG3_GATE 106 -#define IMX93_CLK_WDOG4_GATE 107 -#define IMX93_CLK_WDOG5_GATE 108 -#define IMX93_CLK_SEMA1_GATE 109 -#define IMX93_CLK_SEMA2_GATE 110 -#define IMX93_CLK_MU_A_GATE 111 -#define IMX93_CLK_MU_B_GATE 112 -#define IMX93_CLK_EDMA1_GATE 113 -#define IMX93_CLK_EDMA2_GATE 114 -#define IMX93_CLK_FLEXSPI1_GATE 115 -#define IMX93_CLK_GPIO1_GATE 116 -#define IMX93_CLK_GPIO2_GATE 117 -#define IMX93_CLK_GPIO3_GATE 118 -#define IMX93_CLK_GPIO4_GATE 119 -#define IMX93_CLK_FLEXIO1_GATE 120 -#define IMX93_CLK_FLEXIO2_GATE 121 -#define IMX93_CLK_LPIT1_GATE 122 -#define IMX93_CLK_LPIT2_GATE 123 -#define IMX93_CLK_LPTMR1_GATE 124 -#define IMX93_CLK_LPTMR2_GATE 125 -#define IMX93_CLK_TPM1_GATE 126 -#define IMX93_CLK_TPM2_GATE 127 -#define IMX93_CLK_TPM3_GATE 128 -#define IMX93_CLK_TPM4_GATE 129 -#define IMX93_CLK_TPM5_GATE 130 -#define IMX93_CLK_TPM6_GATE 131 -#define IMX93_CLK_CAN1_GATE 132 -#define IMX93_CLK_CAN2_GATE 133 -#define IMX93_CLK_LPUART1_GATE 134 -#define IMX93_CLK_LPUART2_GATE 135 -#define IMX93_CLK_LPUART3_GATE 136 -#define IMX93_CLK_LPUART4_GATE 137 -#define IMX93_CLK_LPUART5_GATE 138 -#define IMX93_CLK_LPUART6_GATE 139 -#define IMX93_CLK_LPUART7_GATE 140 -#define IMX93_CLK_LPUART8_GATE 141 -#define IMX93_CLK_LPI2C1_GATE 142 -#define IMX93_CLK_LPI2C2_GATE 143 -#define IMX93_CLK_LPI2C3_GATE 144 -#define IMX93_CLK_LPI2C4_GATE 145 -#define IMX93_CLK_LPI2C5_GATE 146 -#define IMX93_CLK_LPI2C6_GATE 147 -#define IMX93_CLK_LPI2C7_GATE 148 -#define IMX93_CLK_LPI2C8_GATE 149 -#define IMX93_CLK_LPSPI1_GATE 150 -#define IMX93_CLK_LPSPI2_GATE 151 -#define IMX93_CLK_LPSPI3_GATE 152 -#define IMX93_CLK_LPSPI4_GATE 153 -#define IMX93_CLK_LPSPI5_GATE 154 -#define IMX93_CLK_LPSPI6_GATE 155 -#define IMX93_CLK_LPSPI7_GATE 156 -#define IMX93_CLK_LPSPI8_GATE 157 -#define IMX93_CLK_I3C1_GATE 158 -#define IMX93_CLK_I3C2_GATE 159 -#define IMX93_CLK_USDHC1_GATE 160 -#define IMX93_CLK_USDHC2_GATE 161 -#define IMX93_CLK_USDHC3_GATE 162 -#define IMX93_CLK_SAI1_GATE 163 -#define IMX93_CLK_SAI2_GATE 164 -#define IMX93_CLK_SAI3_GATE 165 -#define IMX93_CLK_MIPI_CSI_GATE 166 -#define IMX93_CLK_MIPI_DSI_GATE 167 -#define IMX93_CLK_LVDS_GATE 168 -#define IMX93_CLK_LCDIF_GATE 169 -#define IMX93_CLK_PXP_GATE 170 -#define IMX93_CLK_ISI_GATE 171 -#define IMX93_CLK_NIC_MEDIA_GATE 172 -#define IMX93_CLK_USB_CONTROLLER_GATE 173 -#define IMX93_CLK_USB_TEST_60M_GATE 174 -#define IMX93_CLK_HSIO_TROUT_24M_GATE 175 -#define IMX93_CLK_PDM_GATE 176 -#define IMX93_CLK_MQS1_GATE 177 -#define IMX93_CLK_MQS2_GATE 178 -#define IMX93_CLK_AUD_XCVR_GATE 179 -#define IMX93_CLK_SPDIF_GATE 180 -#define IMX93_CLK_HSIO_32K_GATE 181 -#define IMX93_CLK_ENET1_GATE 182 -#define IMX93_CLK_ENET_QOS_GATE 183 -#define IMX93_CLK_SYS_CNT_GATE 184 -#define IMX93_CLK_TSTMR1_GATE 185 -#define IMX93_CLK_TSTMR2_GATE 186 -#define IMX93_CLK_TMC_GATE 187 -#define IMX93_CLK_PMRO_GATE 188 -#define IMX93_CLK_32K 189 -#define IMX93_CLK_SAI1_IPG 190 -#define IMX93_CLK_SAI2_IPG 191 -#define IMX93_CLK_SAI3_IPG 192 -#define IMX93_CLK_MU1_A_GATE 193 -#define IMX93_CLK_MU1_B_GATE 194 -#define IMX93_CLK_MU2_A_GATE 195 -#define IMX93_CLK_MU2_B_GATE 196 -#define IMX93_CLK_NIC_AXI 197 -#define IMX93_CLK_ARM_PLL 198 -#define IMX93_CLK_A55_SEL 199 -#define IMX93_CLK_A55_CORE 200 -#define IMX93_CLK_PDM_IPG 201 -#define IMX93_CLK_END 202 - -#endif diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h deleted file mode 100644 index 93bef0832d1..00000000000 --- a/include/dt-bindings/clock/imxrt1050-clock.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright(C) 2019 - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> - */ - -#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H -#define __DT_BINDINGS_CLOCK_IMXRT1050_H - -#define IMXRT1050_CLK_DUMMY 0 -#define IMXRT1050_CLK_CKIL 1 -#define IMXRT1050_CLK_CKIH 2 -#define IMXRT1050_CLK_OSC 3 -#define IMXRT1050_CLK_PLL2_PFD0_352M 4 -#define IMXRT1050_CLK_PLL2_PFD1_594M 5 -#define IMXRT1050_CLK_PLL2_PFD2_396M 6 -#define IMXRT1050_CLK_PLL3_PFD0_720M 7 -#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 -#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 -#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 -#define IMXRT1050_CLK_PLL2_198M 11 -#define IMXRT1050_CLK_PLL3_120M 12 -#define IMXRT1050_CLK_PLL3_80M 13 -#define IMXRT1050_CLK_PLL3_60M 14 -#define IMXRT1050_CLK_PLL1_BYPASS 15 -#define IMXRT1050_CLK_PLL2_BYPASS 16 -#define IMXRT1050_CLK_PLL3_BYPASS 17 -#define IMXRT1050_CLK_PLL5_BYPASS 19 -#define IMXRT1050_CLK_PLL1_REF_SEL 20 -#define IMXRT1050_CLK_PLL2_REF_SEL 21 -#define IMXRT1050_CLK_PLL3_REF_SEL 22 -#define IMXRT1050_CLK_PLL5_REF_SEL 23 -#define IMXRT1050_CLK_PRE_PERIPH_SEL 24 -#define IMXRT1050_CLK_PERIPH_SEL 25 -#define IMXRT1050_CLK_SEMC_ALT_SEL 26 -#define IMXRT1050_CLK_SEMC_SEL 27 -#define IMXRT1050_CLK_USDHC1_SEL 28 -#define IMXRT1050_CLK_USDHC2_SEL 29 -#define IMXRT1050_CLK_LPUART_SEL 30 -#define IMXRT1050_CLK_LCDIF_SEL 31 -#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32 -#define IMXRT1050_CLK_VIDEO_DIV 33 -#define IMXRT1050_CLK_ARM_PODF 34 -#define IMXRT1050_CLK_LPUART_PODF 35 -#define IMXRT1050_CLK_USDHC1_PODF 36 -#define IMXRT1050_CLK_USDHC2_PODF 37 -#define IMXRT1050_CLK_SEMC_PODF 38 -#define IMXRT1050_CLK_AHB_PODF 39 -#define IMXRT1050_CLK_LCDIF_PRED 40 -#define IMXRT1050_CLK_LCDIF_PODF 41 -#define IMXRT1050_CLK_USDHC1 42 -#define IMXRT1050_CLK_USDHC2 43 -#define IMXRT1050_CLK_LPUART1 44 -#define IMXRT1050_CLK_SEMC 45 -#define IMXRT1050_CLK_LCDIF_APB 46 -#define IMXRT1050_CLK_PLL1_ARM 47 -#define IMXRT1050_CLK_PLL2_SYS 48 -#define IMXRT1050_CLK_PLL3_USB_OTG 49 -#define IMXRT1050_CLK_PLL4_AUDIO 50 -#define IMXRT1050_CLK_PLL5_VIDEO 51 -#define IMXRT1050_CLK_PLL6_ENET 52 -#define IMXRT1050_CLK_PLL7_USB_HOST 53 -#define IMXRT1050_CLK_LCDIF_PIX 54 -#define IMXRT1050_CLK_USBOH3 55 -#define IMXRT1050_CLK_IPG_PDOF 56 -#define IMXRT1050_CLK_PER_CLK_SEL 57 -#define IMXRT1050_CLK_PER_PDOF 58 -#define IMXRT1050_CLK_DMA 59 -#define IMXRT1050_CLK_DMA_MUX 60 -#define IMXRT1050_CLK_END 61 - -#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ diff --git a/include/dt-bindings/interconnect/fsl,imx8mp.h b/include/dt-bindings/interconnect/fsl,imx8mp.h deleted file mode 100644 index 7357d417529..00000000000 --- a/include/dt-bindings/interconnect/fsl,imx8mp.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * Interconnect framework driver for i.MX SoC - * - * Copyright 2022 NXP - * Peng Fan <peng.fan@nxp.com> - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H -#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H - -#define IMX8MP_ICN_NOC 0 -#define IMX8MP_ICN_MAIN 1 -#define IMX8MP_ICS_DRAM 2 -#define IMX8MP_ICS_OCRAM 3 -#define IMX8MP_ICM_A53 4 -#define IMX8MP_ICM_SUPERMIX 5 -#define IMX8MP_ICM_GIC 6 -#define IMX8MP_ICM_MLMIX 7 - -#define IMX8MP_ICN_AUDIO 8 -#define IMX8MP_ICM_DSP 9 -#define IMX8MP_ICM_SDMA2PER 10 -#define IMX8MP_ICM_SDMA2BURST 11 -#define IMX8MP_ICM_SDMA3PER 12 -#define IMX8MP_ICM_SDMA3BURST 13 -#define IMX8MP_ICM_EDMA 14 - -#define IMX8MP_ICN_GPU 15 -#define IMX8MP_ICM_GPU2D 16 -#define IMX8MP_ICM_GPU3D 17 - -#define IMX8MP_ICN_HDMI 18 -#define IMX8MP_ICM_HRV 19 -#define IMX8MP_ICM_LCDIF_HDMI 20 -#define IMX8MP_ICM_HDCP 21 - -#define IMX8MP_ICN_HSIO 22 -#define IMX8MP_ICM_NOC_PCIE 23 -#define IMX8MP_ICM_USB1 24 -#define IMX8MP_ICM_USB2 25 -#define IMX8MP_ICM_PCIE 26 - -#define IMX8MP_ICN_MEDIA 27 -#define IMX8MP_ICM_LCDIF_RD 28 -#define IMX8MP_ICM_LCDIF_WR 29 -#define IMX8MP_ICM_ISI0 30 -#define IMX8MP_ICM_ISI1 31 -#define IMX8MP_ICM_ISI2 32 -#define IMX8MP_ICM_ISP0 33 -#define IMX8MP_ICM_ISP1 34 -#define IMX8MP_ICM_DWE 35 - -#define IMX8MP_ICN_VIDEO 36 -#define IMX8MP_ICM_VPU_G1 37 -#define IMX8MP_ICM_VPU_G2 38 -#define IMX8MP_ICM_VPU_H1 39 - -#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */ diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h deleted file mode 100644 index 8f10bb06cb5..00000000000 --- a/include/dt-bindings/interconnect/imx8mm.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Interconnect framework driver for i.MX SoC - * - * Copyright (c) 2019, BayLibre - * Copyright (c) 2019-2020, NXP - * Author: Alexandre Bailon <abailon@baylibre.com> - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H -#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H - -#define IMX8MM_ICN_NOC 1 -#define IMX8MM_ICS_DRAM 2 -#define IMX8MM_ICS_OCRAM 3 -#define IMX8MM_ICM_A53 4 - -#define IMX8MM_ICM_VPU_H1 5 -#define IMX8MM_ICM_VPU_G1 6 -#define IMX8MM_ICM_VPU_G2 7 -#define IMX8MM_ICN_VIDEO 8 - -#define IMX8MM_ICM_GPU2D 9 -#define IMX8MM_ICM_GPU3D 10 -#define IMX8MM_ICN_GPU 11 - -#define IMX8MM_ICM_CSI 12 -#define IMX8MM_ICM_LCDIF 13 -#define IMX8MM_ICN_MIPI 14 - -#define IMX8MM_ICM_USB1 15 -#define IMX8MM_ICM_USB2 16 -#define IMX8MM_ICM_PCIE 17 -#define IMX8MM_ICN_HSIO 18 - -#define IMX8MM_ICM_SDMA2 19 -#define IMX8MM_ICM_SDMA3 20 -#define IMX8MM_ICN_AUDIO 21 - -#define IMX8MM_ICN_ENET 22 -#define IMX8MM_ICM_ENET 23 - -#define IMX8MM_ICN_MAIN 24 -#define IMX8MM_ICM_NAND 25 -#define IMX8MM_ICM_SDMA1 26 -#define IMX8MM_ICM_USDHC1 27 -#define IMX8MM_ICM_USDHC2 28 -#define IMX8MM_ICM_USDHC3 29 - -#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */ diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h deleted file mode 100644 index 307b977100b..00000000000 --- a/include/dt-bindings/interconnect/imx8mn.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Interconnect framework driver for i.MX SoC - * - * Copyright (c) 2019-2020, NXP - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H -#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H - -#define IMX8MN_ICN_NOC 1 -#define IMX8MN_ICS_DRAM 2 -#define IMX8MN_ICS_OCRAM 3 -#define IMX8MN_ICM_A53 4 - -#define IMX8MN_ICM_GPU 5 -#define IMX8MN_ICN_GPU 6 - -#define IMX8MN_ICM_CSI1 7 -#define IMX8MN_ICM_CSI2 8 -#define IMX8MN_ICM_ISI 9 -#define IMX8MN_ICM_LCDIF 10 -#define IMX8MN_ICN_MIPI 11 - -#define IMX8MN_ICM_USB 12 - -#define IMX8MN_ICM_SDMA2 13 -#define IMX8MN_ICM_SDMA3 14 -#define IMX8MN_ICN_AUDIO 15 - -#define IMX8MN_ICN_ENET 16 -#define IMX8MN_ICM_ENET 17 - -#define IMX8MN_ICM_NAND 18 -#define IMX8MN_ICM_SDMA1 19 -#define IMX8MN_ICM_USDHC1 20 -#define IMX8MN_ICM_USDHC2 21 -#define IMX8MN_ICM_USDHC3 22 -#define IMX8MN_ICN_MAIN 23 - -#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ diff --git a/include/dt-bindings/interconnect/imx8mq.h b/include/dt-bindings/interconnect/imx8mq.h deleted file mode 100644 index 1a4cae7f8be..00000000000 --- a/include/dt-bindings/interconnect/imx8mq.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Interconnect framework driver for i.MX SoC - * - * Copyright (c) 2019-2020, NXP - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H -#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H - -#define IMX8MQ_ICN_NOC 1 -#define IMX8MQ_ICS_DRAM 2 -#define IMX8MQ_ICS_OCRAM 3 -#define IMX8MQ_ICM_A53 4 - -#define IMX8MQ_ICM_VPU 5 -#define IMX8MQ_ICN_VIDEO 6 - -#define IMX8MQ_ICM_GPU 7 -#define IMX8MQ_ICN_GPU 8 - -#define IMX8MQ_ICM_DCSS 9 -#define IMX8MQ_ICN_DCSS 10 - -#define IMX8MQ_ICM_USB1 11 -#define IMX8MQ_ICM_USB2 12 -#define IMX8MQ_ICN_USB 13 - -#define IMX8MQ_ICM_CSI1 14 -#define IMX8MQ_ICM_CSI2 15 -#define IMX8MQ_ICM_LCDIF 16 -#define IMX8MQ_ICN_DISPLAY 17 - -#define IMX8MQ_ICM_SDMA2 18 -#define IMX8MQ_ICN_AUDIO 19 - -#define IMX8MQ_ICN_ENET 20 -#define IMX8MQ_ICM_ENET 21 - -#define IMX8MQ_ICM_SDMA1 22 -#define IMX8MQ_ICM_NAND 23 -#define IMX8MQ_ICM_USDHC1 24 -#define IMX8MQ_ICM_USDHC2 25 -#define IMX8MQ_ICM_PCIE1 26 -#define IMX8MQ_ICM_PCIE2 27 -#define IMX8MQ_ICN_MAIN 28 - -#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */ diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h deleted file mode 100644 index 8bbe2d6538d..00000000000 --- a/include/dt-bindings/phy/phy-imx8-pcie.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * This header provides constants for i.MX8 PCIe. - */ - -#ifndef _DT_BINDINGS_IMX8_PCIE_H -#define _DT_BINDINGS_IMX8_PCIE_H - -/* Reference clock PAD mode */ -#define IMX8_PCIE_REFCLK_PAD_UNUSED 0 -#define IMX8_PCIE_REFCLK_PAD_INPUT 1 -#define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 - -#endif /* _DT_BINDINGS_IMX8_PCIE_H */ diff --git a/include/dt-bindings/pinctrl/pins-imx8mq.h b/include/dt-bindings/pinctrl/pins-imx8mq.h deleted file mode 100644 index 0e1d67d414b..00000000000 --- a/include/dt-bindings/pinctrl/pins-imx8mq.h +++ /dev/null @@ -1,632 +0,0 @@ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DTS_IMX8MQ_PINFUNC_H -#define __DTS_IMX8MQ_PINFUNC_H - -/* - * The pin function ID is a tuple of - * <mux_reg conf_reg input_reg mux_mode input_val> - */ - -#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 - -#endif /* __DTS_IMX8MQ_PINFUNC_H */ diff --git a/include/dt-bindings/power/fsl,imx93-power.h b/include/dt-bindings/power/fsl,imx93-power.h deleted file mode 100644 index 17f9f015bf7..00000000000 --- a/include/dt-bindings/power/fsl,imx93-power.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright 2022 NXP - */ - -#ifndef __DT_BINDINGS_IMX93_POWER_H__ -#define __DT_BINDINGS_IMX93_POWER_H__ - -#define IMX93_MEDIABLK_PD_MIPI_DSI 0 -#define IMX93_MEDIABLK_PD_MIPI_CSI 1 -#define IMX93_MEDIABLK_PD_PXP 2 -#define IMX93_MEDIABLK_PD_LCDIF 3 -#define IMX93_MEDIABLK_PD_ISI 4 - -#endif diff --git a/include/dt-bindings/power/imx7-power.h b/include/dt-bindings/power/imx7-power.h deleted file mode 100644 index 597c1aa06ae..00000000000 --- a/include/dt-bindings/power/imx7-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Impinj - */ - -#ifndef __DT_BINDINGS_IMX7_POWER_H__ -#define __DT_BINDINGS_IMX7_POWER_H__ - -#define IMX7_POWER_DOMAIN_MIPI_PHY 0 -#define IMX7_POWER_DOMAIN_PCIE_PHY 1 -#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2 - -#endif diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h deleted file mode 100644 index 648938f24c8..00000000000 --- a/include/dt-bindings/power/imx8mm-power.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2020 Pengutronix, Lucas Stach <kernel@pengutronix.de> - */ - -#ifndef __DT_BINDINGS_IMX8MM_POWER_H__ -#define __DT_BINDINGS_IMX8MM_POWER_H__ - -#define IMX8MM_POWER_DOMAIN_HSIOMIX 0 -#define IMX8MM_POWER_DOMAIN_PCIE 1 -#define IMX8MM_POWER_DOMAIN_OTG1 2 -#define IMX8MM_POWER_DOMAIN_OTG2 3 -#define IMX8MM_POWER_DOMAIN_GPUMIX 4 -#define IMX8MM_POWER_DOMAIN_GPU 5 -#define IMX8MM_POWER_DOMAIN_VPUMIX 6 -#define IMX8MM_POWER_DOMAIN_VPUG1 7 -#define IMX8MM_POWER_DOMAIN_VPUG2 8 -#define IMX8MM_POWER_DOMAIN_VPUH1 9 -#define IMX8MM_POWER_DOMAIN_DISPMIX 10 -#define IMX8MM_POWER_DOMAIN_MIPI 11 - -#define IMX8MM_VPUBLK_PD_G1 0 -#define IMX8MM_VPUBLK_PD_G2 1 -#define IMX8MM_VPUBLK_PD_H1 2 - -#define IMX8MM_DISPBLK_PD_CSI_BRIDGE 0 -#define IMX8MM_DISPBLK_PD_LCDIF 1 -#define IMX8MM_DISPBLK_PD_MIPI_DSI 2 -#define IMX8MM_DISPBLK_PD_MIPI_CSI 3 - -#endif diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h deleted file mode 100644 index eedd0e58193..00000000000 --- a/include/dt-bindings/power/imx8mn-power.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2020 Compass Electronics Group, LLC - */ - -#ifndef __DT_BINDINGS_IMX8MN_POWER_H__ -#define __DT_BINDINGS_IMX8MN_POWER_H__ - -#define IMX8MN_POWER_DOMAIN_HSIOMIX 0 -#define IMX8MN_POWER_DOMAIN_OTG1 1 -#define IMX8MN_POWER_DOMAIN_GPUMIX 2 -#define IMX8MN_POWER_DOMAIN_DISPMIX 3 -#define IMX8MN_POWER_DOMAIN_MIPI 4 - -#define IMX8MN_DISPBLK_PD_MIPI_DSI 0 -#define IMX8MN_DISPBLK_PD_MIPI_CSI 1 -#define IMX8MN_DISPBLK_PD_LCDIF 2 -#define IMX8MN_DISPBLK_PD_ISI 3 - -#endif diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h deleted file mode 100644 index 2fe3c2abad1..00000000000 --- a/include/dt-bindings/power/imx8mp-power.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de> - */ - -#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ -#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ - -#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0 -#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1 -#define IMX8MP_POWER_DOMAIN_USB1_PHY 2 -#define IMX8MP_POWER_DOMAIN_USB2_PHY 3 -#define IMX8MP_POWER_DOMAIN_MLMIX 4 -#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5 -#define IMX8MP_POWER_DOMAIN_GPU2D 6 -#define IMX8MP_POWER_DOMAIN_GPUMIX 7 -#define IMX8MP_POWER_DOMAIN_VPUMIX 8 -#define IMX8MP_POWER_DOMAIN_GPU3D 9 -#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10 -#define IMX8MP_POWER_DOMAIN_VPU_G1 11 -#define IMX8MP_POWER_DOMAIN_VPU_G2 12 -#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13 -#define IMX8MP_POWER_DOMAIN_HDMIMIX 14 -#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15 -#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16 -#define IMX8MP_POWER_DOMAIN_HSIOMIX 17 -#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 - -#define IMX8MP_HSIOBLK_PD_USB 0 -#define IMX8MP_HSIOBLK_PD_USB_PHY1 1 -#define IMX8MP_HSIOBLK_PD_USB_PHY2 2 -#define IMX8MP_HSIOBLK_PD_PCIE 3 -#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 - -#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0 -#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1 -#define IMX8MP_MEDIABLK_PD_LCDIF_1 2 -#define IMX8MP_MEDIABLK_PD_ISI 3 -#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 -#define IMX8MP_MEDIABLK_PD_LCDIF_2 5 -#define IMX8MP_MEDIABLK_PD_ISP 6 -#define IMX8MP_MEDIABLK_PD_DWE 7 -#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8 - -#define IMX8MP_HDMIBLK_PD_IRQSTEER 0 -#define IMX8MP_HDMIBLK_PD_LCDIF 1 -#define IMX8MP_HDMIBLK_PD_PAI 2 -#define IMX8MP_HDMIBLK_PD_PVI 3 -#define IMX8MP_HDMIBLK_PD_TRNG 4 -#define IMX8MP_HDMIBLK_PD_HDMI_TX 5 -#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6 -#define IMX8MP_HDMIBLK_PD_HDCP 7 -#define IMX8MP_HDMIBLK_PD_HRV 8 - -#define IMX8MP_VPUBLK_PD_G1 0 -#define IMX8MP_VPUBLK_PD_G2 1 -#define IMX8MP_VPUBLK_PD_VC8000E 2 - -#endif diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h deleted file mode 100755 index 9f7d0f1e7c3..00000000000 --- a/include/dt-bindings/power/imx8mq-power.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> - */ - -#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ -#define __DT_BINDINGS_IMX8MQ_POWER_H__ - -#define IMX8M_POWER_DOMAIN_MIPI 0 -#define IMX8M_POWER_DOMAIN_PCIE1 1 -#define IMX8M_POWER_DOMAIN_USB_OTG1 2 -#define IMX8M_POWER_DOMAIN_USB_OTG2 3 -#define IMX8M_POWER_DOMAIN_DDR1 4 -#define IMX8M_POWER_DOMAIN_GPU 5 -#define IMX8M_POWER_DOMAIN_VPU 6 -#define IMX8M_POWER_DOMAIN_DISP 7 -#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 -#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 -#define IMX8M_POWER_DOMAIN_PCIE2 10 - -#define IMX8MQ_VPUBLK_PD_G1 0 -#define IMX8MQ_VPUBLK_PD_G2 1 - -#endif diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h deleted file mode 100644 index a556b2e96df..00000000000 --- a/include/dt-bindings/power/imx8ulp-power.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright 2021 NXP - */ - -#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__ -#define __DT_BINDINGS_IMX8ULP_POWER_H__ - -#define IMX8ULP_PD_DMA1 0 -#define IMX8ULP_PD_FLEXSPI2 1 -#define IMX8ULP_PD_USB0 2 -#define IMX8ULP_PD_USDHC0 3 -#define IMX8ULP_PD_USDHC1 4 -#define IMX8ULP_PD_USDHC2_USB1 5 -#define IMX8ULP_PD_DCNANO 6 -#define IMX8ULP_PD_EPDC 7 -#define IMX8ULP_PD_DMA2 8 -#define IMX8ULP_PD_GPU2D 9 -#define IMX8ULP_PD_GPU3D 10 -#define IMX8ULP_PD_HIFI4 11 -#define IMX8ULP_PD_ISI 12 -#define IMX8ULP_PD_MIPI_CSI 13 -#define IMX8ULP_PD_MIPI_DSI 14 -#define IMX8ULP_PD_PXP 15 - -#endif diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h deleted file mode 100644 index bb92452ffb8..00000000000 --- a/include/dt-bindings/reset/imx7-reset.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Impinj, Inc. - * - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - */ - -#ifndef DT_BINDING_RESET_IMX7_H -#define DT_BINDING_RESET_IMX7_H - -#define IMX7_RESET_A7_CORE_POR_RESET0 0 -#define IMX7_RESET_A7_CORE_POR_RESET1 1 -#define IMX7_RESET_A7_CORE_RESET0 2 -#define IMX7_RESET_A7_CORE_RESET1 3 -#define IMX7_RESET_A7_DBG_RESET0 4 -#define IMX7_RESET_A7_DBG_RESET1 5 -#define IMX7_RESET_A7_ETM_RESET0 6 -#define IMX7_RESET_A7_ETM_RESET1 7 -#define IMX7_RESET_A7_SOC_DBG_RESET 8 -#define IMX7_RESET_A7_L2RESET 9 -#define IMX7_RESET_SW_M4C_RST 10 -#define IMX7_RESET_SW_M4P_RST 11 -#define IMX7_RESET_EIM_RST 12 -#define IMX7_RESET_HSICPHY_PORT_RST 13 -#define IMX7_RESET_USBPHY1_POR 14 -#define IMX7_RESET_USBPHY1_PORT_RST 15 -#define IMX7_RESET_USBPHY2_POR 16 -#define IMX7_RESET_USBPHY2_PORT_RST 17 -#define IMX7_RESET_MIPI_PHY_MRST 18 -#define IMX7_RESET_MIPI_PHY_SRST 19 - -/* - * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN - * and PCIEPHY_G_RST - */ -#define IMX7_RESET_PCIEPHY 20 -#define IMX7_RESET_PCIEPHY_PERST 21 - -/* - * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it - * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht - * of as one - */ -#define IMX7_RESET_PCIE_CTRL_APPS_EN 22 -#define IMX7_RESET_DDRC_PRST 23 -#define IMX7_RESET_DDRC_CORE_RST 24 - -#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 - -#define IMX7_RESET_NUM 26 - -#endif diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h deleted file mode 100644 index 2e8c9104b66..00000000000 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 NXP - */ - -#ifndef DT_BINDING_RESET_IMX8MP_H -#define DT_BINDING_RESET_IMX8MP_H - -#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 -#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 -#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 -#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 -#define IMX8MP_RESET_A53_CORE_RESET0 4 -#define IMX8MP_RESET_A53_CORE_RESET1 5 -#define IMX8MP_RESET_A53_CORE_RESET2 6 -#define IMX8MP_RESET_A53_CORE_RESET3 7 -#define IMX8MP_RESET_A53_DBG_RESET0 8 -#define IMX8MP_RESET_A53_DBG_RESET1 9 -#define IMX8MP_RESET_A53_DBG_RESET2 10 -#define IMX8MP_RESET_A53_DBG_RESET3 11 -#define IMX8MP_RESET_A53_ETM_RESET0 12 -#define IMX8MP_RESET_A53_ETM_RESET1 13 -#define IMX8MP_RESET_A53_ETM_RESET2 14 -#define IMX8MP_RESET_A53_ETM_RESET3 15 -#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 -#define IMX8MP_RESET_A53_L2RESET 17 -#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 -#define IMX8MP_RESET_OTG1_PHY_RESET 19 -#define IMX8MP_RESET_OTG2_PHY_RESET 20 -#define IMX8MP_RESET_SUPERMIX_RESET 21 -#define IMX8MP_RESET_AUDIOMIX_RESET 22 -#define IMX8MP_RESET_MLMIX_RESET 23 -#define IMX8MP_RESET_PCIEPHY 24 -#define IMX8MP_RESET_PCIEPHY_PERST 25 -#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 -#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 -#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 -#define IMX8MP_RESET_MEDIA_RESET 29 -#define IMX8MP_RESET_GPU2D_RESET 30 -#define IMX8MP_RESET_GPU3D_RESET 31 -#define IMX8MP_RESET_GPU_RESET 32 -#define IMX8MP_RESET_VPU_RESET 33 -#define IMX8MP_RESET_VPU_G1_RESET 34 -#define IMX8MP_RESET_VPU_G2_RESET 35 -#define IMX8MP_RESET_VPUVC8KE_RESET 36 -#define IMX8MP_RESET_NOC_RESET 37 - -#define IMX8MP_RESET_NUM 38 - -#endif diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h deleted file mode 100755 index 705870693ec..00000000000 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - * - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - */ - -#ifndef DT_BINDING_RESET_IMX8MQ_H -#define DT_BINDING_RESET_IMX8MQ_H - -#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 -#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 -#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 -#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 -#define IMX8MQ_RESET_A53_CORE_RESET0 4 -#define IMX8MQ_RESET_A53_CORE_RESET1 5 -#define IMX8MQ_RESET_A53_CORE_RESET2 6 -#define IMX8MQ_RESET_A53_CORE_RESET3 7 -#define IMX8MQ_RESET_A53_DBG_RESET0 8 -#define IMX8MQ_RESET_A53_DBG_RESET1 9 -#define IMX8MQ_RESET_A53_DBG_RESET2 10 -#define IMX8MQ_RESET_A53_DBG_RESET3 11 -#define IMX8MQ_RESET_A53_ETM_RESET0 12 -#define IMX8MQ_RESET_A53_ETM_RESET1 13 -#define IMX8MQ_RESET_A53_ETM_RESET2 14 -#define IMX8MQ_RESET_A53_ETM_RESET3 15 -#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 -#define IMX8MQ_RESET_A53_L2RESET 17 -#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 -#define IMX8MQ_RESET_OTG1_PHY_RESET 19 -#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DISP_RESET 31 -#define IMX8MQ_RESET_GPU_RESET 32 -#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_SW_M4C_RST 50 -#define IMX8MQ_RESET_SW_M4P_RST 51 -#define IMX8MQ_RESET_M4_ENABLE 52 - -#define IMX8MQ_RESET_NUM 53 - -#endif diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h deleted file mode 100644 index e99a4735c3c..00000000000 --- a/include/dt-bindings/reset/imx8ulp-pcc-reset.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2021 NXP - */ - -#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H -#define DT_BINDING_PCC_RESET_IMX8ULP_H - -/* PCC3 */ -#define PCC3_WDOG3_SWRST 0 -#define PCC3_WDOG4_SWRST 1 -#define PCC3_LPIT1_SWRST 2 -#define PCC3_TPM4_SWRST 3 -#define PCC3_TPM5_SWRST 4 -#define PCC3_FLEXIO1_SWRST 5 -#define PCC3_I3C2_SWRST 6 -#define PCC3_LPI2C4_SWRST 7 -#define PCC3_LPI2C5_SWRST 8 -#define PCC3_LPUART4_SWRST 9 -#define PCC3_LPUART5_SWRST 10 -#define PCC3_LPSPI4_SWRST 11 -#define PCC3_LPSPI5_SWRST 12 - -/* PCC4 */ -#define PCC4_FLEXSPI2_SWRST 0 -#define PCC4_TPM6_SWRST 1 -#define PCC4_TPM7_SWRST 2 -#define PCC4_LPI2C6_SWRST 3 -#define PCC4_LPI2C7_SWRST 4 -#define PCC4_LPUART6_SWRST 5 -#define PCC4_LPUART7_SWRST 6 -#define PCC4_SAI4_SWRST 7 -#define PCC4_SAI5_SWRST 8 -#define PCC4_USDHC0_SWRST 9 -#define PCC4_USDHC1_SWRST 10 -#define PCC4_USDHC2_SWRST 11 -#define PCC4_USB0_SWRST 12 -#define PCC4_USB0_PHY_SWRST 13 -#define PCC4_USB1_SWRST 14 -#define PCC4_USB1_PHY_SWRST 15 -#define PCC4_ENET_SWRST 16 - -/* PCC5 */ -#define PCC5_TPM8_SWRST 0 -#define PCC5_SAI6_SWRST 1 -#define PCC5_SAI7_SWRST 2 -#define PCC5_SPDIF_SWRST 3 -#define PCC5_ISI_SWRST 4 -#define PCC5_CSI_REGS_SWRST 5 -#define PCC5_CSI_SWRST 6 -#define PCC5_DSI_SWRST 7 -#define PCC5_WDOG5_SWRST 8 -#define PCC5_EPDC_SWRST 9 -#define PCC5_PXP_SWRST 10 -#define PCC5_GPU2D_SWRST 11 -#define PCC5_GPU3D_SWRST 12 -#define PCC5_DC_NANO_SWRST 13 - -#endif /*DT_BINDING_RESET_IMX8ULP_H */ diff --git a/include/dt-bindings/sound/fsl-imx-audmux.h b/include/dt-bindings/sound/fsl-imx-audmux.h deleted file mode 100644 index 15f138bebe1..00000000000 --- a/include/dt-bindings/sound/fsl-imx-audmux.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_FSL_IMX_AUDMUX_H -#define __DT_FSL_IMX_AUDMUX_H - -#define MX27_AUDMUX_HPCR1_SSI0 0 -#define MX27_AUDMUX_HPCR2_SSI1 1 -#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 -#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 -#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 -#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 - -#define MX31_AUDMUX_PORT1_SSI0 0 -#define MX31_AUDMUX_PORT2_SSI1 1 -#define MX31_AUDMUX_PORT3_SSI_PINS_3 2 -#define MX31_AUDMUX_PORT4_SSI_PINS_4 3 -#define MX31_AUDMUX_PORT5_SSI_PINS_5 4 -#define MX31_AUDMUX_PORT6_SSI_PINS_6 5 -#define MX31_AUDMUX_PORT7_SSI_PINS_7 6 - -#define MX51_AUDMUX_PORT1_SSI0 0 -#define MX51_AUDMUX_PORT2_SSI1 1 -#define MX51_AUDMUX_PORT3 2 -#define MX51_AUDMUX_PORT4 3 -#define MX51_AUDMUX_PORT5 4 -#define MX51_AUDMUX_PORT6 5 -#define MX51_AUDMUX_PORT7 6 - -/* - * TFCSEL/RFCSEL (i.MX27) or TFSEL/TCSEL/RFSEL/RCSEL (i.MX31/51/53/6Q) - * can be sourced from Rx/Tx. - */ -#define IMX_AUDMUX_RXFS 0x8 -#define IMX_AUDMUX_RXCLK 0x8 - -/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ -#define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) -#define IMX_AUDMUX_V1_PCR_INMEN (1 << 8) -#define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10) -#define IMX_AUDMUX_V1_PCR_SYN (1 << 12) -#define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) -#define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) -#define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24) -#define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25) -#define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) -#define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30) -#define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31) - -/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ -#define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31) -#define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) -#define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) -#define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) -#define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21) -#define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) -#define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) -#define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) -#define IMX_AUDMUX_V2_PTCR_SYN (1 << 11) - -#define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) -#define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12) -#define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) -#define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) - -#endif /* __DT_FSL_IMX_AUDMUX_H */ diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index a75b5a35b6e..8dfb1bc9527 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -18,6 +18,7 @@ #include <efi_api.h> #include <tpm-v2.h> +#include <tpm_tcg2.h> /* TPMV2 only */ #define TCG2_EVENT_LOG_FORMAT_TCG_2 0x00000002 @@ -25,14 +26,6 @@ #define PE_COFF_IMAGE 0x0000000000000010 #define EFI_TCG2_MAX_PCR_INDEX 23 - -/* Algorithm Registry */ -#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001 -#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002 -#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x00000004 -#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x00000008 -#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 - #define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1 #define TPM2_EVENT_LOG_SIZE CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE diff --git a/include/fdt_support.h b/include/fdt_support.h index 4b71b8948d9..741e2360c22 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -463,4 +463,14 @@ void fdt_fixup_board_enet(void *blob); #ifdef CONFIG_CMD_PSTORE void fdt_fixup_pstore(void *blob); #endif + +/** + * fdt_kaslrseed() - create a 'kaslr-seed' node in chosen + * + * @blob: fdt blob + * @overwrite: do not overwrite existing non-zero node unless true + * Return: 0 if OK, -ve on error + */ +int fdt_kaslrseed(void *blob, bool overwrite); + #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/sysinfo.h b/include/sysinfo.h index 524c7d6b223..8a77ef44856 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -43,8 +43,17 @@ enum sysinfo_id { SYSINFO_ID_NONE, /* For SMBIOS tables */ + SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER, + SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT, SYSINFO_ID_SMBIOS_SYSTEM_VERSION, + SYSINFO_ID_SMBIOS_SYSTEM_SERIAL, + SYSINFO_ID_SMBIOS_SYSTEM_SKU, + SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, + SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER, + SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT, SYSINFO_ID_SMBIOS_BASEBOARD_VERSION, + SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL, + SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG, /* For show_board_info() */ SYSINFO_ID_BOARD_MODEL, diff --git a/include/tpm-v2.h b/include/tpm-v2.h index c9d5cb6d3e5..4fd19c52fd7 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -55,59 +55,6 @@ struct udevice; #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30) #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31) -/* - * event types, cf. - * "TCG Server Management Domain Firmware Profile Specification", - * rev 1.00, 2020-05-01 - */ -#define EV_POST_CODE ((u32)0x00000001) -#define EV_NO_ACTION ((u32)0x00000003) -#define EV_SEPARATOR ((u32)0x00000004) -#define EV_ACTION ((u32)0x00000005) -#define EV_TAG ((u32)0x00000006) -#define EV_S_CRTM_CONTENTS ((u32)0x00000007) -#define EV_S_CRTM_VERSION ((u32)0x00000008) -#define EV_CPU_MICROCODE ((u32)0x00000009) -#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A) -#define EV_TABLE_OF_DEVICES ((u32)0x0000000B) -#define EV_COMPACT_HASH ((u32)0x0000000C) - -/* - * event types, cf. - * "TCG PC Client Platform Firmware Profile Specification", Family "2.0" - * Level 00 Version 1.05 Revision 23, May 7, 2021 - */ -#define EV_EFI_EVENT_BASE ((u32)0x80000000) -#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001) -#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002) -#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003) -#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004) -#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005) -#define EV_EFI_GPT_EVENT ((u32)0x80000006) -#define EV_EFI_ACTION ((u32)0x80000007) -#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008) -#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009) -#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A) -#define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B) -#define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C) -#define EV_EFI_HCRTM_EVENT ((u32)0x80000010) -#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0) -#define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1) -#define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2) - -#define EFI_CALLING_EFI_APPLICATION \ - "Calling EFI Application from Boot Option" -#define EFI_RETURNING_FROM_EFI_APPLICATION \ - "Returning from EFI Application from Boot Option" -#define EFI_EXIT_BOOT_SERVICES_INVOCATION \ - "Exit Boot Services Invocation" -#define EFI_EXIT_BOOT_SERVICES_FAILED \ - "Exit Boot Services Returned with Failure" -#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \ - "Exit Boot Services Returned with Success" -#define EFI_DTB_EVENT_STRING \ - "DTB DATA" - /* TPMS_TAGGED_PROPERTY Structure */ struct tpms_tagged_property { u32 property; @@ -150,23 +97,6 @@ struct tpms_capability_data { } __packed; /** - * SHA1 Event Log Entry Format - * - * @pcr_index: PCRIndex event extended to - * @event_type: Type of event (see EFI specs) - * @digest: Value extended into PCR index - * @event_size: Size of event - * @event: Event data - */ -struct tcg_pcr_event { - u32 pcr_index; - u32 event_type; - u8 digest[TPM2_SHA1_DIGEST_SIZE]; - u32 event_size; - u8 event[]; -} __packed; - -/** * Definition of TPMU_HA Union */ union tpmu_ha { @@ -200,67 +130,6 @@ struct tpml_digest_values { } __packed; /** - * Crypto Agile Log Entry Format - * - * @pcr_index: PCRIndex event extended to - * @event_type: Type of event - * @digests: List of digestsextended to PCR index - * @event_size: Size of the event data - * @event: Event data - */ -struct tcg_pcr_event2 { - u32 pcr_index; - u32 event_type; - struct tpml_digest_values digests; - u32 event_size; - u8 event[]; -} __packed; - -/** - * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information - * - * @algorithm_id: algorithm defined in enum tpm2_algorithms - * @digest_size: size of the algorithm - */ -struct tcg_efi_spec_id_event_algorithm_size { - u16 algorithm_id; - u16 digest_size; -} __packed; - -#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03" -#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2 -#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0 -#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2 - -/** - * struct TCG_EfiSpecIDEventStruct - content of the event log header - * - * @signature: signature, set to Spec ID Event03 - * @platform_class: class defined in TCG ACPI Specification - * Client Common Header. - * @spec_version_minor: minor version - * @spec_version_major: major version - * @spec_version_errata: major version - * @uintn_size: size of the efi_uintn_t fields used in various - * data structures used in this specification. - * 0x01 indicates u32 and 0x02 indicates u64 - * @number_of_algorithms: hashing algorithms used in this event log - * @digest_sizes: array of number_of_algorithms pairs - * 1st member defines the algorithm id - * 2nd member defines the algorithm size - */ -struct tcg_efi_spec_id_event { - u8 signature[16]; - u32 platform_class; - u8 spec_version_minor; - u8 spec_version_major; - u8 spec_errata; - u8 uintn_size; - u32 number_of_algorithms; - struct tcg_efi_spec_id_event_algorithm_size digest_sizes[]; -} __packed; - -/** * TPM2 Structure Tags for command/response buffers. * * @TPM2_ST_NO_SESSIONS: the command does not need an authentication. @@ -409,48 +278,40 @@ struct digest_info { #define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 static const struct digest_info hash_algo_list[] = { +#if IS_ENABLED(CONFIG_SHA1) { "sha1", TPM2_ALG_SHA1, TCG2_BOOT_HASH_ALG_SHA1, TPM2_SHA1_DIGEST_SIZE, }, +#endif +#if IS_ENABLED(CONFIG_SHA256) { "sha256", TPM2_ALG_SHA256, TCG2_BOOT_HASH_ALG_SHA256, TPM2_SHA256_DIGEST_SIZE, }, +#endif +#if IS_ENABLED(CONFIG_SHA384) { "sha384", TPM2_ALG_SHA384, TCG2_BOOT_HASH_ALG_SHA384, TPM2_SHA384_DIGEST_SIZE, }, +#endif +#if IS_ENABLED(CONFIG_SHA512) { "sha512", TPM2_ALG_SHA512, TCG2_BOOT_HASH_ALG_SHA512, TPM2_SHA512_DIGEST_SIZE, }, +#endif }; -static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a) -{ - switch (a) { - case TPM2_ALG_SHA1: - return TPM2_SHA1_DIGEST_SIZE; - case TPM2_ALG_SHA256: - return TPM2_SHA256_DIGEST_SIZE; - case TPM2_ALG_SHA384: - return TPM2_SHA384_DIGEST_SIZE; - case TPM2_ALG_SHA512: - return TPM2_SHA512_DIGEST_SIZE; - default: - return 0; - } -} - /* NV index attributes */ enum tpm_index_attrs { TPMA_NV_PPWRITE = 1UL << 0, @@ -531,188 +392,6 @@ enum { }; /** - * struct tcg2_event_log - Container for managing the platform event log - * - * @log: Address of the log - * @log_position: Current entry position - * @log_size: Log space available - * @found: Boolean indicating if an existing log was discovered - */ -struct tcg2_event_log { - u8 *log; - u32 log_position; - u32 log_size; - bool found; -}; - -/** - * Create a list of digests of the supported PCR banks for a given input data - * - * @dev TPM device - * @input Data - * @length Length of the data to calculate the digest - * @digest_list List of digests to fill in - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, - struct tpml_digest_values *digest_list); - -/** - * Get the event size of the specified digests - * - * @digest_list List of digests for the event - * - * Return: Size in bytes of the event - */ -u32 tcg2_event_get_size(struct tpml_digest_values *digest_list); - -/** - * tcg2_get_active_pcr_banks - * - * @dev TPM device - * @active_pcr_banks Bitmask of PCR algorithms supported - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks); - -/** - * tcg2_log_append - Append an event to an event log - * - * @pcr_index Index of the PCR - * @event_type Type of event - * @digest_list List of digests to add - * @size Size of event - * @event Event data - * @log Log buffer to append the event to - */ -void tcg2_log_append(u32 pcr_index, u32 event_type, - struct tpml_digest_values *digest_list, u32 size, - const u8 *event, u8 *log); - -/** - * Extend the PCR with specified digests - * - * @dev TPM device - * @pcr_index Index of the PCR - * @digest_list List of digests to extend - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index, - struct tpml_digest_values *digest_list); - -/** - * Read the PCR into a list of digests - * - * @dev TPM device - * @pcr_index Index of the PCR - * @digest_list List of digests to extend - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_pcr_read(struct udevice *dev, u32 pcr_index, - struct tpml_digest_values *digest_list); - -/** - * Measure data into the TPM PCRs and the platform event log. - * - * @dev TPM device - * @log Platform event log - * @pcr_index Index of the PCR - * @size Size of the data or 0 for event only - * @data Pointer to the data or NULL for event only - * @event_type Event log type - * @event_size Size of the event - * @event Pointer to the event - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog, - u32 pcr_index, u32 size, const u8 *data, u32 event_type, - u32 event_size, const u8 *event); - -#define tcg2_measure_event(dev, elog, pcr_index, event_type, size, event) \ - tcg2_measure_data(dev, elog, pcr_index, 0, NULL, event_type, size, \ - event) - -/** - * Prepare the event log buffer. This function tries to discover an existing - * event log in memory from a previous bootloader stage. If such a log exists - * and the PCRs are not extended, the log is "replayed" to extend the PCRs. - * If no log is discovered, create the log header. - * - * @dev TPM device - * @elog Platform event log. The log pointer and log_size - * members must be initialized to either 0 or to a valid - * memory region, in which case any existing log - * discovered will be copied to the specified memory - * region. - * @ignore_existing_log Boolean to indicate whether or not to ignore an - * existing platform log in memory - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, - bool ignore_existing_log); - -/** - * Begin measurements. - * - * @dev TPM device - * @elog Platform event log. The log pointer and log_size - * members must be initialized to either 0 or to a valid - * memory region, in which case any existing log - * discovered will be copied to the specified memory - * region. - * @ignore_existing_log Boolean to indicate whether or not to ignore an - * existing platform log in memory - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog, - bool ignore_existing_log); - -/** - * Stop measurements and record separator events. - * - * @dev TPM device - * @elog Platform event log - * @error Boolean to indicate whether an error ocurred or not - */ -void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, - bool error); - -/** - * Get the platform event log address and size. - * - * @dev TPM device - * @addr Address of the log - * @size Size of the log - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size); - -/** - * Get the first TPM2 device found. - * - * @dev TPM device - * - * Return: zero on success, negative errno otherwise - */ -int tcg2_platform_get_tpm2(struct udevice **dev); - -/** - * Platform-specific function for handling TPM startup errors - * - * @dev TPM device - * @rc The TPM response code - */ -void tcg2_platform_startup_error(struct udevice *dev, int rc); - -/** * Issue a TPM2_Startup command. * * @dev TPM device @@ -835,14 +514,11 @@ u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks * * @dev: TPM device - * @supported_pcr: bitmask with the algorithms supported - * @active_pcr: bitmask with the active algorithms - * @pcr_banks: number of PCR banks + * @pcrs: struct tpml_pcr_selection of available PCRs * * @return 0 on success, code of operation or negative errno on failure */ -int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, - u32 *pcr_banks); +int tpm2_get_pcr_info(struct udevice *dev, struct tpml_pcr_selection *pcrs); /** * Issue a TPM2_DictionaryAttackLockReset command. @@ -1029,11 +705,47 @@ enum tpm2_algorithms tpm2_name_to_algorithm(const char *name); const char *tpm2_algorithm_name(enum tpm2_algorithms); /** - * tpm2_algorithm_to_mask() - Get a TCG hash mask for algorithm + * tpm2_algorithm_to_len() - Return an algorithm length for supported algorithm id + * + * @algorithm_id: algorithm defined in enum tpm2_algorithms + * Return: len or 0 if not supported + */ +u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo); + +/* + * When measured boot is enabled via EFI or bootX commands all the algorithms + * above are selected by our Kconfigs. Due to U-Boots nature of being small there + * are cases where we need some functionality from the TPM -- e.g storage or RNG + * but we don't want to support measurements. + * + * The choice of hash algorithms are determined by the platform and the TPM + * configuration. Failing to cap a PCR in a bank which the platform left + * active is a security vulnerability. It permits the unsealing of secrets + * if an attacker can replay a good set of measurements into an unused bank. + * + * On top of that a previous stage bootloader (e.g TF-A), migh pass an eventlog + * since it doesn't have a TPM driver, which U-Boot needs to replace. The algorit h + * choice is a compile time option in that case and we need to make sure we conform. + * + * Add a variable here that sums the supported algorithms U-Boot was compiled + * with so we can refuse to do measurements if we don't support all of them + */ + +/** + * tpm2_allow_extend() - Check if extending PCRs is allowed and safe + * + * @dev: TPM device + * Return: true if allowed + */ +bool tpm2_allow_extend(struct udevice *dev); + +/** + * tpm2_is_active_pcr() - check the pcr_select. If at least one of the PCRs + * supports the algorithm add it on the active ones * - * @hash_alg: TCG defined algorithm - * Return: TCG hashing algorithm bitmaps (or 0 if algo not supported) + * @selection: PCR selection structure + * Return: True if the algorithm is active */ -u32 tpm2_algorithm_to_mask(enum tpm2_algorithms); +bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection); #endif /* __TPM_V2_H */ diff --git a/include/tpm_tcg2.h b/include/tpm_tcg2.h new file mode 100644 index 00000000000..6519004cc41 --- /dev/null +++ b/include/tpm_tcg2.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Defines APIs and structures that adhere to + * https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firmware-profile-specification/ + * https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/ + * + * Copyright (c) 2020 Linaro Limited + */ + +#ifndef __TPM_TCG_V2_H +#define __TPM_TCG_V2_H + +#include <tpm-v2.h> + +/* + * event types, cf. + * "TCG Server Management Domain Firmware Profile Specification", + * rev 1.00, 2020-05-01 + */ +#define EV_POST_CODE ((u32)0x00000001) +#define EV_NO_ACTION ((u32)0x00000003) +#define EV_SEPARATOR ((u32)0x00000004) +#define EV_ACTION ((u32)0x00000005) +#define EV_TAG ((u32)0x00000006) +#define EV_S_CRTM_CONTENTS ((u32)0x00000007) +#define EV_S_CRTM_VERSION ((u32)0x00000008) +#define EV_CPU_MICROCODE ((u32)0x00000009) +#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A) +#define EV_TABLE_OF_DEVICES ((u32)0x0000000B) +#define EV_COMPACT_HASH ((u32)0x0000000C) + +/* + * event types, cf. + * "TCG PC Client Platform Firmware Profile Specification", Family "2.0" + * Level 00 Version 1.05 Revision 23, May 7, 2021 + */ +#define EV_EFI_EVENT_BASE ((u32)0x80000000) +#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001) +#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002) +#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003) +#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004) +#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005) +#define EV_EFI_GPT_EVENT ((u32)0x80000006) +#define EV_EFI_ACTION ((u32)0x80000007) +#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008) +#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009) +#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A) +#define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B) +#define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C) +#define EV_EFI_HCRTM_EVENT ((u32)0x80000010) +#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0) +#define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1) +#define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2) + +#define EFI_CALLING_EFI_APPLICATION \ + "Calling EFI Application from Boot Option" +#define EFI_RETURNING_FROM_EFI_APPLICATION \ + "Returning from EFI Application from Boot Option" +#define EFI_EXIT_BOOT_SERVICES_INVOCATION \ + "Exit Boot Services Invocation" +#define EFI_EXIT_BOOT_SERVICES_FAILED \ + "Exit Boot Services Returned with Failure" +#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \ + "Exit Boot Services Returned with Success" +#define EFI_DTB_EVENT_STRING \ + "DTB DATA" + +/** + * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information + * + * @algorithm_id: algorithm defined in enum tpm2_algorithms + * @digest_size: size of the algorithm + */ +struct tcg_efi_spec_id_event_algorithm_size { + u16 algorithm_id; + u16 digest_size; +} __packed; + +/** + * SHA1 Event Log Entry Format + * + * @pcr_index: PCRIndex event extended to + * @event_type: Type of event (see EFI specs) + * @digest: Value extended into PCR index + * @event_size: Size of event + * @event: Event data + */ +struct tcg_pcr_event { + u32 pcr_index; + u32 event_type; + u8 digest[TPM2_SHA1_DIGEST_SIZE]; + u32 event_size; + u8 event[]; +} __packed; + +/** + * tcg2_get_pcr_info() - get the supported, active PCRs and number of banks + * + * @dev: TPM device + * @supported_pcr: bitmask with the algorithms supported + * @active_pcr: bitmask with the active algorithms + * @pcr_banks: number of PCR banks + * + * @return 0 on success, code of operation or negative errno on failure + */ +int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, + u32 *pcr_banks); + +/** + * Crypto Agile Log Entry Format + * + * @pcr_index: PCRIndex event extended to + * @event_type: Type of event + * @digests: List of digestsextended to PCR index + * @event_size: Size of the event data + * @event: Event data + */ +struct tcg_pcr_event2 { + u32 pcr_index; + u32 event_type; + struct tpml_digest_values digests; + u32 event_size; + u8 event[]; +} __packed; + +/** + * struct TCG_EfiSpecIDEventStruct - content of the event log header + * + * @signature: signature, set to Spec ID Event03 + * @platform_class: class defined in TCG ACPI Specification + * Client Common Header. + * @spec_version_minor: minor version + * @spec_version_major: major version + * @spec_version_errata: major version + * @uintn_size: size of the efi_uintn_t fields used in various + * data structures used in this specification. + * 0x01 indicates u32 and 0x02 indicates u64 + * @number_of_algorithms: hashing algorithms used in this event log + * @digest_sizes: array of number_of_algorithms pairs + * 1st member defines the algorithm id + * 2nd member defines the algorithm size + */ +struct tcg_efi_spec_id_event { + u8 signature[16]; + u32 platform_class; + u8 spec_version_minor; + u8 spec_version_major; + u8 spec_errata; + u8 uintn_size; + u32 number_of_algorithms; + struct tcg_efi_spec_id_event_algorithm_size digest_sizes[]; +} __packed; + +#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03" +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2 +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0 +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2 +/** + * struct tcg2_event_log - Container for managing the platform event log + * + * @log: Address of the log + * @log_position: Current entry position + * @log_size: Log space available + * @found: Boolean indicating if an existing log was discovered + */ +struct tcg2_event_log { + u8 *log; + u32 log_position; + u32 log_size; + bool found; +}; + +/** + * Create a list of digests of the supported PCR banks for a given input data + * + * @dev TPM device + * @input Data + * @length Length of the data to calculate the digest + * @digest_list List of digests to fill in + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, + struct tpml_digest_values *digest_list); + +/** + * Get the event size of the specified digests + * + * @digest_list List of digests for the event + * + * Return: Size in bytes of the event + */ +u32 tcg2_event_get_size(struct tpml_digest_values *digest_list); + +/** + * tcg2_get_active_pcr_banks + * + * @dev TPM device + * @active_pcr_banks Bitmask of PCR algorithms supported + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks); + +/** + * tcg2_log_append - Append an event to an event log + * + * @pcr_index Index of the PCR + * @event_type Type of event + * @digest_list List of digests to add + * @size Size of event + * @event Event data + * @log Log buffer to append the event to + */ +void tcg2_log_append(u32 pcr_index, u32 event_type, + struct tpml_digest_values *digest_list, u32 size, + const u8 *event, u8 *log); + +/** + * Extend the PCR with specified digests + * + * @dev TPM device + * @pcr_index Index of the PCR + * @digest_list List of digests to extend + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index, + struct tpml_digest_values *digest_list); + +/** + * Read the PCR into a list of digests + * + * @dev TPM device + * @pcr_index Index of the PCR + * @digest_list List of digests to extend + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_pcr_read(struct udevice *dev, u32 pcr_index, + struct tpml_digest_values *digest_list); + +/** + * Measure data into the TPM PCRs and the platform event log. + * + * @dev TPM device + * @log Platform event log + * @pcr_index Index of the PCR + * @size Size of the data or 0 for event only + * @data Pointer to the data or NULL for event only + * @event_type Event log type + * @event_size Size of the event + * @event Pointer to the event + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog, + u32 pcr_index, u32 size, const u8 *data, u32 event_type, + u32 event_size, const u8 *event); + +#define tcg2_measure_event(dev, elog, pcr_index, event_type, size, event) \ + tcg2_measure_data(dev, elog, pcr_index, 0, NULL, event_type, size, \ + event) + +/** + * Prepare the event log buffer. This function tries to discover an existing + * event log in memory from a previous bootloader stage. If such a log exists + * and the PCRs are not extended, the log is "replayed" to extend the PCRs. + * If no log is discovered, create the log header. + * + * @dev TPM device + * @elog Platform event log. The log pointer and log_size + * members must be initialized to either 0 or to a valid + * memory region, in which case any existing log + * discovered will be copied to the specified memory + * region. + * @ignore_existing_log Boolean to indicate whether or not to ignore an + * existing platform log in memory + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, + bool ignore_existing_log); + +/** + * Begin measurements. + * + * @dev TPM device + * @elog Platform event log. The log pointer and log_size + * members must be initialized to either 0 or to a valid + * memory region, in which case any existing log + * discovered will be copied to the specified memory + * region. + * @ignore_existing_log Boolean to indicate whether or not to ignore an + * existing platform log in memory + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog, + bool ignore_existing_log); + +/** + * Stop measurements and record separator events. + * + * @dev TPM device + * @elog Platform event log + * @error Boolean to indicate whether an error ocurred or not + */ +void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, + bool error); + +/** + * Get the platform event log address and size. + * + * @dev TPM device + * @addr Address of the log + * @size Size of the log + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size); + +/** + * Get the first TPM2 device found. + * + * @dev TPM device + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_platform_get_tpm2(struct udevice **dev); + +/** + * Platform-specific function for handling TPM startup errors + * + * @dev TPM device + * @rc The TPM response code + */ +void tcg2_platform_startup_error(struct udevice *dev, int rc); + +/** + * tcg2_algorithm_to_mask() - Get a TCG hash mask for algorithm + * + * @hash_alg: TCG defined algorithm + * Return: TCG hashing algorithm bitmaps (or 0 if algo not supported) + */ +u32 tcg2_algorithm_to_mask(enum tpm2_algorithms); + +#endif /* __TPM_TCG_V2_H */ diff --git a/include/u-boot/zlib.h b/include/u-boot/zlib.h index ee19f460958..a33cc8780d3 100644 --- a/include/u-boot/zlib.h +++ b/include/u-boot/zlib.h @@ -49,6 +49,9 @@ extern "C" { #endif +#define ZLIB_VERSION "1.2.3" +#define ZLIB_VERNUM 0x1230 + /* #include "zconf.h" */ /* included directly here */ /* zconf.h -- configuration of the zlib compression library * Copyright (C) 1995-2005 Jean-loup Gailly. @@ -481,6 +484,7 @@ typedef gz_header FAR *gz_headerp; #define Z_DATA_ERROR (-3) #define Z_MEM_ERROR (-4) #define Z_BUF_ERROR (-5) +#define Z_VERSION_ERROR (-6) /* Return codes for the compression/decompression functions. Negative * values are errors, positive values are used for special but normal events. */ @@ -519,11 +523,11 @@ typedef gz_header FAR *gz_headerp; ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush)); ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level, - int stream_size)); + const char *version, int stream_size)); ZEXTERN int ZEXPORT deflateEnd OF((z_streamp strm)); ZEXTERN int ZEXPORT deflateInit2_ OF((z_streamp strm, int level, int method, int windowBits, int memLevel, - int strategy, + int strategy, const char *version, int stream_size)); ZEXTERN int ZEXPORT deflateReset OF((z_streamp strm)); ZEXTERN int ZEXPORT deflateSetDictionary OF((z_streamp strm, @@ -549,7 +553,7 @@ ZEXTERN int ZEXPORT deflateCopy OF((z_streamp dest, ZEXTERN int ZEXPORT inflateInit_ OF((z_streamp strm, - int stream_size)); + const char *version, int stream_size)); ZEXTERN int ZEXPORT inflate OF((z_streamp strm, int flush)); /* inflate decompresses as much data as possible, and stops when the input @@ -739,11 +743,11 @@ ZEXTERN int ZEXPORT uncompress2 OF((Bytef *dest, uLongf *destLen, */ ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int windowBits, - int stream_size)); + const char *version, int stream_size)); #define inflateInit(strm) \ - inflateInit_((strm), sizeof(z_stream)) + inflateInit_((strm), ZLIB_VERSION, sizeof(z_stream)) #define inflateInit2(strm, windowBits) \ - inflateInit2_((strm), (windowBits), sizeof(z_stream)) + inflateInit2_((strm), (windowBits), ZLIB_VERSION, sizeof(z_stream)) #if !defined(ZUTIL_H) && !defined(NO_DUMMY_DECL) struct internal_state {int dummy;}; /* hack for buggy compilers */ diff --git a/lib/Kconfig b/lib/Kconfig index 189e6eb31aa..b3baa4b85b0 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -439,9 +439,6 @@ config TPM depends on DM imply DM_RNG select SHA1 - select SHA256 - select SHA384 - select SHA512 help This enables support for TPMs which can be used to provide security features for your board. The TPM can be connected via LPC or I2C @@ -449,6 +446,9 @@ config TPM command to interactive the TPM. Driver model support is provided for the low-level TPM interface, but only one TPM is supported at a time by the TPM library. + For size reasons only SHA1 is selected which is supported on TPM1.2. + If you want a fully functional TPM enable all hashing algorithms. + If you enabled measured boot all hashing algorithms are selected. config SPL_TPM bool "Trusted Platform Module (TPM) Support in SPL" diff --git a/lib/Makefile b/lib/Makefile index 2a76acf100d..e389ad014f8 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -61,6 +61,8 @@ ifeq ($(CONFIG_$(SPL_TPL_)TPM),y) obj-$(CONFIG_TPM) += tpm_api.o obj-$(CONFIG_TPM_V1) += tpm-v1.o obj-$(CONFIG_TPM_V2) += tpm-v2.o +obj-$(CONFIG_EFI_TCG2_PROTOCOL) += tpm_tcg2.o +obj-$(CONFIG_MEASURED_BOOT) += tpm_tcg2.o endif obj-$(CONFIG_$(SPL_TPL_)CRC8) += crc8.o diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index c16ead6a6ec..6dbfdb22dec 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -117,6 +117,7 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature) memcpy(header->oem_table_id, OEM_TABLE_ID, 8); header->oem_revision = OEM_REVISION; memcpy(header->creator_id, ASLC_ID, 4); + header->creator_revision = ASL_REVISION; } void acpi_align(struct acpi_ctx *ctx) @@ -219,7 +220,6 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, header->revision = acpi_get_table_revision(ACPITAB_DBG2); acpi_fill_header(header, "DBG2"); - header->creator_revision = ASL_REVISION; /* One debug device defined */ dbg2->devices_offset = sizeof(struct acpi_dbg2_header); diff --git a/lib/acpi/ssdt.c b/lib/acpi/ssdt.c index e032e266b3c..df1d739d117 100644 --- a/lib/acpi/ssdt.c +++ b/lib/acpi/ssdt.c @@ -23,7 +23,6 @@ int acpi_write_ssdt(struct acpi_ctx *ctx, const struct acpi_writer *entry) acpi_fill_header(ssdt, "SSDT"); ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT); - ssdt->creator_revision = 1; ssdt->length = sizeof(struct acpi_table_header); acpi_inc(ctx, sizeof(struct acpi_table_header)); diff --git a/lib/efi_loader/capsule_esl.dtsi.in b/lib/efi_loader/capsule_esl.dtsi.in index 61a9f2b25e9..bc7db836faa 100644 --- a/lib/efi_loader/capsule_esl.dtsi.in +++ b/lib/efi_loader/capsule_esl.dtsi.in @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ -/** +/* * Devicetree file with the public key EFI Signature List(ESL) * node. This file is used to generate the dtsi file to be * included into the DTB. -*/ + */ / { signature { capsule-key = /incbin/("ESL_BIN_FILE"); diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 51264c1b998..45f451ef6b6 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -16,7 +16,6 @@ #include <malloc.h> #include <smbios.h> #include <version_string.h> -#include <tpm-v2.h> #include <tpm_api.h> #include <u-boot/hash-checksum.h> #include <linux/unaligned/be_byteshift.h> @@ -254,8 +253,8 @@ efi_tcg2_get_capability(struct efi_tcg2_protocol *this, capability->protocol_version.major = 1; capability->protocol_version.minor = 1; - efi_ret = tcg2_platform_get_tpm2(&dev); - if (efi_ret != EFI_SUCCESS) { + ret = tcg2_platform_get_tpm2(&dev); + if (ret) { capability->supported_event_logs = 0; capability->hash_algorithm_bitmap = 0; capability->tpm_present_flag = false; @@ -277,7 +276,7 @@ efi_tcg2_get_capability(struct efi_tcg2_protocol *this, /* Supported and active PCRs */ capability->hash_algorithm_bitmap = 0; capability->active_pcr_banks = 0; - ret = tpm2_get_pcr_info(dev, &capability->hash_algorithm_bitmap, + ret = tcg2_get_pcr_info(dev, &capability->hash_algorithm_bitmap, &capability->active_pcr_banks, &capability->number_of_pcr_banks); if (ret) { @@ -350,8 +349,7 @@ efi_tcg2_get_eventlog(struct efi_tcg2_protocol *this, goto out; } - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) { + if (tcg2_platform_get_tpm2(&dev)) { event_log_location = NULL; event_log_last_entry = NULL; *event_log_truncated = false; @@ -386,7 +384,7 @@ static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size, void *new_efi = NULL; u8 hash[TPM2_SHA512_DIGEST_SIZE]; struct udevice *dev; - efi_status_t ret; + efi_status_t ret = EFI_SUCCESS; u32 active; int i; @@ -401,12 +399,13 @@ static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size, goto out; } - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + if (tcg2_platform_get_tpm2(&dev)) { + ret = EFI_DEVICE_ERROR; goto out; + } - ret = tcg2_get_active_pcr_banks(dev, &active); - if (ret != EFI_SUCCESS) { + if (tcg2_get_active_pcr_banks(dev, &active)) { + ret = EFI_DEVICE_ERROR; goto out; } @@ -470,12 +469,12 @@ efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size, IMAGE_DOS_HEADER *dos; IMAGE_NT_HEADERS32 *nt; struct efi_handler *handler; + int rc; if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + if (tcg2_platform_get_tpm2(&dev)) return EFI_SECURITY_VIOLATION; switch (handle->image_type) { @@ -499,9 +498,9 @@ efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size, if (ret != EFI_SUCCESS) return ret; - ret = tcg2_pcr_extend(dev, pcr_index, &digest_list); - if (ret != EFI_SUCCESS) - return ret; + rc = tcg2_pcr_extend(dev, pcr_index, &digest_list); + if (rc) + return EFI_DEVICE_ERROR; ret = efi_search_protocol(&handle->header, &efi_guid_loaded_image_device_path, &handler); @@ -571,9 +570,10 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, struct efi_tcg2_event *efi_tcg_event) { struct udevice *dev; - efi_status_t ret; + efi_status_t ret = EFI_SUCCESS; u32 event_type, pcr_index, event_size; struct tpml_digest_values digest_list; + int rc = 0; EFI_ENTRY("%p, %llu, %llu, %llu, %p", this, flags, data_to_hash, data_to_hash_len, efi_tcg_event); @@ -583,9 +583,10 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, goto out; } - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + if (tcg2_platform_get_tpm2(&dev)) { + ret = EFI_DEVICE_ERROR; goto out; + } if (efi_tcg_event->size < efi_tcg_event->header.header_size + sizeof(u32)) { @@ -618,8 +619,10 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, ret = tcg2_hash_pe_image((void *)(uintptr_t)data_to_hash, data_to_hash_len, &digest_list); } else { - ret = tcg2_create_digest(dev, (u8 *)(uintptr_t)data_to_hash, - data_to_hash_len, &digest_list); + rc = tcg2_create_digest(dev, (u8 *)(uintptr_t)data_to_hash, + data_to_hash_len, &digest_list); + if (rc) + ret = EFI_DEVICE_ERROR; } if (ret != EFI_SUCCESS) @@ -628,9 +631,11 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, pcr_index = efi_tcg_event->header.pcr_index; event_type = efi_tcg_event->header.event_type; - ret = tcg2_pcr_extend(dev, pcr_index, &digest_list); - if (ret != EFI_SUCCESS) + rc = tcg2_pcr_extend(dev, pcr_index, &digest_list); + if (rc) { + ret = EFI_DEVICE_ERROR; goto out; + } if (flags & EFI_TCG2_EXTEND_ONLY) { if (event_log.truncated) @@ -669,7 +674,7 @@ efi_tcg2_submit_command(struct efi_tcg2_protocol *this, u8 *output_param_block) { struct udevice *dev; - efi_status_t ret; + efi_status_t ret = EFI_SUCCESS; u32 rc; size_t resp_buf_size = output_param_block_size; @@ -681,9 +686,10 @@ efi_tcg2_submit_command(struct efi_tcg2_protocol *this, goto out; } - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + if (tcg2_platform_get_tpm2(&dev)) { + ret = EFI_DEVICE_ERROR; goto out; + } rc = tpm2_submit_command(dev, input_param_block, output_param_block, &resp_buf_size); @@ -711,19 +717,25 @@ efi_tcg2_get_active_pcr_banks(struct efi_tcg2_protocol *this, u32 *active_pcr_banks) { struct udevice *dev; - efi_status_t ret; + efi_status_t ret = EFI_INVALID_PARAMETER; EFI_ENTRY("%p, %p", this, active_pcr_banks); - if (!this || !active_pcr_banks) { - ret = EFI_INVALID_PARAMETER; + if (!this || !active_pcr_banks) goto out; - } - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + + if (tcg2_platform_get_tpm2(&dev)) + goto out; + + /* + * EFI_INVALID_PARAMETER does not convey the problem type. + * but that's what currently the spec specifies. + * EFI_DEVICE_ERROR would be better + */ + if (tcg2_get_active_pcr_banks(dev, active_pcr_banks)) goto out; - ret = tcg2_get_active_pcr_banks(dev, active_pcr_banks); + ret = EFI_SUCCESS; out: return EFI_EXIT(ret); @@ -849,14 +861,15 @@ static efi_status_t measure_event(struct udevice *dev, u32 pcr_index, u32 event_type, u32 size, u8 event[]) { struct tpml_digest_values digest_list; - efi_status_t ret; + efi_status_t ret = EFI_DEVICE_ERROR; + int rc; - ret = tcg2_create_digest(dev, event, size, &digest_list); - if (ret != EFI_SUCCESS) + rc = tcg2_create_digest(dev, event, size, &digest_list); + if (rc) goto out; - ret = tcg2_pcr_extend(dev, pcr_index, &digest_list); - if (ret != EFI_SUCCESS) + rc = tcg2_pcr_extend(dev, pcr_index, &digest_list); + if (rc) goto out; ret = tcg2_agile_log_append(pcr_index, event_type, &digest_list, @@ -898,10 +911,10 @@ static efi_status_t efi_init_event_log(void) struct tcg2_event_log elog; struct udevice *dev; efi_status_t ret; + int rc; - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) - return ret; + if (tcg2_platform_get_tpm2(&dev)) + return EFI_DEVICE_ERROR; ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, TPM2_EVENT_LOG_SIZE, (void **)&event_log.buffer); @@ -930,9 +943,11 @@ static efi_status_t efi_init_event_log(void) */ elog.log = event_log.buffer; elog.log_size = TPM2_EVENT_LOG_SIZE; - ret = tcg2_log_prepare_buffer(dev, &elog, false); - if (ret != EFI_SUCCESS) + rc = tcg2_log_prepare_buffer(dev, &elog, false); + if (rc) { + ret = (rc == -ENOBUFS) ? EFI_BUFFER_TOO_SMALL : EFI_DEVICE_ERROR; goto free_pool; + } event_log.pos = elog.log_position; @@ -1303,8 +1318,7 @@ efi_status_t efi_tcg2_measure_dtb(void *dtb) if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + if (tcg2_platform_get_tpm2(&dev)) return EFI_SECURITY_VIOLATION; rsvmap_size = size_of_rsvmap(dtb); @@ -1328,7 +1342,7 @@ efi_status_t efi_tcg2_measure_dtb(void *dtb) sha256_update(&hash_ctx, (u8 *)dtb + fdt_off_mem_rsvmap(dtb), rsvmap_size); sha256_finish(&hash_ctx, blob->data + blob->blob_description_size); - ret = measure_event(dev, 0, EV_POST_CODE, event_size, (u8 *)blob); + ret = measure_event(dev, 1, EV_POST_CODE, event_size, (u8 *)blob); free(blob); return ret; @@ -1353,8 +1367,7 @@ efi_status_t efi_tcg2_measure_efi_app_invocation(struct efi_loaded_image_obj *ha if (tcg2_efi_app_invoked) return EFI_SUCCESS; - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + if (tcg2_platform_get_tpm2(&dev)) return EFI_SECURITY_VIOLATION; ret = tcg2_measure_boot_variable(dev); @@ -1403,9 +1416,8 @@ efi_status_t efi_tcg2_measure_efi_app_exit(void) if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) - return ret; + if (tcg2_platform_get_tpm2(&dev)) + return EFI_SECURITY_VIOLATION; ret = measure_event(dev, 4, EV_EFI_ACTION, strlen(EFI_RETURNING_FROM_EFI_APPLICATION), @@ -1434,9 +1446,10 @@ efi_tcg2_notify_exit_boot_services(struct efi_event *event, void *context) goto out; } - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + if (tcg2_platform_get_tpm2(&dev)) { + ret = EFI_SECURITY_VIOLATION; goto out; + } ret = measure_event(dev, 5, EV_EFI_ACTION, strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION), @@ -1466,9 +1479,8 @@ efi_status_t efi_tcg2_notify_exit_boot_services_failed(void) if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) - goto out; + if (tcg2_platform_get_tpm2(&dev)) + return EFI_SECURITY_VIOLATION; ret = measure_event(dev, 5, EV_EFI_ACTION, strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION), @@ -1548,8 +1560,7 @@ efi_status_t efi_tcg2_do_initial_measurement(void) if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) + if (tcg2_platform_get_tpm2(&dev)) return EFI_SECURITY_VIOLATION; ret = tcg2_measure_secure_boot_variable(dev); @@ -1574,8 +1585,7 @@ efi_status_t efi_tcg2_register(void) struct efi_event *event; u32 err; - ret = tcg2_platform_get_tpm2(&dev); - if (ret != EFI_SUCCESS) { + if (tcg2_platform_get_tpm2(&dev)) { log_warning("Missing TPMv2 device for EFI_TCG_PROTOCOL\n"); return EFI_SUCCESS; } @@ -1583,6 +1593,7 @@ efi_status_t efi_tcg2_register(void) /* initialize the TPM as early as possible. */ err = tpm_auto_start(dev); if (err) { + ret = EFI_DEVICE_ERROR; log_err("TPM startup failed\n"); goto fail; } diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 1cc02acb3b2..09651d4675b 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -288,7 +288,6 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, /* check if a variable exists */ var = efi_var_mem_find(vendor, variable_name, NULL); append = !!(attributes & EFI_VARIABLE_APPEND_WRITE); - attributes &= ~EFI_VARIABLE_APPEND_WRITE; delete = !append && (!data_size || !attributes); /* check attributes */ @@ -304,7 +303,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, /* attributes won't be changed */ if (!delete && - ((ro_check && var->attr != attributes) || + ((ro_check && var->attr != (attributes & ~EFI_VARIABLE_APPEND_WRITE)) || (!ro_check && ((var->attr & ~EFI_VARIABLE_READ_ONLY) != (attributes & ~EFI_VARIABLE_READ_ONLY))))) { return EFI_INVALID_PARAMETER; @@ -378,7 +377,8 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, for (; *old_data; ++old_data) ; ++old_data; - ret = efi_var_mem_ins(variable_name, vendor, attributes, + ret = efi_var_mem_ins(variable_name, vendor, + attributes & ~EFI_VARIABLE_APPEND_WRITE, var->length, old_data, data_size, data, time); } else { diff --git a/lib/efi_selftest/efi_selftest_fdt.c b/lib/efi_selftest/efi_selftest_fdt.c index aa3b13ae3ab..a4b0cef20e4 100644 --- a/lib/efi_selftest/efi_selftest_fdt.c +++ b/lib/efi_selftest/efi_selftest_fdt.c @@ -227,6 +227,13 @@ static int execute(void) return EFI_ST_FAILURE; } } + if (IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB)) { + str = get_property(u"kaslr-seed", u"chosen"); + if (str) { + efi_st_error("kaslr-seed with measured fdt\n"); + return EFI_ST_FAILURE; + } + } if (IS_ENABLED(CONFIG_RISCV)) { u32 fdt_hartid; diff --git a/lib/gzip.c b/lib/gzip.c index a9a3df524de..5d9c19598d5 100644 --- a/lib/gzip.c +++ b/lib/gzip.c @@ -67,7 +67,7 @@ int zzip(void *dst, unsigned long *lenp, unsigned char *src, r = deflateInit2_(&s, Z_BEST_SPEED, Z_DEFLATED, window, DEF_MEM_LEVEL, Z_DEFAULT_STRATEGY, - sizeof(z_stream)); + ZLIB_VERSION, sizeof(z_stream)); if (r != Z_OK) { printf ("Error: deflateInit2_() returned %d\n", r); return -1; diff --git a/lib/smbios.c b/lib/smbios.c index a822acd48e9..fb6eaf1d5ca 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -383,8 +383,12 @@ static int smbios_write_type1(ulong *current, int handle, memset(t, 0, sizeof(struct smbios_type1)); fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); - t->manufacturer = smbios_add_prop(ctx, "manufacturer", NULL); - t->product_name = smbios_add_prop(ctx, "product", NULL); + t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", + SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER, + NULL); + t->product_name = smbios_add_prop_si(ctx, "product", + SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT, + NULL); t->version = smbios_add_prop_si(ctx, "version", SYSINFO_ID_SMBIOS_SYSTEM_VERSION, NULL); @@ -392,11 +396,15 @@ static int smbios_write_type1(ulong *current, int handle, t->serial_number = smbios_add_prop(ctx, NULL, serial_str); strncpy((char *)t->uuid, serial_str, sizeof(t->uuid)); } else { - t->serial_number = smbios_add_prop(ctx, "serial", NULL); + t->serial_number = smbios_add_prop_si(ctx, "serial", + SYSINFO_ID_SMBIOS_SYSTEM_SERIAL, + NULL); } t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN; - t->sku_number = smbios_add_prop(ctx, "sku", NULL); - t->family = smbios_add_prop(ctx, "family", NULL); + t->sku_number = smbios_add_prop_si(ctx, "sku", + SYSINFO_ID_SMBIOS_SYSTEM_SKU, NULL); + t->family = smbios_add_prop_si(ctx, "family", + SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, NULL); len = t->length + smbios_string_table_len(ctx); *current += len; @@ -415,12 +423,22 @@ static int smbios_write_type2(ulong *current, int handle, memset(t, 0, sizeof(struct smbios_type2)); fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); - t->manufacturer = smbios_add_prop(ctx, "manufacturer", NULL); - t->product_name = smbios_add_prop(ctx, "product", NULL); + t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", + SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER, + NULL); + t->product_name = smbios_add_prop_si(ctx, "product", + SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT, + NULL); t->version = smbios_add_prop_si(ctx, "version", SYSINFO_ID_SMBIOS_BASEBOARD_VERSION, NULL); - t->asset_tag_number = smbios_add_prop(ctx, "asset-tag", NULL); + + t->serial_number = smbios_add_prop_si(ctx, "serial", + SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL, + NULL); + t->asset_tag_number = smbios_add_prop_si(ctx, "asset-tag", + SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG, + NULL); t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING; t->board_type = SMBIOS_BOARD_MOTHERBOARD; t->chassis_handle = handle + 1; @@ -573,8 +591,14 @@ ulong write_smbios_table(ulong addr) ctx.node = ofnode_null(); if (IS_ENABLED(CONFIG_OF_CONTROL) && CONFIG_IS_ENABLED(SYSINFO)) { uclass_first_device(UCLASS_SYSINFO, &ctx.dev); - if (ctx.dev) + if (ctx.dev) { + int ret; + parent_node = dev_read_subnode(ctx.dev, "smbios"); + ret = sysinfo_detect(ctx.dev); + if (ret) + return ret; + } } else { ctx.dev = NULL; } diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c index a67daed2f3c..59e6cbafafa 100644 --- a/lib/tpm-v2.c +++ b/lib/tpm-v2.c @@ -10,6 +10,7 @@ #include <tpm_api.h> #include <tpm-common.h> #include <tpm-v2.h> +#include <tpm_tcg2.h> #include <u-boot/sha1.h> #include <u-boot/sha256.h> #include <u-boot/sha512.h> @@ -22,668 +23,6 @@ #include "tpm-utils.h" -int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks) -{ - u32 supported = 0; - u32 pcr_banks = 0; - u32 active = 0; - int rc; - - rc = tpm2_get_pcr_info(dev, &supported, &active, &pcr_banks); - if (rc) - return rc; - - *active_pcr_banks = active; - - return 0; -} - -u32 tcg2_event_get_size(struct tpml_digest_values *digest_list) -{ - u32 len; - size_t i; - - len = offsetof(struct tcg_pcr_event2, digests); - len += offsetof(struct tpml_digest_values, digests); - for (i = 0; i < digest_list->count; ++i) { - u16 l = tpm2_algorithm_to_len(digest_list->digests[i].hash_alg); - - if (!l) - continue; - - len += l + offsetof(struct tpmt_ha, digest); - } - len += sizeof(u32); - - return len; -} - -int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, - struct tpml_digest_values *digest_list) -{ - u8 final[sizeof(union tpmu_ha)]; - sha256_context ctx_256; - sha512_context ctx_512; - sha1_context ctx; - u32 active; - size_t i; - u32 len; - int rc; - - rc = tcg2_get_active_pcr_banks(dev, &active); - if (rc) - return rc; - - digest_list->count = 0; - for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { - if (!(active & hash_algo_list[i].hash_mask)) - continue; - - switch (hash_algo_list[i].hash_alg) { - case TPM2_ALG_SHA1: - sha1_starts(&ctx); - sha1_update(&ctx, input, length); - sha1_finish(&ctx, final); - len = TPM2_SHA1_DIGEST_SIZE; - break; - case TPM2_ALG_SHA256: - sha256_starts(&ctx_256); - sha256_update(&ctx_256, input, length); - sha256_finish(&ctx_256, final); - len = TPM2_SHA256_DIGEST_SIZE; - break; - case TPM2_ALG_SHA384: - sha384_starts(&ctx_512); - sha384_update(&ctx_512, input, length); - sha384_finish(&ctx_512, final); - len = TPM2_SHA384_DIGEST_SIZE; - break; - case TPM2_ALG_SHA512: - sha512_starts(&ctx_512); - sha512_update(&ctx_512, input, length); - sha512_finish(&ctx_512, final); - len = TPM2_SHA512_DIGEST_SIZE; - break; - default: - printf("%s: unsupported algorithm %x\n", __func__, - hash_algo_list[i].hash_alg); - continue; - } - - digest_list->digests[digest_list->count].hash_alg = - hash_algo_list[i].hash_alg; - memcpy(&digest_list->digests[digest_list->count].digest, final, - len); - digest_list->count++; - } - - return 0; -} - -void tcg2_log_append(u32 pcr_index, u32 event_type, - struct tpml_digest_values *digest_list, u32 size, - const u8 *event, u8 *log) -{ - size_t len; - size_t pos; - u32 i; - - pos = offsetof(struct tcg_pcr_event2, pcr_index); - put_unaligned_le32(pcr_index, log); - pos = offsetof(struct tcg_pcr_event2, event_type); - put_unaligned_le32(event_type, log + pos); - pos = offsetof(struct tcg_pcr_event2, digests) + - offsetof(struct tpml_digest_values, count); - put_unaligned_le32(digest_list->count, log + pos); - - pos = offsetof(struct tcg_pcr_event2, digests) + - offsetof(struct tpml_digest_values, digests); - for (i = 0; i < digest_list->count; ++i) { - u16 hash_alg = digest_list->digests[i].hash_alg; - - len = tpm2_algorithm_to_len(hash_alg); - if (!len) - continue; - - pos += offsetof(struct tpmt_ha, hash_alg); - put_unaligned_le16(hash_alg, log + pos); - pos += offsetof(struct tpmt_ha, digest); - memcpy(log + pos, (u8 *)&digest_list->digests[i].digest, len); - pos += len; - } - - put_unaligned_le32(size, log + pos); - pos += sizeof(u32); - memcpy(log + pos, event, size); -} - -static int tcg2_log_append_check(struct tcg2_event_log *elog, u32 pcr_index, - u32 event_type, - struct tpml_digest_values *digest_list, - u32 size, const u8 *event) -{ - u32 event_size; - u8 *log; - - event_size = size + tcg2_event_get_size(digest_list); - if (elog->log_position + event_size > elog->log_size) { - printf("%s: log too large: %u + %u > %u\n", __func__, - elog->log_position, event_size, elog->log_size); - return -ENOBUFS; - } - - log = elog->log + elog->log_position; - elog->log_position += event_size; - - tcg2_log_append(pcr_index, event_type, digest_list, size, event, log); - - return 0; -} - -static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog) -{ - struct tcg_efi_spec_id_event *ev; - struct tcg_pcr_event *log; - u32 event_size; - u32 count = 0; - u32 log_size; - u32 active; - size_t i; - u16 len; - int rc; - - rc = tcg2_get_active_pcr_banks(dev, &active); - if (rc) - return rc; - - event_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes); - for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { - if (!(active & hash_algo_list[i].hash_mask)) - continue; - - switch (hash_algo_list[i].hash_alg) { - case TPM2_ALG_SHA1: - case TPM2_ALG_SHA256: - case TPM2_ALG_SHA384: - case TPM2_ALG_SHA512: - count++; - break; - default: - continue; - } - } - - event_size += 1 + - (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count); - log_size = offsetof(struct tcg_pcr_event, event) + event_size; - - if (log_size > elog->log_size) { - printf("%s: log too large: %u > %u\n", __func__, log_size, - elog->log_size); - return -ENOBUFS; - } - - log = (struct tcg_pcr_event *)elog->log; - put_unaligned_le32(0, &log->pcr_index); - put_unaligned_le32(EV_NO_ACTION, &log->event_type); - memset(&log->digest, 0, sizeof(log->digest)); - put_unaligned_le32(event_size, &log->event_size); - - ev = (struct tcg_efi_spec_id_event *)log->event; - strlcpy((char *)ev->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03, - sizeof(ev->signature)); - put_unaligned_le32(0, &ev->platform_class); - ev->spec_version_minor = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2; - ev->spec_version_major = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2; - ev->spec_errata = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2; - ev->uintn_size = sizeof(size_t) / sizeof(u32); - put_unaligned_le32(count, &ev->number_of_algorithms); - - count = 0; - for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { - if (!(active & hash_algo_list[i].hash_mask)) - continue; - - len = hash_algo_list[i].hash_len; - if (!len) - continue; - - put_unaligned_le16(hash_algo_list[i].hash_alg, - &ev->digest_sizes[count].algorithm_id); - put_unaligned_le16(len, &ev->digest_sizes[count].digest_size); - count++; - } - - *((u8 *)ev + (event_size - 1)) = 0; - elog->log_position = log_size; - - return 0; -} - -static int tcg2_replay_eventlog(struct tcg2_event_log *elog, - struct udevice *dev, - struct tpml_digest_values *digest_list, - u32 log_position) -{ - const u32 offset = offsetof(struct tcg_pcr_event2, digests) + - offsetof(struct tpml_digest_values, digests); - u32 event_size; - u32 count; - u16 algo; - u32 pcr; - u32 pos; - u16 len; - u8 *log; - int rc; - u32 i; - - while (log_position + offset < elog->log_size) { - log = elog->log + log_position; - - pos = offsetof(struct tcg_pcr_event2, pcr_index); - pcr = get_unaligned_le32(log + pos); - pos = offsetof(struct tcg_pcr_event2, event_type); - if (!get_unaligned_le32(log + pos)) - return 0; - - pos = offsetof(struct tcg_pcr_event2, digests) + - offsetof(struct tpml_digest_values, count); - count = get_unaligned_le32(log + pos); - if (count > ARRAY_SIZE(hash_algo_list) || - (digest_list->count && digest_list->count != count)) - return 0; - - pos = offsetof(struct tcg_pcr_event2, digests) + - offsetof(struct tpml_digest_values, digests); - for (i = 0; i < count; ++i) { - pos += offsetof(struct tpmt_ha, hash_alg); - if (log_position + pos + sizeof(u16) >= elog->log_size) - return 0; - - algo = get_unaligned_le16(log + pos); - pos += offsetof(struct tpmt_ha, digest); - switch (algo) { - case TPM2_ALG_SHA1: - case TPM2_ALG_SHA256: - case TPM2_ALG_SHA384: - case TPM2_ALG_SHA512: - len = tpm2_algorithm_to_len(algo); - break; - default: - return 0; - } - - if (digest_list->count) { - if (algo != digest_list->digests[i].hash_alg || - log_position + pos + len >= elog->log_size) - return 0; - - memcpy(digest_list->digests[i].digest.sha512, - log + pos, len); - } - - pos += len; - } - - if (log_position + pos + sizeof(u32) >= elog->log_size) - return 0; - - event_size = get_unaligned_le32(log + pos); - pos += event_size + sizeof(u32); - if (log_position + pos > elog->log_size) - return 0; - - if (digest_list->count) { - rc = tcg2_pcr_extend(dev, pcr, digest_list); - if (rc) - return rc; - } - - log_position += pos; - } - - elog->log_position = log_position; - elog->found = true; - return 0; -} - -static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) -{ - struct tpml_digest_values digest_list; - struct tcg_efi_spec_id_event *event; - struct tcg_pcr_event *log; - u32 log_active; - u32 calc_size; - u32 active; - u32 count; - u32 evsz; - u32 mask; - u16 algo; - u16 len; - int rc; - u32 i; - u16 j; - - if (elog->log_size <= offsetof(struct tcg_pcr_event, event)) - return 0; - - log = (struct tcg_pcr_event *)elog->log; - if (get_unaligned_le32(&log->pcr_index) != 0 || - get_unaligned_le32(&log->event_type) != EV_NO_ACTION) - return 0; - - for (i = 0; i < sizeof(log->digest); i++) { - if (log->digest[i]) - return 0; - } - - evsz = get_unaligned_le32(&log->event_size); - if (evsz < offsetof(struct tcg_efi_spec_id_event, digest_sizes) || - evsz + offsetof(struct tcg_pcr_event, event) > elog->log_size) - return 0; - - event = (struct tcg_efi_spec_id_event *)log->event; - if (memcmp(event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03, - sizeof(TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03))) - return 0; - - if (event->spec_version_minor != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 || - event->spec_version_major != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2) - return 0; - - count = get_unaligned_le32(&event->number_of_algorithms); - if (count > ARRAY_SIZE(hash_algo_list)) - return 0; - - calc_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes) + - (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count) + - 1; - if (evsz != calc_size) - return 0; - - rc = tcg2_get_active_pcr_banks(dev, &active); - if (rc) - return rc; - - digest_list.count = 0; - log_active = 0; - - for (i = 0; i < count; ++i) { - algo = get_unaligned_le16(&event->digest_sizes[i].algorithm_id); - mask = tpm2_algorithm_to_mask(algo); - - if (!(active & mask)) - return 0; - - switch (algo) { - case TPM2_ALG_SHA1: - case TPM2_ALG_SHA256: - case TPM2_ALG_SHA384: - case TPM2_ALG_SHA512: - len = get_unaligned_le16(&event->digest_sizes[i].digest_size); - if (tpm2_algorithm_to_len(algo) != len) - return 0; - digest_list.digests[digest_list.count++].hash_alg = algo; - break; - default: - return 0; - } - - log_active |= mask; - } - - /* Ensure the previous firmware extended all the PCRs. */ - if (log_active != active) - return 0; - - /* Read PCR0 to check if previous firmware extended the PCRs or not. */ - rc = tcg2_pcr_read(dev, 0, &digest_list); - if (rc) - return rc; - - for (i = 0; i < digest_list.count; ++i) { - len = tpm2_algorithm_to_len(digest_list.digests[i].hash_alg); - for (j = 0; j < len; ++j) { - if (digest_list.digests[i].digest.sha512[j]) - break; - } - - /* PCR is non-zero; it has been extended, so skip extending. */ - if (j != len) { - digest_list.count = 0; - break; - } - } - - return tcg2_replay_eventlog(elog, dev, &digest_list, - offsetof(struct tcg_pcr_event, event) + - evsz); -} - -int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index, - struct tpml_digest_values *digest_list) -{ - u32 rc; - u32 i; - - for (i = 0; i < digest_list->count; i++) { - u32 alg = digest_list->digests[i].hash_alg; - - rc = tpm2_pcr_extend(dev, pcr_index, alg, - (u8 *)&digest_list->digests[i].digest, - tpm2_algorithm_to_len(alg)); - if (rc) { - printf("%s: error pcr:%u alg:%08x\n", __func__, - pcr_index, alg); - return rc; - } - } - - return 0; -} - -int tcg2_pcr_read(struct udevice *dev, u32 pcr_index, - struct tpml_digest_values *digest_list) -{ - struct tpm_chip_priv *priv; - u32 rc; - u32 i; - - priv = dev_get_uclass_priv(dev); - if (!priv) - return -ENODEV; - - for (i = 0; i < digest_list->count; i++) { - u32 alg = digest_list->digests[i].hash_alg; - u8 *digest = (u8 *)&digest_list->digests[i].digest; - - rc = tpm2_pcr_read(dev, pcr_index, priv->pcr_select_min, alg, - digest, tpm2_algorithm_to_len(alg), NULL); - if (rc) { - printf("%s: error pcr:%u alg:%08x\n", __func__, - pcr_index, alg); - return rc; - } - } - - return 0; -} - -int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog, - u32 pcr_index, u32 size, const u8 *data, u32 event_type, - u32 event_size, const u8 *event) -{ - struct tpml_digest_values digest_list; - int rc; - - if (data) - rc = tcg2_create_digest(dev, data, size, &digest_list); - else - rc = tcg2_create_digest(dev, event, event_size, &digest_list); - if (rc) - return rc; - - rc = tcg2_pcr_extend(dev, pcr_index, &digest_list); - if (rc) - return rc; - - return tcg2_log_append_check(elog, pcr_index, event_type, &digest_list, - event_size, event); -} - -int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, - bool ignore_existing_log) -{ - struct tcg2_event_log log; - int rc; - - elog->log_position = 0; - elog->found = false; - - rc = tcg2_platform_get_log(dev, (void **)&log.log, &log.log_size); - if (!rc) { - log.log_position = 0; - log.found = false; - - if (!ignore_existing_log) { - rc = tcg2_log_parse(dev, &log); - if (rc) - return rc; - } - - if (elog->log_size) { - if (log.found) { - if (elog->log_size < log.log_position) - return -ENOSPC; - - /* - * Copy the discovered log into the user buffer - * if there's enough space. - */ - memcpy(elog->log, log.log, log.log_position); - } - - unmap_physmem(log.log, MAP_NOCACHE); - } else { - elog->log = log.log; - elog->log_size = log.log_size; - } - - elog->log_position = log.log_position; - elog->found = log.found; - } - - /* - * Initialize the log buffer if no log was discovered and the buffer is - * valid. User's can pass in their own buffer as a fallback if no - * memory region is found. - */ - if (!elog->found && elog->log_size) - rc = tcg2_log_init(dev, elog); - - return rc; -} - -int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog, - bool ignore_existing_log) -{ - int rc; - - rc = tcg2_platform_get_tpm2(dev); - if (rc) - return rc; - - rc = tpm_auto_start(*dev); - if (rc) - return rc; - - rc = tcg2_log_prepare_buffer(*dev, elog, ignore_existing_log); - if (rc) { - tcg2_measurement_term(*dev, elog, true); - return rc; - } - - rc = tcg2_measure_event(*dev, elog, 0, EV_S_CRTM_VERSION, - strlen(version_string) + 1, - (u8 *)version_string); - if (rc) { - tcg2_measurement_term(*dev, elog, true); - return rc; - } - - return 0; -} - -void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, - bool error) -{ - u32 event = error ? 0x1 : 0xffffffff; - int i; - - for (i = 0; i < 8; ++i) - tcg2_measure_event(dev, elog, i, EV_SEPARATOR, sizeof(event), - (const u8 *)&event); - - if (elog->log) - unmap_physmem(elog->log, MAP_NOCACHE); -} - -__weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size) -{ - const __be32 *addr_prop; - const __be32 *size_prop; - int asize; - int ssize; - - *addr = NULL; - *size = 0; - - addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize); - if (!addr_prop) - addr_prop = dev_read_prop(dev, "linux,sml-base", &asize); - - size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize); - if (!size_prop) - size_prop = dev_read_prop(dev, "linux,sml-size", &ssize); - - if (addr_prop && size_prop) { - u64 a = of_read_number(addr_prop, asize / sizeof(__be32)); - u64 s = of_read_number(size_prop, ssize / sizeof(__be32)); - - *addr = map_physmem(a, s, MAP_NOCACHE); - *size = (u32)s; - } else { - struct ofnode_phandle_args args; - phys_addr_t a; - fdt_size_t s; - - if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0, - 0, &args)) - return -ENODEV; - - a = ofnode_get_addr_size(args.node, "reg", &s); - if (a == FDT_ADDR_T_NONE) - return -ENOMEM; - - *addr = map_physmem(a, s, MAP_NOCACHE); - *size = (u32)s; - } - - return 0; -} - -__weak int tcg2_platform_get_tpm2(struct udevice **dev) -{ - for_each_tpm_device(*dev) { - if (tpm_get_version(*dev) == TPM_V2) - return 0; - } - - return -ENODEV; -} - -__weak void tcg2_platform_startup_error(struct udevice *dev, int rc) {} - u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode) { const u8 command_v2[12] = { @@ -857,6 +196,11 @@ u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm, if (!digest) return -EINVAL; + + if (!tpm2_allow_extend(dev)) { + log_err("Cannot extend PCRs if all the TPM enabled algorithms are not supported\n"); + return -EINVAL; + } /* * Fill the command structure starting from the first buffer: * - the digest @@ -1056,48 +400,25 @@ static int tpm2_get_num_pcr(struct udevice *dev, u32 *num_pcr) return 0; } -static bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection) -{ - int i; - - /* - * check the pcr_select. If at least one of the PCRs supports the - * algorithm add it on the active ones - */ - for (i = 0; i < selection->size_of_select; i++) { - if (selection->pcr_select[i]) - return true; - } - - return false; -} - -int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, - u32 *pcr_banks) +int tpm2_get_pcr_info(struct udevice *dev, struct tpml_pcr_selection *pcrs) { u8 response[(sizeof(struct tpms_capability_data) - offsetof(struct tpms_capability_data, data))]; - struct tpml_pcr_selection pcrs; u32 num_pcr; size_t i; u32 ret; - *supported_pcr = 0; - *active_pcr = 0; - *pcr_banks = 0; - memset(response, 0, sizeof(response)); ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1); if (ret) return ret; - pcrs.count = get_unaligned_be32(response); + pcrs->count = get_unaligned_be32(response); /* - * We only support 5 algorithms for now so check against that + * We only support 4 algorithms for now so check against that * instead of TPM2_NUM_PCR_BANKS */ - if (pcrs.count > ARRAY_SIZE(hash_algo_list) || - pcrs.count < 1) { - printf("%s: too many pcrs: %u\n", __func__, pcrs.count); + if (pcrs->count > 4 || pcrs->count < 1) { + printf("%s: too many pcrs: %u\n", __func__, pcrs->count); return -EMSGSIZE; } @@ -1105,7 +426,7 @@ int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, if (ret) return ret; - for (i = 0; i < pcrs.count; i++) { + for (i = 0; i < pcrs->count; i++) { /* * Definition of TPMS_PCR_SELECTION Structure * hash: u16 @@ -1125,35 +446,20 @@ int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, hash_offset + offsetof(struct tpms_pcr_selection, pcr_select); - pcrs.selection[i].hash = + pcrs->selection[i].hash = get_unaligned_be16(response + hash_offset); - pcrs.selection[i].size_of_select = + pcrs->selection[i].size_of_select = __get_unaligned_be(response + size_select_offset); - if (pcrs.selection[i].size_of_select > TPM2_PCR_SELECT_MAX) { + if (pcrs->selection[i].size_of_select > TPM2_PCR_SELECT_MAX) { printf("%s: pcrs selection too large: %u\n", __func__, - pcrs.selection[i].size_of_select); + pcrs->selection[i].size_of_select); return -ENOBUFS; } /* copy the array of pcr_select */ - memcpy(pcrs.selection[i].pcr_select, response + pcr_select_offset, - pcrs.selection[i].size_of_select); + memcpy(pcrs->selection[i].pcr_select, response + pcr_select_offset, + pcrs->selection[i].size_of_select); } - for (i = 0; i < pcrs.count; i++) { - u32 hash_mask = tpm2_algorithm_to_mask(pcrs.selection[i].hash); - - if (hash_mask) { - *supported_pcr |= hash_mask; - if (tpm2_is_active_pcr(&pcrs.selection[i])) - *active_pcr |= hash_mask; - } else { - printf("%s: unknown algorithm %x\n", __func__, - pcrs.selection[i].hash); - } - } - - *pcr_banks = pcrs.count; - return 0; } @@ -1541,6 +847,18 @@ u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd, return 0; } +bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection) +{ + int i; + + for (i = 0; i < selection->size_of_select; i++) { + if (selection->pcr_select[i]) + return true; + } + + return false; +} + enum tpm2_algorithms tpm2_name_to_algorithm(const char *name) { size_t i; @@ -1566,14 +884,33 @@ const char *tpm2_algorithm_name(enum tpm2_algorithms algo) return ""; } -u32 tpm2_algorithm_to_mask(enum tpm2_algorithms algo) +u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo) { size_t i; - for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) { + for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { if (hash_algo_list[i].hash_alg == algo) - return hash_algo_list[i].hash_mask; + return hash_algo_list[i].hash_len; } return 0; } + +bool tpm2_allow_extend(struct udevice *dev) +{ + struct tpml_pcr_selection pcrs; + size_t i; + int rc; + + rc = tpm2_get_pcr_info(dev, &pcrs); + if (rc) + return false; + + for (i = 0; i < pcrs.count; i++) { + if (tpm2_is_active_pcr(&pcrs.selection[i]) && + !tpm2_algorithm_to_len(pcrs.selection[i].hash)) + return false; + } + + return true; +} diff --git a/lib/tpm_tcg2.c b/lib/tpm_tcg2.c new file mode 100644 index 00000000000..7f868cc8837 --- /dev/null +++ b/lib/tpm_tcg2.c @@ -0,0 +1,731 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Linaro Limited + */ + +#include <dm.h> +#include <dm/of_access.h> +#include <tpm_api.h> +#include <tpm-common.h> +#include <tpm-v2.h> +#include <tpm_tcg2.h> +#include <u-boot/sha1.h> +#include <u-boot/sha256.h> +#include <u-boot/sha512.h> +#include <version_string.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> +#include <linux/unaligned/le_byteshift.h> +#include "tpm-utils.h" + +int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, + u32 *pcr_banks) +{ + u8 response[(sizeof(struct tpms_capability_data) - + offsetof(struct tpms_capability_data, data))]; + struct tpml_pcr_selection pcrs; + size_t i; + u32 ret; + + *supported_pcr = 0; + *active_pcr = 0; + *pcr_banks = 0; + memset(response, 0, sizeof(response)); + + ret = tpm2_get_pcr_info(dev, &pcrs); + if (ret) + return ret; + + for (i = 0; i < pcrs.count; i++) { + u32 hash_mask = tcg2_algorithm_to_mask(pcrs.selection[i].hash); + + if (hash_mask) { + *supported_pcr |= hash_mask; + if (tpm2_is_active_pcr(&pcrs.selection[i])) + *active_pcr |= hash_mask; + } else { + printf("%s: unknown algorithm %x\n", __func__, + pcrs.selection[i].hash); + } + } + + *pcr_banks = pcrs.count; + + return 0; +} + +int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks) +{ + u32 supported = 0; + u32 pcr_banks = 0; + u32 active = 0; + int rc; + + rc = tcg2_get_pcr_info(dev, &supported, &active, &pcr_banks); + if (rc) + return rc; + + *active_pcr_banks = active; + + return 0; +} + +u32 tcg2_event_get_size(struct tpml_digest_values *digest_list) +{ + u32 len; + size_t i; + + len = offsetof(struct tcg_pcr_event2, digests); + len += offsetof(struct tpml_digest_values, digests); + for (i = 0; i < digest_list->count; ++i) { + u16 l = tpm2_algorithm_to_len(digest_list->digests[i].hash_alg); + + if (!l) + continue; + + len += l + offsetof(struct tpmt_ha, digest); + } + len += sizeof(u32); + + return len; +} + +int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, + struct tpml_digest_values *digest_list) +{ + u8 final[sizeof(union tpmu_ha)]; + sha256_context ctx_256; + sha512_context ctx_512; + sha1_context ctx; + u32 active; + size_t i; + u32 len; + int rc; + + rc = tcg2_get_active_pcr_banks(dev, &active); + if (rc) + return rc; + + digest_list->count = 0; + for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { + if (!(active & hash_algo_list[i].hash_mask)) + continue; + + switch (hash_algo_list[i].hash_alg) { + case TPM2_ALG_SHA1: + sha1_starts(&ctx); + sha1_update(&ctx, input, length); + sha1_finish(&ctx, final); + len = TPM2_SHA1_DIGEST_SIZE; + break; + case TPM2_ALG_SHA256: + sha256_starts(&ctx_256); + sha256_update(&ctx_256, input, length); + sha256_finish(&ctx_256, final); + len = TPM2_SHA256_DIGEST_SIZE; + break; + case TPM2_ALG_SHA384: + sha384_starts(&ctx_512); + sha384_update(&ctx_512, input, length); + sha384_finish(&ctx_512, final); + len = TPM2_SHA384_DIGEST_SIZE; + break; + case TPM2_ALG_SHA512: + sha512_starts(&ctx_512); + sha512_update(&ctx_512, input, length); + sha512_finish(&ctx_512, final); + len = TPM2_SHA512_DIGEST_SIZE; + break; + default: + printf("%s: unsupported algorithm %x\n", __func__, + hash_algo_list[i].hash_alg); + continue; + } + + digest_list->digests[digest_list->count].hash_alg = + hash_algo_list[i].hash_alg; + memcpy(&digest_list->digests[digest_list->count].digest, final, + len); + digest_list->count++; + } + + return 0; +} + +void tcg2_log_append(u32 pcr_index, u32 event_type, + struct tpml_digest_values *digest_list, u32 size, + const u8 *event, u8 *log) +{ + size_t len; + size_t pos; + u32 i; + + pos = offsetof(struct tcg_pcr_event2, pcr_index); + put_unaligned_le32(pcr_index, log); + pos = offsetof(struct tcg_pcr_event2, event_type); + put_unaligned_le32(event_type, log + pos); + pos = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, count); + put_unaligned_le32(digest_list->count, log + pos); + + pos = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, digests); + for (i = 0; i < digest_list->count; ++i) { + u16 hash_alg = digest_list->digests[i].hash_alg; + + len = tpm2_algorithm_to_len(hash_alg); + if (!len) + continue; + + pos += offsetof(struct tpmt_ha, hash_alg); + put_unaligned_le16(hash_alg, log + pos); + pos += offsetof(struct tpmt_ha, digest); + memcpy(log + pos, (u8 *)&digest_list->digests[i].digest, len); + pos += len; + } + + put_unaligned_le32(size, log + pos); + pos += sizeof(u32); + memcpy(log + pos, event, size); +} + +static int tcg2_log_append_check(struct tcg2_event_log *elog, u32 pcr_index, + u32 event_type, + struct tpml_digest_values *digest_list, + u32 size, const u8 *event) +{ + u32 event_size; + u8 *log; + + event_size = size + tcg2_event_get_size(digest_list); + if (elog->log_position + event_size > elog->log_size) { + printf("%s: log too large: %u + %u > %u\n", __func__, + elog->log_position, event_size, elog->log_size); + return -ENOBUFS; + } + + log = elog->log + elog->log_position; + elog->log_position += event_size; + + tcg2_log_append(pcr_index, event_type, digest_list, size, event, log); + + return 0; +} + +static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog) +{ + struct tcg_efi_spec_id_event *ev; + struct tcg_pcr_event *log; + u32 event_size; + u32 count = 0; + u32 log_size; + u32 active; + size_t i; + u16 len; + int rc; + + rc = tcg2_get_active_pcr_banks(dev, &active); + if (rc) + return rc; + + event_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes); + for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { + if (!(active & hash_algo_list[i].hash_mask)) + continue; + + switch (hash_algo_list[i].hash_alg) { + case TPM2_ALG_SHA1: + case TPM2_ALG_SHA256: + case TPM2_ALG_SHA384: + case TPM2_ALG_SHA512: + count++; + break; + default: + continue; + } + } + + event_size += 1 + + (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count); + log_size = offsetof(struct tcg_pcr_event, event) + event_size; + + if (log_size > elog->log_size) { + printf("%s: log too large: %u > %u\n", __func__, log_size, + elog->log_size); + return -ENOBUFS; + } + + log = (struct tcg_pcr_event *)elog->log; + put_unaligned_le32(0, &log->pcr_index); + put_unaligned_le32(EV_NO_ACTION, &log->event_type); + memset(&log->digest, 0, sizeof(log->digest)); + put_unaligned_le32(event_size, &log->event_size); + + ev = (struct tcg_efi_spec_id_event *)log->event; + strlcpy((char *)ev->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03, + sizeof(ev->signature)); + put_unaligned_le32(0, &ev->platform_class); + ev->spec_version_minor = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2; + ev->spec_version_major = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2; + ev->spec_errata = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2; + ev->uintn_size = sizeof(size_t) / sizeof(u32); + put_unaligned_le32(count, &ev->number_of_algorithms); + + count = 0; + for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) { + if (!(active & hash_algo_list[i].hash_mask)) + continue; + + len = hash_algo_list[i].hash_len; + if (!len) + continue; + + put_unaligned_le16(hash_algo_list[i].hash_alg, + &ev->digest_sizes[count].algorithm_id); + put_unaligned_le16(len, &ev->digest_sizes[count].digest_size); + count++; + } + + *((u8 *)ev + (event_size - 1)) = 0; + elog->log_position = log_size; + + return 0; +} + +static int tcg2_replay_eventlog(struct tcg2_event_log *elog, + struct udevice *dev, + struct tpml_digest_values *digest_list, + u32 log_position) +{ + const u32 offset = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, digests); + u32 event_size; + u32 count; + u16 algo; + u32 pcr; + u32 pos; + u16 len; + u8 *log; + int rc; + u32 i; + + while (log_position + offset < elog->log_size) { + log = elog->log + log_position; + + pos = offsetof(struct tcg_pcr_event2, pcr_index); + pcr = get_unaligned_le32(log + pos); + pos = offsetof(struct tcg_pcr_event2, event_type); + if (!get_unaligned_le32(log + pos)) + return 0; + + pos = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, count); + count = get_unaligned_le32(log + pos); + if (count > ARRAY_SIZE(hash_algo_list) || + (digest_list->count && digest_list->count != count)) + return 0; + + pos = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, digests); + for (i = 0; i < count; ++i) { + pos += offsetof(struct tpmt_ha, hash_alg); + if (log_position + pos + sizeof(u16) >= elog->log_size) + return 0; + + algo = get_unaligned_le16(log + pos); + pos += offsetof(struct tpmt_ha, digest); + switch (algo) { + case TPM2_ALG_SHA1: + case TPM2_ALG_SHA256: + case TPM2_ALG_SHA384: + case TPM2_ALG_SHA512: + len = tpm2_algorithm_to_len(algo); + break; + default: + return 0; + } + + if (digest_list->count) { + if (algo != digest_list->digests[i].hash_alg || + log_position + pos + len >= elog->log_size) + return 0; + + memcpy(digest_list->digests[i].digest.sha512, + log + pos, len); + } + + pos += len; + } + + if (log_position + pos + sizeof(u32) >= elog->log_size) + return 0; + + event_size = get_unaligned_le32(log + pos); + pos += event_size + sizeof(u32); + if (log_position + pos > elog->log_size) + return 0; + + if (digest_list->count) { + rc = tcg2_pcr_extend(dev, pcr, digest_list); + if (rc) + return rc; + } + + log_position += pos; + } + + elog->log_position = log_position; + elog->found = true; + return 0; +} + +static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) +{ + struct tpml_digest_values digest_list; + struct tcg_efi_spec_id_event *event; + struct tcg_pcr_event *log; + u32 log_active; + u32 calc_size; + u32 active; + u32 count; + u32 evsz; + u32 mask; + u16 algo; + u16 len; + int rc; + u32 i; + u16 j; + + if (elog->log_size <= offsetof(struct tcg_pcr_event, event)) + return 0; + + log = (struct tcg_pcr_event *)elog->log; + if (get_unaligned_le32(&log->pcr_index) != 0 || + get_unaligned_le32(&log->event_type) != EV_NO_ACTION) + return 0; + + for (i = 0; i < sizeof(log->digest); i++) { + if (log->digest[i]) + return 0; + } + + evsz = get_unaligned_le32(&log->event_size); + if (evsz < offsetof(struct tcg_efi_spec_id_event, digest_sizes) || + evsz + offsetof(struct tcg_pcr_event, event) > elog->log_size) + return 0; + + event = (struct tcg_efi_spec_id_event *)log->event; + if (memcmp(event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03, + sizeof(TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03))) + return 0; + + if (event->spec_version_minor != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 || + event->spec_version_major != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2) + return 0; + + count = get_unaligned_le32(&event->number_of_algorithms); + if (count > ARRAY_SIZE(hash_algo_list)) + return 0; + + calc_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes) + + (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count) + + 1; + if (evsz != calc_size) + return 0; + + rc = tcg2_get_active_pcr_banks(dev, &active); + if (rc) + return rc; + + digest_list.count = 0; + log_active = 0; + + for (i = 0; i < count; ++i) { + algo = get_unaligned_le16(&event->digest_sizes[i].algorithm_id); + mask = tcg2_algorithm_to_mask(algo); + + if (!(active & mask)) + return 0; + + switch (algo) { + case TPM2_ALG_SHA1: + case TPM2_ALG_SHA256: + case TPM2_ALG_SHA384: + case TPM2_ALG_SHA512: + len = get_unaligned_le16(&event->digest_sizes[i].digest_size); + if (tpm2_algorithm_to_len(algo) != len) + return 0; + digest_list.digests[digest_list.count++].hash_alg = algo; + break; + default: + return 0; + } + + log_active |= mask; + } + + /* Ensure the previous firmware extended all the PCRs. */ + if (log_active != active) + return 0; + + /* Read PCR0 to check if previous firmware extended the PCRs or not. */ + rc = tcg2_pcr_read(dev, 0, &digest_list); + if (rc) + return rc; + + for (i = 0; i < digest_list.count; ++i) { + len = tpm2_algorithm_to_len(digest_list.digests[i].hash_alg); + for (j = 0; j < len; ++j) { + if (digest_list.digests[i].digest.sha512[j]) + break; + } + + /* PCR is non-zero; it has been extended, so skip extending. */ + if (j != len) { + digest_list.count = 0; + break; + } + } + + return tcg2_replay_eventlog(elog, dev, &digest_list, + offsetof(struct tcg_pcr_event, event) + + evsz); +} + +int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index, + struct tpml_digest_values *digest_list) +{ + u32 rc; + u32 i; + + for (i = 0; i < digest_list->count; i++) { + u32 alg = digest_list->digests[i].hash_alg; + + rc = tpm2_pcr_extend(dev, pcr_index, alg, + (u8 *)&digest_list->digests[i].digest, + tpm2_algorithm_to_len(alg)); + if (rc) { + printf("%s: error pcr:%u alg:%08x\n", __func__, + pcr_index, alg); + return rc; + } + } + + return 0; +} + +int tcg2_pcr_read(struct udevice *dev, u32 pcr_index, + struct tpml_digest_values *digest_list) +{ + struct tpm_chip_priv *priv; + u32 rc; + u32 i; + + priv = dev_get_uclass_priv(dev); + if (!priv) + return -ENODEV; + + for (i = 0; i < digest_list->count; i++) { + u32 alg = digest_list->digests[i].hash_alg; + u8 *digest = (u8 *)&digest_list->digests[i].digest; + + rc = tpm2_pcr_read(dev, pcr_index, priv->pcr_select_min, alg, + digest, tpm2_algorithm_to_len(alg), NULL); + if (rc) { + printf("%s: error pcr:%u alg:%08x\n", __func__, + pcr_index, alg); + return rc; + } + } + + return 0; +} + +int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog, + u32 pcr_index, u32 size, const u8 *data, u32 event_type, + u32 event_size, const u8 *event) +{ + struct tpml_digest_values digest_list; + int rc; + + if (data) + rc = tcg2_create_digest(dev, data, size, &digest_list); + else + rc = tcg2_create_digest(dev, event, event_size, &digest_list); + if (rc) + return rc; + + rc = tcg2_pcr_extend(dev, pcr_index, &digest_list); + if (rc) + return rc; + + return tcg2_log_append_check(elog, pcr_index, event_type, &digest_list, + event_size, event); +} + +int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, + bool ignore_existing_log) +{ + struct tcg2_event_log log; + int rc; + + elog->log_position = 0; + elog->found = false; + + rc = tcg2_platform_get_log(dev, (void **)&log.log, &log.log_size); + if (!rc) { + log.log_position = 0; + log.found = false; + + if (!ignore_existing_log) { + rc = tcg2_log_parse(dev, &log); + if (rc) + return rc; + } + + if (elog->log_size) { + if (log.found) { + if (elog->log_size < log.log_position) + return -ENOBUFS; + + /* + * Copy the discovered log into the user buffer + * if there's enough space. + */ + memcpy(elog->log, log.log, log.log_position); + } + + unmap_physmem(log.log, MAP_NOCACHE); + } else { + elog->log = log.log; + elog->log_size = log.log_size; + } + + elog->log_position = log.log_position; + elog->found = log.found; + } + + /* + * Initialize the log buffer if no log was discovered and the buffer is + * valid. User's can pass in their own buffer as a fallback if no + * memory region is found. + */ + if (!elog->found && elog->log_size) + rc = tcg2_log_init(dev, elog); + + return rc; +} + +int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog, + bool ignore_existing_log) +{ + int rc; + + rc = tcg2_platform_get_tpm2(dev); + if (rc) + return rc; + + rc = tpm_auto_start(*dev); + if (rc) + return rc; + + rc = tcg2_log_prepare_buffer(*dev, elog, ignore_existing_log); + if (rc) { + tcg2_measurement_term(*dev, elog, true); + return rc; + } + + rc = tcg2_measure_event(*dev, elog, 0, EV_S_CRTM_VERSION, + strlen(version_string) + 1, + (u8 *)version_string); + if (rc) { + tcg2_measurement_term(*dev, elog, true); + return rc; + } + + return 0; +} + +void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, + bool error) +{ + u32 event = error ? 0x1 : 0xffffffff; + int i; + + for (i = 0; i < 8; ++i) + tcg2_measure_event(dev, elog, i, EV_SEPARATOR, sizeof(event), + (const u8 *)&event); + + if (elog->log) + unmap_physmem(elog->log, MAP_NOCACHE); +} + +__weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size) +{ + const __be32 *addr_prop; + const __be32 *size_prop; + int asize; + int ssize; + + *addr = NULL; + *size = 0; + + addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize); + if (!addr_prop) + addr_prop = dev_read_prop(dev, "linux,sml-base", &asize); + + size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize); + if (!size_prop) + size_prop = dev_read_prop(dev, "linux,sml-size", &ssize); + + if (addr_prop && size_prop) { + u64 a = of_read_number(addr_prop, asize / sizeof(__be32)); + u64 s = of_read_number(size_prop, ssize / sizeof(__be32)); + + *addr = map_physmem(a, s, MAP_NOCACHE); + *size = (u32)s; + } else { + struct ofnode_phandle_args args; + phys_addr_t a; + fdt_size_t s; + + if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0, + 0, &args)) + return -ENODEV; + + a = ofnode_get_addr_size(args.node, "reg", &s); + if (a == FDT_ADDR_T_NONE) + return -ENOMEM; + + *addr = map_physmem(a, s, MAP_NOCACHE); + *size = (u32)s; + } + + return 0; +} + +__weak int tcg2_platform_get_tpm2(struct udevice **dev) +{ + for_each_tpm_device(*dev) { + if (tpm_get_version(*dev) == TPM_V2) + return 0; + } + + return -ENODEV; +} + +u32 tcg2_algorithm_to_mask(enum tpm2_algorithms algo) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) { + if (hash_algo_list[i].hash_alg == algo) + return hash_algo_list[i].hash_mask; + } + + return 0; +} + +__weak void tcg2_platform_startup_error(struct udevice *dev, int rc) {} diff --git a/lib/zlib/deflate.c b/lib/zlib/deflate.c index 7e1ed4f9b20..4549f4dc12a 100644 --- a/lib/zlib/deflate.c +++ b/lib/zlib/deflate.c @@ -196,30 +196,37 @@ struct static_tree_desc_s {int dummy;}; /* for buggy compilers */ zmemzero((Bytef *)s->head, (unsigned)(s->hash_size-1)*sizeof(*s->head)); /* ========================================================================= */ -int ZEXPORT deflateInit_(strm, level, stream_size) +int ZEXPORT deflateInit_(strm, level, version, stream_size) z_streamp strm; int level; + const char *version; int stream_size; { return deflateInit2_(strm, level, Z_DEFLATED, MAX_WBITS, DEF_MEM_LEVEL, - Z_DEFAULT_STRATEGY, stream_size); + Z_DEFAULT_STRATEGY, version, stream_size); /* To do: ignore strm->next_in if we use it as window */ } /* ========================================================================= */ int ZEXPORT deflateInit2_(strm, level, method, windowBits, memLevel, strategy, - stream_size) + version, stream_size) z_streamp strm; int level; int method; int windowBits; int memLevel; int strategy; + const char *version; int stream_size; { deflate_state *s; int wrap = 1; + static const char my_version[] = ZLIB_VERSION; + if (version == Z_NULL || version[0] != my_version[0] || + stream_size != sizeof(z_stream)) { + return Z_VERSION_ERROR; + } if (strm == Z_NULL) return Z_STREAM_ERROR; strm->msg = Z_NULL; diff --git a/lib/zlib/inffast.c b/lib/zlib/inffast.c index 5e2a65ad4d2..e3c7f3b892b 100644 --- a/lib/zlib/inffast.c +++ b/lib/zlib/inffast.c @@ -1,5 +1,5 @@ /* inffast.c -- fast decoding - * Copyright (C) 1995-2008, 2010, 2013 Mark Adler + * Copyright (C) 1995-2004 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ @@ -12,6 +12,25 @@ #ifndef ASMINF +/* Allow machine dependent optimization for post-increment or pre-increment. + Based on testing to date, + Pre-increment preferred for: + - PowerPC G3 (Adler) + - MIPS R5000 (Randers-Pehrson) + Post-increment preferred for: + - none + No measurable difference: + - Pentium III (Anderson) + - M68060 (Nikl) + */ +#ifdef POSTINC +# define OFF 0 +# define PUP(a) *(a)++ +#else +# define OFF 1 +# define PUP(a) *++(a) +#endif + /* Decode literal, length, and distance codes and write out the resulting literal and match bytes until either not enough input or output is @@ -47,13 +66,12 @@ requires strm->avail_out >= 258 for each loop to avoid checking for output space. */ -void ZLIB_INTERNAL inflate_fast(strm, start) -z_streamp strm; -unsigned start; /* inflate()'s starting value for strm->avail_out */ +void inflate_fast(z_streamp strm, unsigned start) +/* start: inflate()'s starting value for strm->avail_out */ { struct inflate_state FAR *state; - z_const unsigned char FAR *in; /* local strm->next_in */ - z_const unsigned char FAR *last; /* have enough input while in < last */ + unsigned char FAR *in; /* local strm->next_in */ + unsigned char FAR *last; /* while in < last, enough input available */ unsigned char FAR *out; /* local strm->next_out */ unsigned char FAR *beg; /* inflate()'s initial strm->next_out */ unsigned char FAR *end; /* while out < end, enough space available */ @@ -62,7 +80,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ #endif unsigned wsize; /* window size or zero if not using window */ unsigned whave; /* valid bytes in the window */ - unsigned wnext; /* window write index */ + unsigned write; /* window write index */ unsigned char FAR *window; /* allocated sliding window, if wsize != 0 */ unsigned long hold; /* local strm->hold */ unsigned bits; /* local strm->bits */ @@ -70,7 +88,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ code const FAR *dcode; /* local strm->distcode */ unsigned lmask; /* mask for first level of length codes */ unsigned dmask; /* mask for first level of distance codes */ - code here; /* retrieved table entry */ + code this; /* retrieved table entry */ unsigned op; /* code bits, operation, extra bits, or */ /* window position, window bytes to copy */ unsigned len; /* match length, unused bytes */ @@ -79,7 +97,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ /* copy state to local variables */ state = (struct inflate_state FAR *)strm->state; - in = strm->next_in; + in = strm->next_in - OFF; last = in + (strm->avail_in - 5); if (in > last && strm->avail_in > 5) { /* @@ -89,7 +107,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ strm->avail_in = 0xffffffff - (uintptr_t)in; last = in + (strm->avail_in - 5); } - out = strm->next_out; + out = strm->next_out - OFF; beg = out - (start - strm->avail_out); end = out + (strm->avail_out - 257); #ifdef INFLATE_STRICT @@ -97,7 +115,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ #endif wsize = state->wsize; whave = state->whave; - wnext = state->wnext; + write = state->write; window = state->window; hold = state->hold; bits = state->bits; @@ -110,29 +128,29 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ input data or output space */ do { if (bits < 15) { - hold += (unsigned long)(*in++) << bits; + hold += (unsigned long)(PUP(in)) << bits; bits += 8; - hold += (unsigned long)(*in++) << bits; + hold += (unsigned long)(PUP(in)) << bits; bits += 8; } - here = lcode[hold & lmask]; + this = lcode[hold & lmask]; dolen: - op = (unsigned)(here.bits); + op = (unsigned)(this.bits); hold >>= op; bits -= op; - op = (unsigned)(here.op); + op = (unsigned)(this.op); if (op == 0) { /* literal */ - Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ? + Tracevv((stderr, this.val >= 0x20 && this.val < 0x7f ? "inflate: literal '%c'\n" : - "inflate: literal 0x%02x\n", here.val)); - *out++ = (unsigned char)(here.val); + "inflate: literal 0x%02x\n", this.val)); + PUP(out) = (unsigned char)(this.val); } else if (op & 16) { /* length base */ - len = (unsigned)(here.val); + len = (unsigned)(this.val); op &= 15; /* number of extra bits */ if (op) { if (bits < op) { - hold += (unsigned long)(*in++) << bits; + hold += (unsigned long)(PUP(in)) << bits; bits += 8; } len += (unsigned)hold & ((1U << op) - 1); @@ -141,25 +159,25 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ } Tracevv((stderr, "inflate: length %u\n", len)); if (bits < 15) { - hold += (unsigned long)(*in++) << bits; + hold += (unsigned long)(PUP(in)) << bits; bits += 8; - hold += (unsigned long)(*in++) << bits; + hold += (unsigned long)(PUP(in)) << bits; bits += 8; } - here = dcode[hold & dmask]; + this = dcode[hold & dmask]; dodist: - op = (unsigned)(here.bits); + op = (unsigned)(this.bits); hold >>= op; bits -= op; - op = (unsigned)(here.op); + op = (unsigned)(this.op); if (op & 16) { /* distance base */ - dist = (unsigned)(here.val); + dist = (unsigned)(this.val); op &= 15; /* number of extra bits */ if (bits < op) { - hold += (unsigned long)(*in++) << bits; + hold += (unsigned long)(PUP(in)) << bits; bits += 8; if (bits < op) { - hold += (unsigned long)(*in++) << bits; + hold += (unsigned long)(PUP(in)) << bits; bits += 8; } } @@ -178,80 +196,108 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ if (dist > op) { /* see if copy from window */ op = dist - op; /* distance back in window */ if (op > whave) { - strm->msg = - (char *)"invalid distance too far back"; + strm->msg = (char *)"invalid distance too far back"; state->mode = BAD; break; } - from = window; - if (wnext == 0) { /* very common case */ + from = window - OFF; + if (write == 0) { /* very common case */ from += wsize - op; if (op < len) { /* some from window */ len -= op; do { - *out++ = *from++; + PUP(out) = PUP(from); } while (--op); from = out - dist; /* rest from output */ } } - else if (wnext < op) { /* wrap around window */ - from += wsize + wnext - op; - op -= wnext; + else if (write < op) { /* wrap around window */ + from += wsize + write - op; + op -= write; if (op < len) { /* some from end of window */ len -= op; do { - *out++ = *from++; + PUP(out) = PUP(from); } while (--op); - from = window; - if (wnext < len) { /* some from start of window */ - op = wnext; + from = window - OFF; + if (write < len) { /* some from start of window */ + op = write; len -= op; do { - *out++ = *from++; + PUP(out) = PUP(from); } while (--op); from = out - dist; /* rest from output */ } } } else { /* contiguous in window */ - from += wnext - op; + from += write - op; if (op < len) { /* some from window */ len -= op; do { - *out++ = *from++; + PUP(out) = PUP(from); } while (--op); from = out - dist; /* rest from output */ } } while (len > 2) { - *out++ = *from++; - *out++ = *from++; - *out++ = *from++; + PUP(out) = PUP(from); + PUP(out) = PUP(from); + PUP(out) = PUP(from); len -= 3; } if (len) { - *out++ = *from++; + PUP(out) = PUP(from); if (len > 1) - *out++ = *from++; + PUP(out) = PUP(from); } } else { + unsigned short *sout; + unsigned long loops; + from = out - dist; /* copy direct from output */ - do { /* minimum length is three */ - *out++ = *from++; - *out++ = *from++; - *out++ = *from++; - len -= 3; - } while (len > 2); - if (len) { - *out++ = *from++; - if (len > 1) - *out++ = *from++; - } + /* minimum length is three */ + /* Align out addr */ + if (!((long)(out - 1 + OFF) & 1)) { + PUP(out) = PUP(from); + len--; + } + sout = (unsigned short *)(out - OFF); + if (dist > 2 ) { + unsigned short *sfrom; + + sfrom = (unsigned short *)(from - OFF); + loops = len >> 1; + do + PUP(sout) = get_unaligned(++sfrom); + while (--loops); + out = (unsigned char *)sout + OFF; + from = (unsigned char *)sfrom + OFF; + } else { /* dist == 1 or dist == 2 */ + unsigned short pat16; + + pat16 = *(sout-2+2*OFF); + if (dist == 1) +#if defined(__BIG_ENDIAN) + pat16 = (pat16 & 0xff) | ((pat16 & 0xff ) << 8); +#elif defined(__LITTLE_ENDIAN) + pat16 = (pat16 & 0xff00) | ((pat16 & 0xff00 ) >> 8); +#else +#error __BIG_ENDIAN nor __LITTLE_ENDIAN is defined +#endif + loops = len >> 1; + do + PUP(sout) = pat16; + while (--loops); + out = (unsigned char *)sout + OFF; + } + if (len & 1) + PUP(out) = PUP(from); } } else if ((op & 64) == 0) { /* 2nd level distance code */ - here = dcode[here.val + (hold & ((1U << op) - 1))]; + this = dcode[this.val + (hold & ((1U << op) - 1))]; goto dodist; } else { @@ -261,7 +307,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ } } else if ((op & 64) == 0) { /* 2nd level length code */ - here = lcode[here.val + (hold & ((1U << op) - 1))]; + this = lcode[this.val + (hold & ((1U << op) - 1))]; goto dolen; } else if (op & 32) { /* end-of-block */ @@ -283,8 +329,8 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ hold &= (1U << bits) - 1; /* update state and return */ - strm->next_in = in; - strm->next_out = out; + strm->next_in = in + OFF; + strm->next_out = out + OFF; strm->avail_in = (unsigned)(in < last ? 5 + (last - in) : 5 - (in - last)); strm->avail_out = (unsigned)(out < end ? 257 + (end - out) : 257 - (out - end)); @@ -297,7 +343,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ inflate_fast() speedups that turned out slower (on a PowerPC G3 750CXe): - Using bit fields for code structure - Different op definition to avoid & for extra bits (do & for table bits) - - Three separate decoding do-loops for direct, window, and wnext == 0 + - Three separate decoding do-loops for direct, window, and write == 0 - Special case for distance > 1 copies to do overlapped load and store copy - Explicit branch predictions (based on measured branch probabilities) - Deferring match copy and interspersed it with decoding subsequent codes diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c index f7e81fc8b2a..8f767b7b9d2 100644 --- a/lib/zlib/inflate.c +++ b/lib/zlib/inflate.c @@ -21,7 +21,7 @@ int ZEXPORT inflateReset(z_streamp strm) state->head = Z_NULL; state->wsize = 0; state->whave = 0; - state->wnext = 0; + state->write = 0; state->hold = 0; state->bits = 0; state->lencode = state->distcode = state->next = state->codes; @@ -30,11 +30,14 @@ int ZEXPORT inflateReset(z_streamp strm) return Z_OK; } -int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, +int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, const char *version, int stream_size) { struct inflate_state FAR *state; + if (version == Z_NULL || version[0] != ZLIB_VERSION[0] || + stream_size != (int)(sizeof(z_stream))) + return Z_VERSION_ERROR; if (strm == Z_NULL) return Z_STREAM_ERROR; strm->msg = Z_NULL; /* in case we return an error */ if (strm->zalloc == (alloc_func)0) { @@ -67,9 +70,9 @@ int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, return inflateReset(strm); } -int ZEXPORT inflateInit_(z_streamp strm, int stream_size) +int ZEXPORT inflateInit_(z_streamp strm, const char *version, int stream_size) { - return inflateInit2_(strm, DEF_WBITS, stream_size); + return inflateInit2_(strm, DEF_WBITS, version, stream_size); } local void fixedtables(struct inflate_state FAR *state) @@ -112,7 +115,7 @@ local int updatewindow(z_streamp strm, unsigned out) /* if window not in use yet, initialize */ if (state->wsize == 0) { state->wsize = 1U << state->wbits; - state->wnext = 0; + state->write = 0; state->whave = 0; } @@ -120,22 +123,22 @@ local int updatewindow(z_streamp strm, unsigned out) copy = out - strm->avail_out; if (copy >= state->wsize) { zmemcpy(state->window, strm->next_out - state->wsize, state->wsize); - state->wnext = 0; + state->write = 0; state->whave = state->wsize; } else { - dist = state->wsize - state->wnext; + dist = state->wsize - state->write; if (dist > copy) dist = copy; - zmemcpy(state->window + state->wnext, strm->next_out - copy, dist); + zmemcpy(state->window + state->write, strm->next_out - copy, dist); copy -= dist; if (copy) { zmemcpy(state->window, strm->next_out - copy, copy); - state->wnext = copy; + state->write = copy; state->whave = state->wsize; } else { - state->wnext += dist; - if (state->wnext == state->wsize) state->wnext = 0; + state->write += dist; + if (state->write == state->wsize) state->write = 0; if (state->whave < state->wsize) state->whave += dist; } } @@ -820,12 +823,12 @@ int ZEXPORT inflate(z_streamp strm, int flush) copy = out - left; if (state->offset > copy) { /* copy from window */ copy = state->offset - copy; - if (copy > state->wnext) { - copy -= state->wnext; + if (copy > state->write) { + copy -= state->write; from = state->window + (state->wsize - copy); } else - from = state->window + (state->wnext - copy); + from = state->window + (state->write - copy); if (copy > state->length) copy = state->length; } else { /* copy from output */ diff --git a/lib/zlib/inflate.h b/lib/zlib/inflate.h index 2657d611cda..07bd3e78a7c 100644 --- a/lib/zlib/inflate.h +++ b/lib/zlib/inflate.h @@ -88,7 +88,7 @@ struct inflate_state { unsigned wbits; /* log base 2 of requested window size */ unsigned wsize; /* window size or zero if not using window */ unsigned whave; /* valid bytes in the window */ - unsigned wnext; /* window write index */ + unsigned write; /* window write index */ unsigned char FAR *window; /* allocated sliding window, if needed */ /* bit accumulator */ unsigned long hold; /* input bit accumulator */ diff --git a/lib/zlib/zutil.c b/lib/zlib/zutil.c index ec21b458fcc..609aac55ce1 100644 --- a/lib/zlib/zutil.c +++ b/lib/zlib/zutil.c @@ -21,6 +21,7 @@ const char * const z_errmsg[10] = { "data error", /* Z_DATA_ERROR (-3) */ "insufficient memory", /* Z_MEM_ERROR (-4) */ "buffer error", /* Z_BUF_ERROR (-5) */ +"incompatible version",/* Z_VERSION_ERROR (-6) */ ""}; #ifdef DEBUG diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 62f87517c09..3e68d5aa803 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -673,7 +673,7 @@ quiet_cmd_fdtgrep = FDTGREP $@ -n /chosen -n /config -O dtb | \ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ -P bootph-all -P bootph-pre-ram -P bootph-pre-sram \ - -P bootph-verify \ + -P bootph-verify -P bootph-some-ram \ $(migrate_all) \ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c index a0faf5aca90..e09a929a5e4 100644 --- a/test/cmd/fdt.c +++ b/test/cmd/fdt.c @@ -1346,6 +1346,10 @@ static int fdt_test_chosen(struct unit_test_state *uts) ut_assert_nextlinen("\tu-boot,version = "); /* Ignore the version string */ if (env_bootargs) ut_assert_nextline("\tbootargs = \"%s\";", env_bootargs); + if (IS_ENABLED(CONFIG_DM_RNG) && + !IS_ENABLED(CONFIG_MEASURED_BOOT) && + !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)) + ut_assert_nextlinen("\tkaslr-seed = "); ut_assert_nextline("};"); ut_assertok(ut_check_console_end(uts)); @@ -1362,6 +1366,10 @@ static int fdt_test_chosen(struct unit_test_state *uts) ut_assert_nextlinen("\tu-boot,version = "); /* Ignore the version string */ if (env_bootargs) ut_assert_nextline("\tbootargs = \"%s\";", env_bootargs); + if (IS_ENABLED(CONFIG_DM_RNG) && + !IS_ENABLED(CONFIG_MEASURED_BOOT) && + !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)) + ut_assert_nextlinen("\tkaslr-seed = "); ut_assert_nextline("};"); ut_assertok(ut_check_console_end(uts)); diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 4db2171a4b1..7da381f1a54 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -236,7 +236,6 @@ static int dm_test_acpi_fill_header(struct unit_test_state *uts) hdr.length = 0x11; hdr.revision = 0x22; hdr.checksum = 0x33; - hdr.creator_revision = 0x44; acpi_fill_header(&hdr, "ABCD"); ut_asserteq_mem("ABCD", hdr.signature, sizeof(hdr.signature)); @@ -248,7 +247,7 @@ static int dm_test_acpi_fill_header(struct unit_test_state *uts) sizeof(hdr.oem_table_id)); ut_asserteq(OEM_REVISION, hdr.oem_revision); ut_asserteq_mem(ASLC_ID, hdr.creator_id, sizeof(hdr.creator_id)); - ut_asserteq(0x44, hdr.creator_revision); + ut_asserteq(ASL_REVISION, hdr.creator_revision); return 0; } diff --git a/test/dm/core.c b/test/dm/core.c index 4741c81bcc1..dbad1b317db 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -1006,7 +1006,6 @@ static int dm_test_uclass_before_ready(struct unit_test_state *uts) ut_assertok(uclass_get(UCLASS_TEST, &uc)); gd->dm_root = NULL; - gd->dm_root_f = NULL; memset(&gd->uclass_root, '\0', sizeof(gd->uclass_root)); ut_asserteq_ptr(NULL, uclass_find(UCLASS_TEST)); diff --git a/test/py/requirements.txt b/test/py/requirements.txt index 0f67c3c6194..c1dd636931f 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -20,7 +20,7 @@ pytest==6.2.5 pytest-xdist==2.5.0 python-mimeparse==1.6.0 python-subunit==1.3.0 -requests==2.31.0 +requests==2.32.2 setuptools==65.5.1 six==1.16.0 testtools==2.3.0 diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py index ff7ac7c8101..0fa0747fc76 100644 --- a/test/py/tests/test_efi_secboot/conftest.py +++ b/test/py/tests/test_efi_secboot/conftest.py @@ -64,6 +64,12 @@ def efi_boot_env(request, u_boot_config): check_call('cd %s; %scert-to-efi-sig-list -g %s db1.crt db1.esl; %ssign-efi-sig-list -t "2020-04-05" -c KEK.crt -k KEK.key db db1.esl db1.auth' % (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH), shell=True) + # db2 (APPEND_WRITE) + check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db2/ -keyout db2.key -out db2.crt -nodes -days 365' + % mnt_point, shell=True) + check_call('cd %s; %scert-to-efi-sig-list -g %s db2.crt db2.esl; %ssign-efi-sig-list -a -c KEK.crt -k KEK.key db db2.esl db2.auth' + % (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH), + shell=True) # dbx (TEST_dbx certificate) check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_dbx/ -keyout dbx.key -out dbx.crt -nodes -days 365' % mnt_point, shell=True) @@ -84,6 +90,10 @@ def efi_boot_env(request, u_boot_config): check_call('cd %s; %scert-to-efi-hash-list -g %s -s 256 db1.crt dbx_hash1.crl; %ssign-efi-sig-list -t "2020-04-06" -c KEK.crt -k KEK.key dbx dbx_hash1.crl dbx_hash1.auth' % (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH), shell=True) + # dbx_hash2 (digest of TEST_db2 certificate, with APPEND_WRITE) + check_call('cd %s; %scert-to-efi-hash-list -g %s -s 256 db2.crt dbx_hash2.crl; %ssign-efi-sig-list -a -c KEK.crt -k KEK.key dbx dbx_hash2.crl dbx_hash2.auth' + % (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH), + shell=True) # dbx_db (with TEST_db certificate) check_call('cd %s; %ssign-efi-sig-list -t "2020-04-05" -c KEK.crt -k KEK.key dbx db.esl dbx_db.auth' % (mnt_point, EFITOOLS_PATH), diff --git a/test/py/tests/test_efi_secboot/test_authvar.py b/test/py/tests/test_efi_secboot/test_authvar.py index f99b8270a64..d5aeb650480 100644 --- a/test/py/tests/test_efi_secboot/test_authvar.py +++ b/test/py/tests/test_efi_secboot/test_authvar.py @@ -183,7 +183,7 @@ class TestEfiAuthVar(object): assert 'db:' in ''.join(output) output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 db1.auth', + 'fatload host 0:1 4000000 db2.auth', 'setenv -e -nv -bs -rt -a -i 4000000:$filesize db']) assert 'Failed to set EFI variable' in ''.join(output) @@ -197,7 +197,7 @@ class TestEfiAuthVar(object): with u_boot_console.log.section('Test Case 3c'): # Test Case 3c, update with correct signature output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 db1.auth', + 'fatload host 0:1 4000000 db2.auth', 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db', 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db']) assert 'Failed to set EFI variable' not in ''.join(output) diff --git a/test/py/tests/test_efi_secboot/test_signed.py b/test/py/tests/test_efi_secboot/test_signed.py index 5000a4ab7b6..f604138a356 100644 --- a/test/py/tests/test_efi_secboot/test_signed.py +++ b/test/py/tests/test_efi_secboot/test_signed.py @@ -177,7 +177,7 @@ class TestEfiSignedImage(object): with u_boot_console.log.section('Test Case 5b'): # Test Case 5b, authenticated if both signatures are verified output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 db1.auth', + 'fatload host 0:1 4000000 db2.auth', 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ @@ -201,7 +201,7 @@ class TestEfiSignedImage(object): with u_boot_console.log.section('Test Case 5d'): # Test Case 5d, rejected if both of signatures are revoked output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 dbx_hash1.auth', + 'fatload host 0:1 4000000 dbx_hash2.auth', 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize dbx']) assert 'Failed to set EFI variable' not in ''.join(output) output = u_boot_console.run_command_list([ @@ -223,7 +223,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK', 'fatload host 0:1 4000000 PK.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK', - 'fatload host 0:1 4000000 db1.auth', + 'fatload host 0:1 4000000 db2.auth', 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db', 'fatload host 0:1 4000000 dbx_hash1.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx']) @@ -300,7 +300,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK', 'fatload host 0:1 4000000 PK.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK', - 'fatload host 0:1 4000000 db1.auth', + 'fatload host 0:1 4000000 db2.auth', 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db', 'fatload host 0:1 4000000 dbx_hash384.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx']) @@ -323,7 +323,7 @@ class TestEfiSignedImage(object): 'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK', 'fatload host 0:1 4000000 PK.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK', - 'fatload host 0:1 4000000 db1.auth', + 'fatload host 0:1 4000000 db2.auth', 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db', 'fatload host 0:1 4000000 dbx_hash512.auth', 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx']) diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index 230e055667f..872e9746c8c 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -711,6 +711,13 @@ missing-msg: information about what needs to be fixed. See missing-blob-help for the message for each tag. +assume-size: + Sets the assumed size of a blob entry if it is missing. This allows for a + check that the rest of the image fits into the available space, even when + the contents are not available. If the entry is missing, Binman will use + this assumed size for the entry size, including creating a fake file of that + size if requested. + no-expanded: By default binman substitutes entries with expanded versions if available, so that a `u-boot` entry type turns into `u-boot-expanded`, for example. The diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index 254afe76074..bdda1ef2855 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -470,11 +470,11 @@ updating the EC on startup via software sync. .. _etype_efi_capsule: -Entry: capsule: Entry for generating EFI Capsule files ------------------------------------------------------- +Entry: efi-capsule: Generate EFI capsules +----------------------------------------- -The parameters needed for generation of the capsules can be provided -as properties in the entry. +The parameters needed for generation of the capsules can +be provided as properties in the entry. Properties / Entry arguments: - image-index: Unique number for identifying corresponding @@ -495,9 +495,9 @@ Properties / Entry arguments: file. Mandatory property for generating signed capsules. - oem-flags - OEM flags to be passed through capsule header. - Since this is a subclass of Entry_section, all properties of the parent - class also apply here. Except for the properties stated as mandatory, the - rest of the properties are optional. +Since this is a subclass of Entry_section, all properties of the parent +class also apply here. Except for the properties stated as mandatory, the +rest of the properties are optional. For more details on the description of the capsule format, and the capsule update functionality, refer Section 8.5 and Chapter 23 in the `UEFI @@ -510,17 +510,17 @@ provided as a subnode of the capsule entry. A typical capsule entry node would then look something like this:: capsule { - type = "efi-capsule"; - image-index = <0x1>; - /* Image GUID for testing capsule update */ - image-guid = SANDBOX_UBOOT_IMAGE_GUID; - hardware-instance = <0x0>; - private-key = "path/to/the/private/key"; - public-key-cert = "path/to/the/public-key-cert"; - oem-flags = <0x8000>; + type = "efi-capsule"; + image-index = <0x1>; + /* Image GUID for testing capsule update */ + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + hardware-instance = <0x0>; + private-key = "path/to/the/private/key"; + public-key-cert = "path/to/the/public-key-cert"; + oem-flags = <0x8000>; - u-boot { - }; + u-boot { + }; }; In the above example, the capsule payload is the U-Boot image. The @@ -534,8 +534,8 @@ payload using the blob-ext subnode. .. _etype_efi_empty_capsule: -Entry: efi-empty-capsule: Entry for generating EFI Empty Capsule files ----------------------------------------------------------------------- +Entry: efi-empty-capsule: Generate EFI empty capsules +----------------------------------------------------- The parameters needed for generation of the empty capsules can be provided as properties in the entry. @@ -551,22 +551,22 @@ update functionality, refer Section 8.5 and Chapter 23 in the `UEFI specification`_. For more information on the empty capsule, refer the sections 2.3.2 and 2.3.3 in the `Dependable Boot specification`_. -A typical accept empty capsule entry node would then look something -like this:: +A typical accept empty capsule entry node would then look something like +this:: empty-capsule { - type = "efi-empty-capsule"; - /* GUID of the image being accepted */ - image-type-id = SANDBOX_UBOOT_IMAGE_GUID; - capsule-type = "accept"; + type = "efi-empty-capsule"; + /* GUID of image being accepted */ + image-type-id = SANDBOX_UBOOT_IMAGE_GUID; + capsule-type = "accept"; }; -A typical revert empty capsule entry node would then look something -like this:: +A typical revert empty capsule entry node would then look something like +this:: empty-capsule { - type = "efi-empty-capsule"; - capsule-type = "revert"; + type = "efi-empty-capsule"; + capsule-type = "revert"; }; The empty capsules do not have any input payload image. @@ -1521,6 +1521,28 @@ byte. +.. _etype_nxp_imx8mcst: + +Entry: nxp-imx8mcst: NXP i.MX8M CST .cfg file generator and cst invoker +----------------------------------------------------------------------- + +Properties / Entry arguments: + - nxp,loader-address - loader address (SPL text base) + + + +.. _etype_nxp_imx8mimage: + +Entry: nxp-imx8mimage: NXP i.MX8M imx8mimage .cfg file generator and mkimage invoker +------------------------------------------------------------------------------------ + +Properties / Entry arguments: + - nxp,boot-from - device to boot from (e.g. 'sd') + - nxp,loader-address - loader address (SPL text base) + - nxp,rom-version - BootROM version ('2' for i.MX8M Nano and Plus) + + + .. _etype_opensbi: Entry: opensbi: RISC-V OpenSBI fw_dynamic blob @@ -1929,6 +1951,12 @@ Properties / Entry arguments: - content: List of phandles to entries to sign - keyfile: Filename of file containing key to sign binary with - sha: Hash function to be used for signing + - auth-in-place: This is an integer field that contains two pieces + of information: + + - Lower Byte - Remains 0x02 as per our use case + ( 0x02: Move the authenticated binary back to the header ) + - Upper Byte - The Host ID of the core owning the firewall Output files: - input.<unique_name> - input file passed to openssl @@ -1937,6 +1965,35 @@ Output files: - cert.<unique_name> - output file generated by openssl (which is used as the entry contents) +Depending on auth-in-place information in the inputs, we read the +firewall nodes that describe the configurations of firewall that TIFS +will be doing after reading the certificate. + +The syntax of the firewall nodes are as such:: + + firewall-257-0 { + id = <257>; /* The ID of the firewall being configured */ + region = <0>; /* Region number to configure */ + + control = /* The control register */ + <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; + + permissions = /* The permission registers */ + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + + /* More defines can be found in k3-security.h */ + + start_address = /* The Start Address of the firewall */ + <0x0 0x0>; + end_address = /* The End Address of the firewall */ + <0xff 0xffffffff>; + }; + + openssl signs the provided data, using the TI templated config file and writes the signature in this entry. This allows verification that the data is genuine. diff --git a/tools/binman/entry.py b/tools/binman/entry.py index 42e0b7b9145..219d5dcecab 100644 --- a/tools/binman/entry.py +++ b/tools/binman/entry.py @@ -315,6 +315,7 @@ class Entry(object): self.overlap = fdt_util.GetBool(self._node, 'overlap') if self.overlap: self.required_props += ['offset', 'size'] + self.assume_size = fdt_util.GetInt(self._node, 'assume-size', 0) # This is only supported by blobs and sections at present self.compress = fdt_util.GetString(self._node, 'compress', 'none') @@ -812,7 +813,7 @@ class Entry(object): as missing """ print('''Binman Entry Documentation -=========================== +========================== This file describes the entry types supported by binman. These entry types can be placed in an image one by one to build up a final firmware image. It is diff --git a/tools/binman/entry_test.py b/tools/binman/entry_test.py index ac6582cf86a..40d74d401a2 100644 --- a/tools/binman/entry_test.py +++ b/tools/binman/entry_test.py @@ -103,7 +103,7 @@ class TestEntry(unittest.TestCase): ent = entry.Entry.Create(None, self.GetNode(), 'missing', missing_etype=True) self.assertTrue(isinstance(ent, Entry_blob)) - self.assertEquals('missing', ent.etype) + self.assertEqual('missing', ent.etype) def testDecompressData(self): """Test the DecompressData() method of the base class""" @@ -111,8 +111,8 @@ class TestEntry(unittest.TestCase): base.compress = 'lz4' bintools = {} base.comp_bintool = base.AddBintool(bintools, '_testing') - self.assertEquals(tools.get_bytes(0, 1024), base.CompressData(b'abc')) - self.assertEquals(tools.get_bytes(0, 1024), base.DecompressData(b'abc')) + self.assertEqual(tools.get_bytes(0, 1024), base.CompressData(b'abc')) + self.assertEqual(tools.get_bytes(0, 1024), base.DecompressData(b'abc')) def testLookupOffset(self): """Test the lookup_offset() method of the base class""" diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py index 064fae50365..041e1122953 100644 --- a/tools/binman/etype/blob.py +++ b/tools/binman/etype/blob.py @@ -48,11 +48,16 @@ class Entry_blob(Entry): self.external and (self.optional or self.section.GetAllowMissing())) # Allow the file to be missing if not self._pathname: + if not fake_size and self.assume_size: + fake_size = self.assume_size self._pathname, faked = self.check_fake_fname(self._filename, fake_size) self.missing = True if not faked: - self.SetContents(b'') + content_size = 0 + if self.assume_size: # Ensure we get test coverage on next line + content_size = self.assume_size + self.SetContents(tools.get_bytes(0, content_size)) return True self.ReadBlobContents() diff --git a/tools/binman/etype/efi_capsule.py b/tools/binman/etype/efi_capsule.py index e3203717822..751f654bf31 100644 --- a/tools/binman/etype/efi_capsule.py +++ b/tools/binman/etype/efi_capsule.py @@ -36,23 +36,23 @@ class Entry_efi_capsule(Entry_section): be provided as properties in the entry. Properties / Entry arguments: - - image-index: Unique number for identifying corresponding - payload image. Number between 1 and descriptor count, i.e. - the total number of firmware images that can be updated. Mandatory - property. - - image-guid: Image GUID which will be used for identifying the - updatable image on the board. Mandatory property. - - hardware-instance: Optional number for identifying unique - hardware instance of a device in the system. Default value of 0 - for images where value is not to be used. - - fw-version: Value of image version that can be put on the capsule - through the Firmware Management Protocol(FMP) header. - - monotonic-count: Count used when signing an image. - - private-key: Path to PEM formatted .key private key file. Mandatory - property for generating signed capsules. - - public-key-cert: Path to PEM formatted .crt public key certificate - file. Mandatory property for generating signed capsules. - - oem-flags - OEM flags to be passed through capsule header. + - image-index: Unique number for identifying corresponding + payload image. Number between 1 and descriptor count, i.e. + the total number of firmware images that can be updated. Mandatory + property. + - image-guid: Image GUID which will be used for identifying the + updatable image on the board. Mandatory property. + - hardware-instance: Optional number for identifying unique + hardware instance of a device in the system. Default value of 0 + for images where value is not to be used. + - fw-version: Value of image version that can be put on the capsule + through the Firmware Management Protocol(FMP) header. + - monotonic-count: Count used when signing an image. + - private-key: Path to PEM formatted .key private key file. Mandatory + property for generating signed capsules. + - public-key-cert: Path to PEM formatted .crt public key certificate + file. Mandatory property for generating signed capsules. + - oem-flags - OEM flags to be passed through capsule header. Since this is a subclass of Entry_section, all properties of the parent class also apply here. Except for the properties stated as mandatory, the @@ -66,9 +66,9 @@ class Entry_efi_capsule(Entry_section): properties in the entry. The payload to be used in the capsule is to be provided as a subnode of the capsule entry. - A typical capsule entry node would then look something like this + A typical capsule entry node would then look something like this:: - capsule { + capsule { type = "efi-capsule"; image-index = <0x1>; /* Image GUID for testing capsule update */ @@ -80,7 +80,7 @@ class Entry_efi_capsule(Entry_section): u-boot { }; - }; + }; In the above example, the capsule payload is the U-Boot image. The capsule entry would read the contents of the payload and put them diff --git a/tools/binman/etype/efi_empty_capsule.py b/tools/binman/etype/efi_empty_capsule.py index 064bf9a77f0..1d99fbfb3bb 100644 --- a/tools/binman/etype/efi_empty_capsule.py +++ b/tools/binman/etype/efi_empty_capsule.py @@ -19,31 +19,33 @@ class Entry_efi_empty_capsule(Entry_section): be provided as properties in the entry. Properties / Entry arguments: - - image-guid: Image GUID which will be used for identifying the - updatable image on the board. Mandatory for accept capsule. - - capsule-type - String to indicate type of capsule to generate. Valid - values are 'accept' and 'revert'. + - image-guid: Image GUID which will be used for identifying the + updatable image on the board. Mandatory for accept capsule. + - capsule-type - String to indicate type of capsule to generate. Valid + values are 'accept' and 'revert'. For more details on the description of the capsule format, and the capsule update functionality, refer Section 8.5 and Chapter 23 in the `UEFI specification`_. For more information on the empty capsule, refer the sections 2.3.2 and 2.3.3 in the `Dependable Boot specification`_. - A typical accept empty capsule entry node would then look something like this + A typical accept empty capsule entry node would then look something like + this:: - empty-capsule { + empty-capsule { type = "efi-empty-capsule"; /* GUID of image being accepted */ image-type-id = SANDBOX_UBOOT_IMAGE_GUID; capsule-type = "accept"; - }; + }; - A typical revert empty capsule entry node would then look something like this + A typical revert empty capsule entry node would then look something like + this:: - empty-capsule { + empty-capsule { type = "efi-empty-capsule"; capsule-type = "revert"; - }; + }; The empty capsules do not have any input payload image. diff --git a/tools/binman/etype/intel_descriptor.py b/tools/binman/etype/intel_descriptor.py index 7fe88a9ec1a..3ce967fe81a 100644 --- a/tools/binman/etype/intel_descriptor.py +++ b/tools/binman/etype/intel_descriptor.py @@ -59,7 +59,7 @@ class Entry_intel_descriptor(Entry_blob_ext): if self.missing: # Return zero offsets so that these entries get placed somewhere if self.HasSibling('intel-me'): - info['intel-me'] = [0, None] + info['intel-me'] = [0x1000, None] return info offset = self.data.find(FD_SIGNATURE) if offset == -1: diff --git a/tools/binman/etype/ti_secure.py b/tools/binman/etype/ti_secure.py index 704dcf8a381..420ee263e4f 100644 --- a/tools/binman/etype/ti_secure.py +++ b/tools/binman/etype/ti_secure.py @@ -53,10 +53,11 @@ class Entry_ti_secure(Entry_x509_cert): - keyfile: Filename of file containing key to sign binary with - sha: Hash function to be used for signing - auth-in-place: This is an integer field that contains two pieces - of information - Lower Byte - Remains 0x02 as per our use case - ( 0x02: Move the authenticated binary back to the header ) - Upper Byte - The Host ID of the core owning the firewall + of information: + + - Lower Byte - Remains 0x02 as per our use case + ( 0x02: Move the authenticated binary back to the header ) + - Upper Byte - The Host ID of the core owning the firewall Output files: - input.<unique_name> - input file passed to openssl @@ -69,29 +70,29 @@ class Entry_ti_secure(Entry_x509_cert): firewall nodes that describe the configurations of firewall that TIFS will be doing after reading the certificate. - The syntax of the firewall nodes are as such: + The syntax of the firewall nodes are as such:: - firewall-257-0 { - id = <257>; /* The ID of the firewall being configured */ - region = <0>; /* Region number to configure */ + firewall-257-0 { + id = <257>; /* The ID of the firewall being configured */ + region = <0>; /* Region number to configure */ - control = /* The control register */ - <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; + control = /* The control register */ + <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; - permissions = /* The permission registers */ - <((FWPRIVID_ALL << FWPRIVID_SHIFT) | - FWPERM_SECURE_PRIV_RWCD | - FWPERM_SECURE_USER_RWCD | - FWPERM_NON_SECURE_PRIV_RWCD | - FWPERM_NON_SECURE_USER_RWCD)>; + permissions = /* The permission registers */ + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; - /* More defines can be found in k3-security.h */ + /* More defines can be found in k3-security.h */ - start_address = /* The Start Address of the firewall */ - <0x0 0x0>; - end_address = /* The End Address of the firewall */ - <0xff 0xffffffff>; - }; + start_address = /* The Start Address of the firewall */ + <0x0 0x0>; + end_address = /* The End Address of the firewall */ + <0xff 0xffffffff>; + }; openssl signs the provided data, using the TI templated config file and diff --git a/tools/binman/fdt_test.py b/tools/binman/fdt_test.py index 7ef87295463..564c1770820 100644 --- a/tools/binman/fdt_test.py +++ b/tools/binman/fdt_test.py @@ -44,43 +44,43 @@ class TestFdt(unittest.TestCase): fname = self.GetCompiled('045_prop_test.dts') dt = FdtScan(fname) node = dt.GetNode('/binman/intel-me') - self.assertEquals('intel-me', node.name) + self.assertEqual('intel-me', node.name) val = fdt_util.GetString(node, 'filename') - self.assertEquals(str, type(val)) - self.assertEquals('me.bin', val) + self.assertEqual(str, type(val)) + self.assertEqual('me.bin', val) prop = node.props['intval'] - self.assertEquals(fdt.Type.INT, prop.type) - self.assertEquals(3, fdt_util.GetInt(node, 'intval')) + self.assertEqual(fdt.Type.INT, prop.type) + self.assertEqual(3, fdt_util.GetInt(node, 'intval')) prop = node.props['intarray'] - self.assertEquals(fdt.Type.INT, prop.type) - self.assertEquals(list, type(prop.value)) - self.assertEquals(2, len(prop.value)) - self.assertEquals([5, 6], + self.assertEqual(fdt.Type.INT, prop.type) + self.assertEqual(list, type(prop.value)) + self.assertEqual(2, len(prop.value)) + self.assertEqual([5, 6], [fdt_util.fdt32_to_cpu(val) for val in prop.value]) prop = node.props['byteval'] - self.assertEquals(fdt.Type.BYTE, prop.type) - self.assertEquals(chr(8), prop.value) + self.assertEqual(fdt.Type.BYTE, prop.type) + self.assertEqual(chr(8), prop.value) prop = node.props['bytearray'] - self.assertEquals(fdt.Type.BYTE, prop.type) - self.assertEquals(list, type(prop.value)) - self.assertEquals(str, type(prop.value[0])) - self.assertEquals(3, len(prop.value)) - self.assertEquals([chr(1), '#', '4'], prop.value) + self.assertEqual(fdt.Type.BYTE, prop.type) + self.assertEqual(list, type(prop.value)) + self.assertEqual(str, type(prop.value[0])) + self.assertEqual(3, len(prop.value)) + self.assertEqual([chr(1), '#', '4'], prop.value) prop = node.props['longbytearray'] - self.assertEquals(fdt.Type.INT, prop.type) - self.assertEquals(0x090a0b0c, fdt_util.GetInt(node, 'longbytearray')) + self.assertEqual(fdt.Type.INT, prop.type) + self.assertEqual(0x090a0b0c, fdt_util.GetInt(node, 'longbytearray')) prop = node.props['stringval'] - self.assertEquals(fdt.Type.STRING, prop.type) - self.assertEquals('message2', fdt_util.GetString(node, 'stringval')) + self.assertEqual(fdt.Type.STRING, prop.type) + self.assertEqual('message2', fdt_util.GetString(node, 'stringval')) prop = node.props['stringarray'] - self.assertEquals(fdt.Type.STRING, prop.type) - self.assertEquals(list, type(prop.value)) - self.assertEquals(3, len(prop.value)) - self.assertEquals(['another', 'multi-word', 'message'], prop.value) + self.assertEqual(fdt.Type.STRING, prop.type) + self.assertEqual(list, type(prop.value)) + self.assertEqual(3, len(prop.value)) + self.assertEqual(['another', 'multi-word', 'message'], prop.value) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 8a44bc051b3..e4da04030a5 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -2095,7 +2095,7 @@ class TestFunctional(unittest.TestCase): dtb.Scan() props = self._GetPropTree(dtb, ['size', 'uncomp-size']) orig = self._decompress(data) - self.assertEquals(COMPRESS_DATA, orig) + self.assertEqual(COMPRESS_DATA, orig) # Do a sanity check on various fields image = control.images['image'] @@ -2809,9 +2809,9 @@ class TestFunctional(unittest.TestCase): orig_entry = orig_image.GetEntries()['fdtmap'] entry = image.GetEntries()['fdtmap'] - self.assertEquals(orig_entry.offset, entry.offset) - self.assertEquals(orig_entry.size, entry.size) - self.assertEquals(orig_entry.image_pos, entry.image_pos) + self.assertEqual(orig_entry.offset, entry.offset) + self.assertEqual(orig_entry.size, entry.size) + self.assertEqual(orig_entry.image_pos, entry.image_pos) def testReadImageNoHeader(self): """Test accessing an image's FDT map without an image header""" @@ -3895,7 +3895,7 @@ class TestFunctional(unittest.TestCase): mat = re_line.match(line) vals[mat.group(1)].append(mat.group(2)) - self.assertEquals('FIT description: test-desc', lines[0]) + self.assertEqual('FIT description: test-desc', lines[0]) self.assertIn('Created:', lines[1]) self.assertIn('Image 0 (kernel)', vals) self.assertIn('Hash value', vals) @@ -4012,7 +4012,7 @@ class TestFunctional(unittest.TestCase): fit_pos, fdt_util.fdt32_to_cpu(fnode.props['data-position'].value)) - self.assertEquals(expected_size, len(data)) + self.assertEqual(expected_size, len(data)) actual_pos = len(U_BOOT_DATA) + fit_pos self.assertEqual(U_BOOT_DATA + b'aa', data[actual_pos:actual_pos + external_data_size]) @@ -4431,7 +4431,7 @@ class TestFunctional(unittest.TestCase): props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size', 'uncomp-size']) orig = self._decompress(data) - self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig) + self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, orig) # Do a sanity check on various fields image = control.images['image'] @@ -4475,7 +4475,7 @@ class TestFunctional(unittest.TestCase): 'uncomp-size']) orig = self._decompress(data) - self.assertEquals(COMPRESS_DATA + COMPRESS_DATA + U_BOOT_DATA, orig) + self.assertEqual(COMPRESS_DATA + COMPRESS_DATA + U_BOOT_DATA, orig) # Do a sanity check on various fields image = control.images['image'] @@ -4519,7 +4519,7 @@ class TestFunctional(unittest.TestCase): props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size', 'uncomp-size']) orig = self._decompress(data) - self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig) + self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, orig) expected = { 'section/blob:offset': 0, 'section/blob:size': len(COMPRESS_DATA), @@ -4545,7 +4545,7 @@ class TestFunctional(unittest.TestCase): props = self._GetPropTree(dtb, ['offset', 'image-pos', 'size', 'uncomp-size']) orig = self._decompress(data) - self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, orig) + self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, orig) expected = { 'section/blob:offset': 0, 'section/blob:size': len(COMPRESS_DATA), @@ -4580,7 +4580,7 @@ class TestFunctional(unittest.TestCase): 'uncomp-size']) base = data[len(U_BOOT_DATA):] - self.assertEquals(U_BOOT_DATA, base[:len(U_BOOT_DATA)]) + self.assertEqual(U_BOOT_DATA, base[:len(U_BOOT_DATA)]) rest = base[len(U_BOOT_DATA):] # Check compressed data @@ -4588,22 +4588,22 @@ class TestFunctional(unittest.TestCase): expect1 = bintool.compress(COMPRESS_DATA + U_BOOT_DATA) data1 = rest[:len(expect1)] section1 = self._decompress(data1) - self.assertEquals(expect1, data1) - self.assertEquals(COMPRESS_DATA + U_BOOT_DATA, section1) + self.assertEqual(expect1, data1) + self.assertEqual(COMPRESS_DATA + U_BOOT_DATA, section1) rest1 = rest[len(expect1):] expect2 = bintool.compress(COMPRESS_DATA + COMPRESS_DATA) data2 = rest1[:len(expect2)] section2 = self._decompress(data2) - self.assertEquals(expect2, data2) - self.assertEquals(COMPRESS_DATA + COMPRESS_DATA, section2) + self.assertEqual(expect2, data2) + self.assertEqual(COMPRESS_DATA + COMPRESS_DATA, section2) rest2 = rest1[len(expect2):] expect_size = (len(U_BOOT_DATA) + len(U_BOOT_DATA) + len(expect1) + len(expect2) + len(U_BOOT_DATA)) - #self.assertEquals(expect_size, len(data)) + #self.assertEqual(expect_size, len(data)) - #self.assertEquals(U_BOOT_DATA, rest2) + #self.assertEqual(U_BOOT_DATA, rest2) self.maxDiff = None expected = { @@ -4695,7 +4695,7 @@ class TestFunctional(unittest.TestCase): u_boot = image.GetEntries()['section'].GetEntries()['u-boot'] - self.assertEquals(U_BOOT_DATA, u_boot.ReadData()) + self.assertEqual(U_BOOT_DATA, u_boot.ReadData()) def testTplNoDtb(self): """Test that an image with tpl/u-boot-tpl-nodtb.bin can be created""" @@ -5526,7 +5526,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap segments, entry = elf.read_loadable_segments(elf_data) # We assume there are two segments - self.assertEquals(2, len(segments)) + self.assertEqual(2, len(segments)) atf1 = dtb.GetNode('/images/atf-1') _, start, data = segments[0] @@ -6107,7 +6107,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = bintool.compress(COMPRESS_DATA) self.assertNotEqual(COMPRESS_DATA, data) orig = bintool.decompress(data) - self.assertEquals(COMPRESS_DATA, orig) + self.assertEqual(COMPRESS_DATA, orig) def testCompUtilVersions(self): """Test tool version of compression algorithms""" @@ -6125,7 +6125,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap self.assertNotEqual(COMPRESS_DATA, data) data += tools.get_bytes(0, 64) orig = bintool.decompress(data) - self.assertEquals(COMPRESS_DATA, orig) + self.assertEqual(COMPRESS_DATA, orig) def testCompressDtbZstd(self): """Test that zstd compress of device-tree files failed""" @@ -7460,5 +7460,33 @@ fdt fdtmap Extract the devicetree blob from the fdtmap with self.assertRaises(ValueError) as e: self._DoReadFile('323_capsule_accept_revert_missing.dts') + def test_assume_size(self): + """Test handling of the assume-size property for external blob""" + with self.assertRaises(ValueError) as e: + self._DoTestFile('326_assume_size.dts', allow_missing=True, + allow_fake_blobs=True) + self.assertIn("contents size 0xa (10) exceeds section size 0x9 (9)", + str(e.exception)) + + def test_assume_size_ok(self): + """Test handling of the assume-size where it fits OK""" + with test_util.capture_sys_output() as (stdout, stderr): + self._DoTestFile('327_assume_size_ok.dts', allow_missing=True, + allow_fake_blobs=True) + err = stderr.getvalue() + self.assertRegex( + err, + "Image '.*' has faked external blobs and is non-functional: .*") + + def test_assume_size_no_fake(self): + """Test handling of the assume-size where it fits OK""" + with test_util.capture_sys_output() as (stdout, stderr): + self._DoTestFile('327_assume_size_ok.dts', allow_missing=True) + err = stderr.getvalue() + self.assertRegex( + err, + "Image '.*' is missing external blobs and is non-functional: .*") + + if __name__ == "__main__": unittest.main() diff --git a/tools/binman/test/326_assume_size.dts b/tools/binman/test/326_assume_size.dts new file mode 100644 index 00000000000..4c5f8b418d8 --- /dev/null +++ b/tools/binman/test/326_assume_size.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + size = <9>; + blob-ext { + filename = "assume_blob"; + assume-size = <10>; + }; + }; +}; diff --git a/tools/binman/test/327_assume_size_ok.dts b/tools/binman/test/327_assume_size_ok.dts new file mode 100644 index 00000000000..00ed726f872 --- /dev/null +++ b/tools/binman/test/327_assume_size_ok.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + size = <10>; + blob-ext { + filename = "assume_blob"; + assume-size = <10>; + }; + }; +}; diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py index e225ac2ca0f..a7358cfc08a 100644 --- a/tools/buildman/bsettings.py +++ b/tools/buildman/bsettings.py @@ -29,7 +29,10 @@ def setup(fname=''): settings.read(config_fname) def add_file(data): - settings.readfp(io.StringIO(data)) + settings.read_file(io.StringIO(data)) + +def add_section(name): + settings.add_section(name) def get_items(section): """Get the items from a section of the config. diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index f35175b4598..c794177f2ba 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -255,15 +255,15 @@ class Builder: def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs, gnu_make='make', checkout=True, show_unknown=True, step=1, - no_subdirs=False, full_path=False, verbose_build=False, - mrproper=False, per_board_out_dir=False, - config_only=False, squash_config_y=False, - warnings_as_errors=False, work_in_output=False, - test_thread_exceptions=False, adjust_cfg=None, - allow_missing=False, no_lto=False, reproducible_builds=False, - force_build=False, force_build_failures=False, - force_reconfig=False, in_tree=False, - force_config_on_failure=False, make_func=None): + no_subdirs=False, verbose_build=False, + mrproper=False, fallback_mrproper=False, + per_board_out_dir=False, config_only=False, + squash_config_y=False, warnings_as_errors=False, + work_in_output=False, test_thread_exceptions=False, + adjust_cfg=None, allow_missing=False, no_lto=False, + reproducible_builds=False, force_build=False, + force_build_failures=False, force_reconfig=False, + in_tree=False, force_config_on_failure=False, make_func=None): """Create a new Builder object Args: @@ -279,10 +279,9 @@ class Builder: step: 1 to process every commit, n to process every nth commit no_subdirs: Don't create subdirectories when building current source for a single board - full_path: Return the full path in CROSS_COMPILE and don't set - PATH verbose_build: Run build with V=1 and don't use 'make -s' mrproper: Always run 'make mrproper' when configuring + fallback_mrproper: Run 'make mrproper' and retry on build failure per_board_out_dir: Build in a separate persistent directory per board rather than a thread-specific directory config_only: Only configure each build, don't build it @@ -336,7 +335,6 @@ class Builder: self._step = step self._error_lines = 0 self.no_subdirs = no_subdirs - self.full_path = full_path self.verbose_build = verbose_build self.config_only = config_only self.squash_config_y = squash_config_y @@ -352,6 +350,7 @@ class Builder: self.force_reconfig = force_reconfig self.in_tree = in_tree self.force_config_on_failure = force_config_on_failure + self.fallback_mrproper = fallback_mrproper if not self.squash_config_y: self.config_filenames += EXTRA_CONFIG_FILENAMES diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index a8599c0bb2a..4e085d6d675 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -240,7 +240,7 @@ class BuilderThread(threading.Thread): return args, cwd, src_dir def _reconfigure(self, commit, brd, cwd, args, env, config_args, config_out, - cmd_list): + cmd_list, mrproper): """Reconfigure the build Args: @@ -251,11 +251,12 @@ class BuilderThread(threading.Thread): env (dict): Environment strings config_args (list of str): defconfig arg for this board cmd_list (list of str): List to add the commands to, for logging + mrproper (bool): True to run mrproper first Returns: CommandResult object """ - if self.mrproper: + if mrproper: result = self.make(commit, brd, 'mrproper', cwd, 'mrproper', *args, env=env) config_out.write(result.combined) @@ -380,7 +381,7 @@ class BuilderThread(threading.Thread): commit = 'current' return commit - def _config_and_build(self, commit_upto, brd, work_dir, do_config, + def _config_and_build(self, commit_upto, brd, work_dir, do_config, mrproper, config_only, adjust_cfg, commit, out_dir, out_rel_dir, result): """Do the build, configuring first if necessary @@ -390,6 +391,7 @@ class BuilderThread(threading.Thread): brd (Board): Board to create arguments for work_dir (str): Directory to which the source will be checked out do_config (bool): True to run a make <board>_defconfig on the source + mrproper (bool): True to run mrproper first config_only (bool): Only configure the source, do not build it adjust_cfg (list of str): See the cfgutil module and run_commit() commit (Commit): Commit only being built @@ -404,7 +406,7 @@ class BuilderThread(threading.Thread): the next incremental build """ # Set up the environment and command line - env = self.toolchain.MakeEnvironment(self.builder.full_path) + env = self.toolchain.MakeEnvironment() mkdir(out_dir) args, cwd, src_dir = self._build_args(brd, out_dir, out_rel_dir, @@ -419,7 +421,8 @@ class BuilderThread(threading.Thread): cmd_list = [] if do_config or adjust_cfg: result = self._reconfigure( - commit, brd, cwd, args, env, config_args, config_out, cmd_list) + commit, brd, cwd, args, env, config_args, config_out, cmd_list, + mrproper) do_config = False # No need to configure next time if adjust_cfg: cfgutil.adjust_cfg_file(cfg_file, adjust_cfg) @@ -445,9 +448,9 @@ class BuilderThread(threading.Thread): result.cmd_list = cmd_list return result, do_config - def run_commit(self, commit_upto, brd, work_dir, do_config, config_only, - force_build, force_build_failures, work_in_output, - adjust_cfg): + def run_commit(self, commit_upto, brd, work_dir, do_config, mrproper, + config_only, force_build, force_build_failures, + work_in_output, adjust_cfg): """Build a particular commit. If the build is already done, and we are not forcing a build, we skip @@ -458,6 +461,7 @@ class BuilderThread(threading.Thread): brd (Board): Board to build work_dir (str): Directory to which the source will be checked out do_config (bool): True to run a make <board>_defconfig on the source + mrproper (bool): True to run mrproper first config_only (bool): Only configure the source, do not build it force_build (bool): Force a build even if one was previously done force_build_failures (bool): Force a bulid if the previous result @@ -498,8 +502,9 @@ class BuilderThread(threading.Thread): if self.toolchain: commit = self._checkout(commit_upto, work_dir) result, do_config = self._config_and_build( - commit_upto, brd, work_dir, do_config, config_only, - adjust_cfg, commit, out_dir, out_rel_dir, result) + commit_upto, brd, work_dir, do_config, mrproper, + config_only, adjust_cfg, commit, out_dir, out_rel_dir, + result) result.already_done = False result.toolchain = self.toolchain @@ -569,7 +574,7 @@ class BuilderThread(threading.Thread): outf.write(f'{result.return_code}') # Write out the image and function size information and an objdump - env = result.toolchain.MakeEnvironment(self.builder.full_path) + env = result.toolchain.MakeEnvironment() with open(os.path.join(build_dir, 'out-env'), 'wb') as outf: for var in sorted(env.keys()): outf.write(b'%s="%s"' % (var, env[var])) @@ -688,19 +693,22 @@ class BuilderThread(threading.Thread): force_build = False for commit_upto in range(0, len(job.commits), job.step): result, request_config = self.run_commit(commit_upto, brd, - work_dir, do_config, self.builder.config_only, + work_dir, do_config, self.mrproper, + self.builder.config_only, force_build or self.builder.force_build, self.builder.force_build_failures, job.work_in_output, job.adjust_cfg) failed = result.return_code or result.stderr did_config = do_config - if failed and not do_config: + if failed and not do_config and not self.mrproper: # If our incremental build failed, try building again # with a reconfig. if self.builder.force_config_on_failure: result, request_config = self.run_commit(commit_upto, - brd, work_dir, True, False, True, False, - job.work_in_output, job.adjust_cfg) + brd, work_dir, True, + self.mrproper or self.builder.fallback_mrproper, + False, True, False, job.work_in_output, + job.adjust_cfg) did_config = True if not self.builder.force_reconfig: do_config = request_config @@ -744,7 +752,7 @@ class BuilderThread(threading.Thread): else: # Just build the currently checked-out build result, request_config = self.run_commit(None, brd, work_dir, True, - self.builder.config_only, True, + self.mrproper, self.builder.config_only, True, self.builder.force_build_failures, job.work_in_output, job.adjust_cfg) result.commit_upto = 0 diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index aae2477b5c3..b8ff3bf1ab2 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -995,7 +995,8 @@ By default, buildman doesn't execute 'make mrproper' prior to building the first commit for each board. This reduces the amount of work 'make' does, and hence speeds up the build. To force use of 'make mrproper', use -the -m flag. This flag will slow down any buildman invocation, since it increases the amount -of work done on any build. +of work done on any build. An alternative is to use the --fallback-mrproper +flag, which retries the build with 'make mrproper' only after a build failure. One possible application of buildman is as part of a continual edit, build, edit, build, ... cycle; repeatedly applying buildman to the same change or @@ -1285,6 +1286,11 @@ then buildman hangs. Failing to handle any eventuality is a bug in buildman and should be reported. But you can use -T0 to disable threading and hopefully figure out the root cause of the build failure. +For situations where buildman is invoked from multiple running processes, it is +sometimes useful to have buildman wait until the others have finished. Use the +--process-limit option for this: --process-limit 1 will allow only one buildman +to process jobs at a time. + Build summary ------------- diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py index 03211bd5aa5..2673e749d58 100644 --- a/tools/buildman/cmdline.py +++ b/tools/buildman/cmdline.py @@ -90,7 +90,9 @@ def add_upto_m(parser): parser.add_argument('--list-tool-chains', action='store_true', default=False, help='List available tool chains (use -v to see probing detail)') parser.add_argument('-m', '--mrproper', action='store_true', - default=False, help="Run 'make mrproper before reconfiguring") + default=False, help="Run 'make mrproper' before reconfiguring") + parser.add_argument('--fallback-mrproper', action='store_true', + default=False, help="Run 'make mrproper' and retry on build failure") parser.add_argument( '-M', '--allow-missing', action='store_true', default=False, help='Tell binman to allow missing blobs and generate fake ones as needed') @@ -121,12 +123,12 @@ def add_after_m(parser): help="Override host toochain to use for sandbox (e.g. 'clang-7')") parser.add_argument('-Q', '--quick', action='store_true', default=False, help='Do a rough build, with limited warning resolution') - parser.add_argument('-p', '--full-path', action='store_true', - default=False, help="Use full toolchain path in CROSS_COMPILE") parser.add_argument('-P', '--per-board-out-dir', action='store_true', default=False, help="Use an O= (output) directory per board rather than per thread") parser.add_argument('--print-arch', action='store_true', default=False, help="Print the architecture for a board (ARCH=)") + parser.add_argument('--process-limit', type=int, + default=0, help='Limit to number of buildmans running at once') parser.add_argument('-r', '--reproducible-builds', action='store_true', help='Set SOURCE_DATE_EPOCH=0 to suuport a reproducible build') parser.add_argument('-R', '--regen-board-list', type=str, diff --git a/tools/buildman/control.py b/tools/buildman/control.py index 8f6850c5211..037854dfc07 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -7,10 +7,13 @@ This holds the main control logic for buildman, when not running tests. """ +import getpass import multiprocessing import os import shutil import sys +import tempfile +import time from buildman import boards from buildman import bsettings @@ -21,10 +24,23 @@ from patman import gitutil from patman import patchstream from u_boot_pylib import command from u_boot_pylib import terminal -from u_boot_pylib.terminal import tprint +from u_boot_pylib import tools +from u_boot_pylib.terminal import print_clear, tprint TEST_BUILDER = None +# Space-separated list of buildman process IDs currently running jobs +RUNNING_FNAME = f'buildmanq.{getpass.getuser()}' + +# Lock file for access to RUNNING_FILE +LOCK_FNAME = f'{RUNNING_FNAME}.lock' + +# Wait time for access to lock (seconds) +LOCK_WAIT_S = 10 + +# Wait time to start running +RUN_WAIT_S = 300 + def get_plural(count): """Returns a plural 's' if count is not 1""" return 's' if count != 1 else '' @@ -578,6 +594,125 @@ def calc_adjust_cfg(adjust_cfg, reproducible_builds): return adjust_cfg +def read_procs(tmpdir=tempfile.gettempdir()): + """Read the list of running buildman processes + + If the list is corrupted, returns an empty list + + Args: + tmpdir (str): Temporary directory to use (for testing only) + """ + running_fname = os.path.join(tmpdir, RUNNING_FNAME) + procs = [] + if os.path.exists(running_fname): + items = tools.read_file(running_fname, binary=False).split() + try: + procs = [int(x) for x in items] + except ValueError: # Handle invalid format + pass + return procs + + +def check_pid(pid): + """Check for existence of a unix PID + + https://stackoverflow.com/questions/568271/how-to-check-if-there-exists-a-process-with-a-given-pid-in-python + + Args: + pid (int): PID to check + + Returns: + True if it exists, else False + """ + try: + os.kill(pid, 0) + except OSError: + return False + else: + return True + + +def write_procs(procs, tmpdir=tempfile.gettempdir()): + """Write the list of running buildman processes + + Args: + tmpdir (str): Temporary directory to use (for testing only) + """ + running_fname = os.path.join(tmpdir, RUNNING_FNAME) + tools.write_file(running_fname, ' '.join([str(p) for p in procs]), + binary=False) + + # Allow another user to access the file + os.chmod(running_fname, 0o666) + +def wait_for_process_limit(limit, tmpdir=tempfile.gettempdir(), + pid=os.getpid()): + """Wait until the number of buildman processes drops to the limit + + This uses FileLock to protect a 'running' file, which contains a list of + PIDs of running buildman processes. The number of PIDs in the file indicates + the number of running processes. + + When buildman starts up, it calls this function to wait until it is OK to + start the build. + + On exit, no attempt is made to remove the PID from the file, since other + buildman processes will notice that the PID is no-longer valid, and ignore + it. + + Two timeouts are provided: + LOCK_WAIT_S: length of time to wait for the lock; if this occurs, the + lock is busted / removed before trying again + RUN_WAIT_S: length of time to wait to be allowed to run; if this occurs, + the build starts, with the PID being added to the file. + + Args: + limit (int): Maximum number of buildman processes, including this one; + must be > 0 + tmpdir (str): Temporary directory to use (for testing only) + pid (int): Current process ID (for testing only) + """ + from filelock import Timeout, FileLock + + running_fname = os.path.join(tmpdir, RUNNING_FNAME) + lock_fname = os.path.join(tmpdir, LOCK_FNAME) + lock = FileLock(lock_fname) + + # Allow another user to access the file + col = terminal.Color() + tprint('Waiting for other buildman processes...', newline=False, + colour=col.RED) + + claimed = False + deadline = time.time() + RUN_WAIT_S + while True: + try: + with lock.acquire(timeout=LOCK_WAIT_S): + os.chmod(lock_fname, 0o666) + procs = read_procs(tmpdir) + + # Drop PIDs which are not running + procs = list(filter(check_pid, procs)) + + # If we haven't hit the limit, add ourself + if len(procs) < limit: + tprint('done...', newline=False) + claimed = True + if time.time() >= deadline: + tprint('timeout...', newline=False) + claimed = True + if claimed: + write_procs(procs + [pid], tmpdir) + break + + except Timeout: + tprint('failed to get lock: busting...', newline=False) + os.remove(lock_fname) + + time.sleep(1) + tprint('starting build', newline=False) + print_clear() + def do_buildman(args, toolchains=None, make_func=None, brds=None, clean_dir=False, test_thread_exceptions=False): """The main control code for buildman @@ -653,9 +788,8 @@ def do_buildman(args, toolchains=None, make_func=None, brds=None, builder = Builder(toolchains, output_dir, git_dir, args.threads, args.jobs, checkout=True, show_unknown=args.show_unknown, step=args.step, - no_subdirs=args.no_subdirs, full_path=args.full_path, - verbose_build=args.verbose_build, - mrproper=args.mrproper, + no_subdirs=args.no_subdirs, verbose_build=args.verbose_build, + mrproper=args.mrproper, fallback_mrproper=args.fallback_mrproper, per_board_out_dir=args.per_board_out_dir, config_only=args.config_only, squash_config_y=not args.preserve_config_y, @@ -676,5 +810,8 @@ def do_buildman(args, toolchains=None, make_func=None, brds=None, TEST_BUILDER = builder + if args.process_limit: + wait_for_process_limit(args.process_limit) + return run_builder(builder, series.commits if series else None, brds.get_selected_dict(), args) diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py index 6b88ed815d6..0ac9fc7e44f 100644 --- a/tools/buildman/func_test.py +++ b/tools/buildman/func_test.py @@ -807,27 +807,27 @@ CONFIG_LOCALVERSION=y params, warnings = self._boards.scan_defconfigs(src, src) # We should get two boards - self.assertEquals(2, len(params)) + self.assertEqual(2, len(params)) self.assertFalse(warnings) first = 0 if params[0]['target'] == 'board0' else 1 board0 = params[first] board2 = params[1 - first] - self.assertEquals('arm', board0['arch']) - self.assertEquals('armv7', board0['cpu']) - self.assertEquals('-', board0['soc']) - self.assertEquals('Tester', board0['vendor']) - self.assertEquals('ARM Board 0', board0['board']) - self.assertEquals('config0', board0['config']) - self.assertEquals('board0', board0['target']) - - self.assertEquals('powerpc', board2['arch']) - self.assertEquals('ppc', board2['cpu']) - self.assertEquals('mpc85xx', board2['soc']) - self.assertEquals('Tester', board2['vendor']) - self.assertEquals('PowerPC board 1', board2['board']) - self.assertEquals('config2', board2['config']) - self.assertEquals('board2', board2['target']) + self.assertEqual('arm', board0['arch']) + self.assertEqual('armv7', board0['cpu']) + self.assertEqual('-', board0['soc']) + self.assertEqual('Tester', board0['vendor']) + self.assertEqual('ARM Board 0', board0['board']) + self.assertEqual('config0', board0['config']) + self.assertEqual('board0', board0['target']) + + self.assertEqual('powerpc', board2['arch']) + self.assertEqual('ppc', board2['cpu']) + self.assertEqual('mpc85xx', board2['soc']) + self.assertEqual('Tester', board2['vendor']) + self.assertEqual('PowerPC board 1', board2['board']) + self.assertEqual('config2', board2['config']) + self.assertEqual('board2', board2['target']) def test_output_is_new(self): """Test detecting new changes to Kconfig""" @@ -898,7 +898,7 @@ Active aarch64 armv8 - armltd total_compute board2 params_list, warnings = self._boards.build_board_list(config_dir, src) # There should be two boards no warnings - self.assertEquals(2, len(params_list)) + self.assertEqual(2, len(params_list)) self.assertFalse(warnings) # Set an invalid status line in the file @@ -907,12 +907,12 @@ Active aarch64 armv8 - armltd total_compute board2 for line in orig_data.splitlines(keepends=True)] tools.write_file(main, ''.join(lines), binary=False) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) + self.assertEqual(2, len(params_list)) params = params_list[0] if params['target'] == 'board2': params = params_list[1] - self.assertEquals('-', params['status']) - self.assertEquals(["WARNING: Other: unknown status for 'board0'"], + self.assertEqual('-', params['status']) + self.assertEqual(["WARNING: Other: unknown status for 'board0'"], warnings) # Remove the status line (S:) from a file @@ -920,39 +920,39 @@ Active aarch64 armv8 - armltd total_compute board2 if not line.startswith('S:')] tools.write_file(main, ''.join(lines), binary=False) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) - self.assertEquals(["WARNING: -: unknown status for 'board0'"], warnings) + self.assertEqual(2, len(params_list)) + self.assertEqual(["WARNING: -: unknown status for 'board0'"], warnings) # Remove the configs/ line (F:) from a file - this is the last line data = ''.join(orig_data.splitlines(keepends=True)[:-1]) tools.write_file(main, data, binary=False) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) - self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings) + self.assertEqual(2, len(params_list)) + self.assertEqual(["WARNING: no maintainers for 'board0'"], warnings) # Mark a board as orphaned - this should give a warning lines = ['S: Orphaned' if line.startswith('S') else line for line in orig_data.splitlines(keepends=True)] tools.write_file(main, ''.join(lines), binary=False) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) - self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings) + self.assertEqual(2, len(params_list)) + self.assertEqual(["WARNING: no maintainers for 'board0'"], warnings) # Change the maintainer to '-' - this should give a warning lines = ['M: -' if line.startswith('M') else line for line in orig_data.splitlines(keepends=True)] tools.write_file(main, ''.join(lines), binary=False) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) - self.assertEquals(["WARNING: -: unknown status for 'board0'"], warnings) + self.assertEqual(2, len(params_list)) + self.assertEqual(["WARNING: -: unknown status for 'board0'"], warnings) # Remove the maintainer line (M:) from a file lines = [line for line in orig_data.splitlines(keepends=True) if not line.startswith('M:')] tools.write_file(main, ''.join(lines), binary=False) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) - self.assertEquals(["WARNING: no maintainers for 'board0'"], warnings) + self.assertEqual(2, len(params_list)) + self.assertEqual(["WARNING: no maintainers for 'board0'"], warnings) # Move the contents of the second file into this one, removing the # second file, to check multiple records in a single file. @@ -960,14 +960,14 @@ Active aarch64 armv8 - armltd total_compute board2 tools.write_file(main, both_data, binary=False) os.remove(other) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) + self.assertEqual(2, len(params_list)) self.assertFalse(warnings) # Add another record, this should be ignored with a warning extra = '\n\nAnother\nM: Fred\nF: configs/board9_defconfig\nS: other\n' tools.write_file(main, both_data + extra, binary=False) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) + self.assertEqual(2, len(params_list)) self.assertFalse(warnings) # Add another TARGET to the Kconfig @@ -983,8 +983,8 @@ endif tools.write_file(kc_file, orig_kc_data + extra) params_list, warnings = self._boards.build_board_list(config_dir, src, warn_targets=True) - self.assertEquals(2, len(params_list)) - self.assertEquals( + self.assertEqual(2, len(params_list)) + self.assertEqual( ['WARNING: board2_defconfig: Duplicate TARGET_xxx: board2 and other'], warnings) @@ -994,8 +994,8 @@ endif tools.write_file(kc_file, b''.join(lines)) params_list, warnings = self._boards.build_board_list(config_dir, src, warn_targets=True) - self.assertEquals(2, len(params_list)) - self.assertEquals( + self.assertEqual(2, len(params_list)) + self.assertEqual( ['WARNING: board2_defconfig: No TARGET_BOARD2 enabled'], warnings) tools.write_file(kc_file, orig_kc_data) @@ -1004,7 +1004,7 @@ endif data = ''.join(both_data.splitlines(keepends=True)[:-1]) tools.write_file(main, data + 'N: oa.*2\n', binary=False) params_list, warnings = self._boards.build_board_list(config_dir, src) - self.assertEquals(2, len(params_list)) + self.assertEqual(2, len(params_list)) self.assertFalse(warnings) def testRegenBoards(self): diff --git a/tools/buildman/pyproject.toml b/tools/buildman/pyproject.toml index fe0f6421b53..68bfa45c3f4 100644 --- a/tools/buildman/pyproject.toml +++ b/tools/buildman/pyproject.toml @@ -8,7 +8,11 @@ version = "0.0.6" authors = [ { name="Simon Glass", email="sjg@chromium.org" }, ] -dependencies = ["u_boot_pylib >= 0.0.6", "patch-manager >= 0.0.6"] +dependencies = [ + "filelock >= 3.0.12", + "u_boot_pylib >= 0.0.6", + "patch-manager >= 0.0.6" +] description = "Buildman build tool for U-Boot" readme = "README.rst" requires-python = ">=3.7" diff --git a/tools/buildman/requirements.txt b/tools/buildman/requirements.txt index 4a31e69e4cb..052d0ed5c6f 100644 --- a/tools/buildman/requirements.txt +++ b/tools/buildman/requirements.txt @@ -1,3 +1,5 @@ +coverage==6.2 jsonschema==4.17.3 +pycryptodome==3.20 pyyaml==6.0 yamllint==1.26.3 diff --git a/tools/buildman/test.py b/tools/buildman/test.py index f92add7a7c5..ac0a7ab06d6 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -2,12 +2,14 @@ # Copyright (c) 2012 The Chromium OS Authors. # +from filelock import FileLock import os import shutil import sys import tempfile import time import unittest +from unittest.mock import patch from buildman import board from buildman import boards @@ -146,6 +148,7 @@ class TestBuild(unittest.TestCase): self.toolchains.Add('arm-linux-gcc', test=False) self.toolchains.Add('sparc-linux-gcc', test=False) self.toolchains.Add('powerpc-linux-gcc', test=False) + self.toolchains.Add('/path/to/aarch64-linux-gcc', test=False) self.toolchains.Add('gcc', test=False) # Avoid sending any output @@ -156,6 +159,11 @@ class TestBuild(unittest.TestCase): if not os.path.isdir(self.base_dir): os.mkdir(self.base_dir) + self.cur_time = 0 + self.valid_pids = [] + self.finish_time = None + self.finish_pid = None + def tearDown(self): shutil.rmtree(self.base_dir) @@ -584,7 +592,7 @@ class TestBuild(unittest.TestCase): if use_network: with test_util.capture_sys_output() as (stdout, stderr): url = self.toolchains.LocateArchUrl('arm') - self.assertRegexpMatches(url, 'https://www.kernel.org/pub/tools/' + self.assertRegex(url, 'https://www.kernel.org/pub/tools/' 'crosstool/files/bin/x86_64/.*/' 'x86_64-gcc-.*-nolibc[-_]arm-.*linux-gnueabi.tar.xz') @@ -747,6 +755,194 @@ class TestBuild(unittest.TestCase): self.assertEqual([ ['MARY="mary"', 'Missing expected line: CONFIG_MARY="mary"']], result) + def get_procs(self): + running_fname = os.path.join(self.base_dir, control.RUNNING_FNAME) + items = tools.read_file(running_fname, binary=False).split() + return [int(x) for x in items] + + def get_time(self): + return self.cur_time + + def inc_time(self, amount): + self.cur_time += amount + + # Handle a process exiting + if self.finish_time == self.cur_time: + self.valid_pids = [pid for pid in self.valid_pids + if pid != self.finish_pid] + + def kill(self, pid, signal): + if pid not in self.valid_pids: + raise OSError('Invalid PID') + + def test_process_limit(self): + """Test wait_for_process_limit() function""" + tmpdir = self.base_dir + + with (patch('time.time', side_effect=self.get_time), + patch('time.sleep', side_effect=self.inc_time), + patch('os.kill', side_effect=self.kill)): + # Grab the process. Since there is no other profcess, this should + # immediately succeed + control.wait_for_process_limit(1, tmpdir=tmpdir, pid=1) + lines = terminal.get_print_test_lines() + self.assertEqual(0, self.cur_time) + self.assertEqual('Waiting for other buildman processes...', + lines[0].text) + self.assertEqual(self._col.RED, lines[0].colour) + self.assertEqual(False, lines[0].newline) + self.assertEqual(True, lines[0].bright) + + self.assertEqual('done...', lines[1].text) + self.assertEqual(None, lines[1].colour) + self.assertEqual(False, lines[1].newline) + self.assertEqual(True, lines[1].bright) + + self.assertEqual('starting build', lines[2].text) + self.assertEqual([1], control.read_procs(tmpdir)) + self.assertEqual(None, lines[2].colour) + self.assertEqual(False, lines[2].newline) + self.assertEqual(True, lines[2].bright) + + # Try again, with a different PID...this should eventually timeout + # and start the build anyway + self.cur_time = 0 + self.valid_pids = [1] + control.wait_for_process_limit(1, tmpdir=tmpdir, pid=2) + lines = terminal.get_print_test_lines() + self.assertEqual('Waiting for other buildman processes...', + lines[0].text) + self.assertEqual('timeout...', lines[1].text) + self.assertEqual(None, lines[1].colour) + self.assertEqual(False, lines[1].newline) + self.assertEqual(True, lines[1].bright) + self.assertEqual('starting build', lines[2].text) + self.assertEqual([1, 2], control.read_procs(tmpdir)) + self.assertEqual(control.RUN_WAIT_S, self.cur_time) + + # Check lock-busting + self.cur_time = 0 + self.valid_pids = [1, 2] + lock_fname = os.path.join(tmpdir, control.LOCK_FNAME) + lock = FileLock(lock_fname) + lock.acquire(timeout=1) + control.wait_for_process_limit(1, tmpdir=tmpdir, pid=3) + lines = terminal.get_print_test_lines() + self.assertEqual('Waiting for other buildman processes...', + lines[0].text) + self.assertEqual('failed to get lock: busting...', lines[1].text) + self.assertEqual(None, lines[1].colour) + self.assertEqual(False, lines[1].newline) + self.assertEqual(True, lines[1].bright) + self.assertEqual('timeout...', lines[2].text) + self.assertEqual('starting build', lines[3].text) + self.assertEqual([1, 2, 3], control.read_procs(tmpdir)) + self.assertEqual(control.RUN_WAIT_S, self.cur_time) + lock.release() + + # Check handling of dead processes. Here we have PID 2 as a running + # process, even though the PID file contains 1, 2 and 3. So we can + # add one more PID, to make 2 and 4 + self.cur_time = 0 + self.valid_pids = [2] + control.wait_for_process_limit(2, tmpdir=tmpdir, pid=4) + lines = terminal.get_print_test_lines() + self.assertEqual('Waiting for other buildman processes...', + lines[0].text) + self.assertEqual('done...', lines[1].text) + self.assertEqual('starting build', lines[2].text) + self.assertEqual([2, 4], control.read_procs(tmpdir)) + self.assertEqual(0, self.cur_time) + + # Try again, with PID 2 quitting at time 50. This allows the new + # build to start + self.cur_time = 0 + self.valid_pids = [2, 4] + self.finish_pid = 2 + self.finish_time = 50 + control.wait_for_process_limit(2, tmpdir=tmpdir, pid=5) + lines = terminal.get_print_test_lines() + self.assertEqual('Waiting for other buildman processes...', + lines[0].text) + self.assertEqual('done...', lines[1].text) + self.assertEqual('starting build', lines[2].text) + self.assertEqual([4, 5], control.read_procs(tmpdir)) + self.assertEqual(self.finish_time, self.cur_time) + + def call_make_environment(self, tchn, in_env=None): + """Call Toolchain.MakeEnvironment() and process the result + + Args: + tchn (Toolchain): Toolchain to use + in_env (dict): Input environment to use, None to use current env + + Returns: + tuple: + dict: Changes that MakeEnvironment has made to the environment + key: Environment variable that was changed + value: New value (for PATH this only includes components + which were added) + str: Full value of the new PATH variable + """ + env = tchn.MakeEnvironment(env=in_env) + + # Get the original environment + orig_env = dict(os.environb if in_env is None else in_env) + orig_path = orig_env[b'PATH'].split(b':') + + # Find new variables + diff = dict((k, env[k]) for k in env if orig_env.get(k) != env[k]) + + # Find new / different path components + diff_path = None + new_path = None + if b'PATH' in diff: + new_path = diff[b'PATH'].split(b':') + diff_paths = [p for p in new_path if p not in orig_path] + diff_path = b':'.join(p for p in new_path if p not in orig_path) + if diff_path: + diff[b'PATH'] = diff_path + else: + del diff[b'PATH'] + return diff, new_path + + def test_toolchain_env(self): + """Test PATH and other environment settings for toolchains""" + # Use a toolchain which has a path + tchn = self.toolchains.Select('aarch64') + + # Normal case + diff = self.call_make_environment(tchn)[0] + self.assertEqual( + {b'CROSS_COMPILE': b'/path/to/aarch64-linux-', b'LC_ALL': b'C'}, + diff) + + # When overriding the toolchain, only LC_ALL should be set + tchn.override_toolchain = True + diff = self.call_make_environment(tchn)[0] + self.assertEqual({b'LC_ALL': b'C'}, diff) + + # Test that virtualenv is handled correctly + tchn.override_toolchain = False + sys.prefix = '/some/venv' + env = dict(os.environb) + env[b'PATH'] = b'/some/venv/bin:other/things' + tchn.path = '/my/path' + diff, diff_path = self.call_make_environment(tchn, env) + + self.assertNotIn(b'PATH', diff) + self.assertEqual(None, diff_path) + self.assertEqual( + {b'CROSS_COMPILE': b'/my/path/aarch64-linux-', b'LC_ALL': b'C'}, + diff) + + # Handle a toolchain wrapper + tchn.path = '' + bsettings.add_section('toolchain-wrapper') + bsettings.set_item('toolchain-wrapper', 'my-wrapper', 'fred') + diff = self.call_make_environment(tchn)[0] + self.assertEqual( + {b'CROSS_COMPILE': b'fred aarch64-linux-', b'LC_ALL': b'C'}, diff) if __name__ == "__main__": unittest.main() diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 79c7c11a110..739acf3ec53 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -90,7 +90,7 @@ class Toolchain: if self.arch == 'sandbox' and override_toolchain: self.gcc = override_toolchain - env = self.MakeEnvironment(False) + env = self.MakeEnvironment() # As a basic sanity check, run the C compiler with --version cmd = [fname, '--version'] @@ -172,12 +172,12 @@ class Toolchain: else: raise ValueError('Unknown arg to GetEnvArgs (%d)' % which) - def MakeEnvironment(self, full_path): + def MakeEnvironment(self, env=None): """Returns an environment for using the toolchain. - Thie takes the current environment and adds CROSS_COMPILE so that + This takes the current environment and adds CROSS_COMPILE so that the tool chain will operate correctly. This also disables localized - output and possibly unicode encoded output of all build tools by + output and possibly Unicode encoded output of all build tools by adding LC_ALL=C. Note that os.environb is used to obtain the environment, since in some @@ -188,25 +188,23 @@ class Toolchain: 569-570: surrogates not allowed Args: - full_path: Return the full path in CROSS_COMPILE and don't set - PATH + env (dict of bytes): Original environment, used for testing + Returns: Dict containing the (bytes) environment to use. This is based on the - current environment, with changes as needed to CROSS_COMPILE, PATH - and LC_ALL. + current environment, with changes as needed to CROSS_COMPILE and + LC_ALL. """ - env = dict(os.environb) + env = dict(env or os.environb) + wrapper = self.GetWrapper() if self.override_toolchain: # We'll use MakeArgs() to provide this pass - elif full_path: + else: env[b'CROSS_COMPILE'] = tools.to_bytes( wrapper + os.path.join(self.path, self.cross)) - else: - env[b'CROSS_COMPILE'] = tools.to_bytes(wrapper + self.cross) - env[b'PATH'] = tools.to_bytes(self.path) + b':' + env[b'PATH'] env[b'LC_ALL'] = b'C' diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py index e3918497cf4..af6c025a441 100644 --- a/tools/patman/func_test.py +++ b/tools/patman/func_test.py @@ -211,6 +211,7 @@ class TestFunctional(unittest.TestCase): 'u-boot': ['u-boot@lists.denx.de'], 'simon': [self.leb], 'fred': [self.fred], + 'joe': [self.joe], } text = self._get_text('test01.txt') @@ -259,6 +260,7 @@ class TestFunctional(unittest.TestCase): self.assertEqual('Postfix:\t some-branch', next(lines)) self.assertEqual('Cover: 4 lines', next(lines)) self.assertEqual(' Cc: %s' % self.fred, next(lines)) + self.assertEqual(' Cc: %s' % self.joe, next(lines)) self.assertEqual(' Cc: %s' % self.leb, next(lines)) self.assertEqual(' Cc: %s' % mel, next(lines)) @@ -272,7 +274,8 @@ class TestFunctional(unittest.TestCase): self.assertEqual(('%s %s\0%s' % (args[0], rick, stefan)), cc_lines[0]) self.assertEqual( - '%s %s\0%s\0%s\0%s' % (args[1], self.fred, self.leb, rick, stefan), + '%s %s\0%s\0%s\0%s\0%s' % (args[1], self.fred, self.joe, self.leb, + rick, stefan), cc_lines[1]) expected = ''' @@ -290,6 +293,7 @@ Changes in v4: change - Some changes - Some notes for the cover letter +- fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() Simon Glass (2): pci: Correct cast for sandbox @@ -339,6 +343,7 @@ Changes in v4: - Multi line change +- New - Some changes Changes in v2: @@ -540,7 +545,8 @@ complicated as possible''') with open('.patman', 'w', buffering=1) as f: f.write('[settings]\n' 'get_maintainer_script: dummy-script.sh\n' - 'check_patch: False\n') + 'check_patch: False\n' + 'add_maintainers: True\n') with open('dummy-script.sh', 'w', buffering=1) as f: f.write('#!/usr/bin/env python\n' 'print("hello@there.com")\n') diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index e2e2a83e677..a09ae9c7371 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -475,6 +475,13 @@ class PatchStream: elif name == 'changes': self.in_change = 'Commit' self.change_version = self._parse_version(value, line) + elif name == 'cc': + self.commit.add_cc(value.split(',')) + elif name == 'added-in': + version = self._parse_version(value, line) + self.commit.add_change(version, '- New') + self.series.AddChange(version, None, '- %s' % + self.commit.subject) else: self._add_warn('Line %d: Ignoring Commit-%s' % (self.linenum, name)) diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst index f4588c00fc1..63b95a6b161 100644 --- a/tools/patman/patman.rst +++ b/tools/patman/patman.rst @@ -350,7 +350,20 @@ Cover-changes: n - This line will only appear in the cover letter <blank line> -Patch-cc: Their Name <email> +Commit-added-in: n + Add a change noting the version this commit was added in. This is + equivalent to:: + + Commit-changes: n + - New + + Cover-changes: n + - <commit subject> + + It is a convenient shorthand for suppressing the '(no changes in vN)' + message. + +Patch-cc / Commit-cc: Their Name <email> This copies a single patch to another email address. Note that the Cc: used by git send-email is ignored by patman, but will be interpreted by git send-email if you use it. diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 636983e32da..68c93e313b3 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -59,25 +59,25 @@ class _ProjectConfigParser(ConfigParser.ConfigParser): # Check to make sure that bogus project gets general alias. >>> config = _ProjectConfigParser("zzz") - >>> config.readfp(StringIO(sample_config)) + >>> config.read_file(StringIO(sample_config)) >>> str(config.get("alias", "enemies")) 'Evil <evil@example.com>' # Check to make sure that alias gets overridden by project. >>> config = _ProjectConfigParser("sm") - >>> config.readfp(StringIO(sample_config)) + >>> config.read_file(StringIO(sample_config)) >>> str(config.get("alias", "enemies")) 'Green G. <ugly@example.com>' # Check to make sure that settings get merged with project. >>> config = _ProjectConfigParser("linux") - >>> config.readfp(StringIO(sample_config)) + >>> config.read_file(StringIO(sample_config)) >>> sorted((str(a), str(b)) for (a, b) in config.items("settings")) [('am_hero', 'True'), ('check_patch_use_tree', 'True'), ('process_tags', 'False')] # Check to make sure that settings works with unknown project. >>> config = _ProjectConfigParser("unknown") - >>> config.readfp(StringIO(sample_config)) + >>> config.read_file(StringIO(sample_config)) >>> sorted((str(a), str(b)) for (a, b) in config.items("settings")) [('am_hero', 'True')] """ diff --git a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch index 56278a6ce9b..48ea1793b47 100644 --- a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch +++ b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch @@ -21,7 +21,9 @@ Series-cc: Stefan Brüns <stefan.bruens@rwth-aachen.de> Cover-letter-cc: Lord Mëlchett <clergy@palace.gov> Series-version: 3 Patch-cc: fred +Commit-cc: joe Series-process-log: sort, uniq +Commit-added-in: 4 Series-changes: 4 - Some changes - Multi diff --git a/tools/patman/test/test01.txt b/tools/patman/test/test01.txt index fc3066e50b4..b2d73c5972c 100644 --- a/tools/patman/test/test01.txt +++ b/tools/patman/test/test01.txt @@ -49,7 +49,9 @@ Date: Sat Apr 15 15:39:08 2017 -0600 Cover-letter-cc: Lord Mëlchett <clergy@palace.gov> Series-version: 3 Patch-cc: fred + Commit-cc: joe Series-process-log: sort, uniq + Commit-added-in: 4 Series-changes: 4 - Some changes - Multi diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 12c27b34eaa..3e52236b15a 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -470,7 +470,7 @@ int rkcommon_verify_header(unsigned char *buf, int size, * If no 'imagename' is specified via the commandline (e.g. if this is * 'dumpimage -l' w/o any further constraints), we accept any spl_info. */ - if (params->imagename == NULL) + if (params->imagename == NULL || !strlen(params->imagename)) return 0; /* Match the 'imagename' against the 'spl_hdr' found */ diff --git a/tools/u_boot_pylib/terminal.py b/tools/u_boot_pylib/terminal.py index 40d79f8ac07..2cd5a54ab52 100644 --- a/tools/u_boot_pylib/terminal.py +++ b/tools/u_boot_pylib/terminal.py @@ -164,8 +164,11 @@ def print_clear(): global last_print_len if last_print_len: - print('\r%s\r' % (' '* last_print_len), end='', flush=True) - last_print_len = None + if print_test_mode: + print_test_list.append(PrintLine(None, None, None, None)) + else: + print('\r%s\r' % (' '* last_print_len), end='', flush=True) + last_print_len = None def set_print_test_mode(enable=True): """Go into test mode, where all printing is recorded""" diff --git a/tools/u_boot_pylib/test_util.py b/tools/u_boot_pylib/test_util.py index f18d385d995..857ce58c98c 100644 --- a/tools/u_boot_pylib/test_util.py +++ b/tools/u_boot_pylib/test_util.py @@ -60,12 +60,17 @@ def run_test_coverage(prog, filter_fname, exclude_list, build_dir, required=None prefix = '' if build_dir: prefix = 'PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools ' % build_dir - cmd = ('%spython3-coverage run ' - '--omit "%s" %s %s %s %s' % (prefix, ','.join(glob_list), + + # Detect a Python virtualenv and use 'coverage' instead + covtool = ('python3-coverage' if sys.prefix == sys.base_prefix else + 'coverage') + + cmd = ('%s%s run ' + '--omit "%s" %s %s %s %s' % (prefix, covtool, ','.join(glob_list), prog, extra_args or '', test_cmd, single_thread or '-P1')) os.system(cmd) - stdout = command.output('python3-coverage', 'report') + stdout = command.output(covtool, 'report') lines = stdout.splitlines() if required: # Convert '/path/to/name.py' just the module name 'name' |