diff options
Diffstat (limited to 'arch/arm/cpu/arm926ejs/davinci')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/cpu.c | 22 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 26 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c | 16 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/psc.c | 5 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/reset.S | 81 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/reset.c | 33 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/spl.c | 20 |
8 files changed, 102 insertions, 105 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index da7efac0853..c91928e71d2 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o +COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o @@ -42,8 +42,6 @@ COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o endif -SOBJS = reset.o - ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 6cb857aef52..b31add8deb0 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -117,6 +117,17 @@ int clk_get(enum davinci_clk_ids id) out: return pll_out; } + +int set_cpu_clk_info(void) +{ + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); + gd->bd->bi_dsp_freq = 0; + return 0; +} + #else /* CONFIG_SOC_DA8XX */ static unsigned pll_div(volatile void *pllbase, unsigned offset) @@ -187,16 +198,9 @@ unsigned int davinci_clk_get(unsigned int div) return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; } #endif -#endif /* !CONFIG_SOC_DA8XX */ int set_cpu_clk_info(void) { -#ifdef CONFIG_SOC_DA8XX - gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; - /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; -#else - unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; #if defined(CONFIG_SOC_DM365) pllbase = DAVINCI_PLL_CNTRL1_BASE; @@ -215,10 +219,12 @@ int set_cpu_clk_info(void) pllbase = DAVINCI_PLL_CNTRL0_BASE; #endif gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; -#endif + return 0; } +#endif /* !CONFIG_SOC_DA8XX */ + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index df7d6a24ba2..ff2e2e33dff 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -190,13 +190,21 @@ int da850_ddr_setup(void) setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); - - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); } - + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - clrbits_le32(&davinci_syscfg1_regs->ddr_slew, - (1 << DDR_SLEW_CMOSEN_BIT)); + + if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { + /* DDR2 */ + clrbits_le32(&davinci_syscfg1_regs->ddr_slew, + (1 << DDR_SLEW_DDR_PDENA_BIT) | + (1 << DDR_SLEW_CMOSEN_BIT)); + } else { + /* MOBILE DDR */ + setbits_le32(&davinci_syscfg1_regs->ddr_slew, + (1 << DDR_SLEW_DDR_PDENA_BIT) | + (1 << DDR_SLEW_CMOSEN_BIT)); + } /* * SDRAM Configuration Register (SDCR): @@ -216,7 +224,11 @@ int da850_ddr_setup(void) writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); /* write memory configuration and timing */ - writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); + if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { + /* MOBILE DDR only*/ + writel(CONFIG_SYS_DA850_DDR2_SDBCR2, + &dv_ddr2_regs_ctrl->sdbcr2); + } writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); @@ -240,7 +252,7 @@ int da850_ddr_setup(void) /* disable self refresh */ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, - DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN); + DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); return 0; diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c index fa07fb591fb..133265e5b0e 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c @@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = { }; /* UART pin muxer settings */ +const struct pinmux_config uart0_pins_txrx[] = { + { pinmux(3), 2, 4 }, /* UART0_RXD */ + { pinmux(3), 2, 5 }, /* UART0_TXD */ +}; + const struct pinmux_config uart1_pins_txrx[] = { { pinmux(4), 2, 6 }, /* UART1_RXD */ { pinmux(4), 2, 7 }, /* UART1_TXD */ @@ -169,3 +174,14 @@ const struct pinmux_config emifa_pins_nor[] = { { pinmux(12), 1, 6 }, /* EMA_A[1] */ { pinmux(12), 1, 7 }, /* EMA_A[0] */ }; + +/* MMC0 pin muxer settings */ +const struct pinmux_config mmc0_pins[] = { + { pinmux(10), 2, 0 }, /* MMCSD0_CLK */ + { pinmux(10), 2, 1 }, /* MMCSD0_CMD */ + { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */ + { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */ + { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */ + { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */ + /* DA850 supports only 4-bit mode, remaining pins are not configured */ +}; diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c index 3e925181ea2..2ffb42abca2 100644 --- a/arch/arm/cpu/arm926ejs/davinci/psc.c +++ b/arch/arm/cpu/arm926ejs/davinci/psc.c @@ -128,6 +128,11 @@ void lpsc_syncreset(unsigned int id) lpsc_transition(id, 0x01); } +void lpsc_disable(unsigned int id) +{ + lpsc_transition(id, 0x0); +} + /* Not all DaVinci chips have a DSP power domain. */ #ifdef CONFIG_SOC_DM644X diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.S b/arch/arm/cpu/arm926ejs/davinci/reset.S deleted file mode 100644 index ba0a7c3b4ba..00000000000 --- a/arch/arm/cpu/arm926ejs/davinci/reset.S +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Processor reset using WDT for TI TMS320DM644x SoC. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * ----------------------------------------------------- - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -.globl reset_cpu -reset_cpu: - ldr r0, WDT_TGCR - mov r1, $0x08 - str r1, [r0] - ldr r1, [r0] - orr r1, r1, $0x03 - str r1, [r0] - mov r1, $0 - ldr r0, WDT_TIM12 - str r1, [r0] - ldr r0, WDT_TIM34 - str r1, [r0] - ldr r0, WDT_PRD12 - str r1, [r0] - ldr r0, WDT_PRD34 - str r1, [r0] - ldr r0, WDT_TCR - ldr r1, [r0] - orr r1, r1, $0x40 - str r1, [r0] - ldr r0, WDT_WDTCR - ldr r1, [r0] - orr r1, r1, $0x4000 - str r1, [r0] - ldr r1, WDTCR_VAL1 - str r1, [r0] - ldr r1, WDTCR_VAL2 - str r1, [r0] - /* Write an invalid value to the WDKEY field to trigger - * an immediate watchdog reset */ - mov r1, $0x4000 - str r1, [r0] - nop - nop - nop - nop -reset_cpu_loop: - b reset_cpu_loop - -WDT_TGCR: - .word 0x01c21c24 -WDT_TIM12: - .word 0x01c21c10 -WDT_TIM34: - .word 0x01c21c14 -WDT_PRD12: - .word 0x01c21c18 -WDT_PRD34: - .word 0x01c21c1c -WDT_TCR: - .word 0x01c21c20 -WDT_WDTCR: - .word 0x01c21c28 -WDTCR_VAL1: - .word 0xa5c64000 -WDTCR_VAL2: - .word 0xda7e4000 diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/cpu/arm926ejs/davinci/reset.c new file mode 100644 index 00000000000..968fb035c89 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/reset.c @@ -0,0 +1,33 @@ +/* + * Processor reset using WDT. + * + * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer_defs.h> +#include <asm/arch/hardware.h> + +void reset_cpu(unsigned long a) +{ + struct davinci_timer *const wdttimer = + (struct davinci_timer *)DAVINCI_TIMER1_BASE; + writel(0x08, &wdttimer->tgcr); + writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr); + writel(0, &wdttimer->tim12); + writel(0, &wdttimer->tim34); + writel(0, &wdttimer->prd12); + writel(0, &wdttimer->prd34); + writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr); + writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr); + writel(0xa5c64000, &wdttimer->wdtcr); + writel(0xda7e4000, &wdttimer->wdtcr); + writel(0x4000, &wdttimer->wdtcr); + while (1) + /*nothing*/; +} diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c index 74632e51619..03c85c87fba 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -28,6 +28,7 @@ #include <ns16550.h> #include <malloc.h> #include <spi_flash.h> +#include <mmc.h> #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT @@ -74,12 +75,7 @@ void board_init_f(ulong dummy) void board_init_r(gd_t *id, ulong dummy) { -#ifdef CONFIG_SPL_NAND_LOAD - nand_init(); - puts("Nand boot...\n"); - nand_boot(); -#endif -#ifdef CONFIG_SPL_SPI_LOAD +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); @@ -90,7 +86,19 @@ void board_init_r(gd_t *id, ulong dummy) serial_init(); /* serial communications setup */ gd->have_console = 1; +#endif + +#ifdef CONFIG_SPL_NAND_LOAD + nand_init(); + puts("Nand boot...\n"); + nand_boot(); +#endif +#ifdef CONFIG_SPL_SPI_LOAD puts("SPI boot...\n"); spi_boot(); #endif +#ifdef CONFIG_SPL_MMC_LOAD + puts("MMC boot...\n"); + spl_mmc_load(); +#endif } |