diff options
Diffstat (limited to 'arch/arm/cpu/armv7/exynos/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/soc.c | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index 68eb8e7fc9..0f116b141a 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -9,15 +9,6 @@ #include <asm/io.h> #include <asm/system.h> -enum l2_cache_params { - CACHE_TAG_RAM_SETUP = (1 << 9), - CACHE_DATA_RAM_SETUP = (1 << 5), - CACHE_TAG_RAM_LATENCY = (2 << 6), - CACHE_DATA_RAM_LATENCY = (2 << 0), - CACHE_ENABLE_CLEAN_EVICT = (0 << 3), - CACHE_DISABLE_CLEAN_EVICT = (1 << 3) -}; - void reset_cpu(ulong addr) { writel(0x1, samsung_get_base_swreset()); @@ -30,47 +21,3 @@ void enable_caches(void) dcache_enable(); } #endif - -#ifndef CONFIG_SYS_L2CACHE_OFF -/* - * Set L2 cache parameters - */ -static void exynos5_set_l2cache_params(void) -{ - unsigned int l2ctlr = 0, l2actlr = 0; - - /* Read L2CTLR value */ - asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(l2ctlr)); - - /* Set cache latency cycles */ - l2ctlr |= CACHE_TAG_RAM_LATENCY | - CACHE_DATA_RAM_LATENCY; - - if (proid_is_exynos5420() || proid_is_exynos5800()) { - /* Read L2ACTLR value */ - asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (l2actlr)); - - /* Disable clean/evict push to external */ - l2actlr |= CACHE_DISABLE_CLEAN_EVICT; - - /* Write new vlaue to L2ACTLR */ - asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (l2actlr)); - } else { - /* Set cache setup cycles */ - l2ctlr |= CACHE_TAG_RAM_SETUP | - CACHE_DATA_RAM_SETUP; - } - - /* Write new vlaue to L2CTLR */ - asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(l2ctlr)); -} - -/* - * Sets L2 cache related parameters before enabling data cache - */ -void v7_outer_cache_enable(void) -{ - if (cpu_is_exynos5()) - exynos5_set_l2cache_params(); -} -#endif |