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-rw-r--r--arch/arm/cpu/armv7/omap5/clocks.c39
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c123
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c87
3 files changed, 211 insertions, 38 deletions
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
index 1a59f265f7b..eecfbade354 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -260,20 +260,31 @@ const struct dpll_params *get_abe_dpll_params(void)
*/
void scale_vcores(void)
{
- u32 volt;
+ u32 volt_core, volt_mpu, volt_mm;
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
/* Palmas settings */
- volt = VDD_CORE;
- do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
-
- volt = VDD_MPU;
- do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
-
- volt = VDD_MM;
- do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
-
+ if (omap_revision() != OMAP5432_ES1_0) {
+ volt_core = VDD_CORE;
+ volt_mpu = VDD_MPU;
+ volt_mm = VDD_MM;
+ } else {
+ volt_core = VDD_CORE_5432;
+ volt_mpu = VDD_MPU_5432;
+ volt_mm = VDD_MM_5432;
+ }
+
+ do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
+ do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
+ do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
+
+ if (omap_revision() == OMAP5432_ES1_0) {
+ /* Configure LDO SRAM "magic" bits */
+ writel(2, &prcm->prm_sldo_core_setup);
+ writel(2, &prcm->prm_sldo_mpu_setup);
+ writel(2, &prcm->prm_sldo_mm_setup);
+ }
}
u32 get_offset_code(u32 volt_offset)
@@ -306,6 +317,7 @@ void enable_basic_clocks(void)
};
u32 *const clk_modules_hw_auto_essential[] = {
+ &prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
@@ -382,6 +394,9 @@ void enable_basic_uboot_clocks(void)
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
+ &prcm->cm_l3init_hsusbtll_clkctrl,
+ &prcm->cm_l3init_hsusbhost_clkctrl,
+ &prcm->cm_l3init_fsusb_clkctrl,
0
};
@@ -416,12 +431,10 @@ void enable_non_essential_clocks(void)
&prcm->cm_ivahd_ivahd_clkctrl,
&prcm->cm_ivahd_sl2_clkctrl,
&prcm->cm_dsp_dsp_clkctrl,
- &prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
&prcm->cm_l3init_hsi_clkctrl,
- &prcm->cm_l3init_hsusbtll_clkctrl,
&prcm->cm_l4per_hdq1w_clkctrl,
0
};
@@ -460,8 +473,6 @@ void enable_non_essential_clocks(void)
&prcm->cm_cam_fdif_clkctrl,
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
- &prcm->cm_l3init_fsusb_clkctrl,
0
};
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index d01cc81333b..d0c3ff70218 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -35,6 +35,7 @@
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
+#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -52,6 +53,81 @@ static struct gpio_bank gpio_bank_54xx[6] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#ifdef CONFIG_SPL_BUILD
+/* LPDDR2 specific IO settings */
+static void io_settings_lpddr2(void)
+{
+ struct omap_sys_ctrl_regs *ioregs_base =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch1_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch1_1));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch2_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch2_1));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ &(ioregs_base->control_lpddr2ch1_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ &(ioregs_base->control_lpddr2ch1_1));
+ writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ &(ioregs_base->control_ddrio_0));
+ writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ &(ioregs_base->control_ddrio_1));
+ writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+ &(ioregs_base->control_ddrio_2));
+}
+
+/* DDR3 specific IO settings */
+static void io_settings_ddr3(void)
+{
+ u32 io_settings = 0;
+ struct omap_sys_ctrl_regs *ioregs_base =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddr3ch1_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch1_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch1_1));
+
+ writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddr3ch2_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch2_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch2_1));
+
+ writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_0));
+ writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_1));
+ writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_2));
+
+ /* omap5432 does not use lpddr2 */
+ writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
+ writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
+
+ writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+ &(ioregs_base->control_emif1_sdram_config_ext));
+ writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+ &(ioregs_base->control_emif2_sdram_config_ext));
+
+ /* Disable DLL select */
+ io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
+ & 0xFFEFFFFF);
+ writel(io_settings,
+ &(ioregs_base->control_port_emif1_sdram_config));
+
+ io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
+ & 0xFFEFFFFF);
+ writel(io_settings,
+ &(ioregs_base->control_port_emif2_sdram_config));
+}
+
/*
* Some tuning of IOs for optimal power and performance
*/
@@ -115,25 +191,10 @@ void do_io_settings(void)
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
- /* LPDDR2 io settings */
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_1));
- writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- &(ioregs_base->control_ddrio_0));
- writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- &(ioregs_base->control_ddrio_1));
- writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
- &(ioregs_base->control_ddrio_2));
+ if (omap_revision() <= OMAP5430_ES1_0)
+ io_settings_lpddr2();
+ else
+ io_settings_ddr3();
/* Efuse settings */
writel(EFUSE_1, &(ioregs_base->control_efuse_1));
@@ -143,6 +204,20 @@ void do_io_settings(void)
}
#endif
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+ struct omap_sys_ctrl_regs *ioregs_base =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
+ if (emif_base == EMIF1_BASE)
+ writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+ &(ioregs_base->control_emif1_sdram_config_ext));
+ else if (emif_base == EMIF2_BASE)
+ writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+ &(ioregs_base->control_emif2_sdram_config_ext));
+}
+
void init_omap_revision(void)
{
/*
@@ -154,7 +229,15 @@ void init_omap_revision(void)
switch (rev) {
case MIDR_CORTEX_A15_R0P0:
- *omap_si_rev = OMAP5430_ES1_0;
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP5430_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP5430_ES1_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES1_0:
+ default:
+ *omap_si_rev = OMAP5432_ES1_0;
+ break;
+ }
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index b2b5753e894..6ebdf5fbfd0 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -86,11 +86,34 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x0007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0020420A,
+ .emif_ddr_phy_ctlr_1 = 0x0024420A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0,
- .dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80740300
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80740300,
+ .dmm_lisa_map_3 = 0xFF020100
};
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000077
};
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x01004010,
+ 0x00001004,
+ 0x04010040,
+ 0x01004010,
+ 0x00001004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80080080,
+ 0x00800800,
+ 0x08102040,
+ 0x00000002,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000057
+};
+
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
- *regs = &emif_regs_532_mhz_2cs;
+ if (omap_revision() == OMAP5432_ES1_0)
+ *regs = &emif_regs_ddr3_532_mhz_1cs;
+ else
+ *regs = &emif_regs_532_mhz_2cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
@@ -156,6 +204,37 @@ void emif_get_device_details(u32 emif_nr,
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+ u32 *ext_phy_ctrl_base = 0;
+ u32 *emif_ext_phy_ctrl_base = 0;
+ u32 i = 0;
+
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+ emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+ /* Configure external phy control timing registers */
+ for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+ writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+ }
+
+ /*
+ * external phy 6-24 registers do not change with
+ * ddr frequency
+ */
+ for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+ writel(ext_phy_ctrl_const_base[i],
+ emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(ext_phy_ctrl_const_base[i],
+ emif_ext_phy_ctrl_base++);
+ }
+}
+
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
.max_freq = 532000000,
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-23 15:23:28 +0000