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-rw-r--r--arch/arm/cpu/armv7/arch_timer.c6
-rw-r--r--arch/arm/cpu/armv7/ls102xa/Kconfig8
-rw-r--r--arch/arm/cpu/armv7/ls102xa/cpu.c20
-rw-r--r--arch/arm/cpu/armv7/ls102xa/fdt.c4
-rw-r--r--arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c6
-rw-r--r--arch/arm/cpu/armv7/stv0991/timer.c4
6 files changed, 28 insertions, 20 deletions
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index d96406f7626..17bd53dae84 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_HZ_CLOCK
+#ifndef CFG_SYS_HZ_CLOCK
static inline u32 read_cntfrq(void)
{
u32 frq;
@@ -29,8 +29,8 @@ int timer_init(void)
gd->arch.tbl = 0;
gd->arch.tbu = 0;
-#ifdef CONFIG_SYS_HZ_CLOCK
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#ifdef CFG_SYS_HZ_CLOCK
+ gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = read_cntfrq();
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index e75a895e008..7e138e0cc5b 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -1,6 +1,8 @@
config ARCH_LS1021A
bool
+ select FSL_DEVICE_DISABLE
select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
+ select LS102XA_STREAM_ID
select SYS_FSL_DDR_BE if SYS_FSL_DDR
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_IFC_BE
@@ -30,9 +32,15 @@ config ARCH_LS1021A
menu "LS102xA architecture"
depends on ARCH_LS1021A
+config FSL_DEVICE_DISABLE
+ bool
+
config LS1_DEEP_SLEEP
bool "Deep sleep"
+config LS102XA_STREAM_ID
+ bool
+
config MAX_CPUS
int "Maximum number of CPUs permitted for LS102xA"
default 2
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d530e0655bc..25e4b49c70e 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -168,18 +168,18 @@ static void mmu_setup(void)
/* Level 1 has 512 entries */
for (i = 0; i < 512; i++) {
/* Mapping for PCIe 1 */
- if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
- va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
- CONFIG_SYS_PCIE_MMAP_SIZE))
+ if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
+ va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
+ CFG_SYS_PCIE_MMAP_SIZE))
set_pgsection(level1_table, i,
- CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+ CFG_SYS_PCIE1_PHYS_BASE + va_start,
MT_DEVICE_MEM);
/* Mapping for PCIe 2 */
- else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
- va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
- CONFIG_SYS_PCIE_MMAP_SIZE))
+ else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
+ va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
+ CFG_SYS_PCIE_MMAP_SIZE))
set_pgsection(level1_table, i,
- CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+ CFG_SYS_PCIE2_PHYS_BASE + va_start,
MT_DEVICE_MEM);
else
set_pgsection(level1_table, i,
@@ -313,9 +313,9 @@ int cpu_eth_init(struct bd_info *bis)
int arch_cpu_init(void)
{
- void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
- (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index c01cebbf985..599b7e18ef3 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
- "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+ "clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif
sysclk_path = fdt_get_alias(blob, "sysclk");
@@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
- CONFIG_SYS_IFC_ADDR);
+ CFG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index b4d113dc1e0..dbb0766a9c6 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -29,7 +29,7 @@
*/
static void __secure ls1_save_ddr_head(void)
{
- const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+ const char *src = (const char *)CFG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
@@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void)
static void __secure ls1_fsm_setup(void)
{
- void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop)
static void __secure ls1_start_fsm(void)
{
- void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
index 67764ccf66a..f7cc45772f9 100644
--- a/arch/arm/cpu/armv7/stv0991/timer.c
+++ b/arch/arm/cpu/armv7/stv0991/timer.c
@@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer_masked();
- ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+ ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 02:25:47 +0000