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Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig5
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c49
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c10
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S4
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/mp.c11
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c3
6 files changed, 37 insertions, 45 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5ea99c459ce..80a1642447d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -55,6 +55,7 @@ config ARCH_LS1028A
select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select RESV_RAM if GIC_V3_ITS
+ select SYS_HAS_ARMV8_SECURE_BASE
imply PANIC_HANG
config ARCH_LS1043A
@@ -74,7 +75,6 @@ config ARCH_LS1043A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009660 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
@@ -91,6 +91,7 @@ config ARCH_LS1043A
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
+ select SYS_HAS_ARMV8_SECURE_BASE
imply CMD_PCI
imply ID_EEPROM
@@ -112,7 +113,6 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
@@ -335,6 +335,7 @@ menu "Layerscape architecture"
config FSL_LAYERSCAPE
bool
+ select ARM_SMCCC
config HAS_FEATURE_GIC64K_ALIGN
bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index cf469804c51..a71ee636afe 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -17,6 +17,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/ptrace.h>
+#include <linux/arm-smccc.h>
#include <linux/errno.h>
#include <asm/system.h>
#include <fm_eth.h>
@@ -768,7 +769,7 @@ enum boot_src __get_boot_src(u32 porsr1)
enum boot_src get_boot_src(void)
{
- struct pt_regs regs;
+ struct arm_smccc_res res;
u32 porsr1 = 0;
#if defined(CONFIG_FSL_LSCH3)
@@ -778,11 +779,9 @@ enum boot_src get_boot_src(void)
#endif
if (current_el() == 2) {
- regs.regs[0] = SIP_SVC_RCW;
-
- smc_call(&regs);
- if (!regs.regs[0])
- porsr1 = regs.regs[1];
+ arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res);
+ if (!res.a0)
+ porsr1 = res.a1;
}
if (current_el() == 3 || !porsr1) {
@@ -1081,9 +1080,9 @@ static void config_core_prefetch(void)
char *buf = NULL;
char buffer[HWCONFIG_BUFFER_SIZE];
const char *prefetch_arg = NULL;
+ struct arm_smccc_res res;
size_t arglen;
unsigned int mask;
- struct pt_regs regs;
if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
@@ -1101,11 +1100,10 @@ static void config_core_prefetch(void)
}
#define SIP_PREFETCH_DISABLE_64 0xC200FF13
- regs.regs[0] = SIP_PREFETCH_DISABLE_64;
- regs.regs[1] = mask;
- smc_call(&regs);
+ arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0,
+ &res);
- if (regs.regs[0])
+ if (res.a0)
printf("Prefetch disable config failed for mask ");
else
printf("Prefetch disable config passed for mask ");
@@ -1345,25 +1343,20 @@ phys_size_t get_effective_memsize(void)
#ifdef CONFIG_TFABOOT
phys_size_t tfa_get_dram_size(void)
{
- struct pt_regs regs;
- phys_size_t dram_size = 0;
-
- regs.regs[0] = SMC_DRAM_BANK_INFO;
- regs.regs[1] = -1;
+ struct arm_smccc_res res;
- smc_call(&regs);
- if (regs.regs[0])
+ arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0)
return 0;
- dram_size = regs.regs[1];
- return dram_size;
+ return res.a1;
}
static int tfa_dram_init_banksize(void)
{
int i = 0, ret = 0;
- struct pt_regs regs;
phys_size_t dram_size = tfa_get_dram_size();
+ struct arm_smccc_res res;
debug("dram_size %llx\n", dram_size);
@@ -1371,19 +1364,15 @@ static int tfa_dram_init_banksize(void)
return -EINVAL;
do {
- regs.regs[0] = SMC_DRAM_BANK_INFO;
- regs.regs[1] = i;
-
- smc_call(&regs);
- if (regs.regs[0]) {
+ arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0) {
ret = -EINVAL;
break;
}
- debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
- regs.regs[2]);
- gd->bd->bi_dram[i].start = regs.regs[1];
- gd->bd->bi_dram[i].size = regs.regs[2];
+ debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
+ gd->bd->bi_dram[i].start = res.a1;
+ gd->bd->bi_dram[i].size = res.a2;
dram_size -= gd->bd->bi_dram[i].size;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index fad7a935662..181bd9c1b4e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -147,10 +147,14 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
cfg >>= sd_prctl_shift;
cfg = serdes_get_number(sd, cfg);
- printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+ if (cfg == 0) {
+ printf("SERDES%d is disabled\n", sd + 1);
+ } else {
+ printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
- if (!is_serdes_prtcl_valid(sd, cfg))
- printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+ if (!is_serdes_prtcl_valid(sd, cfg))
+ printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+ }
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 2fb4e404a24..87410c73a92 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019 NXP
+ * Copyright 2019-2022 NXP
*
* Extracted from armv8/start.S
*/
@@ -344,7 +344,7 @@ ENTRY(fsl_ocram_clear_ecc_err)
ldr x0, =DCSR_DCFG_MBEESR2
str w1, [x0]
ret
-ENDPROC(fsl_ocram_init)
+ENDPROC(fsl_ocram_clear_ecc_err)
#endif
#ifdef CONFIG_FSL_LSCH3
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 2e2688eadca..72221191493 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -302,6 +302,7 @@ int cpu_release(u32 nr, int argc, char *const argv[])
u64 boot_addr;
u64 *table = get_spin_tbl_addr();
int pos;
+ int ret;
boot_addr = simple_strtoull(argv[0], NULL, 16);
@@ -326,16 +327,10 @@ int cpu_release(u32 nr, int argc, char *const argv[])
asm volatile("sev");
} else {
/* Use PSCI to kick the core */
- struct pt_regs regs;
-
printf("begin to kick cpu core #%d to address %llx\n",
nr, boot_addr);
- regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
- regs.regs[1] = nr;
- regs.regs[2] = boot_addr;
- regs.regs[3] = 0;
- smc_call(&regs);
- if (regs.regs[0])
+ ret = invoke_psci_fn(PSCI_0_2_FN64_CPU_ON, nr, boot_addr, 0);
+ if (ret)
return -1;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d3a5cfaac19..926f8f21b63 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -206,6 +206,9 @@ static void erratum_a008997(void)
static void erratum_a009007(void)
{
+ if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007))
+ return;
+
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
defined(CONFIG_ARCH_LS1012A)
void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 18:05:38 +0000