diff options
Diffstat (limited to 'arch/arm/cpu/tegra20-common')
| -rw-r--r-- | arch/arm/cpu/tegra20-common/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/ap20.c | 131 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/board.c | 146 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/clock.c | 47 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/emc.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/funcmux.c | 19 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/lowlevel_init.S | 42 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/pinmux.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/pmu.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/sys_info.c | 35 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/timer.c | 111 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/warmboot.c | 18 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/warmboot_avp.c | 14 |
13 files changed, 86 insertions, 496 deletions
diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 9e91e5cb8ca..8184e5e5a85 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -31,8 +31,7 @@ CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t LIB = $(obj)lib$(SOC)-common.o -SOBJS += lowlevel_init.o -COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-y += clock.o funcmux.o pinmux.o COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o COBJS-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c deleted file mode 100644 index c0ca6eb379e..00000000000 --- a/arch/arm/cpu/tegra20-common/ap20.c +++ /dev/null @@ -1,131 +0,0 @@ -/* -* (C) Copyright 2010-2011 -* NVIDIA Corporation <www.nvidia.com> -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ -#include <asm/io.h> -#include <asm/arch/ap20.h> -#include <asm/arch/fuse.h> -#include <asm/arch/gp_padctrl.h> -#include <asm/arch/pmc.h> -#include <asm/arch/scu.h> -#include <asm/arch/warmboot.h> -#include <common.h> - -int tegra_get_chip_type(void) -{ - struct apb_misc_gp_ctlr *gp; - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - uint tegra_sku_id, rev; - - /* - * This is undocumented, Chip ID is bits 15:8 of the register - * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for - * Tegra30 - */ - gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - - tegra_sku_id = readl(&fuse->sku_info) & 0xff; - - switch (rev) { - case CHIPID_TEGRA20: - switch (tegra_sku_id) { - case SKU_ID_T20: - return TEGRA_SOC_T20; - case SKU_ID_T25SE: - case SKU_ID_AP25: - case SKU_ID_T25: - case SKU_ID_AP25E: - case SKU_ID_T25E: - return TEGRA_SOC_T25; - } - break; - } - /* unknown sku id */ - return TEGRA_SOC_UNKNOWN; -} - -static void enable_scu(void) -{ - struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; - u32 reg; - - /* If SCU already setup/enabled, return */ - if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) - return; - - /* Invalidate all ways for all processors */ - writel(0xFFFF, &scu->scu_inv_all); - - /* Enable SCU - bit 0 */ - reg = readl(&scu->scu_ctrl); - reg |= SCU_CTRL_ENABLE; - writel(reg, &scu->scu_ctrl); -} - -static u32 get_odmdata(void) -{ - /* - * ODMDATA is stored in the BCT in IRAM by the BootROM. - * The BCT start and size are stored in the BIT in IRAM. - * Read the data @ bct_start + (bct_size - 12). This works - * on T20 and T30 BCTs, which are locked down. If this changes - * in new chips (T114, etc.), we can revisit this algorithm. - */ - - u32 bct_start, odmdata; - - bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR); - odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); - - return odmdata; -} - -static void init_pmc_scratch(void) -{ - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - u32 odmdata; - int i; - - /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ - for (i = 0; i < 23; i++) - writel(0, &pmc->pmc_scratch1+i); - - /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ - odmdata = get_odmdata(); - writel(odmdata, &pmc->pmc_scratch20); -} - -void s_init(void) -{ - /* Init PMC scratch memory */ - init_pmc_scratch(); - - enable_scu(); - - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #0x41\n" - "mcr p15, 0, r0, c1, c0, 1\n"); - - /* FIXME: should have ap20's L2 disabled too? */ -} diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c deleted file mode 100644 index 8a8d3384ac4..00000000000 --- a/arch/arm/cpu/tegra20-common/board.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <asm/arch/pmc.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/tegra20.h> -#include <asm/arch/warmboot.h> - -DECLARE_GLOBAL_DATA_PTR; - -enum { - /* UARTs which we can enable */ - UARTA = 1 << 0, - UARTB = 1 << 1, - UARTD = 1 << 3, - UART_COUNT = 4, -}; - -/* - * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0, - * so we are using this value to identify memory size. - */ - -unsigned int query_sdram_size(void) -{ - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - u32 reg; - - reg = readl(&pmc->pmc_scratch20); - debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg); - - /* bits 31:28 in OdmData are used for RAM size */ - switch ((reg) >> 28) { - case 1: - return 0x10000000; /* 256 MB */ - case 2: - default: - return 0x20000000; /* 512 MB */ - case 3: - return 0x40000000; /* 1GB */ - } -} - -int dram_init(void) -{ - /* We do not initialise DRAM here. We just query the size */ - gd->ram_size = query_sdram_size(); - return 0; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("Board: %s\n", sysinfo.board_string); - return 0; -} -#endif /* CONFIG_DISPLAY_BOARDINFO */ - -static int uart_configs[] = { -#if defined(CONFIG_TEGRA_UARTA_UAA_UAB) - FUNCMUX_UART1_UAA_UAB, -#elif defined(CONFIG_TEGRA_UARTA_GPU) - FUNCMUX_UART1_GPU, -#elif defined(CONFIG_TEGRA_UARTA_SDIO1) - FUNCMUX_UART1_SDIO1, -#else - FUNCMUX_UART1_IRRX_IRTX, -#endif - FUNCMUX_UART2_IRDA, - -1, - FUNCMUX_UART4_GMC, - -1, -}; - -/** - * Set up the specified uarts - * - * @param uarts_ids Mask containing UARTs to init (UARTx) - */ -static void setup_uarts(int uart_ids) -{ - static enum periph_id id_for_uart[] = { - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_UART4, - }; - size_t i; - - for (i = 0; i < UART_COUNT; i++) { - if (uart_ids & (1 << i)) { - enum periph_id id = id_for_uart[i]; - - funcmux_select(id, uart_configs[i]); - clock_ll_start_uart(id); - } - } -} - -void board_init_uart_f(void) -{ - int uart_ids = 0; /* bit mask of which UART ids to enable */ - -#ifdef CONFIG_TEGRA_ENABLE_UARTA - uart_ids |= UARTA; -#endif -#ifdef CONFIG_TEGRA_ENABLE_UARTB - uart_ids |= UARTB; -#endif -#ifdef CONFIG_TEGRA_ENABLE_UARTD - uart_ids |= UARTD; -#endif - setup_uarts(uart_ids); -} - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c index 24038745bd9..12987a68936 100644 --- a/arch/arm/cpu/tegra20-common/clock.c +++ b/arch/arm/cpu/tegra20-common/clock.c @@ -21,12 +21,12 @@ /* Tegra20 Clock control functions */ +#include <common.h> #include <asm/io.h> -#include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> -#include <asm/arch/timer.h> -#include <asm/arch/tegra20.h> -#include <common.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h> @@ -396,6 +396,16 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(CRAM2), }; +/* number of clock outputs of a PLL */ +static const u8 pll_num_clkouts[] = { + 1, /* PLLC */ + 1, /* PLLM */ + 4, /* PLLP */ + 1, /* PLLA */ + 0, /* PLLU */ + 0, /* PLLD */ +}; + /* * Get the oscillator frequency, from the corresponding hardware configuration * field. @@ -502,6 +512,7 @@ static int clock_periph_id_isvalid(enum periph_id id) case PERIPH_ID_RESERVED81: case PERIPH_ID_RESERVED82: case PERIPH_ID_RESERVED83: + case PERIPH_ID_RESERVED91: printf("Peripheral id %d is reserved\n", id); break; default: @@ -603,6 +614,34 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT); } +int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate) +{ + struct clk_pll *pll = get_pll(clkid); + int data = 0, div = 0, offset = 0; + + if (!clock_id_is_pll(clkid)) + return -1; + + if (pllout + 1 > pll_num_clkouts[clkid]) + return -1; + + div = clk_get_divider(8, pll_rate[clkid], rate); + + if (div < 0) + return -1; + + /* out2 and out4 are in the high part of the register */ + if (pllout == PLL_OUT2 || pllout == PLL_OUT4) + offset = 16; + + data = (div << PLL_OUT_RATIO_SHIFT) | + PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN; + clrsetbits_le32(&pll->pll_out[pllout >> 1], + PLL_OUT_RATIO_MASK << offset, data << offset); + + return 0; +} + /** * Find the best available 7.1 format divisor given a parent clock rate and * required child clock rate. This function assumes that a second-stage diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c index ffc05e453a0..97420d70661 100644 --- a/arch/arm/cpu/tegra20-common/emc.c +++ b/arch/arm/cpu/tegra20-common/emc.c @@ -23,11 +23,11 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> -#include <asm/arch/ap20.h> +#include <asm/arch-tegra/ap.h> #include <asm/arch/apb_misc.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> -#include <asm/arch/tegra20.h> +#include <asm/arch/tegra.h> /* * The EMC registers have shadow registers. When the EMC clock is updated diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c index b2129adf2fe..00b8029ebad 100644 --- a/arch/arm/cpu/tegra20-common/funcmux.c +++ b/arch/arm/cpu/tegra20-common/funcmux.c @@ -235,9 +235,26 @@ int funcmux_select(enum periph_id id, int config) break; case PERIPH_ID_NDFLASH: - if (config == FUNCMUX_NDFLASH_ATC) { + switch (config) { + case FUNCMUX_NDFLASH_ATC: pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND); pinmux_tristate_disable(PINGRP_ATC); + break; + case FUNCMUX_NDFLASH_KBC_8_BIT: + pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND); + pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND); + pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND); + pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND); + + pinmux_tristate_disable(PINGRP_KBCA); + pinmux_tristate_disable(PINGRP_KBCC); + pinmux_tristate_disable(PINGRP_KBCD); + pinmux_tristate_disable(PINGRP_KBCE); + pinmux_tristate_disable(PINGRP_KBCF); + + bad_config = 0; + break; } break; diff --git a/arch/arm/cpu/tegra20-common/lowlevel_init.S b/arch/arm/cpu/tegra20-common/lowlevel_init.S deleted file mode 100644 index d117f23a622..00000000000 --- a/arch/arm/cpu/tegra20-common/lowlevel_init.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * SoC-specific setup info - * - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <linux/linkage.h> - - .align 5 -ENTRY(reset_cpu) - ldr r1, rstctl @ get addr for global reset - @ reg - ldr r3, [r1] - orr r3, r3, #0x10 - str r3, [r1] @ force reset - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PRM_RSTCTRL -ENDPROC(reset_cpu) diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c index 70e84dfa178..08b83055dbb 100644 --- a/arch/arm/cpu/tegra20-common/pinmux.c +++ b/arch/arm/cpu/tegra20-common/pinmux.c @@ -21,10 +21,10 @@ /* Tegra20 pin multiplexing functions */ +#include <common.h> #include <asm/io.h> -#include <asm/arch/tegra20.h> +#include <asm/arch/tegra.h> #include <asm/arch/pinmux.h> -#include <common.h> /* diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c index 53505e9c50c..228295303ca 100644 --- a/arch/arm/cpu/tegra20-common/pmu.c +++ b/arch/arm/cpu/tegra20-common/pmu.c @@ -24,10 +24,10 @@ #include <common.h> #include <tps6586x.h> #include <asm/io.h> -#include <asm/arch/ap20.h> -#include <asm/arch/tegra20.h> -#include <asm/arch/tegra_i2c.h> -#include <asm/arch/sys_proto.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <asm/arch-tegra/sys_proto.h> #define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */ #define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */ diff --git a/arch/arm/cpu/tegra20-common/sys_info.c b/arch/arm/cpu/tegra20-common/sys_info.c deleted file mode 100644 index 1a0bb561a7f..00000000000 --- a/arch/arm/cpu/tegra20-common/sys_info.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#ifdef CONFIG_DISPLAY_CPUINFO -/* Print CPU information */ -int print_cpuinfo(void) -{ - puts("TEGRA20\n"); - - /* TBD: Add printf of major/minor rev info, stepping, etc. */ - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/tegra20-common/timer.c b/arch/arm/cpu/tegra20-common/timer.c deleted file mode 100644 index 562e4140121..00000000000 --- a/arch/arm/cpu/tegra20-common/timer.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * (C) Copyright 2008 - * Texas Instruments - * - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Moahmmed Khasim <khasim@ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/tegra20.h> -#include <asm/arch/timer.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* counter runs at 1MHz */ -#define TIMER_CLK 1000000 -#define TIMER_LOAD_VAL 0xffffffff - -/* timer without interrupts */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds */ -void __udelay(unsigned long usec) -{ - long tmo = usec * (TIMER_CLK / 1000) / 1000; - unsigned long now, last = timer_get_us(); - - while (tmo > 0) { - now = timer_get_us(); - if (last > now) /* count up timer overflow */ - tmo -= TIMER_LOAD_VAL - last + now; - else - tmo -= now - last; - last = now; - } -} - -ulong get_timer_masked(void) -{ - ulong now; - - /* current tick value */ - now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ); - - if (now >= gd->lastinc) /* normal mode (non roll) */ - /* move stamp forward with absolute diff ticks */ - gd->tbl += (now - gd->lastinc); - else /* we have rollover of incrementer */ - gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ)) - - gd->lastinc) + now; - gd->lastinc = now; - return gd->tbl; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} - -unsigned long timer_get_us(void) -{ - struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE; - - return readl(&timer_base->cntr_1us); -} diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c index 6ce995ef029..157b9abc459 100644 --- a/arch/arm/cpu/tegra20-common/warmboot.c +++ b/arch/arm/cpu/tegra20-common/warmboot.c @@ -24,17 +24,17 @@ #include <common.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/arch/ap20.h> -#include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> -#include <asm/arch/pmc.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/tegra20.h> -#include <asm/arch/fuse.h> #include <asm/arch/emc.h> #include <asm/arch/gp_padctrl.h> -#include <asm/arch/warmboot.h> +#include <asm/arch/pinmux.h> #include <asm/arch/sdram_param.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/pmc.h> +#include <asm/arch-tegra/fuse.h> +#include <asm/arch-tegra/warmboot.h> DECLARE_GLOBAL_DATA_PTR; @@ -361,8 +361,8 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) /* Populate the header. */ dst_header->length_insecure = length + sizeof(struct wb_header); dst_header->length_secure = length + sizeof(struct wb_header); - dst_header->destination = AP20_WB_RUN_ADDRESS; - dst_header->entry_point = AP20_WB_RUN_ADDRESS; + dst_header->destination = NV_WB_RUN_ADDRESS; + dst_header->entry_point = NV_WB_RUN_ADDRESS; dst_header->code_length = length; if (is_encrypted) { diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index 80a5a15decf..bc466068925 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -23,14 +23,14 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/ap20.h> -#include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> -#include <asm/arch/pmc.h> -#include <asm/arch/tegra20.h> -#include <asm/arch/warmboot.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/pmc.h> +#include <asm/arch-tegra/warmboot.h> #include "warmboot_avp.h" #define DEBUG_RESET_CORESIGHT @@ -58,7 +58,7 @@ void wb_start(void) /* no input, no clobber list */ ); - if (reg != AP20_WB_RUN_ADDRESS) + if (reg != NV_WB_RUN_ADDRESS) goto do_reset; /* Are we running with AVP? */ @@ -214,7 +214,7 @@ void wb_start(void) reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE | PLLM_OUT1_RATIO_VAL_8; - writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out); + writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]); reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 | SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 | |