diff options
Diffstat (limited to 'arch/arm/cpu')
26 files changed, 35 insertions, 503 deletions
diff --git a/arch/arm/cpu/arm920t/ep93xx/cpu.c b/arch/arm/cpu/arm920t/ep93xx/cpu.c index c9ea4e46a87..3435bdc748a 100644 --- a/arch/arm/cpu/arm920t/ep93xx/cpu.c +++ b/arch/arm/cpu/arm920t/ep93xx/cpu.c @@ -14,7 +14,7 @@ #include <asm/io.h> /* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */ -extern void reset_cpu(ulong addr) +extern void reset_cpu(void) { struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; uint32_t value; diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c index e9d55779214..0cd3a039810 100644 --- a/arch/arm/cpu/arm920t/imx/timer.c +++ b/arch/arm/cpu/arm920t/imx/timer.c @@ -81,7 +81,7 @@ ulong get_tbclk(void) /* * Reset the cpu by setting up the watchdog timer and let him time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Disable watchdog and set Time-Out field to 0 */ WCR = 0x00000000; diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c index ec73393d0fc..6d77ad3b6da 100644 --- a/arch/arm/cpu/arm926ejs/armada100/timer.c +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c @@ -142,7 +142,7 @@ int timer_init(void) * 2. Write key value to TMP_WSAR reg. * 3. Perform write operation. */ -void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct armd1mpmu_registers *mpmu = (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c index 38df1c94022..7844a99c164 100644 --- a/arch/arm/cpu/arm926ejs/mx25/reset.c +++ b/arch/arm/cpu/arm926ejs/mx25/reset.c @@ -23,7 +23,7 @@ /* * Reset the cpu by setting up the watchdog timer and let it time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c index 320b0a65e70..496fb30817d 100644 --- a/arch/arm/cpu/arm926ejs/mx27/reset.c +++ b/arch/arm/cpu/arm926ejs/mx27/reset.c @@ -23,7 +23,7 @@ /* * Reset the cpu by setting up the watchdog timer and let it time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index c9362136fbf..344b9b4e550 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -32,9 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Lowlevel init isn't used on i.MX28, so just have a dummy here */ __weak void lowlevel_init(void) {} -void reset_cpu(ulong ignored) __attribute__((noreturn)); +void reset_cpu(void) __attribute__((noreturn)); -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE; diff --git a/arch/arm/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c index a316540d52a..97a624e16cd 100644 --- a/arch/arm/cpu/arm926ejs/spear/reset.c +++ b/arch/arm/cpu/arm926ejs/spear/reset.c @@ -11,7 +11,7 @@ #include <asm/arch/spr_syscntl.h> #include <linux/delay.h> -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct syscntl_regs *syscntl_regs_p = (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index fb0ea5e817f..334bb542743 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -56,7 +56,7 @@ static void cache_flush (void) #ifndef CONFIG_ARCH_INTEGRATOR -__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +__attribute__((noreturn)) void reset_cpu(void) { writew(0x0, 0xfffece10); writew(0x8, 0xfffece10); diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c index fda5a9527ec..1491e5c88b2 100644 --- a/arch/arm/cpu/armv7/bcm281xx/reset.c +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -13,7 +13,7 @@ #define CLKS_SHIFT 20 /* Clock period shift */ #define LD_SHIFT 0 /* Reload value shift */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* * Set WD enable, RST enable, diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c index 3bfed34533b..63992fd8701 100644 --- a/arch/arm/cpu/armv7/bcmcygnus/reset.c +++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c @@ -10,7 +10,7 @@ #define CRMU_MAIL_BOX1 0x03024028 #define CRMU_SOFT_RESET_CMD 0xFFFFFFFF -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Send soft reset command via Mailbox. */ writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1); diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c index 675f99fe998..a3137752e88 100644 --- a/arch/arm/cpu/armv7/bcmnsp/reset.c +++ b/arch/arm/cpu/armv7/bcmnsp/reset.c @@ -9,7 +9,7 @@ #define CRU_RESET_OFFSET 0x1803F184 -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Reset the cpu by setting software reset request bit */ writel(0x1, CRU_RESET_OFFSET); diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 146cf526089..19ff4323528 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -176,9 +176,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) { } -void arm_init_domains(void) -{ -} #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index f26a5b22fdf..d863c9625aa 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -375,7 +375,7 @@ void smp_kick_all_cpus(void) } #endif -void reset_cpu(ulong addr) +void reset_cpu(void) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 3c71a37a74b..3baa761ec7a 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -88,7 +88,7 @@ int print_cpuinfo(void) } #endif -void reset_cpu(ulong ignored) +void reset_cpu(void) { void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR; const u32 sw_rst_enb_bitpos = 3; diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c index fb67de10f48..77d4477c8dc 100644 --- a/arch/arm/cpu/armv7/stv0991/reset.c +++ b/arch/arm/cpu/armv7/stv0991/reset.c @@ -9,7 +9,7 @@ #include <asm/io.h> #include <asm/arch/stv0991_wdru.h> #include <linux/delay.h> -void reset_cpu(ulong ignored) +void reset_cpu(void) { puts("System is going to reboot ...\n"); /* diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index 7f827da033b..63721018c16 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -47,7 +47,7 @@ int cleanup_before_linux(void) /* * Perform the low-level reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* * Perform reset but keep priority group unchanged. diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9cd6a8d642b..b7a10a8e34e 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -116,7 +116,7 @@ config PSCI_RESET !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ - !ARCH_UNIPHIER && !TARGET_S32V234EVB + !ARCH_UNIPHIER help Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ae0b7b21e81..9d1ba4c771a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -47,6 +47,8 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A050382 + select SYS_FSL_ERRATUM_A011334 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select RESV_RAM if GIC_V3_ITS imply PANIC_HANG diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 3a5bf778260..270a72e550c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1231,7 +1231,7 @@ int timer_init(void) __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; -void __efi_runtime reset_cpu(ulong addr) +void __efi_runtime reset_cpu(void) { #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) /* clear the RST_REQ_MSK and SW_RST_REQ */ @@ -1260,7 +1260,7 @@ void __efi_runtime EFIAPI efi_reset_system( case EFI_RESET_COLD: case EFI_RESET_WARM: case EFI_RESET_PLATFORM_SPECIFIC: - reset_cpu(0); + reset_cpu(); break; case EFI_RESET_SHUTDOWN: /* Nothing we can do */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index d5131bcf4b3..5b43a2a2316 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -6,7 +6,9 @@ #include <common.h> #include <clock_legacy.h> #include <cpu_func.h> +#include <debug_uart.h> #include <env.h> +#include <hang.h> #include <image.h> #include <init.h> #include <log.h> @@ -67,10 +69,19 @@ void spl_board_init(void) void board_init_f(ulong dummy) { + int ret; + icache_enable(); /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); + if (IS_ENABLED(CONFIG_DEBUG_UART)) + debug_uart_init(); board_early_init_f(); + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } timer_init(); #ifdef CONFIG_ARCH_LS2080A env_init(); @@ -139,13 +150,4 @@ int spl_start_uboot(void) return 1; } #endif /* CONFIG_SPL_OS_BOOT */ -#ifdef CONFIG_SPL_LOAD_FIT -__weak int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv8/s32v234/Makefile b/arch/arm/cpu/armv8/s32v234/Makefile deleted file mode 100644 index 3bdb98d995e..00000000000 --- a/arch/arm/cpu/armv8/s32v234/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - -obj-y += generic.o -obj-y += cpu.o diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c deleted file mode 100644 index 8ee3adc8058..00000000000 --- a/arch/arm/cpu/armv8/s32v234/cpu.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014-2016, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <asm/cache.h> -#include <asm/io.h> -#include <asm/system.h> -#include <asm/armv8/mmu.h> -#include <asm/io.h> -#include <asm/arch/mc_me_regs.h> -#include <linux/bitops.h> -#include "cpu.h" - -u32 cpu_mask(void) -{ - return readl(MC_ME_CS); -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) - -#define S32V234_IRAM_BASE 0x3e800000UL -#define S32V234_IRAM_SIZE 0x800000UL -#define S32V234_DRAM_BASE1 0x80000000UL -#define S32V234_DRAM_SIZE1 0x40000000UL -#define S32V234_DRAM_BASE2 0xC0000000UL -#define S32V234_DRAM_SIZE2 0x20000000UL -#define S32V234_PERIPH_BASE 0x40000000UL -#define S32V234_PERIPH_SIZE 0x40000000UL - -static struct mm_region s32v234_mem_map[] = { - { - .virt = S32V234_IRAM_BASE, - .phys = S32V234_IRAM_BASE, - .size = S32V234_IRAM_SIZE, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - .virt = S32V234_DRAM_BASE1, - .phys = S32V234_DRAM_BASE1, - .size = S32V234_DRAM_SIZE1, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE - }, { - .virt = S32V234_PERIPH_BASE, - .phys = S32V234_PERIPH_BASE, - .size = S32V234_PERIPH_SIZE, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - /* TODO: Do we need these? */ - /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */ - }, { - .virt = S32V234_DRAM_BASE2, - .phys = S32V234_DRAM_BASE2, - .size = S32V234_DRAM_SIZE2, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_OUTER_SHARE - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = s32v234_mem_map; - -#endif - -/* - * Return the number of cores on this SOC. - */ -int cpu_numcores(void) -{ - int numcores; - u32 mask; - - mask = cpu_mask(); - numcores = hweight32(cpu_mask()); - - /* Verify if M4 is deactivated */ - if (mask & 0x1) - numcores--; - - return numcores; -} - -#if defined(CONFIG_ARCH_EARLY_INIT_R) -int arch_early_init_r(void) -{ - int rv; - asm volatile ("dsb sy"); - rv = fsl_s32v234_wake_seconday_cores(); - - if (rv) - printf("Did not wake secondary cores\n"); - - asm volatile ("sev"); - return 0; -} -#endif /* CONFIG_ARCH_EARLY_INIT_R */ diff --git a/arch/arm/cpu/armv8/s32v234/cpu.h b/arch/arm/cpu/armv8/s32v234/cpu.h deleted file mode 100644 index 11c3a6b435e..00000000000 --- a/arch/arm/cpu/armv8/s32v234/cpu.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014-2016, Freescale Semiconductor, Inc. - */ - -u32 cpu_mask(void); -int cpu_numcores(void); diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c deleted file mode 100644 index 0fc98852228..00000000000 --- a/arch/arm/cpu/armv8/s32v234/generic.c +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <clock_legacy.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/mc_cgm_regs.h> -#include <asm/arch/mc_me_regs.h> -#include <asm/arch/mc_rgm_regs.h> -#include <netdev.h> -#include <div64.h> -#include <errno.h> - -u32 get_cpu_rev(void) -{ - struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; - u32 cpu = readl(&mscmir->cpxtype); - - return cpu; -} - -DECLARE_GLOBAL_DATA_PTR; - -static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv, - u32 pllfd, u32 selected_output) -{ - u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0; - u32 plldv_rfdphi_div = 0, fout = 0; - u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0; - - if (selected_output > DFS_MAXNUMBER) { - return -1; - } - - plldv_prediv = - (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET; - plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK); - - pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK); - - plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv; - - /* The formula for VCO is from TR manual, rev. D */ - vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481); - - if (selected_output != 0) { - /* Determine the RFDPHI for PHI1 */ - plldv_rfdphi_div = - (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >> - PLLDIG_PLLDV_RFDPHI1_OFFSET; - plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div; - if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) { - dfs_portn = - readl(DFS_DVPORTn(pll, selected_output - 1)); - dfs_mfi = - (dfs_portn & DFS_DVPORTn_MFI_MASK) >> - DFS_DVPORTn_MFI_OFFSET; - dfs_mfn = - (dfs_portn & DFS_DVPORTn_MFI_MASK) >> - DFS_DVPORTn_MFI_OFFSET; - fout = vco / (dfs_mfi + (dfs_mfn / 256)); - } else { - fout = vco / plldv_rfdphi_div; - } - - } else { - /* Determine the RFDPHI for PHI0 */ - plldv_rfdphi_div = - (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >> - PLLDIG_PLLDV_RFDPHI_OFFSET; - fout = vco / plldv_rfdphi_div; - } - - return fout; - -} - -/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */ -static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq, - u32 selected_output) -{ - u32 plldv, pllfd; - - plldv = readl(PLLDIG_PLLDV(pll)); - pllfd = readl(PLLDIG_PLLFD(pll)); - - return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output); -} - -static u32 get_mcu_main_clk(void) -{ - u32 coreclk_div; - u32 sysclk_sel; - u32 freq = 0; - - sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; - sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; - - coreclk_div = - readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK; - coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET; - coreclk_div += 1; - - switch (sysclk_sel) { - case MC_CGM_SC_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_ARMPLL: - /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */ - freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0); - break; - case MC_CGM_SC_SEL_CLKDISABLE: - printf("Sysclk is disabled\n"); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / coreclk_div; -} - -static u32 get_sys_clk(u32 number) -{ - u32 sysclk_div, sysclk_div_number; - u32 sysclk_sel; - u32 freq = 0; - - switch (number) { - case 3: - sysclk_div_number = 0; - break; - case 6: - sysclk_div_number = 1; - break; - default: - printf("unsupported system clock \n"); - return -1; - } - sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; - sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; - - sysclk_div = - readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) & - MC_CGM_SC_DCn_PREDIV_MASK; - sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET; - sysclk_div += 1; - - switch (sysclk_sel) { - case MC_CGM_SC_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_SC_SEL_ARMPLL: - /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */ - freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1); - break; - case MC_CGM_SC_SEL_CLKDISABLE: - printf("Sysclk is disabled\n"); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / sysclk_div; -} - -static u32 get_peripherals_clk(void) -{ - u32 aux5clk_div; - u32 freq = 0; - - aux5clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux5clk_div += 1; - - freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0); - - return freq / aux5clk_div; - -} - -static u32 get_uart_clk(void) -{ - u32 auxclk3_div, auxclk3_sel, freq = 0; - - auxclk3_sel = - readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK; - auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET; - - auxclk3_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - auxclk3_div += 1; - - switch (auxclk3_sel) { - case MC_CGM_ACn_SEL_FIRC: - freq = FIRC_CLK_FREQ; - break; - case MC_CGM_ACn_SEL_XOSC: - freq = XOSC_CLK_FREQ; - break; - case MC_CGM_ACn_SEL_PERPLLDIVX: - freq = get_peripherals_clk() / 3; - break; - case MC_CGM_ACn_SEL_SYSCLK: - freq = get_sys_clk(6); - break; - default: - printf("unsupported system clock select\n"); - } - - return freq / auxclk3_div; -} - -static u32 get_fec_clk(void) -{ - u32 aux2clk_div; - u32 freq = 0; - - aux2clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux2clk_div += 1; - - freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0); - - return freq / aux2clk_div; -} - -static u32 get_usdhc_clk(void) -{ - u32 aux15clk_div; - u32 freq = 0; - - aux15clk_div = - readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) & - MC_CGM_ACn_DCm_PREDIV_MASK; - aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET; - aux15clk_div += 1; - - freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4); - - return freq / aux15clk_div; -} - -static u32 get_i2c_clk(void) -{ - return get_peripherals_clk(); -} - -/* return clocks in Hz */ -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return get_mcu_main_clk(); - case MXC_PERIPHERALS_CLK: - return get_peripherals_clk(); - case MXC_UART_CLK: - return get_uart_clk(); - case MXC_FEC_CLK: - return get_fec_clk(); - case MXC_I2C_CLK: - return get_i2c_clk(); - case MXC_USDHC_CLK: - return get_usdhc_clk(); - default: - break; - } - printf("Error: Unsupported function to read the frequency! \ - Please define it correctly!"); - return -1; -} - -/* Not yet implemented - int soc_clk_dump(); */ - -#if defined(CONFIG_DISPLAY_CPUINFO) -static char *get_reset_cause(void) -{ - u32 cause = readl(MC_RGM_BASE_ADDR + 0x300); - - switch (cause) { - case F_SWT4: - return "WDOG"; - case F_JTAG: - return "JTAG"; - case F_FCCU_SOFT: - return "FCCU soft reaction"; - case F_FCCU_HARD: - return "FCCU hard reaction"; - case F_SOFT_FUNC: - return "Software Functional reset"; - case F_ST_DONE: - return "Self Test done reset"; - case F_EXT_RST: - return "External reset"; - default: - return "unknown reset"; - } - -} - -#define SRC_SCR_SW_RST (1<<12) - -void reset_cpu(ulong addr) -{ - printf("Feature not supported.\n"); -}; - -int print_cpuinfo(void) -{ - printf("CPU: Freescale Treerunner S32V234 at %d MHz\n", - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("Reset cause: %s\n", get_reset_cause()); - - return 0; -} -#endif - -int cpu_eth_init(struct bd_info * bis) -{ - int rc = -ENODEV; - -#if defined(CONFIG_FEC_MXC) - rc = fecmxc_initialize(bis); -#endif - - return rc; -} - -int get_clocks(void) -{ -#ifdef CONFIG_FSL_ESDHC_IMX - gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); -#endif - return 0; -} diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index ea91d8aaec2..c7efb67754e 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -267,9 +267,9 @@ void i2c_clk_enable(void) writel(readl(CKEN) | CKEN14_I2C, CKEN); } -void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn)); +void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn)); -void reset_cpu(ulong ignored) +void reset_cpu(void) { uint32_t tmp; diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c index 91e100af1b6..6f67f7fc228 100644 --- a/arch/arm/cpu/sa1100/cpu.c +++ b/arch/arm/cpu/sa1100/cpu.c @@ -55,7 +55,7 @@ static void cache_flush (void) #define RSRR 0x00 #define RCSR 0x04 -__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +__attribute__((noreturn)) void reset_cpu(void) { /* repeat endlessly */ while (1) { |