diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/cpu.c | 9 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/nonsec_virt.S | 11 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/psci.S | 77 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/s5p-common/pwm.c | 11 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/s5p-common/timer.c | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/s5p4418/cpu.c | 29 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/virt-v7.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/psci.S | 12 |
12 files changed, 54 insertions, 128 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 7e138e0cc5b..a83eb7e8fdd 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -51,6 +51,9 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config PEN_ADDR_BIG_ENDIAN + bool + config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 25e4b49c70e..c455969609f 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -302,15 +302,6 @@ int cpu_mmc_init(struct bd_info *bis) } #endif -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH) - tsec_standard_init(bis); -#endif - - return 0; -} - int arch_cpu_init(void) { void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 39aeeb423f0..9004074da2c 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry) ENDPROC(_do_nonsec_entry) .macro get_cbar_addr addr -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS +#ifdef CFG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS #else mrc p15, 4, \addr, c15, c0, 0 @ read CBAR bfc \addr, #0, #15 @ clear reserved bits @@ -205,11 +205,11 @@ ENTRY(_nonsec_init) bx lr ENDPROC(_nonsec_init) -#ifdef CONFIG_SMP_PEN_ADDR +#ifdef CFG_SMP_PEN_ADDR /* void __weak smp_waitloop(unsigned previous_address); */ -ENTRY(smp_waitloop) +WEAK(smp_waitloop) wfi - ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address + ldr r1, =CFG_SMP_PEN_ADDR @ load start address ldr r1, [r1] #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN rev r1, r1 @@ -219,7 +219,6 @@ ENTRY(smp_waitloop) mov r0, r1 b _do_nonsec_entry ENDPROC(smp_waitloop) -.weak smp_waitloop #endif .popsection diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 983cd904429..6c066e50d91 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -36,34 +36,32 @@ _psci_vectors: b default_psci_vector @ irq b psci_fiq_enter @ fiq -ENTRY(psci_fiq_enter) +WEAK(psci_fiq_enter) movs pc, lr ENDPROC(psci_fiq_enter) -.weak psci_fiq_enter -ENTRY(default_psci_vector) +WEAK(default_psci_vector) movs pc, lr ENDPROC(default_psci_vector) -.weak default_psci_vector - -ENTRY(psci_version) -ENTRY(psci_cpu_suspend) -ENTRY(psci_cpu_off) -ENTRY(psci_cpu_on) -ENTRY(psci_affinity_info) -ENTRY(psci_migrate) -ENTRY(psci_migrate_info_type) -ENTRY(psci_migrate_info_up_cpu) -ENTRY(psci_system_off) -ENTRY(psci_system_reset) -ENTRY(psci_features) -ENTRY(psci_cpu_freeze) -ENTRY(psci_cpu_default_suspend) -ENTRY(psci_node_hw_state) -ENTRY(psci_system_suspend) -ENTRY(psci_set_suspend_mode) -ENTRY(psi_stat_residency) -ENTRY(psci_stat_count) + +WEAK(psci_version) +WEAK(psci_cpu_suspend) +WEAK(psci_cpu_off) +WEAK(psci_cpu_on) +WEAK(psci_affinity_info) +WEAK(psci_migrate) +WEAK(psci_migrate_info_type) +WEAK(psci_migrate_info_up_cpu) +WEAK(psci_system_off) +WEAK(psci_system_reset) +WEAK(psci_features) +WEAK(psci_cpu_freeze) +WEAK(psci_cpu_default_suspend) +WEAK(psci_node_hw_state) +WEAK(psci_system_suspend) +WEAK(psci_set_suspend_mode) +WEAK(psi_stat_residency) +WEAK(psci_stat_count) mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) mov pc, lr ENDPROC(psci_stat_count) @@ -84,24 +82,6 @@ ENDPROC(psci_cpu_on) ENDPROC(psci_cpu_off) ENDPROC(psci_cpu_suspend) ENDPROC(psci_version) -.weak psci_version -.weak psci_cpu_suspend -.weak psci_cpu_off -.weak psci_cpu_on -.weak psci_affinity_info -.weak psci_migrate -.weak psci_migrate_info_type -.weak psci_migrate_info_up_cpu -.weak psci_system_off -.weak psci_system_reset -.weak psci_features -.weak psci_cpu_freeze -.weak psci_cpu_default_suspend -.weak psci_node_hw_state -.weak psci_system_suspend -.weak psci_set_suspend_mode -.weak psi_stat_residency -.weak psci_stat_count _psci_table: .word ARM_PSCI_FN_CPU_SUSPEND @@ -179,12 +159,11 @@ _smc_psci: movs pc, lr @ Return to the kernel @ Requires dense and single-cluster CPU ID space -ENTRY(psci_get_cpu_id) +WEAK(psci_get_cpu_id) mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */ and r0, r0, #0xff /* return CPU ID in cluster */ bx lr ENDPROC(psci_get_cpu_id) -.weak psci_get_cpu_id /* Imported from Linux kernel */ ENTRY(psci_v7_flush_dcache_all) @@ -236,7 +215,7 @@ finished: bx lr ENDPROC(psci_v7_flush_dcache_all) -ENTRY(psci_disable_smp) +WEAK(psci_disable_smp) mrc p15, 0, r0, c1, c0, 1 @ ACTLR bic r0, r0, #(1 << 6) @ Clear SMP bit mcr p15, 0, r0, c1, c0, 1 @ ACTLR @@ -244,16 +223,14 @@ ENTRY(psci_disable_smp) dsb bx lr ENDPROC(psci_disable_smp) -.weak psci_disable_smp -ENTRY(psci_enable_smp) +WEAK(psci_enable_smp) mrc p15, 0, r0, c1, c0, 1 @ ACTLR orr r0, r0, #(1 << 6) @ Set SMP bit mcr p15, 0, r0, c1, c0, 1 @ ACTLR isb bx lr ENDPROC(psci_enable_smp) -.weak psci_enable_smp ENTRY(psci_cpu_off_common) push {lr} @@ -316,15 +293,13 @@ ENTRY(psci_stack_setup) bx r6 ENDPROC(psci_stack_setup) -ENTRY(psci_arch_init) +WEAK(psci_arch_init) mov pc, lr ENDPROC(psci_arch_init) -.weak psci_arch_init -ENTRY(psci_arch_cpu_entry) +WEAK(psci_arch_cpu_entry) mov pc, lr ENDPROC(psci_arch_cpu_entry) -.weak psci_arch_cpu_entry ENTRY(psci_cpu_entry) bl psci_enable_smp diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index aef2e5574b4..5068327d3c5 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -7,12 +7,11 @@ #include <common.h> #include <errno.h> -#include <pwm.h> #include <asm/io.h> #include <asm/arch/pwm.h> #include <asm/arch/clk.h> -int pwm_enable(int pwm_id) +int s5p_pwm_enable(int pwm_id) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -30,7 +29,7 @@ int pwm_enable(int pwm_id) return 0; } -void pwm_disable(int pwm_id) +void s5p_pwm_disable(int pwm_id) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -92,7 +91,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) #define NS_IN_SEC 1000000000UL -int pwm_config(int pwm_id, int duty_ns, int period_ns) +int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -157,7 +156,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) return 0; } -int pwm_init(int pwm_id, int div, int invert) +int s5p_pwm_init(int pwm_id, int div, int invert) { u32 val; const struct s5p_timer *pwm = @@ -219,7 +218,7 @@ int pwm_init(int pwm_id, int div, int invert) val |= TCON_INVERTER(pwm_id); writel(val, &pwm->tcon); - pwm_enable(pwm_id); + s5p_pwm_enable(pwm_id); return 0; } diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 8533d04878c..f4a045e2f0d 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -16,10 +16,6 @@ #include <asm/arch/clk.h> #include <linux/delay.h> -/* Use the old PWM interface for now */ -#undef CONFIG_DM_PWM -#include <pwm.h> - DECLARE_GLOBAL_DATA_PTR; unsigned long get_current_tick(void); @@ -49,9 +45,9 @@ static unsigned long timer_get_us_down(void) int timer_init(void) { /* PWM Timer 4 */ - pwm_init(4, MUX_DIV_4, 0); - pwm_config(4, 100000, 100000); - pwm_enable(4); + s5p_pwm_init(4, MUX_DIV_4, 0); + s5p_pwm_config(4, 100000, 100000); + s5p_pwm_enable(4); /* Use this as the current monotonic time in us */ gd->arch.timer_reset_value = 0; diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 3baa761ec7a..fcaafc0ff76 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -13,10 +13,8 @@ #include <asm/io.h> #include <asm/arch/nexell.h> #include <asm/arch/clk.h> -#include <asm/arch/reset.h> #include <asm/arch/tieoff.h> #include <cpu_func.h> -#include <linux/delay.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,39 +43,12 @@ static void cpu_soc_init(void) nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1); } -#ifdef CONFIG_PL011_SERIAL -static void serial_device_init(void) -{ - char dev[10]; - int id; - - sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX); - id = RESET_ID_UART0 + CONFIG_CONS_INDEX; - - struct clk *clk = clk_get((const char *)dev); - - /* reset control: Low active ___|--- */ - nx_rstcon_setrst(id, RSTCON_ASSERT); - udelay(10); - nx_rstcon_setrst(id, RSTCON_NEGATE); - udelay(10); - - /* set clock */ - clk_disable(clk); - clk_set_rate(clk, CONFIG_PL011_CLOCK); - clk_enable(clk); -} -#endif - int arch_cpu_init(void) { flush_dcache_all(); cpu_soc_init(); clk_init(); - if (IS_ENABLED(CONFIG_PL011_SERIAL)) - serial_device_init(); - return 0; } diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 4f6327fe3ab..7d7aac021e2 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -151,16 +151,14 @@ ENDPROC(c_runtime_cpu_setup) * Don't save anything to stack even if compiled with -O0 * *************************************************************************/ -ENTRY(save_boot_params) +WEAK(save_boot_params) b save_boot_params_ret @ back to my caller ENDPROC(save_boot_params) - .weak save_boot_params #ifdef CONFIG_ARMV7_LPAE -ENTRY(switch_to_hypervisor) +WEAK(switch_to_hypervisor) b switch_to_hypervisor_ret ENDPROC(switch_to_hypervisor) - .weak switch_to_hypervisor #endif /************************************************************************* diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 5ffeca13d91..c82b215b6f9 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void) static unsigned long get_gicd_base_address(void) { -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; +#ifdef CFG_ARM_GIC_BASE_ADDRESS + return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else unsigned periphbase; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2862257e1f2..9656c52e955 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -29,6 +29,7 @@ config ARCH_LS1028A select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_LAYERSCAPE select FSL_LSCH3 + select FSL_TZASC_400 select GICV3 select NXP_LSCH3_2 select SYS_FSL_HAS_CCI400 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 99413ef52e2..5c45c2a5ed5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1058,9 +1058,6 @@ int cpu_eth_init(struct bd_info *bis) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) error = fsl_mc_ldpaa_init(bis); #endif -#ifdef CONFIG_FMAN_ENET - fm_standard_init(bis); -#endif return error; } @@ -1311,13 +1308,13 @@ phys_size_t get_effective_memsize(void) * allocated from first region. If the memory extends to the second * region (or the third region if applicable), Management Complex (MC) * memory should be put into the highest region, i.e. the end of DDR - * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so + * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so * U-Boot doesn't relocate itself into higher address. Should DDR be * configured to skip the first region, this function needs to be * adjusted. */ - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { - ea_size = CONFIG_MAX_MEM_MAPPED; + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { + ea_size = CFG_MAX_MEM_MAPPED; rem = gd->ram_size - ea_size; } else { ea_size = gd->ram_size; diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 7ffc8dbadbe..6aece119871 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -12,11 +12,10 @@ /* Default PSCI function, return -1, Not Implemented */ #define PSCI_DEFAULT(__fn) \ - ENTRY(__fn); \ + WEAK(__fn); \ mov w0, #ARM_PSCI_RET_NI; \ ret; \ ENDPROC(__fn); \ - .weak __fn /* PSCI function and ID table definition*/ #define PSCI_TABLE(__id, __fn) \ @@ -207,7 +206,7 @@ handle_smc64: * used for the return value, while in this PSCI environment, X0 usually holds * the SMC function identifier, so X0 should be saved by caller function. */ -ENTRY(psci_get_cpu_id) +WEAK(psci_get_cpu_id) #ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER mrs x9, MPIDR_EL1 ubfx x9, x9, #8, #8 @@ -221,7 +220,6 @@ ENTRY(psci_get_cpu_id) add x0, x10, x9 ret ENDPROC(psci_get_cpu_id) -.weak psci_get_cpu_id /* CPU ID input in x0, stack top output in x0*/ LENTRY(psci_get_cpu_stack_top) @@ -261,10 +259,9 @@ handle_sync: * Override this function if custom error handling is * needed for asynchronous aborts */ -ENTRY(plat_error_handler) +WEAK(plat_error_handler) ret ENDPROC(plat_error_handler) -.weak plat_error_handler handle_error: bl psci_get_cpu_id @@ -323,9 +320,8 @@ ENTRY(psci_setup_vectors) ret ENDPROC(psci_setup_vectors) -ENTRY(psci_arch_init) +WEAK(psci_arch_init) ret ENDPROC(psci_arch_init) -.weak psci_arch_init .popsection |