diff options
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/mp.c | 29 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 |
5 files changed, 33 insertions, 34 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 1e166c73e40..1a057f7059b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -10,7 +10,7 @@ config ARCH_LS1012A select SYS_HAS_SERDES select SYS_FSL_DDR_BE select SYS_FSL_MMDC - select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 @@ -77,7 +77,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009942 if !TFABOOT - select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -233,6 +233,7 @@ config ARCH_LS2080A config ARCH_LX2162A bool select ARMV8_SET_SMPEN + select FSL_LAYERSCAPE select FSL_LSCH3 select GICV3 select NXP_LSCH3_2 @@ -266,6 +267,7 @@ config ARCH_LX2162A config ARCH_LX2160A bool select ARMV8_SET_SMPEN + select FSL_LAYERSCAPE select FSL_LSCH3 select GICV3 select HAS_FSL_XHCI_USB if USB_HOST diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 6eb7f9c2148..4ec0dbf516d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -427,7 +427,7 @@ static void fdt_disable_multimedia(void *blob, unsigned int svr) fdt_status_disabled(blob, off); /* Disable GPU node */ - off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu"); + off = fdt_node_offset_by_compatible(blob, -1, "vivante,gc"); if (off != -FDT_ERR_NOTFOUND) fdt_status_disabled(blob, off); } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index 49df8b37900..86a49b152e4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -18,7 +18,7 @@ struct icid_id_table icid_tbl[] = { SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID), SET_EDMA_ICID(FSL_EDMA_STREAM_ID), SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), - SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), + SET_GPU_ICID("vivante,gc", FSL_GPU_STREAM_ID), SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), #ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 730d7663d0f..d28ab265335 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -14,11 +14,12 @@ #include <asm/system.h> #include <asm/arch/mp.h> #include <asm/arch/soc.h> +#include <linux/compat.h> #include <linux/delay.h> #include <linux/psci.h> +#include <malloc.h> #include "cpu.h" #include <asm/arch-fsl-layerscape/soc.h> -#include <efi_loader.h> DECLARE_GLOBAL_DATA_PTR; @@ -83,8 +84,7 @@ int fsl_layerscape_wake_seconday_cores(void) int i, timeout = 10; u64 *table; #ifdef CONFIG_EFI_LOADER - u64 reloc_addr = U32_MAX; - efi_status_t ret; + void *reloc_addr; #endif #ifdef COUNTER_FREQUENCY_REAL @@ -102,27 +102,26 @@ int fsl_layerscape_wake_seconday_cores(void) * Keep this after the __real_cntfrq update, so we have it when we * copy the complete section here. */ - ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, - EFI_RESERVED_MEMORY_TYPE, - efi_size_in_pages(secondary_boot_code_size), - &reloc_addr); - if (ret == EFI_SUCCESS) { - debug("Relocating spin table from %llx to %llx (size %lx)\n", - (u64)secondary_boot_code_start, reloc_addr, + reloc_addr = memalign(PAGE_SIZE, + round_up(secondary_boot_code_size, PAGE_SIZE)); + if (reloc_addr) { + debug("Relocating spin table from %p to %p (size %lx)\n", + secondary_boot_code_start, reloc_addr, secondary_boot_code_size); - memcpy((void *)reloc_addr, secondary_boot_code_start, + memcpy(reloc_addr, secondary_boot_code_start, secondary_boot_code_size); - flush_dcache_range(reloc_addr, - reloc_addr + secondary_boot_code_size); + flush_dcache_range((unsigned long)reloc_addr, + (unsigned long)reloc_addr + + secondary_boot_code_size); /* set new entry point for secondary cores */ - secondary_boot_addr += (void *)reloc_addr - + secondary_boot_addr += reloc_addr - secondary_boot_code_start; flush_dcache_range((unsigned long)&secondary_boot_addr, (unsigned long)&secondary_boot_addr + 8); /* this will be used to reserve the memory */ - secondary_boot_code_start = (void *)reloc_addr; + secondary_boot_code_start = reloc_addr; } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a08ed3f5440..d3a5cfaac19 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -929,25 +929,23 @@ __weak int fsl_board_late_init(void) #define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \ << DWC3_GSBUSCFG0_CACHETYPE_SHIFT) -void enable_dwc3_snooping(void) +static void enable_dwc3_snooping(void) { - int ret; - u32 val; - struct udevice *bus; - struct uclass *uc; + static const char * const compatibles[] = { + "fsl,layerscape-dwc3", + "fsl,ls1028a-dwc3", + }; fdt_addr_t dwc3_base; + ofnode node; + u32 val; + int i; - ret = uclass_get(UCLASS_USB, &uc); - if (ret) - return; - - uclass_foreach_dev(bus, uc) { - if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) { - dwc3_base = devfdt_get_addr(bus); - if (dwc3_base == FDT_ADDR_T_NONE) { - dev_err(bus, "dwc3 regs missing\n"); + for (i = 0; i < ARRAY_SIZE(compatibles); i++) { + ofnode_for_each_compatible_node(node, compatibles[i]) { + dwc3_base = ofnode_get_addr(node); + if (dwc3_base == FDT_ADDR_T_NONE) continue; - } + val = in_le32(dwc3_base + DWC3_GSBUSCFG0); val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0); val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222); |