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-rw-r--r--arch/arm/cpu/armv8/Kconfig11
-rw-r--r--arch/arm/cpu/armv8/Makefile4
-rw-r--r--arch/arm/cpu/armv8/exceptions.S132
-rw-r--r--arch/arm/cpu/armv8/start.S19
4 files changed, 112 insertions, 54 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 741e15c7737..c8bebabdf6f 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -1,5 +1,16 @@
if ARM64
+config ARMV8_SPL_EXCEPTION_VECTORS
+ bool "Install crash dump exception vectors"
+ depends on SPL
+ default y
+ help
+ The default exception vector table is only used for the crash
+ dump, but still takes quite a lot of space in the image size.
+
+ Say N here if you are running out of code space in the image
+ and want to save some space at the cost of less debugging info.
+
config ARMV8_MULTIENTRY
bool "Enable multiple CPUs to enter into U-Boot"
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index d1d4ffecfd2..52c8daa0496 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -10,7 +10,11 @@ ifndef CONFIG_$(SPL_TPL_)TIMER
obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
obj-y += cache_v8.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o
+else
obj-y += exceptions.o
+endif
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S
index 1a78a5d1dcc..a15af72e023 100644
--- a/arch/arm/cpu/armv8/exceptions.S
+++ b/arch/arm/cpu/armv8/exceptions.S
@@ -11,7 +11,26 @@
#include <linux/linkage.h>
/*
- * Exception vectors.
+ * AArch64 exception vectors:
+ * We have four types of exceptions:
+ * - synchronous: traps, data aborts, undefined instructions, ...
+ * - IRQ: group 1 (normal) interrupts
+ * - FIQ: group 0 or secure interrupts
+ * - SError: fatal system errors
+ * There are entries for all four of those for different contexts:
+ * - from same exception level, when using the SP_EL0 stack pointer
+ * - from same exception level, when using the SP_ELx stack pointer
+ * - from lower exception level, when this is AArch64
+ * - from lower exception level, when this is AArch32
+ * Each of those 16 entries have space for 32 instructions, each entry must
+ * be 128 byte aligned, the whole table must be 2K aligned.
+ * The 32 instructions are not enough to save and restore all registers and
+ * to branch to the actual handler, so we split this up:
+ * Each entry saves the LR, branches to the save routine, then to the actual
+ * handler, then to the restore routine. The save and restore routines are
+ * each split in half and stuffed in the unused gap between the entries.
+ * Also as we do not run anything in a lower exception level, we just provide
+ * the first 8 entries for exceptions from the same EL.
*/
.align 11
.globl vectors
@@ -22,52 +41,9 @@ vectors:
bl do_bad_sync
b exception_exit
- .align 7 /* Current EL IRQ Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_irq
- b exception_exit
-
- .align 7 /* Current EL FIQ Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_fiq
- b exception_exit
-
- .align 7 /* Current EL Error Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_error
- b exception_exit
-
- .align 7 /* Current EL Synchronous Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_sync
- b exception_exit
-
- .align 7 /* Current EL IRQ Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_irq
- b exception_exit
-
- .align 7 /* Current EL FIQ Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_fiq
- b exception_exit
-
- .align 7 /* Current EL Error Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_error
- b exception_exit
-
/*
- * Enter Exception.
- * This will save the processor state that is ELR/X0~X30
- * to the stack frame.
+ * Save (most of) the GP registers to the stack frame.
+ * This is the first part of the shared routine called into from all entries.
*/
_exception_entry:
stp x27, x28, [sp, #-16]!
@@ -84,7 +60,19 @@ _exception_entry:
stp x5, x6, [sp, #-16]!
stp x3, x4, [sp, #-16]!
stp x1, x2, [sp, #-16]!
+ b _save_el_regs /* jump to the second part */
+ .align 7 /* Current EL IRQ Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_irq
+ b exception_exit
+
+/*
+ * Save exception specific context: ESR and ELR, for all exception levels.
+ * This is the second part of the shared routine called into from all entries.
+ */
+_save_el_regs:
/* Could be running at EL3/EL2/EL1 */
switch_el x11, 3f, 2f, 1f
3: mrs x1, esr_el3
@@ -100,16 +88,36 @@ _exception_entry:
mov x0, sp
ret
-
+ .align 7 /* Current EL FIQ Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_fiq
+ /* falling through to _exception_exit */
+/*
+ * Restore the exception return address, for all exception levels.
+ * This is the first part of the shared routine called into from all entries.
+ */
exception_exit:
ldp x2, x0, [sp],#16
switch_el x11, 3f, 2f, 1f
3: msr elr_el3, x2
- b 0f
+ b _restore_regs
2: msr elr_el2, x2
- b 0f
+ b _restore_regs
1: msr elr_el1, x2
-0:
+ b _restore_regs /* jump to the second part */
+
+ .align 7 /* Current EL Error Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_error
+ b exception_exit
+
+/*
+ * Restore the general purpose registers from the exception stack, then return.
+ * This is the second part of the shared routine called into from all entries.
+ */
+_restore_regs:
ldp x1, x2, [sp],#16
ldp x3, x4, [sp],#16
ldp x5, x6, [sp],#16
@@ -126,3 +134,27 @@ exception_exit:
ldp x27, x28, [sp],#16
ldp x29, x30, [sp],#16
eret
+
+ .align 7 /* Current EL (SP_ELx) Synchronous Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_sync
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) IRQ Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_irq
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) FIQ Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_fiq
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) Error Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_error
+ b exception_exit
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index d4db4d044f6..12a78ee38b4 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -87,13 +87,22 @@ pie_fixup_done:
#ifdef CONFIG_SYS_RESET_SCTRL
bl reset_sctrl
#endif
+
+#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+.macro set_vbar, regname, reg
+ msr \regname, \reg
+.endm
+ adr x0, vectors
+#else
+.macro set_vbar, regname, reg
+.endm
+#endif
/*
* Could be EL3/EL2/EL1, Initial State:
* Little Endian, MMU Disabled, i/dCache Disabled
*/
- adr x0, vectors
switch_el x1, 3f, 2f, 1f
-3: msr vbar_el3, x0
+3: set_vbar vbar_el3, x0
mrs x0, scr_el3
orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
msr scr_el3, x0
@@ -103,11 +112,11 @@ pie_fixup_done:
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
#endif
b 0f
-2: msr vbar_el2, x0
+2: set_vbar vbar_el2, x0
mov x0, #0x33ff
msr cptr_el2, x0 /* Enable FP/SIMD */
b 0f
-1: msr vbar_el1, x0
+1: set_vbar vbar_el1, x0
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
@@ -345,6 +354,7 @@ ENDPROC(smp_kick_all_cpus)
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
+#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
@@ -354,6 +364,7 @@ ENTRY(c_runtime_cpu_setup)
b 0f
1: msr vbar_el1, x0
0:
+#endif
ret
ENDPROC(c_runtime_cpu_setup)
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-24 22:27:20 +0000