diff options
Diffstat (limited to 'arch/arm/dts/imx8mm-venice-gw71xx.dtsi')
| -rw-r--r-- | arch/arm/dts/imx8mm-venice-gw71xx.dtsi | 239 |
1 files changed, 0 insertions, 239 deletions
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx.dtsi deleted file mode 100644 index c557dbf4dcd..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - aliases { - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", - "", "dio1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */ - MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; -}; |