diff options
Diffstat (limited to 'arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi')
| -rw-r--r-- | arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi index 5a6f9b11b8e..a0285ce0520 100644 --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1 - * This file was generated on 07/17/2022 -*/ + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 + * This file was generated on 04/12/2023 + */ #define DDRSS_PLL_FHS_CNT 10 #define DDRSS_PLL_FREQUENCY_0 27500000 @@ -54,11 +54,11 @@ #define DDRSS_CTL_41_DATA 0x1B60008B #define DDRSS_CTL_42_DATA 0x2000422B #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x0400078A +#define DDRSS_CTL_44_DATA 0x040003C5 #define DDRSS_CTL_45_DATA 0x1E161104 -#define DDRSS_CTL_46_DATA 0x10012458 +#define DDRSS_CTL_46_DATA 0x1000922C #define DDRSS_CTL_47_DATA 0x1E161110 -#define DDRSS_CTL_48_DATA 0x10012458 +#define DDRSS_CTL_48_DATA 0x1000922C #define DDRSS_CTL_49_DATA 0x02030410 #define DDRSS_CTL_50_DATA 0x2C040500 #define DDRSS_CTL_51_DATA 0x082D2C2D @@ -71,11 +71,11 @@ #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 #define DDRSS_CTL_60_DATA 0x00001008 -#define DDRSS_CTL_61_DATA 0x000000CE +#define DDRSS_CTL_61_DATA 0x00000063 #define DDRSS_CTL_62_DATA 0x00000256 -#define DDRSS_CTL_63_DATA 0x00002073 +#define DDRSS_CTL_63_DATA 0x00001035 #define DDRSS_CTL_64_DATA 0x00000256 -#define DDRSS_CTL_65_DATA 0x00002073 +#define DDRSS_CTL_65_DATA 0x00001035 #define DDRSS_CTL_66_DATA 0x00000005 #define DDRSS_CTL_67_DATA 0x00040000 #define DDRSS_CTL_68_DATA 0x00950012 @@ -112,27 +112,27 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00003380 -#define DDRSS_CTL_103_DATA 0x00003380 -#define DDRSS_CTL_104_DATA 0x00003380 -#define DDRSS_CTL_105_DATA 0x00003380 -#define DDRSS_CTL_106_DATA 0x00003380 +#define DDRSS_CTL_102_DATA 0x000018C0 +#define DDRSS_CTL_103_DATA 0x000018C0 +#define DDRSS_CTL_104_DATA 0x000018C0 +#define DDRSS_CTL_105_DATA 0x000018C0 +#define DDRSS_CTL_106_DATA 0x000018C0 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x000005A2 -#define DDRSS_CTL_109_DATA 0x00081CC0 -#define DDRSS_CTL_110_DATA 0x00081CC0 -#define DDRSS_CTL_111_DATA 0x00081CC0 -#define DDRSS_CTL_112_DATA 0x00081CC0 -#define DDRSS_CTL_113_DATA 0x00081CC0 +#define DDRSS_CTL_108_DATA 0x000002B5 +#define DDRSS_CTL_109_DATA 0x00040D40 +#define DDRSS_CTL_110_DATA 0x00040D40 +#define DDRSS_CTL_111_DATA 0x00040D40 +#define DDRSS_CTL_112_DATA 0x00040D40 +#define DDRSS_CTL_113_DATA 0x00040D40 #define DDRSS_CTL_114_DATA 0x00000000 -#define DDRSS_CTL_115_DATA 0x0000E325 -#define DDRSS_CTL_116_DATA 0x00081CC0 -#define DDRSS_CTL_117_DATA 0x00081CC0 -#define DDRSS_CTL_118_DATA 0x00081CC0 -#define DDRSS_CTL_119_DATA 0x00081CC0 -#define DDRSS_CTL_120_DATA 0x00081CC0 +#define DDRSS_CTL_115_DATA 0x00007173 +#define DDRSS_CTL_116_DATA 0x00040D40 +#define DDRSS_CTL_117_DATA 0x00040D40 +#define DDRSS_CTL_118_DATA 0x00040D40 +#define DDRSS_CTL_119_DATA 0x00040D40 +#define DDRSS_CTL_120_DATA 0x00040D40 #define DDRSS_CTL_121_DATA 0x00000000 -#define DDRSS_CTL_122_DATA 0x0000E325 +#define DDRSS_CTL_122_DATA 0x00007173 #define DDRSS_CTL_123_DATA 0x00000000 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x00000000 @@ -399,29 +399,29 @@ #define DDRSS_CTL_386_DATA 0x00000000 #define DDRSS_CTL_387_DATA 0x3A3A1B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x0000019C +#define DDRSS_CTL_389_DATA 0x000000C6 #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x000004D4 -#define DDRSS_CTL_395_DATA 0x00001018 +#define DDRSS_CTL_394_DATA 0x00000252 +#define DDRSS_CTL_395_DATA 0x000007BC #define DDRSS_CTL_396_DATA 0x00000204 -#define DDRSS_CTL_397_DATA 0x000040E6 +#define DDRSS_CTL_397_DATA 0x0000206A #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x00000200 #define DDRSS_CTL_400_DATA 0x00000200 #define DDRSS_CTL_401_DATA 0x00000200 -#define DDRSS_CTL_402_DATA 0x0000C2B2 -#define DDRSS_CTL_403_DATA 0x000288FC +#define DDRSS_CTL_402_DATA 0x0000613E +#define DDRSS_CTL_403_DATA 0x00014424 #define DDRSS_CTL_404_DATA 0x00000E15 -#define DDRSS_CTL_405_DATA 0x000040E6 +#define DDRSS_CTL_405_DATA 0x0000206A #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 #define DDRSS_CTL_409_DATA 0x00000200 -#define DDRSS_CTL_410_DATA 0x0000C2B2 -#define DDRSS_CTL_411_DATA 0x000288FC +#define DDRSS_CTL_410_DATA 0x0000613E +#define DDRSS_CTL_411_DATA 0x00014424 #define DDRSS_CTL_412_DATA 0x02020E15 #define DDRSS_CTL_413_DATA 0x03030202 #define DDRSS_CTL_414_DATA 0x00000022 @@ -640,11 +640,11 @@ #define DDRSS_PI_167_DATA 0x02000200 #define DDRSS_PI_168_DATA 0x48120C04 #define DDRSS_PI_169_DATA 0x00104812 -#define DDRSS_PI_170_DATA 0x000000CE +#define DDRSS_PI_170_DATA 0x00000063 #define DDRSS_PI_171_DATA 0x00000256 -#define DDRSS_PI_172_DATA 0x00002073 +#define DDRSS_PI_172_DATA 0x00001035 #define DDRSS_PI_173_DATA 0x00000256 -#define DDRSS_PI_174_DATA 0x04002073 +#define DDRSS_PI_174_DATA 0x04001035 #define DDRSS_PI_175_DATA 0x01010404 #define DDRSS_PI_176_DATA 0x00001501 #define DDRSS_PI_177_DATA 0x00150015 @@ -689,22 +689,22 @@ #define DDRSS_PI_216_DATA 0x3212005B #define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x040006C9 +#define DDRSS_PI_219_DATA 0x04000364 #define DDRSS_PI_220_DATA 0x0A032001 #define DDRSS_PI_221_DATA 0x2C31110A #define DDRSS_PI_222_DATA 0x00002D1C -#define DDRSS_PI_223_DATA 0x6001071C +#define DDRSS_PI_223_DATA 0x6000838E #define DDRSS_PI_224_DATA 0x1E202008 #define DDRSS_PI_225_DATA 0x2C311116 #define DDRSS_PI_226_DATA 0x00002D1C -#define DDRSS_PI_227_DATA 0x6001071C +#define DDRSS_PI_227_DATA 0x6000838E #define DDRSS_PI_228_DATA 0x1E202008 -#define DDRSS_PI_229_DATA 0x00019C16 -#define DDRSS_PI_230_DATA 0x00001018 -#define DDRSS_PI_231_DATA 0x000040E6 -#define DDRSS_PI_232_DATA 0x000288FC -#define DDRSS_PI_233_DATA 0x000040E6 -#define DDRSS_PI_234_DATA 0x000288FC +#define DDRSS_PI_229_DATA 0x0000C616 +#define DDRSS_PI_230_DATA 0x000007BC +#define DDRSS_PI_231_DATA 0x0000206A +#define DDRSS_PI_232_DATA 0x00014424 +#define DDRSS_PI_233_DATA 0x0000206A +#define DDRSS_PI_234_DATA 0x00014424 #define DDRSS_PI_235_DATA 0x02660010 #define DDRSS_PI_236_DATA 0x03030266 #define DDRSS_PI_237_DATA 0x002AF803 |