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Diffstat (limited to 'arch/arm/dts/mt7981.dtsi')
-rw-r--r--arch/arm/dts/mt7981.dtsi124
1 files changed, 61 insertions, 63 deletions
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 7aaa7770f83..a9991a121f1 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -98,14 +98,6 @@
bootph-all;
};
- infracfg_ao: infracfg_ao@10001000 {
- compatible = "mediatek,mt7981-infracfg_ao";
- reg = <0x10001000 0x80>;
- clock-parent = <&infracfg>;
- #clock-cells = <1>;
- bootph-all;
- };
-
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7981-infracfg";
reg = <0x10001000 0x30>;
@@ -140,14 +132,13 @@
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_PWM>,
- <&infracfg_ao CK_INFRA_PWM_BSEL>,
- <&infracfg_ao CK_INFRA_PWM1_CK>,
- <&infracfg_ao CK_INFRA_PWM2_CK>,
- /* FIXME */
- <&infracfg_ao CK_INFRA_PWM2_CK>;
- assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>,
+ <&infracfg CLK_INFRA_PWM3_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};
@@ -158,8 +149,8 @@
<0x10217080 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
- <&infracfg_ao CK_INFRA_AP_DMA_CK>;
+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+ <&infracfg CLK_INFRA_AP_DMA_CK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -170,11 +161,11 @@
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
bootph-all;
@@ -184,11 +175,11 @@
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART1_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -197,11 +188,11 @@
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -211,14 +202,14 @@
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
- clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+ <&infracfg CLK_INFRA_NFI1_CK>,
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
+ <&topckgen CLK_TOP_CB_M_D8>;
status = "disabled";
};
@@ -244,14 +235,14 @@
};
sgmiisys0: syscon@10060000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
reg = <0x10060000 0x1000>;
pn_swap;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
reg = <0x10070000 0x1000>;
#clock-cells = <1>;
};
@@ -265,13 +256,13 @@
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
- clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_INFRA_ISPI0>;
- clock-names = "sel-clk", "spi-clk";
+ clocks = <&infracfg CLK_INFRA_SPI0_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ clock-names = "spi-clk", "sel-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -280,19 +271,26 @@
compatible = "mediatek,ipm-spi";
reg = <0x1100b000 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_SPI1_CK>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
+ clock-names = "spi-clk", "sel-clk";
status = "disabled";
};
spi2: spi@11009000 {
compatible = "mediatek,ipm-spi";
reg = <0x11009000 0x100>;
- clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_INFRA_ISPI0>;
- clock-names = "sel-clk", "spi-clk";
+ clocks = <&infracfg CLK_INFRA_SPI2_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ clock-names = "spi-clk", "sel-clk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -302,13 +300,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_EMMC_400M>,
- <&topckgen CK_TOP_EMMC_208M>,
- <&infracfg_ao CK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
- <&topckgen CK_TOP_EMMC_208M_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
- <&topckgen CK_TOP_CB_M_D2>;
+ clocks = <&topckgen CLK_TOP_EMMC_400M>,
+ <&topckgen CLK_TOP_EMMC_208M>,
+ <&infracfg CLK_INFRA_MSDC_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
+ <&topckgen CLK_TOP_EMMC_208M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
+ <&topckgen CLK_TOP_CB_M_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-26 17:36:27 +0000