diff options
Diffstat (limited to 'arch/arm/dts/stm32f746-disco-u-boot.dtsi')
| -rw-r--r-- | arch/arm/dts/stm32f746-disco-u-boot.dtsi | 103 |
1 files changed, 26 insertions, 77 deletions
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 522cffb1ac9..1b42d6cbbc1 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -23,12 +23,6 @@ spi0 = &qspi; }; - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpiok 3 0>; - status = "okay"; - }; - button1 { compatible = "st,button1"; button-gpio = <&gpioi 11 0>; @@ -38,44 +32,11 @@ compatible = "st,led1"; led-gpio = <&gpioi 1 0>; }; +}; - panel-rgb@0 { - compatible = "simple-panel"; - backlight = <&backlight>; - enable-gpios = <&gpioi 12 0>; - status = "okay"; - - display-timings { - timing@0 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - soc { - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - resets = <&rcc STM32F7_APB2_RESET(LTDC)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; - pinctrl-0 = <<dc_pins>; - - status = "okay"; - bootph-all; - }; - }; +<dc { + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; + bootph-all; }; &fmc { @@ -102,6 +63,28 @@ }; }; +&panel_rgb { + compatible = "simple-panel"; + + display-timings { + timing@0 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <2>; + hback-porch = <2>; + hsync-len = <41>; + vfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; +}; + &pinctrl { ethernet_mii: mii@0 { pins { @@ -166,40 +149,6 @@ }; }; - ltdc_pins: ltdc@0 { - pins { - pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */ - <STM32_PINMUX('G',12, AF9)>, /* B4 */ - <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */ - <STM32_PINMUX('I',10, AF14)>, /* HSYNC */ - <STM32_PINMUX('I',14, AF14)>, /* CLK */ - <STM32_PINMUX('I',15, AF14)>, /* R0 */ - <STM32_PINMUX('J', 0, AF14)>, /* R1 */ - <STM32_PINMUX('J', 1, AF14)>, /* R2 */ - <STM32_PINMUX('J', 2, AF14)>, /* R3 */ - <STM32_PINMUX('J', 3, AF14)>, /* R4 */ - <STM32_PINMUX('J', 4, AF14)>, /* R5 */ - <STM32_PINMUX('J', 5, AF14)>, /* R6 */ - <STM32_PINMUX('J', 6, AF14)>, /* R7 */ - <STM32_PINMUX('J', 7, AF14)>, /* G0 */ - <STM32_PINMUX('J', 8, AF14)>, /* G1 */ - <STM32_PINMUX('J', 9, AF14)>, /* G2 */ - <STM32_PINMUX('J',10, AF14)>, /* G3 */ - <STM32_PINMUX('J',11, AF14)>, /* G4 */ - <STM32_PINMUX('J',13, AF14)>, /* B1 */ - <STM32_PINMUX('J',14, AF14)>, /* B2 */ - <STM32_PINMUX('J',15, AF14)>, /* B3 */ - <STM32_PINMUX('K', 0, AF14)>, /* G5 */ - <STM32_PINMUX('K', 1, AF14)>, /* G6 */ - <STM32_PINMUX('K', 2, AF14)>, /* G7 */ - <STM32_PINMUX('K', 4, AF14)>, /* B5 */ - <STM32_PINMUX('K', 5, AF14)>, /* B6 */ - <STM32_PINMUX('K', 6, AF14)>, /* B7 */ - <STM32_PINMUX('K', 7, AF14)>; /* DE */ - slew-rate = <2>; - }; - }; - qspi_pins: qspi@0 { pins { pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */ |