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Diffstat (limited to 'arch/arm/dts/zynqmp.dtsi')
-rw-r--r--arch/arm/dts/zynqmp.dtsi146
1 files changed, 138 insertions, 8 deletions
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 6a29f610153..0e0436ecce8 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -18,6 +18,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "xlnx,zynqmp";
@@ -36,6 +37,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
+ #cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
@@ -46,6 +48,7 @@
};
cpu1: cpu@1 {
+ #cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
@@ -56,6 +59,7 @@
};
cpu2: cpu@2 {
+ #cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
@@ -66,6 +70,7 @@
};
cpu3: cpu@3 {
+ #cooling-cells = <2>;
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
@@ -168,8 +173,8 @@
bootph-all;
};
- pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
@@ -388,6 +393,102 @@
};
};
+ ams: ams {
+ compatible = "iio-hwmon";
+ status = "disabled";
+ io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
+ <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
+ <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
+ <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
+ <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
+ <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
+ <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
+ <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
+ <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
+ <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
+ };
+
+
+ tsens_apu: thermal-sensor-apu {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&xilinx_ams 7>;
+ io-channel-names = "sensor-channel";
+ };
+
+ tsens_rpu: thermal-sensor-rpu {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&xilinx_ams 8>;
+ io-channel-names = "sensor-channel";
+ };
+
+ tsens_pl: thermal-sensor-pl {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&xilinx_ams 20>;
+ io-channel-names = "sensor-channel";
+ };
+
+ thermal-zones {
+ apu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tsens_apu>;
+
+ trips {
+ apu_passive: passive {
+ temperature = <93000>;
+ hysteresis = <3500>;
+ type = "passive";
+ };
+
+ apu_critical: critical {
+ temperature = <96500>;
+ hysteresis = <3500>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&apu_passive>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ rpu-thermal {
+ polling-delay = <10000>;
+ thermal-sensors = <&tsens_rpu>;
+
+ trips {
+ critical {
+ temperature = <96500>;
+ hysteresis = <3500>;
+ type = "critical";
+ };
+ };
+ };
+
+ pl-thermal {
+ polling-delay = <10000>;
+ thermal-sensors = <&tsens_pl>;
+
+ trips {
+ critical {
+ temperature = <96500>;
+ hysteresis = <3500>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
amba: axi {
compatible = "simple-bus";
bootph-all;
@@ -441,6 +542,34 @@
};
};
+ cpu0_debug: debug@fec10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfec10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
+
+ cpu1_debug: debug@fed10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfed10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ };
+
+ cpu2_debug: debug@fee10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfee10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ };
+
+ cpu3_debug: debug@fef10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfef10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ };
+
/* GDMA */
fpd_dma_chan1: dma-controller@fd500000 {
status = "disabled";
@@ -885,7 +1014,6 @@
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
- /* dma-coherent; */
};
sdhci0: mmc@ff160000 {
@@ -1065,9 +1193,9 @@
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ref";
/* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
- clock-names = "ref";
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -1097,9 +1225,9 @@
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ref";
/* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
- clock-names = "ref";
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -1126,7 +1254,6 @@
xilinx_ams: ams@ffa50000 {
compatible = "xlnx,zynqmp-ams";
- status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xffa50000 0x0 0x800>;
@@ -1176,11 +1303,14 @@
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
- dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dma-names = "vid0", "vid1", "vid2", "gfx0",
+ "aud0", "aud1";
dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
- <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+ <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>;
ports {
#address-cells = <1>;
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-02 21:54:32 +0000