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Diffstat (limited to 'arch/arm/dts/zynqmp.dtsi')
-rw-r--r--arch/arm/dts/zynqmp.dtsi35
1 files changed, 23 insertions, 12 deletions
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 6a166381fa7..1632be843b1 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -4,7 +4,7 @@
*
* (C) Copyright 2014 - 2021, Xilinx, Inc.
*
- * Michal Simek <michal.simek@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -33,6 +33,7 @@
operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -42,6 +43,7 @@
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@@ -51,6 +53,7 @@
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@@ -60,6 +63,13 @@
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
idle-states {
@@ -111,7 +121,7 @@
#size-cells = <2>;
ranges;
- ipi_mailbox_pmu1: mailbox@ff990400 {
+ ipi_mailbox_pmu1: mailbox@ff9905c0 {
bootph-all;
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
@@ -139,6 +149,10 @@
<0 144 4>,
<0 145 4>,
<0 146 4>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
};
psci {
@@ -179,7 +193,6 @@
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
- clock-names = "ref_clk";
};
xlnx_aes: zynqmp-aes {
@@ -396,12 +409,12 @@
gpu: gpu@fd4b0000 {
status = "disabled";
- compatible = "arm,mali-400", "arm,mali-utgard";
+ compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
- interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
- clock-names = "gpu", "gpu_pp0", "gpu_pp1";
+ interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
+ clock-names = "bus", "core";
power-domains = <&zynqmp_firmware PD_GPU>;
};
@@ -611,6 +624,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
+ clock-frequency = <400000>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -622,6 +636,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
+ clock-frequency = <400000>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -876,7 +891,6 @@
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
- snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
snps,resume-hs-terminations;
@@ -908,7 +922,6 @@
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
- snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
snps,resume-hs-terminations;
@@ -940,21 +953,19 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 56 4>;
- interrupt-names = "ams-irq";
reg = <0x0 0xffa50000 0x0 0x800>;
- reg-names = "ams-base";
#address-cells = <1>;
#size-cells = <1>;
#io-channel-cells = <1>;
ranges = <0 0 0xffa50800 0x800>;
- ams_ps: ams_ps@0 {
+ ams_ps: ams-ps@0 {
compatible = "xlnx,zynqmp-ams-ps";
status = "disabled";
reg = <0x0 0x400>;
};
- ams_pl: ams_pl@400 {
+ ams_pl: ams-pl@400 {
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
reg = <0x400 0x400>;