diff options
Diffstat (limited to 'arch/arm/dts')
48 files changed, 735 insertions, 131 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 56d4af518d8..b3fe3f3c535 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -262,11 +262,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-m-a2197-02-revA.dtb \ zynqmp-m-a2197-03-revA.dtb \ zynqmp-p-a2197-00-revA.dtb \ - zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo \ - zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo \ - zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo \ - zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo \ - zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ @@ -281,22 +276,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-qspi-x2-stacked.dtb \ zynqmp-sc-revB.dtb \ zynqmp-sc-revC.dtb \ - zynqmp-sc-vek280-revA.dtbo \ - zynqmp-sc-vek280-revB.dtbo \ - zynqmp-sc-vhk158-revA.dtbo \ - zynqmp-sc-vpk120-revB.dtbo \ - zynqmp-sc-vpk180-revA.dtbo \ - zynqmp-sc-vpk180-revB.dtbo \ - zynqmp-sc-vn-p-b2197-00-revA.dtbo \ zynqmp-sm-k24-revA.dtb \ zynqmp-smk-k24-revA.dtb \ zynqmp-sm-k26-revA.dtb \ zynqmp-smk-k26-revA.dtb \ - zynqmp-sck-kd-g-revA.dtbo \ - zynqmp-sck-kr-g-revA.dtbo \ - zynqmp-sck-kr-g-revB.dtbo \ - zynqmp-sck-kv-g-revA.dtbo \ - zynqmp-sck-kv-g-revB.dtbo \ zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \ zynqmp-vpk120-revA.dtb \ zynqmp-vp-x-a2785-00-revA.dtb \ @@ -324,6 +307,67 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zc1751-xm017-dc3.dtb \ zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb + +zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo +zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo +zynqmp-p-a2197-00-revA-x-prc-03-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo +zynqmp-p-a2197-00-revA-x-prc-04-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo +zynqmp-p-a2197-00-revA-x-prc-05-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo + +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-01-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-02-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb + +zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo +zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo +zynqmp-sc-vhk158-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vhk158-revA.dtbo +zynqmp-sc-vpk120-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk120-revB.dtbo +zynqmp-sc-vpk180-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revA.dtbo +zynqmp-sc-vpk180-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revB.dtbo +zynqmp-sc-vn-p-b2197-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vn-p-b2197-00-revA.dtbo + +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vhk158-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk120-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vn-p-b2197-00-revA.dtb + +zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo +zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo +zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo +zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo + +zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo + +zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo +zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo +zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo +zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo +zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo +zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo + +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini.dtb \ versal-mini-emmc0.dtb \ @@ -812,6 +856,7 @@ dtb-y += \ imx6q-icore-rqs.dtb \ imx6q-kp.dtb \ imx6q-logicpd.dtb \ + imx6q-lxr.dtb \ imx6q-marsboard.dtb \ imx6q-mccmon6.dtb\ imx6q-nitrogen6x.dtb \ diff --git a/arch/arm/dts/imx6q-lxr.dts b/arch/arm/dts/imx6q-lxr.dts new file mode 100644 index 00000000000..ae4f8eeb105 --- /dev/null +++ b/arch/arm/dts/imx6q-lxr.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2024 Comvetia AG + +/dts-v1/; +#include "imx6q-phytec-pfla02.dtsi" + +/ { + model = "COMVETIA QSoIP LXR-2"; + compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q"; + + chosen { + stdout-path = &uart4; + }; + + spi { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi_gpio>; + sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + num-chipselects = <0>; + #address-cells = <1>; + #size-cells = <0>; + + fpga@0 { + compatible = "altr,fpga-passive-serial"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fpga>; + nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usdhc3 { + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_fpga: fpgagrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 + >; + }; + + pinctrl_spi_gpio: spigpiogrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi new file mode 100644 index 00000000000..500944bd2a0 --- /dev/null +++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + */ + +#include "imx6q.dtsi" +#include "imx6qdl-phytec-pfla02.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 Quad"; + compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi new file mode 100644 index 00000000000..c0c47adc586 --- /dev/null +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Phytec phyFLEX-i.MX6 Quad"; + compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 0>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 0>; + enable-active-high; + }; + + gpio_leds: leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + compatible = "gpio-leds"; + + led_green: led-green { + label = "phyflex:green"; + gpios = <&gpio1 30 0>; + }; + + led_red: led-red { + label = "phyflex:red"; + gpios = <&gpio2 31 0>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + + som_flash: flash@0 { + compatible = "m25p80", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; /* in msecs */ + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + phy-supply = <&vdd_eth_io_reg>; + status = "disabled"; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + txc-skew-ps = <1680>; + rxc-skew-ps = <1860>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + som_eeprom: eeprom@50 { + compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + pmic@58 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ + #interrupt-cells = <2>; + interrupt-controller; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_buckmem_reg: bmem { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_eth_reg: bio { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_eth_io_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_3v3_pmic_io_reg: ldo6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_sd0_reg: ldo9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd1_reg: ldo10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_mx6_high_reg: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + + da9063_rtc: rtc { + compatible = "dlg,da9063-rtc"; + }; + + da9063_wdog: watchdog { + compatible = "dlg,da9063-watchdog"; + }; + + onkey { + compatible = "dlg,da9063-onkey"; + status = "disabled"; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; +}; + +&iomuxc { + imx6q-phytec-pfla02 { + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */ + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1_vbus: usbh1vbusgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_sd1_reg>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_sd0_reg>; + status = "disabled"; +}; + +&wdog1 { + /* + * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also + * used for reboot, does not reset all external PMIC voltages on reset. + */ + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index c02e11def5f..d31bc822532 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -122,6 +122,7 @@ binman_imx_fit: fit { description = "Configuration to load ATF before U-Boot"; + filename = "u-boot.itb"; #ifndef CONFIG_IMX_HAB fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; #endif diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 732191f5205..6875c6d44ff 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -193,6 +193,7 @@ binman_imx_fit: fit { description = "Configuration to load ATF before U-Boot"; + filename = "u-boot.itb"; #ifndef CONFIG_IMX_HAB fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; #endif diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index f2655a4d0c8..56749ccacd2 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -148,6 +148,7 @@ binman_imx_fit: fit { description = "Configuration to load ATF before U-Boot"; + filename = "u-boot.itb"; #ifndef CONFIG_IMX_HAB fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; #endif diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index e1cd6f8996d..d7a83a78f4d 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -106,11 +106,14 @@ binman_imx_fit: fit { description = "Configuration to load ATF before U-Boot"; + filename = "u-boot.itb"; #ifndef CONFIG_IMX_HAB fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; #endif #address-cells = <1>; + offset = <0x57c00>; + images { uboot { arch = "arm64"; diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi index 884f44239e1..27851b7d083 100644 --- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -64,6 +64,10 @@ bootph-all; }; +&chipid { + bootph-all; +}; + &mcu_ringacc { reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index cc8becac996..f60eba531e4 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -8,7 +8,6 @@ #include "r8a779x-u-boot.dtsi" &rpc { - reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; bank-width = <2>; num-cs = <1>; }; diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index a102639010d..c3704d789e8 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -13,29 +13,9 @@ }; }; -&pfc { - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; -}; - &rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <40000000>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25fs512s", "jedec,spi-nor"; - reg = <0>; + flash@0 { spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; - spi-max-frequency = <40000000>; }; }; diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index 60b1c0e1fc4..b98ed16bc5f 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -28,7 +28,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <0x2>; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index 751cc38ee5c..e6a5c2b699e 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -28,7 +28,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <0x2>; diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 8735292a127..9ca0cf3c027 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -28,7 +28,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <0x2>; diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi index 9347ea32c9c..57427e099f9 100644 --- a/arch/arm/dts/versal-mini-qspi.dtsi +++ b/arch/arm/dts/versal-mini-qspi.dtsi @@ -28,7 +28,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <0x2>; diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 18f627f3d72..f1fb15902a7 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -31,7 +31,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index a5c8a0813ff..8e60d17b944 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -31,7 +31,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi index 2e4afafebf5..3b7e6c79874 100644 --- a/arch/arm/dts/zynq-cse-qspi.dtsi +++ b/arch/arm/dts/zynq-cse-qspi.dtsi @@ -32,7 +32,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 2076271ac99..293d8e97b63 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -87,7 +87,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; @@ -118,7 +117,7 @@ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 0b97fa3f28a..4e0587fd441 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -155,7 +155,6 @@ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; - is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 36a0db44fd2..c439f778ca4 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -80,7 +80,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; - is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; @@ -112,7 +111,7 @@ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ - "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ + "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 83b8a98d80c..d6cd193a449 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -101,7 +101,7 @@ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ - status = "disable"; + status = "disabled"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; @@ -140,9 +140,9 @@ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ - "", "", "", "", "", /* 78 - 79 */ + "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ @@ -300,7 +300,7 @@ i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; - /* reg = <3>; */ + reg = <3>; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; @@ -365,25 +365,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index dd37b726d3d..902fdd4de6c 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -97,7 +97,7 @@ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ - status = "disable"; + status = "disabled"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; @@ -135,9 +135,9 @@ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ - "", "", "", "", "", /* 78 - 79 */ + "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ @@ -288,7 +288,7 @@ i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; - /* reg = <3>; */ + reg = <3>; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; @@ -367,25 +367,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 811cebafe9e..f3994bca4a0 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -97,7 +97,7 @@ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ - status = "disable"; + status = "disabled"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; @@ -135,9 +135,9 @@ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ - "", "", "", "", "", /* 78 - 79 */ + "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ @@ -292,7 +292,7 @@ i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; - /* reg = <3>; */ + reg = <3>; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; @@ -361,25 +361,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index 7823c58cb27..cf2219797a5 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -41,13 +41,13 @@ clock-frequency = <200000000>; }; - amba: amba { + amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; - sdhci0: sdhci@ff160000 { + sdhci0: mmc@ff160000 { bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 2f6ba95073a..4c9f56a8076 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -41,13 +41,13 @@ clock-frequency = <200000000>; }; - amba: amba { + amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; - sdhci1: sdhci@ff170000 { + sdhci1: mmc@ff170000 { bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index e08a7840d8e..5e2135158cd 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -35,7 +35,7 @@ bootph-all; }; - amba: amba { + amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index e35317f3e2d..917603dec61 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -36,7 +36,13 @@ bootph-all; }; - amba: amba { + misc_clk: misc-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; @@ -52,19 +58,13 @@ #address-cells = <1>; #size-cells = <0>; }; - - misc_clk: misc-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; }; }; &qspi { status = "okay"; flash0: flash@0 { - compatible = "n25q512a11", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso index 197dc252353..82cc383dc4c 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso @@ -33,25 +33,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso index 8eb6e40dd9d..11b15447246 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso @@ -33,25 +33,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso index af7a3ce9c1a..9b4c8b3520d 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso @@ -33,25 +33,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso index 29a6c2a627b..1b1bb365080 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso @@ -33,25 +33,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso index 6ddf18cf643..8c16286a033 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso @@ -33,25 +33,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 5a60b86a574..ae52e8e996a 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -90,7 +90,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; @@ -121,7 +120,7 @@ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ - "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ + "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ @@ -427,25 +426,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index c1d713b5d89..1fcb5bfb928 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -104,7 +104,7 @@ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso index 5333767361f..620afba06e6 100644 --- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso @@ -115,25 +115,25 @@ #gpio-cells = <2>; gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4", "", "", "", ""; - gtr-sel0 { + gtr-sel0-hog { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "xprc_sw_1"; }; - gtr-sel1 { + gtr-sel1-hog { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "xprc_sw_1"; }; - gtr-sel2 { + gtr-sel2-hog { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "xprc_sw_1"; }; - gtr-sel3 { + gtr-sel3-hog { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso index 18625933ad3..ba5484573c9 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso @@ -16,6 +16,12 @@ &{/} { compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA", "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + + vc7_xin: vc7-xin { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <50000000>; + }; }; &i2c0 { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index ce7c5eb6d34..6349a0e1087 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -195,7 +195,6 @@ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; - is-internal-pcspma; assigned-clock-rates = <250000000>; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 0a0cbd2b69a..b0d737d3caf 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -216,7 +216,6 @@ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; - is-internal-pcspma; assigned-clock-rates = <250000000>; }; diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index b626d1aacf5..7849f8c540b 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -117,7 +117,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index e0632883e4e..4768fac71d0 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -118,7 +118,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts index a9b5826a777..f1ec314fdef 100644 --- a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts @@ -11,6 +11,6 @@ / { model = "ZynqMP ZCU106 Rev1.0"; - compatible = "xlnx,zynqmp-zcu106-rev1.0", "xlnx,zynqmp-zcu106-revA", + compatible = "xlnx,zynqmp-zcu106-rev1.0", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 787cf0d87f9..3a1580dfc40 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -494,7 +494,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <5>; - sc18is603@2f { /* sc18is602 - u93 */ + sc18is603: spi@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 4060dc3613a..ed83ba32791 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -43,6 +43,7 @@ &gem1 { status = "okay"; + phy-mode = "rgmii-id"; mdio { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index a113e475082..88536e917d9 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -68,7 +68,7 @@ compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; - ina226-vccint-io-bram-ps { + ina226-vccint-io-bram { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; @@ -205,7 +205,7 @@ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 4d7d5d2e5ef..29087aa7cb9 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -68,7 +68,7 @@ compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; - ina226-vccint-io-bram-ps { + ina226-vccint-io-bram { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; @@ -211,7 +211,7 @@ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts index def3b53cef7..2928ebe56fc 100644 --- a/arch/arm/dts/zynqmp-zcu670-revA.dts +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -71,7 +71,7 @@ compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; - ina226-vccint-io-bram-ps { + ina226-vccint-io-bram { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts index 41f9a23d06a..1a99d1e08fb 100644 --- a/arch/arm/dts/zynqmp-zcu670-revB.dts +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -71,7 +71,7 @@ compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; - ina226-vccint-io-bram-ps { + ina226-vccint-io-bram { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; |