diff options
Diffstat (limited to 'arch/arm/dts')
27 files changed, 1392 insertions, 1422 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aec5020a0f9..a5cae010c26 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -236,7 +236,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ - armada-xp-theadorable.dtb + armada-xp-theadorable.dtb \ + cn9130-crb-A.dtb \ + cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ uniphier-ld11-global.dtb \ diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 1b1b66b94de..42e7ddd25c5 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -70,13 +70,13 @@ &comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_2_5G>; }; }; diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index 96a4b3d95b8..d86d8f0b63c 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -83,18 +83,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_2_5G>; }; phy2 { - phy-type = <PHY_TYPE_SATA0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA0>; + phy-speed = <COMPHY_SPEED_5G>; }; }; diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 974270cc8c6..8e0ebf508d4 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -73,18 +73,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_3_125G>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; }; diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 7f4b8222f4a..4b30f3cea8c 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -108,18 +108,19 @@ &comphy { phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; }; - phy1 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_3_125G>; - }; - - phy2 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; - }; }; ð0 { diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts index 3a9df21a8c2..ccf470b317f 100644 --- a/arch/arm/dts/armada-7040-db-nand.dts +++ b/arch/arm/dts/armada-7040-db-nand.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */ /* @@ -58,8 +21,8 @@ }; aliases { - i2c0 = &cpm_i2c0; - spi0 = &cpm_spi1; + i2c0 = &cp0_i2c0; + spi0 = &cp0_spi1; }; memory@00000000 { @@ -83,18 +46,18 @@ }; -&cpm_pcie2 { +&cp0_pcie2 { status = "okay"; }; -&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; }; -&cpm_pinctl { +&cp0_pinctl { /* MPP Bus: * AUDIO [0-5] * GBE [6-11] @@ -122,9 +85,9 @@ 0xe 0xe 0x0>; }; -&cpm_spi1 { +&cp0_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_spi0_pins>; + pinctrl-0 = <&cp0_spi0_pins>; status = "disabled"; spi-flash@0 { @@ -152,59 +115,59 @@ }; }; -&cpm_sata0 { +&cp0_sata0 { status = "okay"; }; -&cpm_usb3_0 { +&cp0_usb3_0 { status = "okay"; }; -&cpm_usb3_1 { +&cp0_usb3_1 { status = "okay"; }; -&cpm_comphy { +&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy2 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-speed = <COMPHY_SPEED_5G>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX2>; + phy-speed = <COMPHY_SPEED_5G>; }; }; -&cpm_nand { +&cp0_nand { status = "okay"; }; -&cpm_utmi0 { +&cp0_utmi0 { status = "okay"; }; -&cpm_utmi1 { +&cp0_utmi1 { status = "okay"; }; @@ -215,7 +178,7 @@ non-removable; }; -&cpm_sdhci0 { +&cp0_sdhci0 { status = "okay"; bus-width = <4>; no-1-8-v; diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index cfd2b4baf34..b158f923491 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */ /* @@ -57,8 +20,8 @@ }; aliases { - i2c0 = &cpm_i2c0; - spi0 = &cpm_spi1; + i2c0 = &cp0_i2c0; + spi0 = &cp0_spi1; }; memory@00000000 { @@ -82,18 +45,18 @@ }; -&cpm_pcie2 { +&cp0_pcie2 { status = "okay"; }; -&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; }; -&cpm_pinctl { +&cp0_pinctl { /* MPP Bus: * TDM [0-11] * SPI [13-16] @@ -115,9 +78,9 @@ 0xE 0xE 0xE >; }; -&cpm_spi1 { +&cp0_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_spi0_pins>; + pinctrl-0 = <&cp0_spi0_pins>; status = "okay"; spi-flash@0 { @@ -145,54 +108,55 @@ }; }; -&cpm_sata0 { +&cp0_sata0 { status = "okay"; }; -&cpm_usb3_0 { +&cp0_usb3_0 { status = "okay"; }; -&cpm_usb3_1 { +&cp0_usb3_1 { status = "okay"; }; -&cpm_comphy { +&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-speed = <COMPHY_SPEED_5G>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX2>; + phy-speed = <COMPHY_SPEED_5G>; }; }; -&cpm_utmi0 { +&cp0_utmi0 { status = "okay"; }; -&cpm_utmi1 { +&cp0_utmi1 { status = "okay"; }; @@ -203,14 +167,14 @@ non-removable; }; -&cpm_sdhci0 { +&cp0_sdhci0 { status = "okay"; bus-width = <4>; no-1-8-v; non-removable; }; -&cpm_mdio { +&cp0_mdio { phy0: ethernet-phy@0 { reg = <0>; }; @@ -219,22 +183,22 @@ }; }; -&cpm_ethernet { +&cp0_ethernet { status = "okay"; }; -&cpm_eth0 { +&cp0_eth0 { status = "okay"; phy-mode = "sfi"; /* lane-2 */ }; -&cpm_eth1 { +&cp0_eth1 { status = "okay"; phy = <&phy0>; phy-mode = "sgmii"; }; -&cpm_eth2 { +&cp0_eth2 { status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi index b5be0c4652e..039d30c72a8 100644 --- a/arch/arm/dts/armada-7040.dtsi +++ b/arch/arm/dts/armada-7040.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */ /* @@ -46,11 +9,57 @@ */ #include <dt-bindings/gpio/gpio.h> -#include "armada-ap806-quad.dtsi" -#include "armada-cp110-master.dtsi" +#include "armada-common.dtsi" +#include "armada-8k.dtsi" +#include "armada-ap806.dtsi" +#include "armada-ap80x-quad.dtsi" + +/* CP110-0 Settings */ +#define CP110_NAME cp0 +#define CP110_NUM 0 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_NUM / { model = "Marvell Armada 7040"; compatible = "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; }; + +&cp0_pinctl { + compatible = "marvell,mvebu-pinctrl", "marvell,7k-pinctrl"; + bank-name ="cp0-110"; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins = < 35 36 >; + marvell,function = <2>; + }; + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>; + marvell,function = <3>; + }; + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { + marvell,pins = < 44 45 46 47 48 49 50 51 + 52 53 54 55 >; + marvell,function = <1>; + }; + cp0_pca0_pins: cp0-pca0_pins { + marvell,pins = <62>; + marvell,function = <0>; + }; + cp0_sdhci_pins: cp0-sdhi-pins-0 { + marvell,pins = < 56 57 58 59 60 61 >; + marvell,function = <14>; + }; + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; +}; diff --git a/arch/arm/dts/armada-8020.dtsi b/arch/arm/dts/armada-8020.dtsi deleted file mode 100644 index 048e5cf5160..00000000000 --- a/arch/arm/dts/armada-8020.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-cp110-master.dtsi" -#include "armada-cp110-slave.dtsi" - -/ { - model = "Marvell Armada 8020"; - compatible = "marvell,armada8020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 720c95082b6..6a586dbbba1 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -15,9 +15,9 @@ }; aliases { - i2c0 = &cpm_i2c0; - i2c1 = &cpm_i2c1; - spi0 = &cps_spi1; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + spi0 = &cp1_spi1; }; memory@00000000 { @@ -31,14 +31,14 @@ reg_usb3h0_vbus: usb3-vbus0 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&cpm_xhci_vbus_pins>; + pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "reg-usb3h0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; startup-delay-us = <300000>; shutdown-delay-us = <500000>; regulator-force-boot-off; - gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */ + gpio = <&cp0_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */ }; }; }; @@ -66,7 +66,7 @@ status = "okay"; }; -&cpm_pinctl { +&cp0_pinctl { /* * MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins: @@ -99,111 +99,111 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >; - cpm_pcie_reset_pins: cpm-pcie-reset-pins { + cp0_pcie_reset_pins: cp0-pcie-reset-pins { marvell,pins = < 32 >; marvell,function = <0>; }; - cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + cp0_xhci_vbus_pins: cp0-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; }; - cps_1g_phy_reset: cps-1g-phy-reset { + cp1_1g_phy_reset: cp1-1g-phy-reset { marvell,pins = < 43 >; marvell,function = <0>; }; }; /* uSD slot */ -&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width = <4>; status = "okay"; }; -&cpm_pcie0 { +&cp0_pcie0 { num-lanes = <1>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cp0_pcie_reset_pins>; + marvell,reset-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>; status = "okay"; }; -&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; }; -&cpm_i2c1 { +&cp0_i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c1_pins>; + pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; clock-frequency = <100000>; }; -&cpm_sata0 { +&cp0_sata0 { status = "okay"; }; -&cpm_comphy { +&cp0_comphy { /* * CP0 Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: Not connected - * Lane 2: SFI (10G) + * Lane 2: SFI0 (10G) * Lane 3: Not connected * Lane 4: USB 3.0 host port1 (can be PCIe) * Lane 5: Not connected */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy3 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy5 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; }; -&cpm_ethernet { +&cp0_ethernet { pinctrl-names = "default"; status = "okay"; }; /* 10G SFI SFP */ -&cpm_eth0 { +&cp0_eth0 { status = "okay"; phy-mode = "sfi"; }; -&cps_sata0 { +&cp1_sata0 { status = "okay"; }; -&cps_usb3_0 { +&cp1_usb3_0 { vbus-supply = <®_usb3h0_vbus>; status = "okay"; }; -&cps_utmi0 { +&cp1_utmi0 { status = "okay"; }; -&cps_pinctl { +&cp1_pinctl { /* * MPP Bus: * [0-5] TDM @@ -234,9 +234,9 @@ 0xff 0xff 0xff>; }; -&cps_spi1 { +&cp1_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cps_spi1_pins>; + pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; spi-flash@0 { @@ -261,7 +261,7 @@ }; }; -&cps_comphy { +&cp1_comphy { /* * CP1 Serdes Configuration: * Lane 0: SATA 1 (RX swapped). Can be PCIe0 @@ -272,52 +272,52 @@ * Lane 5: SGMII2 - Connected to Topaz switch */ phy0 { - phy-type = <PHY_TYPE_SATA1>; - phy-invert = <PHY_POLARITY_RXD_INVERT>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-invert = <COMPHY_POLARITY_RXD_INVERT>; }; phy1 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; -&cps_mdio { +&cp1_mdio { phy0: ethernet-phy@0 { reg = <0>; }; }; -&cps_ethernet { +&cp1_ethernet { pinctrl-names = "default"; - pinctrl-0 = <&cps_1g_phy_reset>; + pinctrl-0 = <&cp1_1g_phy_reset>; status = "okay"; }; /* 1G SGMII */ -&cps_eth1 { +&cp1_eth1 { status = "okay"; phy-mode = "sgmii"; phy = <&phy0>; - phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>; }; /* 2.5G to Topaz switch */ -&cps_eth2 { +&cp1_eth2 { status = "okay"; phy-mode = "sgmii"; phy-speed = <2500>; - phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&cp1_gpio0 24 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 65b30bbc648..51c2f23f4db 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016 - 2021 Marvell International Ltd. */ /* @@ -56,8 +19,8 @@ }; aliases { - i2c0 = &cpm_i2c0; - spi0 = &cps_spi1; + i2c0 = &cp0_i2c0; + spi0 = &cp1_spi1; }; memory@00000000 { @@ -88,7 +51,7 @@ status = "okay"; }; -&cpm_pinctl { +&cp0_pinctl { /* MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins * [11] CLKOUT_MPP_11 (out) @@ -116,7 +79,7 @@ 0xe 0xe 0xe>; }; -&cpm_comphy { +&cp0_comphy { /* Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: SATA0 @@ -126,77 +89,77 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; + phy-type = <COMPHY_TYPE_PEX2>; }; }; /* CON6 on CP0 expansion */ -&cpm_pcie0 { +&cp0_pcie0 { status = "okay"; }; -&cpm_pcie1 { +&cp0_pcie1 { status = "disabled"; }; /* CON5 on CP0 expansion */ -&cpm_pcie2 { +&cp0_pcie2 { status = "okay"; }; -&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; }; /* CON4 on CP0 expansion */ -&cpm_sata0 { +&cp0_sata0 { status = "okay"; }; /* CON9 on CP0 expansion */ -&cpm_usb3_0 { +&cp0_usb3_0 { status = "okay"; }; /* CON10 on CP0 expansion */ -&cpm_usb3_1 { +&cp0_usb3_1 { status = "okay"; }; -&cpm_utmi0 { +&cp0_utmi0 { status = "okay"; }; -&cpm_utmi1 { +&cp0_utmi1 { status = "okay"; }; -&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width = <4>; status = "okay"; }; -&cps_pinctl { +&cp1_pinctl { /* MPP Bus: * [0-11] RGMII0 * [13-16] SPI1 @@ -215,7 +178,7 @@ 0xff 0xff 0xff>; }; -&cps_comphy { +&cp1_comphy { /* Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: SATA0 @@ -225,42 +188,42 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_PEX1>; + phy-type = <COMPHY_TYPE_PEX1>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; + phy-type = <COMPHY_TYPE_PEX2>; }; }; /* CON6 on CP1 expansion */ -&cps_pcie0 { +&cp1_pcie0 { status = "okay"; }; -&cps_pcie1 { +&cp1_pcie1 { status = "okay"; }; /* CON5 on CP1 expansion */ -&cps_pcie2 { +&cp1_pcie2 { status = "okay"; }; -&cps_spi1 { +&cp1_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cps_spi1_pins>; + pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; spi-flash@0 { @@ -288,35 +251,35 @@ }; /* CON4 on CP1 expansion */ -&cps_sata0 { +&cp1_sata0 { status = "okay"; }; /* CON9 on CP1 expansion */ -&cps_usb3_0 { +&cp1_usb3_0 { status = "okay"; }; /* CON10 on CP1 expansion */ -&cps_usb3_1 { +&cp1_usb3_1 { status = "okay"; }; -&cps_utmi0 { +&cp1_utmi0 { status = "okay"; }; -&cpm_mdio { +&cp0_mdio { phy1: ethernet-phy@1 { reg = <1>; }; }; -&cpm_ethernet { +&cp0_ethernet { status = "okay"; }; -&cpm_eth2 { +&cp0_eth2 { status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 5a046d9de47..21846483186 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2016 - 2021 Marvell International Ltd. */ #include "armada-8040.dtsi" /* include SoC device tree */ @@ -15,12 +15,12 @@ }; aliases { - i2c0 = &cpm_i2c0; - i2c1 = &cpm_i2c1; - spi0 = &cps_spi1; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + spi0 = &cp1_spi1; gpio0 = &ap_gpio0; - gpio1 = &cpm_gpio0; - gpio2 = &cpm_gpio1; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; }; memory@00000000 { @@ -36,7 +36,7 @@ reg_usb3h0_vbus: usb3-vbus0 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&cpm_xhci_vbus_pins>; + pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "reg-usb3h0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -44,7 +44,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ + gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ }; }; }; @@ -73,7 +73,7 @@ status = "okay"; }; -&cpm_pinctl { +&cp0_pinctl { /* * MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins: @@ -108,59 +108,59 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >; - cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + cp0_xhci_vbus_pins: cp0-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; }; - cpm_pcie_reset_pins: cpm-pcie-reset-pins { + cp0_pcie_reset_pins: cp0-pcie-reset-pins { marvell,pins = < 52 >; marvell,function = <0>; }; }; /* uSD slot */ -&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width= <4>; status = "okay"; }; /* PCIe x4 */ -&cpm_pcie0 { +&cp0_pcie0 { num-lanes = <4>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ + pinctrl-0 = <&cp0_pcie_reset_pins>; + marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ status = "okay"; }; -&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; }; -&cpm_i2c1 { +&cp0_i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c1_pins>; + pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; clock-frequency = <100000>; }; -&cpm_sata0 { +&cp0_sata0 { status = "okay"; }; -&cpm_mdio { +&cp0_mdio { ge_phy: ethernet-phy@0 { reg = <0>; }; }; -&cpm_comphy { +&cp0_comphy { /* * CP0 Serdes Configuration: * Lane 0: PCIe0 (x4) @@ -171,49 +171,49 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy3 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; }; -&cps_sata0 { +&cp1_sata0 { status = "okay"; }; -&cps_usb3_0 { +&cp1_usb3_0 { vbus-supply = <®_usb3h0_vbus>; status = "okay"; }; -&cps_utmi0 { +&cp1_utmi0 { status = "okay"; }; -&cps_ethernet { +&cp1_ethernet { status = "okay"; }; -&cps_eth1 { +&cp1_eth1 { status = "okay"; phy = <&ge_phy>; phy-mode = "sgmii"; }; -&cps_pinctl { +&cp1_pinctl { /* * MPP Bus: * [0-5] TDM @@ -246,9 +246,9 @@ 0xff 0xff 0xff>; }; -&cps_spi1 { +&cp1_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cps_spi1_pins>; + pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; spi-flash@0 { @@ -275,7 +275,7 @@ }; }; -&cps_comphy { +&cp1_comphy { /* * CP1 Serdes Configuration: * Lane 0: SGMII1 @@ -286,22 +286,23 @@ * Lane 5: SGMII3 */ phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy5 { - phy-type = <PHY_TYPE_SGMII3>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index 58edb5b3aa3..510fb84d5a9 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -16,14 +16,14 @@ }; aliases { - i2c0 = &i2c0; - i2c1 = &cpm_i2c0; - i2c2 = &cpm_i2c1; + i2c0 = &ap_i2c0; + i2c1 = &cp0_i2c0; + i2c2 = &cp0_i2c1; i2c3 = &i2c_switch; - spi0 = &spi0; + spi0 = &ap_spi0; gpio0 = &ap_gpio0; - gpio1 = &cpm_gpio0; - gpio2 = &cpm_gpio1; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; gpio3 = &sfpplus_gpio; }; @@ -40,7 +40,7 @@ reg_usb3h0_vbus: usb3-vbus0 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&cpm_xhci_vbus_pins>; + pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "reg-usb3h0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -48,12 +48,12 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ + gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ }; }; }; -&i2c0 { +&ap_i2c0 { status = "okay"; clock-frequency = <100000>; @@ -83,7 +83,7 @@ 0 3 0 0 0 0 0 0 0 3 >; }; -&cpm_pinctl { +&cp0_pinctl { /* * MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins: @@ -118,35 +118,35 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >; - cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + cp0_xhci_vbus_pins: cpm-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; }; - cpm_pcie_reset_pins: cpm-pcie-reset-pins { + cp0_pcie_reset_pins: cpm-pcie-reset-pins { marvell,pins = < 52 >; marvell,function = <0>; }; }; -&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width= <4>; status = "okay"; }; -&cpm_pcie0 { +&cp0_pcie0 { num-lanes = <1>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ + pinctrl-0 = <&cp0_pcie_reset_pins>; + marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ status = "okay"; }; -&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; @@ -158,9 +158,9 @@ }; }; -&cpm_i2c1 { +&cp0_i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c1_pins>; + pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; clock-frequency = <100000>; @@ -172,44 +172,44 @@ }; }; -&cpm_sata0 { +&cp0_sata0 { status = "okay"; }; -&cpm_ethernet { +&cp0_ethernet { pinctrl-names = "default"; status = "okay"; }; -&cpm_mdio { +&cp0_mdio { status = "okay"; - cpm_ge_phy0: ethernet-phy@1 { + cp0_ge_phy0: ethernet-phy@1 { reg = <0>; }; - cpm_ge_phy1: ethernet-phy@2 { + cp0_ge_phy1: ethernet-phy@2 { reg = <1>; }; }; -&cpm_eth0 { +&cp0_eth0 { status = "okay"; phy-mode = "sfi"; }; -&cpm_eth1 { +&cp0_eth1 { status = "okay"; phy-mode = "sgmii"; - phy = <&cpm_ge_phy0>; + phy = <&cp0_ge_phy0>; }; -&cpm_eth2 { +&cp0_eth2 { status = "okay"; phy-mode = "sgmii"; - phy = <&cpm_ge_phy1>; + phy = <&cp0_ge_phy1>; }; -&cpm_comphy { +&cp0_comphy { /* * CP0 Serdes Configuration: * Lane 0: PCIe0 (x1) @@ -220,75 +220,75 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy2 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; }; -&cps_mdio { +&cp1_mdio { status = "okay"; - cps_ge_phy0: ethernet-phy@3 { + cp1_ge_phy0: ethernet-phy@3 { reg = <1>; }; - cps_ge_phy1: ethernet-phy@4 { + cp1_ge_phy1: ethernet-phy@4 { reg = <0>; }; }; -&cps_pcie0 { +&cp1_pcie0 { num-lanes = <2>; pinctrl-names = "default"; status = "okay"; }; -&cps_usb3_0 { +&cp1_usb3_0 { vbus-supply = <®_usb3h0_vbus>; status = "okay"; }; -&cps_utmi0 { +&cp1_utmi0 { status = "okay"; }; -&cps_ethernet { +&cp1_ethernet { status = "okay"; }; -&cps_eth0 { +&cp1_eth0 { status = "okay"; phy-mode = "sfi"; }; -&cps_eth1 { +&cp1_eth1 { status = "okay"; - phy = <&cps_ge_phy0>; + phy = <&cp1_ge_phy0>; phy-mode = "sgmii"; }; -&cps_eth2 { +&cp1_eth2 { status = "okay"; - phy = <&cps_ge_phy1>; + phy = <&cp1_ge_phy1>; phy-mode = "sgmii"; }; -&cps_pinctl { +&cp1_pinctl { /* * MPP Bus: * [0-5] TDM @@ -321,7 +321,7 @@ 0xff 0xff 0xff>; }; -&spi0 { +&ap_spi0 { status = "okay"; spi-flash@0 { @@ -356,7 +356,7 @@ }; }; -&cps_comphy { +&cp1_comphy { /* * CP1 Serdes Configuration: * Lane 0: PCIe0 (x2) @@ -367,23 +367,23 @@ * Lane 5: SGMII2 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; }; }; diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi index 96cc112ac9c..5123742b8d5 100644 --- a/arch/arm/dts/armada-8040.dtsi +++ b/arch/arm/dts/armada-8040.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */ /* @@ -46,12 +9,81 @@ */ #include <dt-bindings/gpio/gpio.h> -#include "armada-ap806-quad.dtsi" -#include "armada-cp110-master.dtsi" -#include "armada-cp110-slave.dtsi" +#include "armada-common.dtsi" +#include "armada-8k.dtsi" +#include "armada-ap806.dtsi" +#include "armada-ap80x-quad.dtsi" + +/* CP110-0 Settings */ +#define CP110_NAME cp0 +#define CP110_NUM 0 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_NUM + +/* CP110-1 Settings */ +#define CP110_NAME cp1 +#define CP110_NUM 1 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_NUM + / { model = "Marvell Armada 8040"; compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; }; + +&cp0_pinctl { + compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl"; + bank-name ="cp0-110"; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins = < 35 36 >; + marvell,function = <2>; + }; + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>; + marvell,function = <3>; + }; + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { + marvell,pins = < 44 45 46 47 48 49 50 51 + 52 53 54 55 >; + marvell,function = <1>; + }; + cp0_pca0_pins: cp0-pca0_pins { + marvell,pins = <62>; + marvell,function = <0>; + }; + cp0_sdhci_pins: cp0-sdhi-pins-0 { + marvell,pins = < 56 57 58 59 60 61 >; + marvell,function = <14>; + }; + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; +}; + +&cp1_pinctl { + compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl"; + bank-name ="cp1-110"; + + cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11 >; + marvell,function = <3>; + }; + cp1_spi1_pins: cp1-spi-pins-1 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; +}; diff --git a/arch/arm/dts/armada-8k.dtsi b/arch/arm/dts/armada-8k.dtsi new file mode 100644 index 00000000000..c6af9ce631c --- /dev/null +++ b/arch/arm/dts/armada-8k.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 - 2021 Marvell International Ltd. + */ +/* Common definitions used by Armada 8K DTs */ + +/* This defines used to calculate the base address of each CP */ +#define CP110_BASE_OFFSET (0xf2000000) +#define CP110_SPACE_SIZE (0x02000000) +#define CP110_BASE (CP110_BASE_OFFSET + \ + ((CP110_NUM % 2) * CP110_SPACE_SIZE)) + +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) \ + (0xf6000000 + (CP110_NUM % 2) * 0x4000000 + (iface) * 0x1000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) \ + (CP110_PCIEx_CPU_MEM_BASE(iface)) +#define CP110_PCIE_BUS_MEM_CFG (0x82000000) diff --git a/arch/arm/dts/armada-ap806-quad.dtsi b/arch/arm/dts/armada-ap806-quad.dtsi deleted file mode 100644 index ba43a4357b8..00000000000 --- a/arch/arm/dts/armada-ap806-quad.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model = "Marvell Armada AP806 Quad"; - compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@000 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x000>; - enable-method = "psci"; - }; - cpu@001 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x001>; - enable-method = "psci"; - }; - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x100>; - enable-method = "psci"; - }; - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x101>; - enable-method = "psci"; - }; - }; -}; diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi index 713c2dba74c..f432089ab25 100644 --- a/arch/arm/dts/armada-ap806.dtsi +++ b/arch/arm/dts/armada-ap806.dtsi @@ -1,274 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2020 Marvell International Ltd. */ /* * Device Tree file for Marvell Armada AP806. */ -#include <dt-bindings/interrupt-controller/arm-gic.h> +/* AP806 Settings */ +#define AP_NAME ap806 -/dts-v1/; +#include "armada-ap80x.dtsi" / { model = "Marvell Armada AP806"; - compatible = "marvell,armada-ap806"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - psci-area@4000000 { - reg = <0x0 0x4000000 0x0 0x200000>; - no-map; - }; - }; - - ap806 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; + AP_NAME { config-space { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x0 0xf0000000 0x1000000>; - - gic: interrupt-controller@210000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x210000 0x10000>, - <0x220000 0x20000>, - <0x240000 0x20000>, - <0x260000 0x20000>; - - gic_v2m0: v2m@280000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x280000 0x1000>; - arm,msi-base-spi = <160>; - arm,msi-num-spis = <32>; - }; - gic_v2m1: v2m@290000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x290000 0x1000>; - arm,msi-base-spi = <192>; - arm,msi-num-spis = <32>; - }; - gic_v2m2: v2m@2a0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x2a0000 0x1000>; - arm,msi-base-spi = <224>; - arm,msi-num-spis = <32>; - }; - gic_v2m3: v2m@2b0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x2b0000 0x1000>; - arm,msi-base-spi = <256>; - arm,msi-num-spis = <32>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; - }; - - odmi: odmi@300000 { - compatible = "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames = <4>; - reg = <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base = <128>, <136>, <144>, <152>; - }; - - ap_pinctl: ap-pinctl@6F4000 { - compatible = "marvell,ap806-pinctrl"; - bank-name ="apn-806"; - reg = <0x6F4000 0x10>; - pin-count = <20>; - max-func = <3>; - - ap_i2c0_pins: i2c-pins-0 { - marvell,pins = < 4 5 >; - marvell,function = <3>; - }; - ap_emmc_pins: emmc-pins-0 { - marvell,pins = < 0 1 2 3 4 5 6 7 - 8 9 10 >; - marvell,function = <1>; - }; - }; - - ap_gpio0: gpio@6F5040 { - compatible = "marvell,orion-gpio"; - reg = <0x6F5040 0x40>; - ngpios = <20>; - gpio-controller; - #gpio-cells = <2>; - }; - - xor@400000 { - compatible = "marvell,mv-xor-v2"; - reg = <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; - - xor@420000 { - compatible = "marvell,mv-xor-v2"; - reg = <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; - - xor@440000 { - compatible = "marvell,mv-xor-v2"; - reg = <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; - - xor@460000 { - compatible = "marvell,mv-xor-v2"; - reg = <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; - - spi0: spi@510600 { - compatible = "marvell,armada-380-spi"; - reg = <0x510600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ap_syscon 3>; - status = "disabled"; - }; - - i2c0: i2c@511000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x511000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; - clocks = <&ap_syscon 3>; - status = "disabled"; - }; - - uart0: serial@512000 { - compatible = "snps,dw-apb-uart"; - reg = <0x512000 0x100>; - reg-shift = <2>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clocks = <&ap_syscon 3>; - status = "disabled"; - clock-frequency = <200000000>; - }; - - uart1: serial@512100 { - compatible = "snps,dw-apb-uart"; - reg = <0x512100 0x100>; - reg-shift = <2>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clocks = <&ap_syscon 3>; - status = "disabled"; - - }; - - ap_sdhci0: sdhci@6e0000 { - compatible = "marvell,armada-8k-sdhci"; - reg = <0x6e0000 0x300>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - dma-coherent; - status = "disabled"; - }; - - ap_syscon: system-controller@6f4000 { - compatible = "marvell,ap806-system-controller", - "syscon"; - #clock-cells = <1>; - clock-output-names = "ap-cpu-cluster-0", - "ap-cpu-cluster-1", - "ap-fixed", "ap-mss"; - reg = <0x6f4000 0x1000>; + sar-reg { + compatible = "marvell,sample-at-reset-common", + "marvell,sample-at-reset-ap806"; + reg = <0x6F8200 0x8>; + sar-driver = "ap806_sar"; + sar-name = "ap806_sar"; + status = "okay"; + }; + + thermal: thermal@6f8084 { + compatible = "marvell,mvebu-thermal", + "marvell,thermal-ext-sensor"; + reg = <0x6f8084 0x12>; + gain = <425>; + offset = <153400>; + divisor = <1000>; + status = "okay"; }; }; }; diff --git a/arch/arm/dts/armada-ap807.dtsi b/arch/arm/dts/armada-ap807.dtsi new file mode 100644 index 00000000000..a5309f34309 --- /dev/null +++ b/arch/arm/dts/armada-ap807.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +/* + * Device Tree file for Marvell Armada AP807. + */ + +/* AP807 Settings */ +#define AP_NAME ap807 + +#include "armada-ap80x.dtsi" + +/ { + model = "Marvell Armada AP807"; + + AP_NAME { + config-space { + sar-reg { + compatible = "marvell,sample-at-reset-common", + "marvell,sample-at-reset-ap807"; + reg = <0x6F8200 0x8>; + sar-driver = "ap807_sar"; + sar-name = "ap807_sar"; + status = "okay"; + }; + + thermal: thermal@6f8084 { + compatible = "marvell,mvebu-thermal", + "marvell,thermal-ext-sensor"; + reg = <0x6f8084 0x12>; + gain = <394>; + offset = <128900>; + divisor = <1000>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-ap80x-quad.dtsi b/arch/arm/dts/armada-ap80x-quad.dtsi new file mode 100644 index 00000000000..1220e986e38 --- /dev/null +++ b/arch/arm/dts/armada-ap80x-quad.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + */ + +/* + * Device Tree file for Marvell Armada AP806/AP807. + */ + +/ { + model = "Marvell Armada AP80X Quad"; + compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@000 { + clocks; + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x000>; + enable-method = "psci"; + }; + cpu@001 { + clocks; + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x001>; + enable-method = "psci"; + }; + cpu@100 { + clocks; + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu@101 { + clocks; + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + }; + }; +}; diff --git a/arch/arm/dts/armada-ap80x.dtsi b/arch/arm/dts/armada-ap80x.dtsi new file mode 100644 index 00000000000..8787a872d85 --- /dev/null +++ b/arch/arm/dts/armada-ap80x.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + * + */ + +/* + * Device Tree file for Marvell Armada AP806/AP807. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/dts-v1/; + +/ { + compatible = "marvell,armada-ap806"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + psci-area@4000000 { + reg = <0x0 0x4000000 0x0 0x200000>; + no-map; + }; + }; + + AP_NAME { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + config-space { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x0 0xf0000000 0x1000000>; + + gic: interrupt-controller@210000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x210000 0x10000>, + <0x220000 0x20000>, + <0x240000 0x20000>, + <0x260000 0x20000>; + + gic_v2m0: v2m@280000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x280000 0x1000>; + arm,msi-base-spi = <160>; + arm,msi-num-spis = <32>; + }; + gic_v2m1: v2m@290000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x290000 0x1000>; + arm,msi-base-spi = <192>; + arm,msi-num-spis = <32>; + }; + gic_v2m2: v2m@2a0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x2a0000 0x1000>; + arm,msi-base-spi = <224>; + arm,msi-num-spis = <32>; + }; + gic_v2m3: v2m@2b0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x2b0000 0x1000>; + arm,msi-base-spi = <256>; + arm,msi-num-spis = <32>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + }; + + odmi: odmi@300000 { + compatible = "marvell,odmi-controller"; + interrupt-controller; + msi-controller; + marvell,odmi-frames = <4>; + reg = <0x300000 0x4000>, + <0x304000 0x4000>, + <0x308000 0x4000>, + <0x30C000 0x4000>; + marvell,spi-base = <128>, <136>, <144>, <152>; + }; + + ap_pinctl: ap-pinctl@6F4000 { + compatible = "marvell,ap806-pinctrl"; + bank-name ="apn-806"; + reg = <0x6F4000 0x10>; + pin-count = <20>; + max-func = <3>; + + ap_i2c0_pins: i2c-pins-0 { + marvell,pins = < 4 5 >; + marvell,function = <3>; + }; + ap_emmc_pins: emmc-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 + 8 9 10 12 >; + marvell,function = <1>; + }; + }; + + ap_gpio0: gpio@6F5040 { + compatible = "marvell,orion-gpio"; + reg = <0x6F5040 0x40>; + ngpios = <20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ap_spi0: spi@510600 { + compatible = "marvell,armada-380-spi"; + reg = <0x510600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ap_syscon 3>; + status = "disabled"; + }; + + ap_i2c0: i2c@511000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x511000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + timeout-ms = <1000>; + clocks = <&ap_syscon 3>; + status = "disabled"; + }; + + uart0: serial@512000 { + compatible = "snps,dw-apb-uart"; + reg = <0x512000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&ap_syscon 3>; + status = "disabled"; + clock-frequency = <200000000>; + }; + + uart1: serial@512100 { + compatible = "snps,dw-apb-uart"; + reg = <0x512100 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&ap_syscon 3>; + status = "disabled"; + + }; + + watchdog: watchdog@610000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x610000 0x1000>, <0x600000 0x1000>; + }; + + ap_sdhci0: sdhci@6e0000 { + compatible = "marvell,armada-8k-sdhci"; + reg = <0x6e0000 0x300>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + status = "disabled"; + }; + + ap_syscon: system-controller@6f4000 { + compatible = "marvell,ap806-system-controller", + "syscon"; + #clock-cells = <1>; + clock-output-names = "ap-cpu-cluster-0", + "ap-cpu-cluster-1", + "ap-fixed", "ap-mss"; + reg = <0x6f4000 0x1000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-common.dtsi b/arch/arm/dts/armada-common.dtsi new file mode 100644 index 00000000000..b7dfbda3926 --- /dev/null +++ b/arch/arm/dts/armada-common.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Marvell International Ltd. + */ + +/* Common definitions used by Armada 7K/8K DTs */ +#define PASTER(x, y) x ## _ ## y +#define EVALUATOR(x, y) PASTER(x, y) + +/* This define used to create die label: + * For example: + * CP110 master: + * CP110_LABEL(spi0) -> cp0_spi0 + * CP110 slave: + * CP110_LABEL(usb0) -> cp1_usb0 + */ +#define CP110_LABEL(name) EVALUATOR(CP110_NAME, name) + +#define APPEND_NX(A, B) A ##-## B +#define APPEND(A, B) APPEND_NX(A, B) + +#define STRINGIZE_NX(x) #x +#define STRINGIZE(x) STRINGIZE_NX(x) + +/* Same idea here, but this define convert the name to string: + * For example: + * master: CP110_STRING_LABEL(ppv2) -> "cp0-ppv2" + * slave: CP110_STRING_LABEL(ppv2) -> "cp1-ppv2" + */ +#define CP110_STRING_LABEL(name) STRINGIZE(APPEND(CP110_NAME, name)) diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi deleted file mode 100644 index 6cf21778370..00000000000 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Device Tree file for Marvell Armada CP110 Slave. - */ - -#include <dt-bindings/comphy/comphy_data.h> - -/ { - cp110-slave { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - config-space { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0x0 0xf4000000 0x2000000>; - - cps_ethernet: ethernet@0 { - compatible = "marvell,armada-7k-pp22"; - reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; - clock-names = "pp_clk", "gop_clk", "mg_clk"; - status = "disabled"; - dma-coherent; - - cps_eth0: eth0 { - interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; - port-id = <0>; - gop-port-id = <0>; - status = "disabled"; - }; - - cps_eth1: eth1 { - interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; - port-id = <1>; - gop-port-id = <2>; - status = "disabled"; - }; - - cps_eth2: eth2 { - interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; - port-id = <2>; - gop-port-id = <3>; - status = "disabled"; - }; - }; - - cps_mdio: mdio@12a200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x12a200 0x10>; - device-name = "cps-mdio"; - }; - - cps_xmdio: mdio@12a600 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,xmdio"; - reg = <0x12a600 0x16>; - status = "disabled"; - device-name = "cps-xmdio"; - }; - - cps_syscon0: system-controller@440000 { - compatible = "marvell,cp110-system-controller0", - "syscon"; - reg = <0x440000 0x1000>; - #clock-cells = <2>; - core-clock-output-names = - "cps-apll", "cps-ppv2-core", "cps-eip", - "cps-core", "cps-nand-core"; - gate-clock-output-names = - "cps-audio", "cps-communit", "cps-nand", - "cps-ppv2", "cps-sdio", "cps-mg-domain", - "cps-mg-core", "cps-xor1", "cps-xor0", - "cps-gop-dp", "none", "cps-pcie_x10", - "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", - "cps-sata", "cps-sata-usb", "cps-main", - "cps-sd-mmc", "none", "none", - "cps-slow-io", "cps-usb3h0", "cps-usb3h1", - "cps-usb3dev", "cps-eip150", "cps-eip197"; - }; - - cps_pinctl: cps-pinctl@440000 { - compatible = "marvell,mvebu-pinctrl", - "marvell,armada-8k-cps-pinctrl"; - bank-name ="cp1-110"; - reg = <0x440000 0x20>; - pin-count = <63>; - max-func = <0xf>; - - cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 { - marvell,pins = < 0 1 2 3 4 5 6 7 - 8 9 10 11 >; - marvell,function = <3>; - }; - cps_spi1_pins: cps-spi-pins-1 { - marvell,pins = < 13 14 15 16 >; - marvell,function = <3>; - }; - }; - - cps_gpio0: gpio@440100 { - compatible = "marvell,orion-gpio"; - reg = <0x440100 0x40>; - ngpios = <32>; - gpiobase = <20>; - gpio-controller; - #gpio-cells = <2>; - }; - - cps_gpio1: gpio@440140 { - compatible = "marvell,orion-gpio"; - reg = <0x440140 0x40>; - ngpios = <31>; - gpiobase = <52>; - gpio-controller; - #gpio-cells = <2>; - }; - - cps_sata0: sata@540000 { - compatible = "marvell,armada-8k-ahci"; - reg = <0x540000 0x30000>; - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 15>; - status = "disabled"; - }; - - cps_usb3_0: usb3@500000 { - compatible = "marvell,armada-8k-xhci", - "generic-xhci"; - reg = <0x500000 0x4000>; - dma-coherent; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 22>; - status = "disabled"; - }; - - cps_usb3_1: usb3@510000 { - compatible = "marvell,armada-8k-xhci", - "generic-xhci"; - reg = <0x510000 0x4000>; - dma-coherent; - interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 23>; - status = "disabled"; - }; - - cps_xor0: xor@6a0000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x6a0000 0x1000>, - <0x6b0000 0x1000>; - dma-coherent; - msi-parent = <&gic_v2m0>; - clocks = <&cps_syscon0 1 8>; - }; - - cps_xor1: xor@6c0000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x6c0000 0x1000>, - <0x6d0000 0x1000>; - dma-coherent; - msi-parent = <&gic_v2m0>; - clocks = <&cps_syscon0 1 7>; - }; - - cps_spi0: spi@700600 { - compatible = "marvell,armada-380-spi"; - reg = <0x700600 0x50>; - #address-cells = <0x1>; - #size-cells = <0x0>; - cell-index = <1>; - clocks = <&cps_syscon0 0 3>; - status = "disabled"; - }; - - cps_spi1: spi@700680 { - compatible = "marvell,armada-380-spi"; - reg = <0x700680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <2>; - clocks = <&cps_syscon0 1 21>; - status = "disabled"; - }; - - cps_i2c0: i2c@701000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 21>; - status = "disabled"; - }; - - cps_i2c1: i2c@701100 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cps_syscon0 1 21>; - status = "disabled"; - }; - - cps_comphy: comphy@441000 { - compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; - reg = <0x441000 0x8>, - <0x120000 0x8>; - mux-bitcount = <4>; - max-lanes = <6>; - }; - - cps_utmi0: utmi@580000 { - compatible = "marvell,mvebu-utmi-2.6.0"; - reg = <0x580000 0x1000>, /* utmi-unit */ - <0x440420 0x4>, /* usb-cfg */ - <0x440440 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB3_HOST0>; - status = "disabled"; - }; - - cps_nand: nand@720000 { - compatible = "marvell,armada-8k-nand-controller", - "marvell,armada370-nand-controller"; - reg = <0x720000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&cps_syscon0 1 2>, - <&cps_syscon0 1 17>; - marvell,system-controller = <&cps_syscon0>; - nand-enable-arbiter; - num-cs = <1>; - status = "disabled"; - }; - }; - - cps_pcie0: pcie@f4600000 { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf4600000 0 0x10000>, - <0 0xfaf00000 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <1>; - clocks = <&cps_syscon0 1 13>; - status = "disabled"; - }; - - cps_pcie1: pcie@f4620000 { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf4620000 0 0x10000>, - <0 0xfbf00000 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; - - num-lanes = <1>; - clocks = <&cps_syscon0 1 11>; - status = "disabled"; - }; - - cps_pcie2: pcie@f4640000 { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf4640000 0 0x10000>, - <0 0xfcf00000 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 - /* non-prefetchable memory */ - 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; - - num-lanes = <1>; - clocks = <&cps_syscon0 1 12>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110.dtsi index 7d0d31da306..abf1e4ea087 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110.dtsi @@ -1,53 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2016- 2021 Marvell International Ltd. */ /* - * Device Tree file for Marvell Armada CP110 Master. + * Generic Device Tree describing Marvell Armada CP-110 device */ #include <dt-bindings/comphy/comphy_data.h> +#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff) +#define U64_TO_U32_L(addr) ((addr) & 0xffffffff) + +#define CP110_PCIEx_REG0_BASE(iface) \ + (CP110_BASE + 0x600000 + (iface) * 0x20000) +#define CP110_PCIEx_REG1_BASE(iface) \ + (CP110_PCIEx_CPU_MEM_BASE(iface) + CP110_PCIE_MEM_SIZE(iface)) +#define CP110_PCIE_EP_REG_BASE(iface) (CP110_BASE + 0x600000 + \ + (iface) * 0x4000) + / { - cp110-master { + CP110_NAME { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; @@ -59,56 +32,36 @@ #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&gic>; - ranges = <0x0 0x0 0xf2000000 0x2000000>; - - cpm_ethernet: ethernet@0 { - compatible = "marvell,armada-7k-pp22"; - reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; - clock-names = "pp_clk", "gop_clk", "mg_clk"; - status = "disabled"; - dma-coherent; - - cpm_eth0: eth0 { - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - port-id = <0>; - gop-port-id = <0>; - status = "disabled"; - }; - - cpm_eth1: eth1 { - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - port-id = <1>; - gop-port-id = <2>; - status = "disabled"; - }; - - cpm_eth2: eth2 { - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - port-id = <2>; - gop-port-id = <3>; - status = "disabled"; - }; - }; + ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>; - cpm_mdio: mdio@12a200 { + CP110_LABEL(mdio): mdio@12a200 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x12a200 0x10>; - device-name = "cpm-mdio"; + device-name = CP110_STRING_LABEL(mdio); + status = "disabled"; }; - cpm_xmdio: mdio@12a600 { + CP110_LABEL(xmdio): mdio@12a600 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,xmdio"; - reg = <0x12a600 0x16>; + reg = <0x12a600 0x200>; + device-name = CP110_STRING_LABEL(xmdio); status = "disabled"; - device-name = "cpm-xmdio"; }; - cpm_syscon0: system-controller@440000 { + CP110_LABEL(sar-reg) { + compatible = "marvell,sample-at-reset-common", + "marvell,sample-at-reset-cp110"; + reg = <0x400200 0x8>; + sar-driver = "cp110_sar"; + sar-name = CP110_STRING_LABEL(sar); + status = "okay"; + }; + + CP110_LABEL(syscon0): system-controller@440000 { compatible = "marvell,cp110-system-controller0", "syscon"; reg = <0x440000 0x1000>; @@ -128,43 +81,14 @@ "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; }; - cpm_pinctl: cpm-pinctl@440000 { - compatible = "marvell,mvebu-pinctrl", - "marvell,armada-7k-pinctrl", - "marvell,armada-8k-cpm-pinctrl"; - bank-name ="cp0-110"; + CP110_LABEL(pinctl): pinctl@440000 { + compatible = "marvell,mvebu-pinctrl"; reg = <0x440000 0x20>; pin-count = <63>; max-func = <0xf>; - - cpm_i2c0_pins: cpm-i2c-pins-0 { - marvell,pins = < 37 38 >; - marvell,function = <2>; - }; - cpm_i2c1_pins: cpm-i2c-pins-1 { - marvell,pins = < 35 36 >; - marvell,function = <2>; - }; - cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 { - marvell,pins = < 44 45 46 47 48 49 50 51 - 52 53 54 55 >; - marvell,function = <1>; - }; - pca0_pins: cpm-pca0_pins { - marvell,pins = <62>; - marvell,function = <0>; - }; - cpm_sdhci_pins: cpm-sdhi-pins-0 { - marvell,pins = < 56 57 58 59 60 61 >; - marvell,function = <14>; - }; - cpm_spi0_pins: cpm-spi-pins-0 { - marvell,pins = < 13 14 15 16 >; - marvell,function = <3>; - }; }; - cpm_gpio0: gpio@440100 { + CP110_LABEL(gpio0): gpio@440100 { compatible = "marvell,orion-gpio"; reg = <0x440100 0x40>; ngpios = <32>; @@ -173,7 +97,7 @@ #gpio-cells = <2>; }; - cpm_gpio1: gpio@440140 { + CP110_LABEL(gpio1): gpio@440140 { compatible = "marvell,orion-gpio"; reg = <0x440140 0x40>; ngpios = <31>; @@ -182,75 +106,85 @@ #gpio-cells = <2>; }; - cpm_sata0: sata@540000 { + CP110_LABEL(sata0): sata@540000 { compatible = "marvell,armada-8k-ahci"; reg = <0x540000 0x30000>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 15>; + clocks = <&CP110_LABEL(syscon0) 1 15>; status = "disabled"; }; - cpm_usb3_0: usb3@500000 { + CP110_LABEL(usb3_0): usb3@500000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; reg = <0x500000 0x4000>; dma-coherent; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 22>; + clocks = <&CP110_LABEL(syscon0) 1 22>; status = "disabled"; }; - cpm_usb3_1: usb3@510000 { + CP110_LABEL(usb3_1): usb3@510000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; reg = <0x510000 0x4000>; dma-coherent; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 23>; + clocks = <&CP110_LABEL(syscon0) 1 23>; status = "disabled"; }; - cpm_spi0: spi@700600 { + CP110_LABEL(spi0): spi@700600 { compatible = "marvell,armada-380-spi"; reg = <0x700600 0x50>; #address-cells = <0x1>; #size-cells = <0x0>; cell-index = <1>; - clocks = <&cpm_syscon0 0 3>; + spi-max-frequency = <50000000>; + clocks = <&CP110_LABEL(syscon0) 0 3>; status = "disabled"; }; - cpm_spi1: spi@700680 { + CP110_LABEL(spi1): spi@700680 { compatible = "marvell,armada-380-spi"; reg = <0x700680 0x50>; #address-cells = <1>; #size-cells = <0>; cell-index = <2>; - clocks = <&cpm_syscon0 1 21>; + spi-max-frequency = <50000000>; + clocks = <&CP110_LABEL(syscon0) 1 21>; status = "disabled"; }; - cpm_i2c0: i2c@701000 { + CP110_LABEL(i2c0): i2c@701000 { compatible = "marvell,mv78230-i2c"; reg = <0x701000 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 21>; + clocks = <&CP110_LABEL(syscon0) 1 21>; status = "disabled"; }; - cpm_i2c1: i2c@701100 { + CP110_LABEL(i2c1): i2c@701100 { compatible = "marvell,mv78230-i2c"; reg = <0x701100 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 21>; + clocks = <&CP110_LABEL(syscon0) 1 21>; status = "disabled"; }; - cpm_comphy: comphy@441000 { + CP110_LABEL(mss_i2c0): i2c@211000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x211000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + CP110_LABEL(comphy): comphy@441000 { compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; reg = <0x441000 0x8>, <0x120000 0x8>; @@ -258,25 +192,31 @@ max-lanes = <6>; }; - cpm_utmi0: utmi@580000 { - compatible = "marvell,mvebu-utmi-2.6.0"; - reg = <0x580000 0x1000>, /* utmi-unit */ - <0x440420 0x4>, /* usb-cfg */ - <0x440440 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB3_HOST0>; - status = "disabled"; - }; + CP110_LABEL(utmi): utmi@580000 { + compatible = "marvell,mvebu-utmi"; + reg = <0x580000 0xc>; /* utmi-common-pll */ + #address-cells = <1>; + #size-cells = <1>; + CP110_LABEL(utmi0): utmi@58000c { + compatible = "marvell,mvebu-utmi-2.6.0"; + reg = <0x58000c 0x100>,/* utmi-unit */ + <0x440420 0x4>, /* usb-cfg */ + <0x440440 0x4>; /* utmi-cfg */ + utmi-port = <UTMI_PHY_TO_USB3_HOST0>; + status = "disabled"; + }; - cpm_utmi1: utmi@581000 { - compatible = "marvell,mvebu-utmi-2.6.0"; - reg = <0x581000 0x1000>, /* utmi-unit */ - <0x440420 0x4>, /* usb-cfg */ - <0x440444 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB3_HOST1>; - status = "disabled"; + CP110_LABEL(utmi1): utmi@58100c { + compatible = "marvell,mvebu-utmi-2.6.0"; + reg = <0x58100c 0x100>,/* utmi-unit */ + <0x440420 0x4>, /* usb-cfg */ + <0x440444 0x4>; /* utmi-cfg */ + utmi-port = <UTMI_PHY_TO_USB3_HOST1>; + status = "disabled"; + }; }; - cpm_sdhci0: sdhci@780000 { + CP110_LABEL(sdhci0): sdhci@780000 { compatible = "marvell,armada-8k-sdhci"; reg = <0x780000 0x300>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; @@ -284,28 +224,58 @@ status = "disabled"; }; - cpm_nand: nand@720000 { + CP110_LABEL(nand): nand@720000 { compatible = "marvell,armada-8k-nand-controller", "marvell,armada370-nand-controller"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&cpm_syscon0 1 2>, - <&cpm_syscon0 1 17>; - marvell,system-controller = <&cpm_syscon0>; + clocks = <&CP110_LABEL(syscon0) 1 2>; nand-enable-arbiter; num-cs = <1>; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + marvell,system-controller = <&CP110_LABEL(syscon0)>; status = "disabled"; }; + CP110_LABEL(ethernet): ethernet@0 { + compatible = "marvell,armada-7k-pp22"; + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&CP110_LABEL(syscon0) 1 3>, <&CP110_LABEL(syscon0) 1 9>, <&CP110_LABEL(syscon0) 1 5>; + clock-names = "pp_clk", "gop_clk", "mg_clk"; + status = "disabled"; + dma-coherent; + + CP110_LABEL(eth0): eth0 { + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + port-id = <0>; + gop-port-id = <0>; + status = "disabled"; + }; + + CP110_LABEL(eth1): eth1 { + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + port-id = <1>; + gop-port-id = <2>; + status = "disabled"; + }; + + CP110_LABEL(eth2): eth2 { + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + port-id = <2>; + gop-port-id = <3>; + status = "disabled"; + }; + }; }; - cpm_pcie0: pcie@f2600000 { + CP110_LABEL(pcie0): pcie0@600000 { compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf2600000 0 0x10000>, - <0 0xf6f00000 0 0x80000>; + reg = + <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(0)) 0 0x10000>, + /* Last 512KB of mem space */ + <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(0)) 0 0x80000>; reg-names = "ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -315,22 +285,25 @@ bus-range = <0 0xff>; ranges = - /* downstream I/O */ - <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; + <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(0)) + U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(0)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(0)) + U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(0)) + U64_TO_U32_H(CP110_PCIE_MEM_SIZE(0)) U64_TO_U32_L(CP110_PCIE_MEM_SIZE(0))>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; num-lanes = <1>; - clocks = <&cpm_syscon0 1 13>; + clocks = <&CP110_LABEL(syscon0) 1 13>; status = "disabled"; }; - cpm_pcie1: pcie@f2620000 { + CP110_LABEL(pcie1): pcie1@620000 { compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf2620000 0 0x10000>, - <0 0xf7f00000 0 0x80000>; + reg = + <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(1)) 0 0x10000>, + /* Last 512KB of mem space */ + <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(1)) 0 0x80000>; reg-names = "ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -340,23 +313,26 @@ bus-range = <0 0xff>; ranges = - /* downstream I/O */ - <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; + <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(1)) + U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(1)) + U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(1)) + U64_TO_U32_L(CP110_PCIE_MEM_SIZE(1))>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; num-lanes = <1>; - clocks = <&cpm_syscon0 1 11>; + clocks = <&CP110_LABEL(syscon0) 1 11>; status = "disabled"; }; - cpm_pcie2: pcie@f2640000 { + CP110_LABEL(pcie2): pcie2@640000 { compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf2640000 0 0x10000>, - <0 0xf8f00000 0 0x80000>; + reg = + <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(2)) 0 0x10000>, + /* Last 64KB of mem space */ + <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(2)) 0 0x80000>; reg-names = "ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -366,16 +342,17 @@ bus-range = <0 0xff>; ranges = - /* downstream I/O */ - <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; + <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(2)) + U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(2)) + U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(2)) + U64_TO_U32_L(CP110_PCIE_MEM_SIZE(2))>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; num-lanes = <1>; - clocks = <&cpm_syscon0 1 12>; + clocks = <&CP110_LABEL(syscon0) 1 12>; status = "disabled"; }; }; diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts new file mode 100644 index 00000000000..fcfcd15d8de --- /dev/null +++ b/arch/arm/dts/cn9130-crb-A.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include "cn9130-crb.dtsi" + +/ { + model = "CN9130-CRB-A"; + compatible = "marvell,cn9130-crb-A", + "marvell,cn9130", + "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +&cp0_comphy { + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy3 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy4 { + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; + }; + + phy5 { + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; + }; +}; + +&cp0_pcie0 { + num-lanes = <4>; + /* non-prefetchable memory */ + ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>; + status = "disabled"; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts new file mode 100644 index 00000000000..b681b6032d6 --- /dev/null +++ b/arch/arm/dts/cn9130-crb-B.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include "cn9130-crb.dtsi" + +/ { + model = "CN9130-CRB-B"; + compatible = "marvell,cn9130-crb-B", + "marvell,cn9130", + "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +&cp0_comphy { + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_USB3_HOST0>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_SATA0>; + }; + + phy3 { + phy-type = <COMPHY_TYPE_USB3_HOST1>; + }; + + phy4 { + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; + }; + + phy5 { + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; + }; +}; + +&cp0_sata0 { + status = "okay"; +}; + +&cp0_pcie0 { + num-lanes = <1>; + /* non-prefetchable memory */ + ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>; + status = "disabled"; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; diff --git a/arch/arm/dts/cn9130-crb.dtsi b/arch/arm/dts/cn9130-crb.dtsi new file mode 100644 index 00000000000..b229725184a --- /dev/null +++ b/arch/arm/dts/cn9130-crb.dtsi @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include "cn9130.dtsi" /* include SoC device tree */ + +/ { + model = "CN9130-CRB"; + compatible = "marvell,cn9130-crb", + "marvell,cn9130", + "marvell,armada-ap806-quad", + "marvell,armada-ap806"; + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cp0_i2c0; + spi0 = &cp0_spi1; + gpio0 = &ap_gpio0; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + cp0 { + config-space { + sdhci@780000 { + vqmmc-supply = <&cp0_reg_sd_vccq>; + vmmc-supply = <&cp0_reg_sd_vcc>; + }; + cp0_reg_sd_vccq: cp0_sd_vccq@0 { + compatible = "regulator-gpio"; + regulator-name = "cp0_sd_vccq"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&cp0_gpio1 18 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + }; + cp0_reg_sd_vcc: cp0_sd_vcc@0 { + compatible = "regulator-fixed"; + regulator-name = "cp0_sd_vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&cp0_gpio1 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +/* + * AP related configuration + */ +&ap_pinctl { + /* MPP Bus: + * SDIO [0-10, 12] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 1 0 0 0 0 0 0 3 >; +}; + +/* on-board eMMC - U6 */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + /* MPP Bus: + * [0-11] RGMII1 + * [12] GPIO + * [13-16] SPI1 + * [17-32] GPIO + * [33] SD_PWR_OFF + * [34] CP_PCIE0_CLKREQn + * [35-38] I2C1 I2C0 + * [39] GPIO + * [40-43] SMI/XSMI + * [44-46] GPIO + * [47] UART1_TX + * [48] GPIO + * [49] SD_HST_18_EN + * [50] GPIO + * [51] SD_PWR_0 + * [52] PCIE_RSTn + * [53] UART1_RX + * [54] GPIO + * [55] SD_DT + * [56-61] SDIO + * + * Note that CRB board revisions have different MPP configurations. + * r1p2 has SPI flash on MPP[30:27] and r1p3.1, which is the latest + * board revision, has it mapped to MPP[16:13]. + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 3 3 3 3 3 3 3 3 3 3 + 3 3 0 3 3 3 3 0 0 0 + 0 0 0 0 0 0 0 0 0 0 + 0 0 0 6 9 2 2 2 2 0 + 8 8 8 8 0 0 0 7 0 0xa + 0 0xa 9 7 0 0xb 0xe 0xe 0xe 0xe + 0xe 0xe 0xe>; + + cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb { + marvell,pins = < 55 >; + marvell,function = <0>; + }; + + cp0_spi1_pins_crb: cp0-spi-pins-crb { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; + + cp0_smi_pins_crb: cp0-smi-pins-crb { + marvell,pins = < 40 41 >; + marvell,function = <8>; + }; + + cp0_xsmi_pins_crb: cp0-xsmi-pins-crb { + marvell,pins = < 42 43 >; + marvell,function = <8>; + }; + +}; + +/* + * CP0 + */ +&cp0_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cp0_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + status = "okay"; +}; + +&cp0_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sdhci_pins + &cp0_sdhci_cd_pins_crb>; + bus-width = <4>; + vqmmc-supply = <&cp0_reg_sd_vccq>; + vmmc-supply = <&cp0_reg_sd_vcc>; + status = "okay"; +}; + +&cp0_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_spi1_pins_crb>; + reg = <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>, /* CS0 */ + <0 0xffffffff>, /* CS1 */ + <0 0xffffffff>, /* CS2 */ + <0 0xffffffff>; /* CS3 */ + status = "okay"; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor", "spi-flash"; + reg = <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x200000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xe00000>; + }; + }; + }; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_utmi1 { + status = "okay"; +}; + +&cp0_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_smi_pins_crb>; + status = "okay"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + switch6: ethernet-switch@6 { + reg = <6>; + }; +}; + +&cp0_xmdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_xsmi_pins_crb>; + status = "okay"; + nbaset_phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + phy-mode = "sfi"; +}; + +&cp0_eth1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_ge1_rgmii_pins>; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_eth2 { + /* Disable it for now, as mainline does not support this IF yet */ + status = "disabled"; + phy = <&nbaset_phy0>; +}; diff --git a/arch/arm/dts/cn9130.dtsi b/arch/arm/dts/cn9130.dtsi new file mode 100644 index 00000000000..68b767a7063 --- /dev/null +++ b/arch/arm/dts/cn9130.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +/* + * Device Tree file for the CN 9030 SoC, made of an AP806 Quad and + * one CP110. + */ + +#include <dt-bindings/gpio/gpio.h> +#include "armada-common.dtsi" +#include "armada-ap807.dtsi" +#include "armada-ap80x-quad.dtsi" + +/* This defines used to calculate the base address of each CP */ +#define CP110_BASE_OFFSET (0xf2000000) +#define CP110_SPACE_SIZE (0x02000000) +#define CP110_BASE (CP110_BASE_OFFSET + \ + (CP110_NUM * CP110_SPACE_SIZE)) + +#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000) +#define CP110_PCIE_BUS_MEM_CFG (0x82000000) + +/* CP110-0 Settings */ +#define CP110_NAME cp0 +#define CP110_NUM 0 +#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \ + (0xe0000000 + (iface - 1) * 0x1000000)) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) + +#include "armada-cp110.dtsi" + +/ { + model = "Marvell CN 9030"; + compatible = "marvell,armada70x0", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +&cp0_pinctl { + compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl"; + bank-name ="cp0-110"; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins = < 35 36 >; + marvell,function = <2>; + }; + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { + marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>; + marvell,function = <3>; + }; + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { + marvell,pins = < 44 45 46 47 48 49 50 51 + 52 53 54 55 >; + marvell,function = <1>; + }; + cp0_pca0_pins: cp0-pca0_pins { + marvell,pins = <62>; + marvell,function = <0>; + }; + cp0_sdhci_pins: cp0-sdhi-pins-0 { + marvell,pins = < 56 57 58 59 60 61 >; + marvell,function = <14>; + }; + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; +}; |