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-rw-r--r--arch/arm/dts/imx8ulp-evk-u-boot.dtsi1
-rw-r--r--arch/arm/dts/imxrt1020.dtsi1
-rw-r--r--arch/arm/dts/imxrt1170.dtsi1
-rw-r--r--arch/arm/dts/ipq5424-rdp466-u-boot.dtsi37
-rw-r--r--arch/arm/dts/k3-am625-phycore-som-binman.dtsi94
-rw-r--r--arch/arm/dts/qcs615-ride-u-boot.dtsi14
-rw-r--r--arch/arm/dts/qcs8300-ride-u-boot.dtsi19
-rw-r--r--arch/arm/dts/versal-mini-emmc0.dts36
-rw-r--r--arch/arm/dts/versal-mini-emmc1.dts36
-rw-r--r--arch/arm/dts/versal-mini-ospi.dtsi52
-rw-r--r--arch/arm/dts/versal-mini-qspi.dtsi40
-rw-r--r--arch/arm/dts/versal-net-mini-emmc.dts36
-rw-r--r--arch/arm/dts/versal-net-mini-ospi.dtsi56
-rw-r--r--arch/arm/dts/versal-net-mini-qspi.dtsi42
-rw-r--r--arch/arm/dts/versal-net-mini.dts26
-rw-r--r--arch/arm/dts/vf610-pcm052.dtsi4
-rw-r--r--arch/arm/dts/zynqmp-clk-ccf.dtsi2
-rw-r--r--arch/arm/dts/zynqmp-mini-emmc0.dts31
-rw-r--r--arch/arm/dts/zynqmp-mini-emmc1.dts31
-rw-r--r--arch/arm/dts/zynqmp-mini-nand.dts35
-rw-r--r--arch/arm/dts/zynqmp-mini-qspi.dts25
21 files changed, 344 insertions, 275 deletions
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index f67fe166d31..845fe205925 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -28,7 +28,6 @@
&iomuxc1 {
bootph-pre-ram;
- fsl,mux_mask = <0xf00>;
};
&pinctrl_lpuart5 {
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 13511ebb18e..336aeedb2ce 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -64,7 +64,6 @@
iomuxc: iomuxc@401f8000 {
compatible = "fsl,imxrt-iomuxc";
reg = <0x401f8000 0x4000>;
- fsl,mux_mask = <0x7>;
};
anatop: anatop@400d8000 {
diff --git a/arch/arm/dts/imxrt1170.dtsi b/arch/arm/dts/imxrt1170.dtsi
index 08665eaf06a..7566402353a 100644
--- a/arch/arm/dts/imxrt1170.dtsi
+++ b/arch/arm/dts/imxrt1170.dtsi
@@ -77,7 +77,6 @@
iomuxc: iomuxc@400e8000 {
compatible = "fsl,imxrt-iomuxc";
reg = <0x400e8000 0x4000>;
- fsl,mux_mask = <0x7>;
};
anatop: anatop@40c84000 {
diff --git a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi
new file mode 100644
index 00000000000..9e4af4d9f72
--- /dev/null
+++ b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IPQ5424 RDP466 board device tree source
+ *
+ * Copyright (c) 2025 The Linux Foundation. All rights reserved.
+ */
+
+/ {
+ /* Will be removed when SMEM parsing is updated */
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x20000000>;
+ };
+
+};
+
+ &sdhc {
+ sdhci-caps-mask = <0x0 0x04000000>;
+ sdhci-caps = <0x0 0x04000000>; /* SDHCI_CAN_VDD_180 */
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <192000000>;
+ bus-width = <4>;
+ pinctrl-0 = <&sdc_default_state>;
+ pinctrl-names = "default";
+ non-removable;
+
+ /*
+ * This reset is needed to clear out the settings done by
+ * previous boot loader. Without this the SDHCI_RESET_ALL
+ * reset done sdhci_init() times out.
+ */
+ resets = <&gcc GCC_SDCC_BCR>;
+
+ status = "okay";
+ };
+
diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
index 32d8804a395..6deebdadf09 100644
--- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
@@ -400,11 +400,105 @@
};
&binman {
+ tifsstub-hs {
+ filename = "tifsstub.bin_hs";
+ ti-secure-rom {
+ content = <&tifsstub_hs_cert>;
+ core = "secure";
+ load = <0x40000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "custMpk.pem";
+ countersign;
+ tifsstub;
+ };
+ tifsstub_hs_cert: tifsstub-hs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_hs_enc: tifsstub-hs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ tifsstub-fs {
+ filename = "tifsstub.bin_fs";
+ tifsstub_fs_cert: tifsstub-fs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_fs_enc: tifsstub-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ };
+
+ tifsstub-gp {
+ filename = "tifsstub.bin_gp";
+ ti-secure-rom {
+ content = <&tifsstub_gp>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "ti-degenerate-key.pem";
+ tifsstub;
+ };
+ tifsstub_gp: tifsstub-gp.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
+ tifsstub-hs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9dc00000>;
+ entry = <0x9dc00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9dc00000>;
+ entry = <0x9dc00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
+
+ tifsstub-gp {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-gp";
+ load = <0x9dc00000>;
+ entry = <0x9dc00000>;
+ blob-ext {
+ filename = "tifsstub.bin_gp";
+ };
+ };
+
dm {
ti-dm {
filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
diff --git a/arch/arm/dts/qcs615-ride-u-boot.dtsi b/arch/arm/dts/qcs615-ride-u-boot.dtsi
new file mode 100644
index 00000000000..68fffc70fcb
--- /dev/null
+++ b/arch/arm/dts/qcs615-ride-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x7a00000>,
+ <0x0 0x89600000 0x0 0x30100000>,
+ <0x0 0xc0000000 0x0 0xc0000000>,
+ <0x1 0x80000000 0x1 0x00000000>;
+ };
+};
diff --git a/arch/arm/dts/qcs8300-ride-u-boot.dtsi b/arch/arm/dts/qcs8300-ride-u-boot.dtsi
new file mode 100644
index 00000000000..8c353ace71e
--- /dev/null
+++ b/arch/arm/dts/qcs8300-ride-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x11a80000>,
+ <0x0 0xc0000000 0x0 0x10000000>,
+ <0x0 0xd3100000 0x0 0x26b00000>,
+ <0xe 0x80000000 0x1 0x00000000>,
+ <0xa 0x80000000 0x1 0x80000000>,
+ <0x0 0xb0800000 0x0 0x0f200000>,
+ <0x0 0xd0100000 0x0 0x01800000>,
+ <0x0 0x91b00000 0x0 0x1e500000>;
+ };
+};
+
diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
index 179060c56ee..9044ef1889b 100644
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -28,28 +28,20 @@
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- sdhci0: sdhci@f1040000 {
- compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
- status = "okay";
- non-removable;
- disable-wp;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0x0 0xf1040000 0x0 0x10000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk200 &clk200>;
- no-1-8-v;
- xlnx,mio-bank = <0>;
- };
+ sdhci0: sdhci@f1040000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ status = "okay";
+ non-removable;
+ disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0x0 0xf1040000 0x0 0x10000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk200 &clk200>;
+ no-1-8-v;
+ xlnx,mio-bank = <0>;
};
aliases {
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
index ffcc3334529..47f3b74c065 100644
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -28,28 +28,20 @@
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- sdhci1: sdhci@f1050000 {
- compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
- status = "okay";
- non-removable;
- disable-wp;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0x0 0xf1050000 0x0 0x10000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk200 &clk200>;
- no-1-8-v;
- xlnx,mio-bank = <0>;
- };
+ sdhci1: sdhci@f1050000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ status = "okay";
+ non-removable;
+ disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0x0 0xf1050000 0x0 0x10000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk200 &clk200>;
+ no-1-8-v;
+ xlnx,mio-bank = <0>;
};
aliases {
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
index 9ca0cf3c027..eec2a08e7c7 100644
--- a/arch/arm/dts/versal-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -28,37 +28,29 @@
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- ospi: spi@f1010000 {
- compatible = "cdns,qspi-nor";
- status = "okay";
- reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
- clock-names = "ref_clk", "pclk";
- clocks = <&clk125 &clk125>;
- bus-num = <2>;
- num-cs = <1>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,is-dma = <1>;
- cdns,trigger-address = <0xc0000000>;
- #address-cells = <1>;
- #size-cells = <0>;
+ ospi: spi@f1010000 {
+ compatible = "cdns,qspi-nor";
+ status = "okay";
+ reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
+ clock-names = "ref_clk", "pclk";
+ clocks = <&clk125 &clk125>;
+ bus-num = <2>;
+ num-cs = <1>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,is-dma = <1>;
+ cdns,trigger-address = <0xc0000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- flash0: flash@0 {
- compatible = "n25q512a", "micron,m25p80",
- "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <20000000>;
- no-wp;
- };
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <20000000>;
+ no-wp;
};
};
diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi
index 57427e099f9..ec4eef74020 100644
--- a/arch/arm/dts/versal-mini-qspi.dtsi
+++ b/arch/arm/dts/versal-mini-qspi.dtsi
@@ -28,31 +28,23 @@
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- qspi: spi@f1030000 {
- compatible = "xlnx,versal-qspi-1.0";
- status = "okay";
- clock-names = "ref_clk", "pclk";
- num-cs = <0x1>;
- reg = <0x0 0xf1030000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk150 &clk150>;
+ qspi: spi@f1030000 {
+ compatible = "xlnx,versal-qspi-1.0";
+ status = "okay";
+ clock-names = "ref_clk", "pclk";
+ num-cs = <0x1>;
+ reg = <0x0 0xf1030000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk150 &clk150>;
- flash0: flash@0 {
- compatible = "n25q512a", "micron,m25p80",
- "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <20000000>;
- };
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
};
};
diff --git a/arch/arm/dts/versal-net-mini-emmc.dts b/arch/arm/dts/versal-net-mini-emmc.dts
index 20e4e299404..567ceeb36a0 100644
--- a/arch/arm/dts/versal-net-mini-emmc.dts
+++ b/arch/arm/dts/versal-net-mini-emmc.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx Versal NET Mini eMMC Configuration
*
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
@@ -42,26 +42,18 @@
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- sdhci1: mmc@f1050000 {
- compatible = "xlnx,versal-net-emmc";
- status = "okay";
- non-removable;
- disable-wp;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0 0xf1050000 0 0x10000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk200>, <&clk200>;
- xlnx,mio-bank = <0>;
- };
+ sdhci1: mmc@f1050000 {
+ compatible = "xlnx,versal-net-emmc";
+ status = "okay";
+ non-removable;
+ disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0 0xf1050000 0 0x10000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk200>, <&clk200>;
+ xlnx,mio-bank = <0>;
};
};
diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi
index a9bf7cc4248..1c94b352dc9 100644
--- a/arch/arm/dts/versal-net-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-net-mini-ospi.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx Versal NET Mini OSPI Configuration
*
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
@@ -42,38 +42,30 @@
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- ospi: spi@f1010000 {
- compatible = "cdns,qspi-nor";
- status = "okay";
- reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
- clock-names = "ref_clk", "pclk";
- clocks = <&clk125>, <&clk125>;
- bus-num = <2>;
- num-cs = <1>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,is-dma = <1>;
- cdns,is-stig-pgm = <1>;
- cdns,trigger-address = <0xc0000000>;
- #address-cells = <1>;
- #size-cells = <0>;
+ ospi: spi@f1010000 {
+ compatible = "cdns,qspi-nor";
+ status = "okay";
+ reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
+ clock-names = "ref_clk", "pclk";
+ clocks = <&clk125>, <&clk125>;
+ bus-num = <2>;
+ num-cs = <1>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,is-dma = <1>;
+ cdns,is-stig-pgm = <1>;
+ cdns,trigger-address = <0xc0000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- flash0: flash@0 {
- compatible = "mt35xu02g", "micron,m25p80",
- "jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <20000000>;
- no-wp;
- };
+ flash0: flash@0 {
+ compatible = "mt35xu02g", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <20000000>;
+ no-wp;
};
};
};
diff --git a/arch/arm/dts/versal-net-mini-qspi.dtsi b/arch/arm/dts/versal-net-mini-qspi.dtsi
index e29a3f36d6e..97cc39c73e0 100644
--- a/arch/arm/dts/versal-net-mini-qspi.dtsi
+++ b/arch/arm/dts/versal-net-mini-qspi.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx Versal NET Mini QSPI Configuration
*
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
@@ -42,31 +42,23 @@
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- qspi: spi@f1030000 {
- compatible = "xlnx,versal-qspi-1.0";
- status = "okay";
- clock-names = "ref_clk", "pclk";
- num-cs = <1>;
- reg = <0 0xf1030000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk150>, <&clk150>;
+ qspi: spi@f1030000 {
+ compatible = "xlnx,versal-qspi-1.0";
+ status = "okay";
+ clock-names = "ref_clk", "pclk";
+ num-cs = <1>;
+ reg = <0 0xf1030000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk150>, <&clk150>;
- flash0: flash@0 {
- compatible = "n25q512a", "micron,m25p80",
- "jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <20000000>;
- };
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
};
};
};
diff --git a/arch/arm/dts/versal-net-mini.dts b/arch/arm/dts/versal-net-mini.dts
index f98f95a5c2f..0f0a82e3aa3 100644
--- a/arch/arm/dts/versal-net-mini.dts
+++ b/arch/arm/dts/versal-net-mini.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx Versal NET
*
* Copyright (C) 2021 - 2022, Xilinx, Inc.
- * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ * Copyright (C) 2022-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -45,22 +45,14 @@
bootph-all;
};
- amba: axi {
- compatible = "simple-bus";
+ serial0: serial@f1920000 {
bootph-all;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- serial0: serial@f1920000 {
- bootph-all;
- compatible = "arm,pl011", "arm,primecell";
- reg = <0 0xf1920000 0 0x1000>;
- reg-io-width = <4>;
- clock-names = "uartclk", "apb_pclk";
- clocks = <&clk1>, <&clk1>;
- clock = <1000000>;
- skip-init;
- };
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0xf1920000 0 0x1000>;
+ reg-io-width = <4>;
+ clock-names = "uartclk", "apb_pclk";
+ clocks = <&clk1>, <&clk1>;
+ clock = <1000000>;
+ skip-init;
};
};
diff --git a/arch/arm/dts/vf610-pcm052.dtsi b/arch/arm/dts/vf610-pcm052.dtsi
index ccdc0f57e2b..2b82b7313dd 100644
--- a/arch/arm/dts/vf610-pcm052.dtsi
+++ b/arch/arm/dts/vf610-pcm052.dtsi
@@ -244,7 +244,7 @@
qflash0: spi_flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "spi-flash";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <108000000>;
reg = <0>;
};
@@ -252,7 +252,7 @@
qflash1: spi_flash@1 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "spi-flash";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <66000000>;
reg = <1>;
};
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 385fed8a852..52e122fc7c9 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -8,7 +8,7 @@
* Michal Simek <michal.simek@amd.com>
*/
-#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+#include "xlnx-zynqmp-clk.h"
/ {
pss_ref_clk: pss-ref-clk {
bootph-all;
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index ad4b3c5f8b1..05f61d6bb35 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -41,25 +41,18 @@
clock-frequency = <200000000>;
};
- amba: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- sdhci0: mmc@ff160000 {
- bootph-all;
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- status = "disabled";
- non-removable;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0x0 0xff160000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk_xin &clk_xin>;
- };
+ sdhci0: mmc@ff160000 {
+ bootph-all;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ non-removable;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk_xin &clk_xin>;
};
};
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index fd421b4fe7e..7857106260e 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -41,25 +41,18 @@
clock-frequency = <200000000>;
};
- amba: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- sdhci1: mmc@ff170000 {
- bootph-all;
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- status = "disabled";
- non-removable;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0x0 0xff170000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk_xin &clk_xin>;
- };
+ sdhci1: mmc@ff170000 {
+ bootph-all;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ non-removable;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0x0 0xff170000 0x0 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk_xin &clk_xin>;
};
};
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index 5e2135158cd..1ece3999791 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -35,27 +35,20 @@
bootph-all;
};
- amba: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- nand0: nand@ff100000 {
- compatible = "arasan,nfc-v3p10";
- status = "okay";
- reg = <0x0 0xff100000 0x1000>;
- clock-names = "clk_sys", "clk_flash";
- #address-cells = <1>;
- #size-cells = <0>;
- arasan,has-mdma;
- num-cs = <2>;
- nand@0 {
- reg = <0>;
- #address-cells = <2>;
- #size-cells = <1>;
- nand-ecc-mode = "hw";
- };
+ nand0: nand@ff100000 {
+ compatible = "arasan,nfc-v3p10";
+ status = "okay";
+ reg = <0x0 0xff100000 0x1000>;
+ clock-names = "clk_sys", "clk_flash";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ arasan,has-mdma;
+ num-cs = <2>;
+ nand@0 {
+ reg = <0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ nand-ecc-mode = "hw";
};
};
};
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index 917603dec61..ddcc39b4e94 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -42,22 +42,15 @@
clock-frequency = <125000000>;
};
- amba: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- qspi: spi@ff0f0000 {
- compatible = "xlnx,zynqmp-qspi-1.0";
- status = "disabled";
- clock-names = "ref_clk", "pclk";
- clocks = <&misc_clk &misc_clk>;
- num-cs = <1>;
- reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
+ qspi: spi@ff0f0000 {
+ compatible = "xlnx,zynqmp-qspi-1.0";
+ status = "disabled";
+ clock-names = "ref_clk", "pclk";
+ clocks = <&misc_clk &misc_clk>;
+ num-cs = <1>;
+ reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-27 01:20:11 +0000