diff options
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/common_def.h | 23 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/cpu.h | 33 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 184 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/gpio.h | 29 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware.h | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/omap.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/sys_proto.h | 30 |
8 files changed, 157 insertions, 155 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/common_def.h b/arch/arm/include/asm/arch-am33xx/common_def.h deleted file mode 100644 index aa3b5545368..00000000000 --- a/arch/arm/include/asm/arch-am33xx/common_def.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * common_def.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __COMMON_DEF_H__ -#define __COMMON_DEF_H__ - -extern void enable_uart0_pin_mux(void); -extern void enable_mmc0_pin_mux(void); -extern void enable_i2c0_pin_mux(void); - -#endif/*__COMMON_DEF_H__ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index a027e3128f4..6cfbef76a79 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -234,6 +234,39 @@ struct vtp_reg { struct ctrl_stat { unsigned int resv1[16]; unsigned int statusreg; /* ofset 0x40 */ + unsigned int resv2[51]; + unsigned int secure_emif_sdram_config; /* offset 0x0110 */ +}; + +/* AM33XX GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x002c +#define OMAP_GPIO_IRQSTATUS2 0x0030 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +/* Control Device Register */ +struct ctrl_dev { + unsigned int deviceid; /* offset 0x00 */ + unsigned int resv1[11]; + unsigned int macid0l; /* offset 0x30 */ + unsigned int macid0h; /* offset 0x34 */ + unsigned int macid1l; /* offset 0x38 */ + unsigned int macid1h; /* offset 0x3c */ + unsigned int resv2[4]; + unsigned int miisel; /* offset 0x50 */ }; #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 388336f9d70..6b22c45f775 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -20,158 +20,104 @@ #define _DDR_DEFS_H #include <asm/arch/hardware.h> +#include <asm/emif.h> /* AM335X EMIF Register values */ -#define EMIF_SDMGT 0x80000000 -#define EMIF_SDRAM 0x00004650 -#define EMIF_PHYCFG 0x2 -#define DDR_PHY_RESET (0x1 << 10) -#define DDR_FUNCTIONAL_MODE_EN 0x1 -#define DDR_PHY_READY (0x1 << 2) #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) -#define VTP_CTRL_LOCK_EN (0x1 << 4) #define VTP_CTRL_START_EN (0x1) -#define DDR2_RATIO 0x80 -#define CMD_FORCE 0x00 -#define CMD_DELAY 0x00 - -#define EMIF_READ_LATENCY 0x05 -#define EMIF_TIM1 0x0666B3D6 -#define EMIF_TIM2 0x143731DA -#define EMIF_TIM3 0x00000347 -#define EMIF_SDCFG 0x43805332 -#define EMIF_SDREF 0x0000081a +#define PHY_DLL_LOCK_DIFF 0x0 +#define DDR_CKE_CTRL_NORMAL 0x1 + +#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */ +#define DDR2_EMIF_TIM1 0x0666B3C9 +#define DDR2_EMIF_TIM2 0x243631CA +#define DDR2_EMIF_TIM3 0x0000033F +#define DDR2_EMIF_SDCFG 0x41805332 +#define DDR2_EMIF_SDREF 0x0000081a #define DDR2_DLL_LOCK_DIFF 0x0 -#define DDR2_RD_DQS 0x12 -#define DDR2_PHY_FIFO_WE 0x80 - +#define DDR2_RATIO 0x80 #define DDR2_INVERT_CLKOUT 0x00 +#define DDR2_RD_DQS 0x12 #define DDR2_WR_DQS 0x00 #define DDR2_PHY_WRLVL 0x00 #define DDR2_PHY_GATELVL 0x00 #define DDR2_PHY_WR_DATA 0x40 -#define PHY_RANK0_DELAY 0x01 -#define PHY_DLL_LOCK_DIFF 0x0 -#define DDR_IOCTRL_VALUE 0x18B - -/** - * This structure represents the EMIF registers on AM33XX devices. - */ -struct emif_regs { - unsigned int sdrrev; /* offset 0x00 */ - unsigned int sdrstat; /* offset 0x04 */ - unsigned int sdrcr; /* offset 0x08 */ - unsigned int sdrcr2; /* offset 0x0C */ - unsigned int sdrrcr; /* offset 0x10 */ - unsigned int sdrrcsr; /* offset 0x14 */ - unsigned int sdrtim1; /* offset 0x18 */ - unsigned int sdrtim1sr; /* offset 0x1C */ - unsigned int sdrtim2; /* offset 0x20 */ - unsigned int sdrtim2sr; /* offset 0x24 */ - unsigned int sdrtim3; /* offset 0x28 */ - unsigned int sdrtim3sr; /* offset 0x2C */ - unsigned int res1[2]; - unsigned int sdrmcr; /* offset 0x38 */ - unsigned int sdrmcsr; /* offset 0x3C */ - unsigned int res2[8]; - unsigned int sdritr; /* offset 0x60 */ - unsigned int res3[32]; - unsigned int ddrphycr; /* offset 0xE4 */ - unsigned int ddrphycsr; /* offset 0xE8 */ - unsigned int ddrphycr2; /* offset 0xEC */ -}; - -/** - * Encapsulates DDR PHY control and corresponding shadow registers. - */ -struct ddr_phy_control { - unsigned long reg; - unsigned long reg_sh; - unsigned long reg2; -}; - -/** - * Encapsulates SDRAM timing and corresponding shadow registers. - */ -struct sdram_timing { - unsigned long time1; - unsigned long time1_sh; - unsigned long time2; - unsigned long time2_sh; - unsigned long time3; - unsigned long time3_sh; -}; - -/** - * Encapsulates SDRAM configuration. - * (Includes refresh control registers) */ -struct sdram_config { - unsigned long sdrcr; - unsigned long sdrcr2; - unsigned long refresh; - unsigned long refresh_sh; -}; +#define DDR2_PHY_FIFO_WE 0x80 +#define DDR2_PHY_RANK0_DELAY 0x1 +#define DDR2_IOCTRL_VALUE 0x18B + +/* Micron MT41J128M16JT-125 */ +#define DDR3_EMIF_READ_LATENCY 0x06 +#define DDR3_EMIF_TIM1 0x0888A39B +#define DDR3_EMIF_TIM2 0x26337FDA +#define DDR3_EMIF_TIM3 0x501F830F +#define DDR3_EMIF_SDCFG 0x61C04AB2 +#define DDR3_EMIF_SDREF 0x0000093B +#define DDR3_ZQ_CFG 0x50074BE4 +#define DDR3_DLL_LOCK_DIFF 0x1 +#define DDR3_RATIO 0x40 +#define DDR3_INVERT_CLKOUT 0x1 +#define DDR3_RD_DQS 0x3B +#define DDR3_WR_DQS 0x85 +#define DDR3_PHY_WR_DATA 0xC1 +#define DDR3_PHY_FIFO_WE 0x100 +#define DDR3_IOCTRL_VALUE 0x18B /** * Configure SDRAM */ -int config_sdram(struct sdram_config *cfg); +void config_sdram(const struct emif_regs *regs); /** * Set SDRAM timings */ -int set_sdram_timings(struct sdram_timing *val); +void set_sdram_timings(const struct emif_regs *regs); /** * Configure DDR PHY */ -int config_ddr_phy(struct ddr_phy_control *cfg); +void config_ddr_phy(const struct emif_regs *regs); /** * This structure represents the DDR registers on AM33XX devices. + * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that + * correspond to DATA1 registers defined here. */ struct ddr_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ - unsigned int cm0csforce; /* offset 0x020 */ - unsigned int cm0csdelay; /* offset 0x024 */ + unsigned int resv1[2]; unsigned int cm0dldiff; /* offset 0x028 */ unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv1[8]; + unsigned int resv2[8]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int cm1csforce; /* offset 0x054 */ - unsigned int cm1csdelay; /* offset 0x058 */ + unsigned int resv3[2]; unsigned int cm1dldiff; /* offset 0x05C */ unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv2[8]; + unsigned int resv4[8]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int cm2csforce; /* offset 0x088 */ - unsigned int cm2csdelay; /* offset 0x08C */ + unsigned int resv5[2]; unsigned int cm2dldiff; /* offset 0x090 */ unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv3[12]; + unsigned int resv6[12]; unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int dt0rdsratio1; /* offset 0x0CC */ - unsigned int resv4[3]; + unsigned int resv7[4]; unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int dt0wdsratio1; /* offset 0x0E0 */ - unsigned int resv5[3]; + unsigned int resv8[4]; unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int dt0wiratio1; /* offset 0x0F4 */ + unsigned int resv9; + unsigned int dt0wimode0; /* offset 0x0F8 */ unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int dt0giratio1; /* offset 0x100 */ - unsigned int resv6[1]; + unsigned int resv10; + unsigned int dt0gimode0; /* offset 0x104 */ unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int dt0fwsratio1; /* offset 0x10C */ - unsigned int resv7[4]; + unsigned int resv11[4]; + unsigned int dt0dqoffset; /* offset 0x11C */ unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int dt0wrsratio1; /* offset 0x124 */ - unsigned int resv8[3]; + unsigned int resv12[4]; unsigned int dt0rdelays0; /* offset 0x134 */ unsigned int dt0dldiff0; /* offset 0x138 */ - unsigned int resv9[39]; - unsigned int dt1rdelays0; /* offset 0x1D8 */ }; /** @@ -200,29 +146,24 @@ struct cmd_control { */ struct ddr_data { unsigned long datardsratio0; - unsigned long datardsratio1; unsigned long datawdsratio0; - unsigned long datawdsratio1; unsigned long datawiratio0; - unsigned long datawiratio1; unsigned long datagiratio0; - unsigned long datagiratio1; unsigned long datafwsratio0; - unsigned long datafwsratio1; unsigned long datawrsratio0; - unsigned long datawrsratio1; + unsigned long datauserank0delay; unsigned long datadldiff0; }; /** * Configure DDR CMD control registers */ -int config_cmd_ctrl(struct cmd_control *cmd); +void config_cmd_ctrl(const struct cmd_control *cmd); /** * Configure DDR DATA registers */ -int config_ddr_data(int data_macrono, struct ddr_data *data); +void config_ddr_data(int data_macrono, const struct ddr_data *data); /** * This structure represents the DDR io control on AM33XX devices. @@ -238,20 +179,9 @@ struct ddr_cmdtctrl { }; /** - * Encapsulates DDR CMD & DATA io control registers. - */ -struct ddr_ioctrl { - unsigned long cmd1ctl; - unsigned long cmd2ctl; - unsigned long cmd3ctl; - unsigned long data1ctl; - unsigned long data2ctl; -}; - -/** * Configure DDR io control registers */ -int config_io_ctrl(struct ddr_ioctrl *ioctrl); +void config_io_ctrl(unsigned long val); struct ddr_ctrl { unsigned int ddrioctrl; @@ -259,6 +189,6 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -void config_ddr(void); +void config_ddr(short ddr_type); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h new file mode 100644 index 00000000000..1a211e95e8e --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -0,0 +1,29 @@ +/* + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _GPIO_AM33xx_H +#define _GPIO_AM33xx_H + +#include <asm/omap_gpio.h> + +#define AM33XX_GPIO0_BASE 0x44E07000 +#define AM33XX_GPIO1_BASE 0x4804C000 +#define AM33XX_GPIO2_BASE 0x481AC000 +#define AM33XX_GPIO3_BASE 0x481AE000 + +#endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 0ec22eb918f..62332f2ded5 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -19,8 +19,9 @@ #ifndef __AM33XX_HARDWARE_H #define __AM33XX_HARDWARE_H +#include <asm/arch/omap.h> + /* Module base addresses */ -#define LOW_LEVEL_SRAM_STACK 0x4030B7FC #define UART0_BASE 0x44E09000 /* DM Timer base addresses */ @@ -46,6 +47,7 @@ /* Control Module Base Address */ #define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 /* PRCM Base Address */ #define PRCM_BASE 0x44E00000 @@ -53,7 +55,6 @@ /* EMIF Base address */ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000 -#define DMM_BASE 0x4E000000 /* PLL related registers */ #define CM_PER 0x44E00000 @@ -78,4 +79,8 @@ #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE +/* CPSW Config space */ +#define AM335X_CPSW_BASE 0x4A100000 +#define AM335X_CPSW_MDIO_BASE 0x4A101000 + #endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 26cc300e70f..1f597c0eecd 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -20,8 +20,7 @@ * OMAP HSMMC register definitions */ #define OMAP_HSMMC1_BASE 0x48060100 -#define OMAP_HSMMC2_BASE 0x481D8000 -#define OMAP_HSMMC3_BASE 0x47C24000 +#define OMAP_HSMMC2_BASE 0x481D8100 typedef struct hsmmc { unsigned char res1[0x10]; diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index fc2b7a5a280..850f8a551d8 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -30,7 +30,6 @@ */ #define NON_SECURE_SRAM_START 0x40304000 #define NON_SECURE_SRAM_END 0x4030E000 -#define LOW_LEVEL_SRAM_STACK 0x4030B7FC /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 6c58f1b30fd..819ea650f00 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -19,6 +19,24 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +/* + * AM335x parts define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am335x_baseboard_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + #define BOARD_REV_ID 0x0 u32 get_cpu_rev(void); @@ -28,6 +46,18 @@ u32 get_sysboot_value(void); int print_cpuinfo(void); #endif +extern struct ctrl_stat *cstat; u32 get_device_type(void); void setup_clocks_for_console(void); +void ddr_pll_config(unsigned int ddrpll_M); + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(struct am335x_baseboard_id *header); #endif |