diff options
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/config.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index cd795d6919a..1791b978704 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -40,14 +40,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_IFC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 #define GICR_BASE 0x06100000 @@ -55,9 +47,6 @@ /* SMMU Defintions */ #define SMMU_BASE 0x05000000 /* GR0 Base */ -/* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE - /* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 #define CCI_MN_RNF_NODEID_LIST 0x180 @@ -141,16 +130,7 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_IFC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - /* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ @@ -165,7 +145,6 @@ #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) #endif -#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 @@ -179,13 +158,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 #define GICR_BASE 0x06200000 @@ -194,7 +166,6 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 @@ -234,18 +205,10 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - /* SEC */ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 /* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ @@ -255,16 +218,11 @@ #define DCSR_DCFG_SBEESR2 0x20140534 #define DCSR_DCFG_MBEESR2 0x20140544 -#define CONFIG_SYS_FSL_CCSR_SCFG_BE -#define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_CCSR_GUR_BE -#define CONFIG_SYS_FSL_PEX_LUT_BE /* SoC related */ #ifdef CONFIG_ARCH_LS1043A -#define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 @@ -276,8 +234,6 @@ #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_IFC_BE - /* SMMU Defintions */ #define SMMU_BASE 0x09000000 @@ -317,7 +273,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 @@ -325,8 +280,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_IFC_BE - /* SMMU Defintions */ #define SMMU_BASE 0x09000000 |