diff options
Diffstat (limited to 'arch/arm/include/asm/arch-stm32f4')
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f4/fmc.h | 75 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f4/gpio.h | 146 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f4/stm32.h | 17 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f4/stm32_defs.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f4/stm32_periph.h | 38 |
5 files changed, 3 insertions, 288 deletions
diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h deleted file mode 100644 index 7dd5077d0c3..00000000000 --- a/arch/arm/include/asm/arch-stm32f4/fmc.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2013 - * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MACH_FMC_H_ -#define _MACH_FMC_H_ - -struct stm32_fmc_regs { - u32 sdcr1; /* Control register 1 */ - u32 sdcr2; /* Control register 2 */ - u32 sdtr1; /* Timing register 1 */ - u32 sdtr2; /* Timing register 2 */ - u32 sdcmr; /* Mode register */ - u32 sdrtr; /* Refresh timing register */ - u32 sdsr; /* Status register */ -}; - -/* - * FMC registers base - */ -#define STM32_SDRAM_FMC_BASE 0xA0000140 -#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE) - -/* Control register SDCR */ -#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ -#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ -#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ -#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ -#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ -#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ -#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ -#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ -#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ - -/* Timings register SDTR */ -#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ -#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ -#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ -#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ -#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ -#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ -#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ - - -#define FMC_SDCMR_NRFS_SHIFT 5 - -#define FMC_SDCMR_MODE_NORMAL 0 -#define FMC_SDCMR_MODE_START_CLOCK 1 -#define FMC_SDCMR_MODE_PRECHARGE 2 -#define FMC_SDCMR_MODE_AUTOREFRESH 3 -#define FMC_SDCMR_MODE_WRITE_MODE 4 -#define FMC_SDCMR_MODE_SELFREFRESH 5 -#define FMC_SDCMR_MODE_POWERDOWN 6 - -#define FMC_SDCMR_BANK_1 (1 << 4) -#define FMC_SDCMR_BANK_2 (1 << 3) - -#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 - -#define FMC_SDSR_BUSY (1 << 5) - -#define FMC_BUSY_WAIT() do { \ - __asm__ __volatile__ ("dsb" : : : "memory"); \ - while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ - ; \ - } while (0) - - -#endif /* _MACH_FMC_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h index 6173fa13000..16cdf25a83f 100644 --- a/arch/arm/include/asm/arch-stm32f4/gpio.h +++ b/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -11,150 +11,6 @@ #ifndef _STM32_GPIO_H_ #define _STM32_GPIO_H_ -#if (CONFIG_STM32_USART == 1) -#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A -#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9 -#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10 -#define STM32_GPIO_USART STM32_GPIO_AF7 - -#elif (CONFIG_STM32_USART == 2) -#define STM32_GPIO_PORT_X STM32_GPIO_PORT_D -#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_5 -#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_6 -#define STM32_GPIO_USART STM32_GPIO_AF7 - -#elif (CONFIG_STM32_USART == 3) -#define STM32_GPIO_PORT_X STM32_GPIO_PORT_C -#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_10 -#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_11 -#define STM32_GPIO_USART STM32_GPIO_AF7 - -#elif (CONFIG_STM32_USART == 6) -#define STM32_GPIO_PORT_X STM32_GPIO_PORT_G -#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_14 -#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_9 -#define STM32_GPIO_USART STM32_GPIO_AF8 - -#else -#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A -#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9 -#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10 -#define STM32_GPIO_USART STM32_GPIO_AF7 - -#endif - -enum stm32_gpio_port { - STM32_GPIO_PORT_A = 0, - STM32_GPIO_PORT_B, - STM32_GPIO_PORT_C, - STM32_GPIO_PORT_D, - STM32_GPIO_PORT_E, - STM32_GPIO_PORT_F, - STM32_GPIO_PORT_G, - STM32_GPIO_PORT_H, - STM32_GPIO_PORT_I -}; - -enum stm32_gpio_pin { - STM32_GPIO_PIN_0 = 0, - STM32_GPIO_PIN_1, - STM32_GPIO_PIN_2, - STM32_GPIO_PIN_3, - STM32_GPIO_PIN_4, - STM32_GPIO_PIN_5, - STM32_GPIO_PIN_6, - STM32_GPIO_PIN_7, - STM32_GPIO_PIN_8, - STM32_GPIO_PIN_9, - STM32_GPIO_PIN_10, - STM32_GPIO_PIN_11, - STM32_GPIO_PIN_12, - STM32_GPIO_PIN_13, - STM32_GPIO_PIN_14, - STM32_GPIO_PIN_15 -}; - -enum stm32_gpio_mode { - STM32_GPIO_MODE_IN = 0, - STM32_GPIO_MODE_OUT, - STM32_GPIO_MODE_AF, - STM32_GPIO_MODE_AN -}; - -enum stm32_gpio_otype { - STM32_GPIO_OTYPE_PP = 0, - STM32_GPIO_OTYPE_OD -}; - -enum stm32_gpio_speed { - STM32_GPIO_SPEED_2M = 0, - STM32_GPIO_SPEED_25M, - STM32_GPIO_SPEED_50M, - STM32_GPIO_SPEED_100M -}; - -enum stm32_gpio_pupd { - STM32_GPIO_PUPD_NO = 0, - STM32_GPIO_PUPD_UP, - STM32_GPIO_PUPD_DOWN -}; - -enum stm32_gpio_af { - STM32_GPIO_AF0 = 0, - STM32_GPIO_AF1, - STM32_GPIO_AF2, - STM32_GPIO_AF3, - STM32_GPIO_AF4, - STM32_GPIO_AF5, - STM32_GPIO_AF6, - STM32_GPIO_AF7, - STM32_GPIO_AF8, - STM32_GPIO_AF9, - STM32_GPIO_AF10, - STM32_GPIO_AF11, - STM32_GPIO_AF12, - STM32_GPIO_AF13, - STM32_GPIO_AF14, - STM32_GPIO_AF15 -}; - -struct stm32_gpio_dsc { - enum stm32_gpio_port port; - enum stm32_gpio_pin pin; -}; - -struct stm32_gpio_ctl { - enum stm32_gpio_mode mode; - enum stm32_gpio_otype otype; - enum stm32_gpio_speed speed; - enum stm32_gpio_pupd pupd; - enum stm32_gpio_af af; -}; - -struct stm32_gpio_regs { - u32 moder; /* GPIO port mode */ - u32 otyper; /* GPIO port output type */ - u32 ospeedr; /* GPIO port output speed */ - u32 pupdr; /* GPIO port pull-up/pull-down */ - u32 idr; /* GPIO port input data */ - u32 odr; /* GPIO port output data */ - u32 bsrr; /* GPIO port bit set/reset */ - u32 lckr; /* GPIO port configuration lock */ - u32 afr[2]; /* GPIO alternate function */ -}; - -struct stm32_gpio_priv { - struct stm32_gpio_regs *regs; -}; - -static inline unsigned stm32_gpio_to_port(unsigned gpio) -{ - return gpio / 16; -} - -static inline unsigned stm32_gpio_to_pin(unsigned gpio) -{ - return gpio % 16; -} +#include <asm/arch-stm32/gpio.h> #endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 0449fcecede..903931243c2 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -11,17 +11,12 @@ #ifndef _MACH_STM32_H_ #define _MACH_STM32_H_ +#include <asm/arch-stm32/stm32f.h> + /* * Peripheral memory map */ #define STM32_SYSMEM_BASE 0x1FFF0000 -#define STM32_PERIPH_BASE 0x40000000 -#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) -#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) -#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000) - -#define STM32_BUS_MASK 0xFFFF0000 /* * Register maps @@ -37,18 +32,10 @@ struct stm32_u_id_regs { */ #define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) #define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) - -#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) -#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) - -#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) - static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [0 ... 3] = 16 * 1024, [4] = 64 * 1024, [5 ... 11] = 128 * 1024 }; -void stm32_flash_latency_cfg(int latency); - #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h deleted file mode 100644 index 9a967ac38a1..00000000000 --- a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __STM32_DEFS_H__ -#define __STM32_DEFS_H__ -#include <asm/arch/stm32_periph.h> - -int clock_setup(enum periph_clock); - -#endif - diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h deleted file mode 100644 index fa45a5c0f1c..00000000000 --- a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_PERIPH_H -#define __ASM_ARM_ARCH_PERIPH_H - -/* - * Peripherals required for pinmux configuration. List will - * grow with support for more devices getting added. - * Numbering based on interrupt table. - * - */ -enum periph_id { - UART1_GPIOA_9_10 = 0, - UART2_GPIOD_5_6, -}; - -enum periph_clock { - USART1_CLOCK_CFG = 0, - USART2_CLOCK_CFG, - GPIO_A_CLOCK_CFG, - GPIO_B_CLOCK_CFG, - GPIO_C_CLOCK_CFG, - GPIO_D_CLOCK_CFG, - GPIO_E_CLOCK_CFG, - GPIO_F_CLOCK_CFG, - GPIO_G_CLOCK_CFG, - GPIO_H_CLOCK_CFG, - GPIO_I_CLOCK_CFG, - GPIO_J_CLOCK_CFG, - GPIO_K_CLOCK_CFG, -}; - -#endif /* __ASM_ARM_ARCH_PERIPH_H */ |