diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/ddr.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/imx-regs.h | 10 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-imx8ulp/s400_api.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx27/imx-regs.h | 24 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx31/imx-regs.h | 12 |
5 files changed, 43 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 0f1e832c038..2ce8a8f2d41 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -723,6 +723,7 @@ void ddrphy_init_read_msg_block(enum fw_type type); void update_umctl2_rank_space_setting(unsigned int pstat_num); void get_trained_CDD(unsigned int fsp); +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr); static inline void reg32_write(unsigned long addr, u32 val) { diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b2a8ad77ae1..1da75528d46 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -48,6 +48,16 @@ #ifdef CONFIG_IMX8MM #define USDHC3_BASE_ADDR 0x30B60000 #endif +#define UART_BASE_ADDR(n) ( \ + !!sizeof(struct { \ + static_assert((n) >= 1 && (n) <= 4); \ + int pad; \ + }) * ( \ + (n) == 1 ? UART1_BASE_ADDR : \ + (n) == 2 ? UART2_BASE_ADDR : \ + (n) == 3 ? UART3_BASE_ADDR : \ + UART4_BASE_ADDR) \ + ) #define TZASC_BASE_ADDR 0x32F80000 diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h index 1856659877e..b3e6b3fa45d 100644 --- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h +++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h @@ -17,6 +17,7 @@ #define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91 #define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95 #define AHAB_READ_FUSE_REQ_CID 0x97 +#define AHAB_GET_FW_VERSION_CID 0x9D #define AHAB_RELEASE_RDC_REQ_CID 0xC4 #define AHAB_WRITE_FUSE_REQ_CID 0xD6 #define AHAB_CAAM_RELEASE_CID 0xD7 @@ -39,6 +40,7 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response); int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); int ahab_release_caam(u32 core_did, u32 *response); +int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); int ahab_dump_buffer(u32 *buffer, u32 buffer_length); #endif diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index d39f6b03508..77794d7d03d 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -179,16 +179,16 @@ struct fuse_bank0_regs { #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) #define IMX_RTC_BASE (0x07000 + IMX_IO_BASE) -#define UART1_BASE (0x0a000 + IMX_IO_BASE) -#define UART2_BASE (0x0b000 + IMX_IO_BASE) -#define UART3_BASE (0x0c000 + IMX_IO_BASE) -#define UART4_BASE (0x0d000 + IMX_IO_BASE) +#define UART1_BASE_ADDR (0x0a000 + IMX_IO_BASE) +#define UART2_BASE_ADDR (0x0b000 + IMX_IO_BASE) +#define UART3_BASE_ADDR (0x0c000 + IMX_IO_BASE) +#define UART4_BASE_ADDR (0x0d000 + IMX_IO_BASE) #define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) #define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) -#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) -#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) +#define UART5_BASE_ADDR (0x1b000 + IMX_IO_BASE) +#define UART6_BASE_ADDR (0x1c000 + IMX_IO_BASE) #define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) #define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) #define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) @@ -204,6 +204,18 @@ struct fuse_bank0_regs { #define NFC_BASE_ADDR IMX_NFC_BASE +#define UART_BASE_ADDR(n) ( \ + !!sizeof(struct { \ + static_assert((n) >= 1 && (n) <= 6); \ + int pad; \ + }) * ( \ + (n) == 1 ? UART1_BASE_ADDR : \ + (n) == 2 ? UART2_BASE_ADDR : \ + (n) == 3 ? UART3_BASE_ADDR : \ + (n) == 4 ? UART4_BASE_ADDR : \ + (n) == 5 ? UART5_BASE_ADDR : \ + UART6_BASE_ADDR) \ + ) /* FMCR System Control bit definition*/ #define UART4_RXD_CTL (1 << 25) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 566db549ec6..d5c0ed8e6c2 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -598,6 +598,18 @@ struct esdc_regs { #define UART4_BASE 0x43FB0000 #define UART5_BASE 0x43FB4000 +#define UART_BASE_ADDR(n) ( \ + !!sizeof(struct { \ + static_assert((n) >= 1 && (n) <= 5); \ + int pad; \ + }) * ( \ + (n) == 1 ? UART1_BASE : \ + (n) == 2 ? UART2_BASE : \ + (n) == 3 ? UART3_BASE : \ + (n) == 4 ? UART4_BASE : \ + UART5_BASE_ADDR) \ + ) + #define I2C1_BASE_ADDR 0x43f80000 #define I2C1_CLK_OFFSET 26 #define I2C2_BASE_ADDR 0x43F98000 |