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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 0535224646b..9fab88ab2ff 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -2,7 +2,7 @@
/*
* LayerScape Internal Memory Map
*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*/
@@ -350,6 +350,14 @@ struct ccsr_gur {
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#define FSL_CHASSIS3_SRDS3_REGSR 29
+#define FSL_CHASSIS3_RCWSR12_REGSR 12
+#define FSL_CHASSIS3_RCWSR13_REGSR 13
+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
+#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
+#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
#elif defined(CONFIG_ARCH_LS1088A)
#define FSL_CHASSIS3_EC1_REGSR 26
#define FSL_CHASSIS3_EC2_REGSR 26