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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6sl_pins.h8
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_px30.h6
-rw-r--r--arch/arm/include/asm/arch-rockchip/f_rockusb.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_px30.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_rk3328.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_rv1126.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h7
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h4
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h230
-rw-r--r--arch/arm/include/asm/global_data.h6
-rw-r--r--arch/arm/include/asm/iproc-common/sysmap.h20
13 files changed, 268 insertions, 25 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 306f797f7a8..86d295c1a8d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -241,7 +241,7 @@
#define DCFG_RCWSR15 0x138
#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
-#define DCFG_DCSR_BASE 0X700100000ULL
+#define DCFG_DCSR_BASE 0x700100000ULL
#define DCFG_DCSR_PORCR1 0x000
/* Interrupt Sampling Control */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 01b14d73dc9..699c951b1b9 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -31,10 +31,10 @@ enum {
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
- MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0),
- MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0),
- MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0),
- MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0),
+ MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h
index 504459bd93d..408fdd66635 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h
@@ -299,9 +299,9 @@ enum {
/* CRU_CLK_SEL30_CON */
CLK_I2S1_DIV_CON_MASK = 0x7f,
- CLK_I2S1_PLL_SEL_MASK = 0X1 << 8,
- CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8,
- CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8,
+ CLK_I2S1_PLL_SEL_MASK = 0x1 << 8,
+ CLK_I2S1_PLL_SEL_GPLL = 0x0 << 8,
+ CLK_I2S1_PLL_SEL_NPLL = 0x1 << 8,
CLK_I2S1_SEL_MASK = 0x3 << 10,
CLK_I2S1_SEL_I2S1 = 0x0 << 10,
CLK_I2S1_SEL_FRAC = 0x1 << 10,
diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
index e9c7f793391..9abb3b16c42 100644
--- a/arch/arm/include/asm/arch-rockchip/f_rockusb.h
+++ b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
@@ -65,7 +65,7 @@ K_FW_SPI_READ_10 = 0x21,
K_FW_SPI_WRITE_10 = 0x22,
K_FW_LBA_ERASE_10 = 0x25,
-K_FW_SESSION = 0X30,
+K_FW_SESSION = 0x30,
K_FW_RESET = 0xff,
};
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_px30.h
index 2ab8e97ae1d..bf0cd01e7cc 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_px30.h
@@ -20,7 +20,7 @@
/* DDR GRF */
#define DDR_GRF_CON(n) (0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE (0X100)
+#define DDR_GRF_STATUS_BASE (0x100)
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
#define DDR_GRF_LP_CON (0x20)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
index 10923505d6e..454f9ca8878 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
@@ -32,7 +32,7 @@
/* DDR GRF */
#define DDR_GRF_CON(n) (0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE (0X100)
+#define DDR_GRF_STATUS_BASE (0x100)
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
/* CRU_SOFTRESET_CON5 */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
index 6a07436059c..9b65bad2581 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
@@ -185,7 +185,7 @@
/* DDR GRF */
#define DDR_GRF_CON(n) (0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE (0X100)
+#define DDR_GRF_STATUS_BASE (0x100)
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
#define DDR_GRF_LP_CON (0x20)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index ccacc99d018..575dff68804 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -90,6 +90,13 @@
#define CCM_PLL6_DEFAULT 0xe8216300
#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002
#define CCM_APB1_DEFAULT 0x03000102
+
+#elif CONFIG_MACH_SUN50I_A133 /* A133 */
+
+#define CCM_PLL6_DEFAULT 0xb8003100
+#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002
+#define CCM_AHB3_DEFAULT 0x03000002
+#define CCM_APB1_DEFAULT 0x03000102
#endif
/* apb2 bit field */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
index 8a3f465545a..2a9b086991c 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
@@ -29,6 +29,10 @@
#define SUNXI_DRAM_COM_BASE 0x047FA000
#define SUNXI_DRAM_CTL0_BASE 0x047FB000
#define SUNXI_DRAM_PHY0_BASE 0x04800000
+#elif CONFIG_MACH_SUN50I_A133
+#define SUNXI_DRAM_COM_BASE 0x04810000
+#define SUNXI_DRAM_CTL0_BASE 0x04820000
+#define SUNXI_DRAM_PHY0_BASE 0x04830000
#endif
#define SUNXI_TWI0_BASE 0x05002000
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 9d21b492418..0708ae3ee3b 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -31,6 +31,8 @@
#include <asm/arch/dram_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN50I_H616)
#include <asm/arch/dram_sun50i_h616.h>
+#elif defined(CONFIG_DRAM_SUN50I_A133)
+#include <asm/arch/dram_sun50i_a133.h>
#elif defined(CONFIG_MACH_SUNIV)
#include <asm/arch/dram_suniv.h>
#else
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
new file mode 100644
index 00000000000..a5fc6ad3656
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * A133 dram controller register and constant defines
+ *
+ * (C) Copyright 2024 MasterR3C0RD <masterr3c0rd@epochal.quest>
+ */
+
+#ifndef _SUNXI_DRAM_SUN50I_A133_H
+#define _SUNXI_DRAM_SUN50I_A133_H
+
+#include <linux/bitops.h>
+
+enum sunxi_dram_type {
+ SUNXI_DRAM_TYPE_DDR3 = 3,
+ SUNXI_DRAM_TYPE_DDR4,
+ SUNXI_DRAM_TYPE_LPDDR3 = 7,
+ SUNXI_DRAM_TYPE_LPDDR4
+};
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+ return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+/* MBUS part is largely the same as in H6, except for one special register */
+#define MCTL_COM_UNK_008 0x008
+/* NOTE: This register has the same importance as mctl_ctl->clken in H616 */
+#define MCTL_COM_MAER0 0x020
+
+/*
+ * Controller registers seems to be the same or at least very similar
+ * to those in H6.
+ */
+struct sunxi_mctl_ctl_reg {
+ u32 mstr; /* 0x000 */
+ u32 statr; /* 0x004 unused */
+ u32 mstr1; /* 0x008 unused */
+ u32 clken; /* 0x00c */
+ u32 mrctrl0; /* 0x010 unused */
+ u32 mrctrl1; /* 0x014 unused */
+ u32 mrstatr; /* 0x018 unused */
+ u32 mrctrl2; /* 0x01c unused */
+ u32 derateen; /* 0x020 unused */
+ u32 derateint; /* 0x024 unused */
+ u8 reserved_0x028[8]; /* 0x028 */
+ u32 pwrctl; /* 0x030 unused */
+ u32 pwrtmg; /* 0x034 unused */
+ u32 hwlpctl; /* 0x038 unused */
+ u8 reserved_0x03c[20]; /* 0x03c */
+ u32 rfshctl0; /* 0x050 unused */
+ u32 rfshctl1; /* 0x054 unused */
+ u8 reserved_0x058[8]; /* 0x05c */
+ u32 rfshctl3; /* 0x060 */
+ u32 rfshtmg; /* 0x064 */
+ u8 reserved_0x068[104]; /* 0x068 */
+ u32 init[8]; /* 0x0d0 */
+ u32 dimmctl; /* 0x0f0 unused */
+ u32 rankctl; /* 0x0f4 */
+ u8 reserved_0x0f8[8]; /* 0x0f8 */
+ u32 dramtmg[17]; /* 0x100 */
+ u8 reserved_0x144[60]; /* 0x144 */
+ u32 zqctl[3]; /* 0x180 */
+ u32 zqstat; /* 0x18c unused */
+ u32 dfitmg0; /* 0x190 */
+ u32 dfitmg1; /* 0x194 */
+ u32 dfilpcfg[2]; /* 0x198 unused */
+ u32 dfiupd[3]; /* 0x1a0 */
+ u32 reserved_0x1ac; /* 0x1ac */
+ u32 dfimisc; /* 0x1b0 */
+ u32 dfitmg2; /* 0x1b4 unused */
+ u32 dfitmg3; /* 0x1b8 unused */
+ u32 dfistat; /* 0x1bc */
+ u32 dbictl; /* 0x1c0 */
+ u8 reserved_0x1c4[60]; /* 0x1c4 */
+ u32 addrmap[12]; /* 0x200 */
+ u8 reserved_0x230[16]; /* 0x230 */
+ u32 odtcfg; /* 0x240 */
+ u32 odtmap; /* 0x244 */
+ u8 reserved_0x248[8]; /* 0x248 */
+ u32 sched[2]; /* 0x250 */
+ u8 reserved_0x258[180]; /* 0x258 */
+ u32 dbgcmd; /* 0x30c unused */
+ u32 dbgstat; /* 0x310 unused */
+ u8 reserved_0x314[12]; /* 0x314 */
+ u32 swctl; /* 0x320 */
+ u32 swstat; /* 0x324 */
+ u8 reserved_0x328[7768]; /* 0x328 */
+ u32 unk_0x2180; /* 0x2180 */
+ u8 reserved_0x2184[188]; /* 0x2184 */
+ u32 unk_0x2240; /* 0x2240 */
+ u8 reserved_0x2244[3900]; /* 0x2244 */
+ u32 unk_0x3180; /* 0x3180 */
+ u8 reserved_0x3184[188]; /* 0x3184 */
+ u32 unk_0x3240; /* 0x3240 */
+ u8 reserved_0x3244[3900]; /* 0x3244 */
+ u32 unk_0x4180; /* 0x4180 */
+ u8 reserved_0x4184[188]; /* 0x4184 */
+ u32 unk_0x4240; /* 0x4240 */
+};
+
+check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
+check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
+
+#define MSTR_DEVICETYPE_DDR3 BIT(0)
+#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
+#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
+#define MSTR_DEVICETYPE_DDR4 BIT(4)
+#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
+#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
+#define MSTR_GEARDOWNMODE BIT(0) /* Same as MSTR_DEVICETYPE_DDR3, only used for DDR4 */
+#define MSTR_2TMODE BIT(10)
+#define MSTR_BUSWIDTH_FULL (0 << 12)
+#define MSTR_BUSWIDTH_HALF (1 << 12)
+#define MSTR_ACTIVE_RANKS(x) (((x == 1) ? 3 : 1) << 24)
+#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
+#define MSTR_DEVICECONFIG_X32 (3 << 30)
+
+#define TPR10_CA_BIT_DELAY BIT(16)
+#define TPR10_DX_BIT_DELAY0 BIT(17)
+#define TPR10_DX_BIT_DELAY1 BIT(18)
+#define TPR10_WRITE_LEVELING BIT(20)
+#define TPR10_READ_CALIBRATION BIT(21)
+#define TPR10_READ_TRAINING BIT(22)
+#define TPR10_WRITE_TRAINING BIT(23)
+
+/* MRCTRL constants */
+#define MRCTRL0_MR_RANKS_ALL (3 << 4)
+#define MRCTRL0_MR_ADDR(x) (x << 12)
+#define MRCTRL0_MR_WR BIT(31)
+
+#define MRCTRL1_MR_ADDR(x) (x << 8)
+#define MRCTRL1_MR_DATA(x) (x)
+
+/* ADDRMAP constants */
+#define ADDRMAP_DISABLED_3F_B(b) (0x3f + b)
+#define ADDRMAP_DISABLED_1F_B(b) (0x1f + b)
+#define ADDRMAP_DISABLED_0F_B(b) (0x0f + b)
+
+#define _ADDRMAP_VALUE(a,x,b) (((a) - b) << (x * 8))
+
+/*
+ * Bx = internal base
+ * The selected HIF address bit for each address bit is determined
+ * by adding the internal base to the value of each field
+ * */
+
+#define ADDRMAP0_CS0_B6(v) _ADDRMAP_VALUE(v, 0, 6)
+
+#define ADDRMAP1_BANK0_B2(v) _ADDRMAP_VALUE(v, 0, 2)
+#define ADDRMAP1_BANK1_B3(v) _ADDRMAP_VALUE(v, 1, 3)
+#define ADDRMAP1_BANK2_B4(v) _ADDRMAP_VALUE(v, 2, 4)
+
+#define ADDRMAP2_COL2_B2(v) _ADDRMAP_VALUE(v, 0, 2)
+#define ADDRMAP2_COL3_B3(v) _ADDRMAP_VALUE(v, 1, 3)
+#define ADDRMAP2_COL4_B4(v) _ADDRMAP_VALUE(v, 2, 4)
+#define ADDRMAP2_COL5_B5(v) _ADDRMAP_VALUE(v, 3, 5)
+
+#define ADDRMAP3_COL6_B6(v) _ADDRMAP_VALUE(v, 0, 6)
+#define ADDRMAP3_COL7_B7(v) _ADDRMAP_VALUE(v, 1, 7)
+#define ADDRMAP3_COL8_B8(v) _ADDRMAP_VALUE(v, 2, 8)
+#define ADDRMAP3_COL9_B9(v) _ADDRMAP_VALUE(v, 3, 9)
+
+#define ADDRMAP4_COL10_B10(v) _ADDRMAP_VALUE(v, 0, 10)
+#define ADDRMAP4_COL11_B11(v) _ADDRMAP_VALUE(v, 1, 11)
+
+#define ADDRMAP5_ROW0_B6(v) _ADDRMAP_VALUE(v, 0, 6)
+#define ADDRMAP5_ROW1_B7(v) _ADDRMAP_VALUE(v, 1, 7)
+#define ADDRMAP5_ROW2_10_B8(v) _ADDRMAP_VALUE(v, 2, 8)
+#define ADDRMAP5_ROW11_B17(v) _ADDRMAP_VALUE(v, 3, 17)
+
+#define ADDRMAP6_ROW12_B18(v) _ADDRMAP_VALUE(v, 0, 18)
+#define ADDRMAP6_ROW13_B19(v) _ADDRMAP_VALUE(v, 1, 19)
+#define ADDRMAP6_ROW14_B20(v) _ADDRMAP_VALUE(v, 2, 20)
+#define ADDRMAP6_ROW15_B21(v) _ADDRMAP_VALUE(v, 3, 21)
+
+#define ADDRMAP7_ROW16_B22(v) _ADDRMAP_VALUE(v, 0, 22)
+#define ADDRMAP7_ROW17_B23(v) _ADDRMAP_VALUE(v, 1, 23)
+
+#define ADDRMAP8_BG0_B2(v) _ADDRMAP_VALUE(v, 0, 2)
+#define ADDRMAP8_BG1_B3(v) _ADDRMAP_VALUE(v, 1, 3)
+
+/* These are only used if ADDRMAP5_ROW_BITS_2_10 = ADDRMAP_DISABLED_0F */
+#define ADDRMAP9_ROW2_B8(v) _ADDRMAP_VALUE(v, 0, 8)
+#define ADDRMAP9_ROW3_B9(v) _ADDRMAP_VALUE(v, 1, 9)
+#define ADDRMAP9_ROW4_B10(v) _ADDRMAP_VALUE(v, 2, 10)
+#define ADDRMAP9_ROW5_B11(v) _ADDRMAP_VALUE(v, 3, 11)
+
+#define ADDRMAP10_ROW6_B12(v) _ADDRMAP_VALUE(v, 0, 12)
+#define ADDRMAP10_ROW7_B13(v) _ADDRMAP_VALUE(v, 1, 13)
+#define ADDRMAP10_ROW8_B14(v) _ADDRMAP_VALUE(v, 2, 14)
+#define ADDRMAP10_ROW9_B15(v) _ADDRMAP_VALUE(v, 3, 15)
+
+#define ADDRMAP11_ROW10_B16(v) _ADDRMAP_VALUE(v, 0, 16)
+
+struct dram_para {
+ uint32_t clk;
+ enum sunxi_dram_type type;
+ uint32_t dx_odt;
+ uint32_t dx_dri;
+ uint32_t ca_dri;
+ uint32_t para0;
+ uint32_t mr11;
+ uint32_t mr12;
+ uint32_t mr13;
+ uint32_t mr14;
+ uint32_t tpr1;
+ uint32_t tpr2;
+ uint32_t tpr3;
+ uint32_t tpr6;
+ uint32_t tpr10;
+ uint32_t tpr11;
+ uint32_t tpr12;
+ uint32_t tpr13;
+ uint32_t tpr14;
+};
+
+void mctl_set_timing_params(const struct dram_para *para);
+
+struct dram_config {
+ u8 cols; /* Column bits */
+ u8 rows; /* Row bits */
+ u8 ranks; /* Rank bits (different from H616!) */
+ u8 banks; /* Bank bits */
+ u8 bankgrps; /* Bank group bits */
+ u8 bus_full_width; /* 1 = x32, 0 = x16 */
+};
+
+#endif /* _SUNXI_DRAM_SUN50I_A133_H */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 45401d5e3c8..b2ec450f900 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -133,13 +133,13 @@ static inline gd_t *get_gd(void)
#else
#ifdef CONFIG_ARM64
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18")
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("x18")
#else
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r9")
#endif
#endif
-static inline void set_gd(volatile gd_t *gd_ptr)
+static inline void set_gd(gd_t *gd_ptr)
{
#ifdef CONFIG_ARM64
__asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
diff --git a/arch/arm/include/asm/iproc-common/sysmap.h b/arch/arm/include/asm/iproc-common/sysmap.h
index efd2f35f212..c071e9ea53f 100644
--- a/arch/arm/include/asm/iproc-common/sysmap.h
+++ b/arch/arm/include/asm/iproc-common/sysmap.h
@@ -6,17 +6,17 @@
#ifndef __SYSMAP_H
#define __SYSMAP_H
-#define IHOST_PROC_CLK_PLLARMA 0X19000C00
-#define IHOST_PROC_CLK_PLLARMB 0X19000C04
+#define IHOST_PROC_CLK_PLLARMA 0x19000C00
+#define IHOST_PROC_CLK_PLLARMB 0x19000C04
#define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24
-#define IHOST_PROC_CLK_WR_ACCESS 0X19000000
-#define IHOST_PROC_CLK_POLICY_FREQ 0X19000008
+#define IHOST_PROC_CLK_WR_ACCESS 0x19000000
+#define IHOST_PROC_CLK_POLICY_FREQ 0x19000008
#define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31
#define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24
#define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16
#define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8
-#define IHOST_PROC_CLK_POLICY_CTL 0X1900000C
+#define IHOST_PROC_CLK_POLICY_CTL 0x1900000C
#define IHOST_PROC_CLK_POLICY_CTL__GO 0
#define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1
#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0
@@ -26,11 +26,11 @@
#define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8
#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1
#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0
-#define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200
-#define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204
-#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210
-#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300
-#define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400
+#define IHOST_PROC_CLK_CORE0_CLKGATE 0x19000200
+#define IHOST_PROC_CLK_CORE1_CLKGATE 0x19000204
+#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0x19000210
+#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0x19000300
+#define IHOST_PROC_CLK_APB0_CLKGATE 0x19000400
#define IPROC_CLKCT_HDELAY_SW_EN 0x00000303
#define IPROC_REG_WRITE_ACCESS 0x00a5a501
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-12 20:48:54 +0000