15 files changed, 151 insertions, 255 deletions

diff --git a/arch/arm/include/asm/arch-apple/rtkit.h b/arch/arm/include/asm/arch-apple/rtkit.h
index eff18ddb9d2..4b11e2a72dc 100644
--- a/arch/arm/include/asm/arch-apple/rtkit.h
+++ b/arch/arm/include/asm/arch-apple/rtkit.h
@@ -12,6 +12,7 @@ struct apple_rtkit_buffer {
 	u64 dva;
 	size_t size;
 	bool is_mapped;
+	int endpoint;
 };
 
 typedef int (*apple_rtkit_shmem_setup)(void *cookie,
@@ -26,4 +27,8 @@ struct apple_rtkit *apple_rtkit_init(struct mbox_chan *chan, void *cookie,
 				     apple_rtkit_shmem_destroy shmem_destroy);
 void apple_rtkit_free(struct apple_rtkit *rtk);
 int apple_rtkit_boot(struct apple_rtkit *rtk);
+int apple_rtkit_set_ap_power(struct apple_rtkit *rtk, int pwrstate);
+int apple_rtkit_poll(struct apple_rtkit *rtk, ulong timeout);
 int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate);
+
+int apple_rtkit_helper_poll(struct udevice *dev, ulong timeout);
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 0d7a5734616..1f669c72d00 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -76,6 +76,8 @@
 #define MXC_CPU_IMX9111		0xCD /* dummy ID */
 #define MXC_CPU_IMX9101		0xCE /* dummy ID */
 
+#define MXC_CPU_IMX95		0x1C1 /* dummy ID */
+
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
 #define MXC_SOC_IMX8M		0x80
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
index 60d48b13b11..ffaf6b5f7d8 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -255,5 +255,15 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock
 void enable_usboh3_clk(unsigned char enable);
 int set_clk_enet(enum enet_freq type);
 int set_clk_eqos(enum enet_freq type);
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable);
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate);
+ulong imx_clk_scmi_get_rate(u32 clock_id);
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id);
 void set_arm_clk(ulong freq);
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable);
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate);
+ulong imx_clk_scmi_get_rate(u32 clock_id);
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id);
 #endif
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index ef9538bd42e..5127fe8f286 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -13,6 +13,7 @@
 #define CCM_BASE_ADDR		0x44450000UL
 #define CCM_CCGR_BASE_ADDR	0x44458000UL
 #define SYSCNT_CTRL_BASE_ADDR	0x44290000
+#define SYSCNT_CMP_BASE_ADDR	(SYSCNT_CTRL_BASE_ADDR + 0x10000)
 
 #define ANATOP_BASE_ADDR    0x44480000UL
 
@@ -20,6 +21,11 @@
 #define WDG4_BASE_ADDR      0x424a0000UL
 #define WDG5_BASE_ADDR      0x424b0000UL
 
+#define GPIO2_BASE_ADDR	    0x43810000UL
+#define GPIO3_BASE_ADDR	    0x43820000UL
+#define GPIO4_BASE_ADDR	    0x43840000UL
+#define GPIO5_BASE_ADDR	    0x43850000UL
+
 #define FSB_BASE_ADDR       0x47510000UL
 
 #define ANATOP_BASE_ADDR    0x44480000UL
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
index e4bf6a63424..df2148a53c7 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -12,6 +12,7 @@ enum imx9_soc_voltage_mode {
 	VOLT_LOW_DRIVE = 0,
 	VOLT_NOMINAL_DRIVE,
 	VOLT_OVER_DRIVE,
+	VOLT_SUPER_OVER_DRIVE,
 };
 
 void soc_power_init(void);
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 24c81391d58..d79aea97a40 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -26,11 +26,21 @@
 	.word	0xe580e004	// str     lr, [r0, #4]
 	.word	0xe10fe000	// mrs     lr, CPSR
 	.word	0xe580e008	// str     lr, [r0, #8]
+	.word	0xe101e300	// mrs     lr, SP_irq
+	.word	0xe580e014	// str     lr, [r0, #20]
 	.word	0xee11ef10	// mrc     15, 0, lr, cr1, cr0, {0}
 	.word	0xe580e00c	// str     lr, [r0, #12]
 	.word	0xee1cef10	// mrc     15, 0, lr, cr12, cr0, {0}
 	.word	0xe580e010	// str     lr, [r0, #16]
-
+#ifdef CONFIG_MACH_SUN55I_A523
+	.word	0xee1cefbc	// mrc     15, 0, lr, cr12, cr12, {5}
+	.word	0xe31e0001	// tst     lr, #1
+	.word	0x0a000003	// beq     cc <start32+0x48>
+	.word	0xee14ef16	// mrc     15, 0, lr, cr4, cr6, {0}
+	.word	0xe580e018	// str     lr, [r0, #24]
+	.word	0xee1ceffc	// mrc     15, 0, lr, cr12, cr12, {7}
+	.word	0xe580e01c	// str     lr, [r0, #28]
+#endif
 	.word	0xe59f1034	// ldr     r1, [pc, #52] ; RVBAR_ADDRESS
 	.word	0xe59f0034	// ldr     r0, [pc, #52] ; SUNXI_SRAMC_BASE
 	.word	0xe5900024	// ldr     r0, [r0, #36] ; SRAM_VER_REG
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 2cec91cb20e..00bdd5f938d 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -10,6 +10,12 @@
 #ifndef _SUNXI_CLOCK_SUN4I_H
 #define _SUNXI_CLOCK_SUN4I_H
 
+#define CCU_AHB_GATE0		0x60
+#define CCU_MMC0_CLK_CFG	0x88
+#define CCU_MMC1_CLK_CFG	0x8c
+#define CCU_MMC2_CLK_CFG	0x90
+#define CCU_MMC3_CLK_CFG	0x94
+
 struct sunxi_ccm_reg {
 	u32 pll1_cfg;		/* 0x00 pll1 control */
 	u32 pll1_tun;		/* 0x04 pll1 tuning */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 76dd33c9477..ccacc99d018 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -13,218 +13,23 @@
 #include <linux/bitops.h>
 #endif
 
-struct sunxi_ccm_reg {
-	u32 pll1_cfg;		/* 0x000 pll1 (cpux) control */
-	u8 reserved_0x004[12];
-	u32 pll5_cfg;		/* 0x010 pll5 (ddr) control */
-	u8 reserved_0x014[12];
-	u32 pll6_cfg;		/* 0x020 pll6 (periph0) control */
-	u8 reserved_0x020[4];
-	u32 pll_periph1_cfg;	/* 0x028 pll periph1 control */
-	u8 reserved_0x028[4];
-	u32 pll7_cfg;		/* 0x030 pll7 (gpu) control */
-	u8 reserved_0x034[12];
-	u32 pll3_cfg;		/* 0x040 pll3 (video0) control */
-	u8 reserved_0x044[4];
-	u32 pll_video1_cfg;	/* 0x048 pll video1 control */
-	u8 reserved_0x04c[12];
-	u32 pll4_cfg;		/* 0x058 pll4 (ve) control */
-	u8 reserved_0x05c[4];
-	u32 pll10_cfg;		/* 0x060 pll10 (de) control */
-	u8 reserved_0x064[12];
-	u32 pll9_cfg;		/* 0x070 pll9 (hsic) control */
-	u8 reserved_0x074[4];
-	u32 pll2_cfg;		/* 0x078 pll2 (audio) control */
-	u8 reserved_0x07c[148];
-	u32 pll5_pat;		/* 0x110 pll5 (ddr) pattern */
-	u8 reserved_0x114[20];
-	u32 pll_periph1_pat0;	/* 0x128 pll periph1 pattern0 */
-	u32 pll_periph1_pat1;	/* 0x12c pll periph1 pattern1 */
-	u32 pll7_pat0;		/* 0x130 pll7 (gpu) pattern0 */
-	u32 pll7_pat1;		/* 0x134 pll7 (gpu) pattern1 */
-	u8 reserved_0x138[8];
-	u32 pll3_pat0;		/* 0x140 pll3 (video0) pattern0 */
-	u32 pll3_pat1;		/* 0x144 pll3 (video0) pattern1 */
-	u32 pll_video1_pat0;	/* 0x148 pll video1 pattern0 */
-	u32 pll_video1_pat1;	/* 0x14c pll video1 pattern1 */
-	u8 reserved_0x150[8];
-	u32 pll4_pat0;		/* 0x158 pll4 (ve) pattern0 */
-	u32 pll4_pat1;		/* 0x15c pll4 (ve) pattern1 */
-	u32 pll10_pat0;		/* 0x160 pll10 (de) pattern0 */
-	u32 pll10_pat1;		/* 0x164 pll10 (de) pattern1 */
-	u8 reserved_0x168[8];
-	u32 pll9_pat0;		/* 0x170 pll9 (hsic) pattern0 */
-	u32 pll9_pat1;		/* 0x174 pll9 (hsic) pattern1 */
-	u32 pll2_pat0;		/* 0x178 pll2 (audio) pattern0 */
-	u32 pll2_pat1;		/* 0x17c pll2 (audio) pattern1 */
-	u8 reserved_0x180[384];
-	u32 pll1_bias;		/* 0x300 pll1 (cpux) bias */
-	u8 reserved_0x304[12];
-	u32 pll5_bias;		/* 0x310 pll5 (ddr) bias */
-	u8 reserved_0x314[12];
-	u32 pll6_bias;		/* 0x320 pll6 (periph0) bias */
-	u8 reserved_0x324[4];
-	u32 pll_periph1_bias;	/* 0x328 pll periph1 bias */
-	u8 reserved_0x32c[4];
-	u32 pll7_bias;		/* 0x330 pll7 (gpu) bias */
-	u8 reserved_0x334[12];
-	u32 pll3_bias;		/* 0x340 pll3 (video0) bias */
-	u8 reserved_0x344[4];
-	u32 pll_video1_bias;	/* 0x348 pll video1 bias */
-	u8 reserved_0x34c[12];
-	u32 pll4_bias;		/* 0x358 pll4 (ve) bias */
-	u8 reserved_0x35c[4];
-	u32 pll10_bias;		/* 0x360 pll10 (de) bias */
-	u8 reserved_0x364[12];
-	u32 pll9_bias;		/* 0x370 pll9 (hsic) bias */
-	u8 reserved_0x374[4];
-	u32 pll2_bias;		/* 0x378 pll2 (audio) bias */
-	u8 reserved_0x37c[132];
-	u32 pll1_tun;		/* 0x400 pll1 (cpux) tunning */
-	u8 reserved_0x404[252];
-	u32 cpu_axi_cfg;	/* 0x500 CPUX/AXI clock control*/
-	u8 reserved_0x504[12];
-	u32 psi_ahb1_ahb2_cfg;	/* 0x510 PSI/AHB1/AHB2 clock control */
-	u8 reserved_0x514[8];
-	u32 ahb3_cfg;		/* 0x51c AHB3 clock control */
-	u32 apb1_cfg;		/* 0x520 APB1 clock control */
-	u32 apb2_cfg;		/* 0x524 APB2 clock control */
-	u8 reserved_0x528[24];
-	u32 mbus_cfg;		/* 0x540 MBUS clock control */
-	u8 reserved_0x544[188];
-	u32 de_clk_cfg;		/* 0x600 DE clock control */
-	u8 reserved_0x604[8];
-	u32 de_gate_reset;	/* 0x60c DE gate/reset control */
-	u8 reserved_0x610[16];
-	u32 di_clk_cfg;		/* 0x620 DI clock control */
-	u8 reserved_0x024[8];
-	u32 di_gate_reset;	/* 0x62c DI gate/reset control */
-	u8 reserved_0x630[64];
-	u32 gpu_clk_cfg;	/* 0x670 GPU clock control */
-	u8 reserved_0x674[8];
-	u32 gpu_gate_reset;	/* 0x67c GPU gate/reset control */
-	u32 ce_clk_cfg;		/* 0x680 CE clock control */
-	u8 reserved_0x684[8];
-	u32 ce_gate_reset;	/* 0x68c CE gate/reset control */
-	u32 ve_clk_cfg;		/* 0x690 VE clock control */
-	u8 reserved_0x694[8];
-	u32 ve_gate_reset;	/* 0x69c VE gate/reset control */
-	u8 reserved_0x6a0[16];
-	u32 emce_clk_cfg;	/* 0x6b0 EMCE clock control */
-	u8 reserved_0x6b4[8];
-	u32 emce_gate_reset;	/* 0x6bc EMCE gate/reset control */
-	u32 vp9_clk_cfg;	/* 0x6c0 VP9 clock control */
-	u8 reserved_0x6c4[8];
-	u32 vp9_gate_reset;	/* 0x6cc VP9 gate/reset control */
-	u8 reserved_0x6d0[60];
-	u32 dma_gate_reset;	/* 0x70c DMA gate/reset control */
-	u8 reserved_0x710[12];
-	u32 msgbox_gate_reset;	/* 0x71c Message Box gate/reset control */
-	u8 reserved_0x720[12];
-	u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */
-	u8 reserved_0x730[12];
-	u32 hstimer_gate_reset;	/* 0x73c HS Timer gate/reset control */
-	u32 avs_gate_reset;	/* 0x740 AVS gate/reset control */
-	u8 reserved_0x744[72];
-	u32 dbgsys_gate_reset;	/* 0x78c Debugging system gate/reset control */
-	u8 reserved_0x790[12];
-	u32 psi_gate_reset;	/* 0x79c PSI gate/reset control */
-	u8 reserved_0x7a0[12];
-	u32 pwm_gate_reset;	/* 0x7ac PWM gate/reset control */
-	u8 reserved_0x7b0[12];
-	u32 iommu_gate_reset;	/* 0x7bc IOMMU gate/reset control */
-	u8 reserved_0x7c0[64];
-	u32 dram_clk_cfg;		/* 0x800 DRAM clock control */
-	u32 mbus_gate;		/* 0x804 MBUS gate control */
-	u8 reserved_0x808[4];
-	u32 dram_gate_reset;	/* 0x80c DRAM gate/reset control */
-	u32 nand0_clk_cfg;	/* 0x810 NAND0 clock control */
-	u32 nand1_clk_cfg;	/* 0x814 NAND1 clock control */
-	u8 reserved_0x818[20];
-	u32 nand_gate_reset;	/* 0x82c NAND gate/reset control */
-	u32 sd0_clk_cfg;	/* 0x830 MMC0 clock control */
-	u32 sd1_clk_cfg;	/* 0x834 MMC1 clock control */
-	u32 sd2_clk_cfg;	/* 0x838 MMC2 clock control */
-	u8 reserved_0x83c[16];
-	u32 sd_gate_reset;	/* 0x84c MMC gate/reset control */
-	u8 reserved_0x850[188];
-	u32 uart_gate_reset;	/* 0x90c UART gate/reset control */
-	u8 reserved_0x910[12];
-	u32 twi_gate_reset;	/* 0x91c I2C gate/reset control */
-	u8 reserved_0x920[28];
-	u32 scr_gate_reset;	/* 0x93c SCR gate/reset control */
-	u32 spi0_clk_cfg;	/* 0x940 SPI0 clock control */
-	u32 spi1_clk_cfg;	/* 0x944 SPI1 clock control */
-	u8 reserved_0x948[36];
-	u32 spi_gate_reset;	/* 0x96c SPI gate/reset control */
-	u8 reserved_0x970[12];
-	u32 emac_gate_reset;	/* 0x97c EMAC gate/reset control */
-	u8 reserved_0x980[48];
-	u32 ts_clk_cfg;		/* 0x9b0 TS clock control */
-	u8 reserved_0x9b4[8];
-	u32 ts_gate_reset;	/* 0x9bc TS gate/reset control */
-	u32 irtx_clk_cfg;	/* 0x9c0 IR TX clock control */
-	u8 reserved_0x9c4[8];
-	u32 irtx_gate_reset;	/* 0x9cc IR TX gate/reset control */
-	u8 reserved_0x9d0[44];
-	u32 ths_gate_reset;	/* 0x9fc THS gate/reset control */
-	u8 reserved_0xa00[12];
-	u32 i2s3_clk_cfg;	/* 0xa0c I2S3 clock control */
-	u32 i2s0_clk_cfg;	/* 0xa10 I2S0 clock control */
-	u32 i2s1_clk_cfg;	/* 0xa14 I2S1 clock control */
-	u32 i2s2_clk_cfg;	/* 0xa18 I2S2 clock control */
-	u32 i2s_gate_reset;	/* 0xa1c I2S gate/reset control */
-	u32 spdif_clk_cfg;	/* 0xa20 SPDIF clock control */
-	u8 reserved_0xa24[8];
-	u32 spdif_gate_reset;	/* 0xa2c SPDIF gate/reset control */
-	u8 reserved_0xa30[16];
-	u32 dmic_clk_cfg;	/* 0xa40 DMIC clock control */
-	u8 reserved_0xa44[8];
-	u32 dmic_gate_reset;	/* 0xa4c DMIC gate/reset control */
-	u8 reserved_0xa50[16];
-	u32 ahub_clk_cfg;	/* 0xa60 Audio HUB clock control */
-	u8 reserved_0xa64[8];
-	u32 ahub_gate_reset;	/* 0xa6c Audio HUB gate/reset control */
-	u32 usb0_clk_cfg;	/* 0xa70 USB0(OTG) clock control */
-	u32 usb1_clk_cfg;	/* 0xa74 USB1(XHCI) clock control */
-	u8 reserved_0xa78[4];
-	u32 usb3_clk_cfg;	/* 0xa78 USB3 clock control */
-	u8 reserved_0xa80[12];
-	u32 usb_gate_reset;	/* 0xa8c USB gate/reset control */
-	u8 reserved_0xa90[32];
-	u32 pcie_ref_clk_cfg;	/* 0xab0 PCIE REF clock control */
-	u32 pcie_axi_clk_cfg;	/* 0xab4 PCIE AXI clock control */
-	u32 pcie_aux_clk_cfg;	/* 0xab8 PCIE AUX clock control */
-	u32 pcie_gate_reset;	/* 0xabc PCIE gate/reset control */
-	u8 reserved_0xac0[64];
-	u32 hdmi_clk_cfg;	/* 0xb00 HDMI clock control */
-	u32 hdmi_slow_clk_cfg;	/* 0xb04 HDMI slow clock control */
-	u8 reserved_0xb08[8];
-	u32 hdmi_cec_clk_cfg;	/* 0xb10 HDMI CEC clock control */
-	u8 reserved_0xb14[8];
-	u32 hdmi_gate_reset;	/* 0xb1c HDMI gate/reset control */
-	u8 reserved_0xb20[60];
-	u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
-	u32 tcon_lcd0_clk_cfg;	/* 0xb60 TCON LCD0 clock control */
-	u8 reserved_0xb64[24];
-	u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
-	u32 tcon_tv0_clk_cfg;	/* 0xb80 TCON TV0 clock control */
-	u8 reserved_0xb84[24];
-	u32 tcon_tv_gate_reset;	/* 0xb9c TCON TV gate/reset control */
-	u8 reserved_0xba0[96];
-	u32 csi_misc_clk_cfg;	/* 0xc00 CSI MISC clock control */
-	u32 csi_top_clk_cfg;	/* 0xc04 CSI TOP clock control */
-	u32 csi_mclk_cfg;	/* 0xc08 CSI Master clock control */
-	u8 reserved_0xc0c[32];
-	u32 csi_gate_reset;	/* 0xc2c CSI gate/reset control */
-	u8 reserved_0xc30[16];
-	u32 hdcp_clk_cfg;	/* 0xc40 HDCP clock control */
-	u8 reserved_0xc44[8];
-	u32 hdcp_gate_reset;	/* 0xc4c HDCP gate/reset control */
-	u8 reserved_0xc50[688];
-	u32 ccu_sec_switch;	/* 0xf00 CCU security switch */
-	u32 pll_lock_dbg_ctrl;	/* 0xf04 PLL lock debugging control */
-};
+#define CCU_H6_PLL1_CFG			0x000
+#define CCU_H6_PLL5_CFG			0x010
+#define CCU_H6_PLL6_CFG			0x020
+#define CCU_H6_CPU_AXI_CFG		0x500
+#define CCU_H6_PSI_AHB1_AHB2_CFG	0x510
+#define CCU_H6_AHB3_CFG			0x51c
+#define CCU_H6_APB1_CFG			0x520
+#define CCU_H6_APB2_CFG			0x524
+#define CCU_H6_MBUS_CFG			0x540
+#define CCU_H6_DRAM_CLK_CFG		0x800
+#define CCU_H6_DRAM_GATE_RESET		0x80c
+#define CCU_MMC0_CLK_CFG		0x830
+#define CCU_MMC1_CLK_CFG		0x834
+#define CCU_MMC2_CLK_CFG		0x838
+#define CCU_H6_MMC_GATE_RESET		0x84c
+#define CCU_H6_UART_GATE_RESET		0x90c
+#define CCU_H6_I2C_GATE_RESET		0x91c
 
 /* pll1 bit field */
 #define CCM_PLL1_CTRL_EN		BIT(31)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 7fcf340db69..28c3faccbbc 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -10,6 +10,13 @@
 #ifndef _SUNXI_CLOCK_SUN6I_H
 #define _SUNXI_CLOCK_SUN6I_H
 
+#define CCU_AHB_GATE0		0x060
+#define CCU_MMC0_CLK_CFG	0x088
+#define CCU_MMC1_CLK_CFG	0x08c
+#define CCU_MMC2_CLK_CFG	0x090
+#define CCU_MMC3_CLK_CFG	0x094
+#define CCU_AHB_RESET0_CFG	0x2c0
+
 struct sunxi_ccm_reg {
 	u32 pll1_cfg;		/* 0x00 pll1 control */
 	u32 reserved0;
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
index 35ca0491ac9..5ad2163926a 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -13,6 +13,13 @@
 #ifndef _SUNXI_CLOCK_SUN8I_A83T_H
 #define _SUNXI_CLOCK_SUN8I_A83T_H
 
+#define CCU_AHB_GATE0		0x060
+#define CCU_MMC0_CLK_CFG	0x088
+#define CCU_MMC1_CLK_CFG	0x08c
+#define CCU_MMC2_CLK_CFG	0x090
+#define CCU_MMC3_CLK_CFG	0x094
+#define CCU_AHB_RESET0_CFG	0x2c0
+
 struct sunxi_ccm_reg {
 	u32 pll1_c0_cfg;	/* 0x00 c1cpu# pll control */
 	u32 pll1_c1_cfg;	/* 0x04 c1cpu# pll control */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index 006f7761fc6..8d696e533f8 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -12,6 +12,13 @@
 #include <linux/bitops.h>
 #endif
 
+#define CCU_MMC0_CLK_CFG	0x410
+#define CCU_MMC1_CLK_CFG	0x414
+#define CCU_MMC2_CLK_CFG	0x418
+#define CCU_MMC3_CLK_CFG	0x41c
+#define CCU_AHB_GATE0		0x580
+#define CCU_AHB_RESET0_CFG	0x5a0
+
 struct sunxi_ccm_reg {
 	u32 pll1_c0_cfg;	/* 0x00 c0cpu# pll configuration */
 	u32 pll2_c1_cfg;	/* 0x04 c1cpu# pll configuration */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h
new file mode 100644
index 00000000000..bc9e0d868c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Helpers that are commonly used with DW memory controller.
+ *
+ * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com>
+ *
+ */
+
+#ifndef _DRAM_DW_HELPERS_H
+#define _DRAM_DW_HELPERS_H
+
+#include <asm/arch/dram.h>
+
+bool mctl_core_init(const struct dram_para *para,
+		    const struct dram_config *config);
+void mctl_auto_detect_rank_width(const struct dram_para *para,
+				 struct dram_config *config);
+void mctl_auto_detect_dram_size(const struct dram_para *para,
+				struct dram_config *config);
+unsigned long mctl_calc_size(const struct dram_config *config);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index f0caecc807d..af6cd337d7e 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -315,12 +315,15 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
 struct dram_para {
 	u32 clk;
 	enum sunxi_dram_type type;
+	const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
+	const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
+};
+
+struct dram_config {
 	u8 cols;
 	u8 rows;
 	u8 ranks;
 	u8 bus_full_width;
-	const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
-	const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
 };
 
 static inline int ns_to_t(int nanoseconds)
@@ -330,6 +333,6 @@ static inline int ns_to_t(int nanoseconds)
 	return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
 }
 
-void mctl_set_timing_params(struct dram_para *para);
+void mctl_set_timing_params(void);
 
 #endif /* _SUNXI_DRAM_SUN50I_H6_H */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
index fd63d3aad83..d6653c3bb06 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
@@ -9,46 +9,12 @@
 #define _SUN50I_PRCM_H
 
 #ifndef __ASSEMBLY__
-#include <linux/compiler.h>
 
-struct sunxi_prcm_reg {
-	u32 cpus_cfg;		/* 0x000 */
-	u8 res0[0x8];		/* 0x004 */
-	u32 apbs1_cfg;		/* 0x00c */
-	u32 apbs2_cfg;		/* 0x010 */
-	u8 res1[0x108];		/* 0x014 */
-	u32 tmr_gate_reset;	/* 0x11c */
-	u8 res2[0xc];		/* 0x120 */
-	u32 twd_gate_reset;	/* 0x12c */
-	u8 res3[0xc];		/* 0x130 */
-	u32 pwm_gate_reset;	/* 0x13c */
-	u8 res4[0x4c];		/* 0x140 */
-	u32 uart_gate_reset;	/* 0x18c */
-	u8 res5[0xc];		/* 0x190 */
-	u32 twi_gate_reset;	/* 0x19c */
-	u8 res6[0x1c];		/* 0x1a0 */
-	u32 rsb_gate_reset;	/* 0x1bc */
-	u32 cir_cfg;		/* 0x1c0 */
-	u8 res7[0x8];		/* 0x1c4 */
-	u32 cir_gate_reset;	/* 0x1cc */
-	u8 res8[0x10];		/* 0x1d0 */
-	u32 w1_cfg;		/* 0x1e0 */
-	u8 res9[0x8];		/* 0x1e4 */
-	u32 w1_gate_reset;	/* 0x1ec */
-	u8 res10[0x1c];		/* 0x1f0 */
-	u32 rtc_gate_reset;	/* 0x20c */
-	u8 res11[0x34];		/* 0x210 */
-	u32 pll_ldo_cfg;	/* 0x244 */
-	u8 res12[0x8];		/* 0x248 */
-	u32 sys_pwroff_gating;	/* 0x250 */
-	u8 res13[0xbc];		/* 0x254 */
-	u32 res_cal_ctrl;	/* 0x310 */
-	u32 ohms200;		/* 0x314 */
-	u32 ohms240;		/* 0x318 */
-	u32 res_cal_status;	/* 0x31c */
-};
-check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);
-check_member(sunxi_prcm_reg, res_cal_status, 0x31c);
+#define CCU_PRCM_I2C_GATE_RESET		0x19c
+#define CCU_PRCM_PLL_LDO_CFG		0x244
+#define CCU_PRCM_SYS_PWROFF_GATING	0x250
+#define CCU_PRCM_RES_CAL_CTRL		0x310
+#define CCU_PRCM_OHMS240		0x318
 
 #define PRCM_TWI_GATE		(1 << 0)
 #define PRCM_TWI_RESET		(1 << 16)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 109a806852a..0780f99b49a 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -97,6 +97,8 @@ struct bd_info;
 #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
 #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
 
+#define is_imx95() (is_cpu_type(MXC_CPU_IMX95))
+
 #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
 #define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
 #define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101))
@@ -216,6 +218,43 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
 u32 rom_api_download_image(u8 *dest, u32 offset, u32 size);
 u32 rom_api_query_boot_infor(u32 info_type, u32 *info);
 
+#if IS_ENABLED(CONFIG_SCMI_FIRMWARE)
+typedef struct rom_passover {
+	u16 tag;                   // Tag
+	u8  len;                   // Fixed value of 0x80
+	u8  ver;                   // Version
+	u32 boot_mode;             // Boot mode
+	u32 card_addr_mode;        // SD card address mode
+	u32 bad_blks_of_img_set0;  // NAND bad block count skipped 1
+	u32 ap_mu_id;              // AP MU ID
+	u32 bad_blks_of_img_set1;  // NAND bad block count skipped 1
+	u8  boot_stage;            // Boot stage
+	u8  img_set_sel;           // Image set booted from
+	u8  rsv0[2];               // Reserved
+	u32 img_set_end;           // Offset of Image End
+	u32 rom_version;           // ROM version
+	u8  boot_dev_state;        // Boot device state
+	u8  boot_dev_inst;         // Boot device type
+	u8  boot_dev_type;         // Boot device instance
+	u8  rsv1;                  // Reserved
+	u32 dev_page_size;         // Boot device page size
+	u32 cnt_header_ofs;        // Container header offset
+	u32 img_ofs;               // Image offset
+}  __packed rom_passover_t;
+
+/**
+ * struct scmi_rom_passover_out - Response payload for ROM_PASSOVER_GET command
+ * @status:	SCMI clock ID
+ * @attributes:	Attributes of the targets clock state
+ */
+struct scmi_rom_passover_get_out {
+	u32 status;
+	u32 numPassover;
+	u32 passover[(sizeof(rom_passover_t) + 8) / 4];
+};
+
+#endif
+
 /* For i.MX ULP */
 #define BT0CFG_LPBOOT_MASK	0x1
 #define BT0CFG_DUALBOOT_MASK	0x2