diff options
Diffstat (limited to 'arch/arm/include')
19 files changed, 1057 insertions, 260 deletions
diff --git a/arch/arm/include/asm/arch-apple/rtkit.h b/arch/arm/include/asm/arch-apple/rtkit.h index eff18ddb9d2..4b11e2a72dc 100644 --- a/arch/arm/include/asm/arch-apple/rtkit.h +++ b/arch/arm/include/asm/arch-apple/rtkit.h @@ -12,6 +12,7 @@ struct apple_rtkit_buffer { u64 dva; size_t size; bool is_mapped; + int endpoint; }; typedef int (*apple_rtkit_shmem_setup)(void *cookie, @@ -26,4 +27,8 @@ struct apple_rtkit *apple_rtkit_init(struct mbox_chan *chan, void *cookie, apple_rtkit_shmem_destroy shmem_destroy); void apple_rtkit_free(struct apple_rtkit *rtk); int apple_rtkit_boot(struct apple_rtkit *rtk); +int apple_rtkit_set_ap_power(struct apple_rtkit *rtk, int pwrstate); +int apple_rtkit_poll(struct apple_rtkit *rtk, ulong timeout); int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate); + +int apple_rtkit_helper_poll(struct udevice *dev, ulong timeout); diff --git a/arch/arm/include/asm/arch-rk3528/boot0.h b/arch/arm/include/asm/arch-rk3528/boot0.h new file mode 100644 index 00000000000..8ae46f25a87 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3528/boot0.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3528/gpio.h b/arch/arm/include/asm/arch-rk3528/gpio.h new file mode 100644 index 00000000000..5516e649b80 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3528/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3576/boot0.h b/arch/arm/include/asm/arch-rk3576/boot0.h new file mode 100644 index 00000000000..dea2b20252d --- /dev/null +++ b/arch/arm/include/asm/arch-rk3576/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3576/gpio.h b/arch/arm/include/asm/arch-rk3576/gpio.h new file mode 100644 index 00000000000..b48c0a5cf84 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3576/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 73e5283108b..3c204501f70 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -15,6 +15,13 @@ struct udevice; #define RKCLK_PLL_MODE_NORMAL 1 #define RKCLK_PLL_MODE_DEEP 2 +/* + * PLL flags + */ +#define ROCKCHIP_PLL_SYNC_RATE BIT(0) +/* normal mode only. now only for pll_rk3036, pll_rk3328 type */ +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) + enum { ROCKCHIP_SYSCON_NOC, ROCKCHIP_SYSCON_GRF, @@ -208,6 +215,26 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table, u32 reg_offset, u32 reg_number); /* + * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device + * using dedicated RK3528 lookup table + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * Return: 0 success, or error value + */ +int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number); +/* + * rk3576_reset_bind_lut() - Bind soft reset device as child of clock device + * using dedicated RK3576 lookup table + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * Return: 0 success, or error value + */ +int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number); +/* * rk3588_reset_bind_lut() - Bind soft reset device as child of clock device * using dedicated RK3588 lookup table * diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3528.h b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h new file mode 100644 index 00000000000..b4020958a04 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h @@ -0,0 +1,388 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _ASM_ARCH_CRU_RK3528_H +#define _ASM_ARCH_CRU_RK3528_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define CPU_PVTPLL_HZ (1200 * MHz) +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (996 * MHz) +#define PPLL_HZ (1000 * MHz) + +/* RK3528 pll id */ +enum rk3528_pll_id { + APLL, + CPLL, + GPLL, + PPLL, + DPLL, + PLL_COUNT, +}; + +struct rk3528_clk_priv { + struct rk3528_cru *cru; + unsigned long ppll_hz; + unsigned long gpll_hz; + unsigned long cpll_hz; + unsigned long armclk_hz; + unsigned long armclk_enter_hz; + unsigned long armclk_init_hz; + bool sync_kernel; +}; + +struct rk3528_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +#define RK3528_CRU_BASE ((struct rk3528_cru *)0xff4a0000) + +struct rk3528_cru { + unsigned int apll_con[5]; + unsigned int reserved0014[3]; + unsigned int cpll_con[5]; + unsigned int reserved0034[11]; + unsigned int gpll_con[5]; + unsigned int reserved0074[51 + 32]; + unsigned int reserved01c0[48]; + unsigned int mode_con[1]; + unsigned int reserved0284[31]; + unsigned int clksel_con[91]; + unsigned int reserved046c[229]; + unsigned int gate_con[46]; + unsigned int reserved08b8[82]; + unsigned int softrst_con[47]; + unsigned int reserved0abc[81]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int reserved0c14[6]; + unsigned int corewfi_con; + unsigned int reserved0c30[15604]; + + /* pmucru */ + unsigned int reserved10000[192]; + unsigned int pmuclksel_con[3]; + unsigned int reserved1030c[317]; + unsigned int pmugate_con[3]; + unsigned int reserved1080c[125]; + unsigned int pmusoftrst_con[3]; + unsigned int reserved10a08[7550 + 8191]; + + /* pciecru */ + unsigned int reserved20000[32]; + unsigned int ppll_con[5]; + unsigned int reserved20094[155]; + unsigned int pcieclksel_con[2]; + unsigned int reserved20308[318]; + unsigned int pciegate_con; +}; + +check_member(rk3528_cru, pciegate_con, 0x20800); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +#define RK3528_PMU_CRU_BASE 0x10000 +#define RK3528_PCIE_CRU_BASE 0x20000 +#define RK3528_DDRPHY_CRU_BASE 0x28000 +#define RK3528_PLL_CON(x) ((x) * 0x4) +#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_MODE_CON 0x280 +#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) +#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) + +#define RK3528_DIV_ACLK_M_CORE_SHIFT 11 +#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT) +#define RK3528_DIV_PCLK_DBG_SHIFT 1 +#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT) + +enum { + /* CRU_CLKSEL_CON00 */ + CLK_MATRIX_50M_SRC_DIV_SHIFT = 2, + CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT, + CLK_MATRIX_100M_SRC_DIV_SHIFT = 7, + CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON01 */ + CLK_MATRIX_150M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT, + CLK_MATRIX_200M_SRC_DIV_SHIFT = 5, + CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_SEL_SHIFT = 15, + CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT, + + /* CRU_CLKSEL_CON02 */ + CLK_MATRIX_300M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT, + CLK_MATRIX_339M_SRC_DIV_SHIFT = 5, + CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT, + CLK_MATRIX_400M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON03 */ + CLK_MATRIX_500M_SRC_DIV_SHIFT = 6, + CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT, + CLK_MATRIX_500M_SRC_SEL_SHIFT = 11, + CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT, + + /* CRU_CLKSEL_CON04 */ + CLK_MATRIX_600M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U, + CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U, + CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U, + CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U, + + /* PMUCRU_CLKSEL_CON00 */ + CLK_I2C2_SEL_SHIFT = 0, + CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, + + /* PCIE_CRU_CLKSEL_CON01 */ + PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7, + PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT, + PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11, + PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON32 */ + DCLK_VOP_SRC0_SEL_SHIFT = 10, + DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT, + DCLK_VOP_SRC0_DIV_SHIFT = 2, + DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT, + + /* CRU_CLKSEL_CON33 */ + DCLK_VOP_SRC1_SEL_SHIFT = 8, + DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT, + DCLK_VOP_SRC1_DIV_SHIFT = 0, + DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT, + + /* CRU_CLKSEL_CON43 */ + CLK_CORE_CRYPTO_SEL_SHIFT = 14, + CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, + ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U, + ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT, + + /* CRU_CLKSEL_CON44 */ + CLK_PWM0_SEL_SHIFT = 6, + CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT, + CLK_PWM1_SEL_SHIFT = 8, + CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, + CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U, + CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U, + CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U, + CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U, + CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U, + CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U, + CLK_PKA_CRYPTO_SEL_SHIFT = 0, + CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, + CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, + CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, + + /* CRU_CLKSEL_CON60 */ + CLK_MATRIX_25M_SRC_DIV_SHIFT = 2, + CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT, + CLK_MATRIX_125M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON61 */ + SCLK_SFC_DIV_SHIFT = 6, + SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT, + SCLK_SFC_SEL_SHIFT = 12, + SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT, + SCLK_SFC_SEL_CLK_GPLL_MUX = 0U, + SCLK_SFC_SEL_CLK_CPLL_MUX = 1U, + SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON62 */ + CCLK_SRC_EMMC_DIV_SHIFT = 0, + CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT, + CCLK_SRC_EMMC_SEL_SHIFT = 6, + CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT, + BCLK_EMMC_SEL_SHIFT = 8, + BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT, + + /* CRU_CLKSEL_CON63 */ + CLK_I2C3_SEL_SHIFT = 12, + CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT, + CLK_I2C5_SEL_SHIFT = 14, + CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT, + CLK_SPI1_SEL_SHIFT = 10, + CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, + + /* CRU_CLKSEL_CON64 */ + CLK_I2C6_SEL_SHIFT = 0, + CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT, + + /* CRU_CLKSEL_CON74 */ + CLK_SARADC_DIV_SHIFT = 0, + CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, + CLK_TSADC_DIV_SHIFT = 3, + CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT, + CLK_TSADC_TSEN_DIV_SHIFT = 8, + CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT, + + /* CRU_CLKSEL_CON79 */ + CLK_I2C1_SEL_SHIFT = 9, + CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, + CLK_I2C0_SEL_SHIFT = 11, + CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, + CLK_SPI0_SEL_SHIFT = 13, + CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, + + /* CRU_CLKSEL_CON83 */ + ACLK_VOP_ROOT_DIV_SHIFT = 12, + ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT, + ACLK_VOP_ROOT_SEL_SHIFT = 15, + ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT, + + /* CRU_CLKSEL_CON84 */ + DCLK_VOP0_SEL_SHIFT = 0, + DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT, + DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U, + DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U, + ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U, + ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U, + DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U, + DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U, + + /* CRU_CLKSEL_CON85 */ + CLK_I2C4_SEL_SHIFT = 13, + CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT, + CLK_I2C7_SEL_SHIFT = 0, + CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT, + CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U, + CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U, + CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U, + CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U, + CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U, + CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U, + CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U, + CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U, + CCLK_SRC_SDMMC0_DIV_SHIFT = 0, + CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT, + CCLK_SRC_SDMMC0_SEL_SHIFT = 6, + CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT, + CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U, + CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U, + CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U, + BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U, + BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U, + BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U, + BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U, + CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U, + CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U, + CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON04 */ + CLK_UART0_SRC_DIV_SHIFT = 5, + CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON05 */ + CLK_UART0_FRAC_DIV_SHIFT = 0, + CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON06 */ + SCLK_UART0_SRC_SEL_SHIFT = 0, + SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT, + CLK_UART1_SRC_DIV_SHIFT = 2, + CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON07 */ + CLK_UART1_FRAC_DIV_SHIFT = 0, + CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON08 */ + SCLK_UART1_SRC_SEL_SHIFT = 0, + SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT, + CLK_UART2_SRC_DIV_SHIFT = 2, + CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON09 */ + CLK_UART2_FRAC_DIV_SHIFT = 0, + CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON10 */ + SCLK_UART2_SRC_SEL_SHIFT = 0, + SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT, + CLK_UART3_SRC_DIV_SHIFT = 2, + CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON11 */ + CLK_UART3_FRAC_DIV_SHIFT = 0, + CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON12 */ + SCLK_UART3_SRC_SEL_SHIFT = 0, + SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT, + CLK_UART4_SRC_DIV_SHIFT = 2, + CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON13 */ + CLK_UART4_FRAC_DIV_SHIFT = 0, + CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON14 */ + SCLK_UART4_SRC_SEL_SHIFT = 0, + SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT, + CLK_UART5_SRC_DIV_SHIFT = 2, + CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON15 */ + CLK_UART5_FRAC_DIV_SHIFT = 0, + CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON16 */ + SCLK_UART5_SRC_SEL_SHIFT = 0, + SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT, + CLK_UART6_SRC_DIV_SHIFT = 2, + CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON17 */ + CLK_UART6_FRAC_DIV_SHIFT = 0, + CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON18 */ + SCLK_UART6_SRC_SEL_SHIFT = 0, + SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT, + CLK_UART7_SRC_DIV_SHIFT = 2, + CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON19 */ + CLK_UART7_FRAC_DIV_SHIFT = 0, + CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON20 */ + SCLK_UART7_SRC_SEL_SHIFT = 0, + SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT, + SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U, + SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U, + SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON60 */ + CLK_GMAC1_VPU_25M_DIV_SHIFT = 2, + CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT, + /* CRU_CLKSEL_CON66 */ + CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0, + CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT, + /* CRU_CLKSEL_CON84 */ + CLK_GMAC0_SRC_DIV_SHIFT = 3, + CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT, +}; + +#endif /* _ASM_ARCH_CRU_RK3528_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h new file mode 100644 index 00000000000..c51750beff2 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h @@ -0,0 +1,491 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#ifndef _ASM_ARCH_CRU_RK3576_H +#define _ASM_ARCH_CRU_RK3576_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define CPU_PVTPLL_HZ (1008 * MHz) +#define LPLL_HZ (816 * MHz) +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (1000 * MHz) +#define PPLL_HZ (1100 * MHz) +#define GMAC0_PTP_REFCLK_IN (24 * MHz) +#define GMAC1_PTP_REFCLK_IN (24 * MHz) + +/* RK3576 pll id */ +enum rk3576_pll_id { + BPLL, + LPLL, + DPLL, + CPLL, + GPLL, + VPLL, + AUPLL, + SPLL, + PPLL, + PLL_COUNT, +}; + +struct rk3576_clk_priv { + struct rk3576_cru *cru; + ulong ppll_hz; + ulong gpll_hz; + ulong cpll_hz; + ulong vpll_hz; + ulong aupll_hz; + ulong spll_hz; + ulong lpll_hz; + ulong bpll_hz; + ulong armclk_hz; + ulong armclk_enter_hz; + ulong armclk_init_hz; + bool sync_kernel; + bool set_armclk_rate; +}; + +struct rk3576_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +struct rk3576_cru { + struct rk3576_pll pll[18]; + unsigned int reserved0[16];/* Address Offset: 0x0240 */ + unsigned int mode_con00;/* Address Offset: 0x0280 */ + unsigned int reserved1[31];/* Address Offset: 0x0284 */ + unsigned int clksel_con[181]; /* Address Offset: 0x0300 */ + unsigned int reserved2[139];/* Address Offset: 0x05d4 */ + unsigned int clkgate_con[80];/* Address Offset: 0x0800 */ + unsigned int reserved3[48];/* Address Offset: 0x0938 */ + unsigned int softrst_con[80];/* Address Offset: 0x0400 */ + unsigned int reserved4[48];/* Address Offset: 0x0b38 */ + unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */ + unsigned int glb_rst_st;/* Address Offset: 0x0c04 */ + unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */ + unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */ + unsigned int glb_rst_con;/* Address Offset: 0x0c10 */ + unsigned int reserved5[43];/* Address Offset: 0x0c14 */ + unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */ + unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */ + unsigned int reserved8[32137];/* Address Offset: 0x0c38 */ + unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */ + unsigned int reserved9[298];/* Address Offset: 0x20358 */ + unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */ + unsigned int reserved10[32440];/* Address Offset: 0x20820 */ + unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */ +}; + +check_member(rk3576_cru, mode_con00, 0x280); +check_member(rk3576_cru, pmuclksel_con[1], 0x20304); + +struct pll_rate_table { + unsigned long rate; + unsigned int m; + unsigned int p; + unsigned int s; + unsigned int k; +}; + +#define RK3576_PHP_CRU_BASE 0x8000 +#define RK3576_PMU_CRU_BASE 0x20000 +#define RK3576_BIGCORE_CRU_BASE 0x38000 +#define RK3576_LITCORE_CRU_BASE 0x40000 +#define RK3576_CCI_CRU_BASE 0x48000 +#define RK3576_CRU_BASE 0x27200000 +#define RK3576_SCRU_BASE 0x27214000 + +#define RK3576_BIGCORE_GRF_BASE 0x2600C000 +#define RK3576_LITCORE_GRF_BASE 0x2600E000 +#define RK3576_CCI_GRF_BASE 0x26010000 + +#define RK3576_PLL_CON(x) ((x) * 0x4) +#define RK3576_MODE_CON0 0x280 +#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) +#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) +#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) +#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3576_GLB_CNT_TH 0xc00 +#define RK3576_GLB_SRST_FST 0xc08 +#define RK3576_GLB_SRST_SND 0xc0c +#define RK3576_GLB_RST_CON 0xc10 +#define RK3576_GLB_RST_ST 0xc04 +#define RK3576_SDIO_CON0 0xC24 +#define RK3576_SDIO_CON1 0xC28 +#define RK3576_SDMMC_CON0 0xC30 +#define RK3576_SDMMC_CON1 0xC34 + +#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) +#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) +#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) + +#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) +#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) +#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) +#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) + +#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) +#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) +#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) + +#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) +#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) +#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) +#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) +#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) +#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) +#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) +#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) + +enum { + /* CRU_CLK_SEL8_CON */ + PCLK_TOP_SEL_SHIFT = 7, + PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, + PCLK_TOP_SEL_100M = 0, + PCLK_TOP_SEL_50M, + PCLK_TOP_SEL_OSC, + + /* CRU_CLK_SEL9_CON */ + ACLK_TOP_SEL_SHIFT = 5, + ACLK_TOP_SEL_MASK = 3 << ACLK_TOP_SEL_SHIFT, + ACLK_TOP_SEL_GPLL = 0, + ACLK_TOP_SEL_CPLL, + ACLK_TOP_SEL_AUPLL, + ACLK_TOP_DIV_SHIFT = 0, + ACLK_TOP_DIV_MASK = 0x1f << ACLK_TOP_DIV_SHIFT, + + /* CRU_CLK_SEL10_CON */ + ACLK_TOP_MID_SEL_SHIFT = 5, + ACLK_TOP_MID_SEL_MASK = 1 << ACLK_TOP_MID_SEL_SHIFT, + ACLK_TOP_MID_SEL_GPLL = 0, + ACLK_TOP_MID_SEL_CPLL, + ACLK_TOP_MID_DIV_SHIFT = 0, + ACLK_TOP_MID_DIV_MASK = 0x1f << ACLK_TOP_MID_DIV_SHIFT, + + /* CRU_CLK_SEL19_CON */ + HCLK_TOP_SEL_SHIFT = 2, + HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, + HCLK_TOP_SEL_200M = 0, + HCLK_TOP_SEL_100M, + HCLK_TOP_SEL_50M, + HCLK_TOP_SEL_OSC, + + /* CRU_CLK_SEL25_CON */ + CLK_UART_FRAC_NUMERATOR_SHIFT = 16, + CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, + CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_CLK_SEL26_CON */ + CLK_UART_SRC_SEL_SHIFT = 0, + CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT, + CLK_UART_SRC_SEL_GPLL = 0, + CLK_UART_SRC_SEL_CPLL, + CLK_UART_SRC_SEL_AUPLL, + CLK_UART_SRC_SEL_OSC, + + /* CRU_CLK_SEL27_CON */ + CLK_UART1_SRC_SEL_SHIFT = 13, + CLK_UART1_SRC_SEL_MASK = 0x7 << CLK_UART1_SRC_SEL_SHIFT, + CLK_UART1_SRC_DIV_SHIFT = 5, + CLK_UART1_SRC_DIV_MASK = 0xff << CLK_UART1_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL30_CON */ + CLK_GMAC0_125M_DIV_SHIFT = 10, + CLK_GMAC0_125M_DIV_MASK = 0x1f << CLK_GMAC0_125M_DIV_SHIFT, + + /* CRU_CLK_SEL31_CON */ + CLK_GMAC1_125M_DIV_SHIFT = 0, + CLK_GMAC1_125M_DIV_MASK = 0x1f << CLK_GMAC1_125M_DIV_SHIFT, + + /* CRU_CLK_SEL33_CON */ + REF_CLK0_OUT_PLL_SEL_SHIFT = 8, + REF_CLK0_OUT_PLL_SEL_MASK = 7 << REF_CLK0_OUT_PLL_SEL_SHIFT, + REF_CLK0_OUT_PLL_SEL_GPLL = 0, + REF_CLK0_OUT_PLL_SEL_CPLL, + REF_CLK0_OUT_PLL_SEL_SPLL, + REF_CLK0_OUT_PLL_SEL_AUPLL, + REF_CLK0_OUT_PLL_SEL_LPLL, + REF_CLK0_OUT_PLL_SEL_OSC, + REF_CLK0_OUT_PLL_DIV_SHIFT = 0, + REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT, + + /* CRU_CLK_SEL55_CON */ + ACLK_BUS_ROOT_SEL_SHIFT = 9, + ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT, + ACLK_BUS_ROOT_SEL_GPLL = 0, + ACLK_BUS_ROOT_SEL_CPLL, + ACLK_BUS_ROOT_DIV_SHIFT = 4, + ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT, + PCLK_BUS_ROOT_SEL_SHIFT = 2, + PCLK_BUS_ROOT_SEL_MASK = 3 << PCLK_BUS_ROOT_SEL_SHIFT, + PCLK_BUS_ROOT_SEL_100M = 0, + PCLK_BUS_ROOT_SEL_50M, + PCLK_BUS_ROOT_SEL_OSC, + HCLK_BUS_ROOT_SEL_SHIFT = 0, + HCLK_BUS_ROOT_SEL_MASK = 3 << HCLK_BUS_ROOT_SEL_SHIFT, + HCLK_BUS_ROOT_SEL_200M = 0, + HCLK_BUS_ROOT_SEL_100M, + HCLK_BUS_ROOT_SEL_50M, + HCLK_BUS_ROOT_SEL_OSC, + + /* CRU_CLK_SEL57_CON */ + CLK_I2C8_SEL_SHIFT = 14, + CLK_I2C8_SEL_MASK = 3 << CLK_I2C8_SEL_SHIFT, + CLK_I2C7_SEL_SHIFT = 12, + CLK_I2C7_SEL_MASK = 3 << CLK_I2C7_SEL_SHIFT, + CLK_I2C6_SEL_SHIFT = 10, + CLK_I2C6_SEL_MASK = 3 << CLK_I2C6_SEL_SHIFT, + CLK_I2C5_SEL_SHIFT = 8, + CLK_I2C5_SEL_MASK = 3 << CLK_I2C5_SEL_SHIFT, + CLK_I2C4_SEL_SHIFT = 6, + CLK_I2C4_SEL_MASK = 3 << CLK_I2C4_SEL_SHIFT, + CLK_I2C3_SEL_SHIFT = 4, + CLK_I2C3_SEL_MASK = 3 << CLK_I2C3_SEL_SHIFT, + CLK_I2C2_SEL_SHIFT = 2, + CLK_I2C2_SEL_MASK = 3 << CLK_I2C2_SEL_SHIFT, + CLK_I2C1_SEL_SHIFT = 0, + CLK_I2C1_SEL_MASK = 3 << CLK_I2C1_SEL_SHIFT, + CLK_I2C_SEL_200M = 0, + CLK_I2C_SEL_100M, + CLK_I2C_SEL_50M, + CLK_I2C_SEL_OSC, + + /* CRU_CLK_SEL58_CON */ + CLK_SARADC_SEL_SHIFT = 12, + CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT, + CLK_SARADC_SEL_GPLL = 0, + CLK_SARADC_SEL_OSC, + CLK_SARADC_DIV_SHIFT = 4, + CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT, + CLK_I2C9_SEL_SHIFT = 0, + CLK_I2C9_SEL_MASK = 3 << CLK_I2C9_SEL_SHIFT, + + /* CRU_CLK_SEL59_CON */ + CLK_TSADC_DIV_SHIFT = 0, + CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT, + + /* CRU_CLK_SEL60_CON */ + CLK_UART_SEL_SHIFT = 8, + CLK_UART_SEL_MASK = 7 << CLK_UART_SEL_SHIFT, + CLK_UART_SEL_GPLL = 0, + CLK_UART_SEL_CPLL, + CLK_UART_SEL_AUPLL, + CLK_UART_SEL_OSC, + CLK_UART_SEL_FRAC0, + CLK_UART_SEL_FRAC1, + CLK_UART_SEL_FRAC2, + CLK_UART_DIV_SHIFT = 0, + CLK_UART_DIV_MASK = 0xff << CLK_UART_DIV_SHIFT, + + /* CRU_CLK_SEL70_CON */ + CLK_SPI0_SEL_SHIFT = 13, + CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, + CLK_SPI_SEL_200M = 0, + CLK_SPI_SEL_100M, + CLK_SPI_SEL_50M, + CLK_SPI_SEL_OSC, + + /* CRU_CLK_SEL71_CON */ + CLK_PWM1_SEL_SHIFT = 8, + CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, + CLK_SPI4_SEL_SHIFT = 6, + CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT, + CLK_SPI3_SEL_SHIFT = 4, + CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, + CLK_SPI2_SEL_SHIFT = 2, + CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, + CLK_SPI1_SEL_SHIFT = 0, + CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, + CLK_PWM_SEL_100M = 0, + CLK_PWM_SEL_50M, + CLK_PWM_SEL_OSC, + + /* CRU_CLK_SEL72_CON */ + DCLK_DECOM_SEL_SHIFT = 5, + DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, + DCLK_DECOM_SEL_GPLL = 0, + DCLK_DECOM_SEL_SPLL, + DCLK_DECOM_DIV_SHIFT = 0, + DCLK_DECOM_DIV_MASK = 0x1f << DCLK_DECOM_DIV_SHIFT, + + /* CRU_CLK_SEL74_CON */ + CLK_PWM2_SEL_SHIFT = 6, + CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, + + /* CRU_CLK_SEL89_CON */ + CCLK_EMMC_SEL_SHIFT = 14, + CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT, + CCLK_EMMC_SEL_GPLL = 0, + CCLK_EMMC_SEL_CPLL, + CCLK_EMMC_SEL_OSC, + CCLK_EMMC_DIV_SHIFT = 8, + CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT, + SCLK_FSPI_SEL_SHIFT = 6, + SCLK_FSPI_SEL_MASK = 3 << SCLK_FSPI_SEL_SHIFT, + SCLK_FSPI_SEL_GPLL = 0, + SCLK_FSPI_SEL_CPLL, + SCLK_FSPI_SEL_OSC, + SCLK_FSPI_DIV_SHIFT = 0, + SCLK_FSPI_DIV_MASK = 0x3f << SCLK_FSPI_DIV_SHIFT, + + /* CRU_CLK_SEL90_CON */ + BCLK_EMMC_SEL_SHIFT = 0, + BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, + BCLK_EMMC_SEL_200M = 0, + BCLK_EMMC_SEL_100M, + BCLK_EMMC_SEL_50M, + BCLK_EMMC_SEL_OSC, + + /* CRU_CLK_SEL104_CON */ + CLK_GMAC1_PTP_SEL_SHIFT = 13, + CLK_GMAC1_PTP_SEL_MASK = 3 << CLK_GMAC1_PTP_SEL_SHIFT, + CLK_GMAC1_PTP_SEL_GPLL = 0, + CLK_GMAC1_PTP_SEL_CPLL, + CLK_GMAC1_PTP_SEL_REFIN, + CLK_GMAC1_PTP_DIV_SHIFT = 8, + CLK_GMAC1_PTP_DIV_MASK = 0x1f << CLK_GMAC1_PTP_DIV_SHIFT, + CCLK_SDIO_SRC_SEL_SHIFT = 6, + CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT, + CCLK_SDIO_SRC_SEL_GPLL = 0, + CCLK_SDIO_SRC_SEL_CPLL, + CCLK_SDIO_SRC_SEL_OSC, + CCLK_SDIO_SRC_DIV_SHIFT = 0, + CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL105_CON */ + CCLK_SDMMC0_SRC_SEL_SHIFT = 13, + CCLK_SDMMC0_SRC_SEL_MASK = 3 << CCLK_SDMMC0_SRC_SEL_SHIFT, + CCLK_SDMMC0_SRC_SEL_GPLL = 0, + CCLK_SDMMC0_SRC_SEL_CPLL, + CCLK_SDMMC0_SRC_SEL_OSC, + CCLK_SDMMC0_SRC_DIV_SHIFT = 7, + CCLK_SDMMC0_SRC_DIV_MASK = 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT, + CLK_GMAC0_PTP_SEL_SHIFT = 5, + CLK_GMAC0_PTP_SEL_MASK = 3 << CLK_GMAC0_PTP_SEL_SHIFT, + CLK_GMAC0_PTP_SEL_GPLL = 0, + CLK_GMAC0_PTP_SEL_CPLL, + CLK_GMAC0_PTP_SEL_REFIN, + CLK_GMAC0_PTP_DIV_SHIFT = 0, + CLK_GMAC0_PTP_DIV_MASK = 0x1f << CLK_GMAC0_PTP_DIV_SHIFT, + + /* CRU_CLK_SEL123_CON */ + DCLK_EBC_SEL_SHIFT = 12, + DCLK_EBC_SEL_MASK = 7 << DCLK_EBC_SEL_SHIFT, + DCLK_EBC_SEL_GPLL = 0, + DCLK_EBC_SEL_CPLL, + DCLK_EBC_SEL_VPLL, + DCLK_EBC_SEL_AUPLL, + DCLK_EBC_SEL_LPLL, + DCLK_EBC_SEL_FRAC_SRC, + DCLK_EBC_SEL_OSC, + DCLK_EBC_DIV_SHIFT = 3, + DCLK_EBC_DIV_MASK = 0x1ff << DCLK_EBC_DIV_SHIFT, + DCLK_EBC_FRAC_SRC_SEL_SHIFT = 0, + DCLK_EBC_FRAC_SRC_SEL_MASK = 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT, + DCLK_EBC_FRAC_SRC_SEL_GPLL = 0, + DCLK_EBC_FRAC_SRC_SEL_CPLL, + DCLK_EBC_FRAC_SRC_SEL_VPLL, + DCLK_EBC_FRAC_SRC_SEL_AUPLL, + DCLK_EBC_FRAC_SRC_SEL_OSC, + + /* CRU_CLK_SEL144_CON */ + PCLK_VOP_ROOT_SEL_SHIFT = 12, + PCLK_VOP_ROOT_SEL_MASK = 3 << PCLK_VOP_ROOT_SEL_SHIFT, + PCLK_VOP_ROOT_SEL_100M = 0, + PCLK_VOP_ROOT_SEL_50M, + PCLK_VOP_ROOT_SEL_OSC, + HCLK_VOP_ROOT_SEL_SHIFT = 10, + HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT, + HCLK_VOP_ROOT_SEL_200M = 0, + HCLK_VOP_ROOT_SEL_100M, + HCLK_VOP_ROOT_SEL_50M, + HCLK_VOP_ROOT_SEL_OSC, + ACLK_VOP_ROOT_SEL_SHIFT = 5, + ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT, + ACLK_VOP_ROOT_SEL_GPLL = 0, + ACLK_VOP_ROOT_SEL_CPLL, + ACLK_VOP_ROOT_SEL_AUPLL, + ACLK_VOP_ROOT_SEL_SPLL, + ACLK_VOP_ROOT_SEL_LPLL, + ACLK_VOP_ROOT_DIV_SHIFT = 0, + ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT, + + /* CRU_CLK_SEL145_CON */ + DCLK0_VOP_SRC_SEL_SHIFT = 8, + DCLK0_VOP_SRC_SEL_MASK = 7 << DCLK0_VOP_SRC_SEL_SHIFT, + DCLK_VOP_SRC_SEL_GPLL = 0, + DCLK_VOP_SRC_SEL_CPLL, + DCLK_VOP_SRC_SEL_VPLL, + DCLK_VOP_SRC_SEL_BPLL, + DCLK_VOP_SRC_SEL_LPLL, + DCLK0_VOP_SRC_DIV_SHIFT = 0, + DCLK0_VOP_SRC_DIV_MASK = 0xff << DCLK0_VOP_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL147_CON */ + DCLK2_VOP_SEL_SHIFT = 13, + DCLK2_VOP_SEL_MASK = 1 << DCLK2_VOP_SEL_SHIFT, + DCLK1_VOP_SEL_SHIFT = 12, + DCLK1_VOP_SEL_MASK = 1 << DCLK1_VOP_SEL_SHIFT, + DCLK0_VOP_SEL_SHIFT = 11, + DCLK0_VOP_SEL_MASK = 1 << DCLK0_VOP_SEL_SHIFT, + + /* CRU_CLK_SEL149_CON */ + ACLK_VO0_ROOT_SEL_SHIFT = 5, + ACLK_VO0_ROOT_SEL_MASK = 3 << ACLK_VO0_ROOT_SEL_SHIFT, + ACLK_VO0_ROOT_SEL_GPLL = 0, + ACLK_VO0_ROOT_SEL_CPLL, + ACLK_VO0_ROOT_SEL_LPLL, + ACLK_VO0_ROOT_SEL_BPLL, + ACLK_VO0_ROOT_DIV_SHIFT = 0, + ACLK_VO0_ROOT_DIV_MASK = 0x1f << ACLK_VO0_ROOT_DIV_SHIFT, + + /* CRU_CLK_SEL151_CON */ + CLK_DSIHOST0_SEL_SHIFT = 7, + CLK_DSIHOST0_SEL_MASK = 7 << CLK_DSIHOST0_SEL_SHIFT, + CLK_DSIHOST0_SEL_GPLL = 0, + CLK_DSIHOST0_SEL_CPLL, + CLK_DSIHOST0_SEL_SPLL, + CLK_DSIHOST0_SEL_VPLL, + CLK_DSIHOST0_SEL_BPLL, + CLK_DSIHOST0_SEL_LPLL, + CLK_DSIHOST0_DIV_SHIFT = 0, + CLK_DSIHOST0_DIV_MASK = 0x7f << CLK_DSIHOST0_DIV_SHIFT, + + /* PMUCRU_CLK_SEL5_CON */ + CLK_PMU1PWM_SEL_SHIFT = 2, + CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT, + + /* PMUCRU_CLK_SEL6_CON */ + CLK_I2C0_SEL_SHIFT = 7, + CLK_I2C0_SEL_MASK = 3 << CLK_I2C0_SEL_SHIFT, + + /* PMUCRU_CLK_SEL8_CON */ + CLK_UART1_SEL_SHIFT = 0, + CLK_UART1_SEL_MASK = 1 << CLK_UART1_SEL_SHIFT, + CLK_UART1_SEL_TOP = 0, + CLK_UART1_SEL_OSC, + + /* LITCRU_CLK_SEL0_CON */ + CLK_LITCORE_SEL_SHIFT = 12, + CLK_LITCORE_SEL_MASK = 3 << CLK_LITCORE_SEL_SHIFT, + CLK_LITCORE_SEL_LPLL = 0, + CLK_LITCORE_SEL_GPLL, + CLK_LITCORE_SEL_PVTPLL, + CLK_LITCORE_DIV_SHIFT = 7, + CLK_LITCORE_DIV_MASK = 0x1f << CLK_LITCORE_DIV_SHIFT, + +}; +#endif diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index 24c81391d58..d79aea97a40 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -26,11 +26,21 @@ .word 0xe580e004 // str lr, [r0, #4] .word 0xe10fe000 // mrs lr, CPSR .word 0xe580e008 // str lr, [r0, #8] + .word 0xe101e300 // mrs lr, SP_irq + .word 0xe580e014 // str lr, [r0, #20] .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0} .word 0xe580e00c // str lr, [r0, #12] .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} .word 0xe580e010 // str lr, [r0, #16] - +#ifdef CONFIG_MACH_SUN55I_A523 + .word 0xee1cefbc // mrc 15, 0, lr, cr12, cr12, {5} + .word 0xe31e0001 // tst lr, #1 + .word 0x0a000003 // beq cc <start32+0x48> + .word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0} + .word 0xe580e018 // str lr, [r0, #24] + .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7} + .word 0xe580e01c // str lr, [r0, #28] +#endif .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE .word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 2cec91cb20e..00bdd5f938d 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -10,6 +10,12 @@ #ifndef _SUNXI_CLOCK_SUN4I_H #define _SUNXI_CLOCK_SUN4I_H +#define CCU_AHB_GATE0 0x60 +#define CCU_MMC0_CLK_CFG 0x88 +#define CCU_MMC1_CLK_CFG 0x8c +#define CCU_MMC2_CLK_CFG 0x90 +#define CCU_MMC3_CLK_CFG 0x94 + struct sunxi_ccm_reg { u32 pll1_cfg; /* 0x00 pll1 control */ u32 pll1_tun; /* 0x04 pll1 tuning */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 76dd33c9477..ccacc99d018 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -13,218 +13,23 @@ #include <linux/bitops.h> #endif -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ - u8 reserved_0x004[12]; - u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ - u8 reserved_0x014[12]; - u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ - u8 reserved_0x020[4]; - u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ - u8 reserved_0x028[4]; - u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ - u8 reserved_0x034[12]; - u32 pll3_cfg; /* 0x040 pll3 (video0) control */ - u8 reserved_0x044[4]; - u32 pll_video1_cfg; /* 0x048 pll video1 control */ - u8 reserved_0x04c[12]; - u32 pll4_cfg; /* 0x058 pll4 (ve) control */ - u8 reserved_0x05c[4]; - u32 pll10_cfg; /* 0x060 pll10 (de) control */ - u8 reserved_0x064[12]; - u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ - u8 reserved_0x074[4]; - u32 pll2_cfg; /* 0x078 pll2 (audio) control */ - u8 reserved_0x07c[148]; - u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ - u8 reserved_0x114[20]; - u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ - u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ - u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ - u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ - u8 reserved_0x138[8]; - u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ - u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ - u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ - u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ - u8 reserved_0x150[8]; - u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ - u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ - u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ - u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ - u8 reserved_0x168[8]; - u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ - u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ - u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ - u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ - u8 reserved_0x180[384]; - u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ - u8 reserved_0x304[12]; - u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ - u8 reserved_0x314[12]; - u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ - u8 reserved_0x324[4]; - u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ - u8 reserved_0x32c[4]; - u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ - u8 reserved_0x334[12]; - u32 pll3_bias; /* 0x340 pll3 (video0) bias */ - u8 reserved_0x344[4]; - u32 pll_video1_bias; /* 0x348 pll video1 bias */ - u8 reserved_0x34c[12]; - u32 pll4_bias; /* 0x358 pll4 (ve) bias */ - u8 reserved_0x35c[4]; - u32 pll10_bias; /* 0x360 pll10 (de) bias */ - u8 reserved_0x364[12]; - u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ - u8 reserved_0x374[4]; - u32 pll2_bias; /* 0x378 pll2 (audio) bias */ - u8 reserved_0x37c[132]; - u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ - u8 reserved_0x404[252]; - u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ - u8 reserved_0x504[12]; - u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ - u8 reserved_0x514[8]; - u32 ahb3_cfg; /* 0x51c AHB3 clock control */ - u32 apb1_cfg; /* 0x520 APB1 clock control */ - u32 apb2_cfg; /* 0x524 APB2 clock control */ - u8 reserved_0x528[24]; - u32 mbus_cfg; /* 0x540 MBUS clock control */ - u8 reserved_0x544[188]; - u32 de_clk_cfg; /* 0x600 DE clock control */ - u8 reserved_0x604[8]; - u32 de_gate_reset; /* 0x60c DE gate/reset control */ - u8 reserved_0x610[16]; - u32 di_clk_cfg; /* 0x620 DI clock control */ - u8 reserved_0x024[8]; - u32 di_gate_reset; /* 0x62c DI gate/reset control */ - u8 reserved_0x630[64]; - u32 gpu_clk_cfg; /* 0x670 GPU clock control */ - u8 reserved_0x674[8]; - u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ - u32 ce_clk_cfg; /* 0x680 CE clock control */ - u8 reserved_0x684[8]; - u32 ce_gate_reset; /* 0x68c CE gate/reset control */ - u32 ve_clk_cfg; /* 0x690 VE clock control */ - u8 reserved_0x694[8]; - u32 ve_gate_reset; /* 0x69c VE gate/reset control */ - u8 reserved_0x6a0[16]; - u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ - u8 reserved_0x6b4[8]; - u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ - u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ - u8 reserved_0x6c4[8]; - u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ - u8 reserved_0x6d0[60]; - u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ - u8 reserved_0x710[12]; - u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ - u8 reserved_0x720[12]; - u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ - u8 reserved_0x730[12]; - u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ - u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ - u8 reserved_0x744[72]; - u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ - u8 reserved_0x790[12]; - u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ - u8 reserved_0x7a0[12]; - u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ - u8 reserved_0x7b0[12]; - u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ - u8 reserved_0x7c0[64]; - u32 dram_clk_cfg; /* 0x800 DRAM clock control */ - u32 mbus_gate; /* 0x804 MBUS gate control */ - u8 reserved_0x808[4]; - u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ - u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ - u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ - u8 reserved_0x818[20]; - u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ - u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ - u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ - u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ - u8 reserved_0x83c[16]; - u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ - u8 reserved_0x850[188]; - u32 uart_gate_reset; /* 0x90c UART gate/reset control */ - u8 reserved_0x910[12]; - u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ - u8 reserved_0x920[28]; - u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ - u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ - u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ - u8 reserved_0x948[36]; - u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ - u8 reserved_0x970[12]; - u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ - u8 reserved_0x980[48]; - u32 ts_clk_cfg; /* 0x9b0 TS clock control */ - u8 reserved_0x9b4[8]; - u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ - u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ - u8 reserved_0x9c4[8]; - u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ - u8 reserved_0x9d0[44]; - u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ - u8 reserved_0xa00[12]; - u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ - u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ - u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ - u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ - u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ - u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ - u8 reserved_0xa24[8]; - u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ - u8 reserved_0xa30[16]; - u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ - u8 reserved_0xa44[8]; - u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ - u8 reserved_0xa50[16]; - u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ - u8 reserved_0xa64[8]; - u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ - u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ - u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ - u8 reserved_0xa78[4]; - u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ - u8 reserved_0xa80[12]; - u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ - u8 reserved_0xa90[32]; - u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ - u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ - u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ - u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ - u8 reserved_0xac0[64]; - u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ - u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ - u8 reserved_0xb08[8]; - u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ - u8 reserved_0xb14[8]; - u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ - u8 reserved_0xb20[60]; - u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ - u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ - u8 reserved_0xb64[24]; - u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ - u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ - u8 reserved_0xb84[24]; - u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ - u8 reserved_0xba0[96]; - u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ - u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ - u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ - u8 reserved_0xc0c[32]; - u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ - u8 reserved_0xc30[16]; - u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ - u8 reserved_0xc44[8]; - u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ - u8 reserved_0xc50[688]; - u32 ccu_sec_switch; /* 0xf00 CCU security switch */ - u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ -}; +#define CCU_H6_PLL1_CFG 0x000 +#define CCU_H6_PLL5_CFG 0x010 +#define CCU_H6_PLL6_CFG 0x020 +#define CCU_H6_CPU_AXI_CFG 0x500 +#define CCU_H6_PSI_AHB1_AHB2_CFG 0x510 +#define CCU_H6_AHB3_CFG 0x51c +#define CCU_H6_APB1_CFG 0x520 +#define CCU_H6_APB2_CFG 0x524 +#define CCU_H6_MBUS_CFG 0x540 +#define CCU_H6_DRAM_CLK_CFG 0x800 +#define CCU_H6_DRAM_GATE_RESET 0x80c +#define CCU_MMC0_CLK_CFG 0x830 +#define CCU_MMC1_CLK_CFG 0x834 +#define CCU_MMC2_CLK_CFG 0x838 +#define CCU_H6_MMC_GATE_RESET 0x84c +#define CCU_H6_UART_GATE_RESET 0x90c +#define CCU_H6_I2C_GATE_RESET 0x91c /* pll1 bit field */ #define CCM_PLL1_CTRL_EN BIT(31) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 7fcf340db69..28c3faccbbc 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -10,6 +10,13 @@ #ifndef _SUNXI_CLOCK_SUN6I_H #define _SUNXI_CLOCK_SUN6I_H +#define CCU_AHB_GATE0 0x060 +#define CCU_MMC0_CLK_CFG 0x088 +#define CCU_MMC1_CLK_CFG 0x08c +#define CCU_MMC2_CLK_CFG 0x090 +#define CCU_MMC3_CLK_CFG 0x094 +#define CCU_AHB_RESET0_CFG 0x2c0 + struct sunxi_ccm_reg { u32 pll1_cfg; /* 0x00 pll1 control */ u32 reserved0; diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 35ca0491ac9..5ad2163926a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -13,6 +13,13 @@ #ifndef _SUNXI_CLOCK_SUN8I_A83T_H #define _SUNXI_CLOCK_SUN8I_A83T_H +#define CCU_AHB_GATE0 0x060 +#define CCU_MMC0_CLK_CFG 0x088 +#define CCU_MMC1_CLK_CFG 0x08c +#define CCU_MMC2_CLK_CFG 0x090 +#define CCU_MMC3_CLK_CFG 0x094 +#define CCU_AHB_RESET0_CFG 0x2c0 + struct sunxi_ccm_reg { u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 006f7761fc6..8d696e533f8 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -12,6 +12,13 @@ #include <linux/bitops.h> #endif +#define CCU_MMC0_CLK_CFG 0x410 +#define CCU_MMC1_CLK_CFG 0x414 +#define CCU_MMC2_CLK_CFG 0x418 +#define CCU_MMC3_CLK_CFG 0x41c +#define CCU_AHB_GATE0 0x580 +#define CCU_AHB_RESET0_CFG 0x5a0 + struct sunxi_ccm_reg { u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h new file mode 100644 index 00000000000..bc9e0d868c5 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Helpers that are commonly used with DW memory controller. + * + * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com> + * + */ + +#ifndef _DRAM_DW_HELPERS_H +#define _DRAM_DW_HELPERS_H + +#include <asm/arch/dram.h> + +bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config); +void mctl_auto_detect_rank_width(const struct dram_para *para, + struct dram_config *config); +void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config); +unsigned long mctl_calc_size(const struct dram_config *config); + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index f0caecc807d..af6cd337d7e 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -315,12 +315,15 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); struct dram_para { u32 clk; enum sunxi_dram_type type; + const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; +}; + +struct dram_config { u8 cols; u8 rows; u8 ranks; u8 bus_full_width; - const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; static inline int ns_to_t(int nanoseconds) @@ -330,6 +333,6 @@ static inline int ns_to_t(int nanoseconds) return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); } -void mctl_set_timing_params(struct dram_para *para); +void mctl_set_timing_params(void); #endif /* _SUNXI_DRAM_SUN50I_H6_H */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h index fd63d3aad83..d6653c3bb06 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h +++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h @@ -9,46 +9,12 @@ #define _SUN50I_PRCM_H #ifndef __ASSEMBLY__ -#include <linux/compiler.h> -struct sunxi_prcm_reg { - u32 cpus_cfg; /* 0x000 */ - u8 res0[0x8]; /* 0x004 */ - u32 apbs1_cfg; /* 0x00c */ - u32 apbs2_cfg; /* 0x010 */ - u8 res1[0x108]; /* 0x014 */ - u32 tmr_gate_reset; /* 0x11c */ - u8 res2[0xc]; /* 0x120 */ - u32 twd_gate_reset; /* 0x12c */ - u8 res3[0xc]; /* 0x130 */ - u32 pwm_gate_reset; /* 0x13c */ - u8 res4[0x4c]; /* 0x140 */ - u32 uart_gate_reset; /* 0x18c */ - u8 res5[0xc]; /* 0x190 */ - u32 twi_gate_reset; /* 0x19c */ - u8 res6[0x1c]; /* 0x1a0 */ - u32 rsb_gate_reset; /* 0x1bc */ - u32 cir_cfg; /* 0x1c0 */ - u8 res7[0x8]; /* 0x1c4 */ - u32 cir_gate_reset; /* 0x1cc */ - u8 res8[0x10]; /* 0x1d0 */ - u32 w1_cfg; /* 0x1e0 */ - u8 res9[0x8]; /* 0x1e4 */ - u32 w1_gate_reset; /* 0x1ec */ - u8 res10[0x1c]; /* 0x1f0 */ - u32 rtc_gate_reset; /* 0x20c */ - u8 res11[0x34]; /* 0x210 */ - u32 pll_ldo_cfg; /* 0x244 */ - u8 res12[0x8]; /* 0x248 */ - u32 sys_pwroff_gating; /* 0x250 */ - u8 res13[0xbc]; /* 0x254 */ - u32 res_cal_ctrl; /* 0x310 */ - u32 ohms200; /* 0x314 */ - u32 ohms240; /* 0x318 */ - u32 res_cal_status; /* 0x31c */ -}; -check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c); -check_member(sunxi_prcm_reg, res_cal_status, 0x31c); +#define CCU_PRCM_I2C_GATE_RESET 0x19c +#define CCU_PRCM_PLL_LDO_CFG 0x244 +#define CCU_PRCM_SYS_PWROFF_GATING 0x250 +#define CCU_PRCM_RES_CAL_CTRL 0x310 +#define CCU_PRCM_OHMS240 0x318 #define PRCM_TWI_GATE (1 << 0) #define PRCM_TWI_RESET (1 << 16) diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h index e9e96c1f933..bafcf857620 100644 --- a/arch/arm/include/asm/arch-tegra20/funcmux.h +++ b/arch/arm/include/asm/arch-tegra20/funcmux.h @@ -19,6 +19,7 @@ enum { FUNCMUX_UART1_UAA_UAB, FUNCMUX_UART1_GPU, FUNCMUX_UART1_SDIO1, + FUNCMUX_UART1_SDB_SDD, FUNCMUX_UART2_UAD = 0, FUNCMUX_UART4_GMC = 0, diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 849b3d0efb7..4c1b81483c9 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -428,11 +428,21 @@ void switch_to_hypervisor_ret(void); #define wfi() #endif +#if !defined(__thumb2__) +/* + * We will need to switch to ARM mode (.arm) for some instructions such as + * mrc p15 etc. + */ +#define asm_arm_or_thumb2(insn) asm volatile(".arm\n\t" insn) +#else +#define asm_arm_or_thumb2(insn) asm volatile(insn) +#endif + static inline unsigned long read_mpidr(void) { unsigned long val; - asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (val)); + asm_arm_or_thumb2("mrc p15, 0, %0, c0, c0, 5" : "=r" (val)); return val; } @@ -461,11 +471,13 @@ static inline unsigned int get_cr(void) unsigned int val; if (is_hyp()) - asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val) + asm_arm_or_thumb2("mrc p15, 4, %0, c1, c0, 0 @ get CR" + : "=r" (val) : : "cc"); else - asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) + asm_arm_or_thumb2("mrc p15, 0, %0, c1, c0, 0 @ get CR" + : "=r" (val) : : "cc"); return val; @@ -474,11 +486,11 @@ static inline unsigned int get_cr(void) static inline void set_cr(unsigned int val) { if (is_hyp()) - asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" : + asm_arm_or_thumb2("mcr p15, 4, %0, c1, c0, 0 @ set CR" : : "r" (val) : "cc"); else - asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : + asm_arm_or_thumb2("mcr p15, 0, %0, c1, c0, 0 @ set CR" : : "r" (val) : "cc"); isb(); |