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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6sl_pins.h8
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_px30.h6
-rw-r--r--arch/arm/include/asm/arch-rockchip/f_rockusb.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_px30.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_rk3328.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_rv1126.h2
-rw-r--r--arch/arm/include/asm/iproc-common/sysmap.h20
8 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 306f797f7a8..86d295c1a8d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -241,7 +241,7 @@
#define DCFG_RCWSR15 0x138
#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
-#define DCFG_DCSR_BASE 0X700100000ULL
+#define DCFG_DCSR_BASE 0x700100000ULL
#define DCFG_DCSR_PORCR1 0x000
/* Interrupt Sampling Control */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 01b14d73dc9..699c951b1b9 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -31,10 +31,10 @@ enum {
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
- MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0),
- MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0),
- MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0),
- MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0),
+ MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h
index 504459bd93d..408fdd66635 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h
@@ -299,9 +299,9 @@ enum {
/* CRU_CLK_SEL30_CON */
CLK_I2S1_DIV_CON_MASK = 0x7f,
- CLK_I2S1_PLL_SEL_MASK = 0X1 << 8,
- CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8,
- CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8,
+ CLK_I2S1_PLL_SEL_MASK = 0x1 << 8,
+ CLK_I2S1_PLL_SEL_GPLL = 0x0 << 8,
+ CLK_I2S1_PLL_SEL_NPLL = 0x1 << 8,
CLK_I2S1_SEL_MASK = 0x3 << 10,
CLK_I2S1_SEL_I2S1 = 0x0 << 10,
CLK_I2S1_SEL_FRAC = 0x1 << 10,
diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
index e9c7f793391..9abb3b16c42 100644
--- a/arch/arm/include/asm/arch-rockchip/f_rockusb.h
+++ b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
@@ -65,7 +65,7 @@ K_FW_SPI_READ_10 = 0x21,
K_FW_SPI_WRITE_10 = 0x22,
K_FW_LBA_ERASE_10 = 0x25,
-K_FW_SESSION = 0X30,
+K_FW_SESSION = 0x30,
K_FW_RESET = 0xff,
};
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_px30.h
index 2ab8e97ae1d..bf0cd01e7cc 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_px30.h
@@ -20,7 +20,7 @@
/* DDR GRF */
#define DDR_GRF_CON(n) (0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE (0X100)
+#define DDR_GRF_STATUS_BASE (0x100)
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
#define DDR_GRF_LP_CON (0x20)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
index 10923505d6e..454f9ca8878 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
@@ -32,7 +32,7 @@
/* DDR GRF */
#define DDR_GRF_CON(n) (0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE (0X100)
+#define DDR_GRF_STATUS_BASE (0x100)
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
/* CRU_SOFTRESET_CON5 */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
index 6a07436059c..9b65bad2581 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
@@ -185,7 +185,7 @@
/* DDR GRF */
#define DDR_GRF_CON(n) (0 + (n) * 4)
-#define DDR_GRF_STATUS_BASE (0X100)
+#define DDR_GRF_STATUS_BASE (0x100)
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
#define DDR_GRF_LP_CON (0x20)
diff --git a/arch/arm/include/asm/iproc-common/sysmap.h b/arch/arm/include/asm/iproc-common/sysmap.h
index efd2f35f212..c071e9ea53f 100644
--- a/arch/arm/include/asm/iproc-common/sysmap.h
+++ b/arch/arm/include/asm/iproc-common/sysmap.h
@@ -6,17 +6,17 @@
#ifndef __SYSMAP_H
#define __SYSMAP_H
-#define IHOST_PROC_CLK_PLLARMA 0X19000C00
-#define IHOST_PROC_CLK_PLLARMB 0X19000C04
+#define IHOST_PROC_CLK_PLLARMA 0x19000C00
+#define IHOST_PROC_CLK_PLLARMB 0x19000C04
#define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24
-#define IHOST_PROC_CLK_WR_ACCESS 0X19000000
-#define IHOST_PROC_CLK_POLICY_FREQ 0X19000008
+#define IHOST_PROC_CLK_WR_ACCESS 0x19000000
+#define IHOST_PROC_CLK_POLICY_FREQ 0x19000008
#define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31
#define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24
#define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16
#define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8
-#define IHOST_PROC_CLK_POLICY_CTL 0X1900000C
+#define IHOST_PROC_CLK_POLICY_CTL 0x1900000C
#define IHOST_PROC_CLK_POLICY_CTL__GO 0
#define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1
#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0
@@ -26,11 +26,11 @@
#define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8
#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1
#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0
-#define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200
-#define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204
-#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210
-#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300
-#define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400
+#define IHOST_PROC_CLK_CORE0_CLKGATE 0x19000200
+#define IHOST_PROC_CLK_CORE1_CLKGATE 0x19000204
+#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0x19000210
+#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0x19000300
+#define IHOST_PROC_CLK_APB0_CLKGATE 0x19000400
#define IPROC_CLKCT_HDELAY_SW_EN 0x00000303
#define IPROC_REG_WRITE_ACCESS 0x00a5a501
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-25 13:02:12 +0000