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-rw-r--r--arch/arm/include/asm/arch-meson/boot.h14
-rw-r--r--arch/arm/include/asm/arch-meson/sm.h48
-rw-r--r--arch/arm/include/asm/arch-npcm8xx/gmac.h18
-rw-r--r--arch/arm/include/asm/arch-sunxi/boot0.h8
-rw-r--r--arch/arm/include/asm/arch-tegra/dc.h46
-rw-r--r--arch/arm/include/asm/arch-tegra/pinmux.h20
-rw-r--r--arch/arm/include/asm/arch-tegra124/pinmux.h4
-rw-r--r--arch/arm/include/asm/arch-tegra20/clock-tables.h2
-rw-r--r--arch/arm/include/asm/arch-tegra20/pinmux.h6
-rw-r--r--arch/arm/include/asm/armv8/cpu.h6
-rw-r--r--arch/arm/include/asm/armv8/mmu.h2
-rw-r--r--arch/arm/include/asm/setjmp.h17
-rw-r--r--arch/arm/include/asm/system.h18
13 files changed, 176 insertions, 33 deletions
diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h
index c67d12d06c9..a11dfde719e 100644
--- a/arch/arm/include/asm/arch-meson/boot.h
+++ b/arch/arm/include/asm/arch-meson/boot.h
@@ -21,4 +21,18 @@ int meson_get_boot_device(void);
int meson_get_soc_rev(char *buff, size_t buff_len);
+/**
+ * meson_get_socinfo - retrieve cpu_id of the Amlogic SoC
+ *
+ * The value in the following format is read from register:
+ * +-----------+------------+------------+------------+
+ * | family_id | package_id | chip_rev | layout_rev |
+ * +-----------+------------+------------+------------+
+ * | 31 24 | 23 16 | 15 8 | 7 0 |
+ * +-----------+------------+------------+------------+
+ *
+ * Return: 4 bytes value of cpu_id on success or 0 on failure.
+ */
+u32 meson_get_socinfo(void);
+
#endif /* __MESON_BOOT_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
index 4b1d564bc48..4d614955fc2 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -6,6 +6,8 @@
#ifndef __MESON_SM_H__
#define __MESON_SM_H__
+#include <asm/types.h>
+
/**
* meson_sm_read_efuse - read efuse memory into buffer
*
@@ -27,16 +29,60 @@ ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size);
#define SM_SERIAL_SIZE 12
+#define MESON_CPU_ID_SZ 4
+#define MESON_CHIP_ID_SZ 16
+
+/**
+ * union meson_cpu_id - Amlogic cpu_id.
+ * @raw: buffer to hold the cpu_id value as sequential bytes.
+ * @val: cpu_id represented as 32 bit value.
+ */
+union meson_cpu_id {
+ u8 raw[MESON_CPU_ID_SZ];
+ u32 val;
+};
+
+/**
+ * struct meson_sm_chip_id - Amlogic chip_id.
+ * @cpu_id: cpu_id value, which is distinct from socinfo in that the order of
+ * PACK & MINOR bytes are swapped according to Amlogic chip_id format.
+ * @serial: 12 byte unique SoC number, identifying particular die, read
+ * usually from efuse OTP storage. Serial comes in little-endian
+ * order.
+ */
+struct meson_sm_chip_id {
+ union meson_cpu_id cpu_id;
+ u8 serial[SM_SERIAL_SIZE];
+};
/**
- * meson_sm_get_serial - read chip unique id into buffer
+ * meson_sm_get_serial - read chip unique serial (OTP data) into buffer
*
* @buffer: pointer to buffer
* @size: buffer size.
+ *
+ * Serial is returned in big-endian order.
+ *
* @return: zero on success or -errno on failure
*/
int meson_sm_get_serial(void *buffer, size_t size);
+/**
+ * meson_sm_get_chip_id - read Amlogic chip_id
+ *
+ * @chip_id: pointer to buffer capable to hold the struct meson_sm_chip_id
+ *
+ * Amlogic SoCs support 2 versions of chip_id. Function requests the newest
+ * one (v2), but if chip_id v2 is not supported, then secure monitor returns
+ * v1. All differences between v1 and v2 versions are handled by this function
+ * and chip_id is returned in unified format.
+ *
+ * chip_id contains serial, which is returned here in little-endian order.
+ *
+ * @return: 0 on success or -errno on failure
+ */
+int meson_sm_get_chip_id(struct meson_sm_chip_id *chip_id);
+
enum {
REBOOT_REASON_COLD = 0,
REBOOT_REASON_NORMAL = 1,
diff --git a/arch/arm/include/asm/arch-npcm8xx/gmac.h b/arch/arm/include/asm/arch-npcm8xx/gmac.h
new file mode 100644
index 00000000000..f84eedddc22
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/gmac.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_GMAC_H_
+#define _NPCM_GMAC_H_
+
+/* PCS registers */
+#define PCS_BA 0xF0780000
+#define PCS_IND_AC 0x1FE
+#define SR_MII_MMD 0x3E0000
+#define SR_MII_MMD_CTRL 0x0
+#define SR_MII_MMD_STS 0x2
+#define VR_MII_MMD 0x3F0000
+#define VR_MII_MMD_CTRL1 0x0
+#define VR_MII_MMD_AN_CTRL 0x2
+
+#define LINK_UP_TIMEOUT (3 * CONFIG_SYS_HZ)
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6b2bb5a4586..24c81391d58 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -16,10 +16,11 @@
*/
tst x0, x0 // this is "b #0x84" in ARM
b reset
- .space 0x7c
+ .space 0x78
+ .word fel_stash - .
- .word 0xe28f0070 // add r0, pc, #112 // @(fel_stash - .)
- .word 0xe59f106c // ldr r1, [pc, #108] // fel_stash - .
+ .word 0xe24f000c // sub r0, pc, #12 // @(fel_stash - .)
+ .word 0xe51f1010 // ldr r1, [pc, #-16] // fel_stash - .
.word 0xe0800001 // add r0, r0, r1
.word 0xe580d000 // str sp, [r0]
.word 0xe580e004 // str lr, [r0, #4]
@@ -54,7 +55,6 @@
#else
.word CONFIG_TEXT_BASE
#endif
- .word fel_stash - .
#else
/* normal execution */
b reset
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index ca3718411ab..2fd07403bdf 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -448,6 +448,11 @@ enum win_color_depth_id {
#define LVS_OUTPUT_POLARITY_LOW BIT(28)
#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
+/* DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 */
+#define H_PULSE0_ENABLE BIT(8)
+#define H_PULSE1_ENABLE BIT(10)
+#define H_PULSE2_ENABLE BIT(12)
+
/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
#define CURSOR_ENABLE BIT(16)
#define SOR_ENABLE BIT(25)
@@ -504,6 +509,22 @@ enum {
DATA_ORDER_BLUE_RED,
};
+/* DC_DISP_DISP_COLOR_CONTROL 0x430 */
+#define DITHER_CONTROL_DISABLE (0 << 8)
+#define DITHER_CONTROL_ORDERED (2 << 8)
+#define DITHER_CONTROL_ERRDIFF (3 << 8)
+enum {
+ BASE_COLOR_SIZE_666,
+ BASE_COLOR_SIZE_111,
+ BASE_COLOR_SIZE_222,
+ BASE_COLOR_SIZE_333,
+ BASE_COLOR_SIZE_444,
+ BASE_COLOR_SIZE_555,
+ BASE_COLOR_SIZE_565,
+ BASE_COLOR_SIZE_332,
+ BASE_COLOR_SIZE_888,
+};
+
/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
#define DE_SELECT_SHIFT 0
#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
@@ -570,8 +591,27 @@ enum {
#define V_DDA_INC_SHIFT 16
#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
-#define DC_POLL_TIMEOUT_MS 50
-#define DC_N_WINDOWS 5
-#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
+#define DC_POLL_TIMEOUT_MS 50
+#define DC_N_WINDOWS 5
+#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
+
+#define PULSE_MODE_NORMAL (0 << 3)
+#define PULSE_MODE_ONE_CLOCK (1 << 3)
+#define PULSE_POLARITY_HIGH (0 << 4)
+#define PULSE_POLARITY_LOW (1 << 4)
+#define PULSE_QUAL_ALWAYS (0 << 6)
+#define PULSE_QUAL_VACTIVE (2 << 6)
+#define PULSE_QUAL_VACTIVE1 (3 << 6)
+#define PULSE_LAST_START_A (0 << 8)
+#define PULSE_LAST_END_A (1 << 8)
+#define PULSE_LAST_START_B (2 << 8)
+#define PULSE_LAST_END_B (3 << 8)
+#define PULSE_LAST_START_C (4 << 8)
+#define PULSE_LAST_END_C (5 << 8)
+#define PULSE_LAST_START_D (6 << 8)
+#define PULSE_LAST_END_D (7 << 8)
+
+#define PULSE_START(x) (((x) & 0xfff) << 0)
+#define PULSE_END(x) (((x) & 0xfff) << 16)
#endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index 4b6e8419504..9a5cc93884c 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -34,41 +34,41 @@ enum pmux_pin_io {
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_DISABLE = 0,
PMUX_PIN_LOCK_ENABLE,
+ PMUX_PIN_LOCK_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_DISABLE = 0,
PMUX_PIN_OD_ENABLE,
+ PMUX_PIN_OD_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_DISABLE = 0,
PMUX_PIN_IO_RESET_ENABLE,
+ PMUX_PIN_IO_RESET_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
+ PMUX_PIN_RCV_SEL_NORMAL = 0,
PMUX_PIN_RCV_SEL_HIGH,
+ PMUX_PIN_RCV_SEL_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
enum pmux_pin_e_io_hv {
- PMUX_PIN_E_IO_HV_DEFAULT = 0,
- PMUX_PIN_E_IO_HV_NORMAL,
+ PMUX_PIN_E_IO_HV_NORMAL = 0,
PMUX_PIN_E_IO_HV_HIGH,
+ PMUX_PIN_E_IO_HV_DEFAULT,
};
#endif
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 3aba17d21e4..fbe15fc612d 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -578,6 +578,10 @@ static const char * const tegra_pinctrl_to_drvgrp[] = {
[PMUX_DRVGRP_AO4] = "ao4",
};
+static const char * const tegra_pinctrl_to_mipipadgrp[] = {
+ [PMUX_MIPIPADCTRLGRP_DSI_B] = "mipi_pad_ctrl_dsi_b",
+};
+
static const char * const tegra_pinctrl_to_func[] = {
[PMUX_FUNC_DEFAULT] = "default",
[PMUX_FUNC_BLINK] = "blink",
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
index 861b3d5d07c..82685353bd1 100644
--- a/arch/arm/include/asm/arch-tegra20/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h
@@ -32,6 +32,7 @@ enum clock_id {
CLOCK_ID_COUNT, /* number of clocks */
CLOCK_ID_NONE = -1,
+ CLOCK_ID_DISPLAY2 = CLOCK_ID_NONE, /* for compatibility */
};
/* The clocks supported by the hardware */
@@ -159,6 +160,7 @@ enum periph_id {
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
+ PERIPH_ID_DSIB = CLOCK_ID_NONE, /* for compatibility */
};
enum pll_out_id {
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 8c8579e87e3..9598851b100 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -467,14 +467,14 @@ static const char * const tegra_pinctrl_to_func[] = {
[PMUX_FUNC_DAP3] = "dap3",
[PMUX_FUNC_DAP4] = "dap4",
[PMUX_FUNC_DAP5] = "dap5",
- [PMUX_FUNC_DISPA] = "dispa",
- [PMUX_FUNC_DISPB] = "dispb",
+ [PMUX_FUNC_DISPA] = "displaya",
+ [PMUX_FUNC_DISPB] = "displayb",
[PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll",
[PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll",
[PMUX_FUNC_GMI] = "gmi",
[PMUX_FUNC_GMI_INT] = "gmi_int",
[PMUX_FUNC_HDMI] = "hdmi",
- [PMUX_FUNC_I2C] = "i2c",
+ [PMUX_FUNC_I2C] = "i2c1",
[PMUX_FUNC_I2C2] = "i2c2",
[PMUX_FUNC_I2C3] = "i2c3",
[PMUX_FUNC_IDE] = "ide",
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
index 4dbb589aab8..e906fdf1bf1 100644
--- a/arch/arm/include/asm/armv8/cpu.h
+++ b/arch/arm/include/asm/armv8/cpu.h
@@ -5,8 +5,11 @@
#define MIDR_PARTNUM_CORTEX_A35 0xD04
#define MIDR_PARTNUM_CORTEX_A53 0xD03
+#define MIDR_PARTNUM_CORTEX_A55 0xD05
#define MIDR_PARTNUM_CORTEX_A57 0xD07
#define MIDR_PARTNUM_CORTEX_A72 0xD08
+#define MIDR_PARTNUM_CORTEX_A73 0xD09
+#define MIDR_PARTNUM_CORTEX_A75 0xD0A
#define MIDR_PARTNUM_CORTEX_A76 0xD0B
#define MIDR_PARTNUM_SHIFT 0x4
#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
@@ -31,6 +34,9 @@ static inline unsigned int read_midr(void)
is_cortex_a(35)
is_cortex_a(53)
+is_cortex_a(55)
is_cortex_a(57)
is_cortex_a(72)
+is_cortex_a(73)
+is_cortex_a(75)
is_cortex_a(76)
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 0ab681c893d..6af8cd111a4 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -66,6 +66,7 @@
#define PTE_BLOCK_NG (1 << 11)
#define PTE_BLOCK_PXN (UL(1) << 53)
#define PTE_BLOCK_UXN (UL(1) << 54)
+#define PTE_BLOCK_RO (UL(1) << 7)
/*
* AttrIndx[2:0]
@@ -75,6 +76,7 @@
#define PMD_ATTRMASK (PTE_BLOCK_PXN | \
PTE_BLOCK_UXN | \
PMD_ATTRINDX_MASK | \
+ PTE_BLOCK_RO | \
PTE_TYPE_VALID)
/*
diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
index 662bec86321..a9eccf7f632 100644
--- a/arch/arm/include/asm/setjmp.h
+++ b/arch/arm/include/asm/setjmp.h
@@ -4,13 +4,11 @@
* (C) Copyright 2016 Alexander Graf <agraf@suse.de>
*/
-#ifndef _SETJMP_H_
-#define _SETJMP_H_ 1
+#ifndef _ASM_SETJMP_H_
+#define _ASM_SETJMP_H_ 1
+
+#include <asm-generic/int-ll64.h>
-/*
- * This really should be opaque, but the EFI implementation wrongly
- * assumes that a 'struct jmp_buf_data' is defined.
- */
struct jmp_buf_data {
#if defined(__aarch64__)
u64 regs[13];
@@ -19,9 +17,4 @@ struct jmp_buf_data {
#endif
};
-typedef struct jmp_buf_data jmp_buf[1];
-
-int setjmp(jmp_buf jmp);
-void longjmp(jmp_buf jmp, int ret);
-
-#endif /* _SETJMP_H_ */
+#endif /* _ASM_SETJMP_H_ */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 091082281c7..849b3d0efb7 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -303,8 +303,26 @@ void flush_l3_cache(void);
* @emerg: Also map the region in the emergency table
*/
void mmu_map_region(phys_addr_t start, u64 size, bool emerg);
+
+/**
+ * mmu_change_region_attr() - change a mapped region attributes
+ *
+ * @start: Start address of the region
+ * @size: Size of the region
+ * @aatrs: New attributes
+ */
void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
+/**
+ * mmu_change_region_attr_nobreak() - change a mapped region attributes without doing
+ * break-before-make
+ *
+ * @start: Start address of the region
+ * @size: Size of the region
+ * @aatrs: New attributes
+ */
+void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t size, u64 attrs);
+
/*
* smc_call() - issue a secure monitor call
*
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-20 06:54:52 +0000