diff options
Diffstat (limited to 'arch/arm/mach-at91')
| -rw-r--r-- | arch/arm/mach-at91/Kconfig | 21 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/gpio.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d2_smc.h | 76 |
3 files changed, 95 insertions, 4 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 7e85b69679d..69072635392 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -143,10 +143,9 @@ config TARGET_AT91SAM9X5EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT -config TARGET_SAMA5D2_PTC - bool "SAMA5D2 PTC board" +config TARGET_SAMA5D2_PTC_EK + bool "SAMA5D2 PTC EK board" select SAMA5D2 - select SUPPORT_SPL select BOARD_EARLY_INIT_F config TARGET_SAMA5D2_XPLAINED @@ -237,6 +236,18 @@ config TARGET_VINCO select SAMA5D4 select SUPPORT_SPL +config TARGET_WB45N + bool "Support Laird WB45N" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_WB50N + bool "Support Laird WB50N" + select BOARD_LATE_INIT + select CPU_V7 + select SUPPORT_SPL + select BOARD_EARLY_INIT_F + endchoice config SYS_SOC @@ -251,7 +262,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" -source "board/atmel/sama5d2_ptc/Kconfig" +source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" @@ -271,6 +282,8 @@ source "board/ronetix/pm9g45/Kconfig" source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" +source "board/laird/wb45n/Kconfig" +source "board/laird/wb50n/Kconfig" config SPL_LDSCRIPT default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index df0f71975ad..e2063167359 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin) at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_B_periph(x, y) \ at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y) +#define at91_set_gpio_deglitch(x, y) \ + at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_output(x, y) \ at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_input(x, y) \ diff --git a/arch/arm/mach-at91/include/mach/sama5d2_smc.h b/arch/arm/mach-at91/include/mach/sama5d2_smc.h new file mode 100644 index 00000000000..7ddb728cf3e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2_smc.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2017 Microchip Corporation. + * + * Static Memory Controllers (SMC) - System peripherals registers. + * Based on SAMA5D2 datasheet. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SAMA5D2_SMC_H +#define SAMA5D2_SMC_H + +#ifdef __ASSEMBLY__ +#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700) +#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704) +#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708) +#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c) +#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710) +#else +struct at91_cs { + u32 setup; /* 0x600 SMC Setup Register */ + u32 pulse; /* 0x604 SMC Pulse Register */ + u32 cycle; /* 0x608 SMC Cycle Register */ + u32 timings; /* 0x60C SMC Cycle Register */ + u32 mode; /* 0x610 SMC Mode Register */ +}; + +struct at91_smc { + struct at91_cs cs[4]; +}; +#endif /* __ASSEMBLY__ */ + +#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) +#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) +#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) +#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) + +#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) +#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) +#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) +#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) + +#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) +#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) + +#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) +#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) +#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) +#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) +#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) +#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) +#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) +#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) + +#define AT91_SMC_MODE_RM_NCS 0x00000000 +#define AT91_SMC_MODE_RM_NRD 0x00000001 +#define AT91_SMC_MODE_WM_NCS 0x00000000 +#define AT91_SMC_MODE_WM_NWE 0x00000002 + +#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 +#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 +#define AT91_SMC_MODE_EXNW_READY 0x00000030 + +#define AT91_SMC_MODE_BAT 0x00000100 +#define AT91_SMC_MODE_DBW_8 0x00000000 +#define AT91_SMC_MODE_DBW_16 0x00001000 +#define AT91_SMC_MODE_DBW_32 0x00002000 +#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) +#define AT91_SMC_MODE_TDF 0x00100000 +#define AT91_SMC_MODE_PMEN 0x01000000 +#define AT91_SMC_MODE_PS_4 0x00000000 +#define AT91_SMC_MODE_PS_8 0x10000000 +#define AT91_SMC_MODE_PS_16 0x20000000 +#define AT91_SMC_MODE_PS_32 0x30000000 + +#endif |