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Diffstat (limited to 'arch/arm/mach-exynos/dmc_init_ddr3.c')
-rw-r--r--arch/arm/mach-exynos/dmc_init_ddr3.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index fa867f27f30..cad8ccc5315 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
* better have similar timings, since there's only a single adjustment that is
* shared by both chips).
*/
-const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+const unsigned int test_addr = CFG_SYS_SDRAM_BASE;
/* Test pattern with which RAM will be tested */
static const unsigned int test_pattern[] = {