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-rw-r--r--arch/arm/mach-imx/ddrmc-vf610-calibration.c12
-rw-r--r--arch/arm/mach-imx/ele_ahab.c29
-rw-r--r--arch/arm/mach-imx/image-container.c2
-rw-r--r--arch/arm/mach-imx/imx8/cpu.c4
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig13
-rw-r--r--arch/arm/mach-imx/imx9/soc.c3
-rw-r--r--arch/arm/mach-imx/mx6/clock.c8
-rw-r--r--arch/arm/mach-imx/mx7/psci-mx7.c4
8 files changed, 61 insertions, 14 deletions
diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.c b/arch/arm/mach-imx/ddrmc-vf610-calibration.c
index cd7e95e61d0..7d787d04598 100644
--- a/arch/arm/mach-imx/ddrmc-vf610-calibration.c
+++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.c
@@ -45,7 +45,7 @@
* based on trace length differences from their
* layout.
* Mismatches up to 25% or tCK (clock period) are
- * allowed, so the value in the filed doesn’t have
+ * allowed, so the value in the filed doesn't have
* to be very accurate.
*
* - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
@@ -184,14 +184,14 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n",
(tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0
- /* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */
+ /* Program Leveling mode - CR93[SW_LVL_MODE] to 'b10 */
clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3),
DDRMC_CR93_SW_LVL_MODE(0x2));
tmp = readl(&ddrmr->cr[93]);
debug("RDLVL: SW_LVL_MODE:\t 0x%x\n",
(tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3);
- /* Start procedure - CR93[SWLVL_START] to ’b1 */
+ /* Start procedure - CR93[SWLVL_START] to 'b1 */
sw_leveling_start;
/* Poll CR94[SWLVL_OP_DONE] */
@@ -211,7 +211,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF,
i << DDRMC_CR105_RDLVL_DL_0_OFF);
- /* Load values CR93[SWLVL_LOAD] to ’b1 */
+ /* Load values CR93[SWLVL_LOAD] to 'b1 */
sw_leveling_load_value;
/* Poll CR94[SWLVL_OP_DONE] */
@@ -263,7 +263,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF,
i << DDRMC_CR110_RDLVL_DL_1_OFF);
- /* Load values CR93[SWLVL_LOAD] to ’b1 */
+ /* Load values CR93[SWLVL_LOAD] to 'b1 */
sw_leveling_load_value;
/* Poll CR94[SWLVL_OP_DONE] */
@@ -317,7 +317,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
sw_leveling_load_value;
sw_leveling_op_done;
- /* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */
+ /* Exit procedure - CR94[SWLVL_EXIT] to 'b1 */
sw_leveling_exit;
/* Poll CR94[SWLVL_OP_DONE] */
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 295c055ad0a..d02316ed6cb 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -625,6 +625,29 @@ static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc, c
return CMD_RET_SUCCESS;
}
+static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u32 index;
+ u32 resp;
+ u32 info_type;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ index = simple_strtoul(argv[1], NULL, 16);
+ printf("Commit index is 0x%x\n", index);
+
+ if (ele_commit(index, &resp, &info_type)) {
+ printf("Error in AHAB commit\n");
+ return -EIO;
+ }
+
+ printf("Ahab commit succeeded. Information type is 0x%x\n", info_type);
+
+ return 0;
+}
+
U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
"autenticate OS container via AHAB",
"addr\n"
@@ -657,3 +680,9 @@ U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1, do_ahab_return_lifecycl
"addr\n"
"addr - Return lifecycle message block signed by OEM SRK\n"
);
+
+U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit,
+ "commit into the fuses any new SRK revocation and FW version information\n"
+ "that have been found into the NXP (ELE FW) and OEM containers",
+ ""
+);
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index c9455fe222a..35da0ae0425 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -262,7 +262,7 @@ static int get_imageset_end(void *dev, int dev_type)
}
#ifdef CONFIG_SPL_SPI_LOAD
-unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash)
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
{
int end;
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 0b91e448a5d..6e643188f40 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -84,6 +84,10 @@ static char *get_reset_cause(void)
}
}
+__weak void reset_cpu(void)
+{
+}
+
int arch_cpu_init(void)
{
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 328c3e38805..23d9217fcc2 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -53,6 +53,7 @@ config TARGET_IMX8MQ_EVK
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
@@ -78,6 +79,7 @@ config TARGET_IMX8MM_EVK
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
@@ -119,6 +121,7 @@ config TARGET_IMX8MM_VENICE
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_KONTRON_MX8MM
bool "Kontron Electronics N80xx"
@@ -148,6 +151,7 @@ config TARGET_IMX8MN_EVK
select IMX8M_LPDDR4
select FSL_CAAM
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
@@ -156,6 +160,7 @@ config TARGET_IMX8MN_DDR4_EVK
select IMX8M_DDR4
select FSL_CAAM
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MN_VENICE
bool "Support Gateworks Venice iMX8M Nano module"
@@ -167,6 +172,7 @@ config TARGET_IMX8MN_VENICE
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Plus"
@@ -182,6 +188,7 @@ config TARGET_IMX8MP_BEACON
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_DEBIX_MODEL_A
bool "Polyhex i.MX8M Plus Debix Model A SBC"
@@ -216,6 +223,7 @@ config TARGET_IMX8MP_EVK
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_VENICE
bool "Support Gateworks Venice iMX8M Plus module"
@@ -227,6 +235,7 @@ config TARGET_IMX8MP_VENICE
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
@@ -253,12 +262,14 @@ config TARGET_VERDIN_IMX8MM
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ imply OF_UPSTREAM
config TARGET_VERDIN_IMX8MP
bool "Support Toradex Verdin iMX8M Plus module"
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ imply OF_UPSTREAM
config TARGET_IMX8MM_BEACON
bool "imx8mm Beacon Embedded devkit"
@@ -268,6 +279,7 @@ config TARGET_IMX8MM_BEACON
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MN_BEACON
bool "imx8mn Beacon Embedded devkit"
@@ -277,6 +289,7 @@ config TARGET_IMX8MN_BEACON
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_PHYCORE_IMX8MM
bool "PHYTEC PHYCORE i.MX8MM"
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f06339f1388..2117489f232 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -262,7 +262,7 @@ static struct mm_region imx93_mem_map[] = {
/* Flexible Serial Peripheral Interface */
.virt = 0x28000000UL,
.phys = 0x28000000UL,
- .size = 0x30000000UL,
+ .size = 0x08000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -622,6 +622,7 @@ int imx9_probe_mu(void)
return 0;
}
EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu);
int timer_init(void)
{
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 1bdc568f9b1..e0da9c23958 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -714,10 +714,10 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
/*
* Register: PLL_VIDEO
* Bit Field: POST_DIV_SELECT
- * 00 — Divide by 4.
- * 01 — Divide by 2.
- * 10 — Divide by 1.
- * 11 — Reserved
+ * 00 - Divide by 4.
+ * 01 - Divide by 2.
+ * 10 - Divide by 1.
+ * 11 - Reserved
* No need to check post_div(1)
*/
for (post_div = 2; post_div <= 4; post_div <<= 1) {
diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c
index 699a2569cb7..0b71fa40344 100644
--- a/arch/arm/mach-imx/mx7/psci-mx7.c
+++ b/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -631,9 +631,9 @@ __secure void psci_system_suspend(u32 __always_unused function_id,
* Workaround:
* If both CPU0/CPU1 are IDLE, the last IDLE CPU should
* disable GIC first, then REG_BYPASS_COUNTER is used
- * to mask wakeup INT, and then execute “wfi” is used to
+ * to mask wakeup INT, and then execute "wfi" is used to
* bring the system into power down processing safely.
- * The counter must be enabled as close to the “wfi” state
+ * The counter must be enabled as close to the "wfi" state
* as possible. The following equation can be used to
* determine the RBC counter value:
* RBC_COUNT * (1/32K RTC frequency) >=
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 00:18:45 +0000