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-rw-r--r--arch/arm/mach-imx/cmd_nandbcb.c34
-rw-r--r--arch/arm/mach-imx/cpu.c30
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig16
-rw-r--r--arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg17
-rw-r--r--arch/arm/mach-imx/imx8m/lowlevel_init.S2
-rw-r--r--arch/arm/mach-imx/spl.c2
-rw-r--r--arch/arm/mach-imx/timer.c16
7 files changed, 90 insertions, 27 deletions
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index 44fc37695db..7157c9e9799 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -275,7 +275,8 @@ static int nandbcb_set_boot_config(int argc, char * const argv[],
boot_stream1_address);
if (boot_cfg->secondary_boot_stream_off_in_MB)
- boot_stream2_address = boot_cfg->secondary_boot_stream_off_in_MB * 1024 * 1024;
+ boot_stream2_address =
+ (loff_t)boot_cfg->secondary_boot_stream_off_in_MB * 1024 * 1024;
max_boot_stream_size = boot_stream2_address - boot_stream1_address;
@@ -476,7 +477,7 @@ static int fill_dbbt_data(struct mtd_info *mtd, void *buf, int num_blocks)
u32 *n_bad_blocksp = buf + 0x4;
for (n = 0; n < num_blocks; n++) {
- loff_t offset = n * mtd->erasesize;
+ loff_t offset = (loff_t)n * mtd->erasesize;
if (mtd_block_isbad(mtd, offset)) {
n_bad_blocks++;
*bb = n;
@@ -503,13 +504,18 @@ static int read_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb,
int ret = 0;
mtd = boot_cfg->mtd;
- fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
-
if (mtd_block_isbad(mtd, off)) {
printf("Block %d is bad, skipped\n", (int)CONV_TO_BLOCKS(off));
return 1;
}
+ fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
+ if (!fcb_raw_page) {
+ debug("failed to allocate fcb_raw_page\n");
+ ret = -ENOMEM;
+ return ret;
+ }
+
/*
* User BCH hardware to decode ECC for FCB
*/
@@ -563,7 +569,7 @@ static int write_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb)
{
struct mtd_info *mtd;
void *fcb_raw_page = NULL;
- int i, ret;
+ int i, ret = 0;
loff_t off;
size_t size;
@@ -653,8 +659,6 @@ static int write_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb)
off += g_boot_search_stride;
}
- return 0;
-
fcb_raw_page_err:
kfree(fcb_raw_page);
@@ -1483,7 +1487,7 @@ static int do_nandbcb(struct cmd_tbl *cmdtp, int flag, int argc,
plat_config = imx8mq_plat_config;
} else if (is_imx8mm()) {
plat_config = imx8mm_plat_config;
- } else if (is_imx8mn()) {
+ } else if (is_imx8mn() || is_imx8mp()) {
plat_config = imx8mn_plat_config;
} else if (is_imx8qm() || is_imx8qxp()) {
plat_config = imx8q_plat_config;
@@ -1492,13 +1496,13 @@ static int do_nandbcb(struct cmd_tbl *cmdtp, int flag, int argc,
return CMD_RET_FAILURE;
}
- if (plat_config.misc_flags & BT_SEARCH_CNT_FROM_FUSE) {
- if (is_imx8qxp()) {
- g_boot_search_count = fuse_to_search_count(0, 720,
- 0xc0, 6);
- printf("search count set to %d from fuse\n",
- g_boot_search_count);
- }
+ if ((plat_config.misc_flags) & BT_SEARCH_CNT_FROM_FUSE) {
+ if (is_imx8qxp())
+ g_boot_search_count = fuse_to_search_count(0, 720, 0xc0, 6);
+ if (is_imx8mn() || is_imx8mp())
+ g_boot_search_count = fuse_to_search_count(2, 2, 0x6000, 13);
+ printf("search count set to %d from fuse\n",
+ g_boot_search_count);
}
cmd = argv[1];
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a4d8f101b66..38b87ed5c39 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -24,6 +24,8 @@
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
@@ -278,6 +280,20 @@ void arch_preboot_os(void)
#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
imx_pcie_remove();
#endif
+
+#if defined(CONFIG_IMX_AHCI)
+ struct udevice *dev;
+ int rc;
+
+ rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
+ if (!rc && dev) {
+ rc = device_remove(dev, DM_REMOVE_NORMAL);
+ if (rc)
+ printf("Cannot remove SATA device '%s' (err=%d)\n",
+ dev->name, rc);
+ }
+#endif
+
#if defined(CONFIG_SATA)
if (!is_mx6sdl()) {
sata_remove(0);
@@ -385,6 +401,9 @@ u32 get_cpu_speed_grade_hz(void)
*/
#define OCOTP_TESTER3_TEMP_SHIFT 6
+/* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
+#define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
+
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -394,7 +413,10 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
uint32_t val;
val = readl(&fuse->tester3);
- val >>= OCOTP_TESTER3_TEMP_SHIFT;
+ if (is_imx8mp())
+ val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
+ else
+ val >>= OCOTP_TESTER3_TEMP_SHIFT;
val &= 0x3;
if (minc && maxc) {
@@ -445,12 +467,14 @@ enum boot_device get_boot_device(void)
case BOOT_TYPE_SPINOR:
boot_dev = SPI_NOR_BOOT;
break;
-#ifdef CONFIG_IMX8M
case BOOT_TYPE_USB:
boot_dev = USB_BOOT;
break;
-#endif
default:
+#ifdef CONFIG_IMX8M
+ if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
+ boot_dev = QSPI_BOOT;
+#endif
break;
}
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 8615dc3bec9..c455f7b5eb2 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -43,7 +43,7 @@ config TARGET_IMX8MM_EVK
select SUPPORT_SPL
select IMX8M_LPDDR4
-config TARGET_IMX8MN_EVK
+config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
select IMX8MN
select SUPPORT_SPL
@@ -72,11 +72,23 @@ config TARGET_IMX8MM_BEACON
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_IMX8MN_BEACON
+ bool "imx8mn Beacon Embedded devkit"
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_PHYCORE_IMX8MM
bool "PHYTEC PHYCORE i.MX8MM"
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+
+config TARGET_PHYCORE_IMX8MP
+ bool "PHYTEC PHYCORE i.MX8MP"
+ select IMX8MP
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
@@ -87,6 +99,8 @@ source "board/google/imx8mq_phanbell/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
source "board/beacon/imx8mm/Kconfig"
+source "board/beacon/imx8mn/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
+source "board/phytec/phycore_imx8mp/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg
new file mode 100644
index 00000000000..4c63b31db6d
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+FIT
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER spl/u-boot-spl-ddr.bin 0x912000
+SECOND_LOADER u-boot.itb 0x40200000 0x60000
+
+DDR_FW lpddr4_pmu_train_1d_imem.bin
+DDR_FW lpddr4_pmu_train_1d_dmem.bin
+DDR_FW lpddr4_pmu_train_2d_imem.bin
+DDR_FW lpddr4_pmu_train_2d_dmem.bin
diff --git a/arch/arm/mach-imx/imx8m/lowlevel_init.S b/arch/arm/mach-imx/imx8m/lowlevel_init.S
index a49a9cdb35c..dd263c40600 100644
--- a/arch/arm/mach-imx/imx8m/lowlevel_init.S
+++ b/arch/arm/mach-imx/imx8m/lowlevel_init.S
@@ -5,7 +5,7 @@
#include <config.h>
-.align 8
+.align 4
.global rom_pointer
rom_pointer:
.space 256
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index aa2686bb921..2d15f62445c 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -172,6 +172,8 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NAND;
case SPI_NOR_BOOT:
return BOOT_DEVICE_SPI;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_NOR;
case USB_BOOT:
return BOOT_DEVICE_USB;
default:
diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c
index fa1941aec42..a3c47889f13 100644
--- a/arch/arm/mach-imx/timer.c
+++ b/arch/arm/mach-imx/timer.c
@@ -39,18 +39,16 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
#define GPTPR_PRESCALER24M_SHIFT 12
#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
+DECLARE_GLOBAL_DATA_PTR;
+
static inline int gpt_has_clk_source_osc(void)
{
-#if defined(CONFIG_MX6)
if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
- is_mx6ull() || is_mx6sll())
+ is_mx6ull() || is_mx6sll() || is_mx7())
return 1;
return 0;
-#else
- return 0;
-#endif
}
static inline ulong gpt_get_clk(void)
@@ -73,7 +71,8 @@ int timer_init(void)
__raw_writel(GPTCR_SWR, &cur_gpt->control);
/* We have no udelay by now */
- __raw_writel(0, &cur_gpt->control);
+ for (i = 0; i < 100; i++)
+ __raw_writel(0, &cur_gpt->control);
i = __raw_readl(&cur_gpt->control);
i &= ~GPTCR_CLKSOURCE_MASK;
@@ -87,7 +86,7 @@ int timer_init(void)
* Enable bit and prescaler
*/
if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
- is_mx6sll()) {
+ is_mx6sll() || is_mx7()) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */
@@ -103,6 +102,9 @@ int timer_init(void)
#endif
__raw_writel(i, &cur_gpt->control);
+ gd->arch.tbl = __raw_readl(&cur_gpt->counter);
+ gd->arch.tbu = 0;
+
return 0;
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 17:15:31 +0000