6 files changed, 48 insertions, 22 deletions
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 11f90ed8a21..82257f3280f 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -9,6 +9,34 @@
 #include <asm/io.h>
 #include <asm/mach-imx/sys_proto.h>
 
+static void enable_ca7_smp(void)
+{
+	u32 val;
+
+	/* Read MIDR */
+	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
+	val = (val >> 4);
+	val &= 0xf;
+
+	/* Only set the SMP for Cortex A7 */
+	if (val == 0x7) {
+		/* Read auxiliary control register */
+		asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+
+		if (val & (1 << 6))
+			return;
+
+		/* Enable SMP */
+		val |= (1 << 6);
+
+		/* Write auxiliary control register */
+		asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+
+		DSB;
+		ISB;
+	}
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
@@ -20,6 +48,9 @@ void enable_caches(void)
 	/* Avoid random hang when download by usb */
 	invalidate_dcache_all();
 
+	/* Set ACTLR.SMP bit for Cortex-A7 */
+	enable_ca7_smp();
+
 	/* Enable D-cache. I-cache is already enabled in start.S */
 	dcache_enable();
 
@@ -31,6 +62,17 @@ void enable_caches(void)
 					IRAM_SIZE,
 					option);
 }
+#else
+void enable_caches(void)
+{
+	/*
+	 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are
+	 * disabled by u-boot
+	 */
+	enable_ca7_smp();
+
+	puts("WARNING: Caches not enabled\n");
+}
 #endif
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 06322b2aaac..3654670442f 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -8,9 +8,11 @@ config MX5
 config MX51
 	bool
 	select SYS_FSL_ERRATUM_ESDHC_A001
+	select ARM_CORTEX_A8_CVE_2017_5715
 
 config MX53
 	bool
+	select ARM_CORTEX_A8_CVE_2017_5715
 
 choice
 	prompt "MX5 board select"
@@ -27,11 +29,6 @@ config TARGET_KP_IMX53
 	select DM_GPIO
 	select DM_PMIC
 
-config TARGET_M53EVK
-	bool "Support m53evk"
-	select MX53
-	select SUPPORT_SPL
-
 config TARGET_MX51EVK
 	bool "Support mx51evk"
 	select BOARD_LATE_INIT
@@ -81,7 +78,6 @@ endchoice
 config SYS_SOC
 	default "mx5"
 
-source "board/aries/m53evk/Kconfig"
 source "board/beckhoff/mx53cx9020/Kconfig"
 source "board/freescale/mx51evk/Kconfig"
 source "board/freescale/mx53ard/Kconfig"
diff --git a/arch/arm/mach-imx/mx5/Makefile b/arch/arm/mach-imx/mx5/Makefile
index 1fc9c96aaab..40d1998637c 100644
--- a/arch/arm/mach-imx/mx5/Makefile
+++ b/arch/arm/mach-imx/mx5/Makefile
@@ -9,6 +9,5 @@ obj-y := soc.o clock.o
 obj-y += lowlevel_init.o
 
 # common files for mx53 dram initialization
-obj-$(CONFIG_TARGET_M53EVK)     += mx53_dram.o
 obj-$(CONFIG_TARGET_MX53CX9020) += mx53_dram.o
 obj-$(CONFIG_TARGET_MX53LOCO)   += mx53_dram.o
diff --git a/arch/arm/mach-imx/mx6/mp.c b/arch/arm/mach-imx/mx6/mp.c
index c3806dca3ad..eda168d8671 100644
--- a/arch/arm/mach-imx/mx6/mp.c
+++ b/arch/arm/mach-imx/mx6/mp.c
@@ -29,20 +29,20 @@ static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
 	SRC_SCR_CORE_3_ENABLE_MASK
 };
 
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
 {
 	/* Software reset of the CPU N */
 	src->scr |= cpu_reset_mask[nr];
 	return 0;
 }
 
-int cpu_status(int nr)
+int cpu_status(u32 nr)
 {
 	printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
 	return 0;
 }
 
-int cpu_release(int nr, int argc, char *const argv[])
+int cpu_release(u32 nr, int argc, char *const argv[])
 {
 	uint32_t boot_addr;
 
@@ -78,7 +78,7 @@ int is_core_valid(unsigned int core)
 	return 1;
 }
 
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
 {
 	/* Disable the CPU N */
 	src->scr &= ~cpu_ctrl_mask[nr];
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index f1dea66d60d..2aca24bbb0f 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -280,13 +280,6 @@ const struct boot_mode soc_boot_modes[] = {
 
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD
-	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
-	asm volatile(
-			"mrc p15, 0, r0, c1, c0, 1\n"
-			"orr r0, r0, #1 << 6\n"
-			"mcr p15, 0, r0, c1, c0, 1\n");
-#endif
 	/* clock configuration. */
 	clock_init();
 
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig
index 684d49e5db2..68072d5a1f2 100644
--- a/arch/arm/mach-imx/mxs/Kconfig
+++ b/arch/arm/mach-imx/mxs/Kconfig
@@ -50,9 +50,6 @@ config TARGET_APX4DEVKIT
 config TARGET_BG0900
 	bool "Support bg0900"
 
-config TARGET_M28EVK
-	bool "Support m28evk"
-
 config TARGET_MX28EVK
 	bool "Support mx28evk"
 	select BOARD_EARLY_INIT_F
@@ -68,7 +65,6 @@ endchoice
 config SYS_SOC
 	default "mxs"
 
-source "board/aries/m28evk/Kconfig"
 source "board/bluegiga/apx4devkit/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
 source "board/ppcag/bg0900/Kconfig"