7 files changed, 37 insertions, 9 deletions
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h
index 214c1d3a836..74de6202fe5 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h
@@ -12,8 +12,8 @@
 
 #define PLLSET_CMD_LIST		"<pa|arm|ddr3>"
 
-#define DEV_SUPPORTED_SPEEDS	0xfff
-#define ARM_SUPPORTED_SPEEDS	0xfff
+#define DEV_SUPPORTED_SPEEDS	0x1ff
+#define ARM_SUPPORTED_SPEEDS	0xff
 
 #define KS2_CLK1_6 sys_clk0_6_clk
 
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index cdcff3baee3..72724aa4a91 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -63,8 +63,12 @@
 #define CLOCK_INDEXES_LIST	CLK_LIST(GENERATE_INDX_STR)
 
 enum {
+	SPD200,
+	SPD400,
+	SPD600,
 	SPD800,
 	SPD850,
+	SPD900,
 	SPD1000,
 	SPD1200,
 	SPD1250,
@@ -124,8 +128,8 @@ struct pll_init_data *get_pll_init_data(int pll);
 unsigned long clk_get_rate(unsigned int clk);
 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
-int get_max_dev_speed(void);
-int get_max_arm_speed(void);
+int get_max_dev_speed(int *spds);
+int get_max_arm_speed(int *spds);
 void pll_pa_clk_sel(void);
 
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/ddr3.h b/arch/arm/mach-keystone/include/mach/ddr3.h
index a22c237c802..5feffe825b9 100644
--- a/arch/arm/mach-keystone/include/mach/ddr3.h
+++ b/arch/arm/mach-keystone/include/mach/ddr3.h
@@ -48,6 +48,14 @@ struct ddr3_emif_config {
 	unsigned int sdrfc;
 };
 
+struct ddr3_spd_cb {
+	char   dimm_name[32];
+	struct ddr3_phy_config phy_cfg;
+	struct ddr3_emif_config emif_cfg;
+	unsigned int ddrspdclock;
+	int    ddr_size_gbyte;
+};
+
 u32 ddr3_init(void);
 void ddr3_reset_ddrphy(void);
 void ddr3_init_ecc(u32 base, u32 ddr3_size);
@@ -58,5 +66,6 @@ void ddr3_err_reset_workaround(void);
 void ddr3_enable_ecc(u32 base, int test);
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+int ddr3_get_size(void);
 
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index fa4162fe996..ca2a119d390 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -10,7 +10,7 @@
 #ifndef __ASM_ARCH_HARDWARE_K2G_H
 #define __ASM_ARCH_HARDWARE_K2G_H
 
-#define KS2_NUM_DSPS	0
+#define KS2_NUM_DSPS			1
 
 /* Power and Sleep Controller (PSC) Domains */
 #define KS2_LPSC_ALWAYSON		0
@@ -30,7 +30,10 @@
 #define KS2_LPSC_MCASP			15
 #define KS2_LPSC_SR			16
 #define KS2_LPSC_MSMC			17
-#define KS2_LPSC_GEM			18
+#ifdef KS2_LPSC_GEM_0
+#undef KS2_LPSC_GEM_0
+#endif
+#define KS2_LPSC_GEM_0			18
 #define KS2_LPSC_ARM			19
 #define KS2_LPSC_ASRC			20
 #define KS2_LPSC_ICSS			21
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2l.h b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
index 4f1197ea923..a59e0713593 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
@@ -105,4 +105,11 @@
 /* NETCP */
 #define KS2_NETCP_BASE			0x26000000
 
+#ifndef __ASSEMBLY__
+static inline int ddr3_get_size(void)
+{
+	return 2;
+}
+#endif
+
 #endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index edebcd7bc58..8ca19bbcdbe 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -160,6 +160,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_LPSC_GEM_0			15
 #define KS2_LPSC_TETRIS			52
 #define KS2_TETRIS_PWR_DOMAIN		31
+#define KS2_GEM_0_PWR_DOMAIN		8
 
 /* Chip configuration unlock codes and registers */
 #define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h
index 70d22cf2178..6e6e7fd433a 100644
--- a/arch/arm/mach-keystone/include/mach/psc_defs.h
+++ b/arch/arm/mach-keystone/include/mach/psc_defs.h
@@ -30,9 +30,9 @@
 #define BOOTBITMASK(x, y)     ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
 				  (u32)1)) << ((u32)y)))
 
-#define BOOT_READ_BITFIELD(z, x, y)    (((u32)z) & BOOTBITMASK(x, y)) >> (y)
-#define BOOT_SET_BITFIELD(z, f, x, y)  (((u32)z) & ~BOOTBITMASK(x, y)) | \
-					 ((((u32)f) << (y)) & BOOTBITMASK(x, y))
+#define BOOT_READ_BITFIELD(z, x, y)    ((((u32)z) & BOOTBITMASK(x, y)) >> (y))
+#define BOOT_SET_BITFIELD(z, f, x, y)  ((((u32)z) & ~BOOTBITMASK(x, y)) | \
+					((((u32)f) << (y)) & BOOTBITMASK(x, y)))
 
 /* PDCTL */
 #define PSC_REG_PDCTL_SET_NEXT(x, y)        BOOT_SET_BITFIELD((x), (y), 0, 0)
@@ -56,6 +56,8 @@
 #define PSC_REG_MDSTAT_GET_STATUS(x)        BOOT_READ_BITFIELD((x), 5, 0)
 #define PSC_REG_MDSTAT_GET_LRSTZ(x)         BOOT_READ_BITFIELD((x), 8, 8)
 #define PSC_REG_MDSTAT_GET_LRSTDONE(x)      BOOT_READ_BITFIELD((x), 9, 9)
+#define PSC_REG_MDSTAT_GET_MRSTZ(x)         BOOT_READ_BITFIELD((x), 10, 10)
+#define PSC_REG_MDSTAT_GET_MRSTDONE(x)      BOOT_READ_BITFIELD((x), 11, 11)
 
 /* PDCTL states */
 #define PSC_REG_VAL_PDCTL_NEXT_ON           1
@@ -86,5 +88,7 @@ u32 psc_get_domain_num(u32 mod_num);
 int psc_enable_module(u32 mod_num);
 int psc_disable_module(u32 mod_num);
 int psc_disable_domain(u32 domain_num);
+int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks);
+int psc_module_release_from_reset(u32 mod_num);
 
 #endif /* _PSC_DEFS_H_ */