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-rw-r--r--arch/arm/mach-rockchip/rk3588/Kconfig18
-rw-r--r--arch/arm/mach-rockchip/rk3588/rk3588.c8
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 4e7942ada87..9fbe3f225aa 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588
- 3.5mm Headphone out, 2.0mm PH-2A Mic in
- 5V Fan connector, PWM beeper, IR receiver, RTC battery connector
+config TARGET_GAMEFORCE_ACE_RK3588S
+ bool "GameForce Ace"
+ help
+ The GameForce Ace is a handheld game console from GameForce with
+ the Rockchip RK3588S SoC.
+
+ Hardware features:
+ - Rockchip RK3588S SoC
+ - 12GB LPDDR4x RAM
+ - 128GB eMMC
+ - MicroSD card slot
+ - 1x USB 3.0 Type-C with DP AltMode support
+ - 1x HDMI 2.1 micro-HDMI out
+ - 1920x1080 touchscreen MIPI-DSI panel
+ - Analog joysticks and L/R triggers
+ - 16 digital buttons
+
config TARGET_GENBOOK_CM5_RK3588
bool "Cool Pi CM5 GenBook"
help
@@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
+source "board/gameforce/ace-rk3588s/Kconfig"
source "board/hardkernel/odroid_m2/Kconfig"
source "board/indiedroid/nova/Kconfig"
source "board/khadas/khadas-edge2-rk3588s/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index e2278ff792b..c01a4002089 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -15,6 +15,10 @@
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/ioc_rk3588.h>
+#define USB_GRF_BASE 0xfd5ac000
+#define USB3OTG0_CON1 0x001c
+#define USB3OTG1_CON1 0x0034
+
#define FIREWALL_DDR_BASE 0xfe030000
#define FW_DDR_MST5_REG 0x54
#define FW_DDR_MST13_REG 0x74
@@ -184,6 +188,10 @@ int arch_cpu_init(void)
/* Disable JTAG exposed on SDMMC */
rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
#endif
+
+ /* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */
+ writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+ writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1);
#endif
return 0;