diff options
Diffstat (limited to 'arch/arm/mach-rockchip')
47 files changed, 1180 insertions, 2225 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 1090d21879c..e337d06b999 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -7,6 +7,7 @@ config ROCKCHIP_RK3036 select SPL imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB + imply ROCKCHIP_COMMON_BOARD help The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -16,6 +17,7 @@ config ROCKCHIP_RK3036 config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A + imply ROCKCHIP_COMMON_BOARD help The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -34,8 +36,10 @@ config ROCKCHIP_RK3188 select SPL_RAM select SPL_DRIVERS_MISC_SUPPORT select SPL_ROCKCHIP_EARLYRETURN_TO_BROM + select SPL_ROCKCHIP_BACK_TO_BROM select BOARD_LATE_INIT - select ROCKCHIP_BROM_HELPER + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD help The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two @@ -57,9 +61,11 @@ config ROCKCHIP_RK322X select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_DRIVERS_MISC_SUPPORT + imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL_SUPPORT + imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL_SUPPORT - select ROCKCHIP_BROM_HELPER + imply TPL_ROCKCHIP_COMMON_BOARD select TPL_LIBCOMMON_SUPPORT select TPL_LIBGENERIC_SUPPORT help @@ -68,27 +74,14 @@ config ROCKCHIP_RK322X and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. -if ROCKCHIP_RK322X - -config TPL_TEXT_BASE - default 0x10081000 - -config TPL_MAX_SIZE - default 28672 - -config TPL_STACK - default 0x10088000 - -endif - config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A - select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL select SUPPORT_TPL - imply TPL_BOOTROM_SUPPORT + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_CLK imply TPL_DM imply TPL_DRIVERS_MISC_SUPPORT @@ -100,6 +93,7 @@ config ROCKCHIP_RK3288 imply TPL_OF_PLATDATA imply TPL_RAM imply TPL_REGMAP + imply TPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL_SUPPORT imply TPL_SYSCON imply USB_FUNCTION_ROCKUSB @@ -111,24 +105,13 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. -if ROCKCHIP_RK3288 - -config TPL_TEXT_BASE - default 0xff704000 - -config TPL_MAX_SIZE - default 32768 - -config TPL_STACK - default 0xff718000 - -endif - config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 select SUPPORT_SPL select SPL + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SERIAL_SUPPORT imply SPL_SEPARATE_BSS select ENABLE_ARM_SOC_BOOT0_HOOK @@ -148,9 +131,12 @@ config ROCKCHIP_RK3368 select SUPPORT_TPL select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT + imply TPL_ROCKCHIP_COMMON_BOARD help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised into a big and little cluster with 4 cores each) Cortex-A53 including @@ -162,19 +148,6 @@ config ROCKCHIP_RK3368 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. -if ROCKCHIP_RK3368 - -config TPL_TEXT_BASE - default 0xff8c1000 - -config TPL_MAX_SIZE - default 28672 - -config TPL_STACK - default 0xff8cffff - -endif - config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 @@ -204,13 +177,12 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT - select ROCKCHIP_BROM_HELPER + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL_SUPPORT imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE - imply TPL_BOARD_INIT - imply TPL_BOOTROM_SUPPORT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_OF_CONTROL imply TPL_DM @@ -219,6 +191,7 @@ config ROCKCHIP_RK3399 imply TPL_RAM imply TPL_CLK imply TPL_TINY_MEMSET + imply TPL_ROCKCHIP_COMMON_BOARD help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -227,25 +200,10 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. -if ROCKCHIP_RK3399 - -config TPL_LDSCRIPT - default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" - -config TPL_TEXT_BASE - default 0xff8c2000 - -config TPL_MAX_SIZE - default 188416 - -config TPL_STACK - default 0xff8effff - -endif - config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A + imply ROCKCHIP_COMMON_BOARD help The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. @@ -262,6 +220,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 select ROCKCHIP_BROM_HELPER + select SPL_BOOTROM_SUPPORT depends on SPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, @@ -272,22 +231,39 @@ config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" default y select ROCKCHIP_BROM_HELPER + select TPL_BOOTROM_SUPPORT depends on TPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, SPL will return to the boot rom, which will then load the U-Boot binary to keep going on. +config ROCKCHIP_COMMON_BOARD + bool "Rockchip common board file" + help + Rockchip SoCs have similar boot process, Common board file is mainly + in charge of common process of board_init() and board_late_init() for + U-Boot proper. + +config SPL_ROCKCHIP_COMMON_BOARD + bool "Rockchip SPL common board file" + depends on SPL + help + Rockchip SoCs have similar boot process, SPL is mainly in charge of + load and boot Trust ATF/U-Boot firmware, and DRAM init if there is + no TPL for the board. + +config TPL_ROCKCHIP_COMMON_BOARD + bool "" + depends on TPL + help + Rockchip SoCs have similar boot process, prefer to use TPL for DRAM + init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL + common board is a basic TPL board init which can be shared for most + of SoCs to avoid copy-pase for different SoCs. + config ROCKCHIP_BOOT_MODE_REG hex "Rockchip boot mode flag register address" - default 0x200081c8 if ROCKCHIP_RK3036 - default 0x20004040 if ROCKCHIP_RK3188 - default 0x110005c8 if ROCKCHIP_RK322X - default 0xff730094 if ROCKCHIP_RK3288 - default 0xff738200 if ROCKCHIP_RK3368 - default 0xff320300 if ROCKCHIP_RK3399 - default 0x10300580 if ROCKCHIP_RV1108 - default 0 help The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 23760a959ae..aed379a0dc6 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -7,20 +7,11 @@ # inaccessible/protected memory (and the bootrom-helper assumes that # the stack-pointer is valid before switching to the U-Boot stack). obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o +obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o - -obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o -obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o +obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o -obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o -obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) @@ -29,24 +20,11 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o - -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o -obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o -obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o +obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o -ifndef CONFIG_ARM64 -ifndef CONFIG_ROCKCHIP_RK3188 -obj-y += rk_timer.o -endif -endif - obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/board.c index e6ea0e9a6ae..b2a88e789d8 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/board.c @@ -1,20 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. */ - #include <common.h> #include <clk.h> #include <dm.h> #include <ram.h> -#include <asm/gpio.h> +#include <syscon.h> #include <asm/io.h> +#include <asm/arch-rockchip/boot_mode.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/grf_rk3036.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <asm/arch-rockchip/sdram_rk3036.h> -#include <dm/pinctrl.h> +#include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; @@ -32,23 +29,18 @@ int board_late_init(void) int board_init(void) { - return 0; -} + int ret; -#if !CONFIG_IS_ENABLED(RAM) -/* - * When CONFIG_RAM is enabled, the dram_init() function is implemented - * in sdram_common.c. - */ -int dram_init(void) -{ - gd->ram_size = sdram_size(); +#ifdef CONFIG_DM_REGULATOR + ret = regulators_enable_boot_on(false); + if (ret) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif return 0; } -#endif -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ @@ -60,7 +52,7 @@ void enable_caches(void) #include <usb.h> #include <usb/dwc2_udc.h> -static struct dwc2_plat_otg_data rk3036_otg_data = { +static struct dwc2_plat_otg_data otg_data = { .rx_fifo_sz = 512, .np_tx_fifo_sz = 16, .tx_fifo_sz = 128, @@ -74,8 +66,7 @@ int board_usb_init(int index, enum usb_init_type init) const void *blob = gd->fdt_blob; /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); + node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); while (node > 0) { mode = fdt_getprop(blob, node, "dr_mode", NULL); @@ -84,16 +75,15 @@ int board_usb_init(int index, enum usb_init_type init) break; } - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); + node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2"); } if (!matched) { debug("Not found usb_otg device\n"); return -ENODEV; } - rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - return dwc2_udc_probe(&rk3036_otg_data); + return dwc2_udc_probe(&otg_data); } int board_usb_cleanup(int index, enum usb_init_type init) @@ -101,3 +91,14 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } #endif + +#if CONFIG_IS_ENABLED(FASTBOOT) +int fastboot_set_reboot_flag(void) +{ + printf("Setting reboot to fastboot flag ...\n"); + /* Set boot mode to fastboot */ + writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/fit_spl_optee.its b/arch/arm/mach-rockchip/fit_spl_optee.its index 9be4b3c8d2f..6ed5d486f2e 100644 --- a/arch/arm/mach-rockchip/fit_spl_optee.its +++ b/arch/arm/mach-rockchip/fit_spl_optee.its @@ -11,7 +11,7 @@ #address-cells = <1>; images { - uboot@1 { + uboot { description = "U-Boot"; data = /incbin/("../../../u-boot-nodtb.bin"); type = "standalone"; @@ -20,7 +20,7 @@ compression = "none"; load = <0x61000000>; }; - optee@1 { + optee { description = "OP-TEE"; data = /incbin/("../../../tee.bin"); type = "firmware"; @@ -30,7 +30,7 @@ load = <0x68400000>; entry = <0x68400000>; }; - fdt@1 { + fdt { description = "dtb"; data = /incbin/("../../../u-boot.dtb"); type = "flat_dt"; @@ -39,12 +39,12 @@ }; configurations { - default = "conf@1"; - conf@1 { + default = "conf"; + conf { description = "Rockchip armv7 with OP-TEE"; - firmware = "optee@1"; - loadables = "uboot@1"; - fdt = "fdt@1"; + firmware = "optee"; + loadables = "uboot"; + fdt = "fdt"; }; }; }; diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index db0ae96ca84..b9a19882984 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -13,16 +13,7 @@ import os import sys import getopt import logging - -# pip install pyelftools -from elftools.elf.elffile import ELFFile - -ELF_SEG_P_TYPE = 'p_type' -ELF_SEG_P_PADDR = 'p_paddr' -ELF_SEG_P_VADDR = 'p_vaddr' -ELF_SEG_P_OFFSET = 'p_offset' -ELF_SEG_P_FILESZ = 'p_filesz' -ELF_SEG_P_MEMSZ = 'p_memsz' +import struct DT_HEADER = """ /* @@ -118,33 +109,19 @@ def append_conf_node(file, dtbs, segments): file.write('\n') def generate_atf_fit_dts_uboot(fit_file, uboot_file_name): - num_load_seg = 0 - p_paddr = 0xFFFFFFFF - with open(uboot_file_name, 'rb') as uboot_file: - uboot = ELFFile(uboot_file) - for i in range(uboot.num_segments()): - seg = uboot.get_segment(i) - if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD': - p_paddr = seg.__getitem__(ELF_SEG_P_PADDR) - num_load_seg = num_load_seg + 1 - - assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1) - + segments = unpack_elf(uboot_file_name) + if len(segments) != 1: + raise ValueError("Invalid u-boot ELF image '%s'" % uboot_file_name) + index, entry, p_paddr, data = segments[0] fit_file.write(DT_UBOOT % p_paddr) def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name): - with open(bl31_file_name, 'rb') as bl31_file: - bl31 = ELFFile(bl31_file) - elf_entry = bl31.header['e_entry'] - segments = bl31.num_segments() - for i in range(segments): - seg = bl31.get_segment(i) - if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD': - paddr = seg.__getitem__(ELF_SEG_P_PADDR) - append_bl31_node(fit_file, i + 1, paddr, elf_entry) + segments = unpack_elf(bl31_file_name) + for index, entry, paddr, data in segments: + append_bl31_node(fit_file, index + 1, paddr, entry) append_fdt_node(fit_file, dtbs_file_name) fit_file.write(DT_IMAGES_NODE_END) - append_conf_node(fit_file, dtbs_file_name, segments) + append_conf_node(fit_file, dtbs_file_name, len(segments)) def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name): # Generate FIT script for ATF image. @@ -162,17 +139,29 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_fi fit_file.close() def generate_atf_binary(bl31_file_name): - with open(bl31_file_name, 'rb') as bl31_file: - bl31 = ELFFile(bl31_file) - - num = bl31.num_segments() - for i in range(num): - seg = bl31.get_segment(i) - if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD': - paddr = seg.__getitem__(ELF_SEG_P_PADDR) - file_name = 'bl31_0x%08x.bin' % paddr - with open(file_name, "wb") as atf: - atf.write(seg.data()) + for index, entry, paddr, data in unpack_elf(bl31_file_name): + file_name = 'bl31_0x%08x.bin' % paddr + with open(file_name, "wb") as atf: + atf.write(data) + +def unpack_elf(filename): + with open(filename, 'rb') as file: + elf = file.read() + if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00': + raise ValueError("Invalid arm64 ELF file '%s'" % filename) + + e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18) + e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36) + segments = [] + + for index in range(e_phnum): + offset = e_phoff + e_phentsize * index + p_type, p_flags, p_offset = struct.unpack_from('<LLQ', elf, offset) + if p_type == 1: # PT_LOAD + p_paddr, p_filesz = struct.unpack_from('<2Q', elf, offset + 0x18) + p_data = elf[p_offset:p_offset + p_filesz] + segments.append((index, e_entry, p_paddr, p_data)) + return segments def main(): uboot_elf = "./u-boot" diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 110d06dba5e..fbc89b66c47 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * (C) Copyright 2015-2019 Rockchip Electronics Co., Ltd */ #include <common.h> @@ -8,14 +8,37 @@ #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/sdram_rk3036.h> -#include <asm/arch-rockchip/timer.h> + +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) + +void rockchip_stimer_init(void) +{ + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} void board_init_f(ulong dummy) { #ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif - rockchip_timer_init(); + + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); + sdram_init(); /* return to maskrom */ diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 5e04d204482..51cd43b396f 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -1,5 +1,8 @@ if ROCKCHIP_RK3036 +choice + prompt "RK3036 board select" + config TARGET_EVB_RK3036 bool "EVB_RK3036" select BOARD_LATE_INIT @@ -8,6 +11,11 @@ config TARGET_KYLIN_RK3036 bool "KYLIN_RK3036" select BOARD_LATE_INIT +endchoice + +config ROCKCHIP_BOOT_MODE_REG + default 0x200081c8 + config SYS_SOC default "rk3036" diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c index 481af8a9344..be458cfb642 100644 --- a/arch/arm/mach-rockchip/rk3036/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -5,6 +5,9 @@ #include <asm/io.h> #include <asm/arch-rockchip/grf_rk3036.h> #include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/sdram_rk3036.h> + +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) @@ -36,3 +39,16 @@ void board_debug_uart_init(void) GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); } #endif + +#if !CONFIG_IS_ENABLED(RAM) +/* + * When CONFIG_RAM is enabled, the dram_init() function is implemented + * in sdram_common.c. + */ +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 1d940a0d77c..c39cbb8111a 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -9,7 +9,6 @@ #include <asm/arch-rockchip/grf_rk3036.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/sdram_rk3036.h> -#include <asm/arch-rockchip/timer.h> #include <asm/arch-rockchip/uart.h> /* @@ -345,7 +344,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv) /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) - rockchip_udelay(1); + udelay(1); /* PLL enter normal-mode */ rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, @@ -373,25 +372,25 @@ void phy_pctrl_reset(struct rk3036_sdram_priv *priv) 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); clrsetbits_le32(&ddr_phy->ddrphy_reg1, SOFT_RESET_MASK << SOFT_RESET_SHIFT, 0 << SOFT_RESET_SHIFT); - rockchip_udelay(10); + udelay(10); clrsetbits_le32(&ddr_phy->ddrphy_reg1, SOFT_RESET_MASK << SOFT_RESET_SHIFT, 3 << SOFT_RESET_SHIFT); - rockchip_udelay(1); + udelay(1); } void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq) @@ -444,7 +443,7 @@ static void send_command(struct rk3036_ddr_pctl *pctl, u32 rank, u32 cmd, u32 arg) { writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); - rockchip_udelay(1); + udelay(1); while (readl(&pctl->mcmd) & START_CMD) ; } @@ -454,7 +453,7 @@ static void memory_init(struct rk3036_sdram_priv *priv) struct rk3036_ddr_pctl *pctl = priv->pctl; send_command(pctl, 3, DESELECT_CMD, 0); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, PREA_CMD, 0); send_command(pctl, 3, MRS_CMD, (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | @@ -492,7 +491,7 @@ static void data_training(struct rk3036_sdram_priv *priv) clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START); - rockchip_udelay(1); + udelay(1); while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) { ; diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c deleted file mode 100644 index fa71685af80..00000000000 --- a/arch/arm/mach-rockchip/rk3128-board.c +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/grf_rk3128.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <asm/arch-rockchip/timer.h> -#include <power/regulator.h> - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - setup_boot_mode(); - - return rk_board_late_init(); -} - -int board_init(void) -{ - int ret = 0; - - rockchip_timer_init(); - - ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulator\n", __func__); - return ret; - } - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; - /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0xe00000; - gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start - + gd->ram_size - gd->bd->bi_dram[1].start; - - return 0; -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rk3128_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3128-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3128-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3128_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -#if CONFIG_IS_ENABLED(FASTBOOT) -int fastboot_set_reboot_flag(void) -{ - struct rk3128_grf *grf; - - printf("Setting reboot to fastboot flag ...\n"); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - /* Set boot mode to fastboot */ - writel(BOOT_FASTBOOT, &grf->os_reg[0]); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index a82b7dc063f..b867401c7f5 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -13,6 +13,9 @@ config TARGET_EVB_RK3128 endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0x100a0038 + config SYS_SOC default "rk3128" diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c index 11bba148c33..ee176de80b0 100644 --- a/arch/arm/mach-rockchip/rk3128/rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/rk3128.c @@ -2,6 +2,9 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; int arch_cpu_init(void) { diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c deleted file mode 100644 index 77b9b36d357..00000000000 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <clk.h> -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <fdtdec.h> -#include <led.h> -#include <malloc.h> -#include <ram.h> -#include <spl.h> -#include <syscon.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/grf_rk3188.h> -#include <asm/arch-rockchip/hardware.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/pmu_rk3188.h> -#include <asm/arch-rockchip/sdram.h> -#include <asm/arch-rockchip/timer.h> -#include <dm/pinctrl.h> -#include <dm/root.h> -#include <dm/test.h> -#include <dm/util.h> -#include <power/regulator.h> - -DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - const void *blob = gd->fdt_blob; - struct udevice *dev; - const char *bootdev; - int node; - int ret; - - bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); - debug("Boot device %s\n", bootdev); - if (!bootdev) - goto fallback; - - node = fdt_path_offset(blob, bootdev); - if (node < 0) { - debug("node=%d\n", node); - goto fallback; - } - ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev); - if (ret) { - debug("device at node %s/%d not found: %d\n", bootdev, node, - ret); - goto fallback; - } - debug("Found device %s\n", dev->name); - switch (device_get_uclass_id(dev)) { - case UCLASS_SPI_FLASH: - return BOOT_DEVICE_SPI; - case UCLASS_MMC: - return BOOT_DEVICE_MMC1; - default: - debug("Booting from device uclass '%s' not supported\n", - dev_get_uclass_name(dev)); - } - -fallback: -#endif - return BOOT_DEVICE_MMC1; -} - -static int setup_arm_clock(void) -{ - struct udevice *dev; - struct clk clk; - int ret; - - ret = rockchip_get_clk(&dev); - if (ret) - return ret; - - clk.id = CLK_ARM; - ret = clk_request(dev, &clk); - if (ret < 0) - return ret; - - ret = clk_set_rate(&clk, 600000000); - - clk_free(&clk); - return ret; -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("U-Boot SPL board init"); -#endif - -#ifdef CONFIG_ROCKCHIP_USB_UART - rk_clrsetreg(&grf->uoc0_con[0], - SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK, - 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT | - 1 << COMMON_ON_N_SHIFT); - rk_clrsetreg(&grf->uoc0_con[2], - SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT); - rk_clrsetreg(&grf->uoc0_con[3], - OPMODE_MASK | XCVRSELECT_MASK | - TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK, - OPMODE_NODRIVING << OPMODE_SHIFT | - XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT | - 1 << TERMSEL_FULLSPEED_SHIFT | - 1 << SUSPENDN_SHIFT); - rk_clrsetreg(&grf->uoc0_con[0], - BYPASSSEL_MASK | BYPASSDMEN_MASK, - 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } - - setup_arm_clock(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} - -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_on(dev, 1); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - int ret; - - ret = setup_led(); - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } - - preloader_console_init(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif - return; -} diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c deleted file mode 100644 index 80d8c4241ec..00000000000 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/grf_rk3188.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/pmu_rk3288.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <dm/pinctrl.h> - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - struct rk3188_grf *grf; - - setup_boot_mode(); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - if (IS_ERR(grf)) { - pr_err("grf syscon returned %ld\n", PTR_ERR(grf)); - } else { - /* enable noc remap to mimic legacy loaders */ - rk_clrsetreg(&grf->soc_con0, - NOC_REMAP_MASK << NOC_REMAP_SHIFT, - NOC_REMAP_MASK << NOC_REMAP_SHIFT); - } - - return rk_board_late_init(); -} - -int board_init(void) -{ -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - struct udevice *pinctrl; - int ret; - - /* - * We need to implement sdcard iomux here for the further - * initialization, otherwise, it'll hit sdcard command sending - * timeout exception. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - - return 0; -err: - printf("board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); - - return -1; -#else - return 0; -#endif -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index a6fc691fb6c..e24e68ea518 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -9,6 +9,9 @@ config TARGET_ROCK Expansion connectors provide access to display pins, I2C, SPI, UART and GPIOs. +config ROCKCHIP_BOOT_MODE_REG + default 0x20004040 + config SYS_SOC default "rk3188" diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 933484e0df9..95f0e3ccbea 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -3,15 +3,25 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ #include <common.h> +#include <dm.h> +#include <syscon.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/grf_rk3188.h> #include <asm/arch-rockchip/hardware.h> +#define GRF_BASE 0x20008000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "dwmmc@1021c000", + [BROM_BOOTSOURCE_SD] = "dwmmc@10214000", +}; + #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; enum { GPIO1B1_SHIFT = 2, @@ -34,3 +44,77 @@ void board_debug_uart_init(void) GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); } #endif + +#ifdef CONFIG_SPL_BUILD +int arch_cpu_init(void) +{ + struct rk3188_grf *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(grf)) { + pr_err("grf syscon returned %ld\n", PTR_ERR(grf)); + return 0; + } +#ifdef CONFIG_ROCKCHIP_USB_UART + rk_clrsetreg(&grf->uoc0_con[0], + SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK, + 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT | + 1 << COMMON_ON_N_SHIFT); + rk_clrsetreg(&grf->uoc0_con[2], + SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT); + rk_clrsetreg(&grf->uoc0_con[3], + OPMODE_MASK | XCVRSELECT_MASK | + TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK, + OPMODE_NODRIVING << OPMODE_SHIFT | + XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT | + 1 << TERMSEL_FULLSPEED_SHIFT | + 1 << SUSPENDN_SHIFT); + rk_clrsetreg(&grf->uoc0_con[0], + BYPASSSEL_MASK | BYPASSDMEN_MASK, + 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT); +#endif + + /* enable noc remap to mimic legacy loaders */ + rk_clrsetreg(&grf->soc_con0, + NOC_REMAP_MASK << NOC_REMAP_SHIFT, + NOC_REMAP_MASK << NOC_REMAP_SHIFT); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +static int setup_led(void) +{ +#ifdef CONFIG_SPL_LED + struct udevice *dev; + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + ret = led_set_on(dev, 1); + if (ret) + return ret; +#endif + + return 0; +} + +void spl_board_init(void) +{ + int ret; + + ret = setup_led(); + if (ret) { + debug("LED ret=%d\n", ret); + hang(); + } +} +#endif diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c deleted file mode 100644 index c9b41c62c08..00000000000 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <dm.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch-rockchip/hardware.h> - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -u32 spl_boot_mode(const u32 boot_device) -{ - return MMCSD_MODE_RAW; -} - -#define SGRF_DDR_CON0 0x10150000 -void board_init_f(ulong dummy) -{ - int ret; - - ret = spl_early_init(); - if (ret) { - printf("spl_early_init() failed: %d\n", ret); - hang(); - } - preloader_console_init(); - - /* Disable the ddr secure region setting to make it non-secure */ - rk_clrreg(SGRF_DDR_CON0, 0x4000); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c deleted file mode 100644 index 92d40ee43ae..00000000000 --- a/arch/arm/mach-rockchip/rk322x-board-tpl.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/timer.h> - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("TPL Init"); - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - rockchip_timer_init(); - printf("timer init done\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - printf("DRAM init failed: %d\n", ret); - return; - } - -#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c deleted file mode 100644 index e7a1e54874d..00000000000 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/grf_rk322x.h> -#include <asm/arch-rockchip/periph.h> - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - setup_boot_mode(); - - return rk_board_late_init(); -} - -int board_init(void) -{ -#include <asm/arch-rockchip/grf_rk322x.h> - /* Enable early UART2 channel 1 on the RK322x */ -#define GRF_BASE 0x11000000 - static struct rk322x_grf * const grf = (void *)GRF_BASE; - - /* - * The integrated macphy is enabled by default, disable it - * for saving power consuming. - */ - rk_clrsetreg(&grf->macphy_con[0], - MACPHY_CFG_ENABLE_MASK, - 0 << MACPHY_CFG_ENABLE_SHIFT); - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; - /* Reserve 0x200000 for OPTEE */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0x200000; - gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start - + gd->ram_size - gd->bd->bi_dram[1].start; - - return 0; -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rk322x_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk322x_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -#if CONFIG_IS_ENABLED(FASTBOOT) -int fastboot_set_reboot_flag(void) -{ - struct rk322x_grf *grf; - - printf("Setting reboot to fastboot flag ...\n"); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - /* Set boot mode to fastboot */ - writel(BOOT_FASTBOOT, &grf->os_reg[0]); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 8a1f95f7859..2fc6f6ea3ec 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -1,18 +1,37 @@ if ROCKCHIP_RK322X + config TARGET_EVB_RK3229 bool "EVB_RK3229" select BOARD_LATE_INIT +config ROCKCHIP_BOOT_MODE_REG + default 0x110005c8 + config SYS_SOC default "rk322x" config SYS_MALLOC_F_LEN - default 0x400 + default 0x800 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y config SPL_SERIAL_SUPPORT default y +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0x10088000 + +config TPL_TEXT_BASE + default 0x10081000 + source "board/rockchip/evb_rk3229/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index e5250bc7848..cd0bf8a70cc 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -3,9 +3,15 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk322x.h> #include <asm/arch-rockchip/hardware.h> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "dwmmc@30020000", + [BROM_BOOTSOURCE_SD] = "dwmmc@30000000", +}; + #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { @@ -42,3 +48,26 @@ void board_debug_uart_init(void) CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); } #endif + +int arch_cpu_init(void) +{ +#ifdef CONFIG_SPL_BUILD +#define SGRF_BASE 0x10150000 + static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE; + + /* Disable the ddr secure region setting to make it non-secure */ + rk_clrreg(&sgrf->soc_con[0], 0x4000); +#else +#define GRF_BASE 0x11000000 + static struct rk322x_grf * const grf = (void *)GRF_BASE; + /* + * The integrated macphy is enabled by default, disable it + * for saving power consuming. + */ + rk_clrsetreg(&grf->macphy_con[0], + MACPHY_CFG_ENABLE_MASK, + 0 << MACPHY_CFG_ENABLE_SHIFT); + +#endif + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c deleted file mode 100644 index d8d215db8a0..00000000000 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <fdtdec.h> -#include <i2c.h> -#include <led.h> -#include <malloc.h> -#include <ram.h> -#include <spl.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/hardware.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/pmu_rk3288.h> -#include <asm/arch-rockchip/sdram.h> -#include <asm/arch-rockchip/sdram_common.h> -#include <asm/arch-rockchip/sys_proto.h> -#include <asm/arch-rockchip/timer.h> -#include <dm/pinctrl.h> -#include <dm/root.h> -#include <dm/test.h> -#include <dm/util.h> -#include <power/regulator.h> -#include <power/rk8xx_pmic.h> - -DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - const void *blob = gd->fdt_blob; - struct udevice *dev; - const char *bootdev; - int node; - int ret; - - bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); - debug("Boot device %s\n", bootdev); - if (!bootdev) - goto fallback; - - node = fdt_path_offset(blob, bootdev); - if (node < 0) { - debug("node=%d\n", node); - goto fallback; - } - ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev); - if (ret) { - debug("device at node %s/%d not found: %d\n", bootdev, node, - ret); - goto fallback; - } - debug("Found device %s\n", dev->name); - switch (device_get_uclass_id(dev)) { - case UCLASS_SPI_FLASH: - return BOOT_DEVICE_SPI; - case UCLASS_MMC: - return BOOT_DEVICE_MMC1; - default: - debug("Booting from device uclass '%s' not supported\n", - dev_get_uclass_name(dev)); - } - -fallback: -#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ - defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ - defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) - return BOOT_DEVICE_SPI; -#endif - return BOOT_DEVICE_MMC1; -} - -#if !defined(CONFIG_SPL_OF_PLATDATA) -static int phycore_init(void) -{ - struct udevice *pmic; - int ret; - - ret = uclass_first_device_err(UCLASS_PMIC, &pmic); - if (ret) - return ret; - -#if defined(CONFIG_SPL_POWER_SUPPORT) - /* Increase USB input current to 2A */ - ret = rk818_spl_configure_usb_input_current(pmic, 2000); - if (ret) - return ret; - - /* Close charger when USB lower then 3.26V */ - ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000); - if (ret) - return ret; -#endif - - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - debug("\nspl:debug uart enabled in %s\n", __func__); -#endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - rockchip_timer_init(); - configure_l2ctlr(); - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - -#if !defined(CONFIG_SPL_OF_PLATDATA) - if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { - ret = phycore_init(); - if (ret) { - debug("Failed to set up phycore power settings: %d\n", - ret); - return; - } - } -#endif - -#if !defined(CONFIG_SUPPORT_TPL) - debug("\nspl:init dram\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -#endif - -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} - -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_on(dev, 1); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - int ret; - - ret = setup_led(); - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } - - preloader_console_init(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif - return; -} - -#ifdef CONFIG_SPL_OS_BOOT - -#define PMU_BASE 0xff730000 -int dram_init_banksize(void) -{ - struct rk3288_pmu *const pmu = (void *)PMU_BASE; - size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]); - - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = size; - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c deleted file mode 100644 index 787129bbaea..00000000000 --- a/arch/arm/mach-rockchip/rk3288-board-tpl.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Amarula Solutions - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <version.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/sys_proto.h> -#include <asm/arch-rockchip/timer.h> - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); -#endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - rockchip_timer_init(); - configure_l2ctlr(); - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \ - U_BOOT_TIME ")\n"); -} diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c deleted file mode 100644 index e2de5b2fddb..00000000000 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ /dev/null @@ -1,347 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3288.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/pmu_rk3288.h> -#include <asm/arch-rockchip/qos_rk3288.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <asm/gpio.h> -#include <dm/pinctrl.h> -#include <dt-bindings/clock/rk3288-cru.h> -#include <power/regulator.h> - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int rk3288_qos_init(void) -{ - int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; - /* set vop qos to higher priority */ - writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); - - if (!fdt_node_check_compatible(gd->fdt_blob, 0, - "rockchip,rk3288-tinker")) - { - /* set isp qos to higher priority */ - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); - } - return 0; -} - -static void rk3288_detect_reset_reason(void) -{ - struct rk3288_cru *cru = rockchip_get_cru(); - const char *reason; - - if (IS_ERR(cru)) - return; - - switch (cru->cru_glb_rst_st) { - case GLB_POR_RST: - reason = "POR"; - break; - case FST_GLB_RST_ST: - case SND_GLB_RST_ST: - reason = "RST"; - break; - case FST_GLB_TSADC_RST_ST: - case SND_GLB_TSADC_RST_ST: - reason = "THERMAL"; - break; - case FST_GLB_WDT_RST_ST: - case SND_GLB_WDT_RST_ST: - reason = "WDOG"; - break; - default: - reason = "unknown reset"; - } - - env_set("reset_reason", reason); - - /* - * Clear cru_glb_rst_st, so we can determine the last reset cause - * for following resets. - */ - rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); -} - -int board_late_init(void) -{ - setup_boot_mode(); - rk3288_qos_init(); - rk3288_detect_reset_reason(); - - return rk_board_late_init(); -} - -#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) -static int veyron_init(void) -{ - struct udevice *dev; - struct clk clk; - int ret; - - ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) { - debug("Cannot set regulator name\n"); - return ret; - } - - /* Slowly raise to max CPU voltage to prevent overshoot */ - ret = regulator_set_value(dev, 1200000); - if (ret) - return ret; - udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ - ret = regulator_set_value(dev, 1400000); - if (ret) - return ret; - udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ - - ret = rockchip_get_clk(&clk.dev); - if (ret) - return ret; - clk.id = PLL_APLL; - ret = clk_set_rate(&clk, 1800000000); - if (IS_ERR_VALUE(ret)) - return ret; - - ret = regulator_get_by_platname("vcc33_sd", &dev); - if (ret) { - debug("Cannot get regulator name\n"); - return ret; - } - - ret = regulator_set_value(dev, 3300000); - if (ret) - return ret; - - ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulators\n", __func__); - return ret; - } - - return 0; -} -#endif - -int board_init(void) -{ -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - struct udevice *pinctrl; - int ret; - - /* - * We need to implement sdcard iomux here for the further - * initlization, otherwise, it'll hit sdcard command sending - * timeout exception. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - - return 0; -err: - printf("board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); - - return -1; -#else - int ret; - - /* We do some SoC one time setting here */ - if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { - ret = veyron_init(); - if (ret) - return ret; - } - - return 0; -#endif -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rk3288_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node, phy_node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - u32 grf_phy_offset; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - node = fdtdec_lookup_phandle(blob, node, "phys"); - if (node <= 0) { - debug("Not found usb phy device\n"); - return -ENODEV; - } - - phy_node = fdt_parent_offset(blob, node); - if (phy_node <= 0) { - debug("Not found usb phy device\n"); - return -ENODEV; - } - - rk3288_otg_data.phy_of_node = phy_node; - grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); - - /* find the grf node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-grf"); - if (node <= 0) { - debug("Not found grf device\n"); - return -ENODEV; - } - rk3288_otg_data.regs_phy = grf_phy_offset + - fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3288_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - static const struct { - char *name; - int id; - } clks[] = { - { "osc", CLK_OSC }, - { "apll", CLK_ARM }, - { "dpll", CLK_DDR }, - { "cpll", CLK_CODEC }, - { "gpll", CLK_GENERAL }, -#ifdef CONFIG_ROCKCHIP_RK3036 - { "mpll", CLK_NEW }, -#else - { "npll", CLK_NEW }, -#endif - }; - int ret, i; - struct udevice *dev; - - ret = rockchip_get_clk(&dev); - if (ret) { - printf("clk-uclass not found\n"); - return 0; - } - - for (i = 0; i < ARRAY_SIZE(clks); i++) { - struct clk clk; - ulong rate; - - clk.id = clks[i].id; - ret = clk_request(dev, &clk); - if (ret < 0) - continue; - - rate = clk_get_rate(&clk); - printf("%s: %lu\n", clks[i].name, rate); - - clk_free(&clk); - } - - return 0; -} - -U_BOOT_CMD( - clock, 2, 1, do_clock, - "display information about clocks", - "" -); - -int board_early_init_f(void) -{ - const uintptr_t GRF_SOC_CON0 = 0xff770244; - const uintptr_t GRF_SOC_CON2 = 0xff77024c; - struct udevice *dev; - int ret; - - /* - * This init is done in SPL, but when chain-loading U-Boot SPL will - * have been skipped. Allow the clock driver to check if it needs - * setting up. - */ - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return ret; - } - - rk_setreg(GRF_SOC_CON2, 1 << 0); - - /* - * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is - * cleared - */ - rk_clrreg(GRF_SOC_CON0, 1 << 12); - - return 0; -} diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index c5dcd061cfd..87d0786ba8d 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -1,5 +1,8 @@ if ROCKCHIP_RK3288 +choice + prompt "RK3288 board select" + config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" select BOARD_LATE_INIT @@ -44,6 +47,7 @@ config TARGET_CHROMEBOOK_SPEEDY config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT + select TPL help EVB-RK3288 is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It @@ -62,6 +66,7 @@ config TARGET_FENNEC_RK3288 config TARGET_FIREFLY_RK3288 bool "Firefly-RK3288" select BOARD_LATE_INIT + select SPL_BOARD_INIT if SPL help Firefly is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It @@ -80,6 +85,7 @@ config TARGET_MIQI_RK3288 config TARGET_PHYCORE_RK3288 bool "phyCORE-RK3288" select BOARD_LATE_INIT + select SPL_BOARD_INIT if SPL help Add basic support for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. This board works in a combination @@ -125,6 +131,8 @@ config TARGET_TINKER_RK3288 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to I2C, SPI, UART, GPIOs. +endchoice + config ROCKCHIP_FAST_SPL bool "Change the CPU to full speed in SPL" depends on TARGET_CHROMEBOOK_JERRY @@ -134,11 +142,14 @@ config ROCKCHIP_FAST_SPL voltage. This option is only available on boards which support it and have the required PMIC code. +config ROCKCHIP_BOOT_MODE_REG + default 0xff730094 + config SYS_SOC default "rk3288" config SYS_MALLOC_F_LEN - default 0x0800 + default 0x2000 config SPL_DRIVERS_MISC_SUPPORT default y @@ -152,6 +163,18 @@ config SPL_LIBGENERIC_SUPPORT config SPL_SERIAL_SUPPORT default y +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl.lds" + +config TPL_MAX_SIZE + default 32768 + +config TPL_STACK + default 0xff718000 + +config TPL_TEXT_BASE + default 0xff704000 + source "board/amarula/vyasa-rk3288/Kconfig" source "board/chipspark/popmetal_rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 7941ca68a64..b462c090699 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -2,20 +2,88 @@ /* * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <asm/armv7.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/qos_rk3288.h> +#include <asm/arch-rockchip/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xff770000 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000", +}; + +#ifdef CONFIG_SPL_BUILD +static void configure_l2ctlr(void) +{ + u32 l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} +#endif + +int rk3288_qos_init(void) +{ + int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; + /* set vop qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); + + if (!fdt_node_check_compatible(gd->fdt_blob, 0, + "rockchip,rk3288-tinker")) { + /* set isp qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); + } + + return 0; +} + int arch_cpu_init(void) { +#ifdef CONFIG_SPL_BUILD + configure_l2ctlr(); +#else /* We do some SoC one time setting here. */ struct rk3288_grf * const grf = (void *)GRF_BASE; /* Use rkpwm by default */ rk_setreg(&grf->soc_con2, 1 << 0); + /* + * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is + * cleared + */ + rk_clrreg(&grf->soc_con0, 1 << 12); + + rk3288_qos_init(); +#endif + return 0; } @@ -31,3 +99,103 @@ void board_debug_uart_init(void) GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); } #endif + +static void rk3288_detect_reset_reason(void) +{ + struct rk3288_cru *cru = rockchip_get_cru(); + const char *reason; + + if (IS_ERR(cru)) + return; + + switch (cru->cru_glb_rst_st) { + case GLB_POR_RST: + reason = "POR"; + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + reason = "RST"; + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + reason = "THERMAL"; + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + reason = "WDOG"; + break; + default: + reason = "unknown reset"; + } + + env_set("reset_reason", reason); + + /* + * Clear cru_glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); +} + +__weak int rk3288_board_late_init(void) +{ + return 0; +} + +int rk_board_late_init(void) +{ + rk3288_detect_reset_reason(); + + return rk3288_board_late_init(); +} + +static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + static const struct { + char *name; + int id; + } clks[] = { + { "osc", CLK_OSC }, + { "apll", CLK_ARM }, + { "dpll", CLK_DDR }, + { "cpll", CLK_CODEC }, + { "gpll", CLK_GENERAL }, +#ifdef CONFIG_ROCKCHIP_RK3036 + { "mpll", CLK_NEW }, +#else + { "npll", CLK_NEW }, +#endif + }; + int ret, i; + struct udevice *dev; + + ret = rockchip_get_clk(&dev); + if (ret) { + printf("clk-uclass not found\n"); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(clks); i++) { + struct clk clk; + ulong rate; + + clk.id = clks[i].id; + ret = clk_request(dev, &clk); + if (ret < 0) + continue; + + rate = clk_get_rate(&clk); + printf("%s: %lu\n", clks[i].name, rate); + + clk_free(&clk); + } + + return 0; +} + +U_BOOT_CMD( + clock, 2, 1, do_clock, + "display information about clocks", + "" +); diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c deleted file mode 100644 index 7f49d056a07..00000000000 --- a/arch/arm/mach-rockchip/rk3328-board-spl.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <dm/pinctrl.h> -#include <ram.h> -#include <spl.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -void board_debug_uart_init(void) -{ -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - preloader_console_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -u32 spl_boot_mode(const u32 boot_device) -{ - return MMCSD_MODE_RAW; -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index 6c5c4303a35..f8e15288e0b 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -12,11 +12,20 @@ config TARGET_EVB_RK3328 endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0xff1005c8 + config SYS_SOC default "rk3328" config SYS_MALLOC_F_LEN - default 0x0800 + default 0x2000 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y source "board/rockchip/evb_rk3328/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index 1cf829dc343..592f287613b 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -4,12 +4,24 @@ */ #include <common.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3328.h> +#include <asm/arch-rockchip/uart.h> #include <asm/armv8/mmu.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; +#define CRU_BASE 0xFF440000 +#define GRF_BASE 0xFF100000 +#define UART2_BASE 0xFF130000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000", + [BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000", +}; + static struct mm_region rk3328_mem_map[] = { { .virt = 0x0UL, @@ -32,20 +44,52 @@ static struct mm_region rk3328_mem_map[] = { struct mm_region *mem_map = rk3328_mem_map; -int dram_init_banksize(void) +int arch_cpu_init(void) { - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); - - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; + /* We do some SoC one time setting here. */ return 0; } -int arch_cpu_init(void) +void board_debug_uart_init(void) { - /* We do some SoC one time setting here. */ + struct rk3328_grf_regs * const grf = (void *)GRF_BASE; + struct rk_uart * const uart = (void *)UART2_BASE; + enum{ + GPIO2A0_SEL_SHIFT = 0, + GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, + GPIO2A0_UART2_TX_M1 = 1, - return 0; + GPIO2A1_SEL_SHIFT = 2, + GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, + GPIO2A1_UART2_RX_M1 = 1, + }; + enum { + IOMUX_SEL_UART2_SHIFT = 0, + IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, + IOMUX_SEL_UART2_M0 = 0, + IOMUX_SEL_UART2_M1, + }; + + /* uart_sel_clk default select 24MHz */ + writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148); + + /* init uart baud rate 1500000 */ + writel(0x83, &uart->lcr); + writel(0x1, &uart->rbr); + writel(0x3, &uart->lcr); + + /* Enable early UART2 */ + rk_clrsetreg(&grf->com_iomux, + IOMUX_SEL_UART2_MASK, + IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A0_SEL_MASK, + GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A1_SEL_MASK, + GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT); + + /* enable FIFO */ + writel(0x1, &uart->sfe); } diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c deleted file mode 100644 index c6511937123..00000000000 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch-rockchip/periph.h> - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - preloader_console_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c deleted file mode 100644 index dc65a021c81..00000000000 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3368.h> -#include <asm/arch-rockchip/hardware.h> -#include <asm/arch-rockchip/timer.h> - -/* - * The SPL (and also the full U-Boot stage on the RK3368) will run in - * secure mode (i.e. EL3) and an ATF will eventually be booted before - * starting up the operating system... so we can initialize the SGRF - * here and rely on the ATF installing the final (secure) policy - * later. - */ -static inline uintptr_t sgrf_soc_con_addr(unsigned no) -{ - const uintptr_t SGRF_BASE = - (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - - return SGRF_BASE + sizeof(u32) * no; -} - -static inline uintptr_t sgrf_busdmac_addr(unsigned no) -{ - const uintptr_t SGRF_BASE = - (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; - const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; - - return SGRF_BUSDMAC_BASE + sizeof(u32) * no; -} - -static void sgrf_init(void) -{ - struct rk3368_cru * const cru = - (struct rk3368_cru * const)rockchip_get_cru(); - const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); - const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); - const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); - - /* Set all configurable IP to 'non secure'-mode */ - rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); - rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); - rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); - - /* - * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c - * Original comment: "ddr space set no secure mode" - */ - rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); - rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); - rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); - - /* Set 'secure dma' to 'non secure'-mode */ - rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); - rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); - - dsb(); /* barrier */ - - rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); - rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); - - dsb(); /* barrier */ - udelay(10); - - rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); - rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("U-Boot TPL board init\n"); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* Reset security, so we can use DMA in the MMC drivers */ - sgrf_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 325572a7e40..d6ca5f1d244 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -42,9 +42,21 @@ config TARGET_EVB_PX5 sensor STK3410. endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0xff738200 + config SYS_SOC default "rk3368" +config SYS_MALLOC_F_LEN + default 0x2000 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" @@ -53,4 +65,13 @@ source "board/rockchip/evb_px5/Kconfig" config SPL_LDSCRIPT default "arch/arm/cpu/armv8/u-boot-spl.lds" +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0xff8cffff + +config TPL_TEXT_BASE + default 0xff8c1000 + endif diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index f06d27717de..7ccd417a18c 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -5,12 +5,14 @@ */ #include <common.h> +#include <syscon.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_rk3368.h> #include <asm/arch-rockchip/grf_rk3368.h> -#include <syscon.h> +#include <asm/arch-rockchip/hardware.h> DECLARE_GLOBAL_DATA_PTR; @@ -51,16 +53,10 @@ static struct mm_region rk3368_mem_map[] = { struct mm_region *mem_map = rk3368_mem_map; -int dram_init_banksize(void) -{ - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); - - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; - - return 0; -} +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000", +}; #ifdef CONFIG_ARCH_EARLY_INIT_R static int mcu_init(void) @@ -97,6 +93,78 @@ int arch_early_init_r(void) } #endif +#ifdef CONFIG_SPL_BUILD +/* + * The SPL (and also the full U-Boot stage on the RK3368) will run in + * secure mode (i.e. EL3) and an ATF will eventually be booted before + * starting up the operating system... so we can initialize the SGRF + * here and rely on the ATF installing the final (secure) policy + * later. + */ +static inline uintptr_t sgrf_soc_con_addr(unsigned int no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + + return SGRF_BASE + sizeof(u32) * no; +} + +static inline uintptr_t sgrf_busdmac_addr(unsigned int no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; + const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; + + return SGRF_BUSDMAC_BASE + sizeof(u32) * no; +} + +static void sgrf_init(void) +{ + struct rk3368_cru * const cru = + (struct rk3368_cru * const)rockchip_get_cru(); + const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); + const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); + const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); + + /* Set all configurable IP to 'non secure'-mode */ + rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); + + /* + * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c + * Original comment: "ddr space set no secure mode" + */ + rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); + + /* Set 'secure dma' to 'non secure'-mode */ + rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); + rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); + + dsb(); /* barrier */ + + rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); + + dsb(); /* barrier */ + udelay(10); + + rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); +} + +int arch_cpu_init(void) +{ + /* Reset security, so we can use DMA in the MMC drivers */ + sgrf_init(); + + return 0; +} +#endif + #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c deleted file mode 100644 index 890d80025f6..00000000000 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <spl_gpio.h> -#include <syscon.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> -#include <asm/arch-rockchip/grf_rk3399.h> -#include <asm/arch-rockchip/hardware.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/sys_proto.h> -#include <power/regulator.h> -#include <dm/pinctrl.h> - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", - [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", -}; - -const char *board_spl_was_booted_from(void) -{ - u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR); - const char *bootdevice_ofpath = NULL; - - if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) - bootdevice_ofpath = boot_devices[bootdevice_brom_id]; - - if (bootdevice_ofpath) - debug("%s: brom_bootdevice_id %x maps to '%s'\n", - __func__, bootdevice_brom_id, bootdevice_ofpath); - else - debug("%s: failed to resolve brom_bootdevice_id %x\n", - __func__, bootdevice_brom_id); - - return bootdevice_ofpath; -} - -u32 spl_boot_device(void) -{ - u32 boot_device = BOOT_DEVICE_MMC1; - - if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) - return BOOT_DEVICE_BOOTROM; - - return boot_device; -} - -const char *spl_decode_boot_device(u32 boot_device) -{ - int i; - static const struct { - u32 boot_device; - const char *ofpath; - } spl_boot_devices_tbl[] = { - { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" }, - { BOOT_DEVICE_MMC2, "/sdhci@fe330000" }, - { BOOT_DEVICE_SPI, "/spi@ff1d0000" }, - }; - - for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i) - if (spl_boot_devices_tbl[i].boot_device == boot_device) - return spl_boot_devices_tbl[i].ofpath; - - return NULL; -} - -void spl_perform_fixups(struct spl_image_info *spl_image) -{ - void *blob = spl_image->fdt_addr; - const char *boot_ofpath; - int chosen; - - /* - * Inject the ofpath of the device the full U-Boot (or Linux in - * Falcon-mode) was booted from into the FDT, if a FDT has been - * loaded at the same time. - */ - if (!blob) - return; - - boot_ofpath = spl_decode_boot_device(spl_image->boot_device); - if (!boot_ofpath) { - pr_err("%s: could not map boot_device to ofpath\n", __func__); - return; - } - - chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); - if (chosen < 0) { - pr_err("%s: could not find/create '/chosen'\n", __func__); - return; - } - fdt_setprop_string(blob, chosen, - "u-boot,spl-boot-device", boot_ofpath); -} - -#define TIMER_CHN10_BASE 0xff8680a0 -#define TIMER_END_COUNT_L 0x00 -#define TIMER_END_COUNT_H 0x04 -#define TIMER_INIT_COUNT_L 0x10 -#define TIMER_INIT_COUNT_H 0x14 -#define TIMER_CONTROL_REG 0x1c - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) -{ - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); - writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); -} - - -void board_init_f(ulong dummy) -{ - struct udevice *pinctrl; - struct udevice *dev; - struct rk3399_pmusgrf_regs *sgrf; - struct rk3399_grf_regs *grf; - int ret; - -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); - -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB - int sum, i; - - /* - * Add a delay and ensure that the compiler does not optimise this out. - * This is needed since the power rails tail a while to turn on, and - * we get garbage serial output otherwise. - */ - sum = 0; - for (i = 0; i < 150000; i++) - sum += i; - gru_dummy_function(sum); -#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ - - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug("U-Boot SPL board init\n"); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* - * Disable DDR and SRAM security regions. - * - * As we are entered from the BootROM, the region from - * 0x0 through 0xfffff (i.e. the first MB of memory) will - * be protected. This will cause issues with the DW_MMC - * driver, which tries to DMA from/to the stack (likely) - * located in this range. - */ - sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); - rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); - rk_clrreg(&sgrf->slv_secure_con4, 0x2000); - - /* eMMC clock generator: disable the clock multipilier */ - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - rk_clrreg(&grf->emmccore_con[11], 0x0ff); - - secure_timer_init(); - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - pr_err("Pinctrl init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - pr_err("DRAM init failed: %d\n", ret); - return; - } -} - -#if defined(SPL_GPIO_SUPPORT) -static void rk3399_force_power_on_reset(void) -{ - ofnode node; - struct gpio_desc sysreset_gpio; - - debug("%s: trying to force a power-on reset\n", __func__); - - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - debug("%s: no /config node?\n", __func__); - return; - } - - if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, - &sysreset_gpio, GPIOD_IS_OUT)) { - debug("%s: could not find a /config/sysreset-gpio\n", __func__); - return; - } - - dm_gpio_set_value(&sysreset_gpio, 1); -} -#endif - -void spl_board_init(void) -{ -#if defined(SPL_GPIO_SUPPORT) - struct rk3399_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the TRM - * "3.9.4 Global software reset"), when issuing a software reset. - * This may cause issues during boot-up for some configurations of - * the application software stack. - * - * To work around this, we test whether the last reset reason was - * a power-on reset and (if not) issue an overtemp-reset to reset - * the entire module. - * - * While this was previously fixed by modifying the various places - * that could generate a software reset (e.g. U-Boot's sysreset - * driver, the ATF or Linux), we now have it here to ensure that - * we no longer have to track this through the various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); -#endif - -#if defined(SPL_DM_REGULATOR) - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - if (regulators_enable_boot_on(false)) - debug("%s: Cannot enable boot on regulator\n", __func__); -#endif - - preloader_console_init(); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c deleted file mode 100644 index 4a301249b49..00000000000 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <version.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> - -#define TIMER_CHN10_BASE 0xff8680a0 -#define TIMER_END_COUNT_L 0x00 -#define TIMER_END_COUNT_H 0x04 -#define TIMER_INIT_COUNT_L 0x10 -#define TIMER_INIT_COUNT_H 0x14 -#define TIMER_CONTROL_REG 0x1c - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) -{ - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); - writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug("U-Boot TPL board init\n"); -#endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - secure_timer_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - pr_err("DRAM init failed: %d\n", ret); - return; - } -} - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " - U_BOOT_TIME " " U_BOOT_TZ ")\n"); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c deleted file mode 100644 index 443c87cccce..00000000000 --- a/arch/arm/mach-rockchip/rk3399-board.c +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2017 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <asm/arch-rockchip/boot_mode.h> - -int board_late_init(void) -{ - setup_boot_mode(); - return 0; -} diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 2c5c93c0b85..6660d05349b 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -64,11 +64,32 @@ config TARGET_CHROMEBOOK_BOB endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0xff320300 + config SYS_SOC default "rk3399" config SYS_MALLOC_F_LEN - default 0x0800 + default 0x4000 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" + +config TPL_MAX_SIZE + default 188416 + +config TPL_STACK + default 0xff8effff + +config TPL_TEXT_BASE + default 0xff8c2000 source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index e1f9f8b8efe..863024d0710 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -4,18 +4,29 @@ */ #include <common.h> +#include <spl.h> #include <spl_gpio.h> +#include <syscon.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/gpio.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> +#include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; #define GRF_EMMCCORE_CON11 0xff77f02c #define GRF_BASE 0xff770000 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", +}; + static struct mm_region rk3399_mem_map[] = { { .virt = 0x0UL, @@ -38,24 +49,59 @@ static struct mm_region rk3399_mem_map[] = { struct mm_region *mem_map = rk3399_mem_map; -int dram_init_banksize(void) +#ifdef CONFIG_SPL_BUILD + +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) { - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; + if (reg & TIMER_EN) + return; - return 0; + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H); + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L); + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \ + TIMER_CONTROL_REG); } +#endif int arch_cpu_init(void) { - /* We do some SoC one time setting here. */ - struct rk3399_grf_regs * const grf = (void *)GRF_BASE; - /* Emmc clock generator: disable the clock multipilier */ +#ifdef CONFIG_SPL_BUILD + struct rk3399_pmusgrf_regs *sgrf; + struct rk3399_grf_regs *grf; + + /* + * Disable DDR and SRAM security regions. + * + * As we are entered from the BootROM, the region from + * 0x0 through 0xfffff (i.e. the first MB of memory) will + * be protected. This will cause issues with the DW_MMC + * driver, which tries to DMA from/to the stack (likely) + * located in this range. + */ + sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); + rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); + rk_clrreg(&sgrf->slv_secure_con4, 0x2000); + + /* eMMC clock generator: disable the clock multipilier */ + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); rk_clrreg(&grf->emmccore_con[11], 0x0ff); +#endif return 0; } @@ -117,3 +163,111 @@ void board_debug_uart_init(void) #endif } #endif + +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +const char *spl_decode_boot_device(u32 boot_device) +{ + int i; + static const struct { + u32 boot_device; + const char *ofpath; + } spl_boot_devices_tbl[] = { + { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" }, + { BOOT_DEVICE_MMC2, "/sdhci@fe330000" }, + { BOOT_DEVICE_SPI, "/spi@ff1d0000" }, + }; + + for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i) + if (spl_boot_devices_tbl[i].boot_device == boot_device) + return spl_boot_devices_tbl[i].ofpath; + + return NULL; +} + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + void *blob = spl_image->fdt_addr; + const char *boot_ofpath; + int chosen; + + /* + * Inject the ofpath of the device the full U-Boot (or Linux in + * Falcon-mode) was booted from into the FDT, if a FDT has been + * loaded at the same time. + */ + if (!blob) + return; + + boot_ofpath = spl_decode_boot_device(spl_image->boot_device); + if (!boot_ofpath) { + pr_err("%s: could not map boot_device to ofpath\n", __func__); + return; + } + + chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); + if (chosen < 0) { + pr_err("%s: could not find/create '/chosen'\n", __func__); + return; + } + fdt_setprop_string(blob, chosen, + "u-boot,spl-boot-device", boot_ofpath); +} + +#if defined(SPL_GPIO_SUPPORT) +static void rk3399_force_power_on_reset(void) +{ + ofnode node; + struct gpio_desc sysreset_gpio; + + debug("%s: trying to force a power-on reset\n", __func__); + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + + if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, + &sysreset_gpio, GPIOD_IS_OUT)) { + debug("%s: could not find a /config/sysreset-gpio\n", __func__); + return; + } + + dm_gpio_set_value(&sysreset_gpio, 1); +} +#endif + +void spl_board_init(void) +{ +#if defined(SPL_GPIO_SUPPORT) + struct rk3399_cru *cru = rockchip_get_cru(); + + /* + * The RK3399 resets only 'almost all logic' (see also in the TRM + * "3.9.4 Global software reset"), when issuing a software reset. + * This may cause issues during boot-up for some configurations of + * the application software stack. + * + * To work around this, we test whether the last reset reason was + * a power-on reset and (if not) issue an overtemp-reset to reset + * the entire module. + * + * While this was previously fixed by modifying the various places + * that could generate a software reset (e.g. U-Boot's sysreset + * driver, the ATF or Linux), we now have it here to ensure that + * we no longer have to track this through the various components. + */ + if (cru->glb_rst_st != 0) + rk3399_force_power_on_reset(); +#endif + +#if defined(SPL_DM_REGULATOR) + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index a8bb5b11e56..259ca44d68f 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -13,6 +13,7 @@ static const struct udevice_id rk3399_syscon_ids[] = { { .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, { .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF }, { .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC }, + { .compatible = "rockchip,rk3399-pmu", .data = ROCKCHIP_SYSCON_PMU }, { } }; @@ -58,4 +59,11 @@ U_BOOT_DRIVER(rockchip_rk3399_cic) = { .of_match = rk3399_syscon_ids + 3, .bind = rk3399_syscon_bind_of_platdata, }; + +U_BOOT_DRIVER(rockchip_rk3399_pmu) = { + .name = "rockchip_rk3399_pmu", + .id = UCLASS_SYSCON, + .of_match = rk3399_syscon_ids + 4, + .bind = rk3399_syscon_bind_of_platdata, +}; #endif diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c deleted file mode 100644 index 29d379fa0ab..00000000000 --- a/arch/arm/mach-rockchip/rk_timer.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <asm/arch-rockchip/timer.h> -#include <asm/io.h> -#include <linux/types.h> - -struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE; - -static uint64_t rockchip_get_ticks(void) -{ - uint64_t timebase_h, timebase_l; - - timebase_l = readl(&timer_ptr->timer_curr_value0); - timebase_h = readl(&timer_ptr->timer_curr_value1); - - return timebase_h << 32 | timebase_l; -} - -void rockchip_udelay(unsigned int usec) -{ - uint64_t tmp; - - /* get timestamp */ - tmp = rockchip_get_ticks() + usec_to_tick(usec); - - /* loop till event */ - while (rockchip_get_ticks() < tmp+1) - ; -} - -void rockchip_timer_init(void) -{ - writel(0xffffffff, &timer_ptr->timer_load_count0); - writel(0xffffffff, &timer_ptr->timer_load_count1); - writel(1, &timer_ptr->timer_ctrl_reg); -} diff --git a/arch/arm/mach-rockchip/rv1108-board.c b/arch/arm/mach-rockchip/rv1108-board.c deleted file mode 100644 index 3412f2c063a..00000000000 --- a/arch/arm/mach-rockchip/rv1108-board.c +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <common.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rv1108_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - const void *blob = gd->fdt_blob; - bool matched = false; - int node, phy_node; - u32 grf_phy_offset; - const char *mode; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb"); - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3066-usb"); - } - - if (!matched) { - debug("usb_otg device not found\n"); - return -ENODEV; - } - - rv1108_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - node = fdtdec_lookup_phandle(blob, node, "phys"); - if (node <= 0) { - debug("phys node not found\n"); - return -ENODEV; - } - - phy_node = fdt_parent_offset(blob, node); - if (phy_node <= 0) { - debug("usb phy node not found\n"); - return -ENODEV; - } - - rv1108_otg_data.phy_of_node = phy_node; - grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); - - /* find the grf node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rv1108-grf"); - if (node <= 0) { - debug("grf node not found\n"); - return -ENODEV; - } - - rv1108_otg_data.regs_phy = grf_phy_offset + fdtdec_get_addr(blob, node, - "reg"); - - return dwc2_udc_probe(&rv1108_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index e3a63b80e13..a12216dccf6 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -1,5 +1,8 @@ if ROCKCHIP_RV1108 +choice + prompt "RV1108 board select" + config TARGET_EVB_RV1108 bool "EVB_RV1108" help @@ -22,6 +25,11 @@ config TARGET_ELGIN_RV1108 help RV1108 ELGIN is a board based on the Rockchip RV1108. +endchoice + +config ROCKCHIP_BOOT_MODE_REG + default 0x10300580 + config SYS_SOC default "rv1108" diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c index 66aeb3ffcc9..6362af995bc 100644 --- a/arch/arm/mach-rockchip/rv1108/rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/rv1108.c @@ -3,13 +3,3 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd * Author: Andy Yan <andy.yan@rock-chips.com> */ - -#include <common.h> - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 8684dbd4fa6..22a4aca9402 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -11,6 +11,69 @@ #include <dm/uclass-internal.h> DECLARE_GLOBAL_DATA_PTR; + +#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024) + +struct tos_parameter_t { + u32 version; + u32 checksum; + struct { + char name[8]; + s64 phy_addr; + u32 size; + u32 flags; + } tee_mem; + struct { + char name[8]; + s64 phy_addr; + u32 size; + u32 flags; + } drm_mem; + s64 reserve[8]; +}; + +int dram_init_banksize(void) +{ + size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + gd->ram_top); + +#ifdef CONFIG_ARM64 + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; +#else +#ifdef CONFIG_SPL_OPTEE + struct tos_parameter_t *tos_parameter; + + tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + TRUST_PARAMETER_OFFSET); + + if (tos_parameter->tee_mem.flags == 1) { + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + - CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + tos_parameter->tee_mem.size; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + top - gd->bd->bi_dram[1].start; + } else { + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8400000; + /* Reserve 32M for OPTEE with TA */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + + gd->bd->bi_dram[0].size + 0x2000000; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + top - gd->bd->bi_dram[1].start; + } +#else + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; +#endif +#endif + + return 0; +} + size_t rockchip_sdram_size(phys_addr_t reg) { u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 0e485deda2f..c19c285c070 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -8,7 +8,7 @@ #include <mmc.h> #include <spl.h> -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_LIBFDT) /** * spl_node_to_boot_device() - maps from a DT-node to a SPL boot device * @node: of_offset of the node diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c new file mode 100644 index 00000000000..33137cc5ef4 --- /dev/null +++ b/arch/arm/mach-rockchip/spl.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { +}; + +const char *board_spl_was_booted_from(void) +{ + u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); + const char *bootdevice_ofpath = NULL; + + if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) + bootdevice_ofpath = boot_devices[bootdevice_brom_id]; + + if (bootdevice_ofpath) + debug("%s: brom_bootdevice_id %x maps to '%s'\n", + __func__, bootdevice_brom_id, bootdevice_ofpath); + else + debug("%s: failed to resolve brom_bootdevice_id %x\n", + __func__, bootdevice_brom_id); + + return bootdevice_ofpath; +} + +u32 spl_boot_device(void) +{ + u32 boot_device = BOOT_DEVICE_MMC1; + +#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ + defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + return BOOT_DEVICE_SPI; +#endif + if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) + return BOOT_DEVICE_BOOTROM; + + return boot_device; +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +#if !defined(CONFIG_ROCKCHIP_RK3188) +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +__weak void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; +#ifndef CONFIG_ARM64 + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); +#endif + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} +#endif + +__weak int board_early_init_f(void) +{ + return 0; +} + +__weak int arch_cpu_init(void) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; +#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT) + struct udevice *dev; +#endif + +#ifdef CONFIG_DEBUG_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + debug("\nspl:debug uart enabled in %s\n", __func__); +#endif + + board_early_init_f(); + + ret = spl_early_init(); + if (ret) { + printf("spl_early_init() failed: %d\n", ret); + hang(); + } + arch_cpu_init(); +#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT) + debug("\nspl:init dram\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } +#endif +#if !defined(CONFIG_ROCKCHIP_RK3188) + rockchip_stimer_init(); +#endif +#ifdef CONFIG_SYS_ARCH_TIMER + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); +#endif + preloader_console_init(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c new file mode 100644 index 00000000000..55f6e922d0a --- /dev/null +++ b/arch/arm/mach-rockchip/tpl.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> + +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +__weak void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + +#ifndef CONFIG_ARM64 + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); +#endif + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT) + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); +#ifdef CONFIG_TPL_BANNER_PRINT + printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \ + U_BOOT_TIME ")\n"); +#endif +#endif + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/ */ + timer_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} |