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-rw-r--r--arch/arm/mach-socfpga/Makefile2
-rw-r--r--arch/arm/mach-socfpga/board.c6
-rw-r--r--arch/arm/mach-socfpga/clock_manager.c2
-rw-r--r--arch/arm/mach-socfpga/clock_manager_arria10.c2
-rw-r--r--arch/arm/mach-socfpga/include/mach/boot0.h2
-rw-r--r--arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h2
-rw-r--r--arch/arm/mach-socfpga/lowlevel_init_soc64.S2
-rw-r--r--arch/arm/mach-socfpga/mailbox_s10.c2
-rw-r--r--arch/arm/mach-socfpga/misc.c2
-rw-r--r--arch/arm/mach-socfpga/misc_arria10.c2
-rw-r--r--arch/arm/mach-socfpga/misc_gen5.c2
-rw-r--r--arch/arm/mach-socfpga/reset_manager_s10.c2
-rw-r--r--arch/arm/mach-socfpga/secure_vab.c2
-rw-r--r--arch/arm/mach-socfpga/timer_s10.c4
-rw-r--r--arch/arm/mach-socfpga/wrap_pll_config_soc64.c6
15 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 67c6a8dfec5..5fc61b4a5c6 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -80,7 +80,7 @@ obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
obj-y += freeze_controller.o
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index feaf5ce4596..24a15f7903f 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -102,7 +102,7 @@ u8 socfpga_get_board_id(void)
u32 jtag_usercode;
int err;
-#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)
+#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)
err = smc_get_usercode(&jtag_usercode);
#else
u32 resp_len = 1;
@@ -130,7 +130,7 @@ u8 socfpga_get_board_id(void)
return board_id;
}
-#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
int board_fit_config_name_match(const char *name)
{
char board_name[10];
@@ -154,7 +154,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image,
}
#endif
-#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
+#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(struct bootm_headers *images)
{
bool use_fit = false;
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 160f6e73ca9..134eaf08e0a 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -99,7 +99,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 58b9321131a..5674194f4d1 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -12,7 +12,7 @@
#include <asm/arch/clock_manager.h>
#include <linux/delay.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void sdelay(unsigned long loops);
u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
index c78def5066e..2676d6c8283 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -9,7 +9,7 @@
_start:
ARM_VECTORS
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
.balignl 64,0xf33db33f;
.word 0x1337c0d3; /* SoCFPGA preloader validation word */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index 553ebe660de..80d5047b469 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -62,7 +62,7 @@
#define CLKMGR_INTER CLKMGR_A10_INTER
#define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
int cm_basic_init(const void *blob);
#endif
diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
index 875927cc4d9..8926c2d1d9c 100644
--- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S
+++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
@@ -13,7 +13,7 @@ ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
wait_for_atf:
ldr x4, =CPU_RELEASE_ADDR
ldr x5, [x4]
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 4c86f1e9917..2b4f26040fe 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -400,7 +400,7 @@ error:
int mbox_reset_cold(void)
{
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
psci_system_reset();
#else
int ret;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 495ba2a0d41..46f9c82bbb2 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -180,7 +180,7 @@ int arch_cpu_init(void)
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 34c21317894..c442af02888 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -58,7 +58,7 @@ static Altera_desc altera_fpga[] = {
},
};
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CFG_SYS_PL310_BASE;
static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index b898b6f8f22..b136691c685 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -213,7 +213,7 @@ int arch_early_init_r(void)
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index dd0383c7c76..a634c11a028 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -58,7 +58,7 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
u64 arg = enable;
int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c
index 4347bf6e792..e931f1043b3 100644
--- a/arch/arm/mach-socfpga/secure_vab.c
+++ b/arch/arm/mach-socfpga/secure_vab.c
@@ -120,7 +120,7 @@ int socfpga_vendor_authentication(void **p_image, size_t *p_size)
debug("mbox_relocate_data_addr = 0x%p\n", mbox_relocate_data_addr);
do {
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
/* Invoke SMC call to ATF to send the VAB certificate to SDM */
ret = smc_send_mailbox(MBOX_VAB_SRC_CERT, mbox_data_sz,
(u32 *)mbox_relocate_data_addr, 0, &resp_len,
diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c
index 80933586319..1a4e7c0e7e2 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -14,7 +14,7 @@
*/
int timer_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
@@ -56,4 +56,4 @@ __always_inline void __udelay(unsigned long usec)
while (__get_time_stamp() < tmp + 1) /* loop till event */
;
-} \ No newline at end of file
+}
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
index f13581033e6..60ba557d390 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
@@ -11,7 +11,7 @@
const struct cm_config * const cm_get_default_config(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -32,7 +32,7 @@ const struct cm_config * const cm_get_default_config(void)
const unsigned int cm_get_osc_clk_hz(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC);
@@ -50,7 +50,7 @@ const unsigned int cm_get_intosc_clk_hz(void)
const unsigned int cm_get_fpga_clk_hz(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA);
writel(clock,
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 21:19:56 +0000