diff options
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 18 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/board.c | 64 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 45 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/base_addr_ac5.h (renamed from arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h) | 0 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/reset_manager.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager.h | 10 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 28 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/spl.c | 1 |
9 files changed, 156 insertions, 19 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a413ea4d1b4..dea4ce569f7 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -2,9 +2,14 @@ if ARCH_SOCFPGA config TARGET_SOCFPGA_ARRIA5 bool + select TARGET_SOCFPGA_GEN5 config TARGET_SOCFPGA_CYCLONE5 bool + select TARGET_SOCFPGA_GEN5 + +config TARGET_SOCFPGA_GEN5 + bool choice prompt "Altera SOCFPGA board select" @@ -22,6 +27,14 @@ config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_SR1500 + bool "SR1500 (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_EBV_SOCRATES + bool "EBV SoCrates (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -38,11 +51,14 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES + default "sr1500" if TARGET_SOCFPGA_SR1500 config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -55,5 +71,7 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES + default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 316b326d417..809cd47947a 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,11 +8,12 @@ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o scan_manager.o + fpga_manager.o board.o + obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers -obj-y += wrap_pll_config.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c new file mode 100644 index 00000000000..a41d0899d77 --- /dev/null +++ b/arch/arm/mach-socfpga/board.c @@ -0,0 +1,64 @@ +/* + * Altera SoCFPGA common board code + * + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> + +#include <usb.h> +#include <usb/dwc2_udc.h> + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) {} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#ifdef CONFIG_USB_GADGET +struct dwc2_plat_otg_data socfpga_otg_data = { + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node[2], count; + fdt_addr_t addr; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", + COMPAT_ALTERA_SOCFPGA_DWC2USB, + node, 2); + if (count <= 0) /* No controller found. */ + return 0; + + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); + if (addr == FDT_ADDR_T_NONE) { + printf("UDC Controller has no 'reg' property!\n"); + return -EINVAL; + } + + /* Patch the address from OF into the controller pdata. */ + socfpga_otg_data.regs_otg = addr; + + return dwc2_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h new file mode 100644 index 00000000000..a7056d4da71 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_ +#define _SOCFPGA_A10_BASE_HARDWARE_H_ + +#define SOCFPGA_EMAC0_ADDRESS 0xff800000 +#define SOCFPGA_EMAC1_ADDRESS 0xff802000 +#define SOCFPGA_EMAC2_ADDRESS 0xff804000 +#define SOCFPGA_SDMMC_ADDRESS 0xff808000 +#define SOCFPGA_QSPIREGS_ADDRESS 0xff809000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd06000 +#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200 +#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300 +#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_MPUSCU_ADDRESS 0xffffc000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffff000 +#define SOCFPGA_I2C0_ADDRESS 0xffc02200 +#define SOCFPGA_I2C1_ADDRESS 0xffc02300 + +#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#define SOCFPGA_SDR_ADDRESS 0xffcfb000 +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 +#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 +#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 +#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 + +#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index 6534283331a..6534283331a 100644 --- a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 666a2ef8dfc..2f070f291cb 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -25,6 +25,7 @@ struct socfpga_reset_manager { u32 per2_mod_reset; u32 brg_mod_reset; u32 misc_mod_reset; + u32 padding2[12]; u32 tstscratch; }; @@ -64,12 +65,13 @@ struct socfpga_reset_manager { */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 8712f8ea117..c45edea32d3 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -129,9 +129,13 @@ struct socfpga_system_manager { #define SYSMGR_FPGAINTF_NAND (1 << 4) #define SYSMGR_FPGAINTF_SDMMC (1 << 5) -/* FIXME: This is questionable macro. */ -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 +#else +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#endif + +#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 /* EMAC Group Bit definitions */ #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index bbd31ef7b52..9b43b92f5bc 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,14 +54,23 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - /* disable the L2 cache */ - writel(0, &pl310->pl310_ctrl); + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } /* @@ -130,17 +139,6 @@ int cpu_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_DWMMC -/* - * Initializes MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(bd_t *bis) -{ - return socfpga_dwmmc_init(gd->fdt_blob); -} -#endif - struct { const char *mode; const char *name; @@ -361,6 +359,10 @@ int arch_early_init_r(void) socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); #endif +#ifdef CONFIG_NAND_DENALI + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); +#endif + return 0; } diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a82780f7..98c16a000d8 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -40,6 +40,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ |