diff options
Diffstat (limited to 'arch/arm/mach-stm32mp/cpu.c')
-rw-r--r-- | arch/arm/mach-stm32mp/cpu.c | 52 |
1 files changed, 25 insertions, 27 deletions
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index eb79f3ffd2c..325d7101009 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -93,8 +93,6 @@ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); struct lmb lmb; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) -#ifndef CONFIG_TFABOOT static void security_init(void) { /* Disable the backup domain write protection */ @@ -154,7 +152,6 @@ static void security_init(void) writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); } -#endif /* CONFIG_TFABOOT */ /* * Debug init @@ -166,7 +163,7 @@ static void dbgmcu_init(void) * done in TF-A for TRUSTED boot and * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ - if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) { + if (bsec_dbgswenable()) { setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); } @@ -174,12 +171,17 @@ static void dbgmcu_init(void) void spl_board_init(void) { + struct udevice *dev; + int ret; + dbgmcu_init(); + + /* force probe of BSEC driver to shadow the upper OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret) + log_warning("BSEC probe failed: %d\n", ret); } -#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ -#if !defined(CONFIG_TFABOOT) && \ - (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) /* get bootmode from ROM code boot context: saved in TAMP register */ static void update_bootmode(void) { @@ -205,7 +207,6 @@ static void update_bootmode(void) TAMP_BOOT_MODE_MASK, boot_mode << TAMP_BOOT_MODE_SHIFT); } -#endif u32 get_bootmode(void) { @@ -283,29 +284,26 @@ int arch_cpu_init(void) /* early armv7 timer init: needed for polling */ timer_init(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) -#ifndef CONFIG_TFABOOT - security_init(); - update_bootmode(); -#endif - /* Reset Coprocessor state unless it wakes up from Standby power mode */ - if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { - writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); - writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + security_init(); + update_bootmode(); + } +/* reset copro state in SPL, when used, or in U-Boot */ + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Reset Coprocessor state unless it wakes up from Standby power mode */ + if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { + writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); + writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); + } } -#endif boot_mode = get_bootmode(); if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; -#if defined(CONFIG_DEBUG_UART) && \ - !defined(CONFIG_TFABOOT) && \ - (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) - else + else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) debug_uart_init(); -#endif return 0; } @@ -459,7 +457,7 @@ void get_soc_name(char name[SOC_NAME_SIZE]) soc_type[type], soc_pkg[pkg], soc_rev[rev]); } -#if defined(CONFIG_DISPLAY_CPUINFO) +/* used when CONFIG_DISPLAY_CPUINFO is activated */ int print_cpuinfo(void) { char name[SOC_NAME_SIZE]; @@ -469,7 +467,6 @@ int print_cpuinfo(void) return 0; } -#endif /* CONFIG_DISPLAY_CPUINFO */ static void setup_boot_mode(void) { @@ -599,13 +596,15 @@ static void setup_boot_mode(void) */ __weak int setup_mac_address(void) { -#if defined(CONFIG_NET) int ret; int i; u32 otp[2]; uchar enetaddr[6]; struct udevice *dev; + if (!IS_ENABLED(CONFIG_NET)) + return 0; + /* MAC already in environment */ if (eth_env_get_enetaddr("ethaddr", enetaddr)) return 0; @@ -632,7 +631,6 @@ __weak int setup_mac_address(void) ret = eth_env_set_enetaddr("ethaddr", enetaddr); if (ret) log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret); -#endif return 0; } |